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1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <sound/core.h>
38 #include <sound/jack.h>
39 #include <sound/asoundef.h>
40 #include <sound/tlv.h>
41 #include <sound/hdaudio.h>
42 #include <sound/hda_i915.h>
43 #include <sound/hda_chmap.h>
44 #include <sound/hda_codec.h>
45 #include "hda_local.h"
46 #include "hda_jack.h"
47
48 static bool static_hdmi_pcm;
49 module_param(static_hdmi_pcm, bool, 0644);
50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51
52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
57 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
58 ((codec)->core.vendor_id == 0x80862800))
59 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
60 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
61 || is_skylake(codec) || is_broxton(codec) \
62 || is_kabylake(codec)) || is_geminilake(codec) \
63 || is_cannonlake(codec)
64 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
65 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
66 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
67
68 struct hdmi_spec_per_cvt {
69 hda_nid_t cvt_nid;
70 int assigned;
71 unsigned int channels_min;
72 unsigned int channels_max;
73 u32 rates;
74 u64 formats;
75 unsigned int maxbps;
76 };
77
78 /* max. connections to a widget */
79 #define HDA_MAX_CONNECTIONS 32
80
81 struct hdmi_spec_per_pin {
82 hda_nid_t pin_nid;
83 int dev_id;
84 /* pin idx, different device entries on the same pin use the same idx */
85 int pin_nid_idx;
86 int num_mux_nids;
87 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
88 int mux_idx;
89 hda_nid_t cvt_nid;
90
91 struct hda_codec *codec;
92 struct hdmi_eld sink_eld;
93 struct mutex lock;
94 struct delayed_work work;
95 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
96 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
97 int repoll_count;
98 bool setup; /* the stream has been set up by prepare callback */
99 int channels; /* current number of channels */
100 bool non_pcm;
101 bool chmap_set; /* channel-map override by ALSA API? */
102 unsigned char chmap[8]; /* ALSA API channel-map */
103 #ifdef CONFIG_SND_PROC_FS
104 struct snd_info_entry *proc_entry;
105 #endif
106 };
107
108 /* operations used by generic code that can be overridden by patches */
109 struct hdmi_ops {
110 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
111 unsigned char *buf, int *eld_size);
112
113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int ca, int active_channels, int conn_type);
115
116 /* enable/disable HBR (HD passthrough) */
117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
118
119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
120 hda_nid_t pin_nid, u32 stream_tag, int format);
121
122 void (*pin_cvt_fixup)(struct hda_codec *codec,
123 struct hdmi_spec_per_pin *per_pin,
124 hda_nid_t cvt_nid);
125 };
126
127 struct hdmi_pcm {
128 struct hda_pcm *pcm;
129 struct snd_jack *jack;
130 struct snd_kcontrol *eld_ctl;
131 };
132
133 struct hdmi_spec {
134 int num_cvts;
135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
136 hda_nid_t cvt_nids[4]; /* only for haswell fix */
137
138 /*
139 * num_pins is the number of virtual pins
140 * for example, there are 3 pins, and each pin
141 * has 4 device entries, then the num_pins is 12
142 */
143 int num_pins;
144 /*
145 * num_nids is the number of real pins
146 * In the above example, num_nids is 3
147 */
148 int num_nids;
149 /*
150 * dev_num is the number of device entries
151 * on each pin.
152 * In the above example, dev_num is 4
153 */
154 int dev_num;
155 struct snd_array pins; /* struct hdmi_spec_per_pin */
156 struct hdmi_pcm pcm_rec[16];
157 struct mutex pcm_lock;
158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
160 int pcm_used; /* counter of pcm_rec[] */
161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
164 */
165 unsigned long pcm_in_use;
166
167 struct hdmi_eld temp_eld;
168 struct hdmi_ops ops;
169
170 bool dyn_pin_out;
171 bool dyn_pcm_assign;
172 /*
173 * Non-generic VIA/NVIDIA specific
174 */
175 struct hda_multi_out multiout;
176 struct hda_pcm_stream pcm_playback;
177
178 /* i915/powerwell (Haswell+/Valleyview+) specific */
179 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
180 struct drm_audio_component_audio_ops drm_audio_ops;
181
182 struct hdac_chmap chmap;
183 hda_nid_t vendor_nid;
184 };
185
186 #ifdef CONFIG_SND_HDA_COMPONENT
187 static inline bool codec_has_acomp(struct hda_codec *codec)
188 {
189 struct hdmi_spec *spec = codec->spec;
190 return spec->use_acomp_notifier;
191 }
192 #else
193 #define codec_has_acomp(codec) false
194 #endif
195
196 struct hdmi_audio_infoframe {
197 u8 type; /* 0x84 */
198 u8 ver; /* 0x01 */
199 u8 len; /* 0x0a */
200
201 u8 checksum;
202
203 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
204 u8 SS01_SF24;
205 u8 CXT04;
206 u8 CA;
207 u8 LFEPBL01_LSV36_DM_INH7;
208 };
209
210 struct dp_audio_infoframe {
211 u8 type; /* 0x84 */
212 u8 len; /* 0x1b */
213 u8 ver; /* 0x11 << 2 */
214
215 u8 CC02_CT47; /* match with HDMI infoframe from this on */
216 u8 SS01_SF24;
217 u8 CXT04;
218 u8 CA;
219 u8 LFEPBL01_LSV36_DM_INH7;
220 };
221
222 union audio_infoframe {
223 struct hdmi_audio_infoframe hdmi;
224 struct dp_audio_infoframe dp;
225 u8 bytes[0];
226 };
227
228 /*
229 * HDMI routines
230 */
231
232 #define get_pin(spec, idx) \
233 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
234 #define get_cvt(spec, idx) \
235 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
236 /* obtain hdmi_pcm object assigned to idx */
237 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
238 /* obtain hda_pcm object assigned to idx */
239 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
240
241 static int pin_id_to_pin_index(struct hda_codec *codec,
242 hda_nid_t pin_nid, int dev_id)
243 {
244 struct hdmi_spec *spec = codec->spec;
245 int pin_idx;
246 struct hdmi_spec_per_pin *per_pin;
247
248 /*
249 * (dev_id == -1) means it is NON-MST pin
250 * return the first virtual pin on this port
251 */
252 if (dev_id == -1)
253 dev_id = 0;
254
255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
256 per_pin = get_pin(spec, pin_idx);
257 if ((per_pin->pin_nid == pin_nid) &&
258 (per_pin->dev_id == dev_id))
259 return pin_idx;
260 }
261
262 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
263 return -EINVAL;
264 }
265
266 static int hinfo_to_pcm_index(struct hda_codec *codec,
267 struct hda_pcm_stream *hinfo)
268 {
269 struct hdmi_spec *spec = codec->spec;
270 int pcm_idx;
271
272 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
273 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
274 return pcm_idx;
275
276 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
277 return -EINVAL;
278 }
279
280 static int hinfo_to_pin_index(struct hda_codec *codec,
281 struct hda_pcm_stream *hinfo)
282 {
283 struct hdmi_spec *spec = codec->spec;
284 struct hdmi_spec_per_pin *per_pin;
285 int pin_idx;
286
287 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
288 per_pin = get_pin(spec, pin_idx);
289 if (per_pin->pcm &&
290 per_pin->pcm->pcm->stream == hinfo)
291 return pin_idx;
292 }
293
294 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
295 return -EINVAL;
296 }
297
298 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
299 int pcm_idx)
300 {
301 int i;
302 struct hdmi_spec_per_pin *per_pin;
303
304 for (i = 0; i < spec->num_pins; i++) {
305 per_pin = get_pin(spec, i);
306 if (per_pin->pcm_idx == pcm_idx)
307 return per_pin;
308 }
309 return NULL;
310 }
311
312 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
313 {
314 struct hdmi_spec *spec = codec->spec;
315 int cvt_idx;
316
317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
319 return cvt_idx;
320
321 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
322 return -EINVAL;
323 }
324
325 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_info *uinfo)
327 {
328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
329 struct hdmi_spec *spec = codec->spec;
330 struct hdmi_spec_per_pin *per_pin;
331 struct hdmi_eld *eld;
332 int pcm_idx;
333
334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
335
336 pcm_idx = kcontrol->private_value;
337 mutex_lock(&spec->pcm_lock);
338 per_pin = pcm_idx_to_pin(spec, pcm_idx);
339 if (!per_pin) {
340 /* no pin is bound to the pcm */
341 uinfo->count = 0;
342 goto unlock;
343 }
344 eld = &per_pin->sink_eld;
345 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
346
347 unlock:
348 mutex_unlock(&spec->pcm_lock);
349 return 0;
350 }
351
352 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
354 {
355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
356 struct hdmi_spec *spec = codec->spec;
357 struct hdmi_spec_per_pin *per_pin;
358 struct hdmi_eld *eld;
359 int pcm_idx;
360 int err = 0;
361
362 pcm_idx = kcontrol->private_value;
363 mutex_lock(&spec->pcm_lock);
364 per_pin = pcm_idx_to_pin(spec, pcm_idx);
365 if (!per_pin) {
366 /* no pin is bound to the pcm */
367 memset(ucontrol->value.bytes.data, 0,
368 ARRAY_SIZE(ucontrol->value.bytes.data));
369 goto unlock;
370 }
371
372 eld = &per_pin->sink_eld;
373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
374 eld->eld_size > ELD_MAX_SIZE) {
375 snd_BUG();
376 err = -EINVAL;
377 goto unlock;
378 }
379
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
382 if (eld->eld_valid)
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
384 eld->eld_size);
385
386 unlock:
387 mutex_unlock(&spec->pcm_lock);
388 return err;
389 }
390
391 static const struct snd_kcontrol_new eld_bytes_ctl = {
392 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
393 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
394 .name = "ELD",
395 .info = hdmi_eld_ctl_info,
396 .get = hdmi_eld_ctl_get,
397 };
398
399 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
400 int device)
401 {
402 struct snd_kcontrol *kctl;
403 struct hdmi_spec *spec = codec->spec;
404 int err;
405
406 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
407 if (!kctl)
408 return -ENOMEM;
409 kctl->private_value = pcm_idx;
410 kctl->id.device = device;
411
412 /* no pin nid is associated with the kctl now
413 * tbd: associate pin nid to eld ctl later
414 */
415 err = snd_hda_ctl_add(codec, 0, kctl);
416 if (err < 0)
417 return err;
418
419 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
420 return 0;
421 }
422
423 #ifdef BE_PARANOID
424 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
425 int *packet_index, int *byte_index)
426 {
427 int val;
428
429 val = snd_hda_codec_read(codec, pin_nid, 0,
430 AC_VERB_GET_HDMI_DIP_INDEX, 0);
431
432 *packet_index = val >> 5;
433 *byte_index = val & 0x1f;
434 }
435 #endif
436
437 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
438 int packet_index, int byte_index)
439 {
440 int val;
441
442 val = (packet_index << 5) | (byte_index & 0x1f);
443
444 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
445 }
446
447 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
448 unsigned char val)
449 {
450 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
451 }
452
453 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
454 {
455 struct hdmi_spec *spec = codec->spec;
456 int pin_out;
457
458 /* Unmute */
459 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
460 snd_hda_codec_write(codec, pin_nid, 0,
461 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
462
463 if (spec->dyn_pin_out)
464 /* Disable pin out until stream is active */
465 pin_out = 0;
466 else
467 /* Enable pin out: some machines with GM965 gets broken output
468 * when the pin is disabled or changed while using with HDMI
469 */
470 pin_out = PIN_OUT;
471
472 snd_hda_codec_write(codec, pin_nid, 0,
473 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
474 }
475
476 /*
477 * ELD proc files
478 */
479
480 #ifdef CONFIG_SND_PROC_FS
481 static void print_eld_info(struct snd_info_entry *entry,
482 struct snd_info_buffer *buffer)
483 {
484 struct hdmi_spec_per_pin *per_pin = entry->private_data;
485
486 mutex_lock(&per_pin->lock);
487 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
488 mutex_unlock(&per_pin->lock);
489 }
490
491 static void write_eld_info(struct snd_info_entry *entry,
492 struct snd_info_buffer *buffer)
493 {
494 struct hdmi_spec_per_pin *per_pin = entry->private_data;
495
496 mutex_lock(&per_pin->lock);
497 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
498 mutex_unlock(&per_pin->lock);
499 }
500
501 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
502 {
503 char name[32];
504 struct hda_codec *codec = per_pin->codec;
505 struct snd_info_entry *entry;
506 int err;
507
508 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
509 err = snd_card_proc_new(codec->card, name, &entry);
510 if (err < 0)
511 return err;
512
513 snd_info_set_text_ops(entry, per_pin, print_eld_info);
514 entry->c.text.write = write_eld_info;
515 entry->mode |= 0200;
516 per_pin->proc_entry = entry;
517
518 return 0;
519 }
520
521 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
522 {
523 if (!per_pin->codec->bus->shutdown) {
524 snd_info_free_entry(per_pin->proc_entry);
525 per_pin->proc_entry = NULL;
526 }
527 }
528 #else
529 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
530 int index)
531 {
532 return 0;
533 }
534 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
535 {
536 }
537 #endif
538
539 /*
540 * Audio InfoFrame routines
541 */
542
543 /*
544 * Enable Audio InfoFrame Transmission
545 */
546 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
547 hda_nid_t pin_nid)
548 {
549 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
550 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
551 AC_DIPXMIT_BEST);
552 }
553
554 /*
555 * Disable Audio InfoFrame Transmission
556 */
557 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
558 hda_nid_t pin_nid)
559 {
560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
562 AC_DIPXMIT_DISABLE);
563 }
564
565 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
566 {
567 #ifdef CONFIG_SND_DEBUG_VERBOSE
568 int i;
569 int size;
570
571 size = snd_hdmi_get_eld_size(codec, pin_nid);
572 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
573
574 for (i = 0; i < 8; i++) {
575 size = snd_hda_codec_read(codec, pin_nid, 0,
576 AC_VERB_GET_HDMI_DIP_SIZE, i);
577 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
578 }
579 #endif
580 }
581
582 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
583 {
584 #ifdef BE_PARANOID
585 int i, j;
586 int size;
587 int pi, bi;
588 for (i = 0; i < 8; i++) {
589 size = snd_hda_codec_read(codec, pin_nid, 0,
590 AC_VERB_GET_HDMI_DIP_SIZE, i);
591 if (size == 0)
592 continue;
593
594 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
595 for (j = 1; j < 1000; j++) {
596 hdmi_write_dip_byte(codec, pin_nid, 0x0);
597 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
598 if (pi != i)
599 codec_dbg(codec, "dip index %d: %d != %d\n",
600 bi, pi, i);
601 if (bi == 0) /* byte index wrapped around */
602 break;
603 }
604 codec_dbg(codec,
605 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
606 i, size, j);
607 }
608 #endif
609 }
610
611 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
612 {
613 u8 *bytes = (u8 *)hdmi_ai;
614 u8 sum = 0;
615 int i;
616
617 hdmi_ai->checksum = 0;
618
619 for (i = 0; i < sizeof(*hdmi_ai); i++)
620 sum += bytes[i];
621
622 hdmi_ai->checksum = -sum;
623 }
624
625 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
626 hda_nid_t pin_nid,
627 u8 *dip, int size)
628 {
629 int i;
630
631 hdmi_debug_dip_size(codec, pin_nid);
632 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
633
634 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
635 for (i = 0; i < size; i++)
636 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
637 }
638
639 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
640 u8 *dip, int size)
641 {
642 u8 val;
643 int i;
644
645 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
646 != AC_DIPXMIT_BEST)
647 return false;
648
649 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
650 for (i = 0; i < size; i++) {
651 val = snd_hda_codec_read(codec, pin_nid, 0,
652 AC_VERB_GET_HDMI_DIP_DATA, 0);
653 if (val != dip[i])
654 return false;
655 }
656
657 return true;
658 }
659
660 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
661 hda_nid_t pin_nid,
662 int ca, int active_channels,
663 int conn_type)
664 {
665 union audio_infoframe ai;
666
667 memset(&ai, 0, sizeof(ai));
668 if (conn_type == 0) { /* HDMI */
669 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
670
671 hdmi_ai->type = 0x84;
672 hdmi_ai->ver = 0x01;
673 hdmi_ai->len = 0x0a;
674 hdmi_ai->CC02_CT47 = active_channels - 1;
675 hdmi_ai->CA = ca;
676 hdmi_checksum_audio_infoframe(hdmi_ai);
677 } else if (conn_type == 1) { /* DisplayPort */
678 struct dp_audio_infoframe *dp_ai = &ai.dp;
679
680 dp_ai->type = 0x84;
681 dp_ai->len = 0x1b;
682 dp_ai->ver = 0x11 << 2;
683 dp_ai->CC02_CT47 = active_channels - 1;
684 dp_ai->CA = ca;
685 } else {
686 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
687 pin_nid);
688 return;
689 }
690
691 /*
692 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
693 * sizeof(*dp_ai) to avoid partial match/update problems when
694 * the user switches between HDMI/DP monitors.
695 */
696 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
697 sizeof(ai))) {
698 codec_dbg(codec,
699 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
700 pin_nid,
701 active_channels, ca);
702 hdmi_stop_infoframe_trans(codec, pin_nid);
703 hdmi_fill_audio_infoframe(codec, pin_nid,
704 ai.bytes, sizeof(ai));
705 hdmi_start_infoframe_trans(codec, pin_nid);
706 }
707 }
708
709 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
710 struct hdmi_spec_per_pin *per_pin,
711 bool non_pcm)
712 {
713 struct hdmi_spec *spec = codec->spec;
714 struct hdac_chmap *chmap = &spec->chmap;
715 hda_nid_t pin_nid = per_pin->pin_nid;
716 int channels = per_pin->channels;
717 int active_channels;
718 struct hdmi_eld *eld;
719 int ca;
720
721 if (!channels)
722 return;
723
724 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
725 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
726 snd_hda_codec_write(codec, pin_nid, 0,
727 AC_VERB_SET_AMP_GAIN_MUTE,
728 AMP_OUT_UNMUTE);
729
730 eld = &per_pin->sink_eld;
731
732 ca = snd_hdac_channel_allocation(&codec->core,
733 eld->info.spk_alloc, channels,
734 per_pin->chmap_set, non_pcm, per_pin->chmap);
735
736 active_channels = snd_hdac_get_active_channels(ca);
737
738 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
739 active_channels);
740
741 /*
742 * always configure channel mapping, it may have been changed by the
743 * user in the meantime
744 */
745 snd_hdac_setup_channel_mapping(&spec->chmap,
746 pin_nid, non_pcm, ca, channels,
747 per_pin->chmap, per_pin->chmap_set);
748
749 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
750 eld->info.conn_type);
751
752 per_pin->non_pcm = non_pcm;
753 }
754
755 /*
756 * Unsolicited events
757 */
758
759 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
760
761 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
762 int dev_id)
763 {
764 struct hdmi_spec *spec = codec->spec;
765 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
766
767 if (pin_idx < 0)
768 return;
769 mutex_lock(&spec->pcm_lock);
770 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
771 snd_hda_jack_report_sync(codec);
772 mutex_unlock(&spec->pcm_lock);
773 }
774
775 static void jack_callback(struct hda_codec *codec,
776 struct hda_jack_callback *jack)
777 {
778 /* hda_jack don't support DP MST */
779 check_presence_and_report(codec, jack->nid, 0);
780 }
781
782 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
783 {
784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
785 struct hda_jack_tbl *jack;
786 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
787
788 /*
789 * assume DP MST uses dyn_pcm_assign and acomp and
790 * never comes here
791 * if DP MST supports unsol event, below code need
792 * consider dev_entry
793 */
794 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
795 if (!jack)
796 return;
797 jack->jack_dirty = 1;
798
799 codec_dbg(codec,
800 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
801 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
802 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
803
804 /* hda_jack don't support DP MST */
805 check_presence_and_report(codec, jack->nid, 0);
806 }
807
808 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
809 {
810 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
811 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
812 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
813 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
814
815 codec_info(codec,
816 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
817 codec->addr,
818 tag,
819 subtag,
820 cp_state,
821 cp_ready);
822
823 /* TODO */
824 if (cp_state)
825 ;
826 if (cp_ready)
827 ;
828 }
829
830
831 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
832 {
833 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
834 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
835
836 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
837 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
838 return;
839 }
840
841 if (subtag == 0)
842 hdmi_intrinsic_event(codec, res);
843 else
844 hdmi_non_intrinsic_event(codec, res);
845 }
846
847 static void haswell_verify_D0(struct hda_codec *codec,
848 hda_nid_t cvt_nid, hda_nid_t nid)
849 {
850 int pwr;
851
852 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
853 * thus pins could only choose converter 0 for use. Make sure the
854 * converters are in correct power state */
855 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
856 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
857
858 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
859 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
860 AC_PWRST_D0);
861 msleep(40);
862 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
863 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
864 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
865 }
866 }
867
868 /*
869 * Callbacks
870 */
871
872 /* HBR should be Non-PCM, 8 channels */
873 #define is_hbr_format(format) \
874 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
875
876 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
877 bool hbr)
878 {
879 int pinctl, new_pinctl;
880
881 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
882 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
883 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
884
885 if (pinctl < 0)
886 return hbr ? -EINVAL : 0;
887
888 new_pinctl = pinctl & ~AC_PINCTL_EPT;
889 if (hbr)
890 new_pinctl |= AC_PINCTL_EPT_HBR;
891 else
892 new_pinctl |= AC_PINCTL_EPT_NATIVE;
893
894 codec_dbg(codec,
895 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
896 pin_nid,
897 pinctl == new_pinctl ? "" : "new-",
898 new_pinctl);
899
900 if (pinctl != new_pinctl)
901 snd_hda_codec_write(codec, pin_nid, 0,
902 AC_VERB_SET_PIN_WIDGET_CONTROL,
903 new_pinctl);
904 } else if (hbr)
905 return -EINVAL;
906
907 return 0;
908 }
909
910 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
911 hda_nid_t pin_nid, u32 stream_tag, int format)
912 {
913 struct hdmi_spec *spec = codec->spec;
914 unsigned int param;
915 int err;
916
917 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
918
919 if (err) {
920 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
921 return err;
922 }
923
924 if (is_haswell_plus(codec)) {
925
926 /*
927 * on recent platforms IEC Coding Type is required for HBR
928 * support, read current Digital Converter settings and set
929 * ICT bitfield if needed.
930 */
931 param = snd_hda_codec_read(codec, cvt_nid, 0,
932 AC_VERB_GET_DIGI_CONVERT_1, 0);
933
934 param = (param >> 16) & ~(AC_DIG3_ICT);
935
936 /* on recent platforms ICT mode is required for HBR support */
937 if (is_hbr_format(format))
938 param |= 0x1;
939
940 snd_hda_codec_write(codec, cvt_nid, 0,
941 AC_VERB_SET_DIGI_CONVERT_3, param);
942 }
943
944 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
945 return 0;
946 }
947
948 /* Try to find an available converter
949 * If pin_idx is less then zero, just try to find an available converter.
950 * Otherwise, try to find an available converter and get the cvt mux index
951 * of the pin.
952 */
953 static int hdmi_choose_cvt(struct hda_codec *codec,
954 int pin_idx, int *cvt_id)
955 {
956 struct hdmi_spec *spec = codec->spec;
957 struct hdmi_spec_per_pin *per_pin;
958 struct hdmi_spec_per_cvt *per_cvt = NULL;
959 int cvt_idx, mux_idx = 0;
960
961 /* pin_idx < 0 means no pin will be bound to the converter */
962 if (pin_idx < 0)
963 per_pin = NULL;
964 else
965 per_pin = get_pin(spec, pin_idx);
966
967 /* Dynamically assign converter to stream */
968 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
969 per_cvt = get_cvt(spec, cvt_idx);
970
971 /* Must not already be assigned */
972 if (per_cvt->assigned)
973 continue;
974 if (per_pin == NULL)
975 break;
976 /* Must be in pin's mux's list of converters */
977 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
978 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
979 break;
980 /* Not in mux list */
981 if (mux_idx == per_pin->num_mux_nids)
982 continue;
983 break;
984 }
985
986 /* No free converters */
987 if (cvt_idx == spec->num_cvts)
988 return -EBUSY;
989
990 if (per_pin != NULL)
991 per_pin->mux_idx = mux_idx;
992
993 if (cvt_id)
994 *cvt_id = cvt_idx;
995
996 return 0;
997 }
998
999 /* Assure the pin select the right convetor */
1000 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1001 struct hdmi_spec_per_pin *per_pin)
1002 {
1003 hda_nid_t pin_nid = per_pin->pin_nid;
1004 int mux_idx, curr;
1005
1006 mux_idx = per_pin->mux_idx;
1007 curr = snd_hda_codec_read(codec, pin_nid, 0,
1008 AC_VERB_GET_CONNECT_SEL, 0);
1009 if (curr != mux_idx)
1010 snd_hda_codec_write_cache(codec, pin_nid, 0,
1011 AC_VERB_SET_CONNECT_SEL,
1012 mux_idx);
1013 }
1014
1015 /* get the mux index for the converter of the pins
1016 * converter's mux index is the same for all pins on Intel platform
1017 */
1018 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1019 hda_nid_t cvt_nid)
1020 {
1021 int i;
1022
1023 for (i = 0; i < spec->num_cvts; i++)
1024 if (spec->cvt_nids[i] == cvt_nid)
1025 return i;
1026 return -EINVAL;
1027 }
1028
1029 /* Intel HDMI workaround to fix audio routing issue:
1030 * For some Intel display codecs, pins share the same connection list.
1031 * So a conveter can be selected by multiple pins and playback on any of these
1032 * pins will generate sound on the external display, because audio flows from
1033 * the same converter to the display pipeline. Also muting one pin may make
1034 * other pins have no sound output.
1035 * So this function assures that an assigned converter for a pin is not selected
1036 * by any other pins.
1037 */
1038 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1039 hda_nid_t pin_nid,
1040 int dev_id, int mux_idx)
1041 {
1042 struct hdmi_spec *spec = codec->spec;
1043 hda_nid_t nid;
1044 int cvt_idx, curr;
1045 struct hdmi_spec_per_cvt *per_cvt;
1046 struct hdmi_spec_per_pin *per_pin;
1047 int pin_idx;
1048
1049 /* configure the pins connections */
1050 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1051 int dev_id_saved;
1052 int dev_num;
1053
1054 per_pin = get_pin(spec, pin_idx);
1055 /*
1056 * pin not connected to monitor
1057 * no need to operate on it
1058 */
1059 if (!per_pin->pcm)
1060 continue;
1061
1062 if ((per_pin->pin_nid == pin_nid) &&
1063 (per_pin->dev_id == dev_id))
1064 continue;
1065
1066 /*
1067 * if per_pin->dev_id >= dev_num,
1068 * snd_hda_get_dev_select() will fail,
1069 * and the following operation is unpredictable.
1070 * So skip this situation.
1071 */
1072 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1073 if (per_pin->dev_id >= dev_num)
1074 continue;
1075
1076 nid = per_pin->pin_nid;
1077
1078 /*
1079 * Calling this function should not impact
1080 * on the device entry selection
1081 * So let's save the dev id for each pin,
1082 * and restore it when return
1083 */
1084 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1085 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1086 curr = snd_hda_codec_read(codec, nid, 0,
1087 AC_VERB_GET_CONNECT_SEL, 0);
1088 if (curr != mux_idx) {
1089 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1090 continue;
1091 }
1092
1093
1094 /* choose an unassigned converter. The conveters in the
1095 * connection list are in the same order as in the codec.
1096 */
1097 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1098 per_cvt = get_cvt(spec, cvt_idx);
1099 if (!per_cvt->assigned) {
1100 codec_dbg(codec,
1101 "choose cvt %d for pin nid %d\n",
1102 cvt_idx, nid);
1103 snd_hda_codec_write_cache(codec, nid, 0,
1104 AC_VERB_SET_CONNECT_SEL,
1105 cvt_idx);
1106 break;
1107 }
1108 }
1109 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1110 }
1111 }
1112
1113 /* A wrapper of intel_not_share_asigned_cvt() */
1114 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1115 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1116 {
1117 int mux_idx;
1118 struct hdmi_spec *spec = codec->spec;
1119
1120 /* On Intel platform, the mapping of converter nid to
1121 * mux index of the pins are always the same.
1122 * The pin nid may be 0, this means all pins will not
1123 * share the converter.
1124 */
1125 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1126 if (mux_idx >= 0)
1127 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1128 }
1129
1130 /* skeleton caller of pin_cvt_fixup ops */
1131 static void pin_cvt_fixup(struct hda_codec *codec,
1132 struct hdmi_spec_per_pin *per_pin,
1133 hda_nid_t cvt_nid)
1134 {
1135 struct hdmi_spec *spec = codec->spec;
1136
1137 if (spec->ops.pin_cvt_fixup)
1138 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1139 }
1140
1141 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1142 * in dyn_pcm_assign mode.
1143 */
1144 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1145 struct hda_codec *codec,
1146 struct snd_pcm_substream *substream)
1147 {
1148 struct hdmi_spec *spec = codec->spec;
1149 struct snd_pcm_runtime *runtime = substream->runtime;
1150 int cvt_idx, pcm_idx;
1151 struct hdmi_spec_per_cvt *per_cvt = NULL;
1152 int err;
1153
1154 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1155 if (pcm_idx < 0)
1156 return -EINVAL;
1157
1158 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1159 if (err)
1160 return err;
1161
1162 per_cvt = get_cvt(spec, cvt_idx);
1163 per_cvt->assigned = 1;
1164 hinfo->nid = per_cvt->cvt_nid;
1165
1166 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1167
1168 set_bit(pcm_idx, &spec->pcm_in_use);
1169 /* todo: setup spdif ctls assign */
1170
1171 /* Initially set the converter's capabilities */
1172 hinfo->channels_min = per_cvt->channels_min;
1173 hinfo->channels_max = per_cvt->channels_max;
1174 hinfo->rates = per_cvt->rates;
1175 hinfo->formats = per_cvt->formats;
1176 hinfo->maxbps = per_cvt->maxbps;
1177
1178 /* Store the updated parameters */
1179 runtime->hw.channels_min = hinfo->channels_min;
1180 runtime->hw.channels_max = hinfo->channels_max;
1181 runtime->hw.formats = hinfo->formats;
1182 runtime->hw.rates = hinfo->rates;
1183
1184 snd_pcm_hw_constraint_step(substream->runtime, 0,
1185 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1186 return 0;
1187 }
1188
1189 /*
1190 * HDA PCM callbacks
1191 */
1192 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1193 struct hda_codec *codec,
1194 struct snd_pcm_substream *substream)
1195 {
1196 struct hdmi_spec *spec = codec->spec;
1197 struct snd_pcm_runtime *runtime = substream->runtime;
1198 int pin_idx, cvt_idx, pcm_idx;
1199 struct hdmi_spec_per_pin *per_pin;
1200 struct hdmi_eld *eld;
1201 struct hdmi_spec_per_cvt *per_cvt = NULL;
1202 int err;
1203
1204 /* Validate hinfo */
1205 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1206 if (pcm_idx < 0)
1207 return -EINVAL;
1208
1209 mutex_lock(&spec->pcm_lock);
1210 pin_idx = hinfo_to_pin_index(codec, hinfo);
1211 if (!spec->dyn_pcm_assign) {
1212 if (snd_BUG_ON(pin_idx < 0)) {
1213 err = -EINVAL;
1214 goto unlock;
1215 }
1216 } else {
1217 /* no pin is assigned to the PCM
1218 * PA need pcm open successfully when probe
1219 */
1220 if (pin_idx < 0) {
1221 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1222 goto unlock;
1223 }
1224 }
1225
1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1227 if (err < 0)
1228 goto unlock;
1229
1230 per_cvt = get_cvt(spec, cvt_idx);
1231 /* Claim converter */
1232 per_cvt->assigned = 1;
1233
1234 set_bit(pcm_idx, &spec->pcm_in_use);
1235 per_pin = get_pin(spec, pin_idx);
1236 per_pin->cvt_nid = per_cvt->cvt_nid;
1237 hinfo->nid = per_cvt->cvt_nid;
1238
1239 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1240 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1241 AC_VERB_SET_CONNECT_SEL,
1242 per_pin->mux_idx);
1243
1244 /* configure unused pins to choose other converters */
1245 pin_cvt_fixup(codec, per_pin, 0);
1246
1247 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1248
1249 /* Initially set the converter's capabilities */
1250 hinfo->channels_min = per_cvt->channels_min;
1251 hinfo->channels_max = per_cvt->channels_max;
1252 hinfo->rates = per_cvt->rates;
1253 hinfo->formats = per_cvt->formats;
1254 hinfo->maxbps = per_cvt->maxbps;
1255
1256 eld = &per_pin->sink_eld;
1257 /* Restrict capabilities by ELD if this isn't disabled */
1258 if (!static_hdmi_pcm && eld->eld_valid) {
1259 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1260 if (hinfo->channels_min > hinfo->channels_max ||
1261 !hinfo->rates || !hinfo->formats) {
1262 per_cvt->assigned = 0;
1263 hinfo->nid = 0;
1264 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1265 err = -ENODEV;
1266 goto unlock;
1267 }
1268 }
1269
1270 /* Store the updated parameters */
1271 runtime->hw.channels_min = hinfo->channels_min;
1272 runtime->hw.channels_max = hinfo->channels_max;
1273 runtime->hw.formats = hinfo->formats;
1274 runtime->hw.rates = hinfo->rates;
1275
1276 snd_pcm_hw_constraint_step(substream->runtime, 0,
1277 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1278 unlock:
1279 mutex_unlock(&spec->pcm_lock);
1280 return err;
1281 }
1282
1283 /*
1284 * HDA/HDMI auto parsing
1285 */
1286 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1287 {
1288 struct hdmi_spec *spec = codec->spec;
1289 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1290 hda_nid_t pin_nid = per_pin->pin_nid;
1291
1292 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1293 codec_warn(codec,
1294 "HDMI: pin %d wcaps %#x does not support connection list\n",
1295 pin_nid, get_wcaps(codec, pin_nid));
1296 return -EINVAL;
1297 }
1298
1299 /* all the device entries on the same pin have the same conn list */
1300 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1301 per_pin->mux_nids,
1302 HDA_MAX_CONNECTIONS);
1303
1304 return 0;
1305 }
1306
1307 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1308 struct hdmi_spec_per_pin *per_pin)
1309 {
1310 int i;
1311
1312 /* try the prefer PCM */
1313 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1314 return per_pin->pin_nid_idx;
1315
1316 /* have a second try; check the "reserved area" over num_pins */
1317 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1318 if (!test_bit(i, &spec->pcm_bitmap))
1319 return i;
1320 }
1321
1322 /* the last try; check the empty slots in pins */
1323 for (i = 0; i < spec->num_nids; i++) {
1324 if (!test_bit(i, &spec->pcm_bitmap))
1325 return i;
1326 }
1327 return -EBUSY;
1328 }
1329
1330 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1331 struct hdmi_spec_per_pin *per_pin)
1332 {
1333 int idx;
1334
1335 /* pcm already be attached to the pin */
1336 if (per_pin->pcm)
1337 return;
1338 idx = hdmi_find_pcm_slot(spec, per_pin);
1339 if (idx == -EBUSY)
1340 return;
1341 per_pin->pcm_idx = idx;
1342 per_pin->pcm = get_hdmi_pcm(spec, idx);
1343 set_bit(idx, &spec->pcm_bitmap);
1344 }
1345
1346 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1347 struct hdmi_spec_per_pin *per_pin)
1348 {
1349 int idx;
1350
1351 /* pcm already be detached from the pin */
1352 if (!per_pin->pcm)
1353 return;
1354 idx = per_pin->pcm_idx;
1355 per_pin->pcm_idx = -1;
1356 per_pin->pcm = NULL;
1357 if (idx >= 0 && idx < spec->pcm_used)
1358 clear_bit(idx, &spec->pcm_bitmap);
1359 }
1360
1361 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1362 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1363 {
1364 int mux_idx;
1365
1366 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1367 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1368 break;
1369 return mux_idx;
1370 }
1371
1372 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1373
1374 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1375 struct hdmi_spec_per_pin *per_pin)
1376 {
1377 struct hda_codec *codec = per_pin->codec;
1378 struct hda_pcm *pcm;
1379 struct hda_pcm_stream *hinfo;
1380 struct snd_pcm_substream *substream;
1381 int mux_idx;
1382 bool non_pcm;
1383
1384 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1385 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1386 else
1387 return;
1388 if (!pcm->pcm)
1389 return;
1390 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1391 return;
1392
1393 /* hdmi audio only uses playback and one substream */
1394 hinfo = pcm->stream;
1395 substream = pcm->pcm->streams[0].substream;
1396
1397 per_pin->cvt_nid = hinfo->nid;
1398
1399 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1400 if (mux_idx < per_pin->num_mux_nids) {
1401 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1402 per_pin->dev_id);
1403 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1404 AC_VERB_SET_CONNECT_SEL,
1405 mux_idx);
1406 }
1407 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1408
1409 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1410 if (substream->runtime)
1411 per_pin->channels = substream->runtime->channels;
1412 per_pin->setup = true;
1413 per_pin->mux_idx = mux_idx;
1414
1415 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1416 }
1417
1418 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1419 struct hdmi_spec_per_pin *per_pin)
1420 {
1421 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1422 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1423
1424 per_pin->chmap_set = false;
1425 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1426
1427 per_pin->setup = false;
1428 per_pin->channels = 0;
1429 }
1430
1431 /* update per_pin ELD from the given new ELD;
1432 * setup info frame and notification accordingly
1433 */
1434 static void update_eld(struct hda_codec *codec,
1435 struct hdmi_spec_per_pin *per_pin,
1436 struct hdmi_eld *eld)
1437 {
1438 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1439 struct hdmi_spec *spec = codec->spec;
1440 bool old_eld_valid = pin_eld->eld_valid;
1441 bool eld_changed;
1442 int pcm_idx = -1;
1443
1444 /* for monitor disconnection, save pcm_idx firstly */
1445 pcm_idx = per_pin->pcm_idx;
1446 if (spec->dyn_pcm_assign) {
1447 if (eld->eld_valid) {
1448 hdmi_attach_hda_pcm(spec, per_pin);
1449 hdmi_pcm_setup_pin(spec, per_pin);
1450 } else {
1451 hdmi_pcm_reset_pin(spec, per_pin);
1452 hdmi_detach_hda_pcm(spec, per_pin);
1453 }
1454 }
1455 /* if pcm_idx == -1, it means this is in monitor connection event
1456 * we can get the correct pcm_idx now.
1457 */
1458 if (pcm_idx == -1)
1459 pcm_idx = per_pin->pcm_idx;
1460
1461 if (eld->eld_valid)
1462 snd_hdmi_show_eld(codec, &eld->info);
1463
1464 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1465 if (eld->eld_valid && pin_eld->eld_valid)
1466 if (pin_eld->eld_size != eld->eld_size ||
1467 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1468 eld->eld_size) != 0)
1469 eld_changed = true;
1470
1471 pin_eld->monitor_present = eld->monitor_present;
1472 pin_eld->eld_valid = eld->eld_valid;
1473 pin_eld->eld_size = eld->eld_size;
1474 if (eld->eld_valid)
1475 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1476 pin_eld->info = eld->info;
1477
1478 /*
1479 * Re-setup pin and infoframe. This is needed e.g. when
1480 * - sink is first plugged-in
1481 * - transcoder can change during stream playback on Haswell
1482 * and this can make HW reset converter selection on a pin.
1483 */
1484 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1485 pin_cvt_fixup(codec, per_pin, 0);
1486 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1487 }
1488
1489 if (eld_changed && pcm_idx >= 0)
1490 snd_ctl_notify(codec->card,
1491 SNDRV_CTL_EVENT_MASK_VALUE |
1492 SNDRV_CTL_EVENT_MASK_INFO,
1493 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1494 }
1495
1496 /* update ELD and jack state via HD-audio verbs */
1497 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1498 int repoll)
1499 {
1500 struct hda_jack_tbl *jack;
1501 struct hda_codec *codec = per_pin->codec;
1502 struct hdmi_spec *spec = codec->spec;
1503 struct hdmi_eld *eld = &spec->temp_eld;
1504 hda_nid_t pin_nid = per_pin->pin_nid;
1505 /*
1506 * Always execute a GetPinSense verb here, even when called from
1507 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1508 * response's PD bit is not the real PD value, but indicates that
1509 * the real PD value changed. An older version of the HD-audio
1510 * specification worked this way. Hence, we just ignore the data in
1511 * the unsolicited response to avoid custom WARs.
1512 */
1513 int present;
1514 bool ret;
1515 bool do_repoll = false;
1516
1517 present = snd_hda_pin_sense(codec, pin_nid);
1518
1519 mutex_lock(&per_pin->lock);
1520 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1521 if (eld->monitor_present)
1522 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1523 else
1524 eld->eld_valid = false;
1525
1526 codec_dbg(codec,
1527 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1528 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1529
1530 if (eld->eld_valid) {
1531 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1532 &eld->eld_size) < 0)
1533 eld->eld_valid = false;
1534 else {
1535 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1536 eld->eld_size) < 0)
1537 eld->eld_valid = false;
1538 }
1539 if (!eld->eld_valid && repoll)
1540 do_repoll = true;
1541 }
1542
1543 if (do_repoll)
1544 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1545 else
1546 update_eld(codec, per_pin, eld);
1547
1548 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1549
1550 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1551 if (jack)
1552 jack->block_report = !ret;
1553
1554 mutex_unlock(&per_pin->lock);
1555 return ret;
1556 }
1557
1558 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1559 struct hdmi_spec_per_pin *per_pin)
1560 {
1561 struct hdmi_spec *spec = codec->spec;
1562 struct snd_jack *jack = NULL;
1563 struct hda_jack_tbl *jack_tbl;
1564
1565 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1566 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1567 * NULL even after snd_hda_jack_tbl_clear() is called to
1568 * free snd_jack. This may cause access invalid memory
1569 * when calling snd_jack_report
1570 */
1571 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1572 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1573 else if (!spec->dyn_pcm_assign) {
1574 /*
1575 * jack tbl doesn't support DP MST
1576 * DP MST will use dyn_pcm_assign,
1577 * so DP MST will never come here
1578 */
1579 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1580 if (jack_tbl)
1581 jack = jack_tbl->jack;
1582 }
1583 return jack;
1584 }
1585
1586 /* update ELD and jack state via audio component */
1587 static void sync_eld_via_acomp(struct hda_codec *codec,
1588 struct hdmi_spec_per_pin *per_pin)
1589 {
1590 struct hdmi_spec *spec = codec->spec;
1591 struct hdmi_eld *eld = &spec->temp_eld;
1592 struct snd_jack *jack = NULL;
1593 int size;
1594
1595 mutex_lock(&per_pin->lock);
1596 eld->monitor_present = false;
1597 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1598 per_pin->dev_id, &eld->monitor_present,
1599 eld->eld_buffer, ELD_MAX_SIZE);
1600 if (size > 0) {
1601 size = min(size, ELD_MAX_SIZE);
1602 if (snd_hdmi_parse_eld(codec, &eld->info,
1603 eld->eld_buffer, size) < 0)
1604 size = -EINVAL;
1605 }
1606
1607 if (size > 0) {
1608 eld->eld_valid = true;
1609 eld->eld_size = size;
1610 } else {
1611 eld->eld_valid = false;
1612 eld->eld_size = 0;
1613 }
1614
1615 /* pcm_idx >=0 before update_eld() means it is in monitor
1616 * disconnected event. Jack must be fetched before update_eld()
1617 */
1618 jack = pin_idx_to_jack(codec, per_pin);
1619 update_eld(codec, per_pin, eld);
1620 if (jack == NULL)
1621 jack = pin_idx_to_jack(codec, per_pin);
1622 if (jack == NULL)
1623 goto unlock;
1624 snd_jack_report(jack,
1625 eld->monitor_present ? SND_JACK_AVOUT : 0);
1626 unlock:
1627 mutex_unlock(&per_pin->lock);
1628 }
1629
1630 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1631 {
1632 struct hda_codec *codec = per_pin->codec;
1633 int ret;
1634
1635 /* no temporary power up/down needed for component notifier */
1636 if (!codec_has_acomp(codec)) {
1637 ret = snd_hda_power_up_pm(codec);
1638 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1639 snd_hda_power_down_pm(codec);
1640 return false;
1641 }
1642 }
1643
1644 if (codec_has_acomp(codec)) {
1645 sync_eld_via_acomp(codec, per_pin);
1646 ret = false; /* don't call snd_hda_jack_report_sync() */
1647 } else {
1648 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1649 }
1650
1651 if (!codec_has_acomp(codec))
1652 snd_hda_power_down_pm(codec);
1653
1654 return ret;
1655 }
1656
1657 static void hdmi_repoll_eld(struct work_struct *work)
1658 {
1659 struct hdmi_spec_per_pin *per_pin =
1660 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1661 struct hda_codec *codec = per_pin->codec;
1662 struct hdmi_spec *spec = codec->spec;
1663
1664 if (per_pin->repoll_count++ > 6)
1665 per_pin->repoll_count = 0;
1666
1667 mutex_lock(&spec->pcm_lock);
1668 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1669 snd_hda_jack_report_sync(per_pin->codec);
1670 mutex_unlock(&spec->pcm_lock);
1671 }
1672
1673 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1674 hda_nid_t nid);
1675
1676 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1677 {
1678 struct hdmi_spec *spec = codec->spec;
1679 unsigned int caps, config;
1680 int pin_idx;
1681 struct hdmi_spec_per_pin *per_pin;
1682 int err;
1683 int dev_num, i;
1684
1685 caps = snd_hda_query_pin_caps(codec, pin_nid);
1686 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1687 return 0;
1688
1689 /*
1690 * For DP MST audio, Configuration Default is the same for
1691 * all device entries on the same pin
1692 */
1693 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1694 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1695 return 0;
1696
1697 /*
1698 * To simplify the implementation, malloc all
1699 * the virtual pins in the initialization statically
1700 */
1701 if (is_haswell_plus(codec)) {
1702 /*
1703 * On Intel platforms, device entries number is
1704 * changed dynamically. If there is a DP MST
1705 * hub connected, the device entries number is 3.
1706 * Otherwise, it is 1.
1707 * Here we manually set dev_num to 3, so that
1708 * we can initialize all the device entries when
1709 * bootup statically.
1710 */
1711 dev_num = 3;
1712 spec->dev_num = 3;
1713 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1714 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1715 /*
1716 * spec->dev_num is the maxinum number of device entries
1717 * among all the pins
1718 */
1719 spec->dev_num = (spec->dev_num > dev_num) ?
1720 spec->dev_num : dev_num;
1721 } else {
1722 /*
1723 * If the platform doesn't support DP MST,
1724 * manually set dev_num to 1. This means
1725 * the pin has only one device entry.
1726 */
1727 dev_num = 1;
1728 spec->dev_num = 1;
1729 }
1730
1731 for (i = 0; i < dev_num; i++) {
1732 pin_idx = spec->num_pins;
1733 per_pin = snd_array_new(&spec->pins);
1734
1735 if (!per_pin)
1736 return -ENOMEM;
1737
1738 if (spec->dyn_pcm_assign) {
1739 per_pin->pcm = NULL;
1740 per_pin->pcm_idx = -1;
1741 } else {
1742 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1743 per_pin->pcm_idx = pin_idx;
1744 }
1745 per_pin->pin_nid = pin_nid;
1746 per_pin->pin_nid_idx = spec->num_nids;
1747 per_pin->dev_id = i;
1748 per_pin->non_pcm = false;
1749 snd_hda_set_dev_select(codec, pin_nid, i);
1750 if (is_haswell_plus(codec))
1751 intel_haswell_fixup_connect_list(codec, pin_nid);
1752 err = hdmi_read_pin_conn(codec, pin_idx);
1753 if (err < 0)
1754 return err;
1755 spec->num_pins++;
1756 }
1757 spec->num_nids++;
1758
1759 return 0;
1760 }
1761
1762 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1763 {
1764 struct hdmi_spec *spec = codec->spec;
1765 struct hdmi_spec_per_cvt *per_cvt;
1766 unsigned int chans;
1767 int err;
1768
1769 chans = get_wcaps(codec, cvt_nid);
1770 chans = get_wcaps_channels(chans);
1771
1772 per_cvt = snd_array_new(&spec->cvts);
1773 if (!per_cvt)
1774 return -ENOMEM;
1775
1776 per_cvt->cvt_nid = cvt_nid;
1777 per_cvt->channels_min = 2;
1778 if (chans <= 16) {
1779 per_cvt->channels_max = chans;
1780 if (chans > spec->chmap.channels_max)
1781 spec->chmap.channels_max = chans;
1782 }
1783
1784 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1785 &per_cvt->rates,
1786 &per_cvt->formats,
1787 &per_cvt->maxbps);
1788 if (err < 0)
1789 return err;
1790
1791 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1792 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1793 spec->num_cvts++;
1794
1795 return 0;
1796 }
1797
1798 static int hdmi_parse_codec(struct hda_codec *codec)
1799 {
1800 hda_nid_t nid;
1801 int i, nodes;
1802
1803 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1804 if (!nid || nodes < 0) {
1805 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1806 return -EINVAL;
1807 }
1808
1809 for (i = 0; i < nodes; i++, nid++) {
1810 unsigned int caps;
1811 unsigned int type;
1812
1813 caps = get_wcaps(codec, nid);
1814 type = get_wcaps_type(caps);
1815
1816 if (!(caps & AC_WCAP_DIGITAL))
1817 continue;
1818
1819 switch (type) {
1820 case AC_WID_AUD_OUT:
1821 hdmi_add_cvt(codec, nid);
1822 break;
1823 case AC_WID_PIN:
1824 hdmi_add_pin(codec, nid);
1825 break;
1826 }
1827 }
1828
1829 return 0;
1830 }
1831
1832 /*
1833 */
1834 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1835 {
1836 struct hda_spdif_out *spdif;
1837 bool non_pcm;
1838
1839 mutex_lock(&codec->spdif_mutex);
1840 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1841 /* Add sanity check to pass klockwork check.
1842 * This should never happen.
1843 */
1844 if (WARN_ON(spdif == NULL))
1845 return true;
1846 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1847 mutex_unlock(&codec->spdif_mutex);
1848 return non_pcm;
1849 }
1850
1851 /*
1852 * HDMI callbacks
1853 */
1854
1855 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1856 struct hda_codec *codec,
1857 unsigned int stream_tag,
1858 unsigned int format,
1859 struct snd_pcm_substream *substream)
1860 {
1861 hda_nid_t cvt_nid = hinfo->nid;
1862 struct hdmi_spec *spec = codec->spec;
1863 int pin_idx;
1864 struct hdmi_spec_per_pin *per_pin;
1865 hda_nid_t pin_nid;
1866 struct snd_pcm_runtime *runtime = substream->runtime;
1867 bool non_pcm;
1868 int pinctl, stripe;
1869 int err = 0;
1870
1871 mutex_lock(&spec->pcm_lock);
1872 pin_idx = hinfo_to_pin_index(codec, hinfo);
1873 if (spec->dyn_pcm_assign && pin_idx < 0) {
1874 /* when dyn_pcm_assign and pcm is not bound to a pin
1875 * skip pin setup and return 0 to make audio playback
1876 * be ongoing
1877 */
1878 pin_cvt_fixup(codec, NULL, cvt_nid);
1879 snd_hda_codec_setup_stream(codec, cvt_nid,
1880 stream_tag, 0, format);
1881 goto unlock;
1882 }
1883
1884 if (snd_BUG_ON(pin_idx < 0)) {
1885 err = -EINVAL;
1886 goto unlock;
1887 }
1888 per_pin = get_pin(spec, pin_idx);
1889 pin_nid = per_pin->pin_nid;
1890
1891 /* Verify pin:cvt selections to avoid silent audio after S3.
1892 * After S3, the audio driver restores pin:cvt selections
1893 * but this can happen before gfx is ready and such selection
1894 * is overlooked by HW. Thus multiple pins can share a same
1895 * default convertor and mute control will affect each other,
1896 * which can cause a resumed audio playback become silent
1897 * after S3.
1898 */
1899 pin_cvt_fixup(codec, per_pin, 0);
1900
1901 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1902 /* Todo: add DP1.2 MST audio support later */
1903 if (codec_has_acomp(codec))
1904 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1905 runtime->rate);
1906
1907 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1908 mutex_lock(&per_pin->lock);
1909 per_pin->channels = substream->runtime->channels;
1910 per_pin->setup = true;
1911
1912 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1913 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1914 substream);
1915 snd_hda_codec_write(codec, cvt_nid, 0,
1916 AC_VERB_SET_STRIPE_CONTROL,
1917 stripe);
1918 }
1919
1920 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1921 mutex_unlock(&per_pin->lock);
1922 if (spec->dyn_pin_out) {
1923 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1924 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1925 snd_hda_codec_write(codec, pin_nid, 0,
1926 AC_VERB_SET_PIN_WIDGET_CONTROL,
1927 pinctl | PIN_OUT);
1928 }
1929
1930 /* snd_hda_set_dev_select() has been called before */
1931 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1932 stream_tag, format);
1933 unlock:
1934 mutex_unlock(&spec->pcm_lock);
1935 return err;
1936 }
1937
1938 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1939 struct hda_codec *codec,
1940 struct snd_pcm_substream *substream)
1941 {
1942 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1943 return 0;
1944 }
1945
1946 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1947 struct hda_codec *codec,
1948 struct snd_pcm_substream *substream)
1949 {
1950 struct hdmi_spec *spec = codec->spec;
1951 int cvt_idx, pin_idx, pcm_idx;
1952 struct hdmi_spec_per_cvt *per_cvt;
1953 struct hdmi_spec_per_pin *per_pin;
1954 int pinctl;
1955 int err = 0;
1956
1957 if (hinfo->nid) {
1958 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1959 if (snd_BUG_ON(pcm_idx < 0))
1960 return -EINVAL;
1961 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1962 if (snd_BUG_ON(cvt_idx < 0))
1963 return -EINVAL;
1964 per_cvt = get_cvt(spec, cvt_idx);
1965
1966 snd_BUG_ON(!per_cvt->assigned);
1967 per_cvt->assigned = 0;
1968 hinfo->nid = 0;
1969
1970 mutex_lock(&spec->pcm_lock);
1971 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1972 clear_bit(pcm_idx, &spec->pcm_in_use);
1973 pin_idx = hinfo_to_pin_index(codec, hinfo);
1974 if (spec->dyn_pcm_assign && pin_idx < 0)
1975 goto unlock;
1976
1977 if (snd_BUG_ON(pin_idx < 0)) {
1978 err = -EINVAL;
1979 goto unlock;
1980 }
1981 per_pin = get_pin(spec, pin_idx);
1982
1983 if (spec->dyn_pin_out) {
1984 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1985 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1986 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1987 AC_VERB_SET_PIN_WIDGET_CONTROL,
1988 pinctl & ~PIN_OUT);
1989 }
1990
1991 mutex_lock(&per_pin->lock);
1992 per_pin->chmap_set = false;
1993 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1994
1995 per_pin->setup = false;
1996 per_pin->channels = 0;
1997 mutex_unlock(&per_pin->lock);
1998 unlock:
1999 mutex_unlock(&spec->pcm_lock);
2000 }
2001
2002 return err;
2003 }
2004
2005 static const struct hda_pcm_ops generic_ops = {
2006 .open = hdmi_pcm_open,
2007 .close = hdmi_pcm_close,
2008 .prepare = generic_hdmi_playback_pcm_prepare,
2009 .cleanup = generic_hdmi_playback_pcm_cleanup,
2010 };
2011
2012 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2013 {
2014 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2015 struct hdmi_spec *spec = codec->spec;
2016 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2017
2018 if (!per_pin)
2019 return 0;
2020
2021 return per_pin->sink_eld.info.spk_alloc;
2022 }
2023
2024 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2025 unsigned char *chmap)
2026 {
2027 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2028 struct hdmi_spec *spec = codec->spec;
2029 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2030
2031 /* chmap is already set to 0 in caller */
2032 if (!per_pin)
2033 return;
2034
2035 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2036 }
2037
2038 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2039 unsigned char *chmap, int prepared)
2040 {
2041 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2042 struct hdmi_spec *spec = codec->spec;
2043 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2044
2045 if (!per_pin)
2046 return;
2047 mutex_lock(&per_pin->lock);
2048 per_pin->chmap_set = true;
2049 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2050 if (prepared)
2051 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2052 mutex_unlock(&per_pin->lock);
2053 }
2054
2055 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2056 {
2057 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2058 struct hdmi_spec *spec = codec->spec;
2059 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2060
2061 return per_pin ? true:false;
2062 }
2063
2064 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2065 {
2066 struct hdmi_spec *spec = codec->spec;
2067 int idx;
2068
2069 /*
2070 * for non-mst mode, pcm number is the same as before
2071 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2072 * dev_num is the device entry number in a pin
2073 *
2074 */
2075 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2076 struct hda_pcm *info;
2077 struct hda_pcm_stream *pstr;
2078
2079 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2080 if (!info)
2081 return -ENOMEM;
2082
2083 spec->pcm_rec[idx].pcm = info;
2084 spec->pcm_used++;
2085 info->pcm_type = HDA_PCM_TYPE_HDMI;
2086 info->own_chmap = true;
2087
2088 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2089 pstr->substreams = 1;
2090 pstr->ops = generic_ops;
2091 /* pcm number is less than 16 */
2092 if (spec->pcm_used >= 16)
2093 break;
2094 /* other pstr fields are set in open */
2095 }
2096
2097 return 0;
2098 }
2099
2100 static void free_hdmi_jack_priv(struct snd_jack *jack)
2101 {
2102 struct hdmi_pcm *pcm = jack->private_data;
2103
2104 pcm->jack = NULL;
2105 }
2106
2107 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2108 struct hdmi_spec *spec,
2109 int pcm_idx,
2110 const char *name)
2111 {
2112 struct snd_jack *jack;
2113 int err;
2114
2115 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2116 true, false);
2117 if (err < 0)
2118 return err;
2119
2120 spec->pcm_rec[pcm_idx].jack = jack;
2121 jack->private_data = &spec->pcm_rec[pcm_idx];
2122 jack->private_free = free_hdmi_jack_priv;
2123 return 0;
2124 }
2125
2126 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2127 {
2128 char hdmi_str[32] = "HDMI/DP";
2129 struct hdmi_spec *spec = codec->spec;
2130 struct hdmi_spec_per_pin *per_pin;
2131 struct hda_jack_tbl *jack;
2132 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2133 bool phantom_jack;
2134 int ret;
2135
2136 if (pcmdev > 0)
2137 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2138
2139 if (spec->dyn_pcm_assign)
2140 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2141
2142 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2143 /* if !dyn_pcm_assign, it must be non-MST mode.
2144 * This means pcms and pins are statically mapped.
2145 * And pcm_idx is pin_idx.
2146 */
2147 per_pin = get_pin(spec, pcm_idx);
2148 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2149 if (phantom_jack)
2150 strncat(hdmi_str, " Phantom",
2151 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2152 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2153 phantom_jack, 0, NULL);
2154 if (ret < 0)
2155 return ret;
2156 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2157 if (jack == NULL)
2158 return 0;
2159 /* assign jack->jack to pcm_rec[].jack to
2160 * align with dyn_pcm_assign mode
2161 */
2162 spec->pcm_rec[pcm_idx].jack = jack->jack;
2163 return 0;
2164 }
2165
2166 static int generic_hdmi_build_controls(struct hda_codec *codec)
2167 {
2168 struct hdmi_spec *spec = codec->spec;
2169 int dev, err;
2170 int pin_idx, pcm_idx;
2171
2172 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2173 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2174 /* no PCM: mark this for skipping permanently */
2175 set_bit(pcm_idx, &spec->pcm_bitmap);
2176 continue;
2177 }
2178
2179 err = generic_hdmi_build_jack(codec, pcm_idx);
2180 if (err < 0)
2181 return err;
2182
2183 /* create the spdif for each pcm
2184 * pin will be bound when monitor is connected
2185 */
2186 if (spec->dyn_pcm_assign)
2187 err = snd_hda_create_dig_out_ctls(codec,
2188 0, spec->cvt_nids[0],
2189 HDA_PCM_TYPE_HDMI);
2190 else {
2191 struct hdmi_spec_per_pin *per_pin =
2192 get_pin(spec, pcm_idx);
2193 err = snd_hda_create_dig_out_ctls(codec,
2194 per_pin->pin_nid,
2195 per_pin->mux_nids[0],
2196 HDA_PCM_TYPE_HDMI);
2197 }
2198 if (err < 0)
2199 return err;
2200 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2201
2202 dev = get_pcm_rec(spec, pcm_idx)->device;
2203 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2204 /* add control for ELD Bytes */
2205 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2206 if (err < 0)
2207 return err;
2208 }
2209 }
2210
2211 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2212 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2213
2214 hdmi_present_sense(per_pin, 0);
2215 }
2216
2217 /* add channel maps */
2218 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2219 struct hda_pcm *pcm;
2220
2221 pcm = get_pcm_rec(spec, pcm_idx);
2222 if (!pcm || !pcm->pcm)
2223 break;
2224 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2225 if (err < 0)
2226 return err;
2227 }
2228
2229 return 0;
2230 }
2231
2232 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2233 {
2234 struct hdmi_spec *spec = codec->spec;
2235 int pin_idx;
2236
2237 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2238 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2239
2240 per_pin->codec = codec;
2241 mutex_init(&per_pin->lock);
2242 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2243 eld_proc_new(per_pin, pin_idx);
2244 }
2245 return 0;
2246 }
2247
2248 static int generic_hdmi_init(struct hda_codec *codec)
2249 {
2250 struct hdmi_spec *spec = codec->spec;
2251 int pin_idx;
2252
2253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2254 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2255 hda_nid_t pin_nid = per_pin->pin_nid;
2256 int dev_id = per_pin->dev_id;
2257
2258 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2259 hdmi_init_pin(codec, pin_nid);
2260 if (!codec_has_acomp(codec))
2261 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2262 codec->jackpoll_interval > 0 ?
2263 jack_callback : NULL);
2264 }
2265 return 0;
2266 }
2267
2268 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2269 {
2270 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2271 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2272 }
2273
2274 static void hdmi_array_free(struct hdmi_spec *spec)
2275 {
2276 snd_array_free(&spec->pins);
2277 snd_array_free(&spec->cvts);
2278 }
2279
2280 static void generic_spec_free(struct hda_codec *codec)
2281 {
2282 struct hdmi_spec *spec = codec->spec;
2283
2284 if (spec) {
2285 hdmi_array_free(spec);
2286 kfree(spec);
2287 codec->spec = NULL;
2288 }
2289 codec->dp_mst = false;
2290 }
2291
2292 static void generic_hdmi_free(struct hda_codec *codec)
2293 {
2294 struct hdmi_spec *spec = codec->spec;
2295 int pin_idx, pcm_idx;
2296
2297 if (codec_has_acomp(codec))
2298 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2299
2300 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2301 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2302 cancel_delayed_work_sync(&per_pin->work);
2303 eld_proc_free(per_pin);
2304 }
2305
2306 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2307 if (spec->pcm_rec[pcm_idx].jack == NULL)
2308 continue;
2309 if (spec->dyn_pcm_assign)
2310 snd_device_free(codec->card,
2311 spec->pcm_rec[pcm_idx].jack);
2312 else
2313 spec->pcm_rec[pcm_idx].jack = NULL;
2314 }
2315
2316 generic_spec_free(codec);
2317 }
2318
2319 #ifdef CONFIG_PM
2320 static int generic_hdmi_resume(struct hda_codec *codec)
2321 {
2322 struct hdmi_spec *spec = codec->spec;
2323 int pin_idx;
2324
2325 codec->patch_ops.init(codec);
2326 regcache_sync(codec->core.regmap);
2327
2328 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2329 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2330 hdmi_present_sense(per_pin, 1);
2331 }
2332 return 0;
2333 }
2334 #endif
2335
2336 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2337 .init = generic_hdmi_init,
2338 .free = generic_hdmi_free,
2339 .build_pcms = generic_hdmi_build_pcms,
2340 .build_controls = generic_hdmi_build_controls,
2341 .unsol_event = hdmi_unsol_event,
2342 #ifdef CONFIG_PM
2343 .resume = generic_hdmi_resume,
2344 #endif
2345 };
2346
2347 static const struct hdmi_ops generic_standard_hdmi_ops = {
2348 .pin_get_eld = snd_hdmi_get_eld,
2349 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2350 .pin_hbr_setup = hdmi_pin_hbr_setup,
2351 .setup_stream = hdmi_setup_stream,
2352 };
2353
2354 /* allocate codec->spec and assign/initialize generic parser ops */
2355 static int alloc_generic_hdmi(struct hda_codec *codec)
2356 {
2357 struct hdmi_spec *spec;
2358
2359 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2360 if (!spec)
2361 return -ENOMEM;
2362
2363 spec->ops = generic_standard_hdmi_ops;
2364 spec->dev_num = 1; /* initialize to 1 */
2365 mutex_init(&spec->pcm_lock);
2366 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2367
2368 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2369 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2370 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2371 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2372
2373 codec->spec = spec;
2374 hdmi_array_init(spec, 4);
2375
2376 codec->patch_ops = generic_hdmi_patch_ops;
2377
2378 return 0;
2379 }
2380
2381 /* generic HDMI parser */
2382 static int patch_generic_hdmi(struct hda_codec *codec)
2383 {
2384 int err;
2385
2386 err = alloc_generic_hdmi(codec);
2387 if (err < 0)
2388 return err;
2389
2390 err = hdmi_parse_codec(codec);
2391 if (err < 0) {
2392 generic_spec_free(codec);
2393 return err;
2394 }
2395
2396 generic_hdmi_init_per_pins(codec);
2397 return 0;
2398 }
2399
2400 /*
2401 * Intel codec parsers and helpers
2402 */
2403
2404 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2405 hda_nid_t nid)
2406 {
2407 struct hdmi_spec *spec = codec->spec;
2408 hda_nid_t conns[4];
2409 int nconns;
2410
2411 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2412 if (nconns == spec->num_cvts &&
2413 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2414 return;
2415
2416 /* override pins connection list */
2417 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2418 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2419 }
2420
2421 #define INTEL_VENDOR_NID 0x08
2422 #define INTEL_GLK_VENDOR_NID 0x0B
2423 #define INTEL_GET_VENDOR_VERB 0xf81
2424 #define INTEL_SET_VENDOR_VERB 0x781
2425 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2426 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2427
2428 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2429 bool update_tree)
2430 {
2431 unsigned int vendor_param;
2432 struct hdmi_spec *spec = codec->spec;
2433
2434 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2435 INTEL_GET_VENDOR_VERB, 0);
2436 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2437 return;
2438
2439 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2440 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2441 INTEL_SET_VENDOR_VERB, vendor_param);
2442 if (vendor_param == -1)
2443 return;
2444
2445 if (update_tree)
2446 snd_hda_codec_update_widgets(codec);
2447 }
2448
2449 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2450 {
2451 unsigned int vendor_param;
2452 struct hdmi_spec *spec = codec->spec;
2453
2454 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2455 INTEL_GET_VENDOR_VERB, 0);
2456 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2457 return;
2458
2459 /* enable DP1.2 mode */
2460 vendor_param |= INTEL_EN_DP12;
2461 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2462 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2463 INTEL_SET_VENDOR_VERB, vendor_param);
2464 }
2465
2466 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2467 * Otherwise you may get severe h/w communication errors.
2468 */
2469 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2470 unsigned int power_state)
2471 {
2472 if (power_state == AC_PWRST_D0) {
2473 intel_haswell_enable_all_pins(codec, false);
2474 intel_haswell_fixup_enable_dp12(codec);
2475 }
2476
2477 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2478 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2479 }
2480
2481 /* There is a fixed mapping between audio pin node and display port.
2482 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2483 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2484 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2485 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2486 *
2487 * on VLV, ILK:
2488 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2489 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2490 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2491 */
2492 static int intel_base_nid(struct hda_codec *codec)
2493 {
2494 switch (codec->core.vendor_id) {
2495 case 0x80860054: /* ILK */
2496 case 0x80862804: /* ILK */
2497 case 0x80862882: /* VLV */
2498 return 4;
2499 default:
2500 return 5;
2501 }
2502 }
2503
2504 static int intel_pin2port(void *audio_ptr, int pin_nid)
2505 {
2506 int base_nid = intel_base_nid(audio_ptr);
2507
2508 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2509 return -1;
2510 return pin_nid - base_nid + 1; /* intel port is 1-based */
2511 }
2512
2513 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2514 {
2515 struct hda_codec *codec = audio_ptr;
2516 int pin_nid;
2517 int dev_id = pipe;
2518
2519 /* we assume only from port-B to port-D */
2520 if (port < 1 || port > 3)
2521 return;
2522
2523 pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */
2524
2525 /* skip notification during system suspend (but not in runtime PM);
2526 * the state will be updated at resume
2527 */
2528 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2529 return;
2530 /* ditto during suspend/resume process itself */
2531 if (snd_hdac_is_in_pm(&codec->core))
2532 return;
2533
2534 snd_hdac_i915_set_bclk(&codec->bus->core);
2535 check_presence_and_report(codec, pin_nid, dev_id);
2536 }
2537
2538 /* register i915 component pin_eld_notify callback */
2539 static void register_i915_notifier(struct hda_codec *codec)
2540 {
2541 struct hdmi_spec *spec = codec->spec;
2542
2543 spec->use_acomp_notifier = true;
2544 spec->drm_audio_ops.audio_ptr = codec;
2545 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2546 * will call pin_eld_notify with using audio_ptr pointer
2547 * We need make sure audio_ptr is really setup
2548 */
2549 wmb();
2550 spec->drm_audio_ops.pin2port = intel_pin2port;
2551 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2552 snd_hdac_acomp_register_notifier(&codec->bus->core,
2553 &spec->drm_audio_ops);
2554 }
2555
2556 /* setup_stream ops override for HSW+ */
2557 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2558 hda_nid_t pin_nid, u32 stream_tag, int format)
2559 {
2560 haswell_verify_D0(codec, cvt_nid, pin_nid);
2561 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2562 }
2563
2564 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2565 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2566 struct hdmi_spec_per_pin *per_pin,
2567 hda_nid_t cvt_nid)
2568 {
2569 if (per_pin) {
2570 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2571 per_pin->dev_id);
2572 intel_verify_pin_cvt_connect(codec, per_pin);
2573 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2574 per_pin->dev_id, per_pin->mux_idx);
2575 } else {
2576 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2577 }
2578 }
2579
2580 /* precondition and allocation for Intel codecs */
2581 static int alloc_intel_hdmi(struct hda_codec *codec)
2582 {
2583 /* requires i915 binding */
2584 if (!codec->bus->core.audio_component) {
2585 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2586 /* set probe_id here to prevent generic fallback binding */
2587 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2588 return -ENODEV;
2589 }
2590
2591 return alloc_generic_hdmi(codec);
2592 }
2593
2594 /* parse and post-process for Intel codecs */
2595 static int parse_intel_hdmi(struct hda_codec *codec)
2596 {
2597 int err;
2598
2599 err = hdmi_parse_codec(codec);
2600 if (err < 0) {
2601 generic_spec_free(codec);
2602 return err;
2603 }
2604
2605 generic_hdmi_init_per_pins(codec);
2606 register_i915_notifier(codec);
2607 return 0;
2608 }
2609
2610 /* Intel Haswell and onwards; audio component with eld notifier */
2611 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2612 {
2613 struct hdmi_spec *spec;
2614 int err;
2615
2616 err = alloc_intel_hdmi(codec);
2617 if (err < 0)
2618 return err;
2619 spec = codec->spec;
2620 codec->dp_mst = true;
2621 spec->dyn_pcm_assign = true;
2622 spec->vendor_nid = vendor_nid;
2623
2624 intel_haswell_enable_all_pins(codec, true);
2625 intel_haswell_fixup_enable_dp12(codec);
2626
2627 codec->display_power_control = 1;
2628
2629 codec->patch_ops.set_power_state = haswell_set_power_state;
2630 codec->depop_delay = 0;
2631 codec->auto_runtime_pm = 1;
2632
2633 spec->ops.setup_stream = i915_hsw_setup_stream;
2634 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2635
2636 return parse_intel_hdmi(codec);
2637 }
2638
2639 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2640 {
2641 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2642 }
2643
2644 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2645 {
2646 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2647 }
2648
2649 /* Intel Baytrail and Braswell; with eld notifier */
2650 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2651 {
2652 struct hdmi_spec *spec;
2653 int err;
2654
2655 err = alloc_intel_hdmi(codec);
2656 if (err < 0)
2657 return err;
2658 spec = codec->spec;
2659
2660 /* For Valleyview/Cherryview, only the display codec is in the display
2661 * power well and can use link_power ops to request/release the power.
2662 */
2663 codec->display_power_control = 1;
2664
2665 codec->depop_delay = 0;
2666 codec->auto_runtime_pm = 1;
2667
2668 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2669
2670 return parse_intel_hdmi(codec);
2671 }
2672
2673 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2674 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2675 {
2676 int err;
2677
2678 err = alloc_intel_hdmi(codec);
2679 if (err < 0)
2680 return err;
2681 return parse_intel_hdmi(codec);
2682 }
2683
2684 /*
2685 * Shared non-generic implementations
2686 */
2687
2688 static int simple_playback_build_pcms(struct hda_codec *codec)
2689 {
2690 struct hdmi_spec *spec = codec->spec;
2691 struct hda_pcm *info;
2692 unsigned int chans;
2693 struct hda_pcm_stream *pstr;
2694 struct hdmi_spec_per_cvt *per_cvt;
2695
2696 per_cvt = get_cvt(spec, 0);
2697 chans = get_wcaps(codec, per_cvt->cvt_nid);
2698 chans = get_wcaps_channels(chans);
2699
2700 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2701 if (!info)
2702 return -ENOMEM;
2703 spec->pcm_rec[0].pcm = info;
2704 info->pcm_type = HDA_PCM_TYPE_HDMI;
2705 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2706 *pstr = spec->pcm_playback;
2707 pstr->nid = per_cvt->cvt_nid;
2708 if (pstr->channels_max <= 2 && chans && chans <= 16)
2709 pstr->channels_max = chans;
2710
2711 return 0;
2712 }
2713
2714 /* unsolicited event for jack sensing */
2715 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2716 unsigned int res)
2717 {
2718 snd_hda_jack_set_dirty_all(codec);
2719 snd_hda_jack_report_sync(codec);
2720 }
2721
2722 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2723 * as long as spec->pins[] is set correctly
2724 */
2725 #define simple_hdmi_build_jack generic_hdmi_build_jack
2726
2727 static int simple_playback_build_controls(struct hda_codec *codec)
2728 {
2729 struct hdmi_spec *spec = codec->spec;
2730 struct hdmi_spec_per_cvt *per_cvt;
2731 int err;
2732
2733 per_cvt = get_cvt(spec, 0);
2734 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2735 per_cvt->cvt_nid,
2736 HDA_PCM_TYPE_HDMI);
2737 if (err < 0)
2738 return err;
2739 return simple_hdmi_build_jack(codec, 0);
2740 }
2741
2742 static int simple_playback_init(struct hda_codec *codec)
2743 {
2744 struct hdmi_spec *spec = codec->spec;
2745 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2746 hda_nid_t pin = per_pin->pin_nid;
2747
2748 snd_hda_codec_write(codec, pin, 0,
2749 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2750 /* some codecs require to unmute the pin */
2751 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2752 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2753 AMP_OUT_UNMUTE);
2754 snd_hda_jack_detect_enable(codec, pin);
2755 return 0;
2756 }
2757
2758 static void simple_playback_free(struct hda_codec *codec)
2759 {
2760 struct hdmi_spec *spec = codec->spec;
2761
2762 hdmi_array_free(spec);
2763 kfree(spec);
2764 }
2765
2766 /*
2767 * Nvidia specific implementations
2768 */
2769
2770 #define Nv_VERB_SET_Channel_Allocation 0xF79
2771 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2772 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2773 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2774
2775 #define nvhdmi_master_con_nid_7x 0x04
2776 #define nvhdmi_master_pin_nid_7x 0x05
2777
2778 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2779 /*front, rear, clfe, rear_surr */
2780 0x6, 0x8, 0xa, 0xc,
2781 };
2782
2783 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2784 /* set audio protect on */
2785 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2786 /* enable digital output on pin widget */
2787 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2788 {} /* terminator */
2789 };
2790
2791 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2792 /* set audio protect on */
2793 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2794 /* enable digital output on pin widget */
2795 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2796 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2797 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2798 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2799 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2800 {} /* terminator */
2801 };
2802
2803 #ifdef LIMITED_RATE_FMT_SUPPORT
2804 /* support only the safe format and rate */
2805 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2806 #define SUPPORTED_MAXBPS 16
2807 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2808 #else
2809 /* support all rates and formats */
2810 #define SUPPORTED_RATES \
2811 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2812 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2813 SNDRV_PCM_RATE_192000)
2814 #define SUPPORTED_MAXBPS 24
2815 #define SUPPORTED_FORMATS \
2816 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2817 #endif
2818
2819 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2820 {
2821 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2822 return 0;
2823 }
2824
2825 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2826 {
2827 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2828 return 0;
2829 }
2830
2831 static const unsigned int channels_2_6_8[] = {
2832 2, 6, 8
2833 };
2834
2835 static const unsigned int channels_2_8[] = {
2836 2, 8
2837 };
2838
2839 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2840 .count = ARRAY_SIZE(channels_2_6_8),
2841 .list = channels_2_6_8,
2842 .mask = 0,
2843 };
2844
2845 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2846 .count = ARRAY_SIZE(channels_2_8),
2847 .list = channels_2_8,
2848 .mask = 0,
2849 };
2850
2851 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2852 struct hda_codec *codec,
2853 struct snd_pcm_substream *substream)
2854 {
2855 struct hdmi_spec *spec = codec->spec;
2856 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2857
2858 switch (codec->preset->vendor_id) {
2859 case 0x10de0002:
2860 case 0x10de0003:
2861 case 0x10de0005:
2862 case 0x10de0006:
2863 hw_constraints_channels = &hw_constraints_2_8_channels;
2864 break;
2865 case 0x10de0007:
2866 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2867 break;
2868 default:
2869 break;
2870 }
2871
2872 if (hw_constraints_channels != NULL) {
2873 snd_pcm_hw_constraint_list(substream->runtime, 0,
2874 SNDRV_PCM_HW_PARAM_CHANNELS,
2875 hw_constraints_channels);
2876 } else {
2877 snd_pcm_hw_constraint_step(substream->runtime, 0,
2878 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2879 }
2880
2881 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2882 }
2883
2884 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2885 struct hda_codec *codec,
2886 struct snd_pcm_substream *substream)
2887 {
2888 struct hdmi_spec *spec = codec->spec;
2889 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2890 }
2891
2892 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2893 struct hda_codec *codec,
2894 unsigned int stream_tag,
2895 unsigned int format,
2896 struct snd_pcm_substream *substream)
2897 {
2898 struct hdmi_spec *spec = codec->spec;
2899 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2900 stream_tag, format, substream);
2901 }
2902
2903 static const struct hda_pcm_stream simple_pcm_playback = {
2904 .substreams = 1,
2905 .channels_min = 2,
2906 .channels_max = 2,
2907 .ops = {
2908 .open = simple_playback_pcm_open,
2909 .close = simple_playback_pcm_close,
2910 .prepare = simple_playback_pcm_prepare
2911 },
2912 };
2913
2914 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2915 .build_controls = simple_playback_build_controls,
2916 .build_pcms = simple_playback_build_pcms,
2917 .init = simple_playback_init,
2918 .free = simple_playback_free,
2919 .unsol_event = simple_hdmi_unsol_event,
2920 };
2921
2922 static int patch_simple_hdmi(struct hda_codec *codec,
2923 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2924 {
2925 struct hdmi_spec *spec;
2926 struct hdmi_spec_per_cvt *per_cvt;
2927 struct hdmi_spec_per_pin *per_pin;
2928
2929 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2930 if (!spec)
2931 return -ENOMEM;
2932
2933 codec->spec = spec;
2934 hdmi_array_init(spec, 1);
2935
2936 spec->multiout.num_dacs = 0; /* no analog */
2937 spec->multiout.max_channels = 2;
2938 spec->multiout.dig_out_nid = cvt_nid;
2939 spec->num_cvts = 1;
2940 spec->num_pins = 1;
2941 per_pin = snd_array_new(&spec->pins);
2942 per_cvt = snd_array_new(&spec->cvts);
2943 if (!per_pin || !per_cvt) {
2944 simple_playback_free(codec);
2945 return -ENOMEM;
2946 }
2947 per_cvt->cvt_nid = cvt_nid;
2948 per_pin->pin_nid = pin_nid;
2949 spec->pcm_playback = simple_pcm_playback;
2950
2951 codec->patch_ops = simple_hdmi_patch_ops;
2952
2953 return 0;
2954 }
2955
2956 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2957 int channels)
2958 {
2959 unsigned int chanmask;
2960 int chan = channels ? (channels - 1) : 1;
2961
2962 switch (channels) {
2963 default:
2964 case 0:
2965 case 2:
2966 chanmask = 0x00;
2967 break;
2968 case 4:
2969 chanmask = 0x08;
2970 break;
2971 case 6:
2972 chanmask = 0x0b;
2973 break;
2974 case 8:
2975 chanmask = 0x13;
2976 break;
2977 }
2978
2979 /* Set the audio infoframe channel allocation and checksum fields. The
2980 * channel count is computed implicitly by the hardware. */
2981 snd_hda_codec_write(codec, 0x1, 0,
2982 Nv_VERB_SET_Channel_Allocation, chanmask);
2983
2984 snd_hda_codec_write(codec, 0x1, 0,
2985 Nv_VERB_SET_Info_Frame_Checksum,
2986 (0x71 - chan - chanmask));
2987 }
2988
2989 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2990 struct hda_codec *codec,
2991 struct snd_pcm_substream *substream)
2992 {
2993 struct hdmi_spec *spec = codec->spec;
2994 int i;
2995
2996 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2997 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2998 for (i = 0; i < 4; i++) {
2999 /* set the stream id */
3000 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3001 AC_VERB_SET_CHANNEL_STREAMID, 0);
3002 /* set the stream format */
3003 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3004 AC_VERB_SET_STREAM_FORMAT, 0);
3005 }
3006
3007 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3008 * streams are disabled. */
3009 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3010
3011 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3012 }
3013
3014 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3015 struct hda_codec *codec,
3016 unsigned int stream_tag,
3017 unsigned int format,
3018 struct snd_pcm_substream *substream)
3019 {
3020 int chs;
3021 unsigned int dataDCC2, channel_id;
3022 int i;
3023 struct hdmi_spec *spec = codec->spec;
3024 struct hda_spdif_out *spdif;
3025 struct hdmi_spec_per_cvt *per_cvt;
3026
3027 mutex_lock(&codec->spdif_mutex);
3028 per_cvt = get_cvt(spec, 0);
3029 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3030
3031 chs = substream->runtime->channels;
3032
3033 dataDCC2 = 0x2;
3034
3035 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3036 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3037 snd_hda_codec_write(codec,
3038 nvhdmi_master_con_nid_7x,
3039 0,
3040 AC_VERB_SET_DIGI_CONVERT_1,
3041 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3042
3043 /* set the stream id */
3044 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3045 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3046
3047 /* set the stream format */
3048 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3049 AC_VERB_SET_STREAM_FORMAT, format);
3050
3051 /* turn on again (if needed) */
3052 /* enable and set the channel status audio/data flag */
3053 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3054 snd_hda_codec_write(codec,
3055 nvhdmi_master_con_nid_7x,
3056 0,
3057 AC_VERB_SET_DIGI_CONVERT_1,
3058 spdif->ctls & 0xff);
3059 snd_hda_codec_write(codec,
3060 nvhdmi_master_con_nid_7x,
3061 0,
3062 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3063 }
3064
3065 for (i = 0; i < 4; i++) {
3066 if (chs == 2)
3067 channel_id = 0;
3068 else
3069 channel_id = i * 2;
3070
3071 /* turn off SPDIF once;
3072 *otherwise the IEC958 bits won't be updated
3073 */
3074 if (codec->spdif_status_reset &&
3075 (spdif->ctls & AC_DIG1_ENABLE))
3076 snd_hda_codec_write(codec,
3077 nvhdmi_con_nids_7x[i],
3078 0,
3079 AC_VERB_SET_DIGI_CONVERT_1,
3080 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3081 /* set the stream id */
3082 snd_hda_codec_write(codec,
3083 nvhdmi_con_nids_7x[i],
3084 0,
3085 AC_VERB_SET_CHANNEL_STREAMID,
3086 (stream_tag << 4) | channel_id);
3087 /* set the stream format */
3088 snd_hda_codec_write(codec,
3089 nvhdmi_con_nids_7x[i],
3090 0,
3091 AC_VERB_SET_STREAM_FORMAT,
3092 format);
3093 /* turn on again (if needed) */
3094 /* enable and set the channel status audio/data flag */
3095 if (codec->spdif_status_reset &&
3096 (spdif->ctls & AC_DIG1_ENABLE)) {
3097 snd_hda_codec_write(codec,
3098 nvhdmi_con_nids_7x[i],
3099 0,
3100 AC_VERB_SET_DIGI_CONVERT_1,
3101 spdif->ctls & 0xff);
3102 snd_hda_codec_write(codec,
3103 nvhdmi_con_nids_7x[i],
3104 0,
3105 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3106 }
3107 }
3108
3109 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3110
3111 mutex_unlock(&codec->spdif_mutex);
3112 return 0;
3113 }
3114
3115 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3116 .substreams = 1,
3117 .channels_min = 2,
3118 .channels_max = 8,
3119 .nid = nvhdmi_master_con_nid_7x,
3120 .rates = SUPPORTED_RATES,
3121 .maxbps = SUPPORTED_MAXBPS,
3122 .formats = SUPPORTED_FORMATS,
3123 .ops = {
3124 .open = simple_playback_pcm_open,
3125 .close = nvhdmi_8ch_7x_pcm_close,
3126 .prepare = nvhdmi_8ch_7x_pcm_prepare
3127 },
3128 };
3129
3130 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3131 {
3132 struct hdmi_spec *spec;
3133 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3134 nvhdmi_master_pin_nid_7x);
3135 if (err < 0)
3136 return err;
3137
3138 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3139 /* override the PCM rates, etc, as the codec doesn't give full list */
3140 spec = codec->spec;
3141 spec->pcm_playback.rates = SUPPORTED_RATES;
3142 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3143 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3144 return 0;
3145 }
3146
3147 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3148 {
3149 struct hdmi_spec *spec = codec->spec;
3150 int err = simple_playback_build_pcms(codec);
3151 if (!err) {
3152 struct hda_pcm *info = get_pcm_rec(spec, 0);
3153 info->own_chmap = true;
3154 }
3155 return err;
3156 }
3157
3158 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3159 {
3160 struct hdmi_spec *spec = codec->spec;
3161 struct hda_pcm *info;
3162 struct snd_pcm_chmap *chmap;
3163 int err;
3164
3165 err = simple_playback_build_controls(codec);
3166 if (err < 0)
3167 return err;
3168
3169 /* add channel maps */
3170 info = get_pcm_rec(spec, 0);
3171 err = snd_pcm_add_chmap_ctls(info->pcm,
3172 SNDRV_PCM_STREAM_PLAYBACK,
3173 snd_pcm_alt_chmaps, 8, 0, &chmap);
3174 if (err < 0)
3175 return err;
3176 switch (codec->preset->vendor_id) {
3177 case 0x10de0002:
3178 case 0x10de0003:
3179 case 0x10de0005:
3180 case 0x10de0006:
3181 chmap->channel_mask = (1U << 2) | (1U << 8);
3182 break;
3183 case 0x10de0007:
3184 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3185 }
3186 return 0;
3187 }
3188
3189 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3190 {
3191 struct hdmi_spec *spec;
3192 int err = patch_nvhdmi_2ch(codec);
3193 if (err < 0)
3194 return err;
3195 spec = codec->spec;
3196 spec->multiout.max_channels = 8;
3197 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3198 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3199 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3200 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3201
3202 /* Initialize the audio infoframe channel mask and checksum to something
3203 * valid */
3204 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3205
3206 return 0;
3207 }
3208
3209 /*
3210 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3211 * - 0x10de0015
3212 * - 0x10de0040
3213 */
3214 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3215 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3216 {
3217 if (cap->ca_index == 0x00 && channels == 2)
3218 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3219
3220 /* If the speaker allocation matches the channel count, it is OK. */
3221 if (cap->channels != channels)
3222 return -1;
3223
3224 /* all channels are remappable freely */
3225 return SNDRV_CTL_TLVT_CHMAP_VAR;
3226 }
3227
3228 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3229 int ca, int chs, unsigned char *map)
3230 {
3231 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3232 return -EINVAL;
3233
3234 return 0;
3235 }
3236
3237 static int patch_nvhdmi(struct hda_codec *codec)
3238 {
3239 struct hdmi_spec *spec;
3240 int err;
3241
3242 err = patch_generic_hdmi(codec);
3243 if (err)
3244 return err;
3245
3246 spec = codec->spec;
3247 spec->dyn_pin_out = true;
3248
3249 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3250 nvhdmi_chmap_cea_alloc_validate_get_type;
3251 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3252
3253 return 0;
3254 }
3255
3256 /*
3257 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3258 * accessed using vendor-defined verbs. These registers can be used for
3259 * interoperability between the HDA and HDMI drivers.
3260 */
3261
3262 /* Audio Function Group node */
3263 #define NVIDIA_AFG_NID 0x01
3264
3265 /*
3266 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3267 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3268 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3269 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3270 * additional bit (at position 30) to signal the validity of the format.
3271 *
3272 * | 31 | 30 | 29 16 | 15 0 |
3273 * +---------+-------+--------+--------+
3274 * | TRIGGER | VALID | UNUSED | FORMAT |
3275 * +-----------------------------------|
3276 *
3277 * Note that for the trigger bit to take effect it needs to change value
3278 * (i.e. it needs to be toggled).
3279 */
3280 #define NVIDIA_GET_SCRATCH0 0xfa6
3281 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3282 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3283 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3284 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3285 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3286 #define NVIDIA_SCRATCH_VALID (1 << 6)
3287
3288 #define NVIDIA_GET_SCRATCH1 0xfab
3289 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3290 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3291 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3292 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3293
3294 /*
3295 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3296 * the format is invalidated so that the HDMI codec can be disabled.
3297 */
3298 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3299 {
3300 unsigned int value;
3301
3302 /* bits [31:30] contain the trigger and valid bits */
3303 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3304 NVIDIA_GET_SCRATCH0, 0);
3305 value = (value >> 24) & 0xff;
3306
3307 /* bits [15:0] are used to store the HDA format */
3308 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3309 NVIDIA_SET_SCRATCH0_BYTE0,
3310 (format >> 0) & 0xff);
3311 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3312 NVIDIA_SET_SCRATCH0_BYTE1,
3313 (format >> 8) & 0xff);
3314
3315 /* bits [16:24] are unused */
3316 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3317 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3318
3319 /*
3320 * Bit 30 signals that the data is valid and hence that HDMI audio can
3321 * be enabled.
3322 */
3323 if (format == 0)
3324 value &= ~NVIDIA_SCRATCH_VALID;
3325 else
3326 value |= NVIDIA_SCRATCH_VALID;
3327
3328 /*
3329 * Whenever the trigger bit is toggled, an interrupt is raised in the
3330 * HDMI codec. The HDMI driver will use that as trigger to update its
3331 * configuration.
3332 */
3333 value ^= NVIDIA_SCRATCH_TRIGGER;
3334
3335 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3336 NVIDIA_SET_SCRATCH0_BYTE3, value);
3337 }
3338
3339 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3340 struct hda_codec *codec,
3341 unsigned int stream_tag,
3342 unsigned int format,
3343 struct snd_pcm_substream *substream)
3344 {
3345 int err;
3346
3347 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3348 format, substream);
3349 if (err < 0)
3350 return err;
3351
3352 /* notify the HDMI codec of the format change */
3353 tegra_hdmi_set_format(codec, format);
3354
3355 return 0;
3356 }
3357
3358 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3359 struct hda_codec *codec,
3360 struct snd_pcm_substream *substream)
3361 {
3362 /* invalidate the format in the HDMI codec */
3363 tegra_hdmi_set_format(codec, 0);
3364
3365 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3366 }
3367
3368 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3369 {
3370 struct hdmi_spec *spec = codec->spec;
3371 unsigned int i;
3372
3373 for (i = 0; i < spec->num_pins; i++) {
3374 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3375
3376 if (pcm->pcm_type == type)
3377 return pcm;
3378 }
3379
3380 return NULL;
3381 }
3382
3383 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3384 {
3385 struct hda_pcm_stream *stream;
3386 struct hda_pcm *pcm;
3387 int err;
3388
3389 err = generic_hdmi_build_pcms(codec);
3390 if (err < 0)
3391 return err;
3392
3393 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3394 if (!pcm)
3395 return -ENODEV;
3396
3397 /*
3398 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3399 * codec about format changes.
3400 */
3401 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3402 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3403 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3404
3405 return 0;
3406 }
3407
3408 static int patch_tegra_hdmi(struct hda_codec *codec)
3409 {
3410 int err;
3411
3412 err = patch_generic_hdmi(codec);
3413 if (err)
3414 return err;
3415
3416 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3417
3418 return 0;
3419 }
3420
3421 /*
3422 * ATI/AMD-specific implementations
3423 */
3424
3425 #define is_amdhdmi_rev3_or_later(codec) \
3426 ((codec)->core.vendor_id == 0x1002aa01 && \
3427 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3428 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3429
3430 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3431 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3432 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3433 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3434 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3435 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3436 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3437 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3438 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3439 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3440 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3441 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3442 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3443 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3444 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3445 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3446 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3447 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3448 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3449 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3450 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3451 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3452 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3453 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3454 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3455
3456 /* AMD specific HDA cvt verbs */
3457 #define ATI_VERB_SET_RAMP_RATE 0x770
3458 #define ATI_VERB_GET_RAMP_RATE 0xf70
3459
3460 #define ATI_OUT_ENABLE 0x1
3461
3462 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3463 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3464
3465 #define ATI_HBR_CAPABLE 0x01
3466 #define ATI_HBR_ENABLE 0x10
3467
3468 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3469 unsigned char *buf, int *eld_size)
3470 {
3471 /* call hda_eld.c ATI/AMD-specific function */
3472 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3473 is_amdhdmi_rev3_or_later(codec));
3474 }
3475
3476 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3477 int active_channels, int conn_type)
3478 {
3479 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3480 }
3481
3482 static int atihdmi_paired_swap_fc_lfe(int pos)
3483 {
3484 /*
3485 * ATI/AMD have automatic FC/LFE swap built-in
3486 * when in pairwise mapping mode.
3487 */
3488
3489 switch (pos) {
3490 /* see channel_allocations[].speakers[] */
3491 case 2: return 3;
3492 case 3: return 2;
3493 default: break;
3494 }
3495
3496 return pos;
3497 }
3498
3499 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3500 int ca, int chs, unsigned char *map)
3501 {
3502 struct hdac_cea_channel_speaker_allocation *cap;
3503 int i, j;
3504
3505 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3506
3507 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3508 for (i = 0; i < chs; ++i) {
3509 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3510 bool ok = false;
3511 bool companion_ok = false;
3512
3513 if (!mask)
3514 continue;
3515
3516 for (j = 0 + i % 2; j < 8; j += 2) {
3517 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3518 if (cap->speakers[chan_idx] == mask) {
3519 /* channel is in a supported position */
3520 ok = true;
3521
3522 if (i % 2 == 0 && i + 1 < chs) {
3523 /* even channel, check the odd companion */
3524 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3525 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3526 int comp_mask_act = cap->speakers[comp_chan_idx];
3527
3528 if (comp_mask_req == comp_mask_act)
3529 companion_ok = true;
3530 else
3531 return -EINVAL;
3532 }
3533 break;
3534 }
3535 }
3536
3537 if (!ok)
3538 return -EINVAL;
3539
3540 if (companion_ok)
3541 i++; /* companion channel already checked */
3542 }
3543
3544 return 0;
3545 }
3546
3547 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3548 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3549 {
3550 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3551 int verb;
3552 int ati_channel_setup = 0;
3553
3554 if (hdmi_slot > 7)
3555 return -EINVAL;
3556
3557 if (!has_amd_full_remap_support(codec)) {
3558 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3559
3560 /* In case this is an odd slot but without stream channel, do not
3561 * disable the slot since the corresponding even slot could have a
3562 * channel. In case neither have a channel, the slot pair will be
3563 * disabled when this function is called for the even slot. */
3564 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3565 return 0;
3566
3567 hdmi_slot -= hdmi_slot % 2;
3568
3569 if (stream_channel != 0xf)
3570 stream_channel -= stream_channel % 2;
3571 }
3572
3573 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3574
3575 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3576
3577 if (stream_channel != 0xf)
3578 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3579
3580 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3581 }
3582
3583 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3584 hda_nid_t pin_nid, int asp_slot)
3585 {
3586 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3587 bool was_odd = false;
3588 int ati_asp_slot = asp_slot;
3589 int verb;
3590 int ati_channel_setup;
3591
3592 if (asp_slot > 7)
3593 return -EINVAL;
3594
3595 if (!has_amd_full_remap_support(codec)) {
3596 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3597 if (ati_asp_slot % 2 != 0) {
3598 ati_asp_slot -= 1;
3599 was_odd = true;
3600 }
3601 }
3602
3603 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3604
3605 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3606
3607 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3608 return 0xf;
3609
3610 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3611 }
3612
3613 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3614 struct hdac_chmap *chmap,
3615 struct hdac_cea_channel_speaker_allocation *cap,
3616 int channels)
3617 {
3618 int c;
3619
3620 /*
3621 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3622 * we need to take that into account (a single channel may take 2
3623 * channel slots if we need to carry a silent channel next to it).
3624 * On Rev3+ AMD codecs this function is not used.
3625 */
3626 int chanpairs = 0;
3627
3628 /* We only produce even-numbered channel count TLVs */
3629 if ((channels % 2) != 0)
3630 return -1;
3631
3632 for (c = 0; c < 7; c += 2) {
3633 if (cap->speakers[c] || cap->speakers[c+1])
3634 chanpairs++;
3635 }
3636
3637 if (chanpairs * 2 != channels)
3638 return -1;
3639
3640 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3641 }
3642
3643 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3644 struct hdac_cea_channel_speaker_allocation *cap,
3645 unsigned int *chmap, int channels)
3646 {
3647 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3648 int count = 0;
3649 int c;
3650
3651 for (c = 7; c >= 0; c--) {
3652 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3653 int spk = cap->speakers[chan];
3654 if (!spk) {
3655 /* add N/A channel if the companion channel is occupied */
3656 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3657 chmap[count++] = SNDRV_CHMAP_NA;
3658
3659 continue;
3660 }
3661
3662 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3663 }
3664
3665 WARN_ON(count != channels);
3666 }
3667
3668 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3669 bool hbr)
3670 {
3671 int hbr_ctl, hbr_ctl_new;
3672
3673 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3674 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3675 if (hbr)
3676 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3677 else
3678 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3679
3680 codec_dbg(codec,
3681 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3682 pin_nid,
3683 hbr_ctl == hbr_ctl_new ? "" : "new-",
3684 hbr_ctl_new);
3685
3686 if (hbr_ctl != hbr_ctl_new)
3687 snd_hda_codec_write(codec, pin_nid, 0,
3688 ATI_VERB_SET_HBR_CONTROL,
3689 hbr_ctl_new);
3690
3691 } else if (hbr)
3692 return -EINVAL;
3693
3694 return 0;
3695 }
3696
3697 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3698 hda_nid_t pin_nid, u32 stream_tag, int format)
3699 {
3700
3701 if (is_amdhdmi_rev3_or_later(codec)) {
3702 int ramp_rate = 180; /* default as per AMD spec */
3703 /* disable ramp-up/down for non-pcm as per AMD spec */
3704 if (format & AC_FMT_TYPE_NON_PCM)
3705 ramp_rate = 0;
3706
3707 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3708 }
3709
3710 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3711 }
3712
3713
3714 static int atihdmi_init(struct hda_codec *codec)
3715 {
3716 struct hdmi_spec *spec = codec->spec;
3717 int pin_idx, err;
3718
3719 err = generic_hdmi_init(codec);
3720
3721 if (err)
3722 return err;
3723
3724 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3725 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3726
3727 /* make sure downmix information in infoframe is zero */
3728 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3729
3730 /* enable channel-wise remap mode if supported */
3731 if (has_amd_full_remap_support(codec))
3732 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3733 ATI_VERB_SET_MULTICHANNEL_MODE,
3734 ATI_MULTICHANNEL_MODE_SINGLE);
3735 }
3736
3737 return 0;
3738 }
3739
3740 static int patch_atihdmi(struct hda_codec *codec)
3741 {
3742 struct hdmi_spec *spec;
3743 struct hdmi_spec_per_cvt *per_cvt;
3744 int err, cvt_idx;
3745
3746 err = patch_generic_hdmi(codec);
3747
3748 if (err)
3749 return err;
3750
3751 codec->patch_ops.init = atihdmi_init;
3752
3753 spec = codec->spec;
3754
3755 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3756 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3757 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3758 spec->ops.setup_stream = atihdmi_setup_stream;
3759
3760 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3761 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3762
3763 if (!has_amd_full_remap_support(codec)) {
3764 /* override to ATI/AMD-specific versions with pairwise mapping */
3765 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3766 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3767 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3768 atihdmi_paired_cea_alloc_to_tlv_chmap;
3769 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3770 }
3771
3772 /* ATI/AMD converters do not advertise all of their capabilities */
3773 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3774 per_cvt = get_cvt(spec, cvt_idx);
3775 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3776 per_cvt->rates |= SUPPORTED_RATES;
3777 per_cvt->formats |= SUPPORTED_FORMATS;
3778 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3779 }
3780
3781 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3782
3783 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
3784 * the link-down as is. Tell the core to allow it.
3785 */
3786 codec->link_down_at_suspend = 1;
3787
3788 return 0;
3789 }
3790
3791 /* VIA HDMI Implementation */
3792 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3793 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3794
3795 static int patch_via_hdmi(struct hda_codec *codec)
3796 {
3797 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3798 }
3799
3800 /*
3801 * patch entries
3802 */
3803 static const struct hda_device_id snd_hda_id_hdmi[] = {
3804 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3805 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3806 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3807 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3808 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3809 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3810 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3811 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3812 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3813 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3814 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3815 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3816 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3817 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3818 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3819 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3820 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3821 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3822 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3823 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3824 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3825 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3826 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3827 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3828 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3829 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3830 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3831 /* 17 is known to be absent */
3832 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3833 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3834 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3835 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3836 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3837 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3838 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3839 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3840 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3841 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
3842 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
3843 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
3844 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
3845 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3846 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3847 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3848 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3849 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3850 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3851 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3852 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3853 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3854 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3855 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3856 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3857 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3858 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3859 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3860 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3861 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3862 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3863 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3864 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3865 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3866 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3867 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3868 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3869 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3870 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3871 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3872 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3873 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3874 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3875 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3876 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3877 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3878 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3879 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3880 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3881 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3882 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3883 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3884 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3885 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3886 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3887 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3888 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3889 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3890 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3891 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3892 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3893 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3894 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3895 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3896 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3897 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3898 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3899 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3900 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3901 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3902 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3903 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3904 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3905 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3906 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3907 /* special ID for generic HDMI */
3908 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3909 {} /* terminator */
3910 };
3911 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3912
3913 MODULE_LICENSE("GPL");
3914 MODULE_DESCRIPTION("HDMI HD-audio codec");
3915 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3916 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3917 MODULE_ALIAS("snd-hda-codec-atihdmi");
3918
3919 static struct hda_codec_driver hdmi_driver = {
3920 .id = snd_hda_id_hdmi,
3921 };
3922
3923 module_hda_codec_driver(hdmi_driver);