3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include "hda_codec.h"
41 #include "hda_local.h"
44 static bool static_hdmi_pcm
;
45 module_param(static_hdmi_pcm
, bool, 0644);
46 MODULE_PARM_DESC(static_hdmi_pcm
, "Don't restrict PCM parameters per ELD info");
48 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
49 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
50 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
51 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
54 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
55 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
56 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
58 struct hdmi_spec_per_cvt
{
61 unsigned int channels_min
;
62 unsigned int channels_max
;
68 /* max. connections to a widget */
69 #define HDA_MAX_CONNECTIONS 32
71 struct hdmi_spec_per_pin
{
74 hda_nid_t mux_nids
[HDA_MAX_CONNECTIONS
];
78 struct hda_codec
*codec
;
79 struct hdmi_eld sink_eld
;
81 struct delayed_work work
;
82 struct snd_kcontrol
*eld_ctl
;
84 bool setup
; /* the stream has been set up by prepare callback */
85 int channels
; /* current number of channels */
87 bool chmap_set
; /* channel-map override by ALSA API? */
88 unsigned char chmap
[8]; /* ALSA API channel-map */
90 struct snd_info_entry
*proc_entry
;
94 struct cea_channel_speaker_allocation
;
96 /* operations used by generic code that can be overridden by patches */
98 int (*pin_get_eld
)(struct hda_codec
*codec
, hda_nid_t pin_nid
,
99 unsigned char *buf
, int *eld_size
);
101 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
102 int (*pin_get_slot_channel
)(struct hda_codec
*codec
, hda_nid_t pin_nid
,
104 int (*pin_set_slot_channel
)(struct hda_codec
*codec
, hda_nid_t pin_nid
,
105 int asp_slot
, int channel
);
107 void (*pin_setup_infoframe
)(struct hda_codec
*codec
, hda_nid_t pin_nid
,
108 int ca
, int active_channels
, int conn_type
);
110 /* enable/disable HBR (HD passthrough) */
111 int (*pin_hbr_setup
)(struct hda_codec
*codec
, hda_nid_t pin_nid
, bool hbr
);
113 int (*setup_stream
)(struct hda_codec
*codec
, hda_nid_t cvt_nid
,
114 hda_nid_t pin_nid
, u32 stream_tag
, int format
);
116 /* Helpers for producing the channel map TLVs. These can be overridden
117 * for devices that have non-standard mapping requirements. */
118 int (*chmap_cea_alloc_validate_get_type
)(struct cea_channel_speaker_allocation
*cap
,
120 void (*cea_alloc_to_tlv_chmap
)(struct cea_channel_speaker_allocation
*cap
,
121 unsigned int *chmap
, int channels
);
123 /* check that the user-given chmap is supported */
124 int (*chmap_validate
)(int ca
, int channels
, unsigned char *chmap
);
129 struct snd_array cvts
; /* struct hdmi_spec_per_cvt */
130 hda_nid_t cvt_nids
[4]; /* only for haswell fix */
133 struct snd_array pins
; /* struct hdmi_spec_per_pin */
134 struct hda_pcm
*pcm_rec
[16];
135 unsigned int channels_max
; /* max over all cvts */
137 struct hdmi_eld temp_eld
;
143 * Non-generic VIA/NVIDIA specific
145 struct hda_multi_out multiout
;
146 struct hda_pcm_stream pcm_playback
;
150 struct hdmi_audio_infoframe
{
157 u8 CC02_CT47
; /* CC in bits 0:2, CT in 4:7 */
161 u8 LFEPBL01_LSV36_DM_INH7
;
164 struct dp_audio_infoframe
{
167 u8 ver
; /* 0x11 << 2 */
169 u8 CC02_CT47
; /* match with HDMI infoframe from this on */
173 u8 LFEPBL01_LSV36_DM_INH7
;
176 union audio_infoframe
{
177 struct hdmi_audio_infoframe hdmi
;
178 struct dp_audio_infoframe dp
;
183 * CEA speaker placement:
186 * FLW FL FLC FC FRC FR FRW
193 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
194 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
196 enum cea_speaker_placement
{
197 FL
= (1 << 0), /* Front Left */
198 FC
= (1 << 1), /* Front Center */
199 FR
= (1 << 2), /* Front Right */
200 FLC
= (1 << 3), /* Front Left Center */
201 FRC
= (1 << 4), /* Front Right Center */
202 RL
= (1 << 5), /* Rear Left */
203 RC
= (1 << 6), /* Rear Center */
204 RR
= (1 << 7), /* Rear Right */
205 RLC
= (1 << 8), /* Rear Left Center */
206 RRC
= (1 << 9), /* Rear Right Center */
207 LFE
= (1 << 10), /* Low Frequency Effect */
208 FLW
= (1 << 11), /* Front Left Wide */
209 FRW
= (1 << 12), /* Front Right Wide */
210 FLH
= (1 << 13), /* Front Left High */
211 FCH
= (1 << 14), /* Front Center High */
212 FRH
= (1 << 15), /* Front Right High */
213 TC
= (1 << 16), /* Top Center */
217 * ELD SA bits in the CEA Speaker Allocation data block
219 static int eld_speaker_allocation_bits
[] = {
227 /* the following are not defined in ELD yet */
234 struct cea_channel_speaker_allocation
{
238 /* derived values, just for convenience */
246 * surround40 surround41 surround50 surround51 surround71
247 * ch0 front left = = = =
248 * ch1 front right = = = =
249 * ch2 rear left = = = =
250 * ch3 rear right = = = =
251 * ch4 LFE center center center
256 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
258 static int hdmi_channel_mapping
[0x32][8] = {
260 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
262 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
264 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
266 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
268 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
270 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
272 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
274 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
276 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
280 * This is an ordered list!
282 * The preceding ones have better chances to be selected by
283 * hdmi_channel_allocation().
285 static struct cea_channel_speaker_allocation channel_allocations
[] = {
286 /* channel: 7 6 5 4 3 2 1 0 */
287 { .ca_index
= 0x00, .speakers
= { 0, 0, 0, 0, 0, 0, FR
, FL
} },
289 { .ca_index
= 0x01, .speakers
= { 0, 0, 0, 0, 0, LFE
, FR
, FL
} },
291 { .ca_index
= 0x02, .speakers
= { 0, 0, 0, 0, FC
, 0, FR
, FL
} },
293 { .ca_index
= 0x08, .speakers
= { 0, 0, RR
, RL
, 0, 0, FR
, FL
} },
295 { .ca_index
= 0x09, .speakers
= { 0, 0, RR
, RL
, 0, LFE
, FR
, FL
} },
297 { .ca_index
= 0x0a, .speakers
= { 0, 0, RR
, RL
, FC
, 0, FR
, FL
} },
299 { .ca_index
= 0x0b, .speakers
= { 0, 0, RR
, RL
, FC
, LFE
, FR
, FL
} },
301 { .ca_index
= 0x0f, .speakers
= { 0, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
303 { .ca_index
= 0x13, .speakers
= { RRC
, RLC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
305 { .ca_index
= 0x03, .speakers
= { 0, 0, 0, 0, FC
, LFE
, FR
, FL
} },
306 { .ca_index
= 0x04, .speakers
= { 0, 0, 0, RC
, 0, 0, FR
, FL
} },
307 { .ca_index
= 0x05, .speakers
= { 0, 0, 0, RC
, 0, LFE
, FR
, FL
} },
308 { .ca_index
= 0x06, .speakers
= { 0, 0, 0, RC
, FC
, 0, FR
, FL
} },
309 { .ca_index
= 0x07, .speakers
= { 0, 0, 0, RC
, FC
, LFE
, FR
, FL
} },
310 { .ca_index
= 0x0c, .speakers
= { 0, RC
, RR
, RL
, 0, 0, FR
, FL
} },
311 { .ca_index
= 0x0d, .speakers
= { 0, RC
, RR
, RL
, 0, LFE
, FR
, FL
} },
312 { .ca_index
= 0x0e, .speakers
= { 0, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
313 { .ca_index
= 0x10, .speakers
= { RRC
, RLC
, RR
, RL
, 0, 0, FR
, FL
} },
314 { .ca_index
= 0x11, .speakers
= { RRC
, RLC
, RR
, RL
, 0, LFE
, FR
, FL
} },
315 { .ca_index
= 0x12, .speakers
= { RRC
, RLC
, RR
, RL
, FC
, 0, FR
, FL
} },
316 { .ca_index
= 0x14, .speakers
= { FRC
, FLC
, 0, 0, 0, 0, FR
, FL
} },
317 { .ca_index
= 0x15, .speakers
= { FRC
, FLC
, 0, 0, 0, LFE
, FR
, FL
} },
318 { .ca_index
= 0x16, .speakers
= { FRC
, FLC
, 0, 0, FC
, 0, FR
, FL
} },
319 { .ca_index
= 0x17, .speakers
= { FRC
, FLC
, 0, 0, FC
, LFE
, FR
, FL
} },
320 { .ca_index
= 0x18, .speakers
= { FRC
, FLC
, 0, RC
, 0, 0, FR
, FL
} },
321 { .ca_index
= 0x19, .speakers
= { FRC
, FLC
, 0, RC
, 0, LFE
, FR
, FL
} },
322 { .ca_index
= 0x1a, .speakers
= { FRC
, FLC
, 0, RC
, FC
, 0, FR
, FL
} },
323 { .ca_index
= 0x1b, .speakers
= { FRC
, FLC
, 0, RC
, FC
, LFE
, FR
, FL
} },
324 { .ca_index
= 0x1c, .speakers
= { FRC
, FLC
, RR
, RL
, 0, 0, FR
, FL
} },
325 { .ca_index
= 0x1d, .speakers
= { FRC
, FLC
, RR
, RL
, 0, LFE
, FR
, FL
} },
326 { .ca_index
= 0x1e, .speakers
= { FRC
, FLC
, RR
, RL
, FC
, 0, FR
, FL
} },
327 { .ca_index
= 0x1f, .speakers
= { FRC
, FLC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
328 { .ca_index
= 0x20, .speakers
= { 0, FCH
, RR
, RL
, FC
, 0, FR
, FL
} },
329 { .ca_index
= 0x21, .speakers
= { 0, FCH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
330 { .ca_index
= 0x22, .speakers
= { TC
, 0, RR
, RL
, FC
, 0, FR
, FL
} },
331 { .ca_index
= 0x23, .speakers
= { TC
, 0, RR
, RL
, FC
, LFE
, FR
, FL
} },
332 { .ca_index
= 0x24, .speakers
= { FRH
, FLH
, RR
, RL
, 0, 0, FR
, FL
} },
333 { .ca_index
= 0x25, .speakers
= { FRH
, FLH
, RR
, RL
, 0, LFE
, FR
, FL
} },
334 { .ca_index
= 0x26, .speakers
= { FRW
, FLW
, RR
, RL
, 0, 0, FR
, FL
} },
335 { .ca_index
= 0x27, .speakers
= { FRW
, FLW
, RR
, RL
, 0, LFE
, FR
, FL
} },
336 { .ca_index
= 0x28, .speakers
= { TC
, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
337 { .ca_index
= 0x29, .speakers
= { TC
, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
338 { .ca_index
= 0x2a, .speakers
= { FCH
, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
339 { .ca_index
= 0x2b, .speakers
= { FCH
, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
340 { .ca_index
= 0x2c, .speakers
= { TC
, FCH
, RR
, RL
, FC
, 0, FR
, FL
} },
341 { .ca_index
= 0x2d, .speakers
= { TC
, FCH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
342 { .ca_index
= 0x2e, .speakers
= { FRH
, FLH
, RR
, RL
, FC
, 0, FR
, FL
} },
343 { .ca_index
= 0x2f, .speakers
= { FRH
, FLH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
344 { .ca_index
= 0x30, .speakers
= { FRW
, FLW
, RR
, RL
, FC
, 0, FR
, FL
} },
345 { .ca_index
= 0x31, .speakers
= { FRW
, FLW
, RR
, RL
, FC
, LFE
, FR
, FL
} },
353 #define get_pin(spec, idx) \
354 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
355 #define get_cvt(spec, idx) \
356 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
357 #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
359 static int pin_nid_to_pin_index(struct hda_codec
*codec
, hda_nid_t pin_nid
)
361 struct hdmi_spec
*spec
= codec
->spec
;
364 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++)
365 if (get_pin(spec
, pin_idx
)->pin_nid
== pin_nid
)
368 codec_warn(codec
, "HDMI: pin nid %d not registered\n", pin_nid
);
372 static int hinfo_to_pin_index(struct hda_codec
*codec
,
373 struct hda_pcm_stream
*hinfo
)
375 struct hdmi_spec
*spec
= codec
->spec
;
378 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++)
379 if (get_pcm_rec(spec
, pin_idx
)->stream
== hinfo
)
382 codec_warn(codec
, "HDMI: hinfo %p not registered\n", hinfo
);
386 static int cvt_nid_to_cvt_index(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
388 struct hdmi_spec
*spec
= codec
->spec
;
391 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++)
392 if (get_cvt(spec
, cvt_idx
)->cvt_nid
== cvt_nid
)
395 codec_warn(codec
, "HDMI: cvt nid %d not registered\n", cvt_nid
);
399 static int hdmi_eld_ctl_info(struct snd_kcontrol
*kcontrol
,
400 struct snd_ctl_elem_info
*uinfo
)
402 struct hda_codec
*codec
= snd_kcontrol_chip(kcontrol
);
403 struct hdmi_spec
*spec
= codec
->spec
;
404 struct hdmi_spec_per_pin
*per_pin
;
405 struct hdmi_eld
*eld
;
408 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
410 pin_idx
= kcontrol
->private_value
;
411 per_pin
= get_pin(spec
, pin_idx
);
412 eld
= &per_pin
->sink_eld
;
414 mutex_lock(&per_pin
->lock
);
415 uinfo
->count
= eld
->eld_valid
? eld
->eld_size
: 0;
416 mutex_unlock(&per_pin
->lock
);
421 static int hdmi_eld_ctl_get(struct snd_kcontrol
*kcontrol
,
422 struct snd_ctl_elem_value
*ucontrol
)
424 struct hda_codec
*codec
= snd_kcontrol_chip(kcontrol
);
425 struct hdmi_spec
*spec
= codec
->spec
;
426 struct hdmi_spec_per_pin
*per_pin
;
427 struct hdmi_eld
*eld
;
430 pin_idx
= kcontrol
->private_value
;
431 per_pin
= get_pin(spec
, pin_idx
);
432 eld
= &per_pin
->sink_eld
;
434 mutex_lock(&per_pin
->lock
);
435 if (eld
->eld_size
> ARRAY_SIZE(ucontrol
->value
.bytes
.data
)) {
436 mutex_unlock(&per_pin
->lock
);
441 memset(ucontrol
->value
.bytes
.data
, 0,
442 ARRAY_SIZE(ucontrol
->value
.bytes
.data
));
444 memcpy(ucontrol
->value
.bytes
.data
, eld
->eld_buffer
,
446 mutex_unlock(&per_pin
->lock
);
451 static struct snd_kcontrol_new eld_bytes_ctl
= {
452 .access
= SNDRV_CTL_ELEM_ACCESS_READ
| SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
453 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
455 .info
= hdmi_eld_ctl_info
,
456 .get
= hdmi_eld_ctl_get
,
459 static int hdmi_create_eld_ctl(struct hda_codec
*codec
, int pin_idx
,
462 struct snd_kcontrol
*kctl
;
463 struct hdmi_spec
*spec
= codec
->spec
;
466 kctl
= snd_ctl_new1(&eld_bytes_ctl
, codec
);
469 kctl
->private_value
= pin_idx
;
470 kctl
->id
.device
= device
;
472 err
= snd_hda_ctl_add(codec
, get_pin(spec
, pin_idx
)->pin_nid
, kctl
);
476 get_pin(spec
, pin_idx
)->eld_ctl
= kctl
;
481 static void hdmi_get_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
482 int *packet_index
, int *byte_index
)
486 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
487 AC_VERB_GET_HDMI_DIP_INDEX
, 0);
489 *packet_index
= val
>> 5;
490 *byte_index
= val
& 0x1f;
494 static void hdmi_set_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
495 int packet_index
, int byte_index
)
499 val
= (packet_index
<< 5) | (byte_index
& 0x1f);
501 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_INDEX
, val
);
504 static void hdmi_write_dip_byte(struct hda_codec
*codec
, hda_nid_t pin_nid
,
507 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_DATA
, val
);
510 static void hdmi_init_pin(struct hda_codec
*codec
, hda_nid_t pin_nid
)
512 struct hdmi_spec
*spec
= codec
->spec
;
516 if (get_wcaps(codec
, pin_nid
) & AC_WCAP_OUT_AMP
)
517 snd_hda_codec_write(codec
, pin_nid
, 0,
518 AC_VERB_SET_AMP_GAIN_MUTE
, AMP_OUT_UNMUTE
);
520 if (spec
->dyn_pin_out
)
521 /* Disable pin out until stream is active */
524 /* Enable pin out: some machines with GM965 gets broken output
525 * when the pin is disabled or changed while using with HDMI
529 snd_hda_codec_write(codec
, pin_nid
, 0,
530 AC_VERB_SET_PIN_WIDGET_CONTROL
, pin_out
);
533 static int hdmi_get_channel_count(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
535 return 1 + snd_hda_codec_read(codec
, cvt_nid
, 0,
536 AC_VERB_GET_CVT_CHAN_COUNT
, 0);
539 static void hdmi_set_channel_count(struct hda_codec
*codec
,
540 hda_nid_t cvt_nid
, int chs
)
542 if (chs
!= hdmi_get_channel_count(codec
, cvt_nid
))
543 snd_hda_codec_write(codec
, cvt_nid
, 0,
544 AC_VERB_SET_CVT_CHAN_COUNT
, chs
- 1);
551 #ifdef CONFIG_PROC_FS
552 static void print_eld_info(struct snd_info_entry
*entry
,
553 struct snd_info_buffer
*buffer
)
555 struct hdmi_spec_per_pin
*per_pin
= entry
->private_data
;
557 mutex_lock(&per_pin
->lock
);
558 snd_hdmi_print_eld_info(&per_pin
->sink_eld
, buffer
);
559 mutex_unlock(&per_pin
->lock
);
562 static void write_eld_info(struct snd_info_entry
*entry
,
563 struct snd_info_buffer
*buffer
)
565 struct hdmi_spec_per_pin
*per_pin
= entry
->private_data
;
567 mutex_lock(&per_pin
->lock
);
568 snd_hdmi_write_eld_info(&per_pin
->sink_eld
, buffer
);
569 mutex_unlock(&per_pin
->lock
);
572 static int eld_proc_new(struct hdmi_spec_per_pin
*per_pin
, int index
)
575 struct hda_codec
*codec
= per_pin
->codec
;
576 struct snd_info_entry
*entry
;
579 snprintf(name
, sizeof(name
), "eld#%d.%d", codec
->addr
, index
);
580 err
= snd_card_proc_new(codec
->card
, name
, &entry
);
584 snd_info_set_text_ops(entry
, per_pin
, print_eld_info
);
585 entry
->c
.text
.write
= write_eld_info
;
586 entry
->mode
|= S_IWUSR
;
587 per_pin
->proc_entry
= entry
;
592 static void eld_proc_free(struct hdmi_spec_per_pin
*per_pin
)
594 if (!per_pin
->codec
->bus
->shutdown
&& per_pin
->proc_entry
) {
595 snd_info_free_entry(per_pin
->proc_entry
);
596 per_pin
->proc_entry
= NULL
;
600 static inline int eld_proc_new(struct hdmi_spec_per_pin
*per_pin
,
605 static inline void eld_proc_free(struct hdmi_spec_per_pin
*per_pin
)
611 * Channel mapping routines
615 * Compute derived values in channel_allocations[].
617 static void init_channel_allocations(void)
620 struct cea_channel_speaker_allocation
*p
;
622 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
623 p
= channel_allocations
+ i
;
626 for (j
= 0; j
< ARRAY_SIZE(p
->speakers
); j
++)
627 if (p
->speakers
[j
]) {
629 p
->spk_mask
|= p
->speakers
[j
];
634 static int get_channel_allocation_order(int ca
)
638 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
639 if (channel_allocations
[i
].ca_index
== ca
)
646 * The transformation takes two steps:
648 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
649 * spk_mask => (channel_allocations[]) => ai->CA
651 * TODO: it could select the wrong CA from multiple candidates.
653 static int hdmi_channel_allocation(struct hda_codec
*codec
,
654 struct hdmi_eld
*eld
, int channels
)
659 char buf
[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE
];
662 * CA defaults to 0 for basic stereo audio
668 * expand ELD's speaker allocation mask
670 * ELD tells the speaker mask in a compact(paired) form,
671 * expand ELD's notions to match the ones used by Audio InfoFrame.
673 for (i
= 0; i
< ARRAY_SIZE(eld_speaker_allocation_bits
); i
++) {
674 if (eld
->info
.spk_alloc
& (1 << i
))
675 spk_mask
|= eld_speaker_allocation_bits
[i
];
678 /* search for the first working match in the CA table */
679 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
680 if (channels
== channel_allocations
[i
].channels
&&
681 (spk_mask
& channel_allocations
[i
].spk_mask
) ==
682 channel_allocations
[i
].spk_mask
) {
683 ca
= channel_allocations
[i
].ca_index
;
689 /* if there was no match, select the regular ALSA channel
690 * allocation with the matching number of channels */
691 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
692 if (channels
== channel_allocations
[i
].channels
) {
693 ca
= channel_allocations
[i
].ca_index
;
699 snd_print_channel_allocation(eld
->info
.spk_alloc
, buf
, sizeof(buf
));
700 codec_dbg(codec
, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
706 static void hdmi_debug_channel_mapping(struct hda_codec
*codec
,
709 #ifdef CONFIG_SND_DEBUG_VERBOSE
710 struct hdmi_spec
*spec
= codec
->spec
;
714 for (i
= 0; i
< 8; i
++) {
715 channel
= spec
->ops
.pin_get_slot_channel(codec
, pin_nid
, i
);
716 codec_dbg(codec
, "HDMI: ASP channel %d => slot %d\n",
722 static void hdmi_std_setup_channel_mapping(struct hda_codec
*codec
,
727 struct hdmi_spec
*spec
= codec
->spec
;
728 struct cea_channel_speaker_allocation
*ch_alloc
;
732 int non_pcm_mapping
[8];
734 order
= get_channel_allocation_order(ca
);
735 ch_alloc
= &channel_allocations
[order
];
737 if (hdmi_channel_mapping
[ca
][1] == 0) {
739 /* fill actual channel mappings in ALSA channel (i) order */
740 for (i
= 0; i
< ch_alloc
->channels
; i
++) {
741 while (!ch_alloc
->speakers
[7 - hdmi_slot
] && !WARN_ON(hdmi_slot
>= 8))
742 hdmi_slot
++; /* skip zero slots */
744 hdmi_channel_mapping
[ca
][i
] = (i
<< 4) | hdmi_slot
++;
746 /* fill the rest of the slots with ALSA channel 0xf */
747 for (hdmi_slot
= 0; hdmi_slot
< 8; hdmi_slot
++)
748 if (!ch_alloc
->speakers
[7 - hdmi_slot
])
749 hdmi_channel_mapping
[ca
][i
++] = (0xf << 4) | hdmi_slot
;
753 for (i
= 0; i
< ch_alloc
->channels
; i
++)
754 non_pcm_mapping
[i
] = (i
<< 4) | i
;
756 non_pcm_mapping
[i
] = (0xf << 4) | i
;
759 for (i
= 0; i
< 8; i
++) {
760 int slotsetup
= non_pcm
? non_pcm_mapping
[i
] : hdmi_channel_mapping
[ca
][i
];
761 int hdmi_slot
= slotsetup
& 0x0f;
762 int channel
= (slotsetup
& 0xf0) >> 4;
763 err
= spec
->ops
.pin_set_slot_channel(codec
, pin_nid
, hdmi_slot
, channel
);
765 codec_dbg(codec
, "HDMI: channel mapping failed\n");
771 struct channel_map_table
{
772 unsigned char map
; /* ALSA API channel map position */
773 int spk_mask
; /* speaker position bit mask */
776 static struct channel_map_table map_tables
[] = {
777 { SNDRV_CHMAP_FL
, FL
},
778 { SNDRV_CHMAP_FR
, FR
},
779 { SNDRV_CHMAP_RL
, RL
},
780 { SNDRV_CHMAP_RR
, RR
},
781 { SNDRV_CHMAP_LFE
, LFE
},
782 { SNDRV_CHMAP_FC
, FC
},
783 { SNDRV_CHMAP_RLC
, RLC
},
784 { SNDRV_CHMAP_RRC
, RRC
},
785 { SNDRV_CHMAP_RC
, RC
},
786 { SNDRV_CHMAP_FLC
, FLC
},
787 { SNDRV_CHMAP_FRC
, FRC
},
788 { SNDRV_CHMAP_TFL
, FLH
},
789 { SNDRV_CHMAP_TFR
, FRH
},
790 { SNDRV_CHMAP_FLW
, FLW
},
791 { SNDRV_CHMAP_FRW
, FRW
},
792 { SNDRV_CHMAP_TC
, TC
},
793 { SNDRV_CHMAP_TFC
, FCH
},
797 /* from ALSA API channel position to speaker bit mask */
798 static int to_spk_mask(unsigned char c
)
800 struct channel_map_table
*t
= map_tables
;
801 for (; t
->map
; t
++) {
808 /* from ALSA API channel position to CEA slot */
809 static int to_cea_slot(int ordered_ca
, unsigned char pos
)
811 int mask
= to_spk_mask(pos
);
815 for (i
= 0; i
< 8; i
++) {
816 if (channel_allocations
[ordered_ca
].speakers
[7 - i
] == mask
)
824 /* from speaker bit mask to ALSA API channel position */
825 static int spk_to_chmap(int spk
)
827 struct channel_map_table
*t
= map_tables
;
828 for (; t
->map
; t
++) {
829 if (t
->spk_mask
== spk
)
835 /* from CEA slot to ALSA API channel position */
836 static int from_cea_slot(int ordered_ca
, unsigned char slot
)
838 int mask
= channel_allocations
[ordered_ca
].speakers
[7 - slot
];
840 return spk_to_chmap(mask
);
843 /* get the CA index corresponding to the given ALSA API channel map */
844 static int hdmi_manual_channel_allocation(int chs
, unsigned char *map
)
846 int i
, spks
= 0, spk_mask
= 0;
848 for (i
= 0; i
< chs
; i
++) {
849 int mask
= to_spk_mask(map
[i
]);
856 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
857 if ((chs
== channel_allocations
[i
].channels
||
858 spks
== channel_allocations
[i
].channels
) &&
859 (spk_mask
& channel_allocations
[i
].spk_mask
) ==
860 channel_allocations
[i
].spk_mask
)
861 return channel_allocations
[i
].ca_index
;
866 /* set up the channel slots for the given ALSA API channel map */
867 static int hdmi_manual_setup_channel_mapping(struct hda_codec
*codec
,
869 int chs
, unsigned char *map
,
872 struct hdmi_spec
*spec
= codec
->spec
;
873 int ordered_ca
= get_channel_allocation_order(ca
);
874 int alsa_pos
, hdmi_slot
;
875 int assignments
[8] = {[0 ... 7] = 0xf};
877 for (alsa_pos
= 0; alsa_pos
< chs
; alsa_pos
++) {
879 hdmi_slot
= to_cea_slot(ordered_ca
, map
[alsa_pos
]);
882 continue; /* unassigned channel */
884 assignments
[hdmi_slot
] = alsa_pos
;
887 for (hdmi_slot
= 0; hdmi_slot
< 8; hdmi_slot
++) {
890 err
= spec
->ops
.pin_set_slot_channel(codec
, pin_nid
, hdmi_slot
,
891 assignments
[hdmi_slot
]);
898 /* store ALSA API channel map from the current default map */
899 static void hdmi_setup_fake_chmap(unsigned char *map
, int ca
)
902 int ordered_ca
= get_channel_allocation_order(ca
);
903 for (i
= 0; i
< 8; i
++) {
904 if (i
< channel_allocations
[ordered_ca
].channels
)
905 map
[i
] = from_cea_slot(ordered_ca
, hdmi_channel_mapping
[ca
][i
] & 0x0f);
911 static void hdmi_setup_channel_mapping(struct hda_codec
*codec
,
912 hda_nid_t pin_nid
, bool non_pcm
, int ca
,
913 int channels
, unsigned char *map
,
916 if (!non_pcm
&& chmap_set
) {
917 hdmi_manual_setup_channel_mapping(codec
, pin_nid
,
920 hdmi_std_setup_channel_mapping(codec
, pin_nid
, non_pcm
, ca
);
921 hdmi_setup_fake_chmap(map
, ca
);
924 hdmi_debug_channel_mapping(codec
, pin_nid
);
927 static int hdmi_pin_set_slot_channel(struct hda_codec
*codec
, hda_nid_t pin_nid
,
928 int asp_slot
, int channel
)
930 return snd_hda_codec_write(codec
, pin_nid
, 0,
931 AC_VERB_SET_HDMI_CHAN_SLOT
,
932 (channel
<< 4) | asp_slot
);
935 static int hdmi_pin_get_slot_channel(struct hda_codec
*codec
, hda_nid_t pin_nid
,
938 return (snd_hda_codec_read(codec
, pin_nid
, 0,
939 AC_VERB_GET_HDMI_CHAN_SLOT
,
940 asp_slot
) & 0xf0) >> 4;
944 * Audio InfoFrame routines
948 * Enable Audio InfoFrame Transmission
950 static void hdmi_start_infoframe_trans(struct hda_codec
*codec
,
953 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
954 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
959 * Disable Audio InfoFrame Transmission
961 static void hdmi_stop_infoframe_trans(struct hda_codec
*codec
,
964 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
965 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
969 static void hdmi_debug_dip_size(struct hda_codec
*codec
, hda_nid_t pin_nid
)
971 #ifdef CONFIG_SND_DEBUG_VERBOSE
975 size
= snd_hdmi_get_eld_size(codec
, pin_nid
);
976 codec_dbg(codec
, "HDMI: ELD buf size is %d\n", size
);
978 for (i
= 0; i
< 8; i
++) {
979 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
980 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
981 codec_dbg(codec
, "HDMI: DIP GP[%d] buf size is %d\n", i
, size
);
986 static void hdmi_clear_dip_buffers(struct hda_codec
*codec
, hda_nid_t pin_nid
)
992 for (i
= 0; i
< 8; i
++) {
993 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
994 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
998 hdmi_set_dip_index(codec
, pin_nid
, i
, 0x0);
999 for (j
= 1; j
< 1000; j
++) {
1000 hdmi_write_dip_byte(codec
, pin_nid
, 0x0);
1001 hdmi_get_dip_index(codec
, pin_nid
, &pi
, &bi
);
1003 codec_dbg(codec
, "dip index %d: %d != %d\n",
1005 if (bi
== 0) /* byte index wrapped around */
1009 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1015 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe
*hdmi_ai
)
1017 u8
*bytes
= (u8
*)hdmi_ai
;
1021 hdmi_ai
->checksum
= 0;
1023 for (i
= 0; i
< sizeof(*hdmi_ai
); i
++)
1026 hdmi_ai
->checksum
= -sum
;
1029 static void hdmi_fill_audio_infoframe(struct hda_codec
*codec
,
1035 hdmi_debug_dip_size(codec
, pin_nid
);
1036 hdmi_clear_dip_buffers(codec
, pin_nid
); /* be paranoid */
1038 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
1039 for (i
= 0; i
< size
; i
++)
1040 hdmi_write_dip_byte(codec
, pin_nid
, dip
[i
]);
1043 static bool hdmi_infoframe_uptodate(struct hda_codec
*codec
, hda_nid_t pin_nid
,
1049 if (snd_hda_codec_read(codec
, pin_nid
, 0, AC_VERB_GET_HDMI_DIP_XMIT
, 0)
1053 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
1054 for (i
= 0; i
< size
; i
++) {
1055 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
1056 AC_VERB_GET_HDMI_DIP_DATA
, 0);
1064 static void hdmi_pin_setup_infoframe(struct hda_codec
*codec
,
1066 int ca
, int active_channels
,
1069 union audio_infoframe ai
;
1071 memset(&ai
, 0, sizeof(ai
));
1072 if (conn_type
== 0) { /* HDMI */
1073 struct hdmi_audio_infoframe
*hdmi_ai
= &ai
.hdmi
;
1075 hdmi_ai
->type
= 0x84;
1076 hdmi_ai
->ver
= 0x01;
1077 hdmi_ai
->len
= 0x0a;
1078 hdmi_ai
->CC02_CT47
= active_channels
- 1;
1080 hdmi_checksum_audio_infoframe(hdmi_ai
);
1081 } else if (conn_type
== 1) { /* DisplayPort */
1082 struct dp_audio_infoframe
*dp_ai
= &ai
.dp
;
1086 dp_ai
->ver
= 0x11 << 2;
1087 dp_ai
->CC02_CT47
= active_channels
- 1;
1090 codec_dbg(codec
, "HDMI: unknown connection type at pin %d\n",
1096 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1097 * sizeof(*dp_ai) to avoid partial match/update problems when
1098 * the user switches between HDMI/DP monitors.
1100 if (!hdmi_infoframe_uptodate(codec
, pin_nid
, ai
.bytes
,
1103 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1105 active_channels
, ca
);
1106 hdmi_stop_infoframe_trans(codec
, pin_nid
);
1107 hdmi_fill_audio_infoframe(codec
, pin_nid
,
1108 ai
.bytes
, sizeof(ai
));
1109 hdmi_start_infoframe_trans(codec
, pin_nid
);
1113 static void hdmi_setup_audio_infoframe(struct hda_codec
*codec
,
1114 struct hdmi_spec_per_pin
*per_pin
,
1117 struct hdmi_spec
*spec
= codec
->spec
;
1118 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1119 int channels
= per_pin
->channels
;
1120 int active_channels
;
1121 struct hdmi_eld
*eld
;
1127 if (is_haswell_plus(codec
))
1128 snd_hda_codec_write(codec
, pin_nid
, 0,
1129 AC_VERB_SET_AMP_GAIN_MUTE
,
1132 eld
= &per_pin
->sink_eld
;
1134 if (!non_pcm
&& per_pin
->chmap_set
)
1135 ca
= hdmi_manual_channel_allocation(channels
, per_pin
->chmap
);
1137 ca
= hdmi_channel_allocation(codec
, eld
, channels
);
1141 ordered_ca
= get_channel_allocation_order(ca
);
1142 active_channels
= channel_allocations
[ordered_ca
].channels
;
1144 hdmi_set_channel_count(codec
, per_pin
->cvt_nid
, active_channels
);
1147 * always configure channel mapping, it may have been changed by the
1148 * user in the meantime
1150 hdmi_setup_channel_mapping(codec
, pin_nid
, non_pcm
, ca
,
1151 channels
, per_pin
->chmap
,
1152 per_pin
->chmap_set
);
1154 spec
->ops
.pin_setup_infoframe(codec
, pin_nid
, ca
, active_channels
,
1155 eld
->info
.conn_type
);
1157 per_pin
->non_pcm
= non_pcm
;
1161 * Unsolicited events
1164 static bool hdmi_present_sense(struct hdmi_spec_per_pin
*per_pin
, int repoll
);
1166 static void check_presence_and_report(struct hda_codec
*codec
, hda_nid_t nid
)
1168 struct hdmi_spec
*spec
= codec
->spec
;
1169 int pin_idx
= pin_nid_to_pin_index(codec
, nid
);
1173 if (hdmi_present_sense(get_pin(spec
, pin_idx
), 1))
1174 snd_hda_jack_report_sync(codec
);
1177 static void jack_callback(struct hda_codec
*codec
,
1178 struct hda_jack_callback
*jack
)
1180 check_presence_and_report(codec
, jack
->tbl
->nid
);
1183 static void hdmi_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
1185 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
1186 struct hda_jack_tbl
*jack
;
1187 int dev_entry
= (res
& AC_UNSOL_RES_DE
) >> AC_UNSOL_RES_DE_SHIFT
;
1189 jack
= snd_hda_jack_tbl_get_from_tag(codec
, tag
);
1192 jack
->jack_dirty
= 1;
1195 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1196 codec
->addr
, jack
->nid
, dev_entry
, !!(res
& AC_UNSOL_RES_IA
),
1197 !!(res
& AC_UNSOL_RES_PD
), !!(res
& AC_UNSOL_RES_ELDV
));
1199 check_presence_and_report(codec
, jack
->nid
);
1202 static void hdmi_non_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
1204 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
1205 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
1206 int cp_state
= !!(res
& AC_UNSOL_RES_CP_STATE
);
1207 int cp_ready
= !!(res
& AC_UNSOL_RES_CP_READY
);
1210 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1225 static void hdmi_unsol_event(struct hda_codec
*codec
, unsigned int res
)
1227 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
1228 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
1230 if (!snd_hda_jack_tbl_get_from_tag(codec
, tag
)) {
1231 codec_dbg(codec
, "Unexpected HDMI event tag 0x%x\n", tag
);
1236 hdmi_intrinsic_event(codec
, res
);
1238 hdmi_non_intrinsic_event(codec
, res
);
1241 static void haswell_verify_D0(struct hda_codec
*codec
,
1242 hda_nid_t cvt_nid
, hda_nid_t nid
)
1246 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1247 * thus pins could only choose converter 0 for use. Make sure the
1248 * converters are in correct power state */
1249 if (!snd_hda_check_power_state(codec
, cvt_nid
, AC_PWRST_D0
))
1250 snd_hda_codec_write(codec
, cvt_nid
, 0, AC_VERB_SET_POWER_STATE
, AC_PWRST_D0
);
1252 if (!snd_hda_check_power_state(codec
, nid
, AC_PWRST_D0
)) {
1253 snd_hda_codec_write(codec
, nid
, 0, AC_VERB_SET_POWER_STATE
,
1256 pwr
= snd_hda_codec_read(codec
, nid
, 0, AC_VERB_GET_POWER_STATE
, 0);
1257 pwr
= (pwr
& AC_PWRST_ACTUAL
) >> AC_PWRST_ACTUAL_SHIFT
;
1258 codec_dbg(codec
, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid
, pwr
);
1266 /* HBR should be Non-PCM, 8 channels */
1267 #define is_hbr_format(format) \
1268 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1270 static int hdmi_pin_hbr_setup(struct hda_codec
*codec
, hda_nid_t pin_nid
,
1273 int pinctl
, new_pinctl
;
1275 if (snd_hda_query_pin_caps(codec
, pin_nid
) & AC_PINCAP_HBR
) {
1276 pinctl
= snd_hda_codec_read(codec
, pin_nid
, 0,
1277 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
1280 return hbr
? -EINVAL
: 0;
1282 new_pinctl
= pinctl
& ~AC_PINCTL_EPT
;
1284 new_pinctl
|= AC_PINCTL_EPT_HBR
;
1286 new_pinctl
|= AC_PINCTL_EPT_NATIVE
;
1289 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1291 pinctl
== new_pinctl
? "" : "new-",
1294 if (pinctl
!= new_pinctl
)
1295 snd_hda_codec_write(codec
, pin_nid
, 0,
1296 AC_VERB_SET_PIN_WIDGET_CONTROL
,
1304 static int hdmi_setup_stream(struct hda_codec
*codec
, hda_nid_t cvt_nid
,
1305 hda_nid_t pin_nid
, u32 stream_tag
, int format
)
1307 struct hdmi_spec
*spec
= codec
->spec
;
1310 if (is_haswell_plus(codec
))
1311 haswell_verify_D0(codec
, cvt_nid
, pin_nid
);
1313 err
= spec
->ops
.pin_hbr_setup(codec
, pin_nid
, is_hbr_format(format
));
1316 codec_dbg(codec
, "hdmi_setup_stream: HBR is not supported\n");
1320 snd_hda_codec_setup_stream(codec
, cvt_nid
, stream_tag
, 0, format
);
1324 static int hdmi_choose_cvt(struct hda_codec
*codec
,
1325 int pin_idx
, int *cvt_id
, int *mux_id
)
1327 struct hdmi_spec
*spec
= codec
->spec
;
1328 struct hdmi_spec_per_pin
*per_pin
;
1329 struct hdmi_spec_per_cvt
*per_cvt
= NULL
;
1330 int cvt_idx
, mux_idx
= 0;
1332 per_pin
= get_pin(spec
, pin_idx
);
1334 /* Dynamically assign converter to stream */
1335 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++) {
1336 per_cvt
= get_cvt(spec
, cvt_idx
);
1338 /* Must not already be assigned */
1339 if (per_cvt
->assigned
)
1341 /* Must be in pin's mux's list of converters */
1342 for (mux_idx
= 0; mux_idx
< per_pin
->num_mux_nids
; mux_idx
++)
1343 if (per_pin
->mux_nids
[mux_idx
] == per_cvt
->cvt_nid
)
1345 /* Not in mux list */
1346 if (mux_idx
== per_pin
->num_mux_nids
)
1351 /* No free converters */
1352 if (cvt_idx
== spec
->num_cvts
)
1355 per_pin
->mux_idx
= mux_idx
;
1365 /* Assure the pin select the right convetor */
1366 static void intel_verify_pin_cvt_connect(struct hda_codec
*codec
,
1367 struct hdmi_spec_per_pin
*per_pin
)
1369 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1372 mux_idx
= per_pin
->mux_idx
;
1373 curr
= snd_hda_codec_read(codec
, pin_nid
, 0,
1374 AC_VERB_GET_CONNECT_SEL
, 0);
1375 if (curr
!= mux_idx
)
1376 snd_hda_codec_write_cache(codec
, pin_nid
, 0,
1377 AC_VERB_SET_CONNECT_SEL
,
1381 /* Intel HDMI workaround to fix audio routing issue:
1382 * For some Intel display codecs, pins share the same connection list.
1383 * So a conveter can be selected by multiple pins and playback on any of these
1384 * pins will generate sound on the external display, because audio flows from
1385 * the same converter to the display pipeline. Also muting one pin may make
1386 * other pins have no sound output.
1387 * So this function assures that an assigned converter for a pin is not selected
1388 * by any other pins.
1390 static void intel_not_share_assigned_cvt(struct hda_codec
*codec
,
1391 hda_nid_t pin_nid
, int mux_idx
)
1393 struct hdmi_spec
*spec
= codec
->spec
;
1396 struct hdmi_spec_per_cvt
*per_cvt
;
1398 /* configure all pins, including "no physical connection" ones */
1399 for_each_hda_codec_node(nid
, codec
) {
1400 unsigned int wid_caps
= get_wcaps(codec
, nid
);
1401 unsigned int wid_type
= get_wcaps_type(wid_caps
);
1403 if (wid_type
!= AC_WID_PIN
)
1409 curr
= snd_hda_codec_read(codec
, nid
, 0,
1410 AC_VERB_GET_CONNECT_SEL
, 0);
1411 if (curr
!= mux_idx
)
1414 /* choose an unassigned converter. The conveters in the
1415 * connection list are in the same order as in the codec.
1417 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++) {
1418 per_cvt
= get_cvt(spec
, cvt_idx
);
1419 if (!per_cvt
->assigned
) {
1421 "choose cvt %d for pin nid %d\n",
1423 snd_hda_codec_write_cache(codec
, nid
, 0,
1424 AC_VERB_SET_CONNECT_SEL
,
1435 static int hdmi_pcm_open(struct hda_pcm_stream
*hinfo
,
1436 struct hda_codec
*codec
,
1437 struct snd_pcm_substream
*substream
)
1439 struct hdmi_spec
*spec
= codec
->spec
;
1440 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1441 int pin_idx
, cvt_idx
, mux_idx
= 0;
1442 struct hdmi_spec_per_pin
*per_pin
;
1443 struct hdmi_eld
*eld
;
1444 struct hdmi_spec_per_cvt
*per_cvt
= NULL
;
1447 /* Validate hinfo */
1448 pin_idx
= hinfo_to_pin_index(codec
, hinfo
);
1449 if (snd_BUG_ON(pin_idx
< 0))
1451 per_pin
= get_pin(spec
, pin_idx
);
1452 eld
= &per_pin
->sink_eld
;
1454 err
= hdmi_choose_cvt(codec
, pin_idx
, &cvt_idx
, &mux_idx
);
1458 per_cvt
= get_cvt(spec
, cvt_idx
);
1459 /* Claim converter */
1460 per_cvt
->assigned
= 1;
1461 per_pin
->cvt_nid
= per_cvt
->cvt_nid
;
1462 hinfo
->nid
= per_cvt
->cvt_nid
;
1464 snd_hda_codec_write_cache(codec
, per_pin
->pin_nid
, 0,
1465 AC_VERB_SET_CONNECT_SEL
,
1468 /* configure unused pins to choose other converters */
1469 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
))
1470 intel_not_share_assigned_cvt(codec
, per_pin
->pin_nid
, mux_idx
);
1472 snd_hda_spdif_ctls_assign(codec
, pin_idx
, per_cvt
->cvt_nid
);
1474 /* Initially set the converter's capabilities */
1475 hinfo
->channels_min
= per_cvt
->channels_min
;
1476 hinfo
->channels_max
= per_cvt
->channels_max
;
1477 hinfo
->rates
= per_cvt
->rates
;
1478 hinfo
->formats
= per_cvt
->formats
;
1479 hinfo
->maxbps
= per_cvt
->maxbps
;
1481 /* Restrict capabilities by ELD if this isn't disabled */
1482 if (!static_hdmi_pcm
&& eld
->eld_valid
) {
1483 snd_hdmi_eld_update_pcm_info(&eld
->info
, hinfo
);
1484 if (hinfo
->channels_min
> hinfo
->channels_max
||
1485 !hinfo
->rates
|| !hinfo
->formats
) {
1486 per_cvt
->assigned
= 0;
1488 snd_hda_spdif_ctls_unassign(codec
, pin_idx
);
1493 /* Store the updated parameters */
1494 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1495 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1496 runtime
->hw
.formats
= hinfo
->formats
;
1497 runtime
->hw
.rates
= hinfo
->rates
;
1499 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
1500 SNDRV_PCM_HW_PARAM_CHANNELS
, 2);
1505 * HDA/HDMI auto parsing
1507 static int hdmi_read_pin_conn(struct hda_codec
*codec
, int pin_idx
)
1509 struct hdmi_spec
*spec
= codec
->spec
;
1510 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
1511 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1513 if (!(get_wcaps(codec
, pin_nid
) & AC_WCAP_CONN_LIST
)) {
1515 "HDMI: pin %d wcaps %#x does not support connection list\n",
1516 pin_nid
, get_wcaps(codec
, pin_nid
));
1520 per_pin
->num_mux_nids
= snd_hda_get_connections(codec
, pin_nid
,
1522 HDA_MAX_CONNECTIONS
);
1527 static bool hdmi_present_sense(struct hdmi_spec_per_pin
*per_pin
, int repoll
)
1529 struct hda_jack_tbl
*jack
;
1530 struct hda_codec
*codec
= per_pin
->codec
;
1531 struct hdmi_spec
*spec
= codec
->spec
;
1532 struct hdmi_eld
*eld
= &spec
->temp_eld
;
1533 struct hdmi_eld
*pin_eld
= &per_pin
->sink_eld
;
1534 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1536 * Always execute a GetPinSense verb here, even when called from
1537 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1538 * response's PD bit is not the real PD value, but indicates that
1539 * the real PD value changed. An older version of the HD-audio
1540 * specification worked this way. Hence, we just ignore the data in
1541 * the unsolicited response to avoid custom WARs.
1544 bool update_eld
= false;
1545 bool eld_changed
= false;
1548 snd_hda_power_up_pm(codec
);
1549 present
= snd_hda_pin_sense(codec
, pin_nid
);
1551 mutex_lock(&per_pin
->lock
);
1552 pin_eld
->monitor_present
= !!(present
& AC_PINSENSE_PRESENCE
);
1553 if (pin_eld
->monitor_present
)
1554 eld
->eld_valid
= !!(present
& AC_PINSENSE_ELDV
);
1556 eld
->eld_valid
= false;
1559 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1560 codec
->addr
, pin_nid
, pin_eld
->monitor_present
, eld
->eld_valid
);
1562 if (eld
->eld_valid
) {
1563 if (spec
->ops
.pin_get_eld(codec
, pin_nid
, eld
->eld_buffer
,
1564 &eld
->eld_size
) < 0)
1565 eld
->eld_valid
= false;
1567 memset(&eld
->info
, 0, sizeof(struct parsed_hdmi_eld
));
1568 if (snd_hdmi_parse_eld(codec
, &eld
->info
, eld
->eld_buffer
,
1570 eld
->eld_valid
= false;
1573 if (eld
->eld_valid
) {
1574 snd_hdmi_show_eld(codec
, &eld
->info
);
1578 schedule_delayed_work(&per_pin
->work
,
1579 msecs_to_jiffies(300));
1584 if (pin_eld
->eld_valid
!= eld
->eld_valid
)
1587 if (pin_eld
->eld_valid
&& !eld
->eld_valid
)
1591 bool old_eld_valid
= pin_eld
->eld_valid
;
1592 pin_eld
->eld_valid
= eld
->eld_valid
;
1593 if (pin_eld
->eld_size
!= eld
->eld_size
||
1594 memcmp(pin_eld
->eld_buffer
, eld
->eld_buffer
,
1595 eld
->eld_size
) != 0) {
1596 memcpy(pin_eld
->eld_buffer
, eld
->eld_buffer
,
1600 pin_eld
->eld_size
= eld
->eld_size
;
1601 pin_eld
->info
= eld
->info
;
1604 * Re-setup pin and infoframe. This is needed e.g. when
1605 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1606 * - transcoder can change during stream playback on Haswell
1607 * and this can make HW reset converter selection on a pin.
1609 if (eld
->eld_valid
&& !old_eld_valid
&& per_pin
->setup
) {
1610 if (is_haswell_plus(codec
) ||
1611 is_valleyview_plus(codec
)) {
1612 intel_verify_pin_cvt_connect(codec
, per_pin
);
1613 intel_not_share_assigned_cvt(codec
, pin_nid
,
1617 hdmi_setup_audio_infoframe(codec
, per_pin
,
1623 snd_ctl_notify(codec
->card
,
1624 SNDRV_CTL_EVENT_MASK_VALUE
| SNDRV_CTL_EVENT_MASK_INFO
,
1625 &per_pin
->eld_ctl
->id
);
1627 ret
= !repoll
|| !pin_eld
->monitor_present
|| pin_eld
->eld_valid
;
1629 jack
= snd_hda_jack_tbl_get(codec
, pin_nid
);
1631 jack
->block_report
= !ret
;
1633 mutex_unlock(&per_pin
->lock
);
1634 snd_hda_power_down_pm(codec
);
1638 static void hdmi_repoll_eld(struct work_struct
*work
)
1640 struct hdmi_spec_per_pin
*per_pin
=
1641 container_of(to_delayed_work(work
), struct hdmi_spec_per_pin
, work
);
1643 if (per_pin
->repoll_count
++ > 6)
1644 per_pin
->repoll_count
= 0;
1646 if (hdmi_present_sense(per_pin
, per_pin
->repoll_count
))
1647 snd_hda_jack_report_sync(per_pin
->codec
);
1650 static void intel_haswell_fixup_connect_list(struct hda_codec
*codec
,
1653 static int hdmi_add_pin(struct hda_codec
*codec
, hda_nid_t pin_nid
)
1655 struct hdmi_spec
*spec
= codec
->spec
;
1656 unsigned int caps
, config
;
1658 struct hdmi_spec_per_pin
*per_pin
;
1661 caps
= snd_hda_query_pin_caps(codec
, pin_nid
);
1662 if (!(caps
& (AC_PINCAP_HDMI
| AC_PINCAP_DP
)))
1665 config
= snd_hda_codec_get_pincfg(codec
, pin_nid
);
1666 if (get_defcfg_connect(config
) == AC_JACK_PORT_NONE
)
1669 if (is_haswell_plus(codec
))
1670 intel_haswell_fixup_connect_list(codec
, pin_nid
);
1672 pin_idx
= spec
->num_pins
;
1673 per_pin
= snd_array_new(&spec
->pins
);
1677 per_pin
->pin_nid
= pin_nid
;
1678 per_pin
->non_pcm
= false;
1680 err
= hdmi_read_pin_conn(codec
, pin_idx
);
1689 static int hdmi_add_cvt(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
1691 struct hdmi_spec
*spec
= codec
->spec
;
1692 struct hdmi_spec_per_cvt
*per_cvt
;
1696 chans
= get_wcaps(codec
, cvt_nid
);
1697 chans
= get_wcaps_channels(chans
);
1699 per_cvt
= snd_array_new(&spec
->cvts
);
1703 per_cvt
->cvt_nid
= cvt_nid
;
1704 per_cvt
->channels_min
= 2;
1706 per_cvt
->channels_max
= chans
;
1707 if (chans
> spec
->channels_max
)
1708 spec
->channels_max
= chans
;
1711 err
= snd_hda_query_supported_pcm(codec
, cvt_nid
,
1718 if (spec
->num_cvts
< ARRAY_SIZE(spec
->cvt_nids
))
1719 spec
->cvt_nids
[spec
->num_cvts
] = cvt_nid
;
1725 static int hdmi_parse_codec(struct hda_codec
*codec
)
1730 nodes
= snd_hda_get_sub_nodes(codec
, codec
->core
.afg
, &nid
);
1731 if (!nid
|| nodes
< 0) {
1732 codec_warn(codec
, "HDMI: failed to get afg sub nodes\n");
1736 for (i
= 0; i
< nodes
; i
++, nid
++) {
1740 caps
= get_wcaps(codec
, nid
);
1741 type
= get_wcaps_type(caps
);
1743 if (!(caps
& AC_WCAP_DIGITAL
))
1747 case AC_WID_AUD_OUT
:
1748 hdmi_add_cvt(codec
, nid
);
1751 hdmi_add_pin(codec
, nid
);
1761 static bool check_non_pcm_per_cvt(struct hda_codec
*codec
, hda_nid_t cvt_nid
)
1763 struct hda_spdif_out
*spdif
;
1766 mutex_lock(&codec
->spdif_mutex
);
1767 spdif
= snd_hda_spdif_out_of_nid(codec
, cvt_nid
);
1768 non_pcm
= !!(spdif
->status
& IEC958_AES0_NONAUDIO
);
1769 mutex_unlock(&codec
->spdif_mutex
);
1778 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1779 struct hda_codec
*codec
,
1780 unsigned int stream_tag
,
1781 unsigned int format
,
1782 struct snd_pcm_substream
*substream
)
1784 hda_nid_t cvt_nid
= hinfo
->nid
;
1785 struct hdmi_spec
*spec
= codec
->spec
;
1786 int pin_idx
= hinfo_to_pin_index(codec
, hinfo
);
1787 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
1788 hda_nid_t pin_nid
= per_pin
->pin_nid
;
1792 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
)) {
1793 /* Verify pin:cvt selections to avoid silent audio after S3.
1794 * After S3, the audio driver restores pin:cvt selections
1795 * but this can happen before gfx is ready and such selection
1796 * is overlooked by HW. Thus multiple pins can share a same
1797 * default convertor and mute control will affect each other,
1798 * which can cause a resumed audio playback become silent
1801 intel_verify_pin_cvt_connect(codec
, per_pin
);
1802 intel_not_share_assigned_cvt(codec
, pin_nid
, per_pin
->mux_idx
);
1805 non_pcm
= check_non_pcm_per_cvt(codec
, cvt_nid
);
1806 mutex_lock(&per_pin
->lock
);
1807 per_pin
->channels
= substream
->runtime
->channels
;
1808 per_pin
->setup
= true;
1810 hdmi_setup_audio_infoframe(codec
, per_pin
, non_pcm
);
1811 mutex_unlock(&per_pin
->lock
);
1813 if (spec
->dyn_pin_out
) {
1814 pinctl
= snd_hda_codec_read(codec
, pin_nid
, 0,
1815 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
1816 snd_hda_codec_write(codec
, pin_nid
, 0,
1817 AC_VERB_SET_PIN_WIDGET_CONTROL
,
1821 return spec
->ops
.setup_stream(codec
, cvt_nid
, pin_nid
, stream_tag
, format
);
1824 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream
*hinfo
,
1825 struct hda_codec
*codec
,
1826 struct snd_pcm_substream
*substream
)
1828 snd_hda_codec_cleanup_stream(codec
, hinfo
->nid
);
1832 static int hdmi_pcm_close(struct hda_pcm_stream
*hinfo
,
1833 struct hda_codec
*codec
,
1834 struct snd_pcm_substream
*substream
)
1836 struct hdmi_spec
*spec
= codec
->spec
;
1837 int cvt_idx
, pin_idx
;
1838 struct hdmi_spec_per_cvt
*per_cvt
;
1839 struct hdmi_spec_per_pin
*per_pin
;
1843 cvt_idx
= cvt_nid_to_cvt_index(codec
, hinfo
->nid
);
1844 if (snd_BUG_ON(cvt_idx
< 0))
1846 per_cvt
= get_cvt(spec
, cvt_idx
);
1848 snd_BUG_ON(!per_cvt
->assigned
);
1849 per_cvt
->assigned
= 0;
1852 pin_idx
= hinfo_to_pin_index(codec
, hinfo
);
1853 if (snd_BUG_ON(pin_idx
< 0))
1855 per_pin
= get_pin(spec
, pin_idx
);
1857 if (spec
->dyn_pin_out
) {
1858 pinctl
= snd_hda_codec_read(codec
, per_pin
->pin_nid
, 0,
1859 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
1860 snd_hda_codec_write(codec
, per_pin
->pin_nid
, 0,
1861 AC_VERB_SET_PIN_WIDGET_CONTROL
,
1865 snd_hda_spdif_ctls_unassign(codec
, pin_idx
);
1867 mutex_lock(&per_pin
->lock
);
1868 per_pin
->chmap_set
= false;
1869 memset(per_pin
->chmap
, 0, sizeof(per_pin
->chmap
));
1871 per_pin
->setup
= false;
1872 per_pin
->channels
= 0;
1873 mutex_unlock(&per_pin
->lock
);
1879 static const struct hda_pcm_ops generic_ops
= {
1880 .open
= hdmi_pcm_open
,
1881 .close
= hdmi_pcm_close
,
1882 .prepare
= generic_hdmi_playback_pcm_prepare
,
1883 .cleanup
= generic_hdmi_playback_pcm_cleanup
,
1887 * ALSA API channel-map control callbacks
1889 static int hdmi_chmap_ctl_info(struct snd_kcontrol
*kcontrol
,
1890 struct snd_ctl_elem_info
*uinfo
)
1892 struct snd_pcm_chmap
*info
= snd_kcontrol_chip(kcontrol
);
1893 struct hda_codec
*codec
= info
->private_data
;
1894 struct hdmi_spec
*spec
= codec
->spec
;
1895 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
1896 uinfo
->count
= spec
->channels_max
;
1897 uinfo
->value
.integer
.min
= 0;
1898 uinfo
->value
.integer
.max
= SNDRV_CHMAP_LAST
;
1902 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation
*cap
,
1905 /* If the speaker allocation matches the channel count, it is OK.*/
1906 if (cap
->channels
!= channels
)
1909 /* all channels are remappable freely */
1910 return SNDRV_CTL_TLVT_CHMAP_VAR
;
1913 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation
*cap
,
1914 unsigned int *chmap
, int channels
)
1919 for (c
= 7; c
>= 0; c
--) {
1920 int spk
= cap
->speakers
[c
];
1924 chmap
[count
++] = spk_to_chmap(spk
);
1927 WARN_ON(count
!= channels
);
1930 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol
*kcontrol
, int op_flag
,
1931 unsigned int size
, unsigned int __user
*tlv
)
1933 struct snd_pcm_chmap
*info
= snd_kcontrol_chip(kcontrol
);
1934 struct hda_codec
*codec
= info
->private_data
;
1935 struct hdmi_spec
*spec
= codec
->spec
;
1936 unsigned int __user
*dst
;
1941 if (put_user(SNDRV_CTL_TLVT_CONTAINER
, tlv
))
1945 for (chs
= 2; chs
<= spec
->channels_max
; chs
++) {
1947 struct cea_channel_speaker_allocation
*cap
;
1948 cap
= channel_allocations
;
1949 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++, cap
++) {
1950 int chs_bytes
= chs
* 4;
1951 int type
= spec
->ops
.chmap_cea_alloc_validate_get_type(cap
, chs
);
1952 unsigned int tlv_chmap
[8];
1958 if (put_user(type
, dst
) ||
1959 put_user(chs_bytes
, dst
+ 1))
1964 if (size
< chs_bytes
)
1968 spec
->ops
.cea_alloc_to_tlv_chmap(cap
, tlv_chmap
, chs
);
1969 if (copy_to_user(dst
, tlv_chmap
, chs_bytes
))
1974 if (put_user(count
, tlv
+ 1))
1979 static int hdmi_chmap_ctl_get(struct snd_kcontrol
*kcontrol
,
1980 struct snd_ctl_elem_value
*ucontrol
)
1982 struct snd_pcm_chmap
*info
= snd_kcontrol_chip(kcontrol
);
1983 struct hda_codec
*codec
= info
->private_data
;
1984 struct hdmi_spec
*spec
= codec
->spec
;
1985 int pin_idx
= kcontrol
->private_value
;
1986 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
1989 for (i
= 0; i
< ARRAY_SIZE(per_pin
->chmap
); i
++)
1990 ucontrol
->value
.integer
.value
[i
] = per_pin
->chmap
[i
];
1994 static int hdmi_chmap_ctl_put(struct snd_kcontrol
*kcontrol
,
1995 struct snd_ctl_elem_value
*ucontrol
)
1997 struct snd_pcm_chmap
*info
= snd_kcontrol_chip(kcontrol
);
1998 struct hda_codec
*codec
= info
->private_data
;
1999 struct hdmi_spec
*spec
= codec
->spec
;
2000 int pin_idx
= kcontrol
->private_value
;
2001 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2002 unsigned int ctl_idx
;
2003 struct snd_pcm_substream
*substream
;
2004 unsigned char chmap
[8];
2005 int i
, err
, ca
, prepared
= 0;
2007 ctl_idx
= snd_ctl_get_ioffidx(kcontrol
, &ucontrol
->id
);
2008 substream
= snd_pcm_chmap_substream(info
, ctl_idx
);
2009 if (!substream
|| !substream
->runtime
)
2010 return 0; /* just for avoiding error from alsactl restore */
2011 switch (substream
->runtime
->status
->state
) {
2012 case SNDRV_PCM_STATE_OPEN
:
2013 case SNDRV_PCM_STATE_SETUP
:
2015 case SNDRV_PCM_STATE_PREPARED
:
2021 memset(chmap
, 0, sizeof(chmap
));
2022 for (i
= 0; i
< ARRAY_SIZE(chmap
); i
++)
2023 chmap
[i
] = ucontrol
->value
.integer
.value
[i
];
2024 if (!memcmp(chmap
, per_pin
->chmap
, sizeof(chmap
)))
2026 ca
= hdmi_manual_channel_allocation(ARRAY_SIZE(chmap
), chmap
);
2029 if (spec
->ops
.chmap_validate
) {
2030 err
= spec
->ops
.chmap_validate(ca
, ARRAY_SIZE(chmap
), chmap
);
2034 mutex_lock(&per_pin
->lock
);
2035 per_pin
->chmap_set
= true;
2036 memcpy(per_pin
->chmap
, chmap
, sizeof(chmap
));
2038 hdmi_setup_audio_infoframe(codec
, per_pin
, per_pin
->non_pcm
);
2039 mutex_unlock(&per_pin
->lock
);
2044 static int generic_hdmi_build_pcms(struct hda_codec
*codec
)
2046 struct hdmi_spec
*spec
= codec
->spec
;
2049 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2050 struct hda_pcm
*info
;
2051 struct hda_pcm_stream
*pstr
;
2052 struct hdmi_spec_per_pin
*per_pin
;
2054 per_pin
= get_pin(spec
, pin_idx
);
2055 info
= snd_hda_codec_pcm_new(codec
, "HDMI %d", pin_idx
);
2058 spec
->pcm_rec
[pin_idx
] = info
;
2059 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
2060 info
->own_chmap
= true;
2062 pstr
= &info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
2063 pstr
->substreams
= 1;
2064 pstr
->ops
= generic_ops
;
2065 /* other pstr fields are set in open */
2071 static int generic_hdmi_build_jack(struct hda_codec
*codec
, int pin_idx
)
2073 char hdmi_str
[32] = "HDMI/DP";
2074 struct hdmi_spec
*spec
= codec
->spec
;
2075 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2076 int pcmdev
= get_pcm_rec(spec
, pin_idx
)->device
;
2079 sprintf(hdmi_str
+ strlen(hdmi_str
), ",pcm=%d", pcmdev
);
2080 if (!is_jack_detectable(codec
, per_pin
->pin_nid
))
2081 strncat(hdmi_str
, " Phantom",
2082 sizeof(hdmi_str
) - strlen(hdmi_str
) - 1);
2084 return snd_hda_jack_add_kctl(codec
, per_pin
->pin_nid
, hdmi_str
);
2087 static int generic_hdmi_build_controls(struct hda_codec
*codec
)
2089 struct hdmi_spec
*spec
= codec
->spec
;
2093 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2094 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2096 err
= generic_hdmi_build_jack(codec
, pin_idx
);
2100 err
= snd_hda_create_dig_out_ctls(codec
,
2102 per_pin
->mux_nids
[0],
2106 snd_hda_spdif_ctls_unassign(codec
, pin_idx
);
2108 /* add control for ELD Bytes */
2109 err
= hdmi_create_eld_ctl(codec
, pin_idx
,
2110 get_pcm_rec(spec
, pin_idx
)->device
);
2115 hdmi_present_sense(per_pin
, 0);
2118 /* add channel maps */
2119 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2120 struct hda_pcm
*pcm
;
2121 struct snd_pcm_chmap
*chmap
;
2122 struct snd_kcontrol
*kctl
;
2125 pcm
= spec
->pcm_rec
[pin_idx
];
2126 if (!pcm
|| !pcm
->pcm
)
2128 err
= snd_pcm_add_chmap_ctls(pcm
->pcm
,
2129 SNDRV_PCM_STREAM_PLAYBACK
,
2130 NULL
, 0, pin_idx
, &chmap
);
2133 /* override handlers */
2134 chmap
->private_data
= codec
;
2136 for (i
= 0; i
< kctl
->count
; i
++)
2137 kctl
->vd
[i
].access
|= SNDRV_CTL_ELEM_ACCESS_WRITE
;
2138 kctl
->info
= hdmi_chmap_ctl_info
;
2139 kctl
->get
= hdmi_chmap_ctl_get
;
2140 kctl
->put
= hdmi_chmap_ctl_put
;
2141 kctl
->tlv
.c
= hdmi_chmap_ctl_tlv
;
2147 static int generic_hdmi_init_per_pins(struct hda_codec
*codec
)
2149 struct hdmi_spec
*spec
= codec
->spec
;
2152 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2153 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2155 per_pin
->codec
= codec
;
2156 mutex_init(&per_pin
->lock
);
2157 INIT_DELAYED_WORK(&per_pin
->work
, hdmi_repoll_eld
);
2158 eld_proc_new(per_pin
, pin_idx
);
2163 static int generic_hdmi_init(struct hda_codec
*codec
)
2165 struct hdmi_spec
*spec
= codec
->spec
;
2168 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2169 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2170 hda_nid_t pin_nid
= per_pin
->pin_nid
;
2172 hdmi_init_pin(codec
, pin_nid
);
2173 snd_hda_jack_detect_enable_callback(codec
, pin_nid
,
2174 codec
->jackpoll_interval
> 0 ? jack_callback
: NULL
);
2179 static void hdmi_array_init(struct hdmi_spec
*spec
, int nums
)
2181 snd_array_init(&spec
->pins
, sizeof(struct hdmi_spec_per_pin
), nums
);
2182 snd_array_init(&spec
->cvts
, sizeof(struct hdmi_spec_per_cvt
), nums
);
2185 static void hdmi_array_free(struct hdmi_spec
*spec
)
2187 snd_array_free(&spec
->pins
);
2188 snd_array_free(&spec
->cvts
);
2191 static void generic_hdmi_free(struct hda_codec
*codec
)
2193 struct hdmi_spec
*spec
= codec
->spec
;
2196 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2197 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2199 cancel_delayed_work_sync(&per_pin
->work
);
2200 eld_proc_free(per_pin
);
2203 hdmi_array_free(spec
);
2208 static int generic_hdmi_resume(struct hda_codec
*codec
)
2210 struct hdmi_spec
*spec
= codec
->spec
;
2213 codec
->patch_ops
.init(codec
);
2214 regcache_sync(codec
->core
.regmap
);
2216 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
2217 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
2218 hdmi_present_sense(per_pin
, 1);
2224 static const struct hda_codec_ops generic_hdmi_patch_ops
= {
2225 .init
= generic_hdmi_init
,
2226 .free
= generic_hdmi_free
,
2227 .build_pcms
= generic_hdmi_build_pcms
,
2228 .build_controls
= generic_hdmi_build_controls
,
2229 .unsol_event
= hdmi_unsol_event
,
2231 .resume
= generic_hdmi_resume
,
2235 static const struct hdmi_ops generic_standard_hdmi_ops
= {
2236 .pin_get_eld
= snd_hdmi_get_eld
,
2237 .pin_get_slot_channel
= hdmi_pin_get_slot_channel
,
2238 .pin_set_slot_channel
= hdmi_pin_set_slot_channel
,
2239 .pin_setup_infoframe
= hdmi_pin_setup_infoframe
,
2240 .pin_hbr_setup
= hdmi_pin_hbr_setup
,
2241 .setup_stream
= hdmi_setup_stream
,
2242 .chmap_cea_alloc_validate_get_type
= hdmi_chmap_cea_alloc_validate_get_type
,
2243 .cea_alloc_to_tlv_chmap
= hdmi_cea_alloc_to_tlv_chmap
,
2247 static void intel_haswell_fixup_connect_list(struct hda_codec
*codec
,
2250 struct hdmi_spec
*spec
= codec
->spec
;
2254 nconns
= snd_hda_get_connections(codec
, nid
, conns
, ARRAY_SIZE(conns
));
2255 if (nconns
== spec
->num_cvts
&&
2256 !memcmp(conns
, spec
->cvt_nids
, spec
->num_cvts
* sizeof(hda_nid_t
)))
2259 /* override pins connection list */
2260 codec_dbg(codec
, "hdmi: haswell: override pin connection 0x%x\n", nid
);
2261 snd_hda_override_conn_list(codec
, nid
, spec
->num_cvts
, spec
->cvt_nids
);
2264 #define INTEL_VENDOR_NID 0x08
2265 #define INTEL_GET_VENDOR_VERB 0xf81
2266 #define INTEL_SET_VENDOR_VERB 0x781
2267 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2268 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2270 static void intel_haswell_enable_all_pins(struct hda_codec
*codec
,
2273 unsigned int vendor_param
;
2275 vendor_param
= snd_hda_codec_read(codec
, INTEL_VENDOR_NID
, 0,
2276 INTEL_GET_VENDOR_VERB
, 0);
2277 if (vendor_param
== -1 || vendor_param
& INTEL_EN_ALL_PIN_CVTS
)
2280 vendor_param
|= INTEL_EN_ALL_PIN_CVTS
;
2281 vendor_param
= snd_hda_codec_read(codec
, INTEL_VENDOR_NID
, 0,
2282 INTEL_SET_VENDOR_VERB
, vendor_param
);
2283 if (vendor_param
== -1)
2287 snd_hda_codec_update_widgets(codec
);
2290 static void intel_haswell_fixup_enable_dp12(struct hda_codec
*codec
)
2292 unsigned int vendor_param
;
2294 vendor_param
= snd_hda_codec_read(codec
, INTEL_VENDOR_NID
, 0,
2295 INTEL_GET_VENDOR_VERB
, 0);
2296 if (vendor_param
== -1 || vendor_param
& INTEL_EN_DP12
)
2299 /* enable DP1.2 mode */
2300 vendor_param
|= INTEL_EN_DP12
;
2301 snd_hdac_regmap_add_vendor_verb(&codec
->core
, INTEL_SET_VENDOR_VERB
);
2302 snd_hda_codec_write_cache(codec
, INTEL_VENDOR_NID
, 0,
2303 INTEL_SET_VENDOR_VERB
, vendor_param
);
2306 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2307 * Otherwise you may get severe h/w communication errors.
2309 static void haswell_set_power_state(struct hda_codec
*codec
, hda_nid_t fg
,
2310 unsigned int power_state
)
2312 if (power_state
== AC_PWRST_D0
) {
2313 intel_haswell_enable_all_pins(codec
, false);
2314 intel_haswell_fixup_enable_dp12(codec
);
2317 snd_hda_codec_read(codec
, fg
, 0, AC_VERB_SET_POWER_STATE
, power_state
);
2318 snd_hda_codec_set_power_to_all(codec
, fg
, power_state
);
2321 static int patch_generic_hdmi(struct hda_codec
*codec
)
2323 struct hdmi_spec
*spec
;
2325 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
2329 spec
->ops
= generic_standard_hdmi_ops
;
2331 hdmi_array_init(spec
, 4);
2333 if (is_haswell_plus(codec
)) {
2334 intel_haswell_enable_all_pins(codec
, true);
2335 intel_haswell_fixup_enable_dp12(codec
);
2338 /* For Valleyview/Cherryview, only the display codec is in the display
2339 * power well and can use link_power ops to request/release the power.
2340 * For Haswell/Broadwell, the controller is also in the power well and
2341 * can cover the codec power request, and so need not set this flag.
2342 * For previous platforms, there is no such power well feature.
2344 if (is_valleyview_plus(codec
))
2345 codec
->core
.link_power_control
= 1;
2347 if (is_haswell_plus(codec
) || is_valleyview_plus(codec
))
2348 codec
->depop_delay
= 0;
2350 if (hdmi_parse_codec(codec
) < 0) {
2355 codec
->patch_ops
= generic_hdmi_patch_ops
;
2356 if (is_haswell_plus(codec
)) {
2357 codec
->patch_ops
.set_power_state
= haswell_set_power_state
;
2358 codec
->dp_mst
= true;
2361 generic_hdmi_init_per_pins(codec
);
2363 init_channel_allocations();
2369 * Shared non-generic implementations
2372 static int simple_playback_build_pcms(struct hda_codec
*codec
)
2374 struct hdmi_spec
*spec
= codec
->spec
;
2375 struct hda_pcm
*info
;
2377 struct hda_pcm_stream
*pstr
;
2378 struct hdmi_spec_per_cvt
*per_cvt
;
2380 per_cvt
= get_cvt(spec
, 0);
2381 chans
= get_wcaps(codec
, per_cvt
->cvt_nid
);
2382 chans
= get_wcaps_channels(chans
);
2384 info
= snd_hda_codec_pcm_new(codec
, "HDMI 0");
2387 spec
->pcm_rec
[0] = info
;
2388 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
2389 pstr
= &info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
2390 *pstr
= spec
->pcm_playback
;
2391 pstr
->nid
= per_cvt
->cvt_nid
;
2392 if (pstr
->channels_max
<= 2 && chans
&& chans
<= 16)
2393 pstr
->channels_max
= chans
;
2398 /* unsolicited event for jack sensing */
2399 static void simple_hdmi_unsol_event(struct hda_codec
*codec
,
2402 snd_hda_jack_set_dirty_all(codec
);
2403 snd_hda_jack_report_sync(codec
);
2406 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2407 * as long as spec->pins[] is set correctly
2409 #define simple_hdmi_build_jack generic_hdmi_build_jack
2411 static int simple_playback_build_controls(struct hda_codec
*codec
)
2413 struct hdmi_spec
*spec
= codec
->spec
;
2414 struct hdmi_spec_per_cvt
*per_cvt
;
2417 per_cvt
= get_cvt(spec
, 0);
2418 err
= snd_hda_create_dig_out_ctls(codec
, per_cvt
->cvt_nid
,
2423 return simple_hdmi_build_jack(codec
, 0);
2426 static int simple_playback_init(struct hda_codec
*codec
)
2428 struct hdmi_spec
*spec
= codec
->spec
;
2429 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, 0);
2430 hda_nid_t pin
= per_pin
->pin_nid
;
2432 snd_hda_codec_write(codec
, pin
, 0,
2433 AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
);
2434 /* some codecs require to unmute the pin */
2435 if (get_wcaps(codec
, pin
) & AC_WCAP_OUT_AMP
)
2436 snd_hda_codec_write(codec
, pin
, 0, AC_VERB_SET_AMP_GAIN_MUTE
,
2438 snd_hda_jack_detect_enable(codec
, pin
);
2442 static void simple_playback_free(struct hda_codec
*codec
)
2444 struct hdmi_spec
*spec
= codec
->spec
;
2446 hdmi_array_free(spec
);
2451 * Nvidia specific implementations
2454 #define Nv_VERB_SET_Channel_Allocation 0xF79
2455 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2456 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2457 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2459 #define nvhdmi_master_con_nid_7x 0x04
2460 #define nvhdmi_master_pin_nid_7x 0x05
2462 static const hda_nid_t nvhdmi_con_nids_7x
[4] = {
2463 /*front, rear, clfe, rear_surr */
2467 static const struct hda_verb nvhdmi_basic_init_7x_2ch
[] = {
2468 /* set audio protect on */
2469 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
2470 /* enable digital output on pin widget */
2471 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2475 static const struct hda_verb nvhdmi_basic_init_7x_8ch
[] = {
2476 /* set audio protect on */
2477 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
2478 /* enable digital output on pin widget */
2479 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2480 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2481 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2482 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2483 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
2487 #ifdef LIMITED_RATE_FMT_SUPPORT
2488 /* support only the safe format and rate */
2489 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2490 #define SUPPORTED_MAXBPS 16
2491 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2493 /* support all rates and formats */
2494 #define SUPPORTED_RATES \
2495 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2496 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2497 SNDRV_PCM_RATE_192000)
2498 #define SUPPORTED_MAXBPS 24
2499 #define SUPPORTED_FORMATS \
2500 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2503 static int nvhdmi_7x_init_2ch(struct hda_codec
*codec
)
2505 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x_2ch
);
2509 static int nvhdmi_7x_init_8ch(struct hda_codec
*codec
)
2511 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x_8ch
);
2515 static unsigned int channels_2_6_8
[] = {
2519 static unsigned int channels_2_8
[] = {
2523 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels
= {
2524 .count
= ARRAY_SIZE(channels_2_6_8
),
2525 .list
= channels_2_6_8
,
2529 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels
= {
2530 .count
= ARRAY_SIZE(channels_2_8
),
2531 .list
= channels_2_8
,
2535 static int simple_playback_pcm_open(struct hda_pcm_stream
*hinfo
,
2536 struct hda_codec
*codec
,
2537 struct snd_pcm_substream
*substream
)
2539 struct hdmi_spec
*spec
= codec
->spec
;
2540 struct snd_pcm_hw_constraint_list
*hw_constraints_channels
= NULL
;
2542 switch (codec
->preset
->id
) {
2547 hw_constraints_channels
= &hw_constraints_2_8_channels
;
2550 hw_constraints_channels
= &hw_constraints_2_6_8_channels
;
2556 if (hw_constraints_channels
!= NULL
) {
2557 snd_pcm_hw_constraint_list(substream
->runtime
, 0,
2558 SNDRV_PCM_HW_PARAM_CHANNELS
,
2559 hw_constraints_channels
);
2561 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
2562 SNDRV_PCM_HW_PARAM_CHANNELS
, 2);
2565 return snd_hda_multi_out_dig_open(codec
, &spec
->multiout
);
2568 static int simple_playback_pcm_close(struct hda_pcm_stream
*hinfo
,
2569 struct hda_codec
*codec
,
2570 struct snd_pcm_substream
*substream
)
2572 struct hdmi_spec
*spec
= codec
->spec
;
2573 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
2576 static int simple_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
2577 struct hda_codec
*codec
,
2578 unsigned int stream_tag
,
2579 unsigned int format
,
2580 struct snd_pcm_substream
*substream
)
2582 struct hdmi_spec
*spec
= codec
->spec
;
2583 return snd_hda_multi_out_dig_prepare(codec
, &spec
->multiout
,
2584 stream_tag
, format
, substream
);
2587 static const struct hda_pcm_stream simple_pcm_playback
= {
2592 .open
= simple_playback_pcm_open
,
2593 .close
= simple_playback_pcm_close
,
2594 .prepare
= simple_playback_pcm_prepare
2598 static const struct hda_codec_ops simple_hdmi_patch_ops
= {
2599 .build_controls
= simple_playback_build_controls
,
2600 .build_pcms
= simple_playback_build_pcms
,
2601 .init
= simple_playback_init
,
2602 .free
= simple_playback_free
,
2603 .unsol_event
= simple_hdmi_unsol_event
,
2606 static int patch_simple_hdmi(struct hda_codec
*codec
,
2607 hda_nid_t cvt_nid
, hda_nid_t pin_nid
)
2609 struct hdmi_spec
*spec
;
2610 struct hdmi_spec_per_cvt
*per_cvt
;
2611 struct hdmi_spec_per_pin
*per_pin
;
2613 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
2618 hdmi_array_init(spec
, 1);
2620 spec
->multiout
.num_dacs
= 0; /* no analog */
2621 spec
->multiout
.max_channels
= 2;
2622 spec
->multiout
.dig_out_nid
= cvt_nid
;
2625 per_pin
= snd_array_new(&spec
->pins
);
2626 per_cvt
= snd_array_new(&spec
->cvts
);
2627 if (!per_pin
|| !per_cvt
) {
2628 simple_playback_free(codec
);
2631 per_cvt
->cvt_nid
= cvt_nid
;
2632 per_pin
->pin_nid
= pin_nid
;
2633 spec
->pcm_playback
= simple_pcm_playback
;
2635 codec
->patch_ops
= simple_hdmi_patch_ops
;
2640 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec
*codec
,
2643 unsigned int chanmask
;
2644 int chan
= channels
? (channels
- 1) : 1;
2663 /* Set the audio infoframe channel allocation and checksum fields. The
2664 * channel count is computed implicitly by the hardware. */
2665 snd_hda_codec_write(codec
, 0x1, 0,
2666 Nv_VERB_SET_Channel_Allocation
, chanmask
);
2668 snd_hda_codec_write(codec
, 0x1, 0,
2669 Nv_VERB_SET_Info_Frame_Checksum
,
2670 (0x71 - chan
- chanmask
));
2673 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream
*hinfo
,
2674 struct hda_codec
*codec
,
2675 struct snd_pcm_substream
*substream
)
2677 struct hdmi_spec
*spec
= codec
->spec
;
2680 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
,
2681 0, AC_VERB_SET_CHANNEL_STREAMID
, 0);
2682 for (i
= 0; i
< 4; i
++) {
2683 /* set the stream id */
2684 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
2685 AC_VERB_SET_CHANNEL_STREAMID
, 0);
2686 /* set the stream format */
2687 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
2688 AC_VERB_SET_STREAM_FORMAT
, 0);
2691 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2692 * streams are disabled. */
2693 nvhdmi_8ch_7x_set_info_frame_parameters(codec
, 8);
2695 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
2698 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream
*hinfo
,
2699 struct hda_codec
*codec
,
2700 unsigned int stream_tag
,
2701 unsigned int format
,
2702 struct snd_pcm_substream
*substream
)
2705 unsigned int dataDCC2
, channel_id
;
2707 struct hdmi_spec
*spec
= codec
->spec
;
2708 struct hda_spdif_out
*spdif
;
2709 struct hdmi_spec_per_cvt
*per_cvt
;
2711 mutex_lock(&codec
->spdif_mutex
);
2712 per_cvt
= get_cvt(spec
, 0);
2713 spdif
= snd_hda_spdif_out_of_nid(codec
, per_cvt
->cvt_nid
);
2715 chs
= substream
->runtime
->channels
;
2719 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2720 if (codec
->spdif_status_reset
&& (spdif
->ctls
& AC_DIG1_ENABLE
))
2721 snd_hda_codec_write(codec
,
2722 nvhdmi_master_con_nid_7x
,
2724 AC_VERB_SET_DIGI_CONVERT_1
,
2725 spdif
->ctls
& ~AC_DIG1_ENABLE
& 0xff);
2727 /* set the stream id */
2728 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
2729 AC_VERB_SET_CHANNEL_STREAMID
, (stream_tag
<< 4) | 0x0);
2731 /* set the stream format */
2732 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
2733 AC_VERB_SET_STREAM_FORMAT
, format
);
2735 /* turn on again (if needed) */
2736 /* enable and set the channel status audio/data flag */
2737 if (codec
->spdif_status_reset
&& (spdif
->ctls
& AC_DIG1_ENABLE
)) {
2738 snd_hda_codec_write(codec
,
2739 nvhdmi_master_con_nid_7x
,
2741 AC_VERB_SET_DIGI_CONVERT_1
,
2742 spdif
->ctls
& 0xff);
2743 snd_hda_codec_write(codec
,
2744 nvhdmi_master_con_nid_7x
,
2746 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
2749 for (i
= 0; i
< 4; i
++) {
2755 /* turn off SPDIF once;
2756 *otherwise the IEC958 bits won't be updated
2758 if (codec
->spdif_status_reset
&&
2759 (spdif
->ctls
& AC_DIG1_ENABLE
))
2760 snd_hda_codec_write(codec
,
2761 nvhdmi_con_nids_7x
[i
],
2763 AC_VERB_SET_DIGI_CONVERT_1
,
2764 spdif
->ctls
& ~AC_DIG1_ENABLE
& 0xff);
2765 /* set the stream id */
2766 snd_hda_codec_write(codec
,
2767 nvhdmi_con_nids_7x
[i
],
2769 AC_VERB_SET_CHANNEL_STREAMID
,
2770 (stream_tag
<< 4) | channel_id
);
2771 /* set the stream format */
2772 snd_hda_codec_write(codec
,
2773 nvhdmi_con_nids_7x
[i
],
2775 AC_VERB_SET_STREAM_FORMAT
,
2777 /* turn on again (if needed) */
2778 /* enable and set the channel status audio/data flag */
2779 if (codec
->spdif_status_reset
&&
2780 (spdif
->ctls
& AC_DIG1_ENABLE
)) {
2781 snd_hda_codec_write(codec
,
2782 nvhdmi_con_nids_7x
[i
],
2784 AC_VERB_SET_DIGI_CONVERT_1
,
2785 spdif
->ctls
& 0xff);
2786 snd_hda_codec_write(codec
,
2787 nvhdmi_con_nids_7x
[i
],
2789 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
2793 nvhdmi_8ch_7x_set_info_frame_parameters(codec
, chs
);
2795 mutex_unlock(&codec
->spdif_mutex
);
2799 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x
= {
2803 .nid
= nvhdmi_master_con_nid_7x
,
2804 .rates
= SUPPORTED_RATES
,
2805 .maxbps
= SUPPORTED_MAXBPS
,
2806 .formats
= SUPPORTED_FORMATS
,
2808 .open
= simple_playback_pcm_open
,
2809 .close
= nvhdmi_8ch_7x_pcm_close
,
2810 .prepare
= nvhdmi_8ch_7x_pcm_prepare
2814 static int patch_nvhdmi_2ch(struct hda_codec
*codec
)
2816 struct hdmi_spec
*spec
;
2817 int err
= patch_simple_hdmi(codec
, nvhdmi_master_con_nid_7x
,
2818 nvhdmi_master_pin_nid_7x
);
2822 codec
->patch_ops
.init
= nvhdmi_7x_init_2ch
;
2823 /* override the PCM rates, etc, as the codec doesn't give full list */
2825 spec
->pcm_playback
.rates
= SUPPORTED_RATES
;
2826 spec
->pcm_playback
.maxbps
= SUPPORTED_MAXBPS
;
2827 spec
->pcm_playback
.formats
= SUPPORTED_FORMATS
;
2831 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec
*codec
)
2833 struct hdmi_spec
*spec
= codec
->spec
;
2834 int err
= simple_playback_build_pcms(codec
);
2836 struct hda_pcm
*info
= get_pcm_rec(spec
, 0);
2837 info
->own_chmap
= true;
2842 static int nvhdmi_7x_8ch_build_controls(struct hda_codec
*codec
)
2844 struct hdmi_spec
*spec
= codec
->spec
;
2845 struct hda_pcm
*info
;
2846 struct snd_pcm_chmap
*chmap
;
2849 err
= simple_playback_build_controls(codec
);
2853 /* add channel maps */
2854 info
= get_pcm_rec(spec
, 0);
2855 err
= snd_pcm_add_chmap_ctls(info
->pcm
,
2856 SNDRV_PCM_STREAM_PLAYBACK
,
2857 snd_pcm_alt_chmaps
, 8, 0, &chmap
);
2860 switch (codec
->preset
->id
) {
2865 chmap
->channel_mask
= (1U << 2) | (1U << 8);
2868 chmap
->channel_mask
= (1U << 2) | (1U << 6) | (1U << 8);
2873 static int patch_nvhdmi_8ch_7x(struct hda_codec
*codec
)
2875 struct hdmi_spec
*spec
;
2876 int err
= patch_nvhdmi_2ch(codec
);
2880 spec
->multiout
.max_channels
= 8;
2881 spec
->pcm_playback
= nvhdmi_pcm_playback_8ch_7x
;
2882 codec
->patch_ops
.init
= nvhdmi_7x_init_8ch
;
2883 codec
->patch_ops
.build_pcms
= nvhdmi_7x_8ch_build_pcms
;
2884 codec
->patch_ops
.build_controls
= nvhdmi_7x_8ch_build_controls
;
2886 /* Initialize the audio infoframe channel mask and checksum to something
2888 nvhdmi_8ch_7x_set_info_frame_parameters(codec
, 8);
2894 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2898 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation
*cap
,
2901 if (cap
->ca_index
== 0x00 && channels
== 2)
2902 return SNDRV_CTL_TLVT_CHMAP_FIXED
;
2904 return hdmi_chmap_cea_alloc_validate_get_type(cap
, channels
);
2907 static int nvhdmi_chmap_validate(int ca
, int chs
, unsigned char *map
)
2909 if (ca
== 0x00 && (map
[0] != SNDRV_CHMAP_FL
|| map
[1] != SNDRV_CHMAP_FR
))
2915 static int patch_nvhdmi(struct hda_codec
*codec
)
2917 struct hdmi_spec
*spec
;
2920 err
= patch_generic_hdmi(codec
);
2925 spec
->dyn_pin_out
= true;
2927 spec
->ops
.chmap_cea_alloc_validate_get_type
=
2928 nvhdmi_chmap_cea_alloc_validate_get_type
;
2929 spec
->ops
.chmap_validate
= nvhdmi_chmap_validate
;
2935 * ATI/AMD-specific implementations
2938 #define is_amdhdmi_rev3_or_later(codec) \
2939 ((codec)->core.vendor_id == 0x1002aa01 && \
2940 ((codec)->core.revision_id & 0xff00) >= 0x0300)
2941 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2943 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2944 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2945 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
2946 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
2947 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
2948 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
2949 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2950 #define ATI_VERB_SET_HBR_CONTROL 0x77c
2951 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
2952 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
2953 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
2954 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
2955 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2956 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2957 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2958 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2959 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2960 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2961 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2962 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
2963 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2964 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2965 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2966 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2967 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2969 /* AMD specific HDA cvt verbs */
2970 #define ATI_VERB_SET_RAMP_RATE 0x770
2971 #define ATI_VERB_GET_RAMP_RATE 0xf70
2973 #define ATI_OUT_ENABLE 0x1
2975 #define ATI_MULTICHANNEL_MODE_PAIRED 0
2976 #define ATI_MULTICHANNEL_MODE_SINGLE 1
2978 #define ATI_HBR_CAPABLE 0x01
2979 #define ATI_HBR_ENABLE 0x10
2981 static int atihdmi_pin_get_eld(struct hda_codec
*codec
, hda_nid_t nid
,
2982 unsigned char *buf
, int *eld_size
)
2984 /* call hda_eld.c ATI/AMD-specific function */
2985 return snd_hdmi_get_eld_ati(codec
, nid
, buf
, eld_size
,
2986 is_amdhdmi_rev3_or_later(codec
));
2989 static void atihdmi_pin_setup_infoframe(struct hda_codec
*codec
, hda_nid_t pin_nid
, int ca
,
2990 int active_channels
, int conn_type
)
2992 snd_hda_codec_write(codec
, pin_nid
, 0, ATI_VERB_SET_CHANNEL_ALLOCATION
, ca
);
2995 static int atihdmi_paired_swap_fc_lfe(int pos
)
2998 * ATI/AMD have automatic FC/LFE swap built-in
2999 * when in pairwise mapping mode.
3003 /* see channel_allocations[].speakers[] */
3012 static int atihdmi_paired_chmap_validate(int ca
, int chs
, unsigned char *map
)
3014 struct cea_channel_speaker_allocation
*cap
;
3017 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3019 cap
= &channel_allocations
[get_channel_allocation_order(ca
)];
3020 for (i
= 0; i
< chs
; ++i
) {
3021 int mask
= to_spk_mask(map
[i
]);
3023 bool companion_ok
= false;
3028 for (j
= 0 + i
% 2; j
< 8; j
+= 2) {
3029 int chan_idx
= 7 - atihdmi_paired_swap_fc_lfe(j
);
3030 if (cap
->speakers
[chan_idx
] == mask
) {
3031 /* channel is in a supported position */
3034 if (i
% 2 == 0 && i
+ 1 < chs
) {
3035 /* even channel, check the odd companion */
3036 int comp_chan_idx
= 7 - atihdmi_paired_swap_fc_lfe(j
+ 1);
3037 int comp_mask_req
= to_spk_mask(map
[i
+1]);
3038 int comp_mask_act
= cap
->speakers
[comp_chan_idx
];
3040 if (comp_mask_req
== comp_mask_act
)
3041 companion_ok
= true;
3053 i
++; /* companion channel already checked */
3059 static int atihdmi_pin_set_slot_channel(struct hda_codec
*codec
, hda_nid_t pin_nid
,
3060 int hdmi_slot
, int stream_channel
)
3063 int ati_channel_setup
= 0;
3068 if (!has_amd_full_remap_support(codec
)) {
3069 hdmi_slot
= atihdmi_paired_swap_fc_lfe(hdmi_slot
);
3071 /* In case this is an odd slot but without stream channel, do not
3072 * disable the slot since the corresponding even slot could have a
3073 * channel. In case neither have a channel, the slot pair will be
3074 * disabled when this function is called for the even slot. */
3075 if (hdmi_slot
% 2 != 0 && stream_channel
== 0xf)
3078 hdmi_slot
-= hdmi_slot
% 2;
3080 if (stream_channel
!= 0xf)
3081 stream_channel
-= stream_channel
% 2;
3084 verb
= ATI_VERB_SET_MULTICHANNEL_01
+ hdmi_slot
/2 + (hdmi_slot
% 2) * 0x00e;
3086 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3088 if (stream_channel
!= 0xf)
3089 ati_channel_setup
= (stream_channel
<< 4) | ATI_OUT_ENABLE
;
3091 return snd_hda_codec_write(codec
, pin_nid
, 0, verb
, ati_channel_setup
);
3094 static int atihdmi_pin_get_slot_channel(struct hda_codec
*codec
, hda_nid_t pin_nid
,
3097 bool was_odd
= false;
3098 int ati_asp_slot
= asp_slot
;
3100 int ati_channel_setup
;
3105 if (!has_amd_full_remap_support(codec
)) {
3106 ati_asp_slot
= atihdmi_paired_swap_fc_lfe(asp_slot
);
3107 if (ati_asp_slot
% 2 != 0) {
3113 verb
= ATI_VERB_GET_MULTICHANNEL_01
+ ati_asp_slot
/2 + (ati_asp_slot
% 2) * 0x00e;
3115 ati_channel_setup
= snd_hda_codec_read(codec
, pin_nid
, 0, verb
, 0);
3117 if (!(ati_channel_setup
& ATI_OUT_ENABLE
))
3120 return ((ati_channel_setup
& 0xf0) >> 4) + !!was_odd
;
3123 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation
*cap
,
3129 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3130 * we need to take that into account (a single channel may take 2
3131 * channel slots if we need to carry a silent channel next to it).
3132 * On Rev3+ AMD codecs this function is not used.
3136 /* We only produce even-numbered channel count TLVs */
3137 if ((channels
% 2) != 0)
3140 for (c
= 0; c
< 7; c
+= 2) {
3141 if (cap
->speakers
[c
] || cap
->speakers
[c
+1])
3145 if (chanpairs
* 2 != channels
)
3148 return SNDRV_CTL_TLVT_CHMAP_PAIRED
;
3151 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation
*cap
,
3152 unsigned int *chmap
, int channels
)
3154 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3158 for (c
= 7; c
>= 0; c
--) {
3159 int chan
= 7 - atihdmi_paired_swap_fc_lfe(7 - c
);
3160 int spk
= cap
->speakers
[chan
];
3162 /* add N/A channel if the companion channel is occupied */
3163 if (cap
->speakers
[chan
+ (chan
% 2 ? -1 : 1)])
3164 chmap
[count
++] = SNDRV_CHMAP_NA
;
3169 chmap
[count
++] = spk_to_chmap(spk
);
3172 WARN_ON(count
!= channels
);
3175 static int atihdmi_pin_hbr_setup(struct hda_codec
*codec
, hda_nid_t pin_nid
,
3178 int hbr_ctl
, hbr_ctl_new
;
3180 hbr_ctl
= snd_hda_codec_read(codec
, pin_nid
, 0, ATI_VERB_GET_HBR_CONTROL
, 0);
3181 if (hbr_ctl
>= 0 && (hbr_ctl
& ATI_HBR_CAPABLE
)) {
3183 hbr_ctl_new
= hbr_ctl
| ATI_HBR_ENABLE
;
3185 hbr_ctl_new
= hbr_ctl
& ~ATI_HBR_ENABLE
;
3188 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3190 hbr_ctl
== hbr_ctl_new
? "" : "new-",
3193 if (hbr_ctl
!= hbr_ctl_new
)
3194 snd_hda_codec_write(codec
, pin_nid
, 0,
3195 ATI_VERB_SET_HBR_CONTROL
,
3204 static int atihdmi_setup_stream(struct hda_codec
*codec
, hda_nid_t cvt_nid
,
3205 hda_nid_t pin_nid
, u32 stream_tag
, int format
)
3208 if (is_amdhdmi_rev3_or_later(codec
)) {
3209 int ramp_rate
= 180; /* default as per AMD spec */
3210 /* disable ramp-up/down for non-pcm as per AMD spec */
3211 if (format
& AC_FMT_TYPE_NON_PCM
)
3214 snd_hda_codec_write(codec
, cvt_nid
, 0, ATI_VERB_SET_RAMP_RATE
, ramp_rate
);
3217 return hdmi_setup_stream(codec
, cvt_nid
, pin_nid
, stream_tag
, format
);
3221 static int atihdmi_init(struct hda_codec
*codec
)
3223 struct hdmi_spec
*spec
= codec
->spec
;
3226 err
= generic_hdmi_init(codec
);
3231 for (pin_idx
= 0; pin_idx
< spec
->num_pins
; pin_idx
++) {
3232 struct hdmi_spec_per_pin
*per_pin
= get_pin(spec
, pin_idx
);
3234 /* make sure downmix information in infoframe is zero */
3235 snd_hda_codec_write(codec
, per_pin
->pin_nid
, 0, ATI_VERB_SET_DOWNMIX_INFO
, 0);
3237 /* enable channel-wise remap mode if supported */
3238 if (has_amd_full_remap_support(codec
))
3239 snd_hda_codec_write(codec
, per_pin
->pin_nid
, 0,
3240 ATI_VERB_SET_MULTICHANNEL_MODE
,
3241 ATI_MULTICHANNEL_MODE_SINGLE
);
3247 static int patch_atihdmi(struct hda_codec
*codec
)
3249 struct hdmi_spec
*spec
;
3250 struct hdmi_spec_per_cvt
*per_cvt
;
3253 err
= patch_generic_hdmi(codec
);
3258 codec
->patch_ops
.init
= atihdmi_init
;
3262 spec
->ops
.pin_get_eld
= atihdmi_pin_get_eld
;
3263 spec
->ops
.pin_get_slot_channel
= atihdmi_pin_get_slot_channel
;
3264 spec
->ops
.pin_set_slot_channel
= atihdmi_pin_set_slot_channel
;
3265 spec
->ops
.pin_setup_infoframe
= atihdmi_pin_setup_infoframe
;
3266 spec
->ops
.pin_hbr_setup
= atihdmi_pin_hbr_setup
;
3267 spec
->ops
.setup_stream
= atihdmi_setup_stream
;
3269 if (!has_amd_full_remap_support(codec
)) {
3270 /* override to ATI/AMD-specific versions with pairwise mapping */
3271 spec
->ops
.chmap_cea_alloc_validate_get_type
=
3272 atihdmi_paired_chmap_cea_alloc_validate_get_type
;
3273 spec
->ops
.cea_alloc_to_tlv_chmap
= atihdmi_paired_cea_alloc_to_tlv_chmap
;
3274 spec
->ops
.chmap_validate
= atihdmi_paired_chmap_validate
;
3277 /* ATI/AMD converters do not advertise all of their capabilities */
3278 for (cvt_idx
= 0; cvt_idx
< spec
->num_cvts
; cvt_idx
++) {
3279 per_cvt
= get_cvt(spec
, cvt_idx
);
3280 per_cvt
->channels_max
= max(per_cvt
->channels_max
, 8u);
3281 per_cvt
->rates
|= SUPPORTED_RATES
;
3282 per_cvt
->formats
|= SUPPORTED_FORMATS
;
3283 per_cvt
->maxbps
= max(per_cvt
->maxbps
, 24u);
3286 spec
->channels_max
= max(spec
->channels_max
, 8u);
3291 /* VIA HDMI Implementation */
3292 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3293 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3295 static int patch_via_hdmi(struct hda_codec
*codec
)
3297 return patch_simple_hdmi(codec
, VIAHDMI_CVT_NID
, VIAHDMI_PIN_NID
);
3303 static const struct hda_codec_preset snd_hda_preset_hdmi
[] = {
3304 { .id
= 0x1002793c, .name
= "RS600 HDMI", .patch
= patch_atihdmi
},
3305 { .id
= 0x10027919, .name
= "RS600 HDMI", .patch
= patch_atihdmi
},
3306 { .id
= 0x1002791a, .name
= "RS690/780 HDMI", .patch
= patch_atihdmi
},
3307 { .id
= 0x1002aa01, .name
= "R6xx HDMI", .patch
= patch_atihdmi
},
3308 { .id
= 0x10951390, .name
= "SiI1390 HDMI", .patch
= patch_generic_hdmi
},
3309 { .id
= 0x10951392, .name
= "SiI1392 HDMI", .patch
= patch_generic_hdmi
},
3310 { .id
= 0x17e80047, .name
= "Chrontel HDMI", .patch
= patch_generic_hdmi
},
3311 { .id
= 0x10de0002, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
3312 { .id
= 0x10de0003, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
3313 { .id
= 0x10de0005, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
3314 { .id
= 0x10de0006, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
3315 { .id
= 0x10de0007, .name
= "MCP79/7A HDMI", .patch
= patch_nvhdmi_8ch_7x
},
3316 { .id
= 0x10de000a, .name
= "GPU 0a HDMI/DP", .patch
= patch_nvhdmi
},
3317 { .id
= 0x10de000b, .name
= "GPU 0b HDMI/DP", .patch
= patch_nvhdmi
},
3318 { .id
= 0x10de000c, .name
= "MCP89 HDMI", .patch
= patch_nvhdmi
},
3319 { .id
= 0x10de000d, .name
= "GPU 0d HDMI/DP", .patch
= patch_nvhdmi
},
3320 { .id
= 0x10de0010, .name
= "GPU 10 HDMI/DP", .patch
= patch_nvhdmi
},
3321 { .id
= 0x10de0011, .name
= "GPU 11 HDMI/DP", .patch
= patch_nvhdmi
},
3322 { .id
= 0x10de0012, .name
= "GPU 12 HDMI/DP", .patch
= patch_nvhdmi
},
3323 { .id
= 0x10de0013, .name
= "GPU 13 HDMI/DP", .patch
= patch_nvhdmi
},
3324 { .id
= 0x10de0014, .name
= "GPU 14 HDMI/DP", .patch
= patch_nvhdmi
},
3325 { .id
= 0x10de0015, .name
= "GPU 15 HDMI/DP", .patch
= patch_nvhdmi
},
3326 { .id
= 0x10de0016, .name
= "GPU 16 HDMI/DP", .patch
= patch_nvhdmi
},
3327 /* 17 is known to be absent */
3328 { .id
= 0x10de0018, .name
= "GPU 18 HDMI/DP", .patch
= patch_nvhdmi
},
3329 { .id
= 0x10de0019, .name
= "GPU 19 HDMI/DP", .patch
= patch_nvhdmi
},
3330 { .id
= 0x10de001a, .name
= "GPU 1a HDMI/DP", .patch
= patch_nvhdmi
},
3331 { .id
= 0x10de001b, .name
= "GPU 1b HDMI/DP", .patch
= patch_nvhdmi
},
3332 { .id
= 0x10de001c, .name
= "GPU 1c HDMI/DP", .patch
= patch_nvhdmi
},
3333 { .id
= 0x10de0028, .name
= "Tegra12x HDMI", .patch
= patch_nvhdmi
},
3334 { .id
= 0x10de0040, .name
= "GPU 40 HDMI/DP", .patch
= patch_nvhdmi
},
3335 { .id
= 0x10de0041, .name
= "GPU 41 HDMI/DP", .patch
= patch_nvhdmi
},
3336 { .id
= 0x10de0042, .name
= "GPU 42 HDMI/DP", .patch
= patch_nvhdmi
},
3337 { .id
= 0x10de0043, .name
= "GPU 43 HDMI/DP", .patch
= patch_nvhdmi
},
3338 { .id
= 0x10de0044, .name
= "GPU 44 HDMI/DP", .patch
= patch_nvhdmi
},
3339 { .id
= 0x10de0051, .name
= "GPU 51 HDMI/DP", .patch
= patch_nvhdmi
},
3340 { .id
= 0x10de0060, .name
= "GPU 60 HDMI/DP", .patch
= patch_nvhdmi
},
3341 { .id
= 0x10de0067, .name
= "MCP67 HDMI", .patch
= patch_nvhdmi_2ch
},
3342 { .id
= 0x10de0070, .name
= "GPU 70 HDMI/DP", .patch
= patch_nvhdmi
},
3343 { .id
= 0x10de0071, .name
= "GPU 71 HDMI/DP", .patch
= patch_nvhdmi
},
3344 { .id
= 0x10de0072, .name
= "GPU 72 HDMI/DP", .patch
= patch_nvhdmi
},
3345 { .id
= 0x10de8001, .name
= "MCP73 HDMI", .patch
= patch_nvhdmi_2ch
},
3346 { .id
= 0x11069f80, .name
= "VX900 HDMI/DP", .patch
= patch_via_hdmi
},
3347 { .id
= 0x11069f81, .name
= "VX900 HDMI/DP", .patch
= patch_via_hdmi
},
3348 { .id
= 0x11069f84, .name
= "VX11 HDMI/DP", .patch
= patch_generic_hdmi
},
3349 { .id
= 0x11069f85, .name
= "VX11 HDMI/DP", .patch
= patch_generic_hdmi
},
3350 { .id
= 0x80860054, .name
= "IbexPeak HDMI", .patch
= patch_generic_hdmi
},
3351 { .id
= 0x80862801, .name
= "Bearlake HDMI", .patch
= patch_generic_hdmi
},
3352 { .id
= 0x80862802, .name
= "Cantiga HDMI", .patch
= patch_generic_hdmi
},
3353 { .id
= 0x80862803, .name
= "Eaglelake HDMI", .patch
= patch_generic_hdmi
},
3354 { .id
= 0x80862804, .name
= "IbexPeak HDMI", .patch
= patch_generic_hdmi
},
3355 { .id
= 0x80862805, .name
= "CougarPoint HDMI", .patch
= patch_generic_hdmi
},
3356 { .id
= 0x80862806, .name
= "PantherPoint HDMI", .patch
= patch_generic_hdmi
},
3357 { .id
= 0x80862807, .name
= "Haswell HDMI", .patch
= patch_generic_hdmi
},
3358 { .id
= 0x80862808, .name
= "Broadwell HDMI", .patch
= patch_generic_hdmi
},
3359 { .id
= 0x80862809, .name
= "Skylake HDMI", .patch
= patch_generic_hdmi
},
3360 { .id
= 0x80862880, .name
= "CedarTrail HDMI", .patch
= patch_generic_hdmi
},
3361 { .id
= 0x80862882, .name
= "Valleyview2 HDMI", .patch
= patch_generic_hdmi
},
3362 { .id
= 0x80862883, .name
= "Braswell HDMI", .patch
= patch_generic_hdmi
},
3363 { .id
= 0x808629fb, .name
= "Crestline HDMI", .patch
= patch_generic_hdmi
},
3364 /* special ID for generic HDMI */
3365 { .id
= HDA_CODEC_ID_GENERIC_HDMI
, .patch
= patch_generic_hdmi
},
3369 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3370 MODULE_ALIAS("snd-hda-codec-id:10027919");
3371 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3372 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3373 MODULE_ALIAS("snd-hda-codec-id:10951390");
3374 MODULE_ALIAS("snd-hda-codec-id:10951392");
3375 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3376 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3377 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3378 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3379 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3380 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3381 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3382 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3383 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3384 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3385 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3386 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3387 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3388 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3389 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3390 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3391 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3392 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3393 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3394 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3395 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3396 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3397 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3398 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3399 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3400 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3401 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3402 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3403 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3404 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3405 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3406 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3407 MODULE_ALIAS("snd-hda-codec-id:10de0072");
3408 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3409 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3410 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3411 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3412 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3413 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3414 MODULE_ALIAS("snd-hda-codec-id:80860054");
3415 MODULE_ALIAS("snd-hda-codec-id:80862801");
3416 MODULE_ALIAS("snd-hda-codec-id:80862802");
3417 MODULE_ALIAS("snd-hda-codec-id:80862803");
3418 MODULE_ALIAS("snd-hda-codec-id:80862804");
3419 MODULE_ALIAS("snd-hda-codec-id:80862805");
3420 MODULE_ALIAS("snd-hda-codec-id:80862806");
3421 MODULE_ALIAS("snd-hda-codec-id:80862807");
3422 MODULE_ALIAS("snd-hda-codec-id:80862808");
3423 MODULE_ALIAS("snd-hda-codec-id:80862809");
3424 MODULE_ALIAS("snd-hda-codec-id:80862880");
3425 MODULE_ALIAS("snd-hda-codec-id:80862882");
3426 MODULE_ALIAS("snd-hda-codec-id:80862883");
3427 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3429 MODULE_LICENSE("GPL");
3430 MODULE_DESCRIPTION("HDMI HD-audio codec");
3431 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3432 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3433 MODULE_ALIAS("snd-hda-codec-atihdmi");
3435 static struct hda_codec_driver hdmi_driver
= {
3436 .preset
= snd_hda_preset_hdmi
,
3439 module_hda_codec_driver(hdmi_driver
);