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ALSA: hda - convert to hda_device_id
[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / patch_hdmi.c
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include "hda_codec.h"
43 #include "hda_local.h"
44 #include "hda_jack.h"
45
46 static bool static_hdmi_pcm;
47 module_param(static_hdmi_pcm, bool, 0644);
48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
50 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
53 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
54 || is_skylake(codec))
55
56 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
57 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
58 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
59
60 struct hdmi_spec_per_cvt {
61 hda_nid_t cvt_nid;
62 int assigned;
63 unsigned int channels_min;
64 unsigned int channels_max;
65 u32 rates;
66 u64 formats;
67 unsigned int maxbps;
68 };
69
70 /* max. connections to a widget */
71 #define HDA_MAX_CONNECTIONS 32
72
73 struct hdmi_spec_per_pin {
74 hda_nid_t pin_nid;
75 int num_mux_nids;
76 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
77 int mux_idx;
78 hda_nid_t cvt_nid;
79
80 struct hda_codec *codec;
81 struct hdmi_eld sink_eld;
82 struct mutex lock;
83 struct delayed_work work;
84 struct snd_kcontrol *eld_ctl;
85 int repoll_count;
86 bool setup; /* the stream has been set up by prepare callback */
87 int channels; /* current number of channels */
88 bool non_pcm;
89 bool chmap_set; /* channel-map override by ALSA API? */
90 unsigned char chmap[8]; /* ALSA API channel-map */
91 #ifdef CONFIG_SND_PROC_FS
92 struct snd_info_entry *proc_entry;
93 #endif
94 };
95
96 struct cea_channel_speaker_allocation;
97
98 /* operations used by generic code that can be overridden by patches */
99 struct hdmi_ops {
100 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
101 unsigned char *buf, int *eld_size);
102
103 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
104 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
105 int asp_slot);
106 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int asp_slot, int channel);
108
109 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int ca, int active_channels, int conn_type);
111
112 /* enable/disable HBR (HD passthrough) */
113 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
114
115 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
116 hda_nid_t pin_nid, u32 stream_tag, int format);
117
118 /* Helpers for producing the channel map TLVs. These can be overridden
119 * for devices that have non-standard mapping requirements. */
120 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
121 int channels);
122 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
123 unsigned int *chmap, int channels);
124
125 /* check that the user-given chmap is supported */
126 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
127 };
128
129 struct hdmi_spec {
130 int num_cvts;
131 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
132 hda_nid_t cvt_nids[4]; /* only for haswell fix */
133
134 int num_pins;
135 struct snd_array pins; /* struct hdmi_spec_per_pin */
136 struct hda_pcm *pcm_rec[16];
137 unsigned int channels_max; /* max over all cvts */
138
139 struct hdmi_eld temp_eld;
140 struct hdmi_ops ops;
141
142 bool dyn_pin_out;
143
144 /*
145 * Non-generic VIA/NVIDIA specific
146 */
147 struct hda_multi_out multiout;
148 struct hda_pcm_stream pcm_playback;
149
150 /* i915/powerwell (Haswell+/Valleyview+) specific */
151 struct i915_audio_component_audio_ops i915_audio_ops;
152 };
153
154
155 struct hdmi_audio_infoframe {
156 u8 type; /* 0x84 */
157 u8 ver; /* 0x01 */
158 u8 len; /* 0x0a */
159
160 u8 checksum;
161
162 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
163 u8 SS01_SF24;
164 u8 CXT04;
165 u8 CA;
166 u8 LFEPBL01_LSV36_DM_INH7;
167 };
168
169 struct dp_audio_infoframe {
170 u8 type; /* 0x84 */
171 u8 len; /* 0x1b */
172 u8 ver; /* 0x11 << 2 */
173
174 u8 CC02_CT47; /* match with HDMI infoframe from this on */
175 u8 SS01_SF24;
176 u8 CXT04;
177 u8 CA;
178 u8 LFEPBL01_LSV36_DM_INH7;
179 };
180
181 union audio_infoframe {
182 struct hdmi_audio_infoframe hdmi;
183 struct dp_audio_infoframe dp;
184 u8 bytes[0];
185 };
186
187 /*
188 * CEA speaker placement:
189 *
190 * FLH FCH FRH
191 * FLW FL FLC FC FRC FR FRW
192 *
193 * LFE
194 * TC
195 *
196 * RL RLC RC RRC RR
197 *
198 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
199 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
200 */
201 enum cea_speaker_placement {
202 FL = (1 << 0), /* Front Left */
203 FC = (1 << 1), /* Front Center */
204 FR = (1 << 2), /* Front Right */
205 FLC = (1 << 3), /* Front Left Center */
206 FRC = (1 << 4), /* Front Right Center */
207 RL = (1 << 5), /* Rear Left */
208 RC = (1 << 6), /* Rear Center */
209 RR = (1 << 7), /* Rear Right */
210 RLC = (1 << 8), /* Rear Left Center */
211 RRC = (1 << 9), /* Rear Right Center */
212 LFE = (1 << 10), /* Low Frequency Effect */
213 FLW = (1 << 11), /* Front Left Wide */
214 FRW = (1 << 12), /* Front Right Wide */
215 FLH = (1 << 13), /* Front Left High */
216 FCH = (1 << 14), /* Front Center High */
217 FRH = (1 << 15), /* Front Right High */
218 TC = (1 << 16), /* Top Center */
219 };
220
221 /*
222 * ELD SA bits in the CEA Speaker Allocation data block
223 */
224 static int eld_speaker_allocation_bits[] = {
225 [0] = FL | FR,
226 [1] = LFE,
227 [2] = FC,
228 [3] = RL | RR,
229 [4] = RC,
230 [5] = FLC | FRC,
231 [6] = RLC | RRC,
232 /* the following are not defined in ELD yet */
233 [7] = FLW | FRW,
234 [8] = FLH | FRH,
235 [9] = TC,
236 [10] = FCH,
237 };
238
239 struct cea_channel_speaker_allocation {
240 int ca_index;
241 int speakers[8];
242
243 /* derived values, just for convenience */
244 int channels;
245 int spk_mask;
246 };
247
248 /*
249 * ALSA sequence is:
250 *
251 * surround40 surround41 surround50 surround51 surround71
252 * ch0 front left = = = =
253 * ch1 front right = = = =
254 * ch2 rear left = = = =
255 * ch3 rear right = = = =
256 * ch4 LFE center center center
257 * ch5 LFE LFE
258 * ch6 side left
259 * ch7 side right
260 *
261 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
262 */
263 static int hdmi_channel_mapping[0x32][8] = {
264 /* stereo */
265 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
266 /* 2.1 */
267 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
268 /* Dolby Surround */
269 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
270 /* surround40 */
271 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
272 /* 4ch */
273 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
274 /* surround41 */
275 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
276 /* surround50 */
277 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
278 /* surround51 */
279 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
280 /* 7.1 */
281 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
282 };
283
284 /*
285 * This is an ordered list!
286 *
287 * The preceding ones have better chances to be selected by
288 * hdmi_channel_allocation().
289 */
290 static struct cea_channel_speaker_allocation channel_allocations[] = {
291 /* channel: 7 6 5 4 3 2 1 0 */
292 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
293 /* 2.1 */
294 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
295 /* Dolby Surround */
296 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
297 /* surround40 */
298 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
299 /* surround41 */
300 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
301 /* surround50 */
302 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
303 /* surround51 */
304 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
305 /* 6.1 */
306 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
307 /* surround71 */
308 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
309
310 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
311 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
312 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
313 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
314 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
315 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
316 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
317 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
318 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
319 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
320 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
321 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
322 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
323 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
324 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
325 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
326 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
327 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
328 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
329 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
330 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
331 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
332 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
333 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
334 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
335 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
336 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
337 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
338 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
339 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
340 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
341 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
342 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
343 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
344 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
345 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
346 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
347 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
348 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
349 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
350 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
351 };
352
353
354 /*
355 * HDMI routines
356 */
357
358 #define get_pin(spec, idx) \
359 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
360 #define get_cvt(spec, idx) \
361 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
362 #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
363
364 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
365 {
366 struct hdmi_spec *spec = codec->spec;
367 int pin_idx;
368
369 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
370 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
371 return pin_idx;
372
373 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
374 return -EINVAL;
375 }
376
377 static int hinfo_to_pin_index(struct hda_codec *codec,
378 struct hda_pcm_stream *hinfo)
379 {
380 struct hdmi_spec *spec = codec->spec;
381 int pin_idx;
382
383 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
384 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
385 return pin_idx;
386
387 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
388 return -EINVAL;
389 }
390
391 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
392 {
393 struct hdmi_spec *spec = codec->spec;
394 int cvt_idx;
395
396 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
397 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
398 return cvt_idx;
399
400 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
401 return -EINVAL;
402 }
403
404 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
405 struct snd_ctl_elem_info *uinfo)
406 {
407 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
408 struct hdmi_spec *spec = codec->spec;
409 struct hdmi_spec_per_pin *per_pin;
410 struct hdmi_eld *eld;
411 int pin_idx;
412
413 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
414
415 pin_idx = kcontrol->private_value;
416 per_pin = get_pin(spec, pin_idx);
417 eld = &per_pin->sink_eld;
418
419 mutex_lock(&per_pin->lock);
420 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
421 mutex_unlock(&per_pin->lock);
422
423 return 0;
424 }
425
426 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
427 struct snd_ctl_elem_value *ucontrol)
428 {
429 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
430 struct hdmi_spec *spec = codec->spec;
431 struct hdmi_spec_per_pin *per_pin;
432 struct hdmi_eld *eld;
433 int pin_idx;
434
435 pin_idx = kcontrol->private_value;
436 per_pin = get_pin(spec, pin_idx);
437 eld = &per_pin->sink_eld;
438
439 mutex_lock(&per_pin->lock);
440 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
441 mutex_unlock(&per_pin->lock);
442 snd_BUG();
443 return -EINVAL;
444 }
445
446 memset(ucontrol->value.bytes.data, 0,
447 ARRAY_SIZE(ucontrol->value.bytes.data));
448 if (eld->eld_valid)
449 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
450 eld->eld_size);
451 mutex_unlock(&per_pin->lock);
452
453 return 0;
454 }
455
456 static struct snd_kcontrol_new eld_bytes_ctl = {
457 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
458 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
459 .name = "ELD",
460 .info = hdmi_eld_ctl_info,
461 .get = hdmi_eld_ctl_get,
462 };
463
464 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
465 int device)
466 {
467 struct snd_kcontrol *kctl;
468 struct hdmi_spec *spec = codec->spec;
469 int err;
470
471 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
472 if (!kctl)
473 return -ENOMEM;
474 kctl->private_value = pin_idx;
475 kctl->id.device = device;
476
477 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
478 if (err < 0)
479 return err;
480
481 get_pin(spec, pin_idx)->eld_ctl = kctl;
482 return 0;
483 }
484
485 #ifdef BE_PARANOID
486 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
487 int *packet_index, int *byte_index)
488 {
489 int val;
490
491 val = snd_hda_codec_read(codec, pin_nid, 0,
492 AC_VERB_GET_HDMI_DIP_INDEX, 0);
493
494 *packet_index = val >> 5;
495 *byte_index = val & 0x1f;
496 }
497 #endif
498
499 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
500 int packet_index, int byte_index)
501 {
502 int val;
503
504 val = (packet_index << 5) | (byte_index & 0x1f);
505
506 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
507 }
508
509 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
510 unsigned char val)
511 {
512 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
513 }
514
515 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
516 {
517 struct hdmi_spec *spec = codec->spec;
518 int pin_out;
519
520 /* Unmute */
521 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
522 snd_hda_codec_write(codec, pin_nid, 0,
523 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
524
525 if (spec->dyn_pin_out)
526 /* Disable pin out until stream is active */
527 pin_out = 0;
528 else
529 /* Enable pin out: some machines with GM965 gets broken output
530 * when the pin is disabled or changed while using with HDMI
531 */
532 pin_out = PIN_OUT;
533
534 snd_hda_codec_write(codec, pin_nid, 0,
535 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
536 }
537
538 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
539 {
540 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
541 AC_VERB_GET_CVT_CHAN_COUNT, 0);
542 }
543
544 static void hdmi_set_channel_count(struct hda_codec *codec,
545 hda_nid_t cvt_nid, int chs)
546 {
547 if (chs != hdmi_get_channel_count(codec, cvt_nid))
548 snd_hda_codec_write(codec, cvt_nid, 0,
549 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
550 }
551
552 /*
553 * ELD proc files
554 */
555
556 #ifdef CONFIG_SND_PROC_FS
557 static void print_eld_info(struct snd_info_entry *entry,
558 struct snd_info_buffer *buffer)
559 {
560 struct hdmi_spec_per_pin *per_pin = entry->private_data;
561
562 mutex_lock(&per_pin->lock);
563 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
564 mutex_unlock(&per_pin->lock);
565 }
566
567 static void write_eld_info(struct snd_info_entry *entry,
568 struct snd_info_buffer *buffer)
569 {
570 struct hdmi_spec_per_pin *per_pin = entry->private_data;
571
572 mutex_lock(&per_pin->lock);
573 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
574 mutex_unlock(&per_pin->lock);
575 }
576
577 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
578 {
579 char name[32];
580 struct hda_codec *codec = per_pin->codec;
581 struct snd_info_entry *entry;
582 int err;
583
584 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
585 err = snd_card_proc_new(codec->card, name, &entry);
586 if (err < 0)
587 return err;
588
589 snd_info_set_text_ops(entry, per_pin, print_eld_info);
590 entry->c.text.write = write_eld_info;
591 entry->mode |= S_IWUSR;
592 per_pin->proc_entry = entry;
593
594 return 0;
595 }
596
597 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
598 {
599 if (!per_pin->codec->bus->shutdown) {
600 snd_info_free_entry(per_pin->proc_entry);
601 per_pin->proc_entry = NULL;
602 }
603 }
604 #else
605 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
606 int index)
607 {
608 return 0;
609 }
610 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
611 {
612 }
613 #endif
614
615 /*
616 * Channel mapping routines
617 */
618
619 /*
620 * Compute derived values in channel_allocations[].
621 */
622 static void init_channel_allocations(void)
623 {
624 int i, j;
625 struct cea_channel_speaker_allocation *p;
626
627 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
628 p = channel_allocations + i;
629 p->channels = 0;
630 p->spk_mask = 0;
631 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
632 if (p->speakers[j]) {
633 p->channels++;
634 p->spk_mask |= p->speakers[j];
635 }
636 }
637 }
638
639 static int get_channel_allocation_order(int ca)
640 {
641 int i;
642
643 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
644 if (channel_allocations[i].ca_index == ca)
645 break;
646 }
647 return i;
648 }
649
650 /*
651 * The transformation takes two steps:
652 *
653 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
654 * spk_mask => (channel_allocations[]) => ai->CA
655 *
656 * TODO: it could select the wrong CA from multiple candidates.
657 */
658 static int hdmi_channel_allocation(struct hda_codec *codec,
659 struct hdmi_eld *eld, int channels)
660 {
661 int i;
662 int ca = 0;
663 int spk_mask = 0;
664 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
665
666 /*
667 * CA defaults to 0 for basic stereo audio
668 */
669 if (channels <= 2)
670 return 0;
671
672 /*
673 * expand ELD's speaker allocation mask
674 *
675 * ELD tells the speaker mask in a compact(paired) form,
676 * expand ELD's notions to match the ones used by Audio InfoFrame.
677 */
678 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
679 if (eld->info.spk_alloc & (1 << i))
680 spk_mask |= eld_speaker_allocation_bits[i];
681 }
682
683 /* search for the first working match in the CA table */
684 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
685 if (channels == channel_allocations[i].channels &&
686 (spk_mask & channel_allocations[i].spk_mask) ==
687 channel_allocations[i].spk_mask) {
688 ca = channel_allocations[i].ca_index;
689 break;
690 }
691 }
692
693 if (!ca) {
694 /* if there was no match, select the regular ALSA channel
695 * allocation with the matching number of channels */
696 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
697 if (channels == channel_allocations[i].channels) {
698 ca = channel_allocations[i].ca_index;
699 break;
700 }
701 }
702 }
703
704 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
705 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
706 ca, channels, buf);
707
708 return ca;
709 }
710
711 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
712 hda_nid_t pin_nid)
713 {
714 #ifdef CONFIG_SND_DEBUG_VERBOSE
715 struct hdmi_spec *spec = codec->spec;
716 int i;
717 int channel;
718
719 for (i = 0; i < 8; i++) {
720 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
721 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
722 channel, i);
723 }
724 #endif
725 }
726
727 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
728 hda_nid_t pin_nid,
729 bool non_pcm,
730 int ca)
731 {
732 struct hdmi_spec *spec = codec->spec;
733 struct cea_channel_speaker_allocation *ch_alloc;
734 int i;
735 int err;
736 int order;
737 int non_pcm_mapping[8];
738
739 order = get_channel_allocation_order(ca);
740 ch_alloc = &channel_allocations[order];
741
742 if (hdmi_channel_mapping[ca][1] == 0) {
743 int hdmi_slot = 0;
744 /* fill actual channel mappings in ALSA channel (i) order */
745 for (i = 0; i < ch_alloc->channels; i++) {
746 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
747 hdmi_slot++; /* skip zero slots */
748
749 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
750 }
751 /* fill the rest of the slots with ALSA channel 0xf */
752 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
753 if (!ch_alloc->speakers[7 - hdmi_slot])
754 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
755 }
756
757 if (non_pcm) {
758 for (i = 0; i < ch_alloc->channels; i++)
759 non_pcm_mapping[i] = (i << 4) | i;
760 for (; i < 8; i++)
761 non_pcm_mapping[i] = (0xf << 4) | i;
762 }
763
764 for (i = 0; i < 8; i++) {
765 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
766 int hdmi_slot = slotsetup & 0x0f;
767 int channel = (slotsetup & 0xf0) >> 4;
768 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
769 if (err) {
770 codec_dbg(codec, "HDMI: channel mapping failed\n");
771 break;
772 }
773 }
774 }
775
776 struct channel_map_table {
777 unsigned char map; /* ALSA API channel map position */
778 int spk_mask; /* speaker position bit mask */
779 };
780
781 static struct channel_map_table map_tables[] = {
782 { SNDRV_CHMAP_FL, FL },
783 { SNDRV_CHMAP_FR, FR },
784 { SNDRV_CHMAP_RL, RL },
785 { SNDRV_CHMAP_RR, RR },
786 { SNDRV_CHMAP_LFE, LFE },
787 { SNDRV_CHMAP_FC, FC },
788 { SNDRV_CHMAP_RLC, RLC },
789 { SNDRV_CHMAP_RRC, RRC },
790 { SNDRV_CHMAP_RC, RC },
791 { SNDRV_CHMAP_FLC, FLC },
792 { SNDRV_CHMAP_FRC, FRC },
793 { SNDRV_CHMAP_TFL, FLH },
794 { SNDRV_CHMAP_TFR, FRH },
795 { SNDRV_CHMAP_FLW, FLW },
796 { SNDRV_CHMAP_FRW, FRW },
797 { SNDRV_CHMAP_TC, TC },
798 { SNDRV_CHMAP_TFC, FCH },
799 {} /* terminator */
800 };
801
802 /* from ALSA API channel position to speaker bit mask */
803 static int to_spk_mask(unsigned char c)
804 {
805 struct channel_map_table *t = map_tables;
806 for (; t->map; t++) {
807 if (t->map == c)
808 return t->spk_mask;
809 }
810 return 0;
811 }
812
813 /* from ALSA API channel position to CEA slot */
814 static int to_cea_slot(int ordered_ca, unsigned char pos)
815 {
816 int mask = to_spk_mask(pos);
817 int i;
818
819 if (mask) {
820 for (i = 0; i < 8; i++) {
821 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
822 return i;
823 }
824 }
825
826 return -1;
827 }
828
829 /* from speaker bit mask to ALSA API channel position */
830 static int spk_to_chmap(int spk)
831 {
832 struct channel_map_table *t = map_tables;
833 for (; t->map; t++) {
834 if (t->spk_mask == spk)
835 return t->map;
836 }
837 return 0;
838 }
839
840 /* from CEA slot to ALSA API channel position */
841 static int from_cea_slot(int ordered_ca, unsigned char slot)
842 {
843 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
844
845 return spk_to_chmap(mask);
846 }
847
848 /* get the CA index corresponding to the given ALSA API channel map */
849 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
850 {
851 int i, spks = 0, spk_mask = 0;
852
853 for (i = 0; i < chs; i++) {
854 int mask = to_spk_mask(map[i]);
855 if (mask) {
856 spk_mask |= mask;
857 spks++;
858 }
859 }
860
861 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
862 if ((chs == channel_allocations[i].channels ||
863 spks == channel_allocations[i].channels) &&
864 (spk_mask & channel_allocations[i].spk_mask) ==
865 channel_allocations[i].spk_mask)
866 return channel_allocations[i].ca_index;
867 }
868 return -1;
869 }
870
871 /* set up the channel slots for the given ALSA API channel map */
872 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
873 hda_nid_t pin_nid,
874 int chs, unsigned char *map,
875 int ca)
876 {
877 struct hdmi_spec *spec = codec->spec;
878 int ordered_ca = get_channel_allocation_order(ca);
879 int alsa_pos, hdmi_slot;
880 int assignments[8] = {[0 ... 7] = 0xf};
881
882 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
883
884 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
885
886 if (hdmi_slot < 0)
887 continue; /* unassigned channel */
888
889 assignments[hdmi_slot] = alsa_pos;
890 }
891
892 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
893 int err;
894
895 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
896 assignments[hdmi_slot]);
897 if (err)
898 return -EINVAL;
899 }
900 return 0;
901 }
902
903 /* store ALSA API channel map from the current default map */
904 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
905 {
906 int i;
907 int ordered_ca = get_channel_allocation_order(ca);
908 for (i = 0; i < 8; i++) {
909 if (i < channel_allocations[ordered_ca].channels)
910 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
911 else
912 map[i] = 0;
913 }
914 }
915
916 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
917 hda_nid_t pin_nid, bool non_pcm, int ca,
918 int channels, unsigned char *map,
919 bool chmap_set)
920 {
921 if (!non_pcm && chmap_set) {
922 hdmi_manual_setup_channel_mapping(codec, pin_nid,
923 channels, map, ca);
924 } else {
925 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
926 hdmi_setup_fake_chmap(map, ca);
927 }
928
929 hdmi_debug_channel_mapping(codec, pin_nid);
930 }
931
932 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
933 int asp_slot, int channel)
934 {
935 return snd_hda_codec_write(codec, pin_nid, 0,
936 AC_VERB_SET_HDMI_CHAN_SLOT,
937 (channel << 4) | asp_slot);
938 }
939
940 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
941 int asp_slot)
942 {
943 return (snd_hda_codec_read(codec, pin_nid, 0,
944 AC_VERB_GET_HDMI_CHAN_SLOT,
945 asp_slot) & 0xf0) >> 4;
946 }
947
948 /*
949 * Audio InfoFrame routines
950 */
951
952 /*
953 * Enable Audio InfoFrame Transmission
954 */
955 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
956 hda_nid_t pin_nid)
957 {
958 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
959 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
960 AC_DIPXMIT_BEST);
961 }
962
963 /*
964 * Disable Audio InfoFrame Transmission
965 */
966 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
967 hda_nid_t pin_nid)
968 {
969 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
970 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
971 AC_DIPXMIT_DISABLE);
972 }
973
974 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
975 {
976 #ifdef CONFIG_SND_DEBUG_VERBOSE
977 int i;
978 int size;
979
980 size = snd_hdmi_get_eld_size(codec, pin_nid);
981 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
982
983 for (i = 0; i < 8; i++) {
984 size = snd_hda_codec_read(codec, pin_nid, 0,
985 AC_VERB_GET_HDMI_DIP_SIZE, i);
986 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
987 }
988 #endif
989 }
990
991 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
992 {
993 #ifdef BE_PARANOID
994 int i, j;
995 int size;
996 int pi, bi;
997 for (i = 0; i < 8; i++) {
998 size = snd_hda_codec_read(codec, pin_nid, 0,
999 AC_VERB_GET_HDMI_DIP_SIZE, i);
1000 if (size == 0)
1001 continue;
1002
1003 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1004 for (j = 1; j < 1000; j++) {
1005 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1006 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1007 if (pi != i)
1008 codec_dbg(codec, "dip index %d: %d != %d\n",
1009 bi, pi, i);
1010 if (bi == 0) /* byte index wrapped around */
1011 break;
1012 }
1013 codec_dbg(codec,
1014 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1015 i, size, j);
1016 }
1017 #endif
1018 }
1019
1020 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1021 {
1022 u8 *bytes = (u8 *)hdmi_ai;
1023 u8 sum = 0;
1024 int i;
1025
1026 hdmi_ai->checksum = 0;
1027
1028 for (i = 0; i < sizeof(*hdmi_ai); i++)
1029 sum += bytes[i];
1030
1031 hdmi_ai->checksum = -sum;
1032 }
1033
1034 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1035 hda_nid_t pin_nid,
1036 u8 *dip, int size)
1037 {
1038 int i;
1039
1040 hdmi_debug_dip_size(codec, pin_nid);
1041 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1042
1043 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1044 for (i = 0; i < size; i++)
1045 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1046 }
1047
1048 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1049 u8 *dip, int size)
1050 {
1051 u8 val;
1052 int i;
1053
1054 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1055 != AC_DIPXMIT_BEST)
1056 return false;
1057
1058 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1059 for (i = 0; i < size; i++) {
1060 val = snd_hda_codec_read(codec, pin_nid, 0,
1061 AC_VERB_GET_HDMI_DIP_DATA, 0);
1062 if (val != dip[i])
1063 return false;
1064 }
1065
1066 return true;
1067 }
1068
1069 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1070 hda_nid_t pin_nid,
1071 int ca, int active_channels,
1072 int conn_type)
1073 {
1074 union audio_infoframe ai;
1075
1076 memset(&ai, 0, sizeof(ai));
1077 if (conn_type == 0) { /* HDMI */
1078 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1079
1080 hdmi_ai->type = 0x84;
1081 hdmi_ai->ver = 0x01;
1082 hdmi_ai->len = 0x0a;
1083 hdmi_ai->CC02_CT47 = active_channels - 1;
1084 hdmi_ai->CA = ca;
1085 hdmi_checksum_audio_infoframe(hdmi_ai);
1086 } else if (conn_type == 1) { /* DisplayPort */
1087 struct dp_audio_infoframe *dp_ai = &ai.dp;
1088
1089 dp_ai->type = 0x84;
1090 dp_ai->len = 0x1b;
1091 dp_ai->ver = 0x11 << 2;
1092 dp_ai->CC02_CT47 = active_channels - 1;
1093 dp_ai->CA = ca;
1094 } else {
1095 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1096 pin_nid);
1097 return;
1098 }
1099
1100 /*
1101 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1102 * sizeof(*dp_ai) to avoid partial match/update problems when
1103 * the user switches between HDMI/DP monitors.
1104 */
1105 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1106 sizeof(ai))) {
1107 codec_dbg(codec,
1108 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1109 pin_nid,
1110 active_channels, ca);
1111 hdmi_stop_infoframe_trans(codec, pin_nid);
1112 hdmi_fill_audio_infoframe(codec, pin_nid,
1113 ai.bytes, sizeof(ai));
1114 hdmi_start_infoframe_trans(codec, pin_nid);
1115 }
1116 }
1117
1118 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1119 struct hdmi_spec_per_pin *per_pin,
1120 bool non_pcm)
1121 {
1122 struct hdmi_spec *spec = codec->spec;
1123 hda_nid_t pin_nid = per_pin->pin_nid;
1124 int channels = per_pin->channels;
1125 int active_channels;
1126 struct hdmi_eld *eld;
1127 int ca, ordered_ca;
1128
1129 if (!channels)
1130 return;
1131
1132 if (is_haswell_plus(codec))
1133 snd_hda_codec_write(codec, pin_nid, 0,
1134 AC_VERB_SET_AMP_GAIN_MUTE,
1135 AMP_OUT_UNMUTE);
1136
1137 eld = &per_pin->sink_eld;
1138
1139 if (!non_pcm && per_pin->chmap_set)
1140 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1141 else
1142 ca = hdmi_channel_allocation(codec, eld, channels);
1143 if (ca < 0)
1144 ca = 0;
1145
1146 ordered_ca = get_channel_allocation_order(ca);
1147 active_channels = channel_allocations[ordered_ca].channels;
1148
1149 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1150
1151 /*
1152 * always configure channel mapping, it may have been changed by the
1153 * user in the meantime
1154 */
1155 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1156 channels, per_pin->chmap,
1157 per_pin->chmap_set);
1158
1159 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1160 eld->info.conn_type);
1161
1162 per_pin->non_pcm = non_pcm;
1163 }
1164
1165 /*
1166 * Unsolicited events
1167 */
1168
1169 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1170
1171 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1172 {
1173 struct hdmi_spec *spec = codec->spec;
1174 int pin_idx = pin_nid_to_pin_index(codec, nid);
1175
1176 if (pin_idx < 0)
1177 return;
1178 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1179 snd_hda_jack_report_sync(codec);
1180 }
1181
1182 static void jack_callback(struct hda_codec *codec,
1183 struct hda_jack_callback *jack)
1184 {
1185 check_presence_and_report(codec, jack->tbl->nid);
1186 }
1187
1188 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1189 {
1190 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1191 struct hda_jack_tbl *jack;
1192 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1193
1194 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1195 if (!jack)
1196 return;
1197 jack->jack_dirty = 1;
1198
1199 codec_dbg(codec,
1200 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1201 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1202 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1203
1204 check_presence_and_report(codec, jack->nid);
1205 }
1206
1207 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1208 {
1209 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1210 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1211 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1212 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1213
1214 codec_info(codec,
1215 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1216 codec->addr,
1217 tag,
1218 subtag,
1219 cp_state,
1220 cp_ready);
1221
1222 /* TODO */
1223 if (cp_state)
1224 ;
1225 if (cp_ready)
1226 ;
1227 }
1228
1229
1230 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1231 {
1232 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1233 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1234
1235 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1236 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1237 return;
1238 }
1239
1240 if (subtag == 0)
1241 hdmi_intrinsic_event(codec, res);
1242 else
1243 hdmi_non_intrinsic_event(codec, res);
1244 }
1245
1246 static void haswell_verify_D0(struct hda_codec *codec,
1247 hda_nid_t cvt_nid, hda_nid_t nid)
1248 {
1249 int pwr;
1250
1251 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1252 * thus pins could only choose converter 0 for use. Make sure the
1253 * converters are in correct power state */
1254 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1255 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1256
1257 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1258 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1259 AC_PWRST_D0);
1260 msleep(40);
1261 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1262 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1263 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1264 }
1265 }
1266
1267 /*
1268 * Callbacks
1269 */
1270
1271 /* HBR should be Non-PCM, 8 channels */
1272 #define is_hbr_format(format) \
1273 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1274
1275 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1276 bool hbr)
1277 {
1278 int pinctl, new_pinctl;
1279
1280 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1281 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1282 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1283
1284 if (pinctl < 0)
1285 return hbr ? -EINVAL : 0;
1286
1287 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1288 if (hbr)
1289 new_pinctl |= AC_PINCTL_EPT_HBR;
1290 else
1291 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1292
1293 codec_dbg(codec,
1294 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1295 pin_nid,
1296 pinctl == new_pinctl ? "" : "new-",
1297 new_pinctl);
1298
1299 if (pinctl != new_pinctl)
1300 snd_hda_codec_write(codec, pin_nid, 0,
1301 AC_VERB_SET_PIN_WIDGET_CONTROL,
1302 new_pinctl);
1303 } else if (hbr)
1304 return -EINVAL;
1305
1306 return 0;
1307 }
1308
1309 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1310 hda_nid_t pin_nid, u32 stream_tag, int format)
1311 {
1312 struct hdmi_spec *spec = codec->spec;
1313 int err;
1314
1315 if (is_haswell_plus(codec))
1316 haswell_verify_D0(codec, cvt_nid, pin_nid);
1317
1318 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1319
1320 if (err) {
1321 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1322 return err;
1323 }
1324
1325 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1326 return 0;
1327 }
1328
1329 static int hdmi_choose_cvt(struct hda_codec *codec,
1330 int pin_idx, int *cvt_id, int *mux_id)
1331 {
1332 struct hdmi_spec *spec = codec->spec;
1333 struct hdmi_spec_per_pin *per_pin;
1334 struct hdmi_spec_per_cvt *per_cvt = NULL;
1335 int cvt_idx, mux_idx = 0;
1336
1337 per_pin = get_pin(spec, pin_idx);
1338
1339 /* Dynamically assign converter to stream */
1340 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1341 per_cvt = get_cvt(spec, cvt_idx);
1342
1343 /* Must not already be assigned */
1344 if (per_cvt->assigned)
1345 continue;
1346 /* Must be in pin's mux's list of converters */
1347 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1348 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1349 break;
1350 /* Not in mux list */
1351 if (mux_idx == per_pin->num_mux_nids)
1352 continue;
1353 break;
1354 }
1355
1356 /* No free converters */
1357 if (cvt_idx == spec->num_cvts)
1358 return -ENODEV;
1359
1360 per_pin->mux_idx = mux_idx;
1361
1362 if (cvt_id)
1363 *cvt_id = cvt_idx;
1364 if (mux_id)
1365 *mux_id = mux_idx;
1366
1367 return 0;
1368 }
1369
1370 /* Assure the pin select the right convetor */
1371 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1372 struct hdmi_spec_per_pin *per_pin)
1373 {
1374 hda_nid_t pin_nid = per_pin->pin_nid;
1375 int mux_idx, curr;
1376
1377 mux_idx = per_pin->mux_idx;
1378 curr = snd_hda_codec_read(codec, pin_nid, 0,
1379 AC_VERB_GET_CONNECT_SEL, 0);
1380 if (curr != mux_idx)
1381 snd_hda_codec_write_cache(codec, pin_nid, 0,
1382 AC_VERB_SET_CONNECT_SEL,
1383 mux_idx);
1384 }
1385
1386 /* Intel HDMI workaround to fix audio routing issue:
1387 * For some Intel display codecs, pins share the same connection list.
1388 * So a conveter can be selected by multiple pins and playback on any of these
1389 * pins will generate sound on the external display, because audio flows from
1390 * the same converter to the display pipeline. Also muting one pin may make
1391 * other pins have no sound output.
1392 * So this function assures that an assigned converter for a pin is not selected
1393 * by any other pins.
1394 */
1395 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1396 hda_nid_t pin_nid, int mux_idx)
1397 {
1398 struct hdmi_spec *spec = codec->spec;
1399 hda_nid_t nid;
1400 int cvt_idx, curr;
1401 struct hdmi_spec_per_cvt *per_cvt;
1402
1403 /* configure all pins, including "no physical connection" ones */
1404 for_each_hda_codec_node(nid, codec) {
1405 unsigned int wid_caps = get_wcaps(codec, nid);
1406 unsigned int wid_type = get_wcaps_type(wid_caps);
1407
1408 if (wid_type != AC_WID_PIN)
1409 continue;
1410
1411 if (nid == pin_nid)
1412 continue;
1413
1414 curr = snd_hda_codec_read(codec, nid, 0,
1415 AC_VERB_GET_CONNECT_SEL, 0);
1416 if (curr != mux_idx)
1417 continue;
1418
1419 /* choose an unassigned converter. The conveters in the
1420 * connection list are in the same order as in the codec.
1421 */
1422 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1423 per_cvt = get_cvt(spec, cvt_idx);
1424 if (!per_cvt->assigned) {
1425 codec_dbg(codec,
1426 "choose cvt %d for pin nid %d\n",
1427 cvt_idx, nid);
1428 snd_hda_codec_write_cache(codec, nid, 0,
1429 AC_VERB_SET_CONNECT_SEL,
1430 cvt_idx);
1431 break;
1432 }
1433 }
1434 }
1435 }
1436
1437 /*
1438 * HDA PCM callbacks
1439 */
1440 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1441 struct hda_codec *codec,
1442 struct snd_pcm_substream *substream)
1443 {
1444 struct hdmi_spec *spec = codec->spec;
1445 struct snd_pcm_runtime *runtime = substream->runtime;
1446 int pin_idx, cvt_idx, mux_idx = 0;
1447 struct hdmi_spec_per_pin *per_pin;
1448 struct hdmi_eld *eld;
1449 struct hdmi_spec_per_cvt *per_cvt = NULL;
1450 int err;
1451
1452 /* Validate hinfo */
1453 pin_idx = hinfo_to_pin_index(codec, hinfo);
1454 if (snd_BUG_ON(pin_idx < 0))
1455 return -EINVAL;
1456 per_pin = get_pin(spec, pin_idx);
1457 eld = &per_pin->sink_eld;
1458
1459 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1460 if (err < 0)
1461 return err;
1462
1463 per_cvt = get_cvt(spec, cvt_idx);
1464 /* Claim converter */
1465 per_cvt->assigned = 1;
1466 per_pin->cvt_nid = per_cvt->cvt_nid;
1467 hinfo->nid = per_cvt->cvt_nid;
1468
1469 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1470 AC_VERB_SET_CONNECT_SEL,
1471 mux_idx);
1472
1473 /* configure unused pins to choose other converters */
1474 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1475 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1476
1477 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1478
1479 /* Initially set the converter's capabilities */
1480 hinfo->channels_min = per_cvt->channels_min;
1481 hinfo->channels_max = per_cvt->channels_max;
1482 hinfo->rates = per_cvt->rates;
1483 hinfo->formats = per_cvt->formats;
1484 hinfo->maxbps = per_cvt->maxbps;
1485
1486 /* Restrict capabilities by ELD if this isn't disabled */
1487 if (!static_hdmi_pcm && eld->eld_valid) {
1488 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1489 if (hinfo->channels_min > hinfo->channels_max ||
1490 !hinfo->rates || !hinfo->formats) {
1491 per_cvt->assigned = 0;
1492 hinfo->nid = 0;
1493 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1494 return -ENODEV;
1495 }
1496 }
1497
1498 /* Store the updated parameters */
1499 runtime->hw.channels_min = hinfo->channels_min;
1500 runtime->hw.channels_max = hinfo->channels_max;
1501 runtime->hw.formats = hinfo->formats;
1502 runtime->hw.rates = hinfo->rates;
1503
1504 snd_pcm_hw_constraint_step(substream->runtime, 0,
1505 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1506 return 0;
1507 }
1508
1509 /*
1510 * HDA/HDMI auto parsing
1511 */
1512 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1513 {
1514 struct hdmi_spec *spec = codec->spec;
1515 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1516 hda_nid_t pin_nid = per_pin->pin_nid;
1517
1518 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1519 codec_warn(codec,
1520 "HDMI: pin %d wcaps %#x does not support connection list\n",
1521 pin_nid, get_wcaps(codec, pin_nid));
1522 return -EINVAL;
1523 }
1524
1525 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1526 per_pin->mux_nids,
1527 HDA_MAX_CONNECTIONS);
1528
1529 return 0;
1530 }
1531
1532 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1533 {
1534 struct hda_jack_tbl *jack;
1535 struct hda_codec *codec = per_pin->codec;
1536 struct hdmi_spec *spec = codec->spec;
1537 struct hdmi_eld *eld = &spec->temp_eld;
1538 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1539 hda_nid_t pin_nid = per_pin->pin_nid;
1540 /*
1541 * Always execute a GetPinSense verb here, even when called from
1542 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1543 * response's PD bit is not the real PD value, but indicates that
1544 * the real PD value changed. An older version of the HD-audio
1545 * specification worked this way. Hence, we just ignore the data in
1546 * the unsolicited response to avoid custom WARs.
1547 */
1548 int present;
1549 bool update_eld = false;
1550 bool eld_changed = false;
1551 bool ret;
1552
1553 snd_hda_power_up_pm(codec);
1554 present = snd_hda_pin_sense(codec, pin_nid);
1555
1556 mutex_lock(&per_pin->lock);
1557 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1558 if (pin_eld->monitor_present)
1559 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1560 else
1561 eld->eld_valid = false;
1562
1563 codec_dbg(codec,
1564 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1565 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1566
1567 if (eld->eld_valid) {
1568 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1569 &eld->eld_size) < 0)
1570 eld->eld_valid = false;
1571 else {
1572 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1573 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1574 eld->eld_size) < 0)
1575 eld->eld_valid = false;
1576 }
1577
1578 if (eld->eld_valid) {
1579 snd_hdmi_show_eld(codec, &eld->info);
1580 update_eld = true;
1581 }
1582 else if (repoll) {
1583 schedule_delayed_work(&per_pin->work,
1584 msecs_to_jiffies(300));
1585 goto unlock;
1586 }
1587 }
1588
1589 if (pin_eld->eld_valid != eld->eld_valid)
1590 eld_changed = true;
1591
1592 if (pin_eld->eld_valid && !eld->eld_valid)
1593 update_eld = true;
1594
1595 if (update_eld) {
1596 bool old_eld_valid = pin_eld->eld_valid;
1597 pin_eld->eld_valid = eld->eld_valid;
1598 if (pin_eld->eld_size != eld->eld_size ||
1599 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1600 eld->eld_size) != 0) {
1601 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1602 eld->eld_size);
1603 eld_changed = true;
1604 }
1605 pin_eld->eld_size = eld->eld_size;
1606 pin_eld->info = eld->info;
1607
1608 /*
1609 * Re-setup pin and infoframe. This is needed e.g. when
1610 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1611 * - transcoder can change during stream playback on Haswell
1612 * and this can make HW reset converter selection on a pin.
1613 */
1614 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1615 if (is_haswell_plus(codec) ||
1616 is_valleyview_plus(codec)) {
1617 intel_verify_pin_cvt_connect(codec, per_pin);
1618 intel_not_share_assigned_cvt(codec, pin_nid,
1619 per_pin->mux_idx);
1620 }
1621
1622 hdmi_setup_audio_infoframe(codec, per_pin,
1623 per_pin->non_pcm);
1624 }
1625 }
1626
1627 if (eld_changed)
1628 snd_ctl_notify(codec->card,
1629 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1630 &per_pin->eld_ctl->id);
1631 unlock:
1632 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1633
1634 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1635 if (jack)
1636 jack->block_report = !ret;
1637
1638 mutex_unlock(&per_pin->lock);
1639 snd_hda_power_down_pm(codec);
1640 return ret;
1641 }
1642
1643 static void hdmi_repoll_eld(struct work_struct *work)
1644 {
1645 struct hdmi_spec_per_pin *per_pin =
1646 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1647
1648 if (per_pin->repoll_count++ > 6)
1649 per_pin->repoll_count = 0;
1650
1651 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1652 snd_hda_jack_report_sync(per_pin->codec);
1653 }
1654
1655 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1656 hda_nid_t nid);
1657
1658 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1659 {
1660 struct hdmi_spec *spec = codec->spec;
1661 unsigned int caps, config;
1662 int pin_idx;
1663 struct hdmi_spec_per_pin *per_pin;
1664 int err;
1665
1666 caps = snd_hda_query_pin_caps(codec, pin_nid);
1667 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1668 return 0;
1669
1670 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1671 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1672 return 0;
1673
1674 if (is_haswell_plus(codec))
1675 intel_haswell_fixup_connect_list(codec, pin_nid);
1676
1677 pin_idx = spec->num_pins;
1678 per_pin = snd_array_new(&spec->pins);
1679 if (!per_pin)
1680 return -ENOMEM;
1681
1682 per_pin->pin_nid = pin_nid;
1683 per_pin->non_pcm = false;
1684
1685 err = hdmi_read_pin_conn(codec, pin_idx);
1686 if (err < 0)
1687 return err;
1688
1689 spec->num_pins++;
1690
1691 return 0;
1692 }
1693
1694 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1695 {
1696 struct hdmi_spec *spec = codec->spec;
1697 struct hdmi_spec_per_cvt *per_cvt;
1698 unsigned int chans;
1699 int err;
1700
1701 chans = get_wcaps(codec, cvt_nid);
1702 chans = get_wcaps_channels(chans);
1703
1704 per_cvt = snd_array_new(&spec->cvts);
1705 if (!per_cvt)
1706 return -ENOMEM;
1707
1708 per_cvt->cvt_nid = cvt_nid;
1709 per_cvt->channels_min = 2;
1710 if (chans <= 16) {
1711 per_cvt->channels_max = chans;
1712 if (chans > spec->channels_max)
1713 spec->channels_max = chans;
1714 }
1715
1716 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1717 &per_cvt->rates,
1718 &per_cvt->formats,
1719 &per_cvt->maxbps);
1720 if (err < 0)
1721 return err;
1722
1723 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1724 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1725 spec->num_cvts++;
1726
1727 return 0;
1728 }
1729
1730 static int hdmi_parse_codec(struct hda_codec *codec)
1731 {
1732 hda_nid_t nid;
1733 int i, nodes;
1734
1735 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1736 if (!nid || nodes < 0) {
1737 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1738 return -EINVAL;
1739 }
1740
1741 for (i = 0; i < nodes; i++, nid++) {
1742 unsigned int caps;
1743 unsigned int type;
1744
1745 caps = get_wcaps(codec, nid);
1746 type = get_wcaps_type(caps);
1747
1748 if (!(caps & AC_WCAP_DIGITAL))
1749 continue;
1750
1751 switch (type) {
1752 case AC_WID_AUD_OUT:
1753 hdmi_add_cvt(codec, nid);
1754 break;
1755 case AC_WID_PIN:
1756 hdmi_add_pin(codec, nid);
1757 break;
1758 }
1759 }
1760
1761 return 0;
1762 }
1763
1764 /*
1765 */
1766 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1767 {
1768 struct hda_spdif_out *spdif;
1769 bool non_pcm;
1770
1771 mutex_lock(&codec->spdif_mutex);
1772 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1773 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1774 mutex_unlock(&codec->spdif_mutex);
1775 return non_pcm;
1776 }
1777
1778 /* There is a fixed mapping between audio pin node and display port
1779 * on current Intel platforms:
1780 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
1781 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
1782 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
1783 */
1784 static int intel_pin2port(hda_nid_t pin_nid)
1785 {
1786 return pin_nid - 4;
1787 }
1788
1789 /*
1790 * HDMI callbacks
1791 */
1792
1793 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1794 struct hda_codec *codec,
1795 unsigned int stream_tag,
1796 unsigned int format,
1797 struct snd_pcm_substream *substream)
1798 {
1799 hda_nid_t cvt_nid = hinfo->nid;
1800 struct hdmi_spec *spec = codec->spec;
1801 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1802 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1803 hda_nid_t pin_nid = per_pin->pin_nid;
1804 struct snd_pcm_runtime *runtime = substream->runtime;
1805 struct i915_audio_component *acomp = codec->bus->core.audio_component;
1806 bool non_pcm;
1807 int pinctl;
1808
1809 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1810 /* Verify pin:cvt selections to avoid silent audio after S3.
1811 * After S3, the audio driver restores pin:cvt selections
1812 * but this can happen before gfx is ready and such selection
1813 * is overlooked by HW. Thus multiple pins can share a same
1814 * default convertor and mute control will affect each other,
1815 * which can cause a resumed audio playback become silent
1816 * after S3.
1817 */
1818 intel_verify_pin_cvt_connect(codec, per_pin);
1819 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1820 }
1821
1822 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1823 /* Todo: add DP1.2 MST audio support later */
1824 if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
1825 acomp->ops->sync_audio_rate(acomp->dev,
1826 intel_pin2port(pin_nid),
1827 runtime->rate);
1828
1829 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1830 mutex_lock(&per_pin->lock);
1831 per_pin->channels = substream->runtime->channels;
1832 per_pin->setup = true;
1833
1834 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1835 mutex_unlock(&per_pin->lock);
1836
1837 if (spec->dyn_pin_out) {
1838 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1839 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1840 snd_hda_codec_write(codec, pin_nid, 0,
1841 AC_VERB_SET_PIN_WIDGET_CONTROL,
1842 pinctl | PIN_OUT);
1843 }
1844
1845 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1846 }
1847
1848 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1849 struct hda_codec *codec,
1850 struct snd_pcm_substream *substream)
1851 {
1852 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1853 return 0;
1854 }
1855
1856 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1857 struct hda_codec *codec,
1858 struct snd_pcm_substream *substream)
1859 {
1860 struct hdmi_spec *spec = codec->spec;
1861 int cvt_idx, pin_idx;
1862 struct hdmi_spec_per_cvt *per_cvt;
1863 struct hdmi_spec_per_pin *per_pin;
1864 int pinctl;
1865
1866 if (hinfo->nid) {
1867 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1868 if (snd_BUG_ON(cvt_idx < 0))
1869 return -EINVAL;
1870 per_cvt = get_cvt(spec, cvt_idx);
1871
1872 snd_BUG_ON(!per_cvt->assigned);
1873 per_cvt->assigned = 0;
1874 hinfo->nid = 0;
1875
1876 pin_idx = hinfo_to_pin_index(codec, hinfo);
1877 if (snd_BUG_ON(pin_idx < 0))
1878 return -EINVAL;
1879 per_pin = get_pin(spec, pin_idx);
1880
1881 if (spec->dyn_pin_out) {
1882 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1883 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1884 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1885 AC_VERB_SET_PIN_WIDGET_CONTROL,
1886 pinctl & ~PIN_OUT);
1887 }
1888
1889 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1890
1891 mutex_lock(&per_pin->lock);
1892 per_pin->chmap_set = false;
1893 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1894
1895 per_pin->setup = false;
1896 per_pin->channels = 0;
1897 mutex_unlock(&per_pin->lock);
1898 }
1899
1900 return 0;
1901 }
1902
1903 static const struct hda_pcm_ops generic_ops = {
1904 .open = hdmi_pcm_open,
1905 .close = hdmi_pcm_close,
1906 .prepare = generic_hdmi_playback_pcm_prepare,
1907 .cleanup = generic_hdmi_playback_pcm_cleanup,
1908 };
1909
1910 /*
1911 * ALSA API channel-map control callbacks
1912 */
1913 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1914 struct snd_ctl_elem_info *uinfo)
1915 {
1916 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1917 struct hda_codec *codec = info->private_data;
1918 struct hdmi_spec *spec = codec->spec;
1919 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1920 uinfo->count = spec->channels_max;
1921 uinfo->value.integer.min = 0;
1922 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1923 return 0;
1924 }
1925
1926 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1927 int channels)
1928 {
1929 /* If the speaker allocation matches the channel count, it is OK.*/
1930 if (cap->channels != channels)
1931 return -1;
1932
1933 /* all channels are remappable freely */
1934 return SNDRV_CTL_TLVT_CHMAP_VAR;
1935 }
1936
1937 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1938 unsigned int *chmap, int channels)
1939 {
1940 int count = 0;
1941 int c;
1942
1943 for (c = 7; c >= 0; c--) {
1944 int spk = cap->speakers[c];
1945 if (!spk)
1946 continue;
1947
1948 chmap[count++] = spk_to_chmap(spk);
1949 }
1950
1951 WARN_ON(count != channels);
1952 }
1953
1954 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1955 unsigned int size, unsigned int __user *tlv)
1956 {
1957 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1958 struct hda_codec *codec = info->private_data;
1959 struct hdmi_spec *spec = codec->spec;
1960 unsigned int __user *dst;
1961 int chs, count = 0;
1962
1963 if (size < 8)
1964 return -ENOMEM;
1965 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1966 return -EFAULT;
1967 size -= 8;
1968 dst = tlv + 2;
1969 for (chs = 2; chs <= spec->channels_max; chs++) {
1970 int i;
1971 struct cea_channel_speaker_allocation *cap;
1972 cap = channel_allocations;
1973 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1974 int chs_bytes = chs * 4;
1975 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1976 unsigned int tlv_chmap[8];
1977
1978 if (type < 0)
1979 continue;
1980 if (size < 8)
1981 return -ENOMEM;
1982 if (put_user(type, dst) ||
1983 put_user(chs_bytes, dst + 1))
1984 return -EFAULT;
1985 dst += 2;
1986 size -= 8;
1987 count += 8;
1988 if (size < chs_bytes)
1989 return -ENOMEM;
1990 size -= chs_bytes;
1991 count += chs_bytes;
1992 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1993 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1994 return -EFAULT;
1995 dst += chs;
1996 }
1997 }
1998 if (put_user(count, tlv + 1))
1999 return -EFAULT;
2000 return 0;
2001 }
2002
2003 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2004 struct snd_ctl_elem_value *ucontrol)
2005 {
2006 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2007 struct hda_codec *codec = info->private_data;
2008 struct hdmi_spec *spec = codec->spec;
2009 int pin_idx = kcontrol->private_value;
2010 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2011 int i;
2012
2013 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2014 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2015 return 0;
2016 }
2017
2018 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_value *ucontrol)
2020 {
2021 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2022 struct hda_codec *codec = info->private_data;
2023 struct hdmi_spec *spec = codec->spec;
2024 int pin_idx = kcontrol->private_value;
2025 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2026 unsigned int ctl_idx;
2027 struct snd_pcm_substream *substream;
2028 unsigned char chmap[8];
2029 int i, err, ca, prepared = 0;
2030
2031 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2032 substream = snd_pcm_chmap_substream(info, ctl_idx);
2033 if (!substream || !substream->runtime)
2034 return 0; /* just for avoiding error from alsactl restore */
2035 switch (substream->runtime->status->state) {
2036 case SNDRV_PCM_STATE_OPEN:
2037 case SNDRV_PCM_STATE_SETUP:
2038 break;
2039 case SNDRV_PCM_STATE_PREPARED:
2040 prepared = 1;
2041 break;
2042 default:
2043 return -EBUSY;
2044 }
2045 memset(chmap, 0, sizeof(chmap));
2046 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2047 chmap[i] = ucontrol->value.integer.value[i];
2048 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2049 return 0;
2050 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2051 if (ca < 0)
2052 return -EINVAL;
2053 if (spec->ops.chmap_validate) {
2054 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2055 if (err)
2056 return err;
2057 }
2058 mutex_lock(&per_pin->lock);
2059 per_pin->chmap_set = true;
2060 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2061 if (prepared)
2062 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2063 mutex_unlock(&per_pin->lock);
2064
2065 return 0;
2066 }
2067
2068 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2069 {
2070 struct hdmi_spec *spec = codec->spec;
2071 int pin_idx;
2072
2073 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2074 struct hda_pcm *info;
2075 struct hda_pcm_stream *pstr;
2076
2077 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2078 if (!info)
2079 return -ENOMEM;
2080 spec->pcm_rec[pin_idx] = info;
2081 info->pcm_type = HDA_PCM_TYPE_HDMI;
2082 info->own_chmap = true;
2083
2084 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2085 pstr->substreams = 1;
2086 pstr->ops = generic_ops;
2087 /* other pstr fields are set in open */
2088 }
2089
2090 return 0;
2091 }
2092
2093 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2094 {
2095 char hdmi_str[32] = "HDMI/DP";
2096 struct hdmi_spec *spec = codec->spec;
2097 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2098 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2099
2100 if (pcmdev > 0)
2101 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2102 if (!is_jack_detectable(codec, per_pin->pin_nid))
2103 strncat(hdmi_str, " Phantom",
2104 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2105
2106 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str);
2107 }
2108
2109 static int generic_hdmi_build_controls(struct hda_codec *codec)
2110 {
2111 struct hdmi_spec *spec = codec->spec;
2112 int err;
2113 int pin_idx;
2114
2115 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2116 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2117
2118 err = generic_hdmi_build_jack(codec, pin_idx);
2119 if (err < 0)
2120 return err;
2121
2122 err = snd_hda_create_dig_out_ctls(codec,
2123 per_pin->pin_nid,
2124 per_pin->mux_nids[0],
2125 HDA_PCM_TYPE_HDMI);
2126 if (err < 0)
2127 return err;
2128 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2129
2130 /* add control for ELD Bytes */
2131 err = hdmi_create_eld_ctl(codec, pin_idx,
2132 get_pcm_rec(spec, pin_idx)->device);
2133
2134 if (err < 0)
2135 return err;
2136
2137 hdmi_present_sense(per_pin, 0);
2138 }
2139
2140 /* add channel maps */
2141 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2142 struct hda_pcm *pcm;
2143 struct snd_pcm_chmap *chmap;
2144 struct snd_kcontrol *kctl;
2145 int i;
2146
2147 pcm = spec->pcm_rec[pin_idx];
2148 if (!pcm || !pcm->pcm)
2149 break;
2150 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2151 SNDRV_PCM_STREAM_PLAYBACK,
2152 NULL, 0, pin_idx, &chmap);
2153 if (err < 0)
2154 return err;
2155 /* override handlers */
2156 chmap->private_data = codec;
2157 kctl = chmap->kctl;
2158 for (i = 0; i < kctl->count; i++)
2159 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2160 kctl->info = hdmi_chmap_ctl_info;
2161 kctl->get = hdmi_chmap_ctl_get;
2162 kctl->put = hdmi_chmap_ctl_put;
2163 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2164 }
2165
2166 return 0;
2167 }
2168
2169 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2170 {
2171 struct hdmi_spec *spec = codec->spec;
2172 int pin_idx;
2173
2174 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2175 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2176
2177 per_pin->codec = codec;
2178 mutex_init(&per_pin->lock);
2179 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2180 eld_proc_new(per_pin, pin_idx);
2181 }
2182 return 0;
2183 }
2184
2185 static int generic_hdmi_init(struct hda_codec *codec)
2186 {
2187 struct hdmi_spec *spec = codec->spec;
2188 int pin_idx;
2189
2190 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2191 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2192 hda_nid_t pin_nid = per_pin->pin_nid;
2193
2194 hdmi_init_pin(codec, pin_nid);
2195 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2196 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2197 }
2198 return 0;
2199 }
2200
2201 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2202 {
2203 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2204 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2205 }
2206
2207 static void hdmi_array_free(struct hdmi_spec *spec)
2208 {
2209 snd_array_free(&spec->pins);
2210 snd_array_free(&spec->cvts);
2211 }
2212
2213 static void generic_hdmi_free(struct hda_codec *codec)
2214 {
2215 struct hdmi_spec *spec = codec->spec;
2216 int pin_idx;
2217
2218 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2219 snd_hdac_i915_register_notifier(NULL);
2220
2221 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2222 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2223
2224 cancel_delayed_work_sync(&per_pin->work);
2225 eld_proc_free(per_pin);
2226 }
2227
2228 hdmi_array_free(spec);
2229 kfree(spec);
2230 }
2231
2232 #ifdef CONFIG_PM
2233 static int generic_hdmi_resume(struct hda_codec *codec)
2234 {
2235 struct hdmi_spec *spec = codec->spec;
2236 int pin_idx;
2237
2238 codec->patch_ops.init(codec);
2239 regcache_sync(codec->core.regmap);
2240
2241 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2242 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2243 hdmi_present_sense(per_pin, 1);
2244 }
2245 return 0;
2246 }
2247 #endif
2248
2249 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2250 .init = generic_hdmi_init,
2251 .free = generic_hdmi_free,
2252 .build_pcms = generic_hdmi_build_pcms,
2253 .build_controls = generic_hdmi_build_controls,
2254 .unsol_event = hdmi_unsol_event,
2255 #ifdef CONFIG_PM
2256 .resume = generic_hdmi_resume,
2257 #endif
2258 };
2259
2260 static const struct hdmi_ops generic_standard_hdmi_ops = {
2261 .pin_get_eld = snd_hdmi_get_eld,
2262 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2263 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2264 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2265 .pin_hbr_setup = hdmi_pin_hbr_setup,
2266 .setup_stream = hdmi_setup_stream,
2267 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2268 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2269 };
2270
2271
2272 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2273 hda_nid_t nid)
2274 {
2275 struct hdmi_spec *spec = codec->spec;
2276 hda_nid_t conns[4];
2277 int nconns;
2278
2279 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2280 if (nconns == spec->num_cvts &&
2281 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2282 return;
2283
2284 /* override pins connection list */
2285 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2286 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2287 }
2288
2289 #define INTEL_VENDOR_NID 0x08
2290 #define INTEL_GET_VENDOR_VERB 0xf81
2291 #define INTEL_SET_VENDOR_VERB 0x781
2292 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2293 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2294
2295 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2296 bool update_tree)
2297 {
2298 unsigned int vendor_param;
2299
2300 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2301 INTEL_GET_VENDOR_VERB, 0);
2302 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2303 return;
2304
2305 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2306 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2307 INTEL_SET_VENDOR_VERB, vendor_param);
2308 if (vendor_param == -1)
2309 return;
2310
2311 if (update_tree)
2312 snd_hda_codec_update_widgets(codec);
2313 }
2314
2315 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2316 {
2317 unsigned int vendor_param;
2318
2319 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2320 INTEL_GET_VENDOR_VERB, 0);
2321 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2322 return;
2323
2324 /* enable DP1.2 mode */
2325 vendor_param |= INTEL_EN_DP12;
2326 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2327 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2328 INTEL_SET_VENDOR_VERB, vendor_param);
2329 }
2330
2331 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2332 * Otherwise you may get severe h/w communication errors.
2333 */
2334 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2335 unsigned int power_state)
2336 {
2337 if (power_state == AC_PWRST_D0) {
2338 intel_haswell_enable_all_pins(codec, false);
2339 intel_haswell_fixup_enable_dp12(codec);
2340 }
2341
2342 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2343 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2344 }
2345
2346 static void intel_pin_eld_notify(void *audio_ptr, int port)
2347 {
2348 struct hda_codec *codec = audio_ptr;
2349 int pin_nid = port + 0x04;
2350
2351 check_presence_and_report(codec, pin_nid);
2352 }
2353
2354 static int patch_generic_hdmi(struct hda_codec *codec)
2355 {
2356 struct hdmi_spec *spec;
2357
2358 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2359 if (spec == NULL)
2360 return -ENOMEM;
2361
2362 spec->ops = generic_standard_hdmi_ops;
2363 codec->spec = spec;
2364 hdmi_array_init(spec, 4);
2365
2366 if (is_haswell_plus(codec)) {
2367 intel_haswell_enable_all_pins(codec, true);
2368 intel_haswell_fixup_enable_dp12(codec);
2369 }
2370
2371 /* For Valleyview/Cherryview, only the display codec is in the display
2372 * power well and can use link_power ops to request/release the power.
2373 * For Haswell/Broadwell, the controller is also in the power well and
2374 * can cover the codec power request, and so need not set this flag.
2375 * For previous platforms, there is no such power well feature.
2376 */
2377 if (is_valleyview_plus(codec) || is_skylake(codec))
2378 codec->core.link_power_control = 1;
2379
2380 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2381 codec->depop_delay = 0;
2382 spec->i915_audio_ops.audio_ptr = codec;
2383 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2384 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2385 }
2386
2387 if (hdmi_parse_codec(codec) < 0) {
2388 codec->spec = NULL;
2389 kfree(spec);
2390 return -EINVAL;
2391 }
2392 codec->patch_ops = generic_hdmi_patch_ops;
2393 if (is_haswell_plus(codec)) {
2394 codec->patch_ops.set_power_state = haswell_set_power_state;
2395 codec->dp_mst = true;
2396 }
2397
2398 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2399 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2400 codec->auto_runtime_pm = 1;
2401
2402 generic_hdmi_init_per_pins(codec);
2403
2404 init_channel_allocations();
2405
2406 return 0;
2407 }
2408
2409 /*
2410 * Shared non-generic implementations
2411 */
2412
2413 static int simple_playback_build_pcms(struct hda_codec *codec)
2414 {
2415 struct hdmi_spec *spec = codec->spec;
2416 struct hda_pcm *info;
2417 unsigned int chans;
2418 struct hda_pcm_stream *pstr;
2419 struct hdmi_spec_per_cvt *per_cvt;
2420
2421 per_cvt = get_cvt(spec, 0);
2422 chans = get_wcaps(codec, per_cvt->cvt_nid);
2423 chans = get_wcaps_channels(chans);
2424
2425 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2426 if (!info)
2427 return -ENOMEM;
2428 spec->pcm_rec[0] = info;
2429 info->pcm_type = HDA_PCM_TYPE_HDMI;
2430 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2431 *pstr = spec->pcm_playback;
2432 pstr->nid = per_cvt->cvt_nid;
2433 if (pstr->channels_max <= 2 && chans && chans <= 16)
2434 pstr->channels_max = chans;
2435
2436 return 0;
2437 }
2438
2439 /* unsolicited event for jack sensing */
2440 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2441 unsigned int res)
2442 {
2443 snd_hda_jack_set_dirty_all(codec);
2444 snd_hda_jack_report_sync(codec);
2445 }
2446
2447 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2448 * as long as spec->pins[] is set correctly
2449 */
2450 #define simple_hdmi_build_jack generic_hdmi_build_jack
2451
2452 static int simple_playback_build_controls(struct hda_codec *codec)
2453 {
2454 struct hdmi_spec *spec = codec->spec;
2455 struct hdmi_spec_per_cvt *per_cvt;
2456 int err;
2457
2458 per_cvt = get_cvt(spec, 0);
2459 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2460 per_cvt->cvt_nid,
2461 HDA_PCM_TYPE_HDMI);
2462 if (err < 0)
2463 return err;
2464 return simple_hdmi_build_jack(codec, 0);
2465 }
2466
2467 static int simple_playback_init(struct hda_codec *codec)
2468 {
2469 struct hdmi_spec *spec = codec->spec;
2470 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2471 hda_nid_t pin = per_pin->pin_nid;
2472
2473 snd_hda_codec_write(codec, pin, 0,
2474 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2475 /* some codecs require to unmute the pin */
2476 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2477 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2478 AMP_OUT_UNMUTE);
2479 snd_hda_jack_detect_enable(codec, pin);
2480 return 0;
2481 }
2482
2483 static void simple_playback_free(struct hda_codec *codec)
2484 {
2485 struct hdmi_spec *spec = codec->spec;
2486
2487 hdmi_array_free(spec);
2488 kfree(spec);
2489 }
2490
2491 /*
2492 * Nvidia specific implementations
2493 */
2494
2495 #define Nv_VERB_SET_Channel_Allocation 0xF79
2496 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2497 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2498 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2499
2500 #define nvhdmi_master_con_nid_7x 0x04
2501 #define nvhdmi_master_pin_nid_7x 0x05
2502
2503 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2504 /*front, rear, clfe, rear_surr */
2505 0x6, 0x8, 0xa, 0xc,
2506 };
2507
2508 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2509 /* set audio protect on */
2510 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2511 /* enable digital output on pin widget */
2512 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2513 {} /* terminator */
2514 };
2515
2516 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2517 /* set audio protect on */
2518 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2519 /* enable digital output on pin widget */
2520 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2521 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2522 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2523 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2524 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2525 {} /* terminator */
2526 };
2527
2528 #ifdef LIMITED_RATE_FMT_SUPPORT
2529 /* support only the safe format and rate */
2530 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2531 #define SUPPORTED_MAXBPS 16
2532 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2533 #else
2534 /* support all rates and formats */
2535 #define SUPPORTED_RATES \
2536 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2537 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2538 SNDRV_PCM_RATE_192000)
2539 #define SUPPORTED_MAXBPS 24
2540 #define SUPPORTED_FORMATS \
2541 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2542 #endif
2543
2544 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2545 {
2546 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2547 return 0;
2548 }
2549
2550 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2551 {
2552 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2553 return 0;
2554 }
2555
2556 static unsigned int channels_2_6_8[] = {
2557 2, 6, 8
2558 };
2559
2560 static unsigned int channels_2_8[] = {
2561 2, 8
2562 };
2563
2564 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2565 .count = ARRAY_SIZE(channels_2_6_8),
2566 .list = channels_2_6_8,
2567 .mask = 0,
2568 };
2569
2570 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2571 .count = ARRAY_SIZE(channels_2_8),
2572 .list = channels_2_8,
2573 .mask = 0,
2574 };
2575
2576 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2577 struct hda_codec *codec,
2578 struct snd_pcm_substream *substream)
2579 {
2580 struct hdmi_spec *spec = codec->spec;
2581 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2582
2583 switch (codec->preset->vendor_id) {
2584 case 0x10de0002:
2585 case 0x10de0003:
2586 case 0x10de0005:
2587 case 0x10de0006:
2588 hw_constraints_channels = &hw_constraints_2_8_channels;
2589 break;
2590 case 0x10de0007:
2591 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2592 break;
2593 default:
2594 break;
2595 }
2596
2597 if (hw_constraints_channels != NULL) {
2598 snd_pcm_hw_constraint_list(substream->runtime, 0,
2599 SNDRV_PCM_HW_PARAM_CHANNELS,
2600 hw_constraints_channels);
2601 } else {
2602 snd_pcm_hw_constraint_step(substream->runtime, 0,
2603 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2604 }
2605
2606 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2607 }
2608
2609 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2610 struct hda_codec *codec,
2611 struct snd_pcm_substream *substream)
2612 {
2613 struct hdmi_spec *spec = codec->spec;
2614 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2615 }
2616
2617 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2618 struct hda_codec *codec,
2619 unsigned int stream_tag,
2620 unsigned int format,
2621 struct snd_pcm_substream *substream)
2622 {
2623 struct hdmi_spec *spec = codec->spec;
2624 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2625 stream_tag, format, substream);
2626 }
2627
2628 static const struct hda_pcm_stream simple_pcm_playback = {
2629 .substreams = 1,
2630 .channels_min = 2,
2631 .channels_max = 2,
2632 .ops = {
2633 .open = simple_playback_pcm_open,
2634 .close = simple_playback_pcm_close,
2635 .prepare = simple_playback_pcm_prepare
2636 },
2637 };
2638
2639 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2640 .build_controls = simple_playback_build_controls,
2641 .build_pcms = simple_playback_build_pcms,
2642 .init = simple_playback_init,
2643 .free = simple_playback_free,
2644 .unsol_event = simple_hdmi_unsol_event,
2645 };
2646
2647 static int patch_simple_hdmi(struct hda_codec *codec,
2648 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2649 {
2650 struct hdmi_spec *spec;
2651 struct hdmi_spec_per_cvt *per_cvt;
2652 struct hdmi_spec_per_pin *per_pin;
2653
2654 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2655 if (!spec)
2656 return -ENOMEM;
2657
2658 codec->spec = spec;
2659 hdmi_array_init(spec, 1);
2660
2661 spec->multiout.num_dacs = 0; /* no analog */
2662 spec->multiout.max_channels = 2;
2663 spec->multiout.dig_out_nid = cvt_nid;
2664 spec->num_cvts = 1;
2665 spec->num_pins = 1;
2666 per_pin = snd_array_new(&spec->pins);
2667 per_cvt = snd_array_new(&spec->cvts);
2668 if (!per_pin || !per_cvt) {
2669 simple_playback_free(codec);
2670 return -ENOMEM;
2671 }
2672 per_cvt->cvt_nid = cvt_nid;
2673 per_pin->pin_nid = pin_nid;
2674 spec->pcm_playback = simple_pcm_playback;
2675
2676 codec->patch_ops = simple_hdmi_patch_ops;
2677
2678 return 0;
2679 }
2680
2681 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2682 int channels)
2683 {
2684 unsigned int chanmask;
2685 int chan = channels ? (channels - 1) : 1;
2686
2687 switch (channels) {
2688 default:
2689 case 0:
2690 case 2:
2691 chanmask = 0x00;
2692 break;
2693 case 4:
2694 chanmask = 0x08;
2695 break;
2696 case 6:
2697 chanmask = 0x0b;
2698 break;
2699 case 8:
2700 chanmask = 0x13;
2701 break;
2702 }
2703
2704 /* Set the audio infoframe channel allocation and checksum fields. The
2705 * channel count is computed implicitly by the hardware. */
2706 snd_hda_codec_write(codec, 0x1, 0,
2707 Nv_VERB_SET_Channel_Allocation, chanmask);
2708
2709 snd_hda_codec_write(codec, 0x1, 0,
2710 Nv_VERB_SET_Info_Frame_Checksum,
2711 (0x71 - chan - chanmask));
2712 }
2713
2714 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2715 struct hda_codec *codec,
2716 struct snd_pcm_substream *substream)
2717 {
2718 struct hdmi_spec *spec = codec->spec;
2719 int i;
2720
2721 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2722 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2723 for (i = 0; i < 4; i++) {
2724 /* set the stream id */
2725 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2726 AC_VERB_SET_CHANNEL_STREAMID, 0);
2727 /* set the stream format */
2728 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2729 AC_VERB_SET_STREAM_FORMAT, 0);
2730 }
2731
2732 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2733 * streams are disabled. */
2734 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2735
2736 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2737 }
2738
2739 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2740 struct hda_codec *codec,
2741 unsigned int stream_tag,
2742 unsigned int format,
2743 struct snd_pcm_substream *substream)
2744 {
2745 int chs;
2746 unsigned int dataDCC2, channel_id;
2747 int i;
2748 struct hdmi_spec *spec = codec->spec;
2749 struct hda_spdif_out *spdif;
2750 struct hdmi_spec_per_cvt *per_cvt;
2751
2752 mutex_lock(&codec->spdif_mutex);
2753 per_cvt = get_cvt(spec, 0);
2754 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2755
2756 chs = substream->runtime->channels;
2757
2758 dataDCC2 = 0x2;
2759
2760 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2761 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2762 snd_hda_codec_write(codec,
2763 nvhdmi_master_con_nid_7x,
2764 0,
2765 AC_VERB_SET_DIGI_CONVERT_1,
2766 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2767
2768 /* set the stream id */
2769 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2770 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2771
2772 /* set the stream format */
2773 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2774 AC_VERB_SET_STREAM_FORMAT, format);
2775
2776 /* turn on again (if needed) */
2777 /* enable and set the channel status audio/data flag */
2778 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2779 snd_hda_codec_write(codec,
2780 nvhdmi_master_con_nid_7x,
2781 0,
2782 AC_VERB_SET_DIGI_CONVERT_1,
2783 spdif->ctls & 0xff);
2784 snd_hda_codec_write(codec,
2785 nvhdmi_master_con_nid_7x,
2786 0,
2787 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2788 }
2789
2790 for (i = 0; i < 4; i++) {
2791 if (chs == 2)
2792 channel_id = 0;
2793 else
2794 channel_id = i * 2;
2795
2796 /* turn off SPDIF once;
2797 *otherwise the IEC958 bits won't be updated
2798 */
2799 if (codec->spdif_status_reset &&
2800 (spdif->ctls & AC_DIG1_ENABLE))
2801 snd_hda_codec_write(codec,
2802 nvhdmi_con_nids_7x[i],
2803 0,
2804 AC_VERB_SET_DIGI_CONVERT_1,
2805 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2806 /* set the stream id */
2807 snd_hda_codec_write(codec,
2808 nvhdmi_con_nids_7x[i],
2809 0,
2810 AC_VERB_SET_CHANNEL_STREAMID,
2811 (stream_tag << 4) | channel_id);
2812 /* set the stream format */
2813 snd_hda_codec_write(codec,
2814 nvhdmi_con_nids_7x[i],
2815 0,
2816 AC_VERB_SET_STREAM_FORMAT,
2817 format);
2818 /* turn on again (if needed) */
2819 /* enable and set the channel status audio/data flag */
2820 if (codec->spdif_status_reset &&
2821 (spdif->ctls & AC_DIG1_ENABLE)) {
2822 snd_hda_codec_write(codec,
2823 nvhdmi_con_nids_7x[i],
2824 0,
2825 AC_VERB_SET_DIGI_CONVERT_1,
2826 spdif->ctls & 0xff);
2827 snd_hda_codec_write(codec,
2828 nvhdmi_con_nids_7x[i],
2829 0,
2830 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2831 }
2832 }
2833
2834 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2835
2836 mutex_unlock(&codec->spdif_mutex);
2837 return 0;
2838 }
2839
2840 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2841 .substreams = 1,
2842 .channels_min = 2,
2843 .channels_max = 8,
2844 .nid = nvhdmi_master_con_nid_7x,
2845 .rates = SUPPORTED_RATES,
2846 .maxbps = SUPPORTED_MAXBPS,
2847 .formats = SUPPORTED_FORMATS,
2848 .ops = {
2849 .open = simple_playback_pcm_open,
2850 .close = nvhdmi_8ch_7x_pcm_close,
2851 .prepare = nvhdmi_8ch_7x_pcm_prepare
2852 },
2853 };
2854
2855 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2856 {
2857 struct hdmi_spec *spec;
2858 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2859 nvhdmi_master_pin_nid_7x);
2860 if (err < 0)
2861 return err;
2862
2863 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2864 /* override the PCM rates, etc, as the codec doesn't give full list */
2865 spec = codec->spec;
2866 spec->pcm_playback.rates = SUPPORTED_RATES;
2867 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2868 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2869 return 0;
2870 }
2871
2872 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2873 {
2874 struct hdmi_spec *spec = codec->spec;
2875 int err = simple_playback_build_pcms(codec);
2876 if (!err) {
2877 struct hda_pcm *info = get_pcm_rec(spec, 0);
2878 info->own_chmap = true;
2879 }
2880 return err;
2881 }
2882
2883 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2884 {
2885 struct hdmi_spec *spec = codec->spec;
2886 struct hda_pcm *info;
2887 struct snd_pcm_chmap *chmap;
2888 int err;
2889
2890 err = simple_playback_build_controls(codec);
2891 if (err < 0)
2892 return err;
2893
2894 /* add channel maps */
2895 info = get_pcm_rec(spec, 0);
2896 err = snd_pcm_add_chmap_ctls(info->pcm,
2897 SNDRV_PCM_STREAM_PLAYBACK,
2898 snd_pcm_alt_chmaps, 8, 0, &chmap);
2899 if (err < 0)
2900 return err;
2901 switch (codec->preset->vendor_id) {
2902 case 0x10de0002:
2903 case 0x10de0003:
2904 case 0x10de0005:
2905 case 0x10de0006:
2906 chmap->channel_mask = (1U << 2) | (1U << 8);
2907 break;
2908 case 0x10de0007:
2909 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2910 }
2911 return 0;
2912 }
2913
2914 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2915 {
2916 struct hdmi_spec *spec;
2917 int err = patch_nvhdmi_2ch(codec);
2918 if (err < 0)
2919 return err;
2920 spec = codec->spec;
2921 spec->multiout.max_channels = 8;
2922 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2923 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2924 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2925 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2926
2927 /* Initialize the audio infoframe channel mask and checksum to something
2928 * valid */
2929 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2930
2931 return 0;
2932 }
2933
2934 /*
2935 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2936 * - 0x10de0015
2937 * - 0x10de0040
2938 */
2939 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2940 int channels)
2941 {
2942 if (cap->ca_index == 0x00 && channels == 2)
2943 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2944
2945 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2946 }
2947
2948 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2949 {
2950 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2951 return -EINVAL;
2952
2953 return 0;
2954 }
2955
2956 static int patch_nvhdmi(struct hda_codec *codec)
2957 {
2958 struct hdmi_spec *spec;
2959 int err;
2960
2961 err = patch_generic_hdmi(codec);
2962 if (err)
2963 return err;
2964
2965 spec = codec->spec;
2966 spec->dyn_pin_out = true;
2967
2968 spec->ops.chmap_cea_alloc_validate_get_type =
2969 nvhdmi_chmap_cea_alloc_validate_get_type;
2970 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2971
2972 return 0;
2973 }
2974
2975 /*
2976 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2977 * accessed using vendor-defined verbs. These registers can be used for
2978 * interoperability between the HDA and HDMI drivers.
2979 */
2980
2981 /* Audio Function Group node */
2982 #define NVIDIA_AFG_NID 0x01
2983
2984 /*
2985 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2986 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2987 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2988 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2989 * additional bit (at position 30) to signal the validity of the format.
2990 *
2991 * | 31 | 30 | 29 16 | 15 0 |
2992 * +---------+-------+--------+--------+
2993 * | TRIGGER | VALID | UNUSED | FORMAT |
2994 * +-----------------------------------|
2995 *
2996 * Note that for the trigger bit to take effect it needs to change value
2997 * (i.e. it needs to be toggled).
2998 */
2999 #define NVIDIA_GET_SCRATCH0 0xfa6
3000 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3001 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3002 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3003 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3004 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3005 #define NVIDIA_SCRATCH_VALID (1 << 6)
3006
3007 #define NVIDIA_GET_SCRATCH1 0xfab
3008 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3009 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3010 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3011 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3012
3013 /*
3014 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3015 * the format is invalidated so that the HDMI codec can be disabled.
3016 */
3017 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3018 {
3019 unsigned int value;
3020
3021 /* bits [31:30] contain the trigger and valid bits */
3022 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3023 NVIDIA_GET_SCRATCH0, 0);
3024 value = (value >> 24) & 0xff;
3025
3026 /* bits [15:0] are used to store the HDA format */
3027 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3028 NVIDIA_SET_SCRATCH0_BYTE0,
3029 (format >> 0) & 0xff);
3030 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3031 NVIDIA_SET_SCRATCH0_BYTE1,
3032 (format >> 8) & 0xff);
3033
3034 /* bits [16:24] are unused */
3035 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3036 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3037
3038 /*
3039 * Bit 30 signals that the data is valid and hence that HDMI audio can
3040 * be enabled.
3041 */
3042 if (format == 0)
3043 value &= ~NVIDIA_SCRATCH_VALID;
3044 else
3045 value |= NVIDIA_SCRATCH_VALID;
3046
3047 /*
3048 * Whenever the trigger bit is toggled, an interrupt is raised in the
3049 * HDMI codec. The HDMI driver will use that as trigger to update its
3050 * configuration.
3051 */
3052 value ^= NVIDIA_SCRATCH_TRIGGER;
3053
3054 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3055 NVIDIA_SET_SCRATCH0_BYTE3, value);
3056 }
3057
3058 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3059 struct hda_codec *codec,
3060 unsigned int stream_tag,
3061 unsigned int format,
3062 struct snd_pcm_substream *substream)
3063 {
3064 int err;
3065
3066 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3067 format, substream);
3068 if (err < 0)
3069 return err;
3070
3071 /* notify the HDMI codec of the format change */
3072 tegra_hdmi_set_format(codec, format);
3073
3074 return 0;
3075 }
3076
3077 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3078 struct hda_codec *codec,
3079 struct snd_pcm_substream *substream)
3080 {
3081 /* invalidate the format in the HDMI codec */
3082 tegra_hdmi_set_format(codec, 0);
3083
3084 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3085 }
3086
3087 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3088 {
3089 struct hdmi_spec *spec = codec->spec;
3090 unsigned int i;
3091
3092 for (i = 0; i < spec->num_pins; i++) {
3093 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3094
3095 if (pcm->pcm_type == type)
3096 return pcm;
3097 }
3098
3099 return NULL;
3100 }
3101
3102 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3103 {
3104 struct hda_pcm_stream *stream;
3105 struct hda_pcm *pcm;
3106 int err;
3107
3108 err = generic_hdmi_build_pcms(codec);
3109 if (err < 0)
3110 return err;
3111
3112 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3113 if (!pcm)
3114 return -ENODEV;
3115
3116 /*
3117 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3118 * codec about format changes.
3119 */
3120 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3121 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3122 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3123
3124 return 0;
3125 }
3126
3127 static int patch_tegra_hdmi(struct hda_codec *codec)
3128 {
3129 int err;
3130
3131 err = patch_generic_hdmi(codec);
3132 if (err)
3133 return err;
3134
3135 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3136
3137 return 0;
3138 }
3139
3140 /*
3141 * ATI/AMD-specific implementations
3142 */
3143
3144 #define is_amdhdmi_rev3_or_later(codec) \
3145 ((codec)->core.vendor_id == 0x1002aa01 && \
3146 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3147 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3148
3149 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3150 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3151 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3152 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3153 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3154 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3155 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3156 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3157 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3158 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3159 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3160 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3161 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3162 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3163 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3164 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3165 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3166 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3167 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3168 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3169 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3170 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3171 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3172 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3173 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3174
3175 /* AMD specific HDA cvt verbs */
3176 #define ATI_VERB_SET_RAMP_RATE 0x770
3177 #define ATI_VERB_GET_RAMP_RATE 0xf70
3178
3179 #define ATI_OUT_ENABLE 0x1
3180
3181 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3182 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3183
3184 #define ATI_HBR_CAPABLE 0x01
3185 #define ATI_HBR_ENABLE 0x10
3186
3187 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3188 unsigned char *buf, int *eld_size)
3189 {
3190 /* call hda_eld.c ATI/AMD-specific function */
3191 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3192 is_amdhdmi_rev3_or_later(codec));
3193 }
3194
3195 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3196 int active_channels, int conn_type)
3197 {
3198 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3199 }
3200
3201 static int atihdmi_paired_swap_fc_lfe(int pos)
3202 {
3203 /*
3204 * ATI/AMD have automatic FC/LFE swap built-in
3205 * when in pairwise mapping mode.
3206 */
3207
3208 switch (pos) {
3209 /* see channel_allocations[].speakers[] */
3210 case 2: return 3;
3211 case 3: return 2;
3212 default: break;
3213 }
3214
3215 return pos;
3216 }
3217
3218 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3219 {
3220 struct cea_channel_speaker_allocation *cap;
3221 int i, j;
3222
3223 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3224
3225 cap = &channel_allocations[get_channel_allocation_order(ca)];
3226 for (i = 0; i < chs; ++i) {
3227 int mask = to_spk_mask(map[i]);
3228 bool ok = false;
3229 bool companion_ok = false;
3230
3231 if (!mask)
3232 continue;
3233
3234 for (j = 0 + i % 2; j < 8; j += 2) {
3235 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3236 if (cap->speakers[chan_idx] == mask) {
3237 /* channel is in a supported position */
3238 ok = true;
3239
3240 if (i % 2 == 0 && i + 1 < chs) {
3241 /* even channel, check the odd companion */
3242 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3243 int comp_mask_req = to_spk_mask(map[i+1]);
3244 int comp_mask_act = cap->speakers[comp_chan_idx];
3245
3246 if (comp_mask_req == comp_mask_act)
3247 companion_ok = true;
3248 else
3249 return -EINVAL;
3250 }
3251 break;
3252 }
3253 }
3254
3255 if (!ok)
3256 return -EINVAL;
3257
3258 if (companion_ok)
3259 i++; /* companion channel already checked */
3260 }
3261
3262 return 0;
3263 }
3264
3265 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3266 int hdmi_slot, int stream_channel)
3267 {
3268 int verb;
3269 int ati_channel_setup = 0;
3270
3271 if (hdmi_slot > 7)
3272 return -EINVAL;
3273
3274 if (!has_amd_full_remap_support(codec)) {
3275 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3276
3277 /* In case this is an odd slot but without stream channel, do not
3278 * disable the slot since the corresponding even slot could have a
3279 * channel. In case neither have a channel, the slot pair will be
3280 * disabled when this function is called for the even slot. */
3281 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3282 return 0;
3283
3284 hdmi_slot -= hdmi_slot % 2;
3285
3286 if (stream_channel != 0xf)
3287 stream_channel -= stream_channel % 2;
3288 }
3289
3290 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3291
3292 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3293
3294 if (stream_channel != 0xf)
3295 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3296
3297 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3298 }
3299
3300 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3301 int asp_slot)
3302 {
3303 bool was_odd = false;
3304 int ati_asp_slot = asp_slot;
3305 int verb;
3306 int ati_channel_setup;
3307
3308 if (asp_slot > 7)
3309 return -EINVAL;
3310
3311 if (!has_amd_full_remap_support(codec)) {
3312 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3313 if (ati_asp_slot % 2 != 0) {
3314 ati_asp_slot -= 1;
3315 was_odd = true;
3316 }
3317 }
3318
3319 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3320
3321 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3322
3323 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3324 return 0xf;
3325
3326 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3327 }
3328
3329 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3330 int channels)
3331 {
3332 int c;
3333
3334 /*
3335 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3336 * we need to take that into account (a single channel may take 2
3337 * channel slots if we need to carry a silent channel next to it).
3338 * On Rev3+ AMD codecs this function is not used.
3339 */
3340 int chanpairs = 0;
3341
3342 /* We only produce even-numbered channel count TLVs */
3343 if ((channels % 2) != 0)
3344 return -1;
3345
3346 for (c = 0; c < 7; c += 2) {
3347 if (cap->speakers[c] || cap->speakers[c+1])
3348 chanpairs++;
3349 }
3350
3351 if (chanpairs * 2 != channels)
3352 return -1;
3353
3354 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3355 }
3356
3357 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3358 unsigned int *chmap, int channels)
3359 {
3360 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3361 int count = 0;
3362 int c;
3363
3364 for (c = 7; c >= 0; c--) {
3365 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3366 int spk = cap->speakers[chan];
3367 if (!spk) {
3368 /* add N/A channel if the companion channel is occupied */
3369 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3370 chmap[count++] = SNDRV_CHMAP_NA;
3371
3372 continue;
3373 }
3374
3375 chmap[count++] = spk_to_chmap(spk);
3376 }
3377
3378 WARN_ON(count != channels);
3379 }
3380
3381 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3382 bool hbr)
3383 {
3384 int hbr_ctl, hbr_ctl_new;
3385
3386 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3387 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3388 if (hbr)
3389 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3390 else
3391 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3392
3393 codec_dbg(codec,
3394 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3395 pin_nid,
3396 hbr_ctl == hbr_ctl_new ? "" : "new-",
3397 hbr_ctl_new);
3398
3399 if (hbr_ctl != hbr_ctl_new)
3400 snd_hda_codec_write(codec, pin_nid, 0,
3401 ATI_VERB_SET_HBR_CONTROL,
3402 hbr_ctl_new);
3403
3404 } else if (hbr)
3405 return -EINVAL;
3406
3407 return 0;
3408 }
3409
3410 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3411 hda_nid_t pin_nid, u32 stream_tag, int format)
3412 {
3413
3414 if (is_amdhdmi_rev3_or_later(codec)) {
3415 int ramp_rate = 180; /* default as per AMD spec */
3416 /* disable ramp-up/down for non-pcm as per AMD spec */
3417 if (format & AC_FMT_TYPE_NON_PCM)
3418 ramp_rate = 0;
3419
3420 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3421 }
3422
3423 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3424 }
3425
3426
3427 static int atihdmi_init(struct hda_codec *codec)
3428 {
3429 struct hdmi_spec *spec = codec->spec;
3430 int pin_idx, err;
3431
3432 err = generic_hdmi_init(codec);
3433
3434 if (err)
3435 return err;
3436
3437 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3438 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3439
3440 /* make sure downmix information in infoframe is zero */
3441 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3442
3443 /* enable channel-wise remap mode if supported */
3444 if (has_amd_full_remap_support(codec))
3445 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3446 ATI_VERB_SET_MULTICHANNEL_MODE,
3447 ATI_MULTICHANNEL_MODE_SINGLE);
3448 }
3449
3450 return 0;
3451 }
3452
3453 static int patch_atihdmi(struct hda_codec *codec)
3454 {
3455 struct hdmi_spec *spec;
3456 struct hdmi_spec_per_cvt *per_cvt;
3457 int err, cvt_idx;
3458
3459 err = patch_generic_hdmi(codec);
3460
3461 if (err)
3462 return err;
3463
3464 codec->patch_ops.init = atihdmi_init;
3465
3466 spec = codec->spec;
3467
3468 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3469 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3470 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3471 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3472 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3473 spec->ops.setup_stream = atihdmi_setup_stream;
3474
3475 if (!has_amd_full_remap_support(codec)) {
3476 /* override to ATI/AMD-specific versions with pairwise mapping */
3477 spec->ops.chmap_cea_alloc_validate_get_type =
3478 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3479 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3480 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3481 }
3482
3483 /* ATI/AMD converters do not advertise all of their capabilities */
3484 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3485 per_cvt = get_cvt(spec, cvt_idx);
3486 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3487 per_cvt->rates |= SUPPORTED_RATES;
3488 per_cvt->formats |= SUPPORTED_FORMATS;
3489 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3490 }
3491
3492 spec->channels_max = max(spec->channels_max, 8u);
3493
3494 return 0;
3495 }
3496
3497 /* VIA HDMI Implementation */
3498 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3499 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3500
3501 static int patch_via_hdmi(struct hda_codec *codec)
3502 {
3503 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3504 }
3505
3506 /*
3507 * patch entries
3508 */
3509 static const struct hda_device_id snd_hda_id_hdmi[] = {
3510 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3511 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3512 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3513 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3514 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3515 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3516 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3517 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3518 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3519 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3520 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3521 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3522 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3523 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3524 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3525 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3526 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3527 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3528 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3529 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3530 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3531 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3532 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3533 /* 17 is known to be absent */
3534 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3535 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3536 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3537 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3538 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3539 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3540 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3541 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3542 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3543 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3544 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3545 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3546 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3547 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3548 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3549 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3550 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3551 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3552 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3553 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3554 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3555 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3556 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3557 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3558 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3559 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3560 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3561 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3562 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3563 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3564 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3565 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3566 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3567 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3568 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3569 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3570 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3571 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3572 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3573 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3574 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3575 /* special ID for generic HDMI */
3576 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3577 {} /* terminator */
3578 };
3579 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3580
3581 MODULE_LICENSE("GPL");
3582 MODULE_DESCRIPTION("HDMI HD-audio codec");
3583 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3584 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3585 MODULE_ALIAS("snd-hda-codec-atihdmi");
3586
3587 static struct hda_codec_driver hdmi_driver = {
3588 .id = snd_hda_id_hdmi,
3589 };
3590
3591 module_hda_codec_driver(hdmi_driver);
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