1 #ifndef __SOUND_ICE1712_H
2 #define __SOUND_ICE1712_H
5 * ALSA driver for ICEnsemble ICE1712 (Envy24)
7 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <sound/control.h>
26 #include <sound/ac97_codec.h>
27 #include <sound/rawmidi.h>
28 #include <sound/i2c.h>
29 #include <sound/ak4xxx-adda.h>
30 #include <sound/ak4114.h>
31 #include <sound/pcm.h>
38 #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
40 #define ICE1712_REG_CONTROL 0x00 /* byte */
41 #define ICE1712_RESET 0x80 /* reset whole chip */
42 #define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */
43 #define ICE1712_NATIVE 0x01 /* native mode otherwise SB */
44 #define ICE1712_REG_IRQMASK 0x01 /* byte */
45 #define ICE1712_IRQ_MPU1 0x80
46 #define ICE1712_IRQ_TIMER 0x40
47 #define ICE1712_IRQ_MPU2 0x20
48 #define ICE1712_IRQ_PROPCM 0x10
49 #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
50 #define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */
51 #define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */
52 #define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */
53 #define ICE1712_REG_IRQSTAT 0x02 /* byte */
54 /* look to ICE1712_IRQ_* */
55 #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
56 #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
57 #define ICE1712_REG_NMI_STAT1 0x05 /* byte */
58 #define ICE1712_REG_NMI_DATA 0x06 /* byte */
59 #define ICE1712_REG_NMI_INDEX 0x07 /* byte */
60 #define ICE1712_REG_AC97_INDEX 0x08 /* byte */
61 #define ICE1712_REG_AC97_CMD 0x09 /* byte */
62 #define ICE1712_AC97_COLD 0x80 /* cold reset */
63 #define ICE1712_AC97_WARM 0x40 /* warm reset */
64 #define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */
65 #define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */
66 #define ICE1712_AC97_READY 0x08 /* codec ready status bit */
67 #define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */
68 #define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */
69 #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
70 #define ICE1712_REG_MPU1_CTRL 0x0c /* byte */
71 #define ICE1712_REG_MPU1_DATA 0x0d /* byte */
72 #define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */
73 #define ICE1712_I2C_WRITE 0x01 /* write direction */
74 #define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */
75 #define ICE1712_REG_I2C_DATA 0x12 /* byte */
76 #define ICE1712_REG_I2C_CTRL 0x13 /* byte */
77 #define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */
78 #define ICE1712_I2C_BUSY 0x01 /* busy bit */
79 #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
80 #define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */
81 #define ICE1712_REG_SERR_SHADOW 0x1b /* byte */
82 #define ICE1712_REG_MPU2_CTRL 0x1c /* byte */
83 #define ICE1712_REG_MPU2_DATA 0x1d /* byte */
84 #define ICE1712_REG_TIMER 0x1e /* word */
90 #define ICE1712_IREG_PBK_COUNT_LO 0x00
91 #define ICE1712_IREG_PBK_COUNT_HI 0x01
92 #define ICE1712_IREG_PBK_CTRL 0x02
93 #define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */
94 #define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */
95 #define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */
96 #define ICE1712_IREG_PBK_RATE_LO 0x06
97 #define ICE1712_IREG_PBK_RATE_MID 0x07
98 #define ICE1712_IREG_PBK_RATE_HI 0x08
99 #define ICE1712_IREG_CAP_COUNT_LO 0x10
100 #define ICE1712_IREG_CAP_COUNT_HI 0x11
101 #define ICE1712_IREG_CAP_CTRL 0x12
102 #define ICE1712_IREG_GPIO_DATA 0x20
103 #define ICE1712_IREG_GPIO_WRITE_MASK 0x21
104 #define ICE1712_IREG_GPIO_DIRECTION 0x22
105 #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
106 #define ICE1712_IREG_PRO_POWERDOWN 0x31
109 * Consumer section direct DMA registers
112 #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
114 #define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */
115 #define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */
116 #define ICE1712_DS_DATA 0x04 /* dword - channel data */
117 #define ICE1712_DS_INDEX 0x08 /* dword - channel index */
120 * Consumer section channel registers
123 #define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */
124 #define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */
125 #define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */
126 #define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */
127 #define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */
128 #define ICE1712_BUFFER1 0x80 /* buffer1 is active */
129 #define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */
130 #define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */
131 #define ICE1712_FLUSH 0x10 /* flush FIFO */
132 #define ICE1712_STEREO 0x08 /* stereo */
133 #define ICE1712_16BIT 0x04 /* 16-bit data */
134 #define ICE1712_PAUSE 0x02 /* pause */
135 #define ICE1712_START 0x01 /* start */
136 #define ICE1712_DSC_RATE 0x05 /* dword - rate */
137 #define ICE1712_DSC_VOLUME 0x06 /* word - volume control */
140 * Professional multi-track direct control registers
143 #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
145 #define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */
146 #define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */
147 #define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */
148 #define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */
149 #define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */
150 #define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */
151 #define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
152 #define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
153 #define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
154 #define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
155 /* look to ICE1712_AC97_* */
156 #define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */
157 #define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
158 #define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */
159 #define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */
160 #define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */
161 #define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */
162 #define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */
163 #define ICE1712_PLAYBACK_START 0x01 /* playback start */
164 #define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
165 #define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */
166 #define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */
167 #define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */
168 #define ICE1712_CAPTURE_START 0x01 /* capture start */
169 #define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */
170 #define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */
171 #define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */
172 #define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */
173 #define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */
174 #define ICE1712_MT_MONITOR_RATE 0x3b /* byte */
175 #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */
176 #define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */
177 #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */
178 #define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */
181 * Codec configuration bits
184 /* PCI[60] System Configuration */
185 #define ICE1712_CFG_CLOCK 0xc0
186 #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
187 #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
188 #define ICE1712_CFG_EXT 0x80 /* external clock */
189 #define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */
190 #define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */
191 #define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */
192 #define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
193 /* PCI[61] AC-Link Configuration */
194 #define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
195 #define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
196 /* PCI[62] I2S Features */
197 #define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
198 #define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
199 #define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
200 #define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */
201 /* PCI[63] S/PDIF Configuration */
202 #define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */
203 #define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
204 #define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */
208 * identical with DMA_XXX on i386 architecture.
210 #define ICE1712_DMA_MODE_WRITE 0x48
211 #define ICE1712_DMA_AUTOINIT 0x10
220 struct snd_ice1712_eeprom
{
221 unsigned int subvendor
; /* PCI[2c-2f] */
222 unsigned char size
; /* size of EEPROM image in bytes */
223 unsigned char version
; /* must be 1 (or 2 for vt1724) */
224 unsigned char data
[32];
225 unsigned int gpiomask
;
226 unsigned int gpiostate
;
227 unsigned int gpiodir
;
231 ICE_EEP1_CODEC
= 0, /* 06 */
232 ICE_EEP1_ACLINK
, /* 07 */
233 ICE_EEP1_I2SID
, /* 08 */
234 ICE_EEP1_SPDIF
, /* 09 */
235 ICE_EEP1_GPIO_MASK
, /* 0a */
236 ICE_EEP1_GPIO_STATE
, /* 0b */
237 ICE_EEP1_GPIO_DIR
, /* 0c */
238 ICE_EEP1_AC97_MAIN_LO
, /* 0d */
239 ICE_EEP1_AC97_MAIN_HI
, /* 0e */
240 ICE_EEP1_AC97_PCM_LO
, /* 0f */
241 ICE_EEP1_AC97_PCM_HI
, /* 10 */
242 ICE_EEP1_AC97_REC_LO
, /* 11 */
243 ICE_EEP1_AC97_REC_HI
, /* 12 */
244 ICE_EEP1_AC97_RECSRC
, /* 13 */
245 ICE_EEP1_DAC_ID
, /* 14 */
249 ICE_EEP1_ADC_ID
, /* 18 */
255 #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
258 struct snd_ak4xxx_private
{
259 unsigned int cif
: 1; /* CIF mode */
260 unsigned char caddr
; /* C0 and C1 bits */
261 unsigned int data_mask
; /* DATA gpio bit */
262 unsigned int clk_mask
; /* CLK gpio bit */
263 unsigned int cs_mask
; /* bit mask for select/deselect address */
264 unsigned int cs_addr
; /* bits to select address */
265 unsigned int cs_none
; /* bits to deselect address */
266 unsigned int add_flags
; /* additional bits at init */
267 unsigned int mask_flags
; /* total mask bits */
268 struct snd_akm4xxx_ops
{
269 void (*set_rate_val
)(struct snd_akm4xxx
*ak
, unsigned int rate
);
273 struct snd_ice1712_spdif
{
274 unsigned char cs8403_bits
;
275 unsigned char cs8403_stream_bits
;
276 struct snd_kcontrol
*stream_ctl
;
278 struct snd_ice1712_spdif_ops
{
279 void (*open
)(struct snd_ice1712
*, struct snd_pcm_substream
*);
280 void (*setup_rate
)(struct snd_ice1712
*, int rate
);
281 void (*close
)(struct snd_ice1712
*, struct snd_pcm_substream
*);
282 void (*default_get
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
283 int (*default_put
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
284 void (*stream_get
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
285 int (*stream_put
)(struct snd_ice1712
*, struct snd_ctl_elem_value
*ucontrol
);
291 unsigned long conp_dma_size
;
292 unsigned long conc_dma_size
;
293 unsigned long prop_dma_size
;
294 unsigned long proc_dma_size
;
298 unsigned long ddma_port
;
299 unsigned long dmapath_port
;
300 unsigned long profi_port
;
303 struct snd_card
*card
;
305 struct snd_pcm
*pcm_ds
;
306 struct snd_pcm
*pcm_pro
;
307 struct snd_pcm_substream
*playback_con_substream
;
308 struct snd_pcm_substream
*playback_con_substream_ds
[6];
309 struct snd_pcm_substream
*capture_con_substream
;
310 struct snd_pcm_substream
*playback_pro_substream
;
311 struct snd_pcm_substream
*capture_pro_substream
;
312 unsigned int playback_pro_size
;
313 unsigned int capture_pro_size
;
314 unsigned int playback_con_virt_addr
[6];
315 unsigned int playback_con_active_buf
[6];
316 unsigned int capture_con_virt_addr
;
317 unsigned int ac97_ext_id
;
318 struct snd_ac97
*ac97
;
319 struct snd_rawmidi
*rmidi
[2];
322 struct snd_info_entry
*proc_entry
;
324 struct snd_ice1712_eeprom eeprom
;
326 unsigned int pro_volumes
[20];
327 unsigned int omni
: 1; /* Delta Omni I/O */
328 unsigned int dxr_enable
: 1; /* Terratec DXR enable for DMX6FIRE */
329 unsigned int vt1724
: 1;
330 unsigned int vt1720
: 1;
331 unsigned int has_spdif
: 1; /* VT1720/4 - has SPDIF I/O */
332 unsigned int force_pdma4
: 1; /* VT1720/4 - PDMA4 as non-spdif */
333 unsigned int force_rdma1
: 1; /* VT1720/4 - RDMA1 as non-spdif */
334 unsigned int num_total_dacs
; /* total DACs */
335 unsigned int num_total_adcs
; /* total ADCs */
336 unsigned int cur_rate
; /* current rate */
338 struct mutex open_mutex
;
339 struct snd_pcm_substream
*pcm_reserved
[4];
340 struct snd_pcm_hw_constraint_list
*hw_rates
; /* card-specific rate constraints */
342 unsigned int akm_codecs
;
343 struct snd_akm4xxx
*akm
;
344 struct snd_ice1712_spdif spdif
;
346 struct mutex i2c_mutex
; /* I2C mutex for ICE1724 registers */
347 struct snd_i2c_bus
*i2c
; /* I2C bus */
348 struct snd_i2c_device
*cs8427
; /* CS8427 I2C device */
349 unsigned int cs8427_timeout
; /* CS8427 reset timeout in HZ/100 */
351 struct ice1712_gpio
{
352 unsigned int direction
; /* current direction bits */
353 unsigned int write_mask
; /* current mask bits */
354 unsigned int saved
[2]; /* for ewx_i2c */
356 void (*set_mask
)(struct snd_ice1712
*ice
, unsigned int data
);
357 void (*set_dir
)(struct snd_ice1712
*ice
, unsigned int data
);
358 void (*set_data
)(struct snd_ice1712
*ice
, unsigned int data
);
359 unsigned int (*get_data
)(struct snd_ice1712
*ice
);
360 /* misc operators - move to another place? */
361 void (*set_pro_rate
)(struct snd_ice1712
*ice
, unsigned int rate
);
362 void (*i2s_mclk_changed
)(struct snd_ice1712
*ice
);
364 struct mutex gpio_mutex
;
366 /* other board-specific data */
368 /* additional i2c devices for EWS boards */
369 struct snd_i2c_device
*i2cdevs
[3];
370 /* AC97 register cache for Aureon */
372 unsigned short stac9744
[64];
373 unsigned int cs8415_mux
;
374 unsigned short master
[2];
375 unsigned short vol
[8];
377 /* AC97 register cache for Phase28 */
378 struct phase28_spec
{
379 unsigned short master
[2];
380 unsigned short vol
[8];
382 /* Hoontech-specific setting */
383 struct hoontech_spec
{
384 unsigned char boxbits
[4];
386 unsigned short boxconfig
[4];
389 struct ak4114
*ak4114
;
390 unsigned int analog
: 1;
398 * gpio access functions
400 static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712
*ice
, unsigned int bits
)
402 ice
->gpio
.set_dir(ice
, bits
);
405 static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712
*ice
, unsigned int bits
)
407 ice
->gpio
.set_mask(ice
, bits
);
410 static inline void snd_ice1712_gpio_write(struct snd_ice1712
*ice
, unsigned int val
)
412 ice
->gpio
.set_data(ice
, val
);
415 static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712
*ice
)
417 return ice
->gpio
.get_data(ice
);
421 * save and restore gpio status
422 * The access to gpio will be protected by mutex, so don't forget to
425 static inline void snd_ice1712_save_gpio_status(struct snd_ice1712
*ice
)
427 mutex_lock(&ice
->gpio_mutex
);
428 ice
->gpio
.saved
[0] = ice
->gpio
.direction
;
429 ice
->gpio
.saved
[1] = ice
->gpio
.write_mask
;
432 static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712
*ice
)
434 ice
->gpio
.set_dir(ice
, ice
->gpio
.saved
[0]);
435 ice
->gpio
.set_mask(ice
, ice
->gpio
.saved
[1]);
436 ice
->gpio
.direction
= ice
->gpio
.saved
[0];
437 ice
->gpio
.write_mask
= ice
->gpio
.saved
[1];
438 mutex_unlock(&ice
->gpio_mutex
);
441 /* for bit controls */
442 #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
443 { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ice1712_gpio_info, \
444 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
445 .private_value = mask | (invert << 24) }
447 int snd_ice1712_gpio_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
);
448 int snd_ice1712_gpio_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
);
449 int snd_ice1712_gpio_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
);
452 * set gpio direction, write mask and data
454 static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712
*ice
,
455 unsigned int mask
, unsigned int bits
)
457 ice
->gpio
.direction
|= mask
;
458 snd_ice1712_gpio_set_dir(ice
, ice
->gpio
.direction
);
459 snd_ice1712_gpio_set_mask(ice
, ~mask
);
460 snd_ice1712_gpio_write(ice
, mask
& bits
);
463 int snd_ice1712_spdif_build_controls(struct snd_ice1712
*ice
);
465 int snd_ice1712_akm4xxx_init(struct snd_akm4xxx
*ak
, const struct snd_akm4xxx
*template,
466 const struct snd_ak4xxx_private
*priv
, struct snd_ice1712
*ice
);
467 void snd_ice1712_akm4xxx_free(struct snd_ice1712
*ice
);
468 int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712
*ice
);
470 int snd_ice1712_init_cs8427(struct snd_ice1712
*ice
, int addr
);
472 static inline void snd_ice1712_write(struct snd_ice1712
* ice
, u8 addr
, u8 data
)
474 outb(addr
, ICEREG(ice
, INDEX
));
475 outb(data
, ICEREG(ice
, DATA
));
478 static inline u8
snd_ice1712_read(struct snd_ice1712
* ice
, u8 addr
)
480 outb(addr
, ICEREG(ice
, INDEX
));
481 return inb(ICEREG(ice
, DATA
));
489 struct snd_ice1712_card_info
{
490 unsigned int subvendor
;
494 int (*chip_init
)(struct snd_ice1712
*);
495 int (*build_controls
)(struct snd_ice1712
*);
496 unsigned int no_mpu401
: 1;
497 unsigned int eeprom_size
;
498 unsigned char *eeprom_data
;
502 #endif /* __SOUND_ICE1712_H */