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Merge branch 'for-3.14-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[mirror_ubuntu-bionic-kernel.git] / sound / pci / intel8x0.c
1 /*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/pcm.h>
38 #include <sound/ac97_codec.h>
39 #include <sound/info.h>
40 #include <sound/initval.h>
41 /* for 440MX workaround */
42 #include <asm/pgtable.h>
43 #include <asm/cacheflush.h>
44
45 #ifdef CONFIG_KVM_GUEST
46 #include <linux/kvm_para.h>
47 #else
48 #define kvm_para_available() (0)
49 #endif
50
51 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
52 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
53 MODULE_LICENSE("GPL");
54 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
55 "{Intel,82901AB-ICH0},"
56 "{Intel,82801BA-ICH2},"
57 "{Intel,82801CA-ICH3},"
58 "{Intel,82801DB-ICH4},"
59 "{Intel,ICH5},"
60 "{Intel,ICH6},"
61 "{Intel,ICH7},"
62 "{Intel,6300ESB},"
63 "{Intel,ESB2},"
64 "{Intel,MX440},"
65 "{SiS,SI7012},"
66 "{NVidia,nForce Audio},"
67 "{NVidia,nForce2 Audio},"
68 "{NVidia,nForce3 Audio},"
69 "{NVidia,MCP04},"
70 "{NVidia,MCP501},"
71 "{NVidia,CK804},"
72 "{NVidia,CK8},"
73 "{NVidia,CK8S},"
74 "{AMD,AMD768},"
75 "{AMD,AMD8111},"
76 "{ALI,M5455}}");
77
78 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
79 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
80 static int ac97_clock;
81 static char *ac97_quirk;
82 static bool buggy_semaphore;
83 static int buggy_irq = -1; /* auto-check */
84 static bool xbox;
85 static int spdif_aclink = -1;
86 static int inside_vm = -1;
87
88 module_param(index, int, 0444);
89 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
90 module_param(id, charp, 0444);
91 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
92 module_param(ac97_clock, int, 0444);
93 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
94 module_param(ac97_quirk, charp, 0444);
95 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
96 module_param(buggy_semaphore, bool, 0444);
97 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
98 module_param(buggy_irq, bint, 0444);
99 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
100 module_param(xbox, bool, 0444);
101 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
102 module_param(spdif_aclink, int, 0444);
103 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
104 module_param(inside_vm, bint, 0444);
105 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
106
107 /* just for backward compatibility */
108 static bool enable;
109 module_param(enable, bool, 0444);
110 static int joystick;
111 module_param(joystick, int, 0444);
112
113 /*
114 * Direct registers
115 */
116 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
117
118 #define ICHREG(x) ICH_REG_##x
119
120 #define DEFINE_REGSET(name,base) \
121 enum { \
122 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
123 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
124 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
125 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
126 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
127 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
128 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
129 };
130
131 /* busmaster blocks */
132 DEFINE_REGSET(OFF, 0); /* offset */
133 DEFINE_REGSET(PI, 0x00); /* PCM in */
134 DEFINE_REGSET(PO, 0x10); /* PCM out */
135 DEFINE_REGSET(MC, 0x20); /* Mic in */
136
137 /* ICH4 busmaster blocks */
138 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
139 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
140 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
141
142 /* values for each busmaster block */
143
144 /* LVI */
145 #define ICH_REG_LVI_MASK 0x1f
146
147 /* SR */
148 #define ICH_FIFOE 0x10 /* FIFO error */
149 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
150 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
151 #define ICH_CELV 0x02 /* current equals last valid */
152 #define ICH_DCH 0x01 /* DMA controller halted */
153
154 /* PIV */
155 #define ICH_REG_PIV_MASK 0x1f /* mask */
156
157 /* CR */
158 #define ICH_IOCE 0x10 /* interrupt on completion enable */
159 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
160 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
161 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
162 #define ICH_STARTBM 0x01 /* start busmaster operation */
163
164
165 /* global block */
166 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
167 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
168 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
169 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
170 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
171 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
172 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
173 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
174 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
175 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
176 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
177 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
178 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
179 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
180 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
181 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
182 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
183 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
184 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
185 #define ICH_ACLINK 0x00000008 /* AClink shut off */
186 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
187 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
188 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
189 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
190 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
191 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
192 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
193 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
194 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
195 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
196 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
197 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
198 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
199 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
200 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
201 #define ICH_MD3 0x00020000 /* modem power down semaphore */
202 #define ICH_AD3 0x00010000 /* audio power down semaphore */
203 #define ICH_RCS 0x00008000 /* read completion status */
204 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
205 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
206 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
207 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
208 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
209 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
210 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
211 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
212 #define ICH_POINT 0x00000040 /* playback interrupt */
213 #define ICH_PIINT 0x00000020 /* capture interrupt */
214 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
215 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
216 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
217 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
218 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
219 #define ICH_CAS 0x01 /* codec access semaphore */
220 #define ICH_REG_SDM 0x80
221 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
222 #define ICH_DI2L_SHIFT 6
223 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
224 #define ICH_DI1L_SHIFT 4
225 #define ICH_SE 0x00000008 /* steer enable */
226 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
227
228 #define ICH_MAX_FRAGS 32 /* max hw frags */
229
230
231 /*
232 * registers for Ali5455
233 */
234
235 /* ALi 5455 busmaster blocks */
236 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
237 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
238 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
239 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
240 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
241 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
242 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
243 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
244 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
245 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
246 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
247
248 enum {
249 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
250 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
251 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
252 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
253 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
254 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
255 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
256 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
257 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
258 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
259 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
260 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
261 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
262 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
263 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
264 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
265 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
266 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
267 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
268 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
269 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
270 };
271
272 #define ALI_CAS_SEM_BUSY 0x80000000
273 #define ALI_CPR_ADDR_SECONDARY 0x100
274 #define ALI_CPR_ADDR_READ 0x80
275 #define ALI_CSPSR_CODEC_READY 0x08
276 #define ALI_CSPSR_READ_OK 0x02
277 #define ALI_CSPSR_WRITE_OK 0x01
278
279 /* interrupts for the whole chip by interrupt status register finish */
280
281 #define ALI_INT_MICIN2 (1<<26)
282 #define ALI_INT_PCMIN2 (1<<25)
283 #define ALI_INT_I2SIN (1<<24)
284 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
285 #define ALI_INT_SPDIFIN (1<<22)
286 #define ALI_INT_LFEOUT (1<<21)
287 #define ALI_INT_CENTEROUT (1<<20)
288 #define ALI_INT_CODECSPDIFOUT (1<<19)
289 #define ALI_INT_MICIN (1<<18)
290 #define ALI_INT_PCMOUT (1<<17)
291 #define ALI_INT_PCMIN (1<<16)
292 #define ALI_INT_CPRAIS (1<<7) /* command port available */
293 #define ALI_INT_SPRAIS (1<<5) /* status port available */
294 #define ALI_INT_GPIO (1<<1)
295 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
296 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
297
298 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
299 #define ICH_ALI_SC_AC97_DBL (1<<30)
300 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
301 #define ICH_ALI_SC_IN_BITS (3<<18)
302 #define ICH_ALI_SC_OUT_BITS (3<<16)
303 #define ICH_ALI_SC_6CH_CFG (3<<14)
304 #define ICH_ALI_SC_PCM_4 (1<<8)
305 #define ICH_ALI_SC_PCM_6 (2<<8)
306 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
307
308 #define ICH_ALI_SS_SEC_ID (3<<5)
309 #define ICH_ALI_SS_PRI_ID (3<<3)
310
311 #define ICH_ALI_IF_AC97SP (1<<21)
312 #define ICH_ALI_IF_MC (1<<20)
313 #define ICH_ALI_IF_PI (1<<19)
314 #define ICH_ALI_IF_MC2 (1<<18)
315 #define ICH_ALI_IF_PI2 (1<<17)
316 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
317 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
318 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
319 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
320 #define ICH_ALI_IF_PO_SPDF (1<<3)
321 #define ICH_ALI_IF_PO (1<<1)
322
323 /*
324 *
325 */
326
327 enum {
328 ICHD_PCMIN,
329 ICHD_PCMOUT,
330 ICHD_MIC,
331 ICHD_MIC2,
332 ICHD_PCM2IN,
333 ICHD_SPBAR,
334 ICHD_LAST = ICHD_SPBAR
335 };
336 enum {
337 NVD_PCMIN,
338 NVD_PCMOUT,
339 NVD_MIC,
340 NVD_SPBAR,
341 NVD_LAST = NVD_SPBAR
342 };
343 enum {
344 ALID_PCMIN,
345 ALID_PCMOUT,
346 ALID_MIC,
347 ALID_AC97SPDIFOUT,
348 ALID_SPDIFIN,
349 ALID_SPDIFOUT,
350 ALID_LAST = ALID_SPDIFOUT
351 };
352
353 #define get_ichdev(substream) (substream->runtime->private_data)
354
355 struct ichdev {
356 unsigned int ichd; /* ich device number */
357 unsigned long reg_offset; /* offset to bmaddr */
358 u32 *bdbar; /* CPU address (32bit) */
359 unsigned int bdbar_addr; /* PCI bus address (32bit) */
360 struct snd_pcm_substream *substream;
361 unsigned int physbuf; /* physical address (32bit) */
362 unsigned int size;
363 unsigned int fragsize;
364 unsigned int fragsize1;
365 unsigned int position;
366 unsigned int pos_shift;
367 unsigned int last_pos;
368 int frags;
369 int lvi;
370 int lvi_frag;
371 int civ;
372 int ack;
373 int ack_reload;
374 unsigned int ack_bit;
375 unsigned int roff_sr;
376 unsigned int roff_picb;
377 unsigned int int_sta_mask; /* interrupt status mask */
378 unsigned int ali_slot; /* ALI DMA slot */
379 struct ac97_pcm *pcm;
380 int pcm_open_flag;
381 unsigned int page_attr_changed: 1;
382 unsigned int suspended: 1;
383 };
384
385 struct intel8x0 {
386 unsigned int device_type;
387
388 int irq;
389
390 void __iomem *addr;
391 void __iomem *bmaddr;
392
393 struct pci_dev *pci;
394 struct snd_card *card;
395
396 int pcm_devs;
397 struct snd_pcm *pcm[6];
398 struct ichdev ichd[6];
399
400 unsigned multi4: 1,
401 multi6: 1,
402 multi8 :1,
403 dra: 1,
404 smp20bit: 1;
405 unsigned in_ac97_init: 1,
406 in_sdin_init: 1;
407 unsigned in_measurement: 1; /* during ac97 clock measurement */
408 unsigned fix_nocache: 1; /* workaround for 440MX */
409 unsigned buggy_irq: 1; /* workaround for buggy mobos */
410 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
411 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
412 unsigned inside_vm: 1; /* enable VM optimization */
413
414 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
415 unsigned int sdm_saved; /* SDM reg value */
416
417 struct snd_ac97_bus *ac97_bus;
418 struct snd_ac97 *ac97[3];
419 unsigned int ac97_sdin[3];
420 unsigned int max_codecs, ncodecs;
421 unsigned int *codec_bit;
422 unsigned int codec_isr_bits;
423 unsigned int codec_ready_bits;
424
425 spinlock_t reg_lock;
426
427 u32 bdbars_count;
428 struct snd_dma_buffer bdbars;
429 u32 int_sta_reg; /* interrupt status register */
430 u32 int_sta_mask; /* interrupt status mask */
431 };
432
433 static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
434 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
435 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
436 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
437 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
438 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
439 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
440 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
441 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
442 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
443 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
444 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
445 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
446 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
447 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
448 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
449 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
450 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
451 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
452 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
453 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
454 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
455 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
456 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
457 { 0, }
458 };
459
460 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
461
462 /*
463 * Lowlevel I/O - busmaster
464 */
465
466 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
467 {
468 return ioread8(chip->bmaddr + offset);
469 }
470
471 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
472 {
473 return ioread16(chip->bmaddr + offset);
474 }
475
476 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
477 {
478 return ioread32(chip->bmaddr + offset);
479 }
480
481 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
482 {
483 iowrite8(val, chip->bmaddr + offset);
484 }
485
486 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
487 {
488 iowrite16(val, chip->bmaddr + offset);
489 }
490
491 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
492 {
493 iowrite32(val, chip->bmaddr + offset);
494 }
495
496 /*
497 * Lowlevel I/O - AC'97 registers
498 */
499
500 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
501 {
502 return ioread16(chip->addr + offset);
503 }
504
505 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
506 {
507 iowrite16(val, chip->addr + offset);
508 }
509
510 /*
511 * Basic I/O
512 */
513
514 /*
515 * access to AC97 codec via normal i/o (for ICH and SIS7012)
516 */
517
518 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
519 {
520 int time;
521
522 if (codec > 2)
523 return -EIO;
524 if (chip->in_sdin_init) {
525 /* we don't know the ready bit assignment at the moment */
526 /* so we check any */
527 codec = chip->codec_isr_bits;
528 } else {
529 codec = chip->codec_bit[chip->ac97_sdin[codec]];
530 }
531
532 /* codec ready ? */
533 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
534 return -EIO;
535
536 if (chip->buggy_semaphore)
537 return 0; /* just ignore ... */
538
539 /* Anyone holding a semaphore for 1 msec should be shot... */
540 time = 100;
541 do {
542 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
543 return 0;
544 udelay(10);
545 } while (time--);
546
547 /* access to some forbidden (non existent) ac97 registers will not
548 * reset the semaphore. So even if you don't get the semaphore, still
549 * continue the access. We don't need the semaphore anyway. */
550 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
551 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
552 iagetword(chip, 0); /* clear semaphore flag */
553 /* I don't care about the semaphore */
554 return -EBUSY;
555 }
556
557 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
558 unsigned short reg,
559 unsigned short val)
560 {
561 struct intel8x0 *chip = ac97->private_data;
562
563 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
564 if (! chip->in_ac97_init)
565 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
566 }
567 iaputword(chip, reg + ac97->num * 0x80, val);
568 }
569
570 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
571 unsigned short reg)
572 {
573 struct intel8x0 *chip = ac97->private_data;
574 unsigned short res;
575 unsigned int tmp;
576
577 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
578 if (! chip->in_ac97_init)
579 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
580 res = 0xffff;
581 } else {
582 res = iagetword(chip, reg + ac97->num * 0x80);
583 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
584 /* reset RCS and preserve other R/WC bits */
585 iputdword(chip, ICHREG(GLOB_STA), tmp &
586 ~(chip->codec_ready_bits | ICH_GSCI));
587 if (! chip->in_ac97_init)
588 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
589 res = 0xffff;
590 }
591 }
592 return res;
593 }
594
595 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
596 unsigned int codec)
597 {
598 unsigned int tmp;
599
600 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
601 iagetword(chip, codec * 0x80);
602 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
603 /* reset RCS and preserve other R/WC bits */
604 iputdword(chip, ICHREG(GLOB_STA), tmp &
605 ~(chip->codec_ready_bits | ICH_GSCI));
606 }
607 }
608 }
609
610 /*
611 * access to AC97 for Ali5455
612 */
613 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
614 {
615 int count = 0;
616 for (count = 0; count < 0x7f; count++) {
617 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
618 if (val & mask)
619 return 0;
620 }
621 if (! chip->in_ac97_init)
622 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
623 return -EBUSY;
624 }
625
626 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
627 {
628 int time = 100;
629 if (chip->buggy_semaphore)
630 return 0; /* just ignore ... */
631 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
632 udelay(1);
633 if (! time && ! chip->in_ac97_init)
634 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
635 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
636 }
637
638 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
639 {
640 struct intel8x0 *chip = ac97->private_data;
641 unsigned short data = 0xffff;
642
643 if (snd_intel8x0_ali_codec_semaphore(chip))
644 goto __err;
645 reg |= ALI_CPR_ADDR_READ;
646 if (ac97->num)
647 reg |= ALI_CPR_ADDR_SECONDARY;
648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
649 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
650 goto __err;
651 data = igetword(chip, ICHREG(ALI_SPR));
652 __err:
653 return data;
654 }
655
656 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
657 unsigned short val)
658 {
659 struct intel8x0 *chip = ac97->private_data;
660
661 if (snd_intel8x0_ali_codec_semaphore(chip))
662 return;
663 iputword(chip, ICHREG(ALI_CPR), val);
664 if (ac97->num)
665 reg |= ALI_CPR_ADDR_SECONDARY;
666 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
667 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
668 }
669
670
671 /*
672 * DMA I/O
673 */
674 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
675 {
676 int idx;
677 u32 *bdbar = ichdev->bdbar;
678 unsigned long port = ichdev->reg_offset;
679
680 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
681 if (ichdev->size == ichdev->fragsize) {
682 ichdev->ack_reload = ichdev->ack = 2;
683 ichdev->fragsize1 = ichdev->fragsize >> 1;
684 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
685 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
686 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
687 ichdev->fragsize1 >> ichdev->pos_shift);
688 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
689 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690 ichdev->fragsize1 >> ichdev->pos_shift);
691 }
692 ichdev->frags = 2;
693 } else {
694 ichdev->ack_reload = ichdev->ack = 1;
695 ichdev->fragsize1 = ichdev->fragsize;
696 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
697 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
698 (((idx >> 1) * ichdev->fragsize) %
699 ichdev->size));
700 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
701 ichdev->fragsize >> ichdev->pos_shift);
702 #if 0
703 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
704 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
705 #endif
706 }
707 ichdev->frags = ichdev->size / ichdev->fragsize;
708 }
709 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
710 ichdev->civ = 0;
711 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
712 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
713 ichdev->position = 0;
714 #if 0
715 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
716 "period_size1 = 0x%x\n",
717 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
718 ichdev->fragsize1);
719 #endif
720 /* clear interrupts */
721 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
722 }
723
724 #ifdef __i386__
725 /*
726 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
727 * which aborts PCI busmaster for audio transfer. A workaround is to set
728 * the pages as non-cached. For details, see the errata in
729 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
730 */
731 static void fill_nocache(void *buf, int size, int nocache)
732 {
733 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
734 if (nocache)
735 set_pages_uc(virt_to_page(buf), size);
736 else
737 set_pages_wb(virt_to_page(buf), size);
738 }
739 #else
740 #define fill_nocache(buf, size, nocache) do { ; } while (0)
741 #endif
742
743 /*
744 * Interrupt handler
745 */
746
747 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
748 {
749 unsigned long port = ichdev->reg_offset;
750 unsigned long flags;
751 int status, civ, i, step;
752 int ack = 0;
753
754 spin_lock_irqsave(&chip->reg_lock, flags);
755 status = igetbyte(chip, port + ichdev->roff_sr);
756 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
757 if (!(status & ICH_BCIS)) {
758 step = 0;
759 } else if (civ == ichdev->civ) {
760 // snd_printd("civ same %d\n", civ);
761 step = 1;
762 ichdev->civ++;
763 ichdev->civ &= ICH_REG_LVI_MASK;
764 } else {
765 step = civ - ichdev->civ;
766 if (step < 0)
767 step += ICH_REG_LVI_MASK + 1;
768 // if (step != 1)
769 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
770 ichdev->civ = civ;
771 }
772
773 ichdev->position += step * ichdev->fragsize1;
774 if (! chip->in_measurement)
775 ichdev->position %= ichdev->size;
776 ichdev->lvi += step;
777 ichdev->lvi &= ICH_REG_LVI_MASK;
778 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
779 for (i = 0; i < step; i++) {
780 ichdev->lvi_frag++;
781 ichdev->lvi_frag %= ichdev->frags;
782 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
783 #if 0
784 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
785 "all = 0x%x, 0x%x\n",
786 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
787 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
788 inl(port + 4), inb(port + ICH_REG_OFF_CR));
789 #endif
790 if (--ichdev->ack == 0) {
791 ichdev->ack = ichdev->ack_reload;
792 ack = 1;
793 }
794 }
795 spin_unlock_irqrestore(&chip->reg_lock, flags);
796 if (ack && ichdev->substream) {
797 snd_pcm_period_elapsed(ichdev->substream);
798 }
799 iputbyte(chip, port + ichdev->roff_sr,
800 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
801 }
802
803 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
804 {
805 struct intel8x0 *chip = dev_id;
806 struct ichdev *ichdev;
807 unsigned int status;
808 unsigned int i;
809
810 status = igetdword(chip, chip->int_sta_reg);
811 if (status == 0xffffffff) /* we are not yet resumed */
812 return IRQ_NONE;
813
814 if ((status & chip->int_sta_mask) == 0) {
815 if (status) {
816 /* ack */
817 iputdword(chip, chip->int_sta_reg, status);
818 if (! chip->buggy_irq)
819 status = 0;
820 }
821 return IRQ_RETVAL(status);
822 }
823
824 for (i = 0; i < chip->bdbars_count; i++) {
825 ichdev = &chip->ichd[i];
826 if (status & ichdev->int_sta_mask)
827 snd_intel8x0_update(chip, ichdev);
828 }
829
830 /* ack them */
831 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
832
833 return IRQ_HANDLED;
834 }
835
836 /*
837 * PCM part
838 */
839
840 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
841 {
842 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
843 struct ichdev *ichdev = get_ichdev(substream);
844 unsigned char val = 0;
845 unsigned long port = ichdev->reg_offset;
846
847 switch (cmd) {
848 case SNDRV_PCM_TRIGGER_RESUME:
849 ichdev->suspended = 0;
850 /* fallthru */
851 case SNDRV_PCM_TRIGGER_START:
852 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
853 val = ICH_IOCE | ICH_STARTBM;
854 ichdev->last_pos = ichdev->position;
855 break;
856 case SNDRV_PCM_TRIGGER_SUSPEND:
857 ichdev->suspended = 1;
858 /* fallthru */
859 case SNDRV_PCM_TRIGGER_STOP:
860 val = 0;
861 break;
862 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
863 val = ICH_IOCE;
864 break;
865 default:
866 return -EINVAL;
867 }
868 iputbyte(chip, port + ICH_REG_OFF_CR, val);
869 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
870 /* wait until DMA stopped */
871 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
872 /* reset whole DMA things */
873 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
874 }
875 return 0;
876 }
877
878 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
879 {
880 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
881 struct ichdev *ichdev = get_ichdev(substream);
882 unsigned long port = ichdev->reg_offset;
883 static int fiforeg[] = {
884 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
885 };
886 unsigned int val, fifo;
887
888 val = igetdword(chip, ICHREG(ALI_DMACR));
889 switch (cmd) {
890 case SNDRV_PCM_TRIGGER_RESUME:
891 ichdev->suspended = 0;
892 /* fallthru */
893 case SNDRV_PCM_TRIGGER_START:
894 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
895 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
896 /* clear FIFO for synchronization of channels */
897 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
898 fifo &= ~(0xff << (ichdev->ali_slot % 4));
899 fifo |= 0x83 << (ichdev->ali_slot % 4);
900 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
901 }
902 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
903 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
904 /* start DMA */
905 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
906 break;
907 case SNDRV_PCM_TRIGGER_SUSPEND:
908 ichdev->suspended = 1;
909 /* fallthru */
910 case SNDRV_PCM_TRIGGER_STOP:
911 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
912 /* pause */
913 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
914 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
915 while (igetbyte(chip, port + ICH_REG_OFF_CR))
916 ;
917 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
918 break;
919 /* reset whole DMA things */
920 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
921 /* clear interrupts */
922 iputbyte(chip, port + ICH_REG_OFF_SR,
923 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
924 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
925 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
926 break;
927 default:
928 return -EINVAL;
929 }
930 return 0;
931 }
932
933 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
934 struct snd_pcm_hw_params *hw_params)
935 {
936 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
937 struct ichdev *ichdev = get_ichdev(substream);
938 struct snd_pcm_runtime *runtime = substream->runtime;
939 int dbl = params_rate(hw_params) > 48000;
940 int err;
941
942 if (chip->fix_nocache && ichdev->page_attr_changed) {
943 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
944 ichdev->page_attr_changed = 0;
945 }
946 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
947 if (err < 0)
948 return err;
949 if (chip->fix_nocache) {
950 if (runtime->dma_area && ! ichdev->page_attr_changed) {
951 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
952 ichdev->page_attr_changed = 1;
953 }
954 }
955 if (ichdev->pcm_open_flag) {
956 snd_ac97_pcm_close(ichdev->pcm);
957 ichdev->pcm_open_flag = 0;
958 }
959 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
960 params_channels(hw_params),
961 ichdev->pcm->r[dbl].slots);
962 if (err >= 0) {
963 ichdev->pcm_open_flag = 1;
964 /* Force SPDIF setting */
965 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
966 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
967 params_rate(hw_params));
968 }
969 return err;
970 }
971
972 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
973 {
974 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
975 struct ichdev *ichdev = get_ichdev(substream);
976
977 if (ichdev->pcm_open_flag) {
978 snd_ac97_pcm_close(ichdev->pcm);
979 ichdev->pcm_open_flag = 0;
980 }
981 if (chip->fix_nocache && ichdev->page_attr_changed) {
982 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
983 ichdev->page_attr_changed = 0;
984 }
985 return snd_pcm_lib_free_pages(substream);
986 }
987
988 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
989 struct snd_pcm_runtime *runtime)
990 {
991 unsigned int cnt;
992 int dbl = runtime->rate > 48000;
993
994 spin_lock_irq(&chip->reg_lock);
995 switch (chip->device_type) {
996 case DEVICE_ALI:
997 cnt = igetdword(chip, ICHREG(ALI_SCR));
998 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
999 if (runtime->channels == 4 || dbl)
1000 cnt |= ICH_ALI_SC_PCM_4;
1001 else if (runtime->channels == 6)
1002 cnt |= ICH_ALI_SC_PCM_6;
1003 iputdword(chip, ICHREG(ALI_SCR), cnt);
1004 break;
1005 case DEVICE_SIS:
1006 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1007 cnt &= ~ICH_SIS_PCM_246_MASK;
1008 if (runtime->channels == 4 || dbl)
1009 cnt |= ICH_SIS_PCM_4;
1010 else if (runtime->channels == 6)
1011 cnt |= ICH_SIS_PCM_6;
1012 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1013 break;
1014 default:
1015 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1016 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1017 if (runtime->channels == 4 || dbl)
1018 cnt |= ICH_PCM_4;
1019 else if (runtime->channels == 6)
1020 cnt |= ICH_PCM_6;
1021 else if (runtime->channels == 8)
1022 cnt |= ICH_PCM_8;
1023 if (chip->device_type == DEVICE_NFORCE) {
1024 /* reset to 2ch once to keep the 6 channel data in alignment,
1025 * to start from Front Left always
1026 */
1027 if (cnt & ICH_PCM_246_MASK) {
1028 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1029 spin_unlock_irq(&chip->reg_lock);
1030 msleep(50); /* grrr... */
1031 spin_lock_irq(&chip->reg_lock);
1032 }
1033 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1034 if (runtime->sample_bits > 16)
1035 cnt |= ICH_PCM_20BIT;
1036 }
1037 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1038 break;
1039 }
1040 spin_unlock_irq(&chip->reg_lock);
1041 }
1042
1043 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1044 {
1045 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1046 struct snd_pcm_runtime *runtime = substream->runtime;
1047 struct ichdev *ichdev = get_ichdev(substream);
1048
1049 ichdev->physbuf = runtime->dma_addr;
1050 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1051 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1052 if (ichdev->ichd == ICHD_PCMOUT) {
1053 snd_intel8x0_setup_pcm_out(chip, runtime);
1054 if (chip->device_type == DEVICE_INTEL_ICH4)
1055 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1056 }
1057 snd_intel8x0_setup_periods(chip, ichdev);
1058 return 0;
1059 }
1060
1061 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1062 {
1063 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1064 struct ichdev *ichdev = get_ichdev(substream);
1065 size_t ptr1, ptr;
1066 int civ, timeout = 10;
1067 unsigned int position;
1068
1069 spin_lock(&chip->reg_lock);
1070 do {
1071 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1072 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1073 position = ichdev->position;
1074 if (ptr1 == 0) {
1075 udelay(10);
1076 continue;
1077 }
1078 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1079 continue;
1080
1081 /* IO read operation is very expensive inside virtual machine
1082 * as it is emulated. The probability that subsequent PICB read
1083 * will return different result is high enough to loop till
1084 * timeout here.
1085 * Same CIV is strict enough condition to be sure that PICB
1086 * is valid inside VM on emulated card. */
1087 if (chip->inside_vm)
1088 break;
1089 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1090 break;
1091 } while (timeout--);
1092 ptr = ichdev->last_pos;
1093 if (ptr1 != 0) {
1094 ptr1 <<= ichdev->pos_shift;
1095 ptr = ichdev->fragsize1 - ptr1;
1096 ptr += position;
1097 if (ptr < ichdev->last_pos) {
1098 unsigned int pos_base, last_base;
1099 pos_base = position / ichdev->fragsize1;
1100 last_base = ichdev->last_pos / ichdev->fragsize1;
1101 /* another sanity check; ptr1 can go back to full
1102 * before the base position is updated
1103 */
1104 if (pos_base == last_base)
1105 ptr = ichdev->last_pos;
1106 }
1107 }
1108 ichdev->last_pos = ptr;
1109 spin_unlock(&chip->reg_lock);
1110 if (ptr >= ichdev->size)
1111 return 0;
1112 return bytes_to_frames(substream->runtime, ptr);
1113 }
1114
1115 static struct snd_pcm_hardware snd_intel8x0_stream =
1116 {
1117 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1118 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1119 SNDRV_PCM_INFO_MMAP_VALID |
1120 SNDRV_PCM_INFO_PAUSE |
1121 SNDRV_PCM_INFO_RESUME),
1122 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1123 .rates = SNDRV_PCM_RATE_48000,
1124 .rate_min = 48000,
1125 .rate_max = 48000,
1126 .channels_min = 2,
1127 .channels_max = 2,
1128 .buffer_bytes_max = 128 * 1024,
1129 .period_bytes_min = 32,
1130 .period_bytes_max = 128 * 1024,
1131 .periods_min = 1,
1132 .periods_max = 1024,
1133 .fifo_size = 0,
1134 };
1135
1136 static unsigned int channels4[] = {
1137 2, 4,
1138 };
1139
1140 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1141 .count = ARRAY_SIZE(channels4),
1142 .list = channels4,
1143 .mask = 0,
1144 };
1145
1146 static unsigned int channels6[] = {
1147 2, 4, 6,
1148 };
1149
1150 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1151 .count = ARRAY_SIZE(channels6),
1152 .list = channels6,
1153 .mask = 0,
1154 };
1155
1156 static unsigned int channels8[] = {
1157 2, 4, 6, 8,
1158 };
1159
1160 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1161 .count = ARRAY_SIZE(channels8),
1162 .list = channels8,
1163 .mask = 0,
1164 };
1165
1166 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1167 {
1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1170 int err;
1171
1172 ichdev->substream = substream;
1173 runtime->hw = snd_intel8x0_stream;
1174 runtime->hw.rates = ichdev->pcm->rates;
1175 snd_pcm_limit_hw_rates(runtime);
1176 if (chip->device_type == DEVICE_SIS) {
1177 runtime->hw.buffer_bytes_max = 64*1024;
1178 runtime->hw.period_bytes_max = 64*1024;
1179 }
1180 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1181 return err;
1182 runtime->private_data = ichdev;
1183 return 0;
1184 }
1185
1186 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1187 {
1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189 struct snd_pcm_runtime *runtime = substream->runtime;
1190 int err;
1191
1192 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1193 if (err < 0)
1194 return err;
1195
1196 if (chip->multi8) {
1197 runtime->hw.channels_max = 8;
1198 snd_pcm_hw_constraint_list(runtime, 0,
1199 SNDRV_PCM_HW_PARAM_CHANNELS,
1200 &hw_constraints_channels8);
1201 } else if (chip->multi6) {
1202 runtime->hw.channels_max = 6;
1203 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1204 &hw_constraints_channels6);
1205 } else if (chip->multi4) {
1206 runtime->hw.channels_max = 4;
1207 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1208 &hw_constraints_channels4);
1209 }
1210 if (chip->dra) {
1211 snd_ac97_pcm_double_rate_rules(runtime);
1212 }
1213 if (chip->smp20bit) {
1214 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1215 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1216 }
1217 return 0;
1218 }
1219
1220 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1221 {
1222 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1223
1224 chip->ichd[ICHD_PCMOUT].substream = NULL;
1225 return 0;
1226 }
1227
1228 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1229 {
1230 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1231
1232 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1233 }
1234
1235 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1236 {
1237 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238
1239 chip->ichd[ICHD_PCMIN].substream = NULL;
1240 return 0;
1241 }
1242
1243 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1244 {
1245 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1246
1247 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1248 }
1249
1250 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1251 {
1252 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253
1254 chip->ichd[ICHD_MIC].substream = NULL;
1255 return 0;
1256 }
1257
1258 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1259 {
1260 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1261
1262 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1263 }
1264
1265 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1266 {
1267 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1268
1269 chip->ichd[ICHD_MIC2].substream = NULL;
1270 return 0;
1271 }
1272
1273 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1274 {
1275 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1276
1277 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1278 }
1279
1280 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1281 {
1282 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1283
1284 chip->ichd[ICHD_PCM2IN].substream = NULL;
1285 return 0;
1286 }
1287
1288 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1289 {
1290 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1291 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1292
1293 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1294 }
1295
1296 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1297 {
1298 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1299 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1300
1301 chip->ichd[idx].substream = NULL;
1302 return 0;
1303 }
1304
1305 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1306 {
1307 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1308 unsigned int val;
1309
1310 spin_lock_irq(&chip->reg_lock);
1311 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1312 val |= ICH_ALI_IF_AC97SP;
1313 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1314 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1315 spin_unlock_irq(&chip->reg_lock);
1316
1317 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1318 }
1319
1320 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1321 {
1322 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1323 unsigned int val;
1324
1325 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1326 spin_lock_irq(&chip->reg_lock);
1327 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1328 val &= ~ICH_ALI_IF_AC97SP;
1329 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1330 spin_unlock_irq(&chip->reg_lock);
1331
1332 return 0;
1333 }
1334
1335 #if 0 // NYI
1336 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1337 {
1338 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1339
1340 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1341 }
1342
1343 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1344 {
1345 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1346
1347 chip->ichd[ALID_SPDIFIN].substream = NULL;
1348 return 0;
1349 }
1350
1351 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1352 {
1353 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1354
1355 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1356 }
1357
1358 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1359 {
1360 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1361
1362 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1363 return 0;
1364 }
1365 #endif
1366
1367 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1368 .open = snd_intel8x0_playback_open,
1369 .close = snd_intel8x0_playback_close,
1370 .ioctl = snd_pcm_lib_ioctl,
1371 .hw_params = snd_intel8x0_hw_params,
1372 .hw_free = snd_intel8x0_hw_free,
1373 .prepare = snd_intel8x0_pcm_prepare,
1374 .trigger = snd_intel8x0_pcm_trigger,
1375 .pointer = snd_intel8x0_pcm_pointer,
1376 };
1377
1378 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1379 .open = snd_intel8x0_capture_open,
1380 .close = snd_intel8x0_capture_close,
1381 .ioctl = snd_pcm_lib_ioctl,
1382 .hw_params = snd_intel8x0_hw_params,
1383 .hw_free = snd_intel8x0_hw_free,
1384 .prepare = snd_intel8x0_pcm_prepare,
1385 .trigger = snd_intel8x0_pcm_trigger,
1386 .pointer = snd_intel8x0_pcm_pointer,
1387 };
1388
1389 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1390 .open = snd_intel8x0_mic_open,
1391 .close = snd_intel8x0_mic_close,
1392 .ioctl = snd_pcm_lib_ioctl,
1393 .hw_params = snd_intel8x0_hw_params,
1394 .hw_free = snd_intel8x0_hw_free,
1395 .prepare = snd_intel8x0_pcm_prepare,
1396 .trigger = snd_intel8x0_pcm_trigger,
1397 .pointer = snd_intel8x0_pcm_pointer,
1398 };
1399
1400 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1401 .open = snd_intel8x0_mic2_open,
1402 .close = snd_intel8x0_mic2_close,
1403 .ioctl = snd_pcm_lib_ioctl,
1404 .hw_params = snd_intel8x0_hw_params,
1405 .hw_free = snd_intel8x0_hw_free,
1406 .prepare = snd_intel8x0_pcm_prepare,
1407 .trigger = snd_intel8x0_pcm_trigger,
1408 .pointer = snd_intel8x0_pcm_pointer,
1409 };
1410
1411 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1412 .open = snd_intel8x0_capture2_open,
1413 .close = snd_intel8x0_capture2_close,
1414 .ioctl = snd_pcm_lib_ioctl,
1415 .hw_params = snd_intel8x0_hw_params,
1416 .hw_free = snd_intel8x0_hw_free,
1417 .prepare = snd_intel8x0_pcm_prepare,
1418 .trigger = snd_intel8x0_pcm_trigger,
1419 .pointer = snd_intel8x0_pcm_pointer,
1420 };
1421
1422 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1423 .open = snd_intel8x0_spdif_open,
1424 .close = snd_intel8x0_spdif_close,
1425 .ioctl = snd_pcm_lib_ioctl,
1426 .hw_params = snd_intel8x0_hw_params,
1427 .hw_free = snd_intel8x0_hw_free,
1428 .prepare = snd_intel8x0_pcm_prepare,
1429 .trigger = snd_intel8x0_pcm_trigger,
1430 .pointer = snd_intel8x0_pcm_pointer,
1431 };
1432
1433 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1434 .open = snd_intel8x0_playback_open,
1435 .close = snd_intel8x0_playback_close,
1436 .ioctl = snd_pcm_lib_ioctl,
1437 .hw_params = snd_intel8x0_hw_params,
1438 .hw_free = snd_intel8x0_hw_free,
1439 .prepare = snd_intel8x0_pcm_prepare,
1440 .trigger = snd_intel8x0_ali_trigger,
1441 .pointer = snd_intel8x0_pcm_pointer,
1442 };
1443
1444 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1445 .open = snd_intel8x0_capture_open,
1446 .close = snd_intel8x0_capture_close,
1447 .ioctl = snd_pcm_lib_ioctl,
1448 .hw_params = snd_intel8x0_hw_params,
1449 .hw_free = snd_intel8x0_hw_free,
1450 .prepare = snd_intel8x0_pcm_prepare,
1451 .trigger = snd_intel8x0_ali_trigger,
1452 .pointer = snd_intel8x0_pcm_pointer,
1453 };
1454
1455 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1456 .open = snd_intel8x0_mic_open,
1457 .close = snd_intel8x0_mic_close,
1458 .ioctl = snd_pcm_lib_ioctl,
1459 .hw_params = snd_intel8x0_hw_params,
1460 .hw_free = snd_intel8x0_hw_free,
1461 .prepare = snd_intel8x0_pcm_prepare,
1462 .trigger = snd_intel8x0_ali_trigger,
1463 .pointer = snd_intel8x0_pcm_pointer,
1464 };
1465
1466 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1467 .open = snd_intel8x0_ali_ac97spdifout_open,
1468 .close = snd_intel8x0_ali_ac97spdifout_close,
1469 .ioctl = snd_pcm_lib_ioctl,
1470 .hw_params = snd_intel8x0_hw_params,
1471 .hw_free = snd_intel8x0_hw_free,
1472 .prepare = snd_intel8x0_pcm_prepare,
1473 .trigger = snd_intel8x0_ali_trigger,
1474 .pointer = snd_intel8x0_pcm_pointer,
1475 };
1476
1477 #if 0 // NYI
1478 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1479 .open = snd_intel8x0_ali_spdifin_open,
1480 .close = snd_intel8x0_ali_spdifin_close,
1481 .ioctl = snd_pcm_lib_ioctl,
1482 .hw_params = snd_intel8x0_hw_params,
1483 .hw_free = snd_intel8x0_hw_free,
1484 .prepare = snd_intel8x0_pcm_prepare,
1485 .trigger = snd_intel8x0_pcm_trigger,
1486 .pointer = snd_intel8x0_pcm_pointer,
1487 };
1488
1489 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1490 .open = snd_intel8x0_ali_spdifout_open,
1491 .close = snd_intel8x0_ali_spdifout_close,
1492 .ioctl = snd_pcm_lib_ioctl,
1493 .hw_params = snd_intel8x0_hw_params,
1494 .hw_free = snd_intel8x0_hw_free,
1495 .prepare = snd_intel8x0_pcm_prepare,
1496 .trigger = snd_intel8x0_pcm_trigger,
1497 .pointer = snd_intel8x0_pcm_pointer,
1498 };
1499 #endif // NYI
1500
1501 struct ich_pcm_table {
1502 char *suffix;
1503 struct snd_pcm_ops *playback_ops;
1504 struct snd_pcm_ops *capture_ops;
1505 size_t prealloc_size;
1506 size_t prealloc_max_size;
1507 int ac97_idx;
1508 };
1509
1510 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1511 struct ich_pcm_table *rec)
1512 {
1513 struct snd_pcm *pcm;
1514 int err;
1515 char name[32];
1516
1517 if (rec->suffix)
1518 sprintf(name, "Intel ICH - %s", rec->suffix);
1519 else
1520 strcpy(name, "Intel ICH");
1521 err = snd_pcm_new(chip->card, name, device,
1522 rec->playback_ops ? 1 : 0,
1523 rec->capture_ops ? 1 : 0, &pcm);
1524 if (err < 0)
1525 return err;
1526
1527 if (rec->playback_ops)
1528 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1529 if (rec->capture_ops)
1530 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1531
1532 pcm->private_data = chip;
1533 pcm->info_flags = 0;
1534 if (rec->suffix)
1535 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1536 else
1537 strcpy(pcm->name, chip->card->shortname);
1538 chip->pcm[device] = pcm;
1539
1540 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1541 snd_dma_pci_data(chip->pci),
1542 rec->prealloc_size, rec->prealloc_max_size);
1543
1544 if (rec->playback_ops &&
1545 rec->playback_ops->open == snd_intel8x0_playback_open) {
1546 struct snd_pcm_chmap *chmap;
1547 int chs = 2;
1548 if (chip->multi8)
1549 chs = 8;
1550 else if (chip->multi6)
1551 chs = 6;
1552 else if (chip->multi4)
1553 chs = 4;
1554 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1555 snd_pcm_alt_chmaps, chs, 0,
1556 &chmap);
1557 if (err < 0)
1558 return err;
1559 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1560 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1561 }
1562
1563 return 0;
1564 }
1565
1566 static struct ich_pcm_table intel_pcms[] = {
1567 {
1568 .playback_ops = &snd_intel8x0_playback_ops,
1569 .capture_ops = &snd_intel8x0_capture_ops,
1570 .prealloc_size = 64 * 1024,
1571 .prealloc_max_size = 128 * 1024,
1572 },
1573 {
1574 .suffix = "MIC ADC",
1575 .capture_ops = &snd_intel8x0_capture_mic_ops,
1576 .prealloc_size = 0,
1577 .prealloc_max_size = 128 * 1024,
1578 .ac97_idx = ICHD_MIC,
1579 },
1580 {
1581 .suffix = "MIC2 ADC",
1582 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1583 .prealloc_size = 0,
1584 .prealloc_max_size = 128 * 1024,
1585 .ac97_idx = ICHD_MIC2,
1586 },
1587 {
1588 .suffix = "ADC2",
1589 .capture_ops = &snd_intel8x0_capture2_ops,
1590 .prealloc_size = 0,
1591 .prealloc_max_size = 128 * 1024,
1592 .ac97_idx = ICHD_PCM2IN,
1593 },
1594 {
1595 .suffix = "IEC958",
1596 .playback_ops = &snd_intel8x0_spdif_ops,
1597 .prealloc_size = 64 * 1024,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ICHD_SPBAR,
1600 },
1601 };
1602
1603 static struct ich_pcm_table nforce_pcms[] = {
1604 {
1605 .playback_ops = &snd_intel8x0_playback_ops,
1606 .capture_ops = &snd_intel8x0_capture_ops,
1607 .prealloc_size = 64 * 1024,
1608 .prealloc_max_size = 128 * 1024,
1609 },
1610 {
1611 .suffix = "MIC ADC",
1612 .capture_ops = &snd_intel8x0_capture_mic_ops,
1613 .prealloc_size = 0,
1614 .prealloc_max_size = 128 * 1024,
1615 .ac97_idx = NVD_MIC,
1616 },
1617 {
1618 .suffix = "IEC958",
1619 .playback_ops = &snd_intel8x0_spdif_ops,
1620 .prealloc_size = 64 * 1024,
1621 .prealloc_max_size = 128 * 1024,
1622 .ac97_idx = NVD_SPBAR,
1623 },
1624 };
1625
1626 static struct ich_pcm_table ali_pcms[] = {
1627 {
1628 .playback_ops = &snd_intel8x0_ali_playback_ops,
1629 .capture_ops = &snd_intel8x0_ali_capture_ops,
1630 .prealloc_size = 64 * 1024,
1631 .prealloc_max_size = 128 * 1024,
1632 },
1633 {
1634 .suffix = "MIC ADC",
1635 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1636 .prealloc_size = 0,
1637 .prealloc_max_size = 128 * 1024,
1638 .ac97_idx = ALID_MIC,
1639 },
1640 {
1641 .suffix = "IEC958",
1642 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1643 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1644 .prealloc_size = 64 * 1024,
1645 .prealloc_max_size = 128 * 1024,
1646 .ac97_idx = ALID_AC97SPDIFOUT,
1647 },
1648 #if 0 // NYI
1649 {
1650 .suffix = "HW IEC958",
1651 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1652 .prealloc_size = 64 * 1024,
1653 .prealloc_max_size = 128 * 1024,
1654 },
1655 #endif
1656 };
1657
1658 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1659 {
1660 int i, tblsize, device, err;
1661 struct ich_pcm_table *tbl, *rec;
1662
1663 switch (chip->device_type) {
1664 case DEVICE_INTEL_ICH4:
1665 tbl = intel_pcms;
1666 tblsize = ARRAY_SIZE(intel_pcms);
1667 if (spdif_aclink)
1668 tblsize--;
1669 break;
1670 case DEVICE_NFORCE:
1671 tbl = nforce_pcms;
1672 tblsize = ARRAY_SIZE(nforce_pcms);
1673 if (spdif_aclink)
1674 tblsize--;
1675 break;
1676 case DEVICE_ALI:
1677 tbl = ali_pcms;
1678 tblsize = ARRAY_SIZE(ali_pcms);
1679 break;
1680 default:
1681 tbl = intel_pcms;
1682 tblsize = 2;
1683 break;
1684 }
1685
1686 device = 0;
1687 for (i = 0; i < tblsize; i++) {
1688 rec = tbl + i;
1689 if (i > 0 && rec->ac97_idx) {
1690 /* activate PCM only when associated AC'97 codec */
1691 if (! chip->ichd[rec->ac97_idx].pcm)
1692 continue;
1693 }
1694 err = snd_intel8x0_pcm1(chip, device, rec);
1695 if (err < 0)
1696 return err;
1697 device++;
1698 }
1699
1700 chip->pcm_devs = device;
1701 return 0;
1702 }
1703
1704
1705 /*
1706 * Mixer part
1707 */
1708
1709 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1710 {
1711 struct intel8x0 *chip = bus->private_data;
1712 chip->ac97_bus = NULL;
1713 }
1714
1715 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1716 {
1717 struct intel8x0 *chip = ac97->private_data;
1718 chip->ac97[ac97->num] = NULL;
1719 }
1720
1721 static struct ac97_pcm ac97_pcm_defs[] = {
1722 /* front PCM */
1723 {
1724 .exclusive = 1,
1725 .r = { {
1726 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1727 (1 << AC97_SLOT_PCM_RIGHT) |
1728 (1 << AC97_SLOT_PCM_CENTER) |
1729 (1 << AC97_SLOT_PCM_SLEFT) |
1730 (1 << AC97_SLOT_PCM_SRIGHT) |
1731 (1 << AC97_SLOT_LFE)
1732 },
1733 {
1734 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1735 (1 << AC97_SLOT_PCM_RIGHT) |
1736 (1 << AC97_SLOT_PCM_LEFT_0) |
1737 (1 << AC97_SLOT_PCM_RIGHT_0)
1738 }
1739 }
1740 },
1741 /* PCM IN #1 */
1742 {
1743 .stream = 1,
1744 .exclusive = 1,
1745 .r = { {
1746 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1747 (1 << AC97_SLOT_PCM_RIGHT)
1748 }
1749 }
1750 },
1751 /* MIC IN #1 */
1752 {
1753 .stream = 1,
1754 .exclusive = 1,
1755 .r = { {
1756 .slots = (1 << AC97_SLOT_MIC)
1757 }
1758 }
1759 },
1760 /* S/PDIF PCM */
1761 {
1762 .exclusive = 1,
1763 .spdif = 1,
1764 .r = { {
1765 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1766 (1 << AC97_SLOT_SPDIF_RIGHT2)
1767 }
1768 }
1769 },
1770 /* PCM IN #2 */
1771 {
1772 .stream = 1,
1773 .exclusive = 1,
1774 .r = { {
1775 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1776 (1 << AC97_SLOT_PCM_RIGHT)
1777 }
1778 }
1779 },
1780 /* MIC IN #2 */
1781 {
1782 .stream = 1,
1783 .exclusive = 1,
1784 .r = { {
1785 .slots = (1 << AC97_SLOT_MIC)
1786 }
1787 }
1788 },
1789 };
1790
1791 static struct ac97_quirk ac97_quirks[] = {
1792 {
1793 .subvendor = 0x0e11,
1794 .subdevice = 0x000e,
1795 .name = "Compaq Deskpro EN", /* AD1885 */
1796 .type = AC97_TUNE_HP_ONLY
1797 },
1798 {
1799 .subvendor = 0x0e11,
1800 .subdevice = 0x008a,
1801 .name = "Compaq Evo W4000", /* AD1885 */
1802 .type = AC97_TUNE_HP_ONLY
1803 },
1804 {
1805 .subvendor = 0x0e11,
1806 .subdevice = 0x00b8,
1807 .name = "Compaq Evo D510C",
1808 .type = AC97_TUNE_HP_ONLY
1809 },
1810 {
1811 .subvendor = 0x0e11,
1812 .subdevice = 0x0860,
1813 .name = "HP/Compaq nx7010",
1814 .type = AC97_TUNE_MUTE_LED
1815 },
1816 {
1817 .subvendor = 0x1014,
1818 .subdevice = 0x0534,
1819 .name = "ThinkPad X31",
1820 .type = AC97_TUNE_INV_EAPD
1821 },
1822 {
1823 .subvendor = 0x1014,
1824 .subdevice = 0x1f00,
1825 .name = "MS-9128",
1826 .type = AC97_TUNE_ALC_JACK
1827 },
1828 {
1829 .subvendor = 0x1014,
1830 .subdevice = 0x0267,
1831 .name = "IBM NetVista A30p", /* AD1981B */
1832 .type = AC97_TUNE_HP_ONLY
1833 },
1834 {
1835 .subvendor = 0x1025,
1836 .subdevice = 0x0082,
1837 .name = "Acer Travelmate 2310",
1838 .type = AC97_TUNE_HP_ONLY
1839 },
1840 {
1841 .subvendor = 0x1025,
1842 .subdevice = 0x0083,
1843 .name = "Acer Aspire 3003LCi",
1844 .type = AC97_TUNE_HP_ONLY
1845 },
1846 {
1847 .subvendor = 0x1028,
1848 .subdevice = 0x00d8,
1849 .name = "Dell Precision 530", /* AD1885 */
1850 .type = AC97_TUNE_HP_ONLY
1851 },
1852 {
1853 .subvendor = 0x1028,
1854 .subdevice = 0x010d,
1855 .name = "Dell", /* which model? AD1885 */
1856 .type = AC97_TUNE_HP_ONLY
1857 },
1858 {
1859 .subvendor = 0x1028,
1860 .subdevice = 0x0126,
1861 .name = "Dell Optiplex GX260", /* AD1981A */
1862 .type = AC97_TUNE_HP_ONLY
1863 },
1864 {
1865 .subvendor = 0x1028,
1866 .subdevice = 0x012c,
1867 .name = "Dell Precision 650", /* AD1981A */
1868 .type = AC97_TUNE_HP_ONLY
1869 },
1870 {
1871 .subvendor = 0x1028,
1872 .subdevice = 0x012d,
1873 .name = "Dell Precision 450", /* AD1981B*/
1874 .type = AC97_TUNE_HP_ONLY
1875 },
1876 {
1877 .subvendor = 0x1028,
1878 .subdevice = 0x0147,
1879 .name = "Dell", /* which model? AD1981B*/
1880 .type = AC97_TUNE_HP_ONLY
1881 },
1882 {
1883 .subvendor = 0x1028,
1884 .subdevice = 0x0151,
1885 .name = "Dell Optiplex GX270", /* AD1981B */
1886 .type = AC97_TUNE_HP_ONLY
1887 },
1888 {
1889 .subvendor = 0x1028,
1890 .subdevice = 0x014e,
1891 .name = "Dell D800", /* STAC9750/51 */
1892 .type = AC97_TUNE_HP_ONLY
1893 },
1894 {
1895 .subvendor = 0x1028,
1896 .subdevice = 0x0163,
1897 .name = "Dell Unknown", /* STAC9750/51 */
1898 .type = AC97_TUNE_HP_ONLY
1899 },
1900 {
1901 .subvendor = 0x1028,
1902 .subdevice = 0x016a,
1903 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1904 .type = AC97_TUNE_HP_ONLY
1905 },
1906 {
1907 .subvendor = 0x1028,
1908 .subdevice = 0x0182,
1909 .name = "Dell Latitude D610", /* STAC9750/51 */
1910 .type = AC97_TUNE_HP_ONLY
1911 },
1912 {
1913 .subvendor = 0x1028,
1914 .subdevice = 0x0186,
1915 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1916 .type = AC97_TUNE_HP_MUTE_LED
1917 },
1918 {
1919 .subvendor = 0x1028,
1920 .subdevice = 0x0188,
1921 .name = "Dell Inspiron 6000",
1922 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1923 },
1924 {
1925 .subvendor = 0x1028,
1926 .subdevice = 0x0189,
1927 .name = "Dell Inspiron 9300",
1928 .type = AC97_TUNE_HP_MUTE_LED
1929 },
1930 {
1931 .subvendor = 0x1028,
1932 .subdevice = 0x0191,
1933 .name = "Dell Inspiron 8600",
1934 .type = AC97_TUNE_HP_ONLY
1935 },
1936 {
1937 .subvendor = 0x103c,
1938 .subdevice = 0x006d,
1939 .name = "HP zv5000",
1940 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1941 },
1942 { /* FIXME: which codec? */
1943 .subvendor = 0x103c,
1944 .subdevice = 0x00c3,
1945 .name = "HP xw6000",
1946 .type = AC97_TUNE_HP_ONLY
1947 },
1948 {
1949 .subvendor = 0x103c,
1950 .subdevice = 0x088c,
1951 .name = "HP nc8000",
1952 .type = AC97_TUNE_HP_MUTE_LED
1953 },
1954 {
1955 .subvendor = 0x103c,
1956 .subdevice = 0x0890,
1957 .name = "HP nc6000",
1958 .type = AC97_TUNE_MUTE_LED
1959 },
1960 {
1961 .subvendor = 0x103c,
1962 .subdevice = 0x129d,
1963 .name = "HP xw8000",
1964 .type = AC97_TUNE_HP_ONLY
1965 },
1966 {
1967 .subvendor = 0x103c,
1968 .subdevice = 0x0938,
1969 .name = "HP nc4200",
1970 .type = AC97_TUNE_HP_MUTE_LED
1971 },
1972 {
1973 .subvendor = 0x103c,
1974 .subdevice = 0x099c,
1975 .name = "HP nx6110/nc6120",
1976 .type = AC97_TUNE_HP_MUTE_LED
1977 },
1978 {
1979 .subvendor = 0x103c,
1980 .subdevice = 0x0944,
1981 .name = "HP nc6220",
1982 .type = AC97_TUNE_HP_MUTE_LED
1983 },
1984 {
1985 .subvendor = 0x103c,
1986 .subdevice = 0x0934,
1987 .name = "HP nc8220",
1988 .type = AC97_TUNE_HP_MUTE_LED
1989 },
1990 {
1991 .subvendor = 0x103c,
1992 .subdevice = 0x12f1,
1993 .name = "HP xw8200", /* AD1981B*/
1994 .type = AC97_TUNE_HP_ONLY
1995 },
1996 {
1997 .subvendor = 0x103c,
1998 .subdevice = 0x12f2,
1999 .name = "HP xw6200",
2000 .type = AC97_TUNE_HP_ONLY
2001 },
2002 {
2003 .subvendor = 0x103c,
2004 .subdevice = 0x3008,
2005 .name = "HP xw4200", /* AD1981B*/
2006 .type = AC97_TUNE_HP_ONLY
2007 },
2008 {
2009 .subvendor = 0x104d,
2010 .subdevice = 0x8144,
2011 .name = "Sony",
2012 .type = AC97_TUNE_INV_EAPD
2013 },
2014 {
2015 .subvendor = 0x104d,
2016 .subdevice = 0x8197,
2017 .name = "Sony S1XP",
2018 .type = AC97_TUNE_INV_EAPD
2019 },
2020 {
2021 .subvendor = 0x104d,
2022 .subdevice = 0x81c0,
2023 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2024 .type = AC97_TUNE_INV_EAPD
2025 },
2026 {
2027 .subvendor = 0x104d,
2028 .subdevice = 0x81c5,
2029 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2030 .type = AC97_TUNE_INV_EAPD
2031 },
2032 {
2033 .subvendor = 0x1043,
2034 .subdevice = 0x80f3,
2035 .name = "ASUS ICH5/AD1985",
2036 .type = AC97_TUNE_AD_SHARING
2037 },
2038 {
2039 .subvendor = 0x10cf,
2040 .subdevice = 0x11c3,
2041 .name = "Fujitsu-Siemens E4010",
2042 .type = AC97_TUNE_HP_ONLY
2043 },
2044 {
2045 .subvendor = 0x10cf,
2046 .subdevice = 0x1225,
2047 .name = "Fujitsu-Siemens T3010",
2048 .type = AC97_TUNE_HP_ONLY
2049 },
2050 {
2051 .subvendor = 0x10cf,
2052 .subdevice = 0x1253,
2053 .name = "Fujitsu S6210", /* STAC9750/51 */
2054 .type = AC97_TUNE_HP_ONLY
2055 },
2056 {
2057 .subvendor = 0x10cf,
2058 .subdevice = 0x127d,
2059 .name = "Fujitsu Lifebook P7010",
2060 .type = AC97_TUNE_HP_ONLY
2061 },
2062 {
2063 .subvendor = 0x10cf,
2064 .subdevice = 0x127e,
2065 .name = "Fujitsu Lifebook C1211D",
2066 .type = AC97_TUNE_HP_ONLY
2067 },
2068 {
2069 .subvendor = 0x10cf,
2070 .subdevice = 0x12ec,
2071 .name = "Fujitsu-Siemens 4010",
2072 .type = AC97_TUNE_HP_ONLY
2073 },
2074 {
2075 .subvendor = 0x10cf,
2076 .subdevice = 0x12f2,
2077 .name = "Fujitsu-Siemens Celsius H320",
2078 .type = AC97_TUNE_SWAP_HP
2079 },
2080 {
2081 .subvendor = 0x10f1,
2082 .subdevice = 0x2665,
2083 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2084 .type = AC97_TUNE_HP_ONLY
2085 },
2086 {
2087 .subvendor = 0x10f1,
2088 .subdevice = 0x2885,
2089 .name = "AMD64 Mobo", /* ALC650 */
2090 .type = AC97_TUNE_HP_ONLY
2091 },
2092 {
2093 .subvendor = 0x10f1,
2094 .subdevice = 0x2895,
2095 .name = "Tyan Thunder K8WE",
2096 .type = AC97_TUNE_HP_ONLY
2097 },
2098 {
2099 .subvendor = 0x10f7,
2100 .subdevice = 0x834c,
2101 .name = "Panasonic CF-R4",
2102 .type = AC97_TUNE_HP_ONLY,
2103 },
2104 {
2105 .subvendor = 0x110a,
2106 .subdevice = 0x0056,
2107 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2108 .type = AC97_TUNE_HP_ONLY
2109 },
2110 {
2111 .subvendor = 0x11d4,
2112 .subdevice = 0x5375,
2113 .name = "ADI AD1985 (discrete)",
2114 .type = AC97_TUNE_HP_ONLY
2115 },
2116 {
2117 .subvendor = 0x1462,
2118 .subdevice = 0x5470,
2119 .name = "MSI P4 ATX 645 Ultra",
2120 .type = AC97_TUNE_HP_ONLY
2121 },
2122 {
2123 .subvendor = 0x161f,
2124 .subdevice = 0x202f,
2125 .name = "Gateway M520",
2126 .type = AC97_TUNE_INV_EAPD
2127 },
2128 {
2129 .subvendor = 0x161f,
2130 .subdevice = 0x203a,
2131 .name = "Gateway 4525GZ", /* AD1981B */
2132 .type = AC97_TUNE_INV_EAPD
2133 },
2134 {
2135 .subvendor = 0x1734,
2136 .subdevice = 0x0088,
2137 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2138 .type = AC97_TUNE_HP_ONLY
2139 },
2140 {
2141 .subvendor = 0x8086,
2142 .subdevice = 0x2000,
2143 .mask = 0xfff0,
2144 .name = "Intel ICH5/AD1985",
2145 .type = AC97_TUNE_AD_SHARING
2146 },
2147 {
2148 .subvendor = 0x8086,
2149 .subdevice = 0x4000,
2150 .mask = 0xfff0,
2151 .name = "Intel ICH5/AD1985",
2152 .type = AC97_TUNE_AD_SHARING
2153 },
2154 {
2155 .subvendor = 0x8086,
2156 .subdevice = 0x4856,
2157 .name = "Intel D845WN (82801BA)",
2158 .type = AC97_TUNE_SWAP_HP
2159 },
2160 {
2161 .subvendor = 0x8086,
2162 .subdevice = 0x4d44,
2163 .name = "Intel D850EMV2", /* AD1885 */
2164 .type = AC97_TUNE_HP_ONLY
2165 },
2166 {
2167 .subvendor = 0x8086,
2168 .subdevice = 0x4d56,
2169 .name = "Intel ICH/AD1885",
2170 .type = AC97_TUNE_HP_ONLY
2171 },
2172 {
2173 .subvendor = 0x8086,
2174 .subdevice = 0x6000,
2175 .mask = 0xfff0,
2176 .name = "Intel ICH5/AD1985",
2177 .type = AC97_TUNE_AD_SHARING
2178 },
2179 {
2180 .subvendor = 0x8086,
2181 .subdevice = 0xe000,
2182 .mask = 0xfff0,
2183 .name = "Intel ICH5/AD1985",
2184 .type = AC97_TUNE_AD_SHARING
2185 },
2186 #if 0 /* FIXME: this seems wrong on most boards */
2187 {
2188 .subvendor = 0x8086,
2189 .subdevice = 0xa000,
2190 .mask = 0xfff0,
2191 .name = "Intel ICH5/AD1985",
2192 .type = AC97_TUNE_HP_ONLY
2193 },
2194 #endif
2195 { } /* terminator */
2196 };
2197
2198 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2199 const char *quirk_override)
2200 {
2201 struct snd_ac97_bus *pbus;
2202 struct snd_ac97_template ac97;
2203 int err;
2204 unsigned int i, codecs;
2205 unsigned int glob_sta = 0;
2206 struct snd_ac97_bus_ops *ops;
2207 static struct snd_ac97_bus_ops standard_bus_ops = {
2208 .write = snd_intel8x0_codec_write,
2209 .read = snd_intel8x0_codec_read,
2210 };
2211 static struct snd_ac97_bus_ops ali_bus_ops = {
2212 .write = snd_intel8x0_ali_codec_write,
2213 .read = snd_intel8x0_ali_codec_read,
2214 };
2215
2216 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2217 if (!spdif_aclink) {
2218 switch (chip->device_type) {
2219 case DEVICE_NFORCE:
2220 chip->spdif_idx = NVD_SPBAR;
2221 break;
2222 case DEVICE_ALI:
2223 chip->spdif_idx = ALID_AC97SPDIFOUT;
2224 break;
2225 case DEVICE_INTEL_ICH4:
2226 chip->spdif_idx = ICHD_SPBAR;
2227 break;
2228 }
2229 }
2230
2231 chip->in_ac97_init = 1;
2232
2233 memset(&ac97, 0, sizeof(ac97));
2234 ac97.private_data = chip;
2235 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2236 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2237 if (chip->xbox)
2238 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2239 if (chip->device_type != DEVICE_ALI) {
2240 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2241 ops = &standard_bus_ops;
2242 chip->in_sdin_init = 1;
2243 codecs = 0;
2244 for (i = 0; i < chip->max_codecs; i++) {
2245 if (! (glob_sta & chip->codec_bit[i]))
2246 continue;
2247 if (chip->device_type == DEVICE_INTEL_ICH4) {
2248 snd_intel8x0_codec_read_test(chip, codecs);
2249 chip->ac97_sdin[codecs] =
2250 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2251 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2252 chip->ac97_sdin[codecs] = 0;
2253 } else
2254 chip->ac97_sdin[codecs] = i;
2255 codecs++;
2256 }
2257 chip->in_sdin_init = 0;
2258 if (! codecs)
2259 codecs = 1;
2260 } else {
2261 ops = &ali_bus_ops;
2262 codecs = 1;
2263 /* detect the secondary codec */
2264 for (i = 0; i < 100; i++) {
2265 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2266 if (reg & 0x40) {
2267 codecs = 2;
2268 break;
2269 }
2270 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2271 udelay(1);
2272 }
2273 }
2274 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2275 goto __err;
2276 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2277 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2278 pbus->clock = ac97_clock;
2279 /* FIXME: my test board doesn't work well with VRA... */
2280 if (chip->device_type == DEVICE_ALI)
2281 pbus->no_vra = 1;
2282 else
2283 pbus->dra = 1;
2284 chip->ac97_bus = pbus;
2285 chip->ncodecs = codecs;
2286
2287 ac97.pci = chip->pci;
2288 for (i = 0; i < codecs; i++) {
2289 ac97.num = i;
2290 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2291 if (err != -EACCES)
2292 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2293 if (i == 0)
2294 goto __err;
2295 }
2296 }
2297 /* tune up the primary codec */
2298 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2299 /* enable separate SDINs for ICH4 */
2300 if (chip->device_type == DEVICE_INTEL_ICH4)
2301 pbus->isdin = 1;
2302 /* find the available PCM streams */
2303 i = ARRAY_SIZE(ac97_pcm_defs);
2304 if (chip->device_type != DEVICE_INTEL_ICH4)
2305 i -= 2; /* do not allocate PCM2IN and MIC2 */
2306 if (chip->spdif_idx < 0)
2307 i--; /* do not allocate S/PDIF */
2308 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2309 if (err < 0)
2310 goto __err;
2311 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2312 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2313 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2314 if (chip->spdif_idx >= 0)
2315 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2316 if (chip->device_type == DEVICE_INTEL_ICH4) {
2317 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2318 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2319 }
2320 /* enable separate SDINs for ICH4 */
2321 if (chip->device_type == DEVICE_INTEL_ICH4) {
2322 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2323 u8 tmp = igetbyte(chip, ICHREG(SDM));
2324 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2325 if (pcm) {
2326 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2327 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2328 for (i = 1; i < 4; i++) {
2329 if (pcm->r[0].codec[i]) {
2330 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2331 break;
2332 }
2333 }
2334 } else {
2335 tmp &= ~ICH_SE; /* steer disable */
2336 }
2337 iputbyte(chip, ICHREG(SDM), tmp);
2338 }
2339 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2340 chip->multi4 = 1;
2341 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2342 chip->multi6 = 1;
2343 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2344 chip->multi8 = 1;
2345 }
2346 }
2347 if (pbus->pcms[0].r[1].rslots[0]) {
2348 chip->dra = 1;
2349 }
2350 if (chip->device_type == DEVICE_INTEL_ICH4) {
2351 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2352 chip->smp20bit = 1;
2353 }
2354 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2355 /* 48kHz only */
2356 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2357 }
2358 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2359 /* use slot 10/11 for SPDIF */
2360 u32 val;
2361 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2362 val |= ICH_PCM_SPDIF_1011;
2363 iputdword(chip, ICHREG(GLOB_CNT), val);
2364 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2365 }
2366 chip->in_ac97_init = 0;
2367 return 0;
2368
2369 __err:
2370 /* clear the cold-reset bit for the next chance */
2371 if (chip->device_type != DEVICE_ALI)
2372 iputdword(chip, ICHREG(GLOB_CNT),
2373 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2374 return err;
2375 }
2376
2377
2378 /*
2379 *
2380 */
2381
2382 static void do_ali_reset(struct intel8x0 *chip)
2383 {
2384 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2385 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2386 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2387 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2388 iputdword(chip, ICHREG(ALI_INTERFACECR),
2389 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2390 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2391 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2392 }
2393
2394 #ifdef CONFIG_SND_AC97_POWER_SAVE
2395 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2396 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2397 { } /* end */
2398 };
2399
2400 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2401 {
2402 unsigned int cnt;
2403 /* ACLink on, 2 channels */
2404
2405 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2406 return -EIO;
2407
2408 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2409 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2410
2411 /* do cold reset - the full ac97 powerdown may leave the controller
2412 * in a warm state but actually it cannot communicate with the codec.
2413 */
2414 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2415 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2416 udelay(10);
2417 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2418 msleep(1);
2419 return 0;
2420 }
2421 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2422 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2423 #else
2424 #define snd_intel8x0_ich_chip_cold_reset(chip) 0
2425 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2426 #endif
2427
2428 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2429 {
2430 unsigned long end_time;
2431 unsigned int cnt;
2432 /* ACLink on, 2 channels */
2433 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2434 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2435 /* finish cold or do warm reset */
2436 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2437 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2438 end_time = (jiffies + (HZ / 4)) + 1;
2439 do {
2440 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2441 return 0;
2442 schedule_timeout_uninterruptible(1);
2443 } while (time_after_eq(end_time, jiffies));
2444 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2445 igetdword(chip, ICHREG(GLOB_CNT)));
2446 return -EIO;
2447 }
2448
2449 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2450 {
2451 unsigned long end_time;
2452 unsigned int status, nstatus;
2453 unsigned int cnt;
2454 int err;
2455
2456 /* put logic to right state */
2457 /* first clear status bits */
2458 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2459 if (chip->device_type == DEVICE_NFORCE)
2460 status |= ICH_NVSPINT;
2461 cnt = igetdword(chip, ICHREG(GLOB_STA));
2462 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2463
2464 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2465 err = snd_intel8x0_ich_chip_cold_reset(chip);
2466 else
2467 err = snd_intel8x0_ich_chip_reset(chip);
2468 if (err < 0)
2469 return err;
2470
2471 if (probing) {
2472 /* wait for any codec ready status.
2473 * Once it becomes ready it should remain ready
2474 * as long as we do not disable the ac97 link.
2475 */
2476 end_time = jiffies + HZ;
2477 do {
2478 status = igetdword(chip, ICHREG(GLOB_STA)) &
2479 chip->codec_isr_bits;
2480 if (status)
2481 break;
2482 schedule_timeout_uninterruptible(1);
2483 } while (time_after_eq(end_time, jiffies));
2484 if (! status) {
2485 /* no codec is found */
2486 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2487 igetdword(chip, ICHREG(GLOB_STA)));
2488 return -EIO;
2489 }
2490
2491 /* wait for other codecs ready status. */
2492 end_time = jiffies + HZ / 4;
2493 while (status != chip->codec_isr_bits &&
2494 time_after_eq(end_time, jiffies)) {
2495 schedule_timeout_uninterruptible(1);
2496 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2497 chip->codec_isr_bits;
2498 }
2499
2500 } else {
2501 /* resume phase */
2502 int i;
2503 status = 0;
2504 for (i = 0; i < chip->ncodecs; i++)
2505 if (chip->ac97[i])
2506 status |= chip->codec_bit[chip->ac97_sdin[i]];
2507 /* wait until all the probed codecs are ready */
2508 end_time = jiffies + HZ;
2509 do {
2510 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2511 chip->codec_isr_bits;
2512 if (status == nstatus)
2513 break;
2514 schedule_timeout_uninterruptible(1);
2515 } while (time_after_eq(end_time, jiffies));
2516 }
2517
2518 if (chip->device_type == DEVICE_SIS) {
2519 /* unmute the output on SIS7012 */
2520 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2521 }
2522 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2523 /* enable SPDIF interrupt */
2524 unsigned int val;
2525 pci_read_config_dword(chip->pci, 0x4c, &val);
2526 val |= 0x1000000;
2527 pci_write_config_dword(chip->pci, 0x4c, val);
2528 }
2529 return 0;
2530 }
2531
2532 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2533 {
2534 u32 reg;
2535 int i = 0;
2536
2537 reg = igetdword(chip, ICHREG(ALI_SCR));
2538 if ((reg & 2) == 0) /* Cold required */
2539 reg |= 2;
2540 else
2541 reg |= 1; /* Warm */
2542 reg &= ~0x80000000; /* ACLink on */
2543 iputdword(chip, ICHREG(ALI_SCR), reg);
2544
2545 for (i = 0; i < HZ / 2; i++) {
2546 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2547 goto __ok;
2548 schedule_timeout_uninterruptible(1);
2549 }
2550 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2551 if (probing)
2552 return -EIO;
2553
2554 __ok:
2555 for (i = 0; i < HZ / 2; i++) {
2556 reg = igetdword(chip, ICHREG(ALI_RTSR));
2557 if (reg & 0x80) /* primary codec */
2558 break;
2559 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2560 schedule_timeout_uninterruptible(1);
2561 }
2562
2563 do_ali_reset(chip);
2564 return 0;
2565 }
2566
2567 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2568 {
2569 unsigned int i, timeout;
2570 int err;
2571
2572 if (chip->device_type != DEVICE_ALI) {
2573 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2574 return err;
2575 iagetword(chip, 0); /* clear semaphore flag */
2576 } else {
2577 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2578 return err;
2579 }
2580
2581 /* disable interrupts */
2582 for (i = 0; i < chip->bdbars_count; i++)
2583 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2584 /* reset channels */
2585 for (i = 0; i < chip->bdbars_count; i++)
2586 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2587 for (i = 0; i < chip->bdbars_count; i++) {
2588 timeout = 100000;
2589 while (--timeout != 0) {
2590 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2591 break;
2592 }
2593 if (timeout == 0)
2594 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2595 }
2596 /* initialize Buffer Descriptor Lists */
2597 for (i = 0; i < chip->bdbars_count; i++)
2598 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2599 chip->ichd[i].bdbar_addr);
2600 return 0;
2601 }
2602
2603 static int snd_intel8x0_free(struct intel8x0 *chip)
2604 {
2605 unsigned int i;
2606
2607 if (chip->irq < 0)
2608 goto __hw_end;
2609 /* disable interrupts */
2610 for (i = 0; i < chip->bdbars_count; i++)
2611 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2612 /* reset channels */
2613 for (i = 0; i < chip->bdbars_count; i++)
2614 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2615 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2616 /* stop the spdif interrupt */
2617 unsigned int val;
2618 pci_read_config_dword(chip->pci, 0x4c, &val);
2619 val &= ~0x1000000;
2620 pci_write_config_dword(chip->pci, 0x4c, val);
2621 }
2622 /* --- */
2623
2624 __hw_end:
2625 if (chip->irq >= 0)
2626 free_irq(chip->irq, chip);
2627 if (chip->bdbars.area) {
2628 if (chip->fix_nocache)
2629 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2630 snd_dma_free_pages(&chip->bdbars);
2631 }
2632 if (chip->addr)
2633 pci_iounmap(chip->pci, chip->addr);
2634 if (chip->bmaddr)
2635 pci_iounmap(chip->pci, chip->bmaddr);
2636 pci_release_regions(chip->pci);
2637 pci_disable_device(chip->pci);
2638 kfree(chip);
2639 return 0;
2640 }
2641
2642 #ifdef CONFIG_PM_SLEEP
2643 /*
2644 * power management
2645 */
2646 static int intel8x0_suspend(struct device *dev)
2647 {
2648 struct pci_dev *pci = to_pci_dev(dev);
2649 struct snd_card *card = dev_get_drvdata(dev);
2650 struct intel8x0 *chip = card->private_data;
2651 int i;
2652
2653 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2654 for (i = 0; i < chip->pcm_devs; i++)
2655 snd_pcm_suspend_all(chip->pcm[i]);
2656 /* clear nocache */
2657 if (chip->fix_nocache) {
2658 for (i = 0; i < chip->bdbars_count; i++) {
2659 struct ichdev *ichdev = &chip->ichd[i];
2660 if (ichdev->substream && ichdev->page_attr_changed) {
2661 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2662 if (runtime->dma_area)
2663 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2664 }
2665 }
2666 }
2667 for (i = 0; i < chip->ncodecs; i++)
2668 snd_ac97_suspend(chip->ac97[i]);
2669 if (chip->device_type == DEVICE_INTEL_ICH4)
2670 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2671
2672 if (chip->irq >= 0) {
2673 free_irq(chip->irq, chip);
2674 chip->irq = -1;
2675 }
2676 pci_disable_device(pci);
2677 pci_save_state(pci);
2678 /* The call below may disable built-in speaker on some laptops
2679 * after S2RAM. So, don't touch it.
2680 */
2681 /* pci_set_power_state(pci, PCI_D3hot); */
2682 return 0;
2683 }
2684
2685 static int intel8x0_resume(struct device *dev)
2686 {
2687 struct pci_dev *pci = to_pci_dev(dev);
2688 struct snd_card *card = dev_get_drvdata(dev);
2689 struct intel8x0 *chip = card->private_data;
2690 int i;
2691
2692 pci_set_power_state(pci, PCI_D0);
2693 pci_restore_state(pci);
2694 if (pci_enable_device(pci) < 0) {
2695 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2696 "disabling device\n");
2697 snd_card_disconnect(card);
2698 return -EIO;
2699 }
2700 pci_set_master(pci);
2701 snd_intel8x0_chip_init(chip, 0);
2702 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2703 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2704 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2705 "disabling device\n", pci->irq);
2706 snd_card_disconnect(card);
2707 return -EIO;
2708 }
2709 chip->irq = pci->irq;
2710 synchronize_irq(chip->irq);
2711
2712 /* re-initialize mixer stuff */
2713 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2714 /* enable separate SDINs for ICH4 */
2715 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2716 /* use slot 10/11 for SPDIF */
2717 iputdword(chip, ICHREG(GLOB_CNT),
2718 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2719 ICH_PCM_SPDIF_1011);
2720 }
2721
2722 /* refill nocache */
2723 if (chip->fix_nocache)
2724 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2725
2726 for (i = 0; i < chip->ncodecs; i++)
2727 snd_ac97_resume(chip->ac97[i]);
2728
2729 /* refill nocache */
2730 if (chip->fix_nocache) {
2731 for (i = 0; i < chip->bdbars_count; i++) {
2732 struct ichdev *ichdev = &chip->ichd[i];
2733 if (ichdev->substream && ichdev->page_attr_changed) {
2734 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2735 if (runtime->dma_area)
2736 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2737 }
2738 }
2739 }
2740
2741 /* resume status */
2742 for (i = 0; i < chip->bdbars_count; i++) {
2743 struct ichdev *ichdev = &chip->ichd[i];
2744 unsigned long port = ichdev->reg_offset;
2745 if (! ichdev->substream || ! ichdev->suspended)
2746 continue;
2747 if (ichdev->ichd == ICHD_PCMOUT)
2748 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2749 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2750 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2751 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2752 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2753 }
2754
2755 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2756 return 0;
2757 }
2758
2759 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2760 #define INTEL8X0_PM_OPS &intel8x0_pm
2761 #else
2762 #define INTEL8X0_PM_OPS NULL
2763 #endif /* CONFIG_PM_SLEEP */
2764
2765 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2766
2767 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2768 {
2769 struct snd_pcm_substream *subs;
2770 struct ichdev *ichdev;
2771 unsigned long port;
2772 unsigned long pos, pos1, t;
2773 int civ, timeout = 1000, attempt = 1;
2774 struct timespec start_time, stop_time;
2775
2776 if (chip->ac97_bus->clock != 48000)
2777 return; /* specified in module option */
2778
2779 __again:
2780 subs = chip->pcm[0]->streams[0].substream;
2781 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2782 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2783 return;
2784 }
2785 ichdev = &chip->ichd[ICHD_PCMOUT];
2786 ichdev->physbuf = subs->dma_buffer.addr;
2787 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2788 ichdev->substream = NULL; /* don't process interrupts */
2789
2790 /* set rate */
2791 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2792 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2793 return;
2794 }
2795 snd_intel8x0_setup_periods(chip, ichdev);
2796 port = ichdev->reg_offset;
2797 spin_lock_irq(&chip->reg_lock);
2798 chip->in_measurement = 1;
2799 /* trigger */
2800 if (chip->device_type != DEVICE_ALI)
2801 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2802 else {
2803 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2804 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2805 }
2806 do_posix_clock_monotonic_gettime(&start_time);
2807 spin_unlock_irq(&chip->reg_lock);
2808 msleep(50);
2809 spin_lock_irq(&chip->reg_lock);
2810 /* check the position */
2811 do {
2812 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2813 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2814 if (pos1 == 0) {
2815 udelay(10);
2816 continue;
2817 }
2818 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2819 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2820 break;
2821 } while (timeout--);
2822 if (pos1 == 0) { /* oops, this value is not reliable */
2823 pos = 0;
2824 } else {
2825 pos = ichdev->fragsize1;
2826 pos -= pos1 << ichdev->pos_shift;
2827 pos += ichdev->position;
2828 }
2829 chip->in_measurement = 0;
2830 do_posix_clock_monotonic_gettime(&stop_time);
2831 /* stop */
2832 if (chip->device_type == DEVICE_ALI) {
2833 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2834 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2835 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2836 ;
2837 } else {
2838 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2839 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2840 ;
2841 }
2842 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2843 spin_unlock_irq(&chip->reg_lock);
2844
2845 if (pos == 0) {
2846 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2847 __retry:
2848 if (attempt < 3) {
2849 msleep(300);
2850 attempt++;
2851 goto __again;
2852 }
2853 goto __end;
2854 }
2855
2856 pos /= 4;
2857 t = stop_time.tv_sec - start_time.tv_sec;
2858 t *= 1000000;
2859 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2860 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2861 if (t == 0) {
2862 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2863 goto __retry;
2864 }
2865 pos *= 1000;
2866 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2867 if (pos < 40000 || pos >= 60000) {
2868 /* abnormal value. hw problem? */
2869 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2870 goto __retry;
2871 } else if (pos > 40500 && pos < 41500)
2872 /* first exception - 41000Hz reference clock */
2873 chip->ac97_bus->clock = 41000;
2874 else if (pos > 43600 && pos < 44600)
2875 /* second exception - 44100HZ reference clock */
2876 chip->ac97_bus->clock = 44100;
2877 else if (pos < 47500 || pos > 48500)
2878 /* not 48000Hz, tuning the clock.. */
2879 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2880 __end:
2881 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2882 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2883 }
2884
2885 static struct snd_pci_quirk intel8x0_clock_list[] = {
2886 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2887 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2888 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2889 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2890 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2891 { } /* terminator */
2892 };
2893
2894 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2895 {
2896 struct pci_dev *pci = chip->pci;
2897 const struct snd_pci_quirk *wl;
2898
2899 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2900 if (!wl)
2901 return 0;
2902 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2903 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2904 chip->ac97_bus->clock = wl->value;
2905 return 1;
2906 }
2907
2908 #ifdef CONFIG_PROC_FS
2909 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2910 struct snd_info_buffer *buffer)
2911 {
2912 struct intel8x0 *chip = entry->private_data;
2913 unsigned int tmp;
2914
2915 snd_iprintf(buffer, "Intel8x0\n\n");
2916 if (chip->device_type == DEVICE_ALI)
2917 return;
2918 tmp = igetdword(chip, ICHREG(GLOB_STA));
2919 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2920 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2921 if (chip->device_type == DEVICE_INTEL_ICH4)
2922 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2923 snd_iprintf(buffer, "AC'97 codecs ready :");
2924 if (tmp & chip->codec_isr_bits) {
2925 int i;
2926 static const char *codecs[3] = {
2927 "primary", "secondary", "tertiary"
2928 };
2929 for (i = 0; i < chip->max_codecs; i++)
2930 if (tmp & chip->codec_bit[i])
2931 snd_iprintf(buffer, " %s", codecs[i]);
2932 } else
2933 snd_iprintf(buffer, " none");
2934 snd_iprintf(buffer, "\n");
2935 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2936 chip->device_type == DEVICE_SIS)
2937 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2938 chip->ac97_sdin[0],
2939 chip->ac97_sdin[1],
2940 chip->ac97_sdin[2]);
2941 }
2942
2943 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2944 {
2945 struct snd_info_entry *entry;
2946
2947 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2948 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2949 }
2950 #else
2951 #define snd_intel8x0_proc_init(x)
2952 #endif
2953
2954 static int snd_intel8x0_dev_free(struct snd_device *device)
2955 {
2956 struct intel8x0 *chip = device->device_data;
2957 return snd_intel8x0_free(chip);
2958 }
2959
2960 struct ich_reg_info {
2961 unsigned int int_sta_mask;
2962 unsigned int offset;
2963 };
2964
2965 static unsigned int ich_codec_bits[3] = {
2966 ICH_PCR, ICH_SCR, ICH_TCR
2967 };
2968 static unsigned int sis_codec_bits[3] = {
2969 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2970 };
2971
2972 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2973 {
2974 int result = inside_vm;
2975 char *msg = NULL;
2976
2977 /* check module parameter first (override detection) */
2978 if (result >= 0) {
2979 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2980 goto fini;
2981 }
2982
2983 /* detect KVM and Parallels virtual environments */
2984 result = kvm_para_available();
2985 #ifdef X86_FEATURE_HYPERVISOR
2986 result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR);
2987 #endif
2988 if (!result)
2989 goto fini;
2990
2991 /* check for known (emulated) devices */
2992 if (pci->subsystem_vendor == 0x1af4 &&
2993 pci->subsystem_device == 0x1100) {
2994 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2995 msg = "enable KVM";
2996 } else if (pci->subsystem_vendor == 0x1ab8) {
2997 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2998 msg = "enable Parallels VM";
2999 } else {
3000 msg = "disable (unknown or VT-d) VM";
3001 result = 0;
3002 }
3003
3004 fini:
3005 if (msg != NULL)
3006 printk(KERN_INFO "intel8x0: %s optimization\n", msg);
3007
3008 return result;
3009 }
3010
3011 static int snd_intel8x0_create(struct snd_card *card,
3012 struct pci_dev *pci,
3013 unsigned long device_type,
3014 struct intel8x0 **r_intel8x0)
3015 {
3016 struct intel8x0 *chip;
3017 int err;
3018 unsigned int i;
3019 unsigned int int_sta_masks;
3020 struct ichdev *ichdev;
3021 static struct snd_device_ops ops = {
3022 .dev_free = snd_intel8x0_dev_free,
3023 };
3024
3025 static unsigned int bdbars[] = {
3026 3, /* DEVICE_INTEL */
3027 6, /* DEVICE_INTEL_ICH4 */
3028 3, /* DEVICE_SIS */
3029 6, /* DEVICE_ALI */
3030 4, /* DEVICE_NFORCE */
3031 };
3032 static struct ich_reg_info intel_regs[6] = {
3033 { ICH_PIINT, 0 },
3034 { ICH_POINT, 0x10 },
3035 { ICH_MCINT, 0x20 },
3036 { ICH_M2INT, 0x40 },
3037 { ICH_P2INT, 0x50 },
3038 { ICH_SPINT, 0x60 },
3039 };
3040 static struct ich_reg_info nforce_regs[4] = {
3041 { ICH_PIINT, 0 },
3042 { ICH_POINT, 0x10 },
3043 { ICH_MCINT, 0x20 },
3044 { ICH_NVSPINT, 0x70 },
3045 };
3046 static struct ich_reg_info ali_regs[6] = {
3047 { ALI_INT_PCMIN, 0x40 },
3048 { ALI_INT_PCMOUT, 0x50 },
3049 { ALI_INT_MICIN, 0x60 },
3050 { ALI_INT_CODECSPDIFOUT, 0x70 },
3051 { ALI_INT_SPDIFIN, 0xa0 },
3052 { ALI_INT_SPDIFOUT, 0xb0 },
3053 };
3054 struct ich_reg_info *tbl;
3055
3056 *r_intel8x0 = NULL;
3057
3058 if ((err = pci_enable_device(pci)) < 0)
3059 return err;
3060
3061 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3062 if (chip == NULL) {
3063 pci_disable_device(pci);
3064 return -ENOMEM;
3065 }
3066 spin_lock_init(&chip->reg_lock);
3067 chip->device_type = device_type;
3068 chip->card = card;
3069 chip->pci = pci;
3070 chip->irq = -1;
3071
3072 /* module parameters */
3073 chip->buggy_irq = buggy_irq;
3074 chip->buggy_semaphore = buggy_semaphore;
3075 if (xbox)
3076 chip->xbox = 1;
3077
3078 chip->inside_vm = snd_intel8x0_inside_vm(pci);
3079
3080 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3081 pci->device == PCI_DEVICE_ID_INTEL_440MX)
3082 chip->fix_nocache = 1; /* enable workaround */
3083
3084 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3085 kfree(chip);
3086 pci_disable_device(pci);
3087 return err;
3088 }
3089
3090 if (device_type == DEVICE_ALI) {
3091 /* ALI5455 has no ac97 region */
3092 chip->bmaddr = pci_iomap(pci, 0, 0);
3093 goto port_inited;
3094 }
3095
3096 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3097 chip->addr = pci_iomap(pci, 2, 0);
3098 else
3099 chip->addr = pci_iomap(pci, 0, 0);
3100 if (!chip->addr) {
3101 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
3102 snd_intel8x0_free(chip);
3103 return -EIO;
3104 }
3105 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3106 chip->bmaddr = pci_iomap(pci, 3, 0);
3107 else
3108 chip->bmaddr = pci_iomap(pci, 1, 0);
3109 if (!chip->bmaddr) {
3110 snd_printk(KERN_ERR "Controller space ioremap problem\n");
3111 snd_intel8x0_free(chip);
3112 return -EIO;
3113 }
3114
3115 port_inited:
3116 chip->bdbars_count = bdbars[device_type];
3117
3118 /* initialize offsets */
3119 switch (device_type) {
3120 case DEVICE_NFORCE:
3121 tbl = nforce_regs;
3122 break;
3123 case DEVICE_ALI:
3124 tbl = ali_regs;
3125 break;
3126 default:
3127 tbl = intel_regs;
3128 break;
3129 }
3130 for (i = 0; i < chip->bdbars_count; i++) {
3131 ichdev = &chip->ichd[i];
3132 ichdev->ichd = i;
3133 ichdev->reg_offset = tbl[i].offset;
3134 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3135 if (device_type == DEVICE_SIS) {
3136 /* SiS 7012 swaps the registers */
3137 ichdev->roff_sr = ICH_REG_OFF_PICB;
3138 ichdev->roff_picb = ICH_REG_OFF_SR;
3139 } else {
3140 ichdev->roff_sr = ICH_REG_OFF_SR;
3141 ichdev->roff_picb = ICH_REG_OFF_PICB;
3142 }
3143 if (device_type == DEVICE_ALI)
3144 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3145 /* SIS7012 handles the pcm data in bytes, others are in samples */
3146 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3147 }
3148
3149 /* allocate buffer descriptor lists */
3150 /* the start of each lists must be aligned to 8 bytes */
3151 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3152 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3153 &chip->bdbars) < 0) {
3154 snd_intel8x0_free(chip);
3155 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3156 return -ENOMEM;
3157 }
3158 /* tables must be aligned to 8 bytes here, but the kernel pages
3159 are much bigger, so we don't care (on i386) */
3160 /* workaround for 440MX */
3161 if (chip->fix_nocache)
3162 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3163 int_sta_masks = 0;
3164 for (i = 0; i < chip->bdbars_count; i++) {
3165 ichdev = &chip->ichd[i];
3166 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3167 (i * ICH_MAX_FRAGS * 2);
3168 ichdev->bdbar_addr = chip->bdbars.addr +
3169 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3170 int_sta_masks |= ichdev->int_sta_mask;
3171 }
3172 chip->int_sta_reg = device_type == DEVICE_ALI ?
3173 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3174 chip->int_sta_mask = int_sta_masks;
3175
3176 pci_set_master(pci);
3177
3178 switch(chip->device_type) {
3179 case DEVICE_INTEL_ICH4:
3180 /* ICH4 can have three codecs */
3181 chip->max_codecs = 3;
3182 chip->codec_bit = ich_codec_bits;
3183 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3184 break;
3185 case DEVICE_SIS:
3186 /* recent SIS7012 can have three codecs */
3187 chip->max_codecs = 3;
3188 chip->codec_bit = sis_codec_bits;
3189 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3190 break;
3191 default:
3192 /* others up to two codecs */
3193 chip->max_codecs = 2;
3194 chip->codec_bit = ich_codec_bits;
3195 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3196 break;
3197 }
3198 for (i = 0; i < chip->max_codecs; i++)
3199 chip->codec_isr_bits |= chip->codec_bit[i];
3200
3201 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3202 snd_intel8x0_free(chip);
3203 return err;
3204 }
3205
3206 /* request irq after initializaing int_sta_mask, etc */
3207 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3208 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3209 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3210 snd_intel8x0_free(chip);
3211 return -EBUSY;
3212 }
3213 chip->irq = pci->irq;
3214
3215 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3216 snd_intel8x0_free(chip);
3217 return err;
3218 }
3219
3220 snd_card_set_dev(card, &pci->dev);
3221
3222 *r_intel8x0 = chip;
3223 return 0;
3224 }
3225
3226 static struct shortname_table {
3227 unsigned int id;
3228 const char *s;
3229 } shortnames[] = {
3230 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3231 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3232 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3233 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3234 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3235 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3236 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3237 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3238 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3239 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3240 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3241 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3242 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3243 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3244 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3245 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3246 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3247 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3248 { 0x003a, "NVidia MCP04" },
3249 { 0x746d, "AMD AMD8111" },
3250 { 0x7445, "AMD AMD768" },
3251 { 0x5455, "ALi M5455" },
3252 { 0, NULL },
3253 };
3254
3255 static struct snd_pci_quirk spdif_aclink_defaults[] = {
3256 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3257 { } /* end */
3258 };
3259
3260 /* look up white/black list for SPDIF over ac-link */
3261 static int check_default_spdif_aclink(struct pci_dev *pci)
3262 {
3263 const struct snd_pci_quirk *w;
3264
3265 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3266 if (w) {
3267 if (w->value)
3268 snd_printdd(KERN_INFO
3269 "intel8x0: Using SPDIF over AC-Link for %s\n",
3270 snd_pci_quirk_name(w));
3271 else
3272 snd_printdd(KERN_INFO
3273 "intel8x0: Using integrated SPDIF DMA for %s\n",
3274 snd_pci_quirk_name(w));
3275 return w->value;
3276 }
3277 return 0;
3278 }
3279
3280 static int snd_intel8x0_probe(struct pci_dev *pci,
3281 const struct pci_device_id *pci_id)
3282 {
3283 struct snd_card *card;
3284 struct intel8x0 *chip;
3285 int err;
3286 struct shortname_table *name;
3287
3288 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3289 if (err < 0)
3290 return err;
3291
3292 if (spdif_aclink < 0)
3293 spdif_aclink = check_default_spdif_aclink(pci);
3294
3295 strcpy(card->driver, "ICH");
3296 if (!spdif_aclink) {
3297 switch (pci_id->driver_data) {
3298 case DEVICE_NFORCE:
3299 strcpy(card->driver, "NFORCE");
3300 break;
3301 case DEVICE_INTEL_ICH4:
3302 strcpy(card->driver, "ICH4");
3303 }
3304 }
3305
3306 strcpy(card->shortname, "Intel ICH");
3307 for (name = shortnames; name->id; name++) {
3308 if (pci->device == name->id) {
3309 strcpy(card->shortname, name->s);
3310 break;
3311 }
3312 }
3313
3314 if (buggy_irq < 0) {
3315 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3316 * Needs to return IRQ_HANDLED for unknown irqs.
3317 */
3318 if (pci_id->driver_data == DEVICE_NFORCE)
3319 buggy_irq = 1;
3320 else
3321 buggy_irq = 0;
3322 }
3323
3324 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3325 &chip)) < 0) {
3326 snd_card_free(card);
3327 return err;
3328 }
3329 card->private_data = chip;
3330
3331 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3332 snd_card_free(card);
3333 return err;
3334 }
3335 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3336 snd_card_free(card);
3337 return err;
3338 }
3339
3340 snd_intel8x0_proc_init(chip);
3341
3342 snprintf(card->longname, sizeof(card->longname),
3343 "%s with %s at irq %i", card->shortname,
3344 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3345
3346 if (ac97_clock == 0 || ac97_clock == 1) {
3347 if (ac97_clock == 0) {
3348 if (intel8x0_in_clock_list(chip) == 0)
3349 intel8x0_measure_ac97_clock(chip);
3350 } else {
3351 intel8x0_measure_ac97_clock(chip);
3352 }
3353 }
3354
3355 if ((err = snd_card_register(card)) < 0) {
3356 snd_card_free(card);
3357 return err;
3358 }
3359 pci_set_drvdata(pci, card);
3360 return 0;
3361 }
3362
3363 static void snd_intel8x0_remove(struct pci_dev *pci)
3364 {
3365 snd_card_free(pci_get_drvdata(pci));
3366 }
3367
3368 static struct pci_driver intel8x0_driver = {
3369 .name = KBUILD_MODNAME,
3370 .id_table = snd_intel8x0_ids,
3371 .probe = snd_intel8x0_probe,
3372 .remove = snd_intel8x0_remove,
3373 .driver = {
3374 .pm = INTEL8X0_PM_OPS,
3375 },
3376 };
3377
3378 module_pci_driver(intel8x0_driver);
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