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Linux-2.6.12-rc2
[mirror_ubuntu-artful-kernel.git] / sound / pci / intel8x0.c
1 /*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29 #include <sound/driver.h>
30 #include <asm/io.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/moduleparam.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/initval.h>
42 /* for 440MX workaround */
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
45
46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
62 "{AMD,AMD768},"
63 "{AMD,AMD8111},"
64 "{ALI,M5455}}");
65
66 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
67 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
68 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
69 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
70 static char *ac97_quirk[SNDRV_CARDS];
71 static int buggy_irq[SNDRV_CARDS];
72 static int xbox[SNDRV_CARDS];
73
74 #ifdef SUPPORT_MIDI
75 static int mpu_port[SNDRV_CARDS]; /* disabled */
76 #endif
77
78 module_param_array(index, int, NULL, 0444);
79 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
80 module_param_array(id, charp, NULL, 0444);
81 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
82 module_param_array(enable, bool, NULL, 0444);
83 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
84 module_param_array(ac97_clock, int, NULL, 0444);
85 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
86 module_param_array(ac97_quirk, charp, NULL, 0444);
87 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
88 module_param_array(buggy_irq, bool, NULL, 0444);
89 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
90 module_param_array(xbox, bool, NULL, 0444);
91 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
92
93 /*
94 * Direct registers
95 */
96
97 #ifndef PCI_DEVICE_ID_INTEL_82801
98 #define PCI_DEVICE_ID_INTEL_82801 0x2415
99 #endif
100 #ifndef PCI_DEVICE_ID_INTEL_82901
101 #define PCI_DEVICE_ID_INTEL_82901 0x2425
102 #endif
103 #ifndef PCI_DEVICE_ID_INTEL_82801BA
104 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445
105 #endif
106 #ifndef PCI_DEVICE_ID_INTEL_440MX
107 #define PCI_DEVICE_ID_INTEL_440MX 0x7195
108 #endif
109 #ifndef PCI_DEVICE_ID_INTEL_ICH3
110 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485
111 #endif
112 #ifndef PCI_DEVICE_ID_INTEL_ICH4
113 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
114 #endif
115 #ifndef PCI_DEVICE_ID_INTEL_ICH5
116 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
117 #endif
118 #ifndef PCI_DEVICE_ID_INTEL_ESB_5
119 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
120 #endif
121 #ifndef PCI_DEVICE_ID_INTEL_ICH6_18
122 #define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
123 #endif
124 #ifndef PCI_DEVICE_ID_INTEL_ICH7_20
125 #define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
126 #endif
127 #ifndef PCI_DEVICE_ID_SI_7012
128 #define PCI_DEVICE_ID_SI_7012 0x7012
129 #endif
130 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
131 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
132 #endif
133 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
134 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
135 #endif
136 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
137 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
138 #endif
139 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
140 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
141 #endif
142 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
143 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
144 #endif
145 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
146 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
147 #endif
148
149 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
150
151 #define ICHREG(x) ICH_REG_##x
152
153 #define DEFINE_REGSET(name,base) \
154 enum { \
155 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
156 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
157 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
158 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
159 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
160 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
161 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
162 };
163
164 /* busmaster blocks */
165 DEFINE_REGSET(OFF, 0); /* offset */
166 DEFINE_REGSET(PI, 0x00); /* PCM in */
167 DEFINE_REGSET(PO, 0x10); /* PCM out */
168 DEFINE_REGSET(MC, 0x20); /* Mic in */
169
170 /* ICH4 busmaster blocks */
171 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
172 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
173 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
174
175 /* values for each busmaster block */
176
177 /* LVI */
178 #define ICH_REG_LVI_MASK 0x1f
179
180 /* SR */
181 #define ICH_FIFOE 0x10 /* FIFO error */
182 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
183 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
184 #define ICH_CELV 0x02 /* current equals last valid */
185 #define ICH_DCH 0x01 /* DMA controller halted */
186
187 /* PIV */
188 #define ICH_REG_PIV_MASK 0x1f /* mask */
189
190 /* CR */
191 #define ICH_IOCE 0x10 /* interrupt on completion enable */
192 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
193 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
194 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
195 #define ICH_STARTBM 0x01 /* start busmaster operation */
196
197
198 /* global block */
199 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
200 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
201 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
202 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
203 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
204 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
205 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
206 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
207 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
208 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
209 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
210 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
211 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
212 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
213 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
214 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
215 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
216 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
217 #define ICH_ACLINK 0x00000008 /* AClink shut off */
218 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
219 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
220 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
221 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
222 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
223 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
224 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
225 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
226 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
227 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
228 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
229 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
230 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
231 #define ICH_MD3 0x00020000 /* modem power down semaphore */
232 #define ICH_AD3 0x00010000 /* audio power down semaphore */
233 #define ICH_RCS 0x00008000 /* read completion status */
234 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
235 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
236 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
237 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
238 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
239 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
240 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
241 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
242 #define ICH_POINT 0x00000040 /* playback interrupt */
243 #define ICH_PIINT 0x00000020 /* capture interrupt */
244 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
245 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
246 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
247 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
248 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
249 #define ICH_CAS 0x01 /* codec access semaphore */
250 #define ICH_REG_SDM 0x80
251 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
252 #define ICH_DI2L_SHIFT 6
253 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
254 #define ICH_DI1L_SHIFT 4
255 #define ICH_SE 0x00000008 /* steer enable */
256 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
257
258 #define ICH_MAX_FRAGS 32 /* max hw frags */
259
260
261 /*
262 * registers for Ali5455
263 */
264
265 /* ALi 5455 busmaster blocks */
266 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
267 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
268 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
269 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
270 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
271 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
272 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
273 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
274 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
275 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
276 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
277
278 enum {
279 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
280 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
281 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
282 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
283 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
284 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
285 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
286 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
287 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
288 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
289 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
290 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
291 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
292 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
293 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
294 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
295 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
296 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
297 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
298 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
299 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
300 };
301
302 #define ALI_CAS_SEM_BUSY 0x80000000
303 #define ALI_CPR_ADDR_SECONDARY 0x100
304 #define ALI_CPR_ADDR_READ 0x80
305 #define ALI_CSPSR_CODEC_READY 0x08
306 #define ALI_CSPSR_READ_OK 0x02
307 #define ALI_CSPSR_WRITE_OK 0x01
308
309 /* interrupts for the whole chip by interrupt status register finish */
310
311 #define ALI_INT_MICIN2 (1<<26)
312 #define ALI_INT_PCMIN2 (1<<25)
313 #define ALI_INT_I2SIN (1<<24)
314 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
315 #define ALI_INT_SPDIFIN (1<<22)
316 #define ALI_INT_LFEOUT (1<<21)
317 #define ALI_INT_CENTEROUT (1<<20)
318 #define ALI_INT_CODECSPDIFOUT (1<<19)
319 #define ALI_INT_MICIN (1<<18)
320 #define ALI_INT_PCMOUT (1<<17)
321 #define ALI_INT_PCMIN (1<<16)
322 #define ALI_INT_CPRAIS (1<<7) /* command port available */
323 #define ALI_INT_SPRAIS (1<<5) /* status port available */
324 #define ALI_INT_GPIO (1<<1)
325 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
326
327 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
328 #define ICH_ALI_SC_AC97_DBL (1<<30)
329 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
330 #define ICH_ALI_SC_IN_BITS (3<<18)
331 #define ICH_ALI_SC_OUT_BITS (3<<16)
332 #define ICH_ALI_SC_6CH_CFG (3<<14)
333 #define ICH_ALI_SC_PCM_4 (1<<8)
334 #define ICH_ALI_SC_PCM_6 (2<<8)
335 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
336
337 #define ICH_ALI_SS_SEC_ID (3<<5)
338 #define ICH_ALI_SS_PRI_ID (3<<3)
339
340 #define ICH_ALI_IF_AC97SP (1<<21)
341 #define ICH_ALI_IF_MC (1<<20)
342 #define ICH_ALI_IF_PI (1<<19)
343 #define ICH_ALI_IF_MC2 (1<<18)
344 #define ICH_ALI_IF_PI2 (1<<17)
345 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
346 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
347 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
348 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
349 #define ICH_ALI_IF_PO_SPDF (1<<3)
350 #define ICH_ALI_IF_PO (1<<1)
351
352 /*
353 *
354 */
355
356 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
357 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
358 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
359
360 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
361
362 typedef struct {
363 unsigned int ichd; /* ich device number */
364 unsigned long reg_offset; /* offset to bmaddr */
365 u32 *bdbar; /* CPU address (32bit) */
366 unsigned int bdbar_addr; /* PCI bus address (32bit) */
367 snd_pcm_substream_t *substream;
368 unsigned int physbuf; /* physical address (32bit) */
369 unsigned int size;
370 unsigned int fragsize;
371 unsigned int fragsize1;
372 unsigned int position;
373 unsigned int pos_shift;
374 int frags;
375 int lvi;
376 int lvi_frag;
377 int civ;
378 int ack;
379 int ack_reload;
380 unsigned int ack_bit;
381 unsigned int roff_sr;
382 unsigned int roff_picb;
383 unsigned int int_sta_mask; /* interrupt status mask */
384 unsigned int ali_slot; /* ALI DMA slot */
385 struct ac97_pcm *pcm;
386 int pcm_open_flag;
387 unsigned int page_attr_changed: 1;
388 } ichdev_t;
389
390 typedef struct _snd_intel8x0 intel8x0_t;
391
392 struct _snd_intel8x0 {
393 unsigned int device_type;
394
395 int irq;
396
397 unsigned int mmio;
398 unsigned long addr;
399 void __iomem *remap_addr;
400 unsigned int bm_mmio;
401 unsigned long bmaddr;
402 void __iomem *remap_bmaddr;
403
404 struct pci_dev *pci;
405 snd_card_t *card;
406
407 int pcm_devs;
408 snd_pcm_t *pcm[6];
409 ichdev_t ichd[6];
410
411 unsigned multi4: 1,
412 multi6: 1,
413 dra: 1,
414 smp20bit: 1;
415 unsigned in_ac97_init: 1,
416 in_sdin_init: 1;
417 unsigned in_measurement: 1; /* during ac97 clock measurement */
418 unsigned fix_nocache: 1; /* workaround for 440MX */
419 unsigned buggy_irq: 1; /* workaround for buggy mobos */
420 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
421
422 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
423
424 ac97_bus_t *ac97_bus;
425 ac97_t *ac97[3];
426 unsigned int ac97_sdin[3];
427
428 spinlock_t reg_lock;
429
430 u32 bdbars_count;
431 struct snd_dma_buffer bdbars;
432 u32 int_sta_reg; /* interrupt status register */
433 u32 int_sta_mask; /* interrupt status mask */
434 };
435
436 static struct pci_device_id snd_intel8x0_ids[] = {
437 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
438 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
439 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
440 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
441 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
442 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
443 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
444 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
445 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
446 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
447 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
448 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
449 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
450 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
451 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
452 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
453 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
454 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
455 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
456 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
457 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
458 { 0, }
459 };
460
461 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
462
463 /*
464 * Lowlevel I/O - busmaster
465 */
466
467 static u8 igetbyte(intel8x0_t *chip, u32 offset)
468 {
469 if (chip->bm_mmio)
470 return readb(chip->remap_bmaddr + offset);
471 else
472 return inb(chip->bmaddr + offset);
473 }
474
475 static u16 igetword(intel8x0_t *chip, u32 offset)
476 {
477 if (chip->bm_mmio)
478 return readw(chip->remap_bmaddr + offset);
479 else
480 return inw(chip->bmaddr + offset);
481 }
482
483 static u32 igetdword(intel8x0_t *chip, u32 offset)
484 {
485 if (chip->bm_mmio)
486 return readl(chip->remap_bmaddr + offset);
487 else
488 return inl(chip->bmaddr + offset);
489 }
490
491 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
492 {
493 if (chip->bm_mmio)
494 writeb(val, chip->remap_bmaddr + offset);
495 else
496 outb(val, chip->bmaddr + offset);
497 }
498
499 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
500 {
501 if (chip->bm_mmio)
502 writew(val, chip->remap_bmaddr + offset);
503 else
504 outw(val, chip->bmaddr + offset);
505 }
506
507 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
508 {
509 if (chip->bm_mmio)
510 writel(val, chip->remap_bmaddr + offset);
511 else
512 outl(val, chip->bmaddr + offset);
513 }
514
515 /*
516 * Lowlevel I/O - AC'97 registers
517 */
518
519 static u16 iagetword(intel8x0_t *chip, u32 offset)
520 {
521 if (chip->mmio)
522 return readw(chip->remap_addr + offset);
523 else
524 return inw(chip->addr + offset);
525 }
526
527 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
528 {
529 if (chip->mmio)
530 writew(val, chip->remap_addr + offset);
531 else
532 outw(val, chip->addr + offset);
533 }
534
535 /*
536 * Basic I/O
537 */
538
539 /*
540 * access to AC97 codec via normal i/o (for ICH and SIS7012)
541 */
542
543 /* return the GLOB_STA bit for the corresponding codec */
544 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
545 {
546 static unsigned int codec_bit[3] = {
547 ICH_PCR, ICH_SCR, ICH_TCR
548 };
549 snd_assert(codec < 3, return ICH_PCR);
550 if (chip->device_type == DEVICE_INTEL_ICH4)
551 codec = chip->ac97_sdin[codec];
552 return codec_bit[codec];
553 }
554
555 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
556 {
557 int time;
558
559 if (codec > 2)
560 return -EIO;
561 if (chip->in_sdin_init) {
562 /* we don't know the ready bit assignment at the moment */
563 /* so we check any */
564 codec = ICH_PCR | ICH_SCR | ICH_TCR;
565 } else {
566 codec = get_ich_codec_bit(chip, codec);
567 }
568
569 /* codec ready ? */
570 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
571 return -EIO;
572
573 /* Anyone holding a semaphore for 1 msec should be shot... */
574 time = 100;
575 do {
576 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
577 return 0;
578 udelay(10);
579 } while (time--);
580
581 /* access to some forbidden (non existant) ac97 registers will not
582 * reset the semaphore. So even if you don't get the semaphore, still
583 * continue the access. We don't need the semaphore anyway. */
584 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
585 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
586 iagetword(chip, 0); /* clear semaphore flag */
587 /* I don't care about the semaphore */
588 return -EBUSY;
589 }
590
591 static void snd_intel8x0_codec_write(ac97_t *ac97,
592 unsigned short reg,
593 unsigned short val)
594 {
595 intel8x0_t *chip = ac97->private_data;
596
597 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
598 if (! chip->in_ac97_init)
599 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
600 }
601 iaputword(chip, reg + ac97->num * 0x80, val);
602 }
603
604 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
605 unsigned short reg)
606 {
607 intel8x0_t *chip = ac97->private_data;
608 unsigned short res;
609 unsigned int tmp;
610
611 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
612 if (! chip->in_ac97_init)
613 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
614 res = 0xffff;
615 } else {
616 res = iagetword(chip, reg + ac97->num * 0x80);
617 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
618 /* reset RCS and preserve other R/WC bits */
619 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
620 if (! chip->in_ac97_init)
621 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
622 res = 0xffff;
623 }
624 }
625 return res;
626 }
627
628 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
629 {
630 unsigned int tmp;
631
632 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
633 iagetword(chip, codec * 0x80);
634 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
635 /* reset RCS and preserve other R/WC bits */
636 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
637 }
638 }
639 }
640
641 /*
642 * access to AC97 for Ali5455
643 */
644 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
645 {
646 int count = 0;
647 for (count = 0; count < 0x7f; count++) {
648 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
649 if (val & mask)
650 return 0;
651 }
652 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
653 return -EBUSY;
654 }
655
656 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
657 {
658 int time = 100;
659 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
660 udelay(1);
661 if (! time)
662 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
663 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
664 }
665
666 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
667 {
668 intel8x0_t *chip = ac97->private_data;
669 unsigned short data = 0xffff;
670
671 if (snd_intel8x0_ali_codec_semaphore(chip))
672 goto __err;
673 reg |= ALI_CPR_ADDR_READ;
674 if (ac97->num)
675 reg |= ALI_CPR_ADDR_SECONDARY;
676 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
677 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
678 goto __err;
679 data = igetword(chip, ICHREG(ALI_SPR));
680 __err:
681 return data;
682 }
683
684 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
685 {
686 intel8x0_t *chip = ac97->private_data;
687
688 if (snd_intel8x0_ali_codec_semaphore(chip))
689 return;
690 iputword(chip, ICHREG(ALI_CPR), val);
691 if (ac97->num)
692 reg |= ALI_CPR_ADDR_SECONDARY;
693 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
694 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
695 }
696
697
698 /*
699 * DMA I/O
700 */
701 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
702 {
703 int idx;
704 u32 *bdbar = ichdev->bdbar;
705 unsigned long port = ichdev->reg_offset;
706
707 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
708 if (ichdev->size == ichdev->fragsize) {
709 ichdev->ack_reload = ichdev->ack = 2;
710 ichdev->fragsize1 = ichdev->fragsize >> 1;
711 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
712 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
713 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
714 ichdev->fragsize1 >> ichdev->pos_shift);
715 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
716 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
717 ichdev->fragsize1 >> ichdev->pos_shift);
718 }
719 ichdev->frags = 2;
720 } else {
721 ichdev->ack_reload = ichdev->ack = 1;
722 ichdev->fragsize1 = ichdev->fragsize;
723 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
724 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
725 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
726 ichdev->fragsize >> ichdev->pos_shift);
727 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
728 }
729 ichdev->frags = ichdev->size / ichdev->fragsize;
730 }
731 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
732 ichdev->civ = 0;
733 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
734 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
735 ichdev->position = 0;
736 #if 0
737 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
738 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
739 #endif
740 /* clear interrupts */
741 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
742 }
743
744 #ifdef __i386__
745 /*
746 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
747 * which aborts PCI busmaster for audio transfer. A workaround is to set
748 * the pages as non-cached. For details, see the errata in
749 * http://www.intel.com/design/chipsets/specupdt/245051.htm
750 */
751 static void fill_nocache(void *buf, int size, int nocache)
752 {
753 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
754 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
755 global_flush_tlb();
756 }
757 #else
758 #define fill_nocache(buf,size,nocache)
759 #endif
760
761 /*
762 * Interrupt handler
763 */
764
765 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
766 {
767 unsigned long port = ichdev->reg_offset;
768 int status, civ, i, step;
769 int ack = 0;
770
771 spin_lock(&chip->reg_lock);
772 status = igetbyte(chip, port + ichdev->roff_sr);
773 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
774 if (!(status & ICH_BCIS)) {
775 step = 0;
776 } else if (civ == ichdev->civ) {
777 // snd_printd("civ same %d\n", civ);
778 step = 1;
779 ichdev->civ++;
780 ichdev->civ &= ICH_REG_LVI_MASK;
781 } else {
782 step = civ - ichdev->civ;
783 if (step < 0)
784 step += ICH_REG_LVI_MASK + 1;
785 // if (step != 1)
786 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
787 ichdev->civ = civ;
788 }
789
790 ichdev->position += step * ichdev->fragsize1;
791 if (! chip->in_measurement)
792 ichdev->position %= ichdev->size;
793 ichdev->lvi += step;
794 ichdev->lvi &= ICH_REG_LVI_MASK;
795 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
796 for (i = 0; i < step; i++) {
797 ichdev->lvi_frag++;
798 ichdev->lvi_frag %= ichdev->frags;
799 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
800 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
801 if (--ichdev->ack == 0) {
802 ichdev->ack = ichdev->ack_reload;
803 ack = 1;
804 }
805 }
806 spin_unlock(&chip->reg_lock);
807 if (ack && ichdev->substream) {
808 snd_pcm_period_elapsed(ichdev->substream);
809 }
810 iputbyte(chip, port + ichdev->roff_sr,
811 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
812 }
813
814 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
815 {
816 intel8x0_t *chip = dev_id;
817 ichdev_t *ichdev;
818 unsigned int status;
819 unsigned int i;
820
821 status = igetdword(chip, chip->int_sta_reg);
822 if (status == 0xffffffff) /* we are not yet resumed */
823 return IRQ_NONE;
824
825 if ((status & chip->int_sta_mask) == 0) {
826 if (status) {
827 /* ack */
828 iputdword(chip, chip->int_sta_reg, status);
829 if (! chip->buggy_irq)
830 status = 0;
831 }
832 return IRQ_RETVAL(status);
833 }
834
835 for (i = 0; i < chip->bdbars_count; i++) {
836 ichdev = &chip->ichd[i];
837 if (status & ichdev->int_sta_mask)
838 snd_intel8x0_update(chip, ichdev);
839 }
840
841 /* ack them */
842 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
843
844 return IRQ_HANDLED;
845 }
846
847 /*
848 * PCM part
849 */
850
851 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
852 {
853 intel8x0_t *chip = snd_pcm_substream_chip(substream);
854 ichdev_t *ichdev = get_ichdev(substream);
855 unsigned char val = 0;
856 unsigned long port = ichdev->reg_offset;
857
858 switch (cmd) {
859 case SNDRV_PCM_TRIGGER_START:
860 case SNDRV_PCM_TRIGGER_RESUME:
861 val = ICH_IOCE | ICH_STARTBM;
862 break;
863 case SNDRV_PCM_TRIGGER_STOP:
864 case SNDRV_PCM_TRIGGER_SUSPEND:
865 val = 0;
866 break;
867 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
868 val = ICH_IOCE;
869 break;
870 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
871 val = ICH_IOCE | ICH_STARTBM;
872 break;
873 default:
874 return -EINVAL;
875 }
876 iputbyte(chip, port + ICH_REG_OFF_CR, val);
877 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
878 /* wait until DMA stopped */
879 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
880 /* reset whole DMA things */
881 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
882 }
883 return 0;
884 }
885
886 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
887 {
888 intel8x0_t *chip = snd_pcm_substream_chip(substream);
889 ichdev_t *ichdev = get_ichdev(substream);
890 unsigned long port = ichdev->reg_offset;
891 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
892 unsigned int val, fifo;
893
894 val = igetdword(chip, ICHREG(ALI_DMACR));
895 switch (cmd) {
896 case SNDRV_PCM_TRIGGER_START:
897 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
898 case SNDRV_PCM_TRIGGER_RESUME:
899 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
900 /* clear FIFO for synchronization of channels */
901 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
902 fifo &= ~(0xff << (ichdev->ali_slot % 4));
903 fifo |= 0x83 << (ichdev->ali_slot % 4);
904 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
905 }
906 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
907 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
908 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
909 break;
910 case SNDRV_PCM_TRIGGER_STOP:
911 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
912 case SNDRV_PCM_TRIGGER_SUSPEND:
913 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
914 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
915 while (igetbyte(chip, port + ICH_REG_OFF_CR))
916 ;
917 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
918 break;
919 /* reset whole DMA things */
920 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
921 /* clear interrupts */
922 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
923 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
924 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
925 break;
926 default:
927 return -EINVAL;
928 }
929 return 0;
930 }
931
932 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
933 snd_pcm_hw_params_t * hw_params)
934 {
935 intel8x0_t *chip = snd_pcm_substream_chip(substream);
936 ichdev_t *ichdev = get_ichdev(substream);
937 snd_pcm_runtime_t *runtime = substream->runtime;
938 int dbl = params_rate(hw_params) > 48000;
939 int err;
940
941 if (chip->fix_nocache && ichdev->page_attr_changed) {
942 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
943 ichdev->page_attr_changed = 0;
944 }
945 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
946 if (err < 0)
947 return err;
948 if (chip->fix_nocache) {
949 if (runtime->dma_area && ! ichdev->page_attr_changed) {
950 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
951 ichdev->page_attr_changed = 1;
952 }
953 }
954 if (ichdev->pcm_open_flag) {
955 snd_ac97_pcm_close(ichdev->pcm);
956 ichdev->pcm_open_flag = 0;
957 }
958 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
959 params_channels(hw_params),
960 ichdev->pcm->r[dbl].slots);
961 if (err >= 0) {
962 ichdev->pcm_open_flag = 1;
963 /* Force SPDIF setting */
964 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
965 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
966 }
967 return err;
968 }
969
970 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
971 {
972 intel8x0_t *chip = snd_pcm_substream_chip(substream);
973 ichdev_t *ichdev = get_ichdev(substream);
974
975 if (ichdev->pcm_open_flag) {
976 snd_ac97_pcm_close(ichdev->pcm);
977 ichdev->pcm_open_flag = 0;
978 }
979 if (chip->fix_nocache && ichdev->page_attr_changed) {
980 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
981 ichdev->page_attr_changed = 0;
982 }
983 return snd_pcm_lib_free_pages(substream);
984 }
985
986 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
987 snd_pcm_runtime_t *runtime)
988 {
989 unsigned int cnt;
990 int dbl = runtime->rate > 48000;
991 switch (chip->device_type) {
992 case DEVICE_ALI:
993 cnt = igetdword(chip, ICHREG(ALI_SCR));
994 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
995 if (runtime->channels == 4 || dbl)
996 cnt |= ICH_ALI_SC_PCM_4;
997 else if (runtime->channels == 6)
998 cnt |= ICH_ALI_SC_PCM_6;
999 iputdword(chip, ICHREG(ALI_SCR), cnt);
1000 break;
1001 case DEVICE_SIS:
1002 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1003 cnt &= ~ICH_SIS_PCM_246_MASK;
1004 if (runtime->channels == 4 || dbl)
1005 cnt |= ICH_SIS_PCM_4;
1006 else if (runtime->channels == 6)
1007 cnt |= ICH_SIS_PCM_6;
1008 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1009 break;
1010 default:
1011 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1012 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1013 if (runtime->channels == 4 || dbl)
1014 cnt |= ICH_PCM_4;
1015 else if (runtime->channels == 6)
1016 cnt |= ICH_PCM_6;
1017 if (chip->device_type == DEVICE_NFORCE) {
1018 /* reset to 2ch once to keep the 6 channel data in alignment,
1019 * to start from Front Left always
1020 */
1021 if (cnt & ICH_PCM_246_MASK) {
1022 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1023 spin_unlock_irq(&chip->reg_lock);
1024 msleep(50); /* grrr... */
1025 spin_lock_irq(&chip->reg_lock);
1026 }
1027 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1028 if (runtime->sample_bits > 16)
1029 cnt |= ICH_PCM_20BIT;
1030 }
1031 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1032 break;
1033 }
1034 }
1035
1036 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1037 {
1038 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1039 snd_pcm_runtime_t *runtime = substream->runtime;
1040 ichdev_t *ichdev = get_ichdev(substream);
1041
1042 ichdev->physbuf = runtime->dma_addr;
1043 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1044 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1045 spin_lock_irq(&chip->reg_lock);
1046 if (ichdev->ichd == ICHD_PCMOUT) {
1047 snd_intel8x0_setup_pcm_out(chip, runtime);
1048 if (chip->device_type == DEVICE_INTEL_ICH4) {
1049 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1050 }
1051 }
1052 snd_intel8x0_setup_periods(chip, ichdev);
1053 spin_unlock_irq(&chip->reg_lock);
1054 return 0;
1055 }
1056
1057 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1058 {
1059 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1060 ichdev_t *ichdev = get_ichdev(substream);
1061 size_t ptr1, ptr;
1062 int civ, timeout = 100;
1063 unsigned int position;
1064
1065 spin_lock(&chip->reg_lock);
1066 do {
1067 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1068 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1069 position = ichdev->position;
1070 if (ptr1 == 0) {
1071 udelay(10);
1072 continue;
1073 }
1074 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1075 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1076 break;
1077 } while (timeout--);
1078 ptr1 <<= ichdev->pos_shift;
1079 ptr = ichdev->fragsize1 - ptr1;
1080 ptr += position;
1081 spin_unlock(&chip->reg_lock);
1082 if (ptr >= ichdev->size)
1083 return 0;
1084 return bytes_to_frames(substream->runtime, ptr);
1085 }
1086
1087 static snd_pcm_hardware_t snd_intel8x0_stream =
1088 {
1089 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1090 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1091 SNDRV_PCM_INFO_MMAP_VALID |
1092 SNDRV_PCM_INFO_PAUSE |
1093 SNDRV_PCM_INFO_RESUME),
1094 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1095 .rates = SNDRV_PCM_RATE_48000,
1096 .rate_min = 48000,
1097 .rate_max = 48000,
1098 .channels_min = 2,
1099 .channels_max = 2,
1100 .buffer_bytes_max = 128 * 1024,
1101 .period_bytes_min = 32,
1102 .period_bytes_max = 128 * 1024,
1103 .periods_min = 1,
1104 .periods_max = 1024,
1105 .fifo_size = 0,
1106 };
1107
1108 static unsigned int channels4[] = {
1109 2, 4,
1110 };
1111
1112 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1113 .count = ARRAY_SIZE(channels4),
1114 .list = channels4,
1115 .mask = 0,
1116 };
1117
1118 static unsigned int channels6[] = {
1119 2, 4, 6,
1120 };
1121
1122 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1123 .count = ARRAY_SIZE(channels6),
1124 .list = channels6,
1125 .mask = 0,
1126 };
1127
1128 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1129 {
1130 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1131 snd_pcm_runtime_t *runtime = substream->runtime;
1132 int err;
1133
1134 ichdev->substream = substream;
1135 runtime->hw = snd_intel8x0_stream;
1136 runtime->hw.rates = ichdev->pcm->rates;
1137 snd_pcm_limit_hw_rates(runtime);
1138 if (chip->device_type == DEVICE_SIS) {
1139 runtime->hw.buffer_bytes_max = 64*1024;
1140 runtime->hw.period_bytes_max = 64*1024;
1141 }
1142 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1143 return err;
1144 runtime->private_data = ichdev;
1145 return 0;
1146 }
1147
1148 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1149 {
1150 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1151 snd_pcm_runtime_t *runtime = substream->runtime;
1152 int err;
1153
1154 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1155 if (err < 0)
1156 return err;
1157
1158 if (chip->multi6) {
1159 runtime->hw.channels_max = 6;
1160 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1161 } else if (chip->multi4) {
1162 runtime->hw.channels_max = 4;
1163 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1164 }
1165 if (chip->dra) {
1166 snd_ac97_pcm_double_rate_rules(runtime);
1167 }
1168 if (chip->smp20bit) {
1169 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1170 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1171 }
1172 return 0;
1173 }
1174
1175 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1176 {
1177 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1178
1179 chip->ichd[ICHD_PCMOUT].substream = NULL;
1180 return 0;
1181 }
1182
1183 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1184 {
1185 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1186
1187 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1188 }
1189
1190 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1191 {
1192 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1193
1194 chip->ichd[ICHD_PCMIN].substream = NULL;
1195 return 0;
1196 }
1197
1198 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1199 {
1200 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1201
1202 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1203 }
1204
1205 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1206 {
1207 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1208
1209 chip->ichd[ICHD_MIC].substream = NULL;
1210 return 0;
1211 }
1212
1213 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1214 {
1215 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1216
1217 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1218 }
1219
1220 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1221 {
1222 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1223
1224 chip->ichd[ICHD_MIC2].substream = NULL;
1225 return 0;
1226 }
1227
1228 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1229 {
1230 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1231
1232 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1233 }
1234
1235 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1236 {
1237 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1238
1239 chip->ichd[ICHD_PCM2IN].substream = NULL;
1240 return 0;
1241 }
1242
1243 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1244 {
1245 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1246 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1247
1248 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1249 }
1250
1251 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1252 {
1253 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1254 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1255
1256 chip->ichd[idx].substream = NULL;
1257 return 0;
1258 }
1259
1260 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1261 {
1262 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1263 unsigned int val;
1264
1265 spin_lock_irq(&chip->reg_lock);
1266 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1267 val |= ICH_ALI_IF_AC97SP;
1268 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1269 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1270 spin_unlock_irq(&chip->reg_lock);
1271
1272 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1273 }
1274
1275 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1276 {
1277 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1278 unsigned int val;
1279
1280 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1281 spin_lock_irq(&chip->reg_lock);
1282 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1283 val &= ~ICH_ALI_IF_AC97SP;
1284 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1285 spin_unlock_irq(&chip->reg_lock);
1286
1287 return 0;
1288 }
1289
1290 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1291 {
1292 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1293
1294 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1295 }
1296
1297 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1298 {
1299 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1300
1301 chip->ichd[ALID_SPDIFIN].substream = NULL;
1302 return 0;
1303 }
1304
1305 #if 0 // NYI
1306 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1307 {
1308 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1309
1310 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1311 }
1312
1313 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1314 {
1315 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1316
1317 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1318 return 0;
1319 }
1320 #endif
1321
1322 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1323 .open = snd_intel8x0_playback_open,
1324 .close = snd_intel8x0_playback_close,
1325 .ioctl = snd_pcm_lib_ioctl,
1326 .hw_params = snd_intel8x0_hw_params,
1327 .hw_free = snd_intel8x0_hw_free,
1328 .prepare = snd_intel8x0_pcm_prepare,
1329 .trigger = snd_intel8x0_pcm_trigger,
1330 .pointer = snd_intel8x0_pcm_pointer,
1331 };
1332
1333 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1334 .open = snd_intel8x0_capture_open,
1335 .close = snd_intel8x0_capture_close,
1336 .ioctl = snd_pcm_lib_ioctl,
1337 .hw_params = snd_intel8x0_hw_params,
1338 .hw_free = snd_intel8x0_hw_free,
1339 .prepare = snd_intel8x0_pcm_prepare,
1340 .trigger = snd_intel8x0_pcm_trigger,
1341 .pointer = snd_intel8x0_pcm_pointer,
1342 };
1343
1344 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1345 .open = snd_intel8x0_mic_open,
1346 .close = snd_intel8x0_mic_close,
1347 .ioctl = snd_pcm_lib_ioctl,
1348 .hw_params = snd_intel8x0_hw_params,
1349 .hw_free = snd_intel8x0_hw_free,
1350 .prepare = snd_intel8x0_pcm_prepare,
1351 .trigger = snd_intel8x0_pcm_trigger,
1352 .pointer = snd_intel8x0_pcm_pointer,
1353 };
1354
1355 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1356 .open = snd_intel8x0_mic2_open,
1357 .close = snd_intel8x0_mic2_close,
1358 .ioctl = snd_pcm_lib_ioctl,
1359 .hw_params = snd_intel8x0_hw_params,
1360 .hw_free = snd_intel8x0_hw_free,
1361 .prepare = snd_intel8x0_pcm_prepare,
1362 .trigger = snd_intel8x0_pcm_trigger,
1363 .pointer = snd_intel8x0_pcm_pointer,
1364 };
1365
1366 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1367 .open = snd_intel8x0_capture2_open,
1368 .close = snd_intel8x0_capture2_close,
1369 .ioctl = snd_pcm_lib_ioctl,
1370 .hw_params = snd_intel8x0_hw_params,
1371 .hw_free = snd_intel8x0_hw_free,
1372 .prepare = snd_intel8x0_pcm_prepare,
1373 .trigger = snd_intel8x0_pcm_trigger,
1374 .pointer = snd_intel8x0_pcm_pointer,
1375 };
1376
1377 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1378 .open = snd_intel8x0_spdif_open,
1379 .close = snd_intel8x0_spdif_close,
1380 .ioctl = snd_pcm_lib_ioctl,
1381 .hw_params = snd_intel8x0_hw_params,
1382 .hw_free = snd_intel8x0_hw_free,
1383 .prepare = snd_intel8x0_pcm_prepare,
1384 .trigger = snd_intel8x0_pcm_trigger,
1385 .pointer = snd_intel8x0_pcm_pointer,
1386 };
1387
1388 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1389 .open = snd_intel8x0_playback_open,
1390 .close = snd_intel8x0_playback_close,
1391 .ioctl = snd_pcm_lib_ioctl,
1392 .hw_params = snd_intel8x0_hw_params,
1393 .hw_free = snd_intel8x0_hw_free,
1394 .prepare = snd_intel8x0_pcm_prepare,
1395 .trigger = snd_intel8x0_ali_trigger,
1396 .pointer = snd_intel8x0_pcm_pointer,
1397 };
1398
1399 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1400 .open = snd_intel8x0_capture_open,
1401 .close = snd_intel8x0_capture_close,
1402 .ioctl = snd_pcm_lib_ioctl,
1403 .hw_params = snd_intel8x0_hw_params,
1404 .hw_free = snd_intel8x0_hw_free,
1405 .prepare = snd_intel8x0_pcm_prepare,
1406 .trigger = snd_intel8x0_ali_trigger,
1407 .pointer = snd_intel8x0_pcm_pointer,
1408 };
1409
1410 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1411 .open = snd_intel8x0_mic_open,
1412 .close = snd_intel8x0_mic_close,
1413 .ioctl = snd_pcm_lib_ioctl,
1414 .hw_params = snd_intel8x0_hw_params,
1415 .hw_free = snd_intel8x0_hw_free,
1416 .prepare = snd_intel8x0_pcm_prepare,
1417 .trigger = snd_intel8x0_ali_trigger,
1418 .pointer = snd_intel8x0_pcm_pointer,
1419 };
1420
1421 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1422 .open = snd_intel8x0_ali_ac97spdifout_open,
1423 .close = snd_intel8x0_ali_ac97spdifout_close,
1424 .ioctl = snd_pcm_lib_ioctl,
1425 .hw_params = snd_intel8x0_hw_params,
1426 .hw_free = snd_intel8x0_hw_free,
1427 .prepare = snd_intel8x0_pcm_prepare,
1428 .trigger = snd_intel8x0_ali_trigger,
1429 .pointer = snd_intel8x0_pcm_pointer,
1430 };
1431
1432 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1433 .open = snd_intel8x0_ali_spdifin_open,
1434 .close = snd_intel8x0_ali_spdifin_close,
1435 .ioctl = snd_pcm_lib_ioctl,
1436 .hw_params = snd_intel8x0_hw_params,
1437 .hw_free = snd_intel8x0_hw_free,
1438 .prepare = snd_intel8x0_pcm_prepare,
1439 .trigger = snd_intel8x0_pcm_trigger,
1440 .pointer = snd_intel8x0_pcm_pointer,
1441 };
1442
1443 #if 0 // NYI
1444 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1445 .open = snd_intel8x0_ali_spdifout_open,
1446 .close = snd_intel8x0_ali_spdifout_close,
1447 .ioctl = snd_pcm_lib_ioctl,
1448 .hw_params = snd_intel8x0_hw_params,
1449 .hw_free = snd_intel8x0_hw_free,
1450 .prepare = snd_intel8x0_pcm_prepare,
1451 .trigger = snd_intel8x0_pcm_trigger,
1452 .pointer = snd_intel8x0_pcm_pointer,
1453 };
1454 #endif // NYI
1455
1456 struct ich_pcm_table {
1457 char *suffix;
1458 snd_pcm_ops_t *playback_ops;
1459 snd_pcm_ops_t *capture_ops;
1460 size_t prealloc_size;
1461 size_t prealloc_max_size;
1462 int ac97_idx;
1463 };
1464
1465 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1466 {
1467 snd_pcm_t *pcm;
1468 int err;
1469 char name[32];
1470
1471 if (rec->suffix)
1472 sprintf(name, "Intel ICH - %s", rec->suffix);
1473 else
1474 strcpy(name, "Intel ICH");
1475 err = snd_pcm_new(chip->card, name, device,
1476 rec->playback_ops ? 1 : 0,
1477 rec->capture_ops ? 1 : 0, &pcm);
1478 if (err < 0)
1479 return err;
1480
1481 if (rec->playback_ops)
1482 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1483 if (rec->capture_ops)
1484 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1485
1486 pcm->private_data = chip;
1487 pcm->info_flags = 0;
1488 if (rec->suffix)
1489 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1490 else
1491 strcpy(pcm->name, chip->card->shortname);
1492 chip->pcm[device] = pcm;
1493
1494 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1495 rec->prealloc_size, rec->prealloc_max_size);
1496
1497 return 0;
1498 }
1499
1500 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1501 {
1502 .playback_ops = &snd_intel8x0_playback_ops,
1503 .capture_ops = &snd_intel8x0_capture_ops,
1504 .prealloc_size = 64 * 1024,
1505 .prealloc_max_size = 128 * 1024,
1506 },
1507 {
1508 .suffix = "MIC ADC",
1509 .capture_ops = &snd_intel8x0_capture_mic_ops,
1510 .prealloc_size = 0,
1511 .prealloc_max_size = 128 * 1024,
1512 .ac97_idx = ICHD_MIC,
1513 },
1514 {
1515 .suffix = "MIC2 ADC",
1516 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1517 .prealloc_size = 0,
1518 .prealloc_max_size = 128 * 1024,
1519 .ac97_idx = ICHD_MIC2,
1520 },
1521 {
1522 .suffix = "ADC2",
1523 .capture_ops = &snd_intel8x0_capture2_ops,
1524 .prealloc_size = 0,
1525 .prealloc_max_size = 128 * 1024,
1526 .ac97_idx = ICHD_PCM2IN,
1527 },
1528 {
1529 .suffix = "IEC958",
1530 .playback_ops = &snd_intel8x0_spdif_ops,
1531 .prealloc_size = 64 * 1024,
1532 .prealloc_max_size = 128 * 1024,
1533 .ac97_idx = ICHD_SPBAR,
1534 },
1535 };
1536
1537 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1538 {
1539 .playback_ops = &snd_intel8x0_playback_ops,
1540 .capture_ops = &snd_intel8x0_capture_ops,
1541 .prealloc_size = 64 * 1024,
1542 .prealloc_max_size = 128 * 1024,
1543 },
1544 {
1545 .suffix = "MIC ADC",
1546 .capture_ops = &snd_intel8x0_capture_mic_ops,
1547 .prealloc_size = 0,
1548 .prealloc_max_size = 128 * 1024,
1549 .ac97_idx = NVD_MIC,
1550 },
1551 {
1552 .suffix = "IEC958",
1553 .playback_ops = &snd_intel8x0_spdif_ops,
1554 .prealloc_size = 64 * 1024,
1555 .prealloc_max_size = 128 * 1024,
1556 .ac97_idx = NVD_SPBAR,
1557 },
1558 };
1559
1560 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1561 {
1562 .playback_ops = &snd_intel8x0_ali_playback_ops,
1563 .capture_ops = &snd_intel8x0_ali_capture_ops,
1564 .prealloc_size = 64 * 1024,
1565 .prealloc_max_size = 128 * 1024,
1566 },
1567 {
1568 .suffix = "MIC ADC",
1569 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1570 .prealloc_size = 0,
1571 .prealloc_max_size = 128 * 1024,
1572 .ac97_idx = ALID_MIC,
1573 },
1574 {
1575 .suffix = "IEC958",
1576 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1577 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1578 .prealloc_size = 64 * 1024,
1579 .prealloc_max_size = 128 * 1024,
1580 .ac97_idx = ALID_AC97SPDIFOUT,
1581 },
1582 #if 0 // NYI
1583 {
1584 .suffix = "HW IEC958",
1585 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1586 .prealloc_size = 64 * 1024,
1587 .prealloc_max_size = 128 * 1024,
1588 },
1589 #endif
1590 };
1591
1592 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1593 {
1594 int i, tblsize, device, err;
1595 struct ich_pcm_table *tbl, *rec;
1596
1597 switch (chip->device_type) {
1598 case DEVICE_INTEL_ICH4:
1599 tbl = intel_pcms;
1600 tblsize = ARRAY_SIZE(intel_pcms);
1601 break;
1602 case DEVICE_NFORCE:
1603 tbl = nforce_pcms;
1604 tblsize = ARRAY_SIZE(nforce_pcms);
1605 break;
1606 case DEVICE_ALI:
1607 tbl = ali_pcms;
1608 tblsize = ARRAY_SIZE(ali_pcms);
1609 break;
1610 default:
1611 tbl = intel_pcms;
1612 tblsize = 2;
1613 break;
1614 }
1615
1616 device = 0;
1617 for (i = 0; i < tblsize; i++) {
1618 rec = tbl + i;
1619 if (i > 0 && rec->ac97_idx) {
1620 /* activate PCM only when associated AC'97 codec */
1621 if (! chip->ichd[rec->ac97_idx].pcm)
1622 continue;
1623 }
1624 err = snd_intel8x0_pcm1(chip, device, rec);
1625 if (err < 0)
1626 return err;
1627 device++;
1628 }
1629
1630 chip->pcm_devs = device;
1631 return 0;
1632 }
1633
1634
1635 /*
1636 * Mixer part
1637 */
1638
1639 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1640 {
1641 intel8x0_t *chip = bus->private_data;
1642 chip->ac97_bus = NULL;
1643 }
1644
1645 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1646 {
1647 intel8x0_t *chip = ac97->private_data;
1648 chip->ac97[ac97->num] = NULL;
1649 }
1650
1651 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1652 /* front PCM */
1653 {
1654 .exclusive = 1,
1655 .r = { {
1656 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1657 (1 << AC97_SLOT_PCM_RIGHT) |
1658 (1 << AC97_SLOT_PCM_CENTER) |
1659 (1 << AC97_SLOT_PCM_SLEFT) |
1660 (1 << AC97_SLOT_PCM_SRIGHT) |
1661 (1 << AC97_SLOT_LFE)
1662 },
1663 {
1664 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1665 (1 << AC97_SLOT_PCM_RIGHT) |
1666 (1 << AC97_SLOT_PCM_LEFT_0) |
1667 (1 << AC97_SLOT_PCM_RIGHT_0)
1668 }
1669 }
1670 },
1671 /* PCM IN #1 */
1672 {
1673 .stream = 1,
1674 .exclusive = 1,
1675 .r = { {
1676 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1677 (1 << AC97_SLOT_PCM_RIGHT)
1678 }
1679 }
1680 },
1681 /* MIC IN #1 */
1682 {
1683 .stream = 1,
1684 .exclusive = 1,
1685 .r = { {
1686 .slots = (1 << AC97_SLOT_MIC)
1687 }
1688 }
1689 },
1690 /* S/PDIF PCM */
1691 {
1692 .exclusive = 1,
1693 .spdif = 1,
1694 .r = { {
1695 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1696 (1 << AC97_SLOT_SPDIF_RIGHT2)
1697 }
1698 }
1699 },
1700 /* PCM IN #2 */
1701 {
1702 .stream = 1,
1703 .exclusive = 1,
1704 .r = { {
1705 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1706 (1 << AC97_SLOT_PCM_RIGHT)
1707 }
1708 }
1709 },
1710 /* MIC IN #2 */
1711 {
1712 .stream = 1,
1713 .exclusive = 1,
1714 .r = { {
1715 .slots = (1 << AC97_SLOT_MIC)
1716 }
1717 }
1718 },
1719 };
1720
1721 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1722 {
1723 .vendor = 0x0e11,
1724 .device = 0x008a,
1725 .name = "Compaq Evo W4000", /* AD1885 */
1726 .type = AC97_TUNE_HP_ONLY
1727 },
1728 {
1729 .vendor = 0x0e11,
1730 .device = 0x00b8,
1731 .name = "Compaq Evo D510C",
1732 .type = AC97_TUNE_HP_ONLY
1733 },
1734 {
1735 .vendor = 0x0e11,
1736 .device = 0x0860,
1737 .name = "HP/Compaq nx7010",
1738 .type = AC97_TUNE_MUTE_LED
1739 },
1740 {
1741 .vendor = 0x1014,
1742 .device = 0x1f00,
1743 .name = "MS-9128",
1744 .type = AC97_TUNE_ALC_JACK
1745 },
1746 {
1747 .vendor = 0x1028,
1748 .device = 0x00d8,
1749 .name = "Dell Precision 530", /* AD1885 */
1750 .type = AC97_TUNE_HP_ONLY
1751 },
1752 {
1753 .vendor = 0x1028,
1754 .device = 0x010d,
1755 .name = "Dell", /* which model? AD1885 */
1756 .type = AC97_TUNE_HP_ONLY
1757 },
1758 {
1759 .vendor = 0x1028,
1760 .device = 0x0126,
1761 .name = "Dell Optiplex GX260", /* AD1981A */
1762 .type = AC97_TUNE_HP_ONLY
1763 },
1764 {
1765 .vendor = 0x1028,
1766 .device = 0x012c,
1767 .name = "Dell Precision 650", /* AD1981A */
1768 .type = AC97_TUNE_HP_ONLY
1769 },
1770 {
1771 .vendor = 0x1028,
1772 .device = 0x012d,
1773 .name = "Dell Precision 450", /* AD1981B*/
1774 .type = AC97_TUNE_HP_ONLY
1775 },
1776 {
1777 .vendor = 0x1028,
1778 .device = 0x0147,
1779 .name = "Dell", /* which model? AD1981B*/
1780 .type = AC97_TUNE_HP_ONLY
1781 },
1782 {
1783 .vendor = 0x1028,
1784 .device = 0x0163,
1785 .name = "Dell Unknown", /* STAC9750/51 */
1786 .type = AC97_TUNE_HP_ONLY
1787 },
1788 {
1789 .vendor = 0x103c,
1790 .device = 0x006d,
1791 .name = "HP zv5000",
1792 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1793 },
1794 { /* FIXME: which codec? */
1795 .vendor = 0x103c,
1796 .device = 0x00c3,
1797 .name = "HP xw6000",
1798 .type = AC97_TUNE_HP_ONLY
1799 },
1800 {
1801 .vendor = 0x103c,
1802 .device = 0x088c,
1803 .name = "HP nc8000",
1804 .type = AC97_TUNE_MUTE_LED
1805 },
1806 {
1807 .vendor = 0x103c,
1808 .device = 0x0890,
1809 .name = "HP nc6000",
1810 .type = AC97_TUNE_MUTE_LED
1811 },
1812 {
1813 .vendor = 0x103c,
1814 .device = 0x129d,
1815 .name = "HP xw8000",
1816 .type = AC97_TUNE_HP_ONLY
1817 },
1818 {
1819 .vendor = 0x103c,
1820 .device = 0x12f1,
1821 .name = "HP xw8200", /* AD1981B*/
1822 .type = AC97_TUNE_HP_ONLY
1823 },
1824 {
1825 .vendor = 0x103c,
1826 .device = 0x12f2,
1827 .name = "HP xw6200",
1828 .type = AC97_TUNE_HP_ONLY
1829 },
1830 {
1831 .vendor = 0x103c,
1832 .device = 0x3008,
1833 .name = "HP xw4200", /* AD1981B*/
1834 .type = AC97_TUNE_HP_ONLY
1835 },
1836 {
1837 .vendor = 0x104d,
1838 .device = 0x8197,
1839 .name = "Sony S1XP",
1840 .type = AC97_TUNE_INV_EAPD
1841 },
1842 {
1843 .vendor = 0x1043,
1844 .device = 0x80f3,
1845 .name = "ASUS ICH5/AD1985",
1846 .type = AC97_TUNE_AD_SHARING
1847 },
1848 {
1849 .vendor = 0x10cf,
1850 .device = 0x11c3,
1851 .name = "Fujitsu-Siemens E4010",
1852 .type = AC97_TUNE_HP_ONLY
1853 },
1854 {
1855 .vendor = 0x10cf,
1856 .device = 0x1253,
1857 .name = "Fujitsu S6210", /* STAC9750/51 */
1858 .type = AC97_TUNE_HP_ONLY
1859 },
1860 {
1861 .vendor = 0x10f1,
1862 .device = 0x2665,
1863 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1864 .type = AC97_TUNE_HP_ONLY
1865 },
1866 {
1867 .vendor = 0x10f1,
1868 .device = 0x2885,
1869 .name = "AMD64 Mobo", /* ALC650 */
1870 .type = AC97_TUNE_HP_ONLY
1871 },
1872 {
1873 .vendor = 0x110a,
1874 .device = 0x0056,
1875 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1876 .type = AC97_TUNE_HP_ONLY
1877 },
1878 {
1879 .vendor = 0x11d4,
1880 .device = 0x5375,
1881 .name = "ADI AD1985 (discrete)",
1882 .type = AC97_TUNE_HP_ONLY
1883 },
1884 {
1885 .vendor = 0x1462,
1886 .device = 0x5470,
1887 .name = "MSI P4 ATX 645 Ultra",
1888 .type = AC97_TUNE_HP_ONLY
1889 },
1890 {
1891 .vendor = 0x1734,
1892 .device = 0x0088,
1893 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1894 .type = AC97_TUNE_HP_ONLY
1895 },
1896 {
1897 .vendor = 0x8086,
1898 .device = 0x2000,
1899 .mask = 0xfff0,
1900 .name = "Intel ICH5/AD1985",
1901 .type = AC97_TUNE_AD_SHARING
1902 },
1903 {
1904 .vendor = 0x8086,
1905 .device = 0x4000,
1906 .mask = 0xfff0,
1907 .name = "Intel ICH5/AD1985",
1908 .type = AC97_TUNE_AD_SHARING
1909 },
1910 {
1911 .vendor = 0x8086,
1912 .device = 0x4856,
1913 .name = "Intel D845WN (82801BA)",
1914 .type = AC97_TUNE_SWAP_HP
1915 },
1916 {
1917 .vendor = 0x8086,
1918 .device = 0x4d44,
1919 .name = "Intel D850EMV2", /* AD1885 */
1920 .type = AC97_TUNE_HP_ONLY
1921 },
1922 {
1923 .vendor = 0x8086,
1924 .device = 0x4d56,
1925 .name = "Intel ICH/AD1885",
1926 .type = AC97_TUNE_HP_ONLY
1927 },
1928 {
1929 .vendor = 0x8086,
1930 .device = 0x6000,
1931 .mask = 0xfff0,
1932 .name = "Intel ICH5/AD1985",
1933 .type = AC97_TUNE_AD_SHARING
1934 },
1935 {
1936 .vendor = 0x8086,
1937 .device = 0xe000,
1938 .mask = 0xfff0,
1939 .name = "Intel ICH5/AD1985",
1940 .type = AC97_TUNE_AD_SHARING
1941 },
1942 #if 0 /* FIXME: this seems wrong on most boards */
1943 {
1944 .vendor = 0x8086,
1945 .device = 0xa000,
1946 .mask = 0xfff0,
1947 .name = "Intel ICH5/AD1985",
1948 .type = AC97_TUNE_HP_ONLY
1949 },
1950 #endif
1951 { } /* terminator */
1952 };
1953
1954 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1955 {
1956 ac97_bus_t *pbus;
1957 ac97_template_t ac97;
1958 int err;
1959 unsigned int i, codecs;
1960 unsigned int glob_sta = 0;
1961 ac97_bus_ops_t *ops;
1962 static ac97_bus_ops_t standard_bus_ops = {
1963 .write = snd_intel8x0_codec_write,
1964 .read = snd_intel8x0_codec_read,
1965 };
1966 static ac97_bus_ops_t ali_bus_ops = {
1967 .write = snd_intel8x0_ali_codec_write,
1968 .read = snd_intel8x0_ali_codec_read,
1969 };
1970
1971 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1972 switch (chip->device_type) {
1973 case DEVICE_NFORCE:
1974 chip->spdif_idx = NVD_SPBAR;
1975 break;
1976 case DEVICE_ALI:
1977 chip->spdif_idx = ALID_AC97SPDIFOUT;
1978 break;
1979 case DEVICE_INTEL_ICH4:
1980 chip->spdif_idx = ICHD_SPBAR;
1981 break;
1982 };
1983
1984 chip->in_ac97_init = 1;
1985
1986 memset(&ac97, 0, sizeof(ac97));
1987 ac97.private_data = chip;
1988 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1989 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1990 if (chip->xbox)
1991 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1992 if (chip->device_type != DEVICE_ALI) {
1993 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1994 ops = &standard_bus_ops;
1995 if (chip->device_type == DEVICE_INTEL_ICH4) {
1996 codecs = 0;
1997 if (glob_sta & ICH_PCR)
1998 codecs++;
1999 if (glob_sta & ICH_SCR)
2000 codecs++;
2001 if (glob_sta & ICH_TCR)
2002 codecs++;
2003 chip->in_sdin_init = 1;
2004 for (i = 0; i < codecs; i++) {
2005 snd_intel8x0_codec_read_test(chip, i);
2006 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2007 }
2008 chip->in_sdin_init = 0;
2009 } else {
2010 codecs = glob_sta & ICH_SCR ? 2 : 1;
2011 }
2012 } else {
2013 ops = &ali_bus_ops;
2014 codecs = 1;
2015 /* detect the secondary codec */
2016 for (i = 0; i < 100; i++) {
2017 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2018 if (reg & 0x40) {
2019 codecs = 2;
2020 break;
2021 }
2022 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2023 udelay(1);
2024 }
2025 }
2026 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2027 goto __err;
2028 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2029 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
2030 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2031 pbus->clock = ac97_clock;
2032 /* FIXME: my test board doesn't work well with VRA... */
2033 if (chip->device_type == DEVICE_ALI)
2034 pbus->no_vra = 1;
2035 else
2036 pbus->dra = 1;
2037 chip->ac97_bus = pbus;
2038
2039 ac97.pci = chip->pci;
2040 for (i = 0; i < codecs; i++) {
2041 ac97.num = i;
2042 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2043 if (err != -EACCES)
2044 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2045 if (i == 0)
2046 goto __err;
2047 continue;
2048 }
2049 }
2050 /* tune up the primary codec */
2051 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2052 /* enable separate SDINs for ICH4 */
2053 if (chip->device_type == DEVICE_INTEL_ICH4)
2054 pbus->isdin = 1;
2055 /* find the available PCM streams */
2056 i = ARRAY_SIZE(ac97_pcm_defs);
2057 if (chip->device_type != DEVICE_INTEL_ICH4)
2058 i -= 2; /* do not allocate PCM2IN and MIC2 */
2059 if (chip->spdif_idx < 0)
2060 i--; /* do not allocate S/PDIF */
2061 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2062 if (err < 0)
2063 goto __err;
2064 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2065 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2066 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2067 if (chip->spdif_idx >= 0)
2068 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2069 if (chip->device_type == DEVICE_INTEL_ICH4) {
2070 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2071 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2072 }
2073 /* enable separate SDINs for ICH4 */
2074 if (chip->device_type == DEVICE_INTEL_ICH4) {
2075 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2076 u8 tmp = igetbyte(chip, ICHREG(SDM));
2077 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2078 if (pcm) {
2079 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2080 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2081 for (i = 1; i < 4; i++) {
2082 if (pcm->r[0].codec[i]) {
2083 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2084 break;
2085 }
2086 }
2087 } else {
2088 tmp &= ~ICH_SE; /* steer disable */
2089 }
2090 iputbyte(chip, ICHREG(SDM), tmp);
2091 }
2092 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2093 chip->multi4 = 1;
2094 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2095 chip->multi6 = 1;
2096 }
2097 if (pbus->pcms[0].r[1].rslots[0]) {
2098 chip->dra = 1;
2099 }
2100 if (chip->device_type == DEVICE_INTEL_ICH4) {
2101 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2102 chip->smp20bit = 1;
2103 }
2104 if (chip->device_type == DEVICE_NFORCE) {
2105 /* 48kHz only */
2106 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2107 }
2108 if (chip->device_type == DEVICE_INTEL_ICH4) {
2109 /* use slot 10/11 for SPDIF */
2110 u32 val;
2111 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2112 val |= ICH_PCM_SPDIF_1011;
2113 iputdword(chip, ICHREG(GLOB_CNT), val);
2114 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2115 }
2116 chip->in_ac97_init = 0;
2117 return 0;
2118
2119 __err:
2120 /* clear the cold-reset bit for the next chance */
2121 if (chip->device_type != DEVICE_ALI)
2122 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2123 return err;
2124 }
2125
2126
2127 /*
2128 *
2129 */
2130
2131 static void do_ali_reset(intel8x0_t *chip)
2132 {
2133 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2134 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2135 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2136 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2137 iputdword(chip, ICHREG(ALI_INTERFACECR),
2138 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2139 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2140 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2141 }
2142
2143 #define do_delay(chip) do {\
2144 set_current_state(TASK_UNINTERRUPTIBLE);\
2145 schedule_timeout(1);\
2146 } while (0)
2147
2148 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2149 {
2150 unsigned long end_time;
2151 unsigned int cnt, status, nstatus;
2152
2153 /* put logic to right state */
2154 /* first clear status bits */
2155 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2156 if (chip->device_type == DEVICE_NFORCE)
2157 status |= ICH_NVSPINT;
2158 cnt = igetdword(chip, ICHREG(GLOB_STA));
2159 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2160
2161 /* ACLink on, 2 channels */
2162 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2163 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2164 /* finish cold or do warm reset */
2165 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2166 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2167 end_time = (jiffies + (HZ / 4)) + 1;
2168 do {
2169 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2170 goto __ok;
2171 do_delay(chip);
2172 } while (time_after_eq(end_time, jiffies));
2173 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2174 return -EIO;
2175
2176 __ok:
2177 if (probing) {
2178 /* wait for any codec ready status.
2179 * Once it becomes ready it should remain ready
2180 * as long as we do not disable the ac97 link.
2181 */
2182 end_time = jiffies + HZ;
2183 do {
2184 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2185 if (status)
2186 break;
2187 do_delay(chip);
2188 } while (time_after_eq(end_time, jiffies));
2189 if (! status) {
2190 /* no codec is found */
2191 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2192 return -EIO;
2193 }
2194
2195 if (chip->device_type == DEVICE_INTEL_ICH4)
2196 /* ICH4 can have three codecs */
2197 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2198 else
2199 /* others up to two codecs */
2200 nstatus = ICH_PCR | ICH_SCR;
2201
2202 /* wait for other codecs ready status. */
2203 end_time = jiffies + HZ / 4;
2204 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2205 do_delay(chip);
2206 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2207 }
2208
2209 } else {
2210 /* resume phase */
2211 int i;
2212 status = 0;
2213 for (i = 0; i < 3; i++)
2214 if (chip->ac97[i])
2215 status |= get_ich_codec_bit(chip, i);
2216 /* wait until all the probed codecs are ready */
2217 end_time = jiffies + HZ;
2218 do {
2219 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2220 if (status == nstatus)
2221 break;
2222 do_delay(chip);
2223 } while (time_after_eq(end_time, jiffies));
2224 }
2225
2226 if (chip->device_type == DEVICE_SIS) {
2227 /* unmute the output on SIS7012 */
2228 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2229 }
2230 if (chip->device_type == DEVICE_NFORCE) {
2231 /* enable SPDIF interrupt */
2232 unsigned int val;
2233 pci_read_config_dword(chip->pci, 0x4c, &val);
2234 val |= 0x1000000;
2235 pci_write_config_dword(chip->pci, 0x4c, val);
2236 }
2237 return 0;
2238 }
2239
2240 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2241 {
2242 u32 reg;
2243 int i = 0;
2244
2245 reg = igetdword(chip, ICHREG(ALI_SCR));
2246 if ((reg & 2) == 0) /* Cold required */
2247 reg |= 2;
2248 else
2249 reg |= 1; /* Warm */
2250 reg &= ~0x80000000; /* ACLink on */
2251 iputdword(chip, ICHREG(ALI_SCR), reg);
2252
2253 for (i = 0; i < HZ / 2; i++) {
2254 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2255 goto __ok;
2256 do_delay(chip);
2257 }
2258 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2259 if (probing)
2260 return -EIO;
2261
2262 __ok:
2263 for (i = 0; i < HZ / 2; i++) {
2264 reg = igetdword(chip, ICHREG(ALI_RTSR));
2265 if (reg & 0x80) /* primary codec */
2266 break;
2267 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2268 do_delay(chip);
2269 }
2270
2271 do_ali_reset(chip);
2272 return 0;
2273 }
2274
2275 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2276 {
2277 unsigned int i;
2278 int err;
2279
2280 if (chip->device_type != DEVICE_ALI) {
2281 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2282 return err;
2283 iagetword(chip, 0); /* clear semaphore flag */
2284 } else {
2285 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2286 return err;
2287 }
2288
2289 /* disable interrupts */
2290 for (i = 0; i < chip->bdbars_count; i++)
2291 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2292 /* reset channels */
2293 for (i = 0; i < chip->bdbars_count; i++)
2294 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2295 /* initialize Buffer Descriptor Lists */
2296 for (i = 0; i < chip->bdbars_count; i++)
2297 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2298 return 0;
2299 }
2300
2301 static int snd_intel8x0_free(intel8x0_t *chip)
2302 {
2303 unsigned int i;
2304
2305 if (chip->irq < 0)
2306 goto __hw_end;
2307 /* disable interrupts */
2308 for (i = 0; i < chip->bdbars_count; i++)
2309 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2310 /* reset channels */
2311 for (i = 0; i < chip->bdbars_count; i++)
2312 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2313 if (chip->device_type == DEVICE_NFORCE) {
2314 /* stop the spdif interrupt */
2315 unsigned int val;
2316 pci_read_config_dword(chip->pci, 0x4c, &val);
2317 val &= ~0x1000000;
2318 pci_write_config_dword(chip->pci, 0x4c, val);
2319 }
2320 /* --- */
2321 synchronize_irq(chip->irq);
2322 __hw_end:
2323 if (chip->irq >= 0)
2324 free_irq(chip->irq, (void *)chip);
2325 if (chip->bdbars.area) {
2326 if (chip->fix_nocache)
2327 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2328 snd_dma_free_pages(&chip->bdbars);
2329 }
2330 if (chip->remap_addr)
2331 iounmap(chip->remap_addr);
2332 if (chip->remap_bmaddr)
2333 iounmap(chip->remap_bmaddr);
2334 pci_release_regions(chip->pci);
2335 pci_disable_device(chip->pci);
2336 kfree(chip);
2337 return 0;
2338 }
2339
2340 #ifdef CONFIG_PM
2341 /*
2342 * power management
2343 */
2344 static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2345 {
2346 intel8x0_t *chip = card->pm_private_data;
2347 int i;
2348
2349 for (i = 0; i < chip->pcm_devs; i++)
2350 snd_pcm_suspend_all(chip->pcm[i]);
2351 /* clear nocache */
2352 if (chip->fix_nocache) {
2353 for (i = 0; i < chip->bdbars_count; i++) {
2354 ichdev_t *ichdev = &chip->ichd[i];
2355 if (ichdev->substream && ichdev->page_attr_changed) {
2356 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2357 if (runtime->dma_area)
2358 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2359 }
2360 }
2361 }
2362 for (i = 0; i < 3; i++)
2363 if (chip->ac97[i])
2364 snd_ac97_suspend(chip->ac97[i]);
2365 pci_disable_device(chip->pci);
2366 return 0;
2367 }
2368
2369 static int intel8x0_resume(snd_card_t *card)
2370 {
2371 intel8x0_t *chip = card->pm_private_data;
2372 int i;
2373
2374 pci_enable_device(chip->pci);
2375 pci_set_master(chip->pci);
2376 snd_intel8x0_chip_init(chip, 0);
2377
2378 /* refill nocache */
2379 if (chip->fix_nocache)
2380 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2381
2382 for (i = 0; i < 3; i++)
2383 if (chip->ac97[i])
2384 snd_ac97_resume(chip->ac97[i]);
2385
2386 /* refill nocache */
2387 if (chip->fix_nocache) {
2388 for (i = 0; i < chip->bdbars_count; i++) {
2389 ichdev_t *ichdev = &chip->ichd[i];
2390 if (ichdev->substream && ichdev->page_attr_changed) {
2391 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2392 if (runtime->dma_area)
2393 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2394 }
2395 }
2396 }
2397
2398 return 0;
2399 }
2400 #endif /* CONFIG_PM */
2401
2402 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2403
2404 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2405 {
2406 snd_pcm_substream_t *subs;
2407 ichdev_t *ichdev;
2408 unsigned long port;
2409 unsigned long pos, t;
2410 struct timeval start_time, stop_time;
2411
2412 if (chip->ac97_bus->clock != 48000)
2413 return; /* specified in module option */
2414
2415 subs = chip->pcm[0]->streams[0].substream;
2416 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2417 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2418 return;
2419 }
2420 ichdev = &chip->ichd[ICHD_PCMOUT];
2421 ichdev->physbuf = subs->dma_buffer.addr;
2422 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2423 ichdev->substream = NULL; /* don't process interrupts */
2424
2425 /* set rate */
2426 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2427 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2428 return;
2429 }
2430 snd_intel8x0_setup_periods(chip, ichdev);
2431 port = ichdev->reg_offset;
2432 spin_lock_irq(&chip->reg_lock);
2433 chip->in_measurement = 1;
2434 /* trigger */
2435 if (chip->device_type != DEVICE_ALI)
2436 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2437 else {
2438 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2439 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2440 }
2441 do_gettimeofday(&start_time);
2442 spin_unlock_irq(&chip->reg_lock);
2443 set_current_state(TASK_UNINTERRUPTIBLE);
2444 schedule_timeout(HZ / 20);
2445 spin_lock_irq(&chip->reg_lock);
2446 /* check the position */
2447 pos = ichdev->fragsize1;
2448 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2449 pos += ichdev->position;
2450 chip->in_measurement = 0;
2451 do_gettimeofday(&stop_time);
2452 /* stop */
2453 if (chip->device_type == DEVICE_ALI) {
2454 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2455 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2456 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2457 ;
2458 } else {
2459 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2460 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2461 ;
2462 }
2463 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2464 spin_unlock_irq(&chip->reg_lock);
2465
2466 t = stop_time.tv_sec - start_time.tv_sec;
2467 t *= 1000000;
2468 t += stop_time.tv_usec - start_time.tv_usec;
2469 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2470 if (t == 0) {
2471 snd_printk(KERN_ERR "?? calculation error..\n");
2472 return;
2473 }
2474 pos = (pos / 4) * 1000;
2475 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2476 if (pos < 40000 || pos >= 60000)
2477 /* abnormal value. hw problem? */
2478 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2479 else if (pos < 47500 || pos > 48500)
2480 /* not 48000Hz, tuning the clock.. */
2481 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2482 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2483 }
2484
2485 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2486 snd_info_buffer_t * buffer)
2487 {
2488 intel8x0_t *chip = entry->private_data;
2489 unsigned int tmp;
2490
2491 snd_iprintf(buffer, "Intel8x0\n\n");
2492 if (chip->device_type == DEVICE_ALI)
2493 return;
2494 tmp = igetdword(chip, ICHREG(GLOB_STA));
2495 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2496 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2497 if (chip->device_type == DEVICE_INTEL_ICH4)
2498 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2499 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2500 tmp & ICH_PCR ? " primary" : "",
2501 tmp & ICH_SCR ? " secondary" : "",
2502 tmp & ICH_TCR ? " tertiary" : "",
2503 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2504 if (chip->device_type == DEVICE_INTEL_ICH4)
2505 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2506 chip->ac97_sdin[0],
2507 chip->ac97_sdin[1],
2508 chip->ac97_sdin[2]);
2509 }
2510
2511 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2512 {
2513 snd_info_entry_t *entry;
2514
2515 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2516 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2517 }
2518
2519 static int snd_intel8x0_dev_free(snd_device_t *device)
2520 {
2521 intel8x0_t *chip = device->device_data;
2522 return snd_intel8x0_free(chip);
2523 }
2524
2525 struct ich_reg_info {
2526 unsigned int int_sta_mask;
2527 unsigned int offset;
2528 };
2529
2530 static int __devinit snd_intel8x0_create(snd_card_t * card,
2531 struct pci_dev *pci,
2532 unsigned long device_type,
2533 intel8x0_t ** r_intel8x0)
2534 {
2535 intel8x0_t *chip;
2536 int err;
2537 unsigned int i;
2538 unsigned int int_sta_masks;
2539 ichdev_t *ichdev;
2540 static snd_device_ops_t ops = {
2541 .dev_free = snd_intel8x0_dev_free,
2542 };
2543
2544 static unsigned int bdbars[] = {
2545 3, /* DEVICE_INTEL */
2546 6, /* DEVICE_INTEL_ICH4 */
2547 3, /* DEVICE_SIS */
2548 6, /* DEVICE_ALI */
2549 4, /* DEVICE_NFORCE */
2550 };
2551 static struct ich_reg_info intel_regs[6] = {
2552 { ICH_PIINT, 0 },
2553 { ICH_POINT, 0x10 },
2554 { ICH_MCINT, 0x20 },
2555 { ICH_M2INT, 0x40 },
2556 { ICH_P2INT, 0x50 },
2557 { ICH_SPINT, 0x60 },
2558 };
2559 static struct ich_reg_info nforce_regs[4] = {
2560 { ICH_PIINT, 0 },
2561 { ICH_POINT, 0x10 },
2562 { ICH_MCINT, 0x20 },
2563 { ICH_NVSPINT, 0x70 },
2564 };
2565 static struct ich_reg_info ali_regs[6] = {
2566 { ALI_INT_PCMIN, 0x40 },
2567 { ALI_INT_PCMOUT, 0x50 },
2568 { ALI_INT_MICIN, 0x60 },
2569 { ALI_INT_CODECSPDIFOUT, 0x70 },
2570 { ALI_INT_SPDIFIN, 0xa0 },
2571 { ALI_INT_SPDIFOUT, 0xb0 },
2572 };
2573 struct ich_reg_info *tbl;
2574
2575 *r_intel8x0 = NULL;
2576
2577 if ((err = pci_enable_device(pci)) < 0)
2578 return err;
2579
2580 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2581 if (chip == NULL) {
2582 pci_disable_device(pci);
2583 return -ENOMEM;
2584 }
2585 spin_lock_init(&chip->reg_lock);
2586 chip->device_type = device_type;
2587 chip->card = card;
2588 chip->pci = pci;
2589 chip->irq = -1;
2590
2591 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2592 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2593 chip->fix_nocache = 1; /* enable workaround */
2594
2595 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2596 * Needs to return IRQ_HANDLED for unknown irqs.
2597 */
2598 if (device_type == DEVICE_NFORCE)
2599 chip->buggy_irq = 1;
2600
2601 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2602 kfree(chip);
2603 pci_disable_device(pci);
2604 return err;
2605 }
2606
2607 if (device_type == DEVICE_ALI) {
2608 /* ALI5455 has no ac97 region */
2609 chip->bmaddr = pci_resource_start(pci, 0);
2610 goto port_inited;
2611 }
2612
2613 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2614 chip->mmio = 1;
2615 chip->addr = pci_resource_start(pci, 2);
2616 chip->remap_addr = ioremap_nocache(chip->addr,
2617 pci_resource_len(pci, 2));
2618 if (chip->remap_addr == NULL) {
2619 snd_printk("AC'97 space ioremap problem\n");
2620 snd_intel8x0_free(chip);
2621 return -EIO;
2622 }
2623 } else {
2624 chip->addr = pci_resource_start(pci, 0);
2625 }
2626 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2627 chip->bm_mmio = 1;
2628 chip->bmaddr = pci_resource_start(pci, 3);
2629 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2630 pci_resource_len(pci, 3));
2631 if (chip->remap_bmaddr == NULL) {
2632 snd_printk("Controller space ioremap problem\n");
2633 snd_intel8x0_free(chip);
2634 return -EIO;
2635 }
2636 } else {
2637 chip->bmaddr = pci_resource_start(pci, 1);
2638 }
2639
2640 port_inited:
2641 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2642 snd_printk("unable to grab IRQ %d\n", pci->irq);
2643 snd_intel8x0_free(chip);
2644 return -EBUSY;
2645 }
2646 chip->irq = pci->irq;
2647 pci_set_master(pci);
2648 synchronize_irq(chip->irq);
2649
2650 chip->bdbars_count = bdbars[device_type];
2651
2652 /* initialize offsets */
2653 switch (device_type) {
2654 case DEVICE_NFORCE:
2655 tbl = nforce_regs;
2656 break;
2657 case DEVICE_ALI:
2658 tbl = ali_regs;
2659 break;
2660 default:
2661 tbl = intel_regs;
2662 break;
2663 }
2664 for (i = 0; i < chip->bdbars_count; i++) {
2665 ichdev = &chip->ichd[i];
2666 ichdev->ichd = i;
2667 ichdev->reg_offset = tbl[i].offset;
2668 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2669 if (device_type == DEVICE_SIS) {
2670 /* SiS 7012 swaps the registers */
2671 ichdev->roff_sr = ICH_REG_OFF_PICB;
2672 ichdev->roff_picb = ICH_REG_OFF_SR;
2673 } else {
2674 ichdev->roff_sr = ICH_REG_OFF_SR;
2675 ichdev->roff_picb = ICH_REG_OFF_PICB;
2676 }
2677 if (device_type == DEVICE_ALI)
2678 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2679 /* SIS7012 handles the pcm data in bytes, others are in samples */
2680 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2681 }
2682
2683 /* allocate buffer descriptor lists */
2684 /* the start of each lists must be aligned to 8 bytes */
2685 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2686 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2687 &chip->bdbars) < 0) {
2688 snd_intel8x0_free(chip);
2689 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2690 return -ENOMEM;
2691 }
2692 /* tables must be aligned to 8 bytes here, but the kernel pages
2693 are much bigger, so we don't care (on i386) */
2694 /* workaround for 440MX */
2695 if (chip->fix_nocache)
2696 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2697 int_sta_masks = 0;
2698 for (i = 0; i < chip->bdbars_count; i++) {
2699 ichdev = &chip->ichd[i];
2700 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2701 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2702 int_sta_masks |= ichdev->int_sta_mask;
2703 }
2704 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2705 chip->int_sta_mask = int_sta_masks;
2706
2707 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2708 snd_intel8x0_free(chip);
2709 return err;
2710 }
2711
2712 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2713
2714 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2715 snd_intel8x0_free(chip);
2716 return err;
2717 }
2718
2719 snd_card_set_dev(card, &pci->dev);
2720
2721 *r_intel8x0 = chip;
2722 return 0;
2723 }
2724
2725 static struct shortname_table {
2726 unsigned int id;
2727 const char *s;
2728 } shortnames[] __devinitdata = {
2729 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2730 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2731 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2732 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2733 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2734 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2735 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2736 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2737 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2738 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2739 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2740 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2741 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2742 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2743 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2744 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2745 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2746 { 0x003a, "NVidia MCP04" },
2747 { 0x746d, "AMD AMD8111" },
2748 { 0x7445, "AMD AMD768" },
2749 { 0x5455, "ALi M5455" },
2750 { 0, NULL },
2751 };
2752
2753 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2754 const struct pci_device_id *pci_id)
2755 {
2756 static int dev;
2757 snd_card_t *card;
2758 intel8x0_t *chip;
2759 int err;
2760 struct shortname_table *name;
2761
2762 if (dev >= SNDRV_CARDS)
2763 return -ENODEV;
2764 if (!enable[dev]) {
2765 dev++;
2766 return -ENOENT;
2767 }
2768
2769 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2770 if (card == NULL)
2771 return -ENOMEM;
2772
2773 switch (pci_id->driver_data) {
2774 case DEVICE_NFORCE:
2775 strcpy(card->driver, "NFORCE");
2776 break;
2777 case DEVICE_INTEL_ICH4:
2778 strcpy(card->driver, "ICH4");
2779 break;
2780 default:
2781 strcpy(card->driver, "ICH");
2782 break;
2783 }
2784
2785 strcpy(card->shortname, "Intel ICH");
2786 for (name = shortnames; name->id; name++) {
2787 if (pci->device == name->id) {
2788 strcpy(card->shortname, name->s);
2789 break;
2790 }
2791 }
2792
2793 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2794 snd_card_free(card);
2795 return err;
2796 }
2797 if (buggy_irq[dev])
2798 chip->buggy_irq = 1;
2799 if (xbox[dev])
2800 chip->xbox = 1;
2801
2802 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2803 snd_card_free(card);
2804 return err;
2805 }
2806 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2807 snd_card_free(card);
2808 return err;
2809 }
2810
2811 snd_intel8x0_proc_init(chip);
2812
2813 snprintf(card->longname, sizeof(card->longname),
2814 "%s with %s at %#lx, irq %i", card->shortname,
2815 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2816
2817 if (! ac97_clock[dev])
2818 intel8x0_measure_ac97_clock(chip);
2819
2820 if ((err = snd_card_register(card)) < 0) {
2821 snd_card_free(card);
2822 return err;
2823 }
2824 pci_set_drvdata(pci, card);
2825 dev++;
2826 return 0;
2827 }
2828
2829 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2830 {
2831 snd_card_free(pci_get_drvdata(pci));
2832 pci_set_drvdata(pci, NULL);
2833 }
2834
2835 static struct pci_driver driver = {
2836 .name = "Intel ICH",
2837 .id_table = snd_intel8x0_ids,
2838 .probe = snd_intel8x0_probe,
2839 .remove = __devexit_p(snd_intel8x0_remove),
2840 SND_PCI_PM_CALLBACKS
2841 };
2842
2843
2844 static int __init alsa_card_intel8x0_init(void)
2845 {
2846 return pci_module_init(&driver);
2847 }
2848
2849 static void __exit alsa_card_intel8x0_exit(void)
2850 {
2851 pci_unregister_driver(&driver);
2852 }
2853
2854 module_init(alsa_card_intel8x0_init)
2855 module_exit(alsa_card_intel8x0_exit)
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