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[mirror_ubuntu-bionic-kernel.git] / sound / pci / intel8x0.c
1 /*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/moduleparam.h>
36 #include <sound/core.h>
37 #include <sound/pcm.h>
38 #include <sound/ac97_codec.h>
39 #include <sound/info.h>
40 #include <sound/initval.h>
41 /* for 440MX workaround */
42 #include <asm/pgtable.h>
43 #include <asm/cacheflush.h>
44
45 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
46 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47 MODULE_LICENSE("GPL");
48 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49 "{Intel,82901AB-ICH0},"
50 "{Intel,82801BA-ICH2},"
51 "{Intel,82801CA-ICH3},"
52 "{Intel,82801DB-ICH4},"
53 "{Intel,ICH5},"
54 "{Intel,ICH6},"
55 "{Intel,ICH7},"
56 "{Intel,6300ESB},"
57 "{Intel,ESB2},"
58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
62 "{NVidia,nForce3 Audio},"
63 "{NVidia,MCP04},"
64 "{NVidia,MCP501},"
65 "{NVidia,CK804},"
66 "{NVidia,CK8},"
67 "{NVidia,CK8S},"
68 "{AMD,AMD768},"
69 "{AMD,AMD8111},"
70 "{ALI,M5455}}");
71
72 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
73 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
74 static int ac97_clock;
75 static char *ac97_quirk;
76 static int buggy_semaphore;
77 static int buggy_irq = -1; /* auto-check */
78 static int xbox;
79 static int spdif_aclink = -1;
80
81 module_param(index, int, 0444);
82 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
83 module_param(id, charp, 0444);
84 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
85 module_param(ac97_clock, int, 0444);
86 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
87 module_param(ac97_quirk, charp, 0444);
88 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
89 module_param(buggy_semaphore, bool, 0444);
90 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
91 module_param(buggy_irq, bool, 0444);
92 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
93 module_param(xbox, bool, 0444);
94 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
95 module_param(spdif_aclink, int, 0444);
96 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
97
98 /* just for backward compatibility */
99 static int enable;
100 module_param(enable, bool, 0444);
101 static int joystick;
102 module_param(joystick, int, 0444);
103
104 /*
105 * Direct registers
106 */
107 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
108
109 #define ICHREG(x) ICH_REG_##x
110
111 #define DEFINE_REGSET(name,base) \
112 enum { \
113 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
114 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
115 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
116 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
117 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
118 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
119 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
120 };
121
122 /* busmaster blocks */
123 DEFINE_REGSET(OFF, 0); /* offset */
124 DEFINE_REGSET(PI, 0x00); /* PCM in */
125 DEFINE_REGSET(PO, 0x10); /* PCM out */
126 DEFINE_REGSET(MC, 0x20); /* Mic in */
127
128 /* ICH4 busmaster blocks */
129 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
130 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
131 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
132
133 /* values for each busmaster block */
134
135 /* LVI */
136 #define ICH_REG_LVI_MASK 0x1f
137
138 /* SR */
139 #define ICH_FIFOE 0x10 /* FIFO error */
140 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
141 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
142 #define ICH_CELV 0x02 /* current equals last valid */
143 #define ICH_DCH 0x01 /* DMA controller halted */
144
145 /* PIV */
146 #define ICH_REG_PIV_MASK 0x1f /* mask */
147
148 /* CR */
149 #define ICH_IOCE 0x10 /* interrupt on completion enable */
150 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
151 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
152 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
153 #define ICH_STARTBM 0x01 /* start busmaster operation */
154
155
156 /* global block */
157 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
158 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
159 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
160 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
161 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
162 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
163 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
164 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
165 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
166 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
167 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
168 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
169 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
170 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
171 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
172 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
173 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
174 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
175 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
176 #define ICH_ACLINK 0x00000008 /* AClink shut off */
177 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
178 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
179 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
180 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
181 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
182 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
183 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
184 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
185 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
186 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
187 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
188 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
189 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
190 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
191 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
192 #define ICH_MD3 0x00020000 /* modem power down semaphore */
193 #define ICH_AD3 0x00010000 /* audio power down semaphore */
194 #define ICH_RCS 0x00008000 /* read completion status */
195 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
196 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
197 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
198 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
199 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
200 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
201 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
202 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
203 #define ICH_POINT 0x00000040 /* playback interrupt */
204 #define ICH_PIINT 0x00000020 /* capture interrupt */
205 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
206 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
207 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
208 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
209 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
210 #define ICH_CAS 0x01 /* codec access semaphore */
211 #define ICH_REG_SDM 0x80
212 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
213 #define ICH_DI2L_SHIFT 6
214 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
215 #define ICH_DI1L_SHIFT 4
216 #define ICH_SE 0x00000008 /* steer enable */
217 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
218
219 #define ICH_MAX_FRAGS 32 /* max hw frags */
220
221
222 /*
223 * registers for Ali5455
224 */
225
226 /* ALi 5455 busmaster blocks */
227 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
228 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
229 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
230 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
231 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
232 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
233 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
234 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
235 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
236 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
237 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
238
239 enum {
240 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
241 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
242 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
243 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
244 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
245 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
246 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
247 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
248 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
249 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
250 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
251 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
252 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
253 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
254 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
255 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
256 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
257 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
258 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
259 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
260 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
261 };
262
263 #define ALI_CAS_SEM_BUSY 0x80000000
264 #define ALI_CPR_ADDR_SECONDARY 0x100
265 #define ALI_CPR_ADDR_READ 0x80
266 #define ALI_CSPSR_CODEC_READY 0x08
267 #define ALI_CSPSR_READ_OK 0x02
268 #define ALI_CSPSR_WRITE_OK 0x01
269
270 /* interrupts for the whole chip by interrupt status register finish */
271
272 #define ALI_INT_MICIN2 (1<<26)
273 #define ALI_INT_PCMIN2 (1<<25)
274 #define ALI_INT_I2SIN (1<<24)
275 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
276 #define ALI_INT_SPDIFIN (1<<22)
277 #define ALI_INT_LFEOUT (1<<21)
278 #define ALI_INT_CENTEROUT (1<<20)
279 #define ALI_INT_CODECSPDIFOUT (1<<19)
280 #define ALI_INT_MICIN (1<<18)
281 #define ALI_INT_PCMOUT (1<<17)
282 #define ALI_INT_PCMIN (1<<16)
283 #define ALI_INT_CPRAIS (1<<7) /* command port available */
284 #define ALI_INT_SPRAIS (1<<5) /* status port available */
285 #define ALI_INT_GPIO (1<<1)
286 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
287 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
288
289 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
290 #define ICH_ALI_SC_AC97_DBL (1<<30)
291 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
292 #define ICH_ALI_SC_IN_BITS (3<<18)
293 #define ICH_ALI_SC_OUT_BITS (3<<16)
294 #define ICH_ALI_SC_6CH_CFG (3<<14)
295 #define ICH_ALI_SC_PCM_4 (1<<8)
296 #define ICH_ALI_SC_PCM_6 (2<<8)
297 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
298
299 #define ICH_ALI_SS_SEC_ID (3<<5)
300 #define ICH_ALI_SS_PRI_ID (3<<3)
301
302 #define ICH_ALI_IF_AC97SP (1<<21)
303 #define ICH_ALI_IF_MC (1<<20)
304 #define ICH_ALI_IF_PI (1<<19)
305 #define ICH_ALI_IF_MC2 (1<<18)
306 #define ICH_ALI_IF_PI2 (1<<17)
307 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
308 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
309 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
310 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
311 #define ICH_ALI_IF_PO_SPDF (1<<3)
312 #define ICH_ALI_IF_PO (1<<1)
313
314 /*
315 *
316 */
317
318 enum {
319 ICHD_PCMIN,
320 ICHD_PCMOUT,
321 ICHD_MIC,
322 ICHD_MIC2,
323 ICHD_PCM2IN,
324 ICHD_SPBAR,
325 ICHD_LAST = ICHD_SPBAR
326 };
327 enum {
328 NVD_PCMIN,
329 NVD_PCMOUT,
330 NVD_MIC,
331 NVD_SPBAR,
332 NVD_LAST = NVD_SPBAR
333 };
334 enum {
335 ALID_PCMIN,
336 ALID_PCMOUT,
337 ALID_MIC,
338 ALID_AC97SPDIFOUT,
339 ALID_SPDIFIN,
340 ALID_SPDIFOUT,
341 ALID_LAST = ALID_SPDIFOUT
342 };
343
344 #define get_ichdev(substream) (substream->runtime->private_data)
345
346 struct ichdev {
347 unsigned int ichd; /* ich device number */
348 unsigned long reg_offset; /* offset to bmaddr */
349 u32 *bdbar; /* CPU address (32bit) */
350 unsigned int bdbar_addr; /* PCI bus address (32bit) */
351 struct snd_pcm_substream *substream;
352 unsigned int physbuf; /* physical address (32bit) */
353 unsigned int size;
354 unsigned int fragsize;
355 unsigned int fragsize1;
356 unsigned int position;
357 unsigned int pos_shift;
358 int frags;
359 int lvi;
360 int lvi_frag;
361 int civ;
362 int ack;
363 int ack_reload;
364 unsigned int ack_bit;
365 unsigned int roff_sr;
366 unsigned int roff_picb;
367 unsigned int int_sta_mask; /* interrupt status mask */
368 unsigned int ali_slot; /* ALI DMA slot */
369 struct ac97_pcm *pcm;
370 int pcm_open_flag;
371 unsigned int page_attr_changed: 1;
372 unsigned int suspended: 1;
373 };
374
375 struct intel8x0 {
376 unsigned int device_type;
377
378 int irq;
379
380 void __iomem *addr;
381 void __iomem *bmaddr;
382
383 struct pci_dev *pci;
384 struct snd_card *card;
385
386 int pcm_devs;
387 struct snd_pcm *pcm[6];
388 struct ichdev ichd[6];
389
390 unsigned multi4: 1,
391 multi6: 1,
392 multi8 :1,
393 dra: 1,
394 smp20bit: 1;
395 unsigned in_ac97_init: 1,
396 in_sdin_init: 1;
397 unsigned in_measurement: 1; /* during ac97 clock measurement */
398 unsigned fix_nocache: 1; /* workaround for 440MX */
399 unsigned buggy_irq: 1; /* workaround for buggy mobos */
400 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
401 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
402
403 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
404 unsigned int sdm_saved; /* SDM reg value */
405
406 struct snd_ac97_bus *ac97_bus;
407 struct snd_ac97 *ac97[3];
408 unsigned int ac97_sdin[3];
409 unsigned int max_codecs, ncodecs;
410 unsigned int *codec_bit;
411 unsigned int codec_isr_bits;
412 unsigned int codec_ready_bits;
413
414 spinlock_t reg_lock;
415
416 u32 bdbars_count;
417 struct snd_dma_buffer bdbars;
418 u32 int_sta_reg; /* interrupt status register */
419 u32 int_sta_mask; /* interrupt status mask */
420 };
421
422 static struct pci_device_id snd_intel8x0_ids[] = {
423 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
424 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
425 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
426 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
427 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
428 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
429 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
430 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
431 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
432 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
433 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
434 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
435 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
436 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
437 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
438 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
439 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
440 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
441 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
442 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
443 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
444 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
445 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
446 { 0, }
447 };
448
449 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
450
451 /*
452 * Lowlevel I/O - busmaster
453 */
454
455 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
456 {
457 return ioread8(chip->bmaddr + offset);
458 }
459
460 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
461 {
462 return ioread16(chip->bmaddr + offset);
463 }
464
465 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
466 {
467 return ioread32(chip->bmaddr + offset);
468 }
469
470 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
471 {
472 iowrite8(val, chip->bmaddr + offset);
473 }
474
475 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
476 {
477 iowrite16(val, chip->bmaddr + offset);
478 }
479
480 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
481 {
482 iowrite32(val, chip->bmaddr + offset);
483 }
484
485 /*
486 * Lowlevel I/O - AC'97 registers
487 */
488
489 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
490 {
491 return ioread16(chip->addr + offset);
492 }
493
494 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
495 {
496 iowrite16(val, chip->addr + offset);
497 }
498
499 /*
500 * Basic I/O
501 */
502
503 /*
504 * access to AC97 codec via normal i/o (for ICH and SIS7012)
505 */
506
507 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
508 {
509 int time;
510
511 if (codec > 2)
512 return -EIO;
513 if (chip->in_sdin_init) {
514 /* we don't know the ready bit assignment at the moment */
515 /* so we check any */
516 codec = chip->codec_isr_bits;
517 } else {
518 codec = chip->codec_bit[chip->ac97_sdin[codec]];
519 }
520
521 /* codec ready ? */
522 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
523 return -EIO;
524
525 if (chip->buggy_semaphore)
526 return 0; /* just ignore ... */
527
528 /* Anyone holding a semaphore for 1 msec should be shot... */
529 time = 100;
530 do {
531 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
532 return 0;
533 udelay(10);
534 } while (time--);
535
536 /* access to some forbidden (non existant) ac97 registers will not
537 * reset the semaphore. So even if you don't get the semaphore, still
538 * continue the access. We don't need the semaphore anyway. */
539 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
540 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
541 iagetword(chip, 0); /* clear semaphore flag */
542 /* I don't care about the semaphore */
543 return -EBUSY;
544 }
545
546 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
547 unsigned short reg,
548 unsigned short val)
549 {
550 struct intel8x0 *chip = ac97->private_data;
551
552 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
553 if (! chip->in_ac97_init)
554 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
555 }
556 iaputword(chip, reg + ac97->num * 0x80, val);
557 }
558
559 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
560 unsigned short reg)
561 {
562 struct intel8x0 *chip = ac97->private_data;
563 unsigned short res;
564 unsigned int tmp;
565
566 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
567 if (! chip->in_ac97_init)
568 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
569 res = 0xffff;
570 } else {
571 res = iagetword(chip, reg + ac97->num * 0x80);
572 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
573 /* reset RCS and preserve other R/WC bits */
574 iputdword(chip, ICHREG(GLOB_STA), tmp &
575 ~(chip->codec_ready_bits | ICH_GSCI));
576 if (! chip->in_ac97_init)
577 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
578 res = 0xffff;
579 }
580 }
581 return res;
582 }
583
584 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
585 unsigned int codec)
586 {
587 unsigned int tmp;
588
589 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
590 iagetword(chip, codec * 0x80);
591 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
592 /* reset RCS and preserve other R/WC bits */
593 iputdword(chip, ICHREG(GLOB_STA), tmp &
594 ~(chip->codec_ready_bits | ICH_GSCI));
595 }
596 }
597 }
598
599 /*
600 * access to AC97 for Ali5455
601 */
602 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
603 {
604 int count = 0;
605 for (count = 0; count < 0x7f; count++) {
606 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
607 if (val & mask)
608 return 0;
609 }
610 if (! chip->in_ac97_init)
611 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
612 return -EBUSY;
613 }
614
615 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
616 {
617 int time = 100;
618 if (chip->buggy_semaphore)
619 return 0; /* just ignore ... */
620 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
621 udelay(1);
622 if (! time && ! chip->in_ac97_init)
623 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
624 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
625 }
626
627 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
628 {
629 struct intel8x0 *chip = ac97->private_data;
630 unsigned short data = 0xffff;
631
632 if (snd_intel8x0_ali_codec_semaphore(chip))
633 goto __err;
634 reg |= ALI_CPR_ADDR_READ;
635 if (ac97->num)
636 reg |= ALI_CPR_ADDR_SECONDARY;
637 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
638 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
639 goto __err;
640 data = igetword(chip, ICHREG(ALI_SPR));
641 __err:
642 return data;
643 }
644
645 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
646 unsigned short val)
647 {
648 struct intel8x0 *chip = ac97->private_data;
649
650 if (snd_intel8x0_ali_codec_semaphore(chip))
651 return;
652 iputword(chip, ICHREG(ALI_CPR), val);
653 if (ac97->num)
654 reg |= ALI_CPR_ADDR_SECONDARY;
655 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
656 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
657 }
658
659
660 /*
661 * DMA I/O
662 */
663 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
664 {
665 int idx;
666 u32 *bdbar = ichdev->bdbar;
667 unsigned long port = ichdev->reg_offset;
668
669 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
670 if (ichdev->size == ichdev->fragsize) {
671 ichdev->ack_reload = ichdev->ack = 2;
672 ichdev->fragsize1 = ichdev->fragsize >> 1;
673 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
674 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
675 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
676 ichdev->fragsize1 >> ichdev->pos_shift);
677 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
678 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
679 ichdev->fragsize1 >> ichdev->pos_shift);
680 }
681 ichdev->frags = 2;
682 } else {
683 ichdev->ack_reload = ichdev->ack = 1;
684 ichdev->fragsize1 = ichdev->fragsize;
685 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
686 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
687 (((idx >> 1) * ichdev->fragsize) %
688 ichdev->size));
689 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690 ichdev->fragsize >> ichdev->pos_shift);
691 #if 0
692 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
693 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
694 #endif
695 }
696 ichdev->frags = ichdev->size / ichdev->fragsize;
697 }
698 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
699 ichdev->civ = 0;
700 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
701 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
702 ichdev->position = 0;
703 #if 0
704 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
705 "period_size1 = 0x%x\n",
706 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
707 ichdev->fragsize1);
708 #endif
709 /* clear interrupts */
710 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
711 }
712
713 #ifdef __i386__
714 /*
715 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
716 * which aborts PCI busmaster for audio transfer. A workaround is to set
717 * the pages as non-cached. For details, see the errata in
718 * http://www.intel.com/design/chipsets/specupdt/245051.htm
719 */
720 static void fill_nocache(void *buf, int size, int nocache)
721 {
722 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
723 if (nocache)
724 set_pages_uc(virt_to_page(buf), size);
725 else
726 set_pages_wb(virt_to_page(buf), size);
727 }
728 #else
729 #define fill_nocache(buf, size, nocache) do { ; } while (0)
730 #endif
731
732 /*
733 * Interrupt handler
734 */
735
736 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
737 {
738 unsigned long port = ichdev->reg_offset;
739 unsigned long flags;
740 int status, civ, i, step;
741 int ack = 0;
742
743 spin_lock_irqsave(&chip->reg_lock, flags);
744 status = igetbyte(chip, port + ichdev->roff_sr);
745 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
746 if (!(status & ICH_BCIS)) {
747 step = 0;
748 } else if (civ == ichdev->civ) {
749 // snd_printd("civ same %d\n", civ);
750 step = 1;
751 ichdev->civ++;
752 ichdev->civ &= ICH_REG_LVI_MASK;
753 } else {
754 step = civ - ichdev->civ;
755 if (step < 0)
756 step += ICH_REG_LVI_MASK + 1;
757 // if (step != 1)
758 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
759 ichdev->civ = civ;
760 }
761
762 ichdev->position += step * ichdev->fragsize1;
763 if (! chip->in_measurement)
764 ichdev->position %= ichdev->size;
765 ichdev->lvi += step;
766 ichdev->lvi &= ICH_REG_LVI_MASK;
767 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
768 for (i = 0; i < step; i++) {
769 ichdev->lvi_frag++;
770 ichdev->lvi_frag %= ichdev->frags;
771 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
772 #if 0
773 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
774 "all = 0x%x, 0x%x\n",
775 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
776 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
777 inl(port + 4), inb(port + ICH_REG_OFF_CR));
778 #endif
779 if (--ichdev->ack == 0) {
780 ichdev->ack = ichdev->ack_reload;
781 ack = 1;
782 }
783 }
784 spin_unlock_irqrestore(&chip->reg_lock, flags);
785 if (ack && ichdev->substream) {
786 snd_pcm_period_elapsed(ichdev->substream);
787 }
788 iputbyte(chip, port + ichdev->roff_sr,
789 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
790 }
791
792 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
793 {
794 struct intel8x0 *chip = dev_id;
795 struct ichdev *ichdev;
796 unsigned int status;
797 unsigned int i;
798
799 status = igetdword(chip, chip->int_sta_reg);
800 if (status == 0xffffffff) /* we are not yet resumed */
801 return IRQ_NONE;
802
803 if ((status & chip->int_sta_mask) == 0) {
804 if (status) {
805 /* ack */
806 iputdword(chip, chip->int_sta_reg, status);
807 if (! chip->buggy_irq)
808 status = 0;
809 }
810 return IRQ_RETVAL(status);
811 }
812
813 for (i = 0; i < chip->bdbars_count; i++) {
814 ichdev = &chip->ichd[i];
815 if (status & ichdev->int_sta_mask)
816 snd_intel8x0_update(chip, ichdev);
817 }
818
819 /* ack them */
820 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
821
822 return IRQ_HANDLED;
823 }
824
825 /*
826 * PCM part
827 */
828
829 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
830 {
831 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
832 struct ichdev *ichdev = get_ichdev(substream);
833 unsigned char val = 0;
834 unsigned long port = ichdev->reg_offset;
835
836 switch (cmd) {
837 case SNDRV_PCM_TRIGGER_RESUME:
838 ichdev->suspended = 0;
839 /* fallthru */
840 case SNDRV_PCM_TRIGGER_START:
841 val = ICH_IOCE | ICH_STARTBM;
842 break;
843 case SNDRV_PCM_TRIGGER_SUSPEND:
844 ichdev->suspended = 1;
845 /* fallthru */
846 case SNDRV_PCM_TRIGGER_STOP:
847 val = 0;
848 break;
849 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
850 val = ICH_IOCE;
851 break;
852 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
853 val = ICH_IOCE | ICH_STARTBM;
854 break;
855 default:
856 return -EINVAL;
857 }
858 iputbyte(chip, port + ICH_REG_OFF_CR, val);
859 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
860 /* wait until DMA stopped */
861 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
862 /* reset whole DMA things */
863 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
864 }
865 return 0;
866 }
867
868 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
869 {
870 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
871 struct ichdev *ichdev = get_ichdev(substream);
872 unsigned long port = ichdev->reg_offset;
873 static int fiforeg[] = {
874 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
875 };
876 unsigned int val, fifo;
877
878 val = igetdword(chip, ICHREG(ALI_DMACR));
879 switch (cmd) {
880 case SNDRV_PCM_TRIGGER_RESUME:
881 ichdev->suspended = 0;
882 /* fallthru */
883 case SNDRV_PCM_TRIGGER_START:
884 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
885 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
886 /* clear FIFO for synchronization of channels */
887 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
888 fifo &= ~(0xff << (ichdev->ali_slot % 4));
889 fifo |= 0x83 << (ichdev->ali_slot % 4);
890 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
891 }
892 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
893 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
894 /* start DMA */
895 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
896 break;
897 case SNDRV_PCM_TRIGGER_SUSPEND:
898 ichdev->suspended = 1;
899 /* fallthru */
900 case SNDRV_PCM_TRIGGER_STOP:
901 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
902 /* pause */
903 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
904 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
905 while (igetbyte(chip, port + ICH_REG_OFF_CR))
906 ;
907 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
908 break;
909 /* reset whole DMA things */
910 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
911 /* clear interrupts */
912 iputbyte(chip, port + ICH_REG_OFF_SR,
913 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
914 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
915 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
916 break;
917 default:
918 return -EINVAL;
919 }
920 return 0;
921 }
922
923 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
924 struct snd_pcm_hw_params *hw_params)
925 {
926 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
927 struct ichdev *ichdev = get_ichdev(substream);
928 struct snd_pcm_runtime *runtime = substream->runtime;
929 int dbl = params_rate(hw_params) > 48000;
930 int err;
931
932 if (chip->fix_nocache && ichdev->page_attr_changed) {
933 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
934 ichdev->page_attr_changed = 0;
935 }
936 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
937 if (err < 0)
938 return err;
939 if (chip->fix_nocache) {
940 if (runtime->dma_area && ! ichdev->page_attr_changed) {
941 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
942 ichdev->page_attr_changed = 1;
943 }
944 }
945 if (ichdev->pcm_open_flag) {
946 snd_ac97_pcm_close(ichdev->pcm);
947 ichdev->pcm_open_flag = 0;
948 }
949 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
950 params_channels(hw_params),
951 ichdev->pcm->r[dbl].slots);
952 if (err >= 0) {
953 ichdev->pcm_open_flag = 1;
954 /* Force SPDIF setting */
955 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
956 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
957 params_rate(hw_params));
958 }
959 return err;
960 }
961
962 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
963 {
964 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
965 struct ichdev *ichdev = get_ichdev(substream);
966
967 if (ichdev->pcm_open_flag) {
968 snd_ac97_pcm_close(ichdev->pcm);
969 ichdev->pcm_open_flag = 0;
970 }
971 if (chip->fix_nocache && ichdev->page_attr_changed) {
972 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
973 ichdev->page_attr_changed = 0;
974 }
975 return snd_pcm_lib_free_pages(substream);
976 }
977
978 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
979 struct snd_pcm_runtime *runtime)
980 {
981 unsigned int cnt;
982 int dbl = runtime->rate > 48000;
983
984 spin_lock_irq(&chip->reg_lock);
985 switch (chip->device_type) {
986 case DEVICE_ALI:
987 cnt = igetdword(chip, ICHREG(ALI_SCR));
988 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
989 if (runtime->channels == 4 || dbl)
990 cnt |= ICH_ALI_SC_PCM_4;
991 else if (runtime->channels == 6)
992 cnt |= ICH_ALI_SC_PCM_6;
993 iputdword(chip, ICHREG(ALI_SCR), cnt);
994 break;
995 case DEVICE_SIS:
996 cnt = igetdword(chip, ICHREG(GLOB_CNT));
997 cnt &= ~ICH_SIS_PCM_246_MASK;
998 if (runtime->channels == 4 || dbl)
999 cnt |= ICH_SIS_PCM_4;
1000 else if (runtime->channels == 6)
1001 cnt |= ICH_SIS_PCM_6;
1002 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1003 break;
1004 default:
1005 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1006 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1007 if (runtime->channels == 4 || dbl)
1008 cnt |= ICH_PCM_4;
1009 else if (runtime->channels == 6)
1010 cnt |= ICH_PCM_6;
1011 else if (runtime->channels == 8)
1012 cnt |= ICH_PCM_8;
1013 if (chip->device_type == DEVICE_NFORCE) {
1014 /* reset to 2ch once to keep the 6 channel data in alignment,
1015 * to start from Front Left always
1016 */
1017 if (cnt & ICH_PCM_246_MASK) {
1018 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1019 spin_unlock_irq(&chip->reg_lock);
1020 msleep(50); /* grrr... */
1021 spin_lock_irq(&chip->reg_lock);
1022 }
1023 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1024 if (runtime->sample_bits > 16)
1025 cnt |= ICH_PCM_20BIT;
1026 }
1027 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1028 break;
1029 }
1030 spin_unlock_irq(&chip->reg_lock);
1031 }
1032
1033 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1034 {
1035 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1036 struct snd_pcm_runtime *runtime = substream->runtime;
1037 struct ichdev *ichdev = get_ichdev(substream);
1038
1039 ichdev->physbuf = runtime->dma_addr;
1040 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1041 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1042 if (ichdev->ichd == ICHD_PCMOUT) {
1043 snd_intel8x0_setup_pcm_out(chip, runtime);
1044 if (chip->device_type == DEVICE_INTEL_ICH4)
1045 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1046 }
1047 snd_intel8x0_setup_periods(chip, ichdev);
1048 return 0;
1049 }
1050
1051 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1052 {
1053 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1054 struct ichdev *ichdev = get_ichdev(substream);
1055 size_t ptr1, ptr;
1056 int civ, timeout = 100;
1057 unsigned int position;
1058
1059 spin_lock(&chip->reg_lock);
1060 do {
1061 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1062 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1063 position = ichdev->position;
1064 if (ptr1 == 0) {
1065 udelay(10);
1066 continue;
1067 }
1068 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1069 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1070 break;
1071 } while (timeout--);
1072 ptr1 <<= ichdev->pos_shift;
1073 ptr = ichdev->fragsize1 - ptr1;
1074 ptr += position;
1075 spin_unlock(&chip->reg_lock);
1076 if (ptr >= ichdev->size)
1077 return 0;
1078 return bytes_to_frames(substream->runtime, ptr);
1079 }
1080
1081 static struct snd_pcm_hardware snd_intel8x0_stream =
1082 {
1083 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1084 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1085 SNDRV_PCM_INFO_MMAP_VALID |
1086 SNDRV_PCM_INFO_PAUSE |
1087 SNDRV_PCM_INFO_RESUME),
1088 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1089 .rates = SNDRV_PCM_RATE_48000,
1090 .rate_min = 48000,
1091 .rate_max = 48000,
1092 .channels_min = 2,
1093 .channels_max = 2,
1094 .buffer_bytes_max = 128 * 1024,
1095 .period_bytes_min = 32,
1096 .period_bytes_max = 128 * 1024,
1097 .periods_min = 1,
1098 .periods_max = 1024,
1099 .fifo_size = 0,
1100 };
1101
1102 static unsigned int channels4[] = {
1103 2, 4,
1104 };
1105
1106 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1107 .count = ARRAY_SIZE(channels4),
1108 .list = channels4,
1109 .mask = 0,
1110 };
1111
1112 static unsigned int channels6[] = {
1113 2, 4, 6,
1114 };
1115
1116 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1117 .count = ARRAY_SIZE(channels6),
1118 .list = channels6,
1119 .mask = 0,
1120 };
1121
1122 static unsigned int channels8[] = {
1123 2, 4, 6, 8,
1124 };
1125
1126 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1127 .count = ARRAY_SIZE(channels8),
1128 .list = channels8,
1129 .mask = 0,
1130 };
1131
1132 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1133 {
1134 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1135 struct snd_pcm_runtime *runtime = substream->runtime;
1136 int err;
1137
1138 ichdev->substream = substream;
1139 runtime->hw = snd_intel8x0_stream;
1140 runtime->hw.rates = ichdev->pcm->rates;
1141 snd_pcm_limit_hw_rates(runtime);
1142 if (chip->device_type == DEVICE_SIS) {
1143 runtime->hw.buffer_bytes_max = 64*1024;
1144 runtime->hw.period_bytes_max = 64*1024;
1145 }
1146 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1147 return err;
1148 runtime->private_data = ichdev;
1149 return 0;
1150 }
1151
1152 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1153 {
1154 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1155 struct snd_pcm_runtime *runtime = substream->runtime;
1156 int err;
1157
1158 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1159 if (err < 0)
1160 return err;
1161
1162 if (chip->multi8) {
1163 runtime->hw.channels_max = 8;
1164 snd_pcm_hw_constraint_list(runtime, 0,
1165 SNDRV_PCM_HW_PARAM_CHANNELS,
1166 &hw_constraints_channels8);
1167 } else if (chip->multi6) {
1168 runtime->hw.channels_max = 6;
1169 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1170 &hw_constraints_channels6);
1171 } else if (chip->multi4) {
1172 runtime->hw.channels_max = 4;
1173 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1174 &hw_constraints_channels4);
1175 }
1176 if (chip->dra) {
1177 snd_ac97_pcm_double_rate_rules(runtime);
1178 }
1179 if (chip->smp20bit) {
1180 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1181 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1182 }
1183 return 0;
1184 }
1185
1186 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1187 {
1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189
1190 chip->ichd[ICHD_PCMOUT].substream = NULL;
1191 return 0;
1192 }
1193
1194 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1195 {
1196 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1197
1198 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1199 }
1200
1201 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1202 {
1203 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1204
1205 chip->ichd[ICHD_PCMIN].substream = NULL;
1206 return 0;
1207 }
1208
1209 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1210 {
1211 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1212
1213 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1214 }
1215
1216 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1217 {
1218 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219
1220 chip->ichd[ICHD_MIC].substream = NULL;
1221 return 0;
1222 }
1223
1224 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1225 {
1226 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227
1228 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1229 }
1230
1231 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1232 {
1233 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1234
1235 chip->ichd[ICHD_MIC2].substream = NULL;
1236 return 0;
1237 }
1238
1239 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1240 {
1241 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1242
1243 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1244 }
1245
1246 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1247 {
1248 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1249
1250 chip->ichd[ICHD_PCM2IN].substream = NULL;
1251 return 0;
1252 }
1253
1254 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1255 {
1256 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1257 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1258
1259 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1260 }
1261
1262 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1263 {
1264 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1265 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1266
1267 chip->ichd[idx].substream = NULL;
1268 return 0;
1269 }
1270
1271 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1272 {
1273 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1274 unsigned int val;
1275
1276 spin_lock_irq(&chip->reg_lock);
1277 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1278 val |= ICH_ALI_IF_AC97SP;
1279 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1280 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1281 spin_unlock_irq(&chip->reg_lock);
1282
1283 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1284 }
1285
1286 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1287 {
1288 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1289 unsigned int val;
1290
1291 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1292 spin_lock_irq(&chip->reg_lock);
1293 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1294 val &= ~ICH_ALI_IF_AC97SP;
1295 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1296 spin_unlock_irq(&chip->reg_lock);
1297
1298 return 0;
1299 }
1300
1301 #if 0 // NYI
1302 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1303 {
1304 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1305
1306 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1307 }
1308
1309 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1310 {
1311 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1312
1313 chip->ichd[ALID_SPDIFIN].substream = NULL;
1314 return 0;
1315 }
1316
1317 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1318 {
1319 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1320
1321 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1322 }
1323
1324 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1325 {
1326 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1327
1328 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1329 return 0;
1330 }
1331 #endif
1332
1333 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1334 .open = snd_intel8x0_playback_open,
1335 .close = snd_intel8x0_playback_close,
1336 .ioctl = snd_pcm_lib_ioctl,
1337 .hw_params = snd_intel8x0_hw_params,
1338 .hw_free = snd_intel8x0_hw_free,
1339 .prepare = snd_intel8x0_pcm_prepare,
1340 .trigger = snd_intel8x0_pcm_trigger,
1341 .pointer = snd_intel8x0_pcm_pointer,
1342 };
1343
1344 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1345 .open = snd_intel8x0_capture_open,
1346 .close = snd_intel8x0_capture_close,
1347 .ioctl = snd_pcm_lib_ioctl,
1348 .hw_params = snd_intel8x0_hw_params,
1349 .hw_free = snd_intel8x0_hw_free,
1350 .prepare = snd_intel8x0_pcm_prepare,
1351 .trigger = snd_intel8x0_pcm_trigger,
1352 .pointer = snd_intel8x0_pcm_pointer,
1353 };
1354
1355 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1356 .open = snd_intel8x0_mic_open,
1357 .close = snd_intel8x0_mic_close,
1358 .ioctl = snd_pcm_lib_ioctl,
1359 .hw_params = snd_intel8x0_hw_params,
1360 .hw_free = snd_intel8x0_hw_free,
1361 .prepare = snd_intel8x0_pcm_prepare,
1362 .trigger = snd_intel8x0_pcm_trigger,
1363 .pointer = snd_intel8x0_pcm_pointer,
1364 };
1365
1366 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1367 .open = snd_intel8x0_mic2_open,
1368 .close = snd_intel8x0_mic2_close,
1369 .ioctl = snd_pcm_lib_ioctl,
1370 .hw_params = snd_intel8x0_hw_params,
1371 .hw_free = snd_intel8x0_hw_free,
1372 .prepare = snd_intel8x0_pcm_prepare,
1373 .trigger = snd_intel8x0_pcm_trigger,
1374 .pointer = snd_intel8x0_pcm_pointer,
1375 };
1376
1377 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1378 .open = snd_intel8x0_capture2_open,
1379 .close = snd_intel8x0_capture2_close,
1380 .ioctl = snd_pcm_lib_ioctl,
1381 .hw_params = snd_intel8x0_hw_params,
1382 .hw_free = snd_intel8x0_hw_free,
1383 .prepare = snd_intel8x0_pcm_prepare,
1384 .trigger = snd_intel8x0_pcm_trigger,
1385 .pointer = snd_intel8x0_pcm_pointer,
1386 };
1387
1388 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1389 .open = snd_intel8x0_spdif_open,
1390 .close = snd_intel8x0_spdif_close,
1391 .ioctl = snd_pcm_lib_ioctl,
1392 .hw_params = snd_intel8x0_hw_params,
1393 .hw_free = snd_intel8x0_hw_free,
1394 .prepare = snd_intel8x0_pcm_prepare,
1395 .trigger = snd_intel8x0_pcm_trigger,
1396 .pointer = snd_intel8x0_pcm_pointer,
1397 };
1398
1399 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1400 .open = snd_intel8x0_playback_open,
1401 .close = snd_intel8x0_playback_close,
1402 .ioctl = snd_pcm_lib_ioctl,
1403 .hw_params = snd_intel8x0_hw_params,
1404 .hw_free = snd_intel8x0_hw_free,
1405 .prepare = snd_intel8x0_pcm_prepare,
1406 .trigger = snd_intel8x0_ali_trigger,
1407 .pointer = snd_intel8x0_pcm_pointer,
1408 };
1409
1410 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1411 .open = snd_intel8x0_capture_open,
1412 .close = snd_intel8x0_capture_close,
1413 .ioctl = snd_pcm_lib_ioctl,
1414 .hw_params = snd_intel8x0_hw_params,
1415 .hw_free = snd_intel8x0_hw_free,
1416 .prepare = snd_intel8x0_pcm_prepare,
1417 .trigger = snd_intel8x0_ali_trigger,
1418 .pointer = snd_intel8x0_pcm_pointer,
1419 };
1420
1421 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1422 .open = snd_intel8x0_mic_open,
1423 .close = snd_intel8x0_mic_close,
1424 .ioctl = snd_pcm_lib_ioctl,
1425 .hw_params = snd_intel8x0_hw_params,
1426 .hw_free = snd_intel8x0_hw_free,
1427 .prepare = snd_intel8x0_pcm_prepare,
1428 .trigger = snd_intel8x0_ali_trigger,
1429 .pointer = snd_intel8x0_pcm_pointer,
1430 };
1431
1432 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1433 .open = snd_intel8x0_ali_ac97spdifout_open,
1434 .close = snd_intel8x0_ali_ac97spdifout_close,
1435 .ioctl = snd_pcm_lib_ioctl,
1436 .hw_params = snd_intel8x0_hw_params,
1437 .hw_free = snd_intel8x0_hw_free,
1438 .prepare = snd_intel8x0_pcm_prepare,
1439 .trigger = snd_intel8x0_ali_trigger,
1440 .pointer = snd_intel8x0_pcm_pointer,
1441 };
1442
1443 #if 0 // NYI
1444 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1445 .open = snd_intel8x0_ali_spdifin_open,
1446 .close = snd_intel8x0_ali_spdifin_close,
1447 .ioctl = snd_pcm_lib_ioctl,
1448 .hw_params = snd_intel8x0_hw_params,
1449 .hw_free = snd_intel8x0_hw_free,
1450 .prepare = snd_intel8x0_pcm_prepare,
1451 .trigger = snd_intel8x0_pcm_trigger,
1452 .pointer = snd_intel8x0_pcm_pointer,
1453 };
1454
1455 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1456 .open = snd_intel8x0_ali_spdifout_open,
1457 .close = snd_intel8x0_ali_spdifout_close,
1458 .ioctl = snd_pcm_lib_ioctl,
1459 .hw_params = snd_intel8x0_hw_params,
1460 .hw_free = snd_intel8x0_hw_free,
1461 .prepare = snd_intel8x0_pcm_prepare,
1462 .trigger = snd_intel8x0_pcm_trigger,
1463 .pointer = snd_intel8x0_pcm_pointer,
1464 };
1465 #endif // NYI
1466
1467 struct ich_pcm_table {
1468 char *suffix;
1469 struct snd_pcm_ops *playback_ops;
1470 struct snd_pcm_ops *capture_ops;
1471 size_t prealloc_size;
1472 size_t prealloc_max_size;
1473 int ac97_idx;
1474 };
1475
1476 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1477 struct ich_pcm_table *rec)
1478 {
1479 struct snd_pcm *pcm;
1480 int err;
1481 char name[32];
1482
1483 if (rec->suffix)
1484 sprintf(name, "Intel ICH - %s", rec->suffix);
1485 else
1486 strcpy(name, "Intel ICH");
1487 err = snd_pcm_new(chip->card, name, device,
1488 rec->playback_ops ? 1 : 0,
1489 rec->capture_ops ? 1 : 0, &pcm);
1490 if (err < 0)
1491 return err;
1492
1493 if (rec->playback_ops)
1494 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1495 if (rec->capture_ops)
1496 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1497
1498 pcm->private_data = chip;
1499 pcm->info_flags = 0;
1500 if (rec->suffix)
1501 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1502 else
1503 strcpy(pcm->name, chip->card->shortname);
1504 chip->pcm[device] = pcm;
1505
1506 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1507 snd_dma_pci_data(chip->pci),
1508 rec->prealloc_size, rec->prealloc_max_size);
1509
1510 return 0;
1511 }
1512
1513 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1514 {
1515 .playback_ops = &snd_intel8x0_playback_ops,
1516 .capture_ops = &snd_intel8x0_capture_ops,
1517 .prealloc_size = 64 * 1024,
1518 .prealloc_max_size = 128 * 1024,
1519 },
1520 {
1521 .suffix = "MIC ADC",
1522 .capture_ops = &snd_intel8x0_capture_mic_ops,
1523 .prealloc_size = 0,
1524 .prealloc_max_size = 128 * 1024,
1525 .ac97_idx = ICHD_MIC,
1526 },
1527 {
1528 .suffix = "MIC2 ADC",
1529 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1530 .prealloc_size = 0,
1531 .prealloc_max_size = 128 * 1024,
1532 .ac97_idx = ICHD_MIC2,
1533 },
1534 {
1535 .suffix = "ADC2",
1536 .capture_ops = &snd_intel8x0_capture2_ops,
1537 .prealloc_size = 0,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = ICHD_PCM2IN,
1540 },
1541 {
1542 .suffix = "IEC958",
1543 .playback_ops = &snd_intel8x0_spdif_ops,
1544 .prealloc_size = 64 * 1024,
1545 .prealloc_max_size = 128 * 1024,
1546 .ac97_idx = ICHD_SPBAR,
1547 },
1548 };
1549
1550 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1551 {
1552 .playback_ops = &snd_intel8x0_playback_ops,
1553 .capture_ops = &snd_intel8x0_capture_ops,
1554 .prealloc_size = 64 * 1024,
1555 .prealloc_max_size = 128 * 1024,
1556 },
1557 {
1558 .suffix = "MIC ADC",
1559 .capture_ops = &snd_intel8x0_capture_mic_ops,
1560 .prealloc_size = 0,
1561 .prealloc_max_size = 128 * 1024,
1562 .ac97_idx = NVD_MIC,
1563 },
1564 {
1565 .suffix = "IEC958",
1566 .playback_ops = &snd_intel8x0_spdif_ops,
1567 .prealloc_size = 64 * 1024,
1568 .prealloc_max_size = 128 * 1024,
1569 .ac97_idx = NVD_SPBAR,
1570 },
1571 };
1572
1573 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1574 {
1575 .playback_ops = &snd_intel8x0_ali_playback_ops,
1576 .capture_ops = &snd_intel8x0_ali_capture_ops,
1577 .prealloc_size = 64 * 1024,
1578 .prealloc_max_size = 128 * 1024,
1579 },
1580 {
1581 .suffix = "MIC ADC",
1582 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1583 .prealloc_size = 0,
1584 .prealloc_max_size = 128 * 1024,
1585 .ac97_idx = ALID_MIC,
1586 },
1587 {
1588 .suffix = "IEC958",
1589 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1590 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1591 .prealloc_size = 64 * 1024,
1592 .prealloc_max_size = 128 * 1024,
1593 .ac97_idx = ALID_AC97SPDIFOUT,
1594 },
1595 #if 0 // NYI
1596 {
1597 .suffix = "HW IEC958",
1598 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1599 .prealloc_size = 64 * 1024,
1600 .prealloc_max_size = 128 * 1024,
1601 },
1602 #endif
1603 };
1604
1605 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1606 {
1607 int i, tblsize, device, err;
1608 struct ich_pcm_table *tbl, *rec;
1609
1610 switch (chip->device_type) {
1611 case DEVICE_INTEL_ICH4:
1612 tbl = intel_pcms;
1613 tblsize = ARRAY_SIZE(intel_pcms);
1614 if (spdif_aclink)
1615 tblsize--;
1616 break;
1617 case DEVICE_NFORCE:
1618 tbl = nforce_pcms;
1619 tblsize = ARRAY_SIZE(nforce_pcms);
1620 if (spdif_aclink)
1621 tblsize--;
1622 break;
1623 case DEVICE_ALI:
1624 tbl = ali_pcms;
1625 tblsize = ARRAY_SIZE(ali_pcms);
1626 break;
1627 default:
1628 tbl = intel_pcms;
1629 tblsize = 2;
1630 break;
1631 }
1632
1633 device = 0;
1634 for (i = 0; i < tblsize; i++) {
1635 rec = tbl + i;
1636 if (i > 0 && rec->ac97_idx) {
1637 /* activate PCM only when associated AC'97 codec */
1638 if (! chip->ichd[rec->ac97_idx].pcm)
1639 continue;
1640 }
1641 err = snd_intel8x0_pcm1(chip, device, rec);
1642 if (err < 0)
1643 return err;
1644 device++;
1645 }
1646
1647 chip->pcm_devs = device;
1648 return 0;
1649 }
1650
1651
1652 /*
1653 * Mixer part
1654 */
1655
1656 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1657 {
1658 struct intel8x0 *chip = bus->private_data;
1659 chip->ac97_bus = NULL;
1660 }
1661
1662 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1663 {
1664 struct intel8x0 *chip = ac97->private_data;
1665 chip->ac97[ac97->num] = NULL;
1666 }
1667
1668 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1669 /* front PCM */
1670 {
1671 .exclusive = 1,
1672 .r = { {
1673 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1674 (1 << AC97_SLOT_PCM_RIGHT) |
1675 (1 << AC97_SLOT_PCM_CENTER) |
1676 (1 << AC97_SLOT_PCM_SLEFT) |
1677 (1 << AC97_SLOT_PCM_SRIGHT) |
1678 (1 << AC97_SLOT_LFE)
1679 },
1680 {
1681 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1682 (1 << AC97_SLOT_PCM_RIGHT) |
1683 (1 << AC97_SLOT_PCM_LEFT_0) |
1684 (1 << AC97_SLOT_PCM_RIGHT_0)
1685 }
1686 }
1687 },
1688 /* PCM IN #1 */
1689 {
1690 .stream = 1,
1691 .exclusive = 1,
1692 .r = { {
1693 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1694 (1 << AC97_SLOT_PCM_RIGHT)
1695 }
1696 }
1697 },
1698 /* MIC IN #1 */
1699 {
1700 .stream = 1,
1701 .exclusive = 1,
1702 .r = { {
1703 .slots = (1 << AC97_SLOT_MIC)
1704 }
1705 }
1706 },
1707 /* S/PDIF PCM */
1708 {
1709 .exclusive = 1,
1710 .spdif = 1,
1711 .r = { {
1712 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1713 (1 << AC97_SLOT_SPDIF_RIGHT2)
1714 }
1715 }
1716 },
1717 /* PCM IN #2 */
1718 {
1719 .stream = 1,
1720 .exclusive = 1,
1721 .r = { {
1722 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1723 (1 << AC97_SLOT_PCM_RIGHT)
1724 }
1725 }
1726 },
1727 /* MIC IN #2 */
1728 {
1729 .stream = 1,
1730 .exclusive = 1,
1731 .r = { {
1732 .slots = (1 << AC97_SLOT_MIC)
1733 }
1734 }
1735 },
1736 };
1737
1738 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1739 {
1740 .subvendor = 0x0e11,
1741 .subdevice = 0x000e,
1742 .name = "Compaq Deskpro EN", /* AD1885 */
1743 .type = AC97_TUNE_HP_ONLY
1744 },
1745 {
1746 .subvendor = 0x0e11,
1747 .subdevice = 0x008a,
1748 .name = "Compaq Evo W4000", /* AD1885 */
1749 .type = AC97_TUNE_HP_ONLY
1750 },
1751 {
1752 .subvendor = 0x0e11,
1753 .subdevice = 0x00b8,
1754 .name = "Compaq Evo D510C",
1755 .type = AC97_TUNE_HP_ONLY
1756 },
1757 {
1758 .subvendor = 0x0e11,
1759 .subdevice = 0x0860,
1760 .name = "HP/Compaq nx7010",
1761 .type = AC97_TUNE_MUTE_LED
1762 },
1763 {
1764 .subvendor = 0x1014,
1765 .subdevice = 0x1f00,
1766 .name = "MS-9128",
1767 .type = AC97_TUNE_ALC_JACK
1768 },
1769 {
1770 .subvendor = 0x1014,
1771 .subdevice = 0x0267,
1772 .name = "IBM NetVista A30p", /* AD1981B */
1773 .type = AC97_TUNE_HP_ONLY
1774 },
1775 {
1776 .subvendor = 0x1025,
1777 .subdevice = 0x0082,
1778 .name = "Acer Travelmate 2310",
1779 .type = AC97_TUNE_HP_ONLY
1780 },
1781 {
1782 .subvendor = 0x1025,
1783 .subdevice = 0x0083,
1784 .name = "Acer Aspire 3003LCi",
1785 .type = AC97_TUNE_HP_ONLY
1786 },
1787 {
1788 .subvendor = 0x1028,
1789 .subdevice = 0x00d8,
1790 .name = "Dell Precision 530", /* AD1885 */
1791 .type = AC97_TUNE_HP_ONLY
1792 },
1793 {
1794 .subvendor = 0x1028,
1795 .subdevice = 0x010d,
1796 .name = "Dell", /* which model? AD1885 */
1797 .type = AC97_TUNE_HP_ONLY
1798 },
1799 {
1800 .subvendor = 0x1028,
1801 .subdevice = 0x0126,
1802 .name = "Dell Optiplex GX260", /* AD1981A */
1803 .type = AC97_TUNE_HP_ONLY
1804 },
1805 {
1806 .subvendor = 0x1028,
1807 .subdevice = 0x012c,
1808 .name = "Dell Precision 650", /* AD1981A */
1809 .type = AC97_TUNE_HP_ONLY
1810 },
1811 {
1812 .subvendor = 0x1028,
1813 .subdevice = 0x012d,
1814 .name = "Dell Precision 450", /* AD1981B*/
1815 .type = AC97_TUNE_HP_ONLY
1816 },
1817 {
1818 .subvendor = 0x1028,
1819 .subdevice = 0x0147,
1820 .name = "Dell", /* which model? AD1981B*/
1821 .type = AC97_TUNE_HP_ONLY
1822 },
1823 {
1824 .subvendor = 0x1028,
1825 .subdevice = 0x0151,
1826 .name = "Dell Optiplex GX270", /* AD1981B */
1827 .type = AC97_TUNE_HP_ONLY
1828 },
1829 {
1830 .subvendor = 0x1028,
1831 .subdevice = 0x014e,
1832 .name = "Dell D800", /* STAC9750/51 */
1833 .type = AC97_TUNE_HP_ONLY
1834 },
1835 {
1836 .subvendor = 0x1028,
1837 .subdevice = 0x0163,
1838 .name = "Dell Unknown", /* STAC9750/51 */
1839 .type = AC97_TUNE_HP_ONLY
1840 },
1841 {
1842 .subvendor = 0x1028,
1843 .subdevice = 0x0186,
1844 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1845 .type = AC97_TUNE_HP_MUTE_LED
1846 },
1847 {
1848 .subvendor = 0x1028,
1849 .subdevice = 0x0188,
1850 .name = "Dell Inspiron 6000",
1851 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1852 },
1853 {
1854 .subvendor = 0x1028,
1855 .subdevice = 0x0191,
1856 .name = "Dell Inspiron 8600",
1857 .type = AC97_TUNE_HP_ONLY
1858 },
1859 {
1860 .subvendor = 0x103c,
1861 .subdevice = 0x006d,
1862 .name = "HP zv5000",
1863 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1864 },
1865 { /* FIXME: which codec? */
1866 .subvendor = 0x103c,
1867 .subdevice = 0x00c3,
1868 .name = "HP xw6000",
1869 .type = AC97_TUNE_HP_ONLY
1870 },
1871 {
1872 .subvendor = 0x103c,
1873 .subdevice = 0x088c,
1874 .name = "HP nc8000",
1875 .type = AC97_TUNE_HP_MUTE_LED
1876 },
1877 {
1878 .subvendor = 0x103c,
1879 .subdevice = 0x0890,
1880 .name = "HP nc6000",
1881 .type = AC97_TUNE_MUTE_LED
1882 },
1883 {
1884 .subvendor = 0x103c,
1885 .subdevice = 0x0934,
1886 .name = "HP nx8220",
1887 .type = AC97_TUNE_MUTE_LED
1888 },
1889 {
1890 .subvendor = 0x103c,
1891 .subdevice = 0x129d,
1892 .name = "HP xw8000",
1893 .type = AC97_TUNE_HP_ONLY
1894 },
1895 {
1896 .subvendor = 0x103c,
1897 .subdevice = 0x0938,
1898 .name = "HP nc4200",
1899 .type = AC97_TUNE_HP_MUTE_LED
1900 },
1901 {
1902 .subvendor = 0x103c,
1903 .subdevice = 0x099c,
1904 .name = "HP nx6110/nc6120",
1905 .type = AC97_TUNE_HP_MUTE_LED
1906 },
1907 {
1908 .subvendor = 0x103c,
1909 .subdevice = 0x0944,
1910 .name = "HP nc6220",
1911 .type = AC97_TUNE_HP_MUTE_LED
1912 },
1913 {
1914 .subvendor = 0x103c,
1915 .subdevice = 0x0934,
1916 .name = "HP nc8220",
1917 .type = AC97_TUNE_HP_MUTE_LED
1918 },
1919 {
1920 .subvendor = 0x103c,
1921 .subdevice = 0x12f1,
1922 .name = "HP xw8200", /* AD1981B*/
1923 .type = AC97_TUNE_HP_ONLY
1924 },
1925 {
1926 .subvendor = 0x103c,
1927 .subdevice = 0x12f2,
1928 .name = "HP xw6200",
1929 .type = AC97_TUNE_HP_ONLY
1930 },
1931 {
1932 .subvendor = 0x103c,
1933 .subdevice = 0x3008,
1934 .name = "HP xw4200", /* AD1981B*/
1935 .type = AC97_TUNE_HP_ONLY
1936 },
1937 {
1938 .subvendor = 0x104d,
1939 .subdevice = 0x8197,
1940 .name = "Sony S1XP",
1941 .type = AC97_TUNE_INV_EAPD
1942 },
1943 {
1944 .subvendor = 0x1043,
1945 .subdevice = 0x80f3,
1946 .name = "ASUS ICH5/AD1985",
1947 .type = AC97_TUNE_AD_SHARING
1948 },
1949 {
1950 .subvendor = 0x10cf,
1951 .subdevice = 0x11c3,
1952 .name = "Fujitsu-Siemens E4010",
1953 .type = AC97_TUNE_HP_ONLY
1954 },
1955 {
1956 .subvendor = 0x10cf,
1957 .subdevice = 0x1225,
1958 .name = "Fujitsu-Siemens T3010",
1959 .type = AC97_TUNE_HP_ONLY
1960 },
1961 {
1962 .subvendor = 0x10cf,
1963 .subdevice = 0x1253,
1964 .name = "Fujitsu S6210", /* STAC9750/51 */
1965 .type = AC97_TUNE_HP_ONLY
1966 },
1967 {
1968 .subvendor = 0x10cf,
1969 .subdevice = 0x127d,
1970 .name = "Fujitsu Lifebook P7010",
1971 .type = AC97_TUNE_HP_ONLY
1972 },
1973 {
1974 .subvendor = 0x10cf,
1975 .subdevice = 0x127e,
1976 .name = "Fujitsu Lifebook C1211D",
1977 .type = AC97_TUNE_HP_ONLY
1978 },
1979 {
1980 .subvendor = 0x10cf,
1981 .subdevice = 0x12ec,
1982 .name = "Fujitsu-Siemens 4010",
1983 .type = AC97_TUNE_HP_ONLY
1984 },
1985 {
1986 .subvendor = 0x10cf,
1987 .subdevice = 0x12f2,
1988 .name = "Fujitsu-Siemens Celsius H320",
1989 .type = AC97_TUNE_SWAP_HP
1990 },
1991 {
1992 .subvendor = 0x10f1,
1993 .subdevice = 0x2665,
1994 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1995 .type = AC97_TUNE_HP_ONLY
1996 },
1997 {
1998 .subvendor = 0x10f1,
1999 .subdevice = 0x2885,
2000 .name = "AMD64 Mobo", /* ALC650 */
2001 .type = AC97_TUNE_HP_ONLY
2002 },
2003 {
2004 .subvendor = 0x10f1,
2005 .subdevice = 0x2895,
2006 .name = "Tyan Thunder K8WE",
2007 .type = AC97_TUNE_HP_ONLY
2008 },
2009 {
2010 .subvendor = 0x10f7,
2011 .subdevice = 0x834c,
2012 .name = "Panasonic CF-R4",
2013 .type = AC97_TUNE_HP_ONLY,
2014 },
2015 {
2016 .subvendor = 0x110a,
2017 .subdevice = 0x0056,
2018 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2019 .type = AC97_TUNE_HP_ONLY
2020 },
2021 {
2022 .subvendor = 0x11d4,
2023 .subdevice = 0x5375,
2024 .name = "ADI AD1985 (discrete)",
2025 .type = AC97_TUNE_HP_ONLY
2026 },
2027 {
2028 .subvendor = 0x1462,
2029 .subdevice = 0x5470,
2030 .name = "MSI P4 ATX 645 Ultra",
2031 .type = AC97_TUNE_HP_ONLY
2032 },
2033 {
2034 .subvendor = 0x1734,
2035 .subdevice = 0x0088,
2036 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2037 .type = AC97_TUNE_HP_ONLY
2038 },
2039 {
2040 .subvendor = 0x8086,
2041 .subdevice = 0x2000,
2042 .mask = 0xfff0,
2043 .name = "Intel ICH5/AD1985",
2044 .type = AC97_TUNE_AD_SHARING
2045 },
2046 {
2047 .subvendor = 0x8086,
2048 .subdevice = 0x4000,
2049 .mask = 0xfff0,
2050 .name = "Intel ICH5/AD1985",
2051 .type = AC97_TUNE_AD_SHARING
2052 },
2053 {
2054 .subvendor = 0x8086,
2055 .subdevice = 0x4856,
2056 .name = "Intel D845WN (82801BA)",
2057 .type = AC97_TUNE_SWAP_HP
2058 },
2059 {
2060 .subvendor = 0x8086,
2061 .subdevice = 0x4d44,
2062 .name = "Intel D850EMV2", /* AD1885 */
2063 .type = AC97_TUNE_HP_ONLY
2064 },
2065 {
2066 .subvendor = 0x8086,
2067 .subdevice = 0x4d56,
2068 .name = "Intel ICH/AD1885",
2069 .type = AC97_TUNE_HP_ONLY
2070 },
2071 {
2072 .subvendor = 0x8086,
2073 .subdevice = 0x6000,
2074 .mask = 0xfff0,
2075 .name = "Intel ICH5/AD1985",
2076 .type = AC97_TUNE_AD_SHARING
2077 },
2078 {
2079 .subvendor = 0x8086,
2080 .subdevice = 0xe000,
2081 .mask = 0xfff0,
2082 .name = "Intel ICH5/AD1985",
2083 .type = AC97_TUNE_AD_SHARING
2084 },
2085 #if 0 /* FIXME: this seems wrong on most boards */
2086 {
2087 .subvendor = 0x8086,
2088 .subdevice = 0xa000,
2089 .mask = 0xfff0,
2090 .name = "Intel ICH5/AD1985",
2091 .type = AC97_TUNE_HP_ONLY
2092 },
2093 #endif
2094 { } /* terminator */
2095 };
2096
2097 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2098 const char *quirk_override)
2099 {
2100 struct snd_ac97_bus *pbus;
2101 struct snd_ac97_template ac97;
2102 int err;
2103 unsigned int i, codecs;
2104 unsigned int glob_sta = 0;
2105 struct snd_ac97_bus_ops *ops;
2106 static struct snd_ac97_bus_ops standard_bus_ops = {
2107 .write = snd_intel8x0_codec_write,
2108 .read = snd_intel8x0_codec_read,
2109 };
2110 static struct snd_ac97_bus_ops ali_bus_ops = {
2111 .write = snd_intel8x0_ali_codec_write,
2112 .read = snd_intel8x0_ali_codec_read,
2113 };
2114
2115 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2116 if (!spdif_aclink) {
2117 switch (chip->device_type) {
2118 case DEVICE_NFORCE:
2119 chip->spdif_idx = NVD_SPBAR;
2120 break;
2121 case DEVICE_ALI:
2122 chip->spdif_idx = ALID_AC97SPDIFOUT;
2123 break;
2124 case DEVICE_INTEL_ICH4:
2125 chip->spdif_idx = ICHD_SPBAR;
2126 break;
2127 };
2128 }
2129
2130 chip->in_ac97_init = 1;
2131
2132 memset(&ac97, 0, sizeof(ac97));
2133 ac97.private_data = chip;
2134 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2135 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2136 if (chip->xbox)
2137 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2138 if (chip->device_type != DEVICE_ALI) {
2139 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2140 ops = &standard_bus_ops;
2141 chip->in_sdin_init = 1;
2142 codecs = 0;
2143 for (i = 0; i < chip->max_codecs; i++) {
2144 if (! (glob_sta & chip->codec_bit[i]))
2145 continue;
2146 if (chip->device_type == DEVICE_INTEL_ICH4) {
2147 snd_intel8x0_codec_read_test(chip, codecs);
2148 chip->ac97_sdin[codecs] =
2149 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2150 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2151 chip->ac97_sdin[codecs] = 0;
2152 } else
2153 chip->ac97_sdin[codecs] = i;
2154 codecs++;
2155 }
2156 chip->in_sdin_init = 0;
2157 if (! codecs)
2158 codecs = 1;
2159 } else {
2160 ops = &ali_bus_ops;
2161 codecs = 1;
2162 /* detect the secondary codec */
2163 for (i = 0; i < 100; i++) {
2164 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2165 if (reg & 0x40) {
2166 codecs = 2;
2167 break;
2168 }
2169 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2170 udelay(1);
2171 }
2172 }
2173 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2174 goto __err;
2175 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2176 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2177 pbus->clock = ac97_clock;
2178 /* FIXME: my test board doesn't work well with VRA... */
2179 if (chip->device_type == DEVICE_ALI)
2180 pbus->no_vra = 1;
2181 else
2182 pbus->dra = 1;
2183 chip->ac97_bus = pbus;
2184 chip->ncodecs = codecs;
2185
2186 ac97.pci = chip->pci;
2187 for (i = 0; i < codecs; i++) {
2188 ac97.num = i;
2189 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2190 if (err != -EACCES)
2191 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2192 if (i == 0)
2193 goto __err;
2194 }
2195 }
2196 /* tune up the primary codec */
2197 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2198 /* enable separate SDINs for ICH4 */
2199 if (chip->device_type == DEVICE_INTEL_ICH4)
2200 pbus->isdin = 1;
2201 /* find the available PCM streams */
2202 i = ARRAY_SIZE(ac97_pcm_defs);
2203 if (chip->device_type != DEVICE_INTEL_ICH4)
2204 i -= 2; /* do not allocate PCM2IN and MIC2 */
2205 if (chip->spdif_idx < 0)
2206 i--; /* do not allocate S/PDIF */
2207 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2208 if (err < 0)
2209 goto __err;
2210 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2211 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2212 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2213 if (chip->spdif_idx >= 0)
2214 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2215 if (chip->device_type == DEVICE_INTEL_ICH4) {
2216 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2217 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2218 }
2219 /* enable separate SDINs for ICH4 */
2220 if (chip->device_type == DEVICE_INTEL_ICH4) {
2221 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2222 u8 tmp = igetbyte(chip, ICHREG(SDM));
2223 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2224 if (pcm) {
2225 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2226 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2227 for (i = 1; i < 4; i++) {
2228 if (pcm->r[0].codec[i]) {
2229 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2230 break;
2231 }
2232 }
2233 } else {
2234 tmp &= ~ICH_SE; /* steer disable */
2235 }
2236 iputbyte(chip, ICHREG(SDM), tmp);
2237 }
2238 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2239 chip->multi4 = 1;
2240 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2241 chip->multi6 = 1;
2242 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2243 chip->multi8 = 1;
2244 }
2245 }
2246 if (pbus->pcms[0].r[1].rslots[0]) {
2247 chip->dra = 1;
2248 }
2249 if (chip->device_type == DEVICE_INTEL_ICH4) {
2250 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2251 chip->smp20bit = 1;
2252 }
2253 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2254 /* 48kHz only */
2255 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2256 }
2257 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2258 /* use slot 10/11 for SPDIF */
2259 u32 val;
2260 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2261 val |= ICH_PCM_SPDIF_1011;
2262 iputdword(chip, ICHREG(GLOB_CNT), val);
2263 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2264 }
2265 chip->in_ac97_init = 0;
2266 return 0;
2267
2268 __err:
2269 /* clear the cold-reset bit for the next chance */
2270 if (chip->device_type != DEVICE_ALI)
2271 iputdword(chip, ICHREG(GLOB_CNT),
2272 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2273 return err;
2274 }
2275
2276
2277 /*
2278 *
2279 */
2280
2281 static void do_ali_reset(struct intel8x0 *chip)
2282 {
2283 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2284 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2285 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2286 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2287 iputdword(chip, ICHREG(ALI_INTERFACECR),
2288 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2289 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2290 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2291 }
2292
2293 #ifdef CONFIG_SND_AC97_POWER_SAVE
2294 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2295 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2296 { } /* end */
2297 };
2298
2299 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2300 {
2301 unsigned int cnt;
2302 /* ACLink on, 2 channels */
2303
2304 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2305 return -EIO;
2306
2307 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2308 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2309
2310 /* do cold reset - the full ac97 powerdown may leave the controller
2311 * in a warm state but actually it cannot communicate with the codec.
2312 */
2313 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2314 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2315 udelay(10);
2316 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2317 msleep(1);
2318 return 0;
2319 }
2320 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2321 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2322 #else
2323 #define snd_intel8x0_ich_chip_cold_reset(chip) 0
2324 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2325 #endif
2326
2327 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2328 {
2329 unsigned long end_time;
2330 unsigned int cnt;
2331 /* ACLink on, 2 channels */
2332 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2333 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2334 /* finish cold or do warm reset */
2335 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2336 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2337 end_time = (jiffies + (HZ / 4)) + 1;
2338 do {
2339 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2340 return 0;
2341 schedule_timeout_uninterruptible(1);
2342 } while (time_after_eq(end_time, jiffies));
2343 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2344 igetdword(chip, ICHREG(GLOB_CNT)));
2345 return -EIO;
2346 }
2347
2348 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2349 {
2350 unsigned long end_time;
2351 unsigned int status, nstatus;
2352 unsigned int cnt;
2353 int err;
2354
2355 /* put logic to right state */
2356 /* first clear status bits */
2357 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2358 if (chip->device_type == DEVICE_NFORCE)
2359 status |= ICH_NVSPINT;
2360 cnt = igetdword(chip, ICHREG(GLOB_STA));
2361 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2362
2363 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2364 err = snd_intel8x0_ich_chip_cold_reset(chip);
2365 else
2366 err = snd_intel8x0_ich_chip_reset(chip);
2367 if (err < 0)
2368 return err;
2369
2370 if (probing) {
2371 /* wait for any codec ready status.
2372 * Once it becomes ready it should remain ready
2373 * as long as we do not disable the ac97 link.
2374 */
2375 end_time = jiffies + HZ;
2376 do {
2377 status = igetdword(chip, ICHREG(GLOB_STA)) &
2378 chip->codec_isr_bits;
2379 if (status)
2380 break;
2381 schedule_timeout_uninterruptible(1);
2382 } while (time_after_eq(end_time, jiffies));
2383 if (! status) {
2384 /* no codec is found */
2385 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2386 igetdword(chip, ICHREG(GLOB_STA)));
2387 return -EIO;
2388 }
2389
2390 /* wait for other codecs ready status. */
2391 end_time = jiffies + HZ / 4;
2392 while (status != chip->codec_isr_bits &&
2393 time_after_eq(end_time, jiffies)) {
2394 schedule_timeout_uninterruptible(1);
2395 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2396 chip->codec_isr_bits;
2397 }
2398
2399 } else {
2400 /* resume phase */
2401 int i;
2402 status = 0;
2403 for (i = 0; i < chip->ncodecs; i++)
2404 if (chip->ac97[i])
2405 status |= chip->codec_bit[chip->ac97_sdin[i]];
2406 /* wait until all the probed codecs are ready */
2407 end_time = jiffies + HZ;
2408 do {
2409 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2410 chip->codec_isr_bits;
2411 if (status == nstatus)
2412 break;
2413 schedule_timeout_uninterruptible(1);
2414 } while (time_after_eq(end_time, jiffies));
2415 }
2416
2417 if (chip->device_type == DEVICE_SIS) {
2418 /* unmute the output on SIS7012 */
2419 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2420 }
2421 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2422 /* enable SPDIF interrupt */
2423 unsigned int val;
2424 pci_read_config_dword(chip->pci, 0x4c, &val);
2425 val |= 0x1000000;
2426 pci_write_config_dword(chip->pci, 0x4c, val);
2427 }
2428 return 0;
2429 }
2430
2431 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2432 {
2433 u32 reg;
2434 int i = 0;
2435
2436 reg = igetdword(chip, ICHREG(ALI_SCR));
2437 if ((reg & 2) == 0) /* Cold required */
2438 reg |= 2;
2439 else
2440 reg |= 1; /* Warm */
2441 reg &= ~0x80000000; /* ACLink on */
2442 iputdword(chip, ICHREG(ALI_SCR), reg);
2443
2444 for (i = 0; i < HZ / 2; i++) {
2445 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2446 goto __ok;
2447 schedule_timeout_uninterruptible(1);
2448 }
2449 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2450 if (probing)
2451 return -EIO;
2452
2453 __ok:
2454 for (i = 0; i < HZ / 2; i++) {
2455 reg = igetdword(chip, ICHREG(ALI_RTSR));
2456 if (reg & 0x80) /* primary codec */
2457 break;
2458 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2459 schedule_timeout_uninterruptible(1);
2460 }
2461
2462 do_ali_reset(chip);
2463 return 0;
2464 }
2465
2466 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2467 {
2468 unsigned int i, timeout;
2469 int err;
2470
2471 if (chip->device_type != DEVICE_ALI) {
2472 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2473 return err;
2474 iagetword(chip, 0); /* clear semaphore flag */
2475 } else {
2476 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2477 return err;
2478 }
2479
2480 /* disable interrupts */
2481 for (i = 0; i < chip->bdbars_count; i++)
2482 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2483 /* reset channels */
2484 for (i = 0; i < chip->bdbars_count; i++)
2485 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2486 for (i = 0; i < chip->bdbars_count; i++) {
2487 timeout = 100000;
2488 while (--timeout != 0) {
2489 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2490 break;
2491 }
2492 if (timeout == 0)
2493 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2494 }
2495 /* initialize Buffer Descriptor Lists */
2496 for (i = 0; i < chip->bdbars_count; i++)
2497 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2498 chip->ichd[i].bdbar_addr);
2499 return 0;
2500 }
2501
2502 static int snd_intel8x0_free(struct intel8x0 *chip)
2503 {
2504 unsigned int i;
2505
2506 if (chip->irq < 0)
2507 goto __hw_end;
2508 /* disable interrupts */
2509 for (i = 0; i < chip->bdbars_count; i++)
2510 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2511 /* reset channels */
2512 for (i = 0; i < chip->bdbars_count; i++)
2513 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2514 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2515 /* stop the spdif interrupt */
2516 unsigned int val;
2517 pci_read_config_dword(chip->pci, 0x4c, &val);
2518 val &= ~0x1000000;
2519 pci_write_config_dword(chip->pci, 0x4c, val);
2520 }
2521 /* --- */
2522
2523 __hw_end:
2524 if (chip->irq >= 0)
2525 free_irq(chip->irq, chip);
2526 if (chip->bdbars.area) {
2527 if (chip->fix_nocache)
2528 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2529 snd_dma_free_pages(&chip->bdbars);
2530 }
2531 if (chip->addr)
2532 pci_iounmap(chip->pci, chip->addr);
2533 if (chip->bmaddr)
2534 pci_iounmap(chip->pci, chip->bmaddr);
2535 pci_release_regions(chip->pci);
2536 pci_disable_device(chip->pci);
2537 kfree(chip);
2538 return 0;
2539 }
2540
2541 #ifdef CONFIG_PM
2542 /*
2543 * power management
2544 */
2545 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2546 {
2547 struct snd_card *card = pci_get_drvdata(pci);
2548 struct intel8x0 *chip = card->private_data;
2549 int i;
2550
2551 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2552 for (i = 0; i < chip->pcm_devs; i++)
2553 snd_pcm_suspend_all(chip->pcm[i]);
2554 /* clear nocache */
2555 if (chip->fix_nocache) {
2556 for (i = 0; i < chip->bdbars_count; i++) {
2557 struct ichdev *ichdev = &chip->ichd[i];
2558 if (ichdev->substream && ichdev->page_attr_changed) {
2559 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2560 if (runtime->dma_area)
2561 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2562 }
2563 }
2564 }
2565 for (i = 0; i < chip->ncodecs; i++)
2566 snd_ac97_suspend(chip->ac97[i]);
2567 if (chip->device_type == DEVICE_INTEL_ICH4)
2568 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2569
2570 if (chip->irq >= 0) {
2571 free_irq(chip->irq, chip);
2572 chip->irq = -1;
2573 }
2574 pci_disable_device(pci);
2575 pci_save_state(pci);
2576 /* The call below may disable built-in speaker on some laptops
2577 * after S2RAM. So, don't touch it.
2578 */
2579 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2580 return 0;
2581 }
2582
2583 static int intel8x0_resume(struct pci_dev *pci)
2584 {
2585 struct snd_card *card = pci_get_drvdata(pci);
2586 struct intel8x0 *chip = card->private_data;
2587 int i;
2588
2589 pci_set_power_state(pci, PCI_D0);
2590 pci_restore_state(pci);
2591 if (pci_enable_device(pci) < 0) {
2592 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2593 "disabling device\n");
2594 snd_card_disconnect(card);
2595 return -EIO;
2596 }
2597 pci_set_master(pci);
2598 snd_intel8x0_chip_init(chip, 0);
2599 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2600 IRQF_SHARED, card->shortname, chip)) {
2601 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2602 "disabling device\n", pci->irq);
2603 snd_card_disconnect(card);
2604 return -EIO;
2605 }
2606 chip->irq = pci->irq;
2607 synchronize_irq(chip->irq);
2608
2609 /* re-initialize mixer stuff */
2610 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2611 /* enable separate SDINs for ICH4 */
2612 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2613 /* use slot 10/11 for SPDIF */
2614 iputdword(chip, ICHREG(GLOB_CNT),
2615 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2616 ICH_PCM_SPDIF_1011);
2617 }
2618
2619 /* refill nocache */
2620 if (chip->fix_nocache)
2621 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2622
2623 for (i = 0; i < chip->ncodecs; i++)
2624 snd_ac97_resume(chip->ac97[i]);
2625
2626 /* refill nocache */
2627 if (chip->fix_nocache) {
2628 for (i = 0; i < chip->bdbars_count; i++) {
2629 struct ichdev *ichdev = &chip->ichd[i];
2630 if (ichdev->substream && ichdev->page_attr_changed) {
2631 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2632 if (runtime->dma_area)
2633 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2634 }
2635 }
2636 }
2637
2638 /* resume status */
2639 for (i = 0; i < chip->bdbars_count; i++) {
2640 struct ichdev *ichdev = &chip->ichd[i];
2641 unsigned long port = ichdev->reg_offset;
2642 if (! ichdev->substream || ! ichdev->suspended)
2643 continue;
2644 if (ichdev->ichd == ICHD_PCMOUT)
2645 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2646 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2647 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2648 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2649 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2650 }
2651
2652 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2653 return 0;
2654 }
2655 #endif /* CONFIG_PM */
2656
2657 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2658
2659 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2660 {
2661 struct snd_pcm_substream *subs;
2662 struct ichdev *ichdev;
2663 unsigned long port;
2664 unsigned long pos, t;
2665 struct timeval start_time, stop_time;
2666
2667 if (chip->ac97_bus->clock != 48000)
2668 return; /* specified in module option */
2669
2670 subs = chip->pcm[0]->streams[0].substream;
2671 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2672 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2673 return;
2674 }
2675 ichdev = &chip->ichd[ICHD_PCMOUT];
2676 ichdev->physbuf = subs->dma_buffer.addr;
2677 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2678 ichdev->substream = NULL; /* don't process interrupts */
2679
2680 /* set rate */
2681 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2682 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2683 return;
2684 }
2685 snd_intel8x0_setup_periods(chip, ichdev);
2686 port = ichdev->reg_offset;
2687 spin_lock_irq(&chip->reg_lock);
2688 chip->in_measurement = 1;
2689 /* trigger */
2690 if (chip->device_type != DEVICE_ALI)
2691 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2692 else {
2693 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2694 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2695 }
2696 do_gettimeofday(&start_time);
2697 spin_unlock_irq(&chip->reg_lock);
2698 msleep(50);
2699 spin_lock_irq(&chip->reg_lock);
2700 /* check the position */
2701 pos = ichdev->fragsize1;
2702 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2703 pos += ichdev->position;
2704 chip->in_measurement = 0;
2705 do_gettimeofday(&stop_time);
2706 /* stop */
2707 if (chip->device_type == DEVICE_ALI) {
2708 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2709 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2710 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2711 ;
2712 } else {
2713 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2714 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2715 ;
2716 }
2717 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2718 spin_unlock_irq(&chip->reg_lock);
2719
2720 t = stop_time.tv_sec - start_time.tv_sec;
2721 t *= 1000000;
2722 t += stop_time.tv_usec - start_time.tv_usec;
2723 printk(KERN_INFO "%s: measured %lu usecs\n", __func__, t);
2724 if (t == 0) {
2725 snd_printk(KERN_ERR "?? calculation error..\n");
2726 return;
2727 }
2728 pos = (pos / 4) * 1000;
2729 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2730 if (pos < 40000 || pos >= 60000)
2731 /* abnormal value. hw problem? */
2732 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2733 else if (pos < 47500 || pos > 48500)
2734 /* not 48000Hz, tuning the clock.. */
2735 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2736 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2737 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2738 }
2739
2740 static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2741 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2742 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2743 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2744 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2745 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2746 { } /* terminator */
2747 };
2748
2749 static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2750 {
2751 struct pci_dev *pci = chip->pci;
2752 const struct snd_pci_quirk *wl;
2753
2754 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2755 if (!wl)
2756 return 0;
2757 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2758 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2759 chip->ac97_bus->clock = wl->value;
2760 return 1;
2761 }
2762
2763 #ifdef CONFIG_PROC_FS
2764 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2765 struct snd_info_buffer *buffer)
2766 {
2767 struct intel8x0 *chip = entry->private_data;
2768 unsigned int tmp;
2769
2770 snd_iprintf(buffer, "Intel8x0\n\n");
2771 if (chip->device_type == DEVICE_ALI)
2772 return;
2773 tmp = igetdword(chip, ICHREG(GLOB_STA));
2774 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2775 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2776 if (chip->device_type == DEVICE_INTEL_ICH4)
2777 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2778 snd_iprintf(buffer, "AC'97 codecs ready :");
2779 if (tmp & chip->codec_isr_bits) {
2780 int i;
2781 static const char *codecs[3] = {
2782 "primary", "secondary", "tertiary"
2783 };
2784 for (i = 0; i < chip->max_codecs; i++)
2785 if (tmp & chip->codec_bit[i])
2786 snd_iprintf(buffer, " %s", codecs[i]);
2787 } else
2788 snd_iprintf(buffer, " none");
2789 snd_iprintf(buffer, "\n");
2790 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2791 chip->device_type == DEVICE_SIS)
2792 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2793 chip->ac97_sdin[0],
2794 chip->ac97_sdin[1],
2795 chip->ac97_sdin[2]);
2796 }
2797
2798 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2799 {
2800 struct snd_info_entry *entry;
2801
2802 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2803 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2804 }
2805 #else
2806 #define snd_intel8x0_proc_init(x)
2807 #endif
2808
2809 static int snd_intel8x0_dev_free(struct snd_device *device)
2810 {
2811 struct intel8x0 *chip = device->device_data;
2812 return snd_intel8x0_free(chip);
2813 }
2814
2815 struct ich_reg_info {
2816 unsigned int int_sta_mask;
2817 unsigned int offset;
2818 };
2819
2820 static unsigned int ich_codec_bits[3] = {
2821 ICH_PCR, ICH_SCR, ICH_TCR
2822 };
2823 static unsigned int sis_codec_bits[3] = {
2824 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2825 };
2826
2827 static int __devinit snd_intel8x0_create(struct snd_card *card,
2828 struct pci_dev *pci,
2829 unsigned long device_type,
2830 struct intel8x0 ** r_intel8x0)
2831 {
2832 struct intel8x0 *chip;
2833 int err;
2834 unsigned int i;
2835 unsigned int int_sta_masks;
2836 struct ichdev *ichdev;
2837 static struct snd_device_ops ops = {
2838 .dev_free = snd_intel8x0_dev_free,
2839 };
2840
2841 static unsigned int bdbars[] = {
2842 3, /* DEVICE_INTEL */
2843 6, /* DEVICE_INTEL_ICH4 */
2844 3, /* DEVICE_SIS */
2845 6, /* DEVICE_ALI */
2846 4, /* DEVICE_NFORCE */
2847 };
2848 static struct ich_reg_info intel_regs[6] = {
2849 { ICH_PIINT, 0 },
2850 { ICH_POINT, 0x10 },
2851 { ICH_MCINT, 0x20 },
2852 { ICH_M2INT, 0x40 },
2853 { ICH_P2INT, 0x50 },
2854 { ICH_SPINT, 0x60 },
2855 };
2856 static struct ich_reg_info nforce_regs[4] = {
2857 { ICH_PIINT, 0 },
2858 { ICH_POINT, 0x10 },
2859 { ICH_MCINT, 0x20 },
2860 { ICH_NVSPINT, 0x70 },
2861 };
2862 static struct ich_reg_info ali_regs[6] = {
2863 { ALI_INT_PCMIN, 0x40 },
2864 { ALI_INT_PCMOUT, 0x50 },
2865 { ALI_INT_MICIN, 0x60 },
2866 { ALI_INT_CODECSPDIFOUT, 0x70 },
2867 { ALI_INT_SPDIFIN, 0xa0 },
2868 { ALI_INT_SPDIFOUT, 0xb0 },
2869 };
2870 struct ich_reg_info *tbl;
2871
2872 *r_intel8x0 = NULL;
2873
2874 if ((err = pci_enable_device(pci)) < 0)
2875 return err;
2876
2877 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2878 if (chip == NULL) {
2879 pci_disable_device(pci);
2880 return -ENOMEM;
2881 }
2882 spin_lock_init(&chip->reg_lock);
2883 chip->device_type = device_type;
2884 chip->card = card;
2885 chip->pci = pci;
2886 chip->irq = -1;
2887
2888 /* module parameters */
2889 chip->buggy_irq = buggy_irq;
2890 chip->buggy_semaphore = buggy_semaphore;
2891 if (xbox)
2892 chip->xbox = 1;
2893
2894 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2895 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2896 chip->fix_nocache = 1; /* enable workaround */
2897
2898 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2899 kfree(chip);
2900 pci_disable_device(pci);
2901 return err;
2902 }
2903
2904 if (device_type == DEVICE_ALI) {
2905 /* ALI5455 has no ac97 region */
2906 chip->bmaddr = pci_iomap(pci, 0, 0);
2907 goto port_inited;
2908 }
2909
2910 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2911 chip->addr = pci_iomap(pci, 2, 0);
2912 else
2913 chip->addr = pci_iomap(pci, 0, 0);
2914 if (!chip->addr) {
2915 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2916 snd_intel8x0_free(chip);
2917 return -EIO;
2918 }
2919 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2920 chip->bmaddr = pci_iomap(pci, 3, 0);
2921 else
2922 chip->bmaddr = pci_iomap(pci, 1, 0);
2923 if (!chip->bmaddr) {
2924 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2925 snd_intel8x0_free(chip);
2926 return -EIO;
2927 }
2928
2929 port_inited:
2930 chip->bdbars_count = bdbars[device_type];
2931
2932 /* initialize offsets */
2933 switch (device_type) {
2934 case DEVICE_NFORCE:
2935 tbl = nforce_regs;
2936 break;
2937 case DEVICE_ALI:
2938 tbl = ali_regs;
2939 break;
2940 default:
2941 tbl = intel_regs;
2942 break;
2943 }
2944 for (i = 0; i < chip->bdbars_count; i++) {
2945 ichdev = &chip->ichd[i];
2946 ichdev->ichd = i;
2947 ichdev->reg_offset = tbl[i].offset;
2948 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2949 if (device_type == DEVICE_SIS) {
2950 /* SiS 7012 swaps the registers */
2951 ichdev->roff_sr = ICH_REG_OFF_PICB;
2952 ichdev->roff_picb = ICH_REG_OFF_SR;
2953 } else {
2954 ichdev->roff_sr = ICH_REG_OFF_SR;
2955 ichdev->roff_picb = ICH_REG_OFF_PICB;
2956 }
2957 if (device_type == DEVICE_ALI)
2958 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2959 /* SIS7012 handles the pcm data in bytes, others are in samples */
2960 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2961 }
2962
2963 /* allocate buffer descriptor lists */
2964 /* the start of each lists must be aligned to 8 bytes */
2965 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2966 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2967 &chip->bdbars) < 0) {
2968 snd_intel8x0_free(chip);
2969 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2970 return -ENOMEM;
2971 }
2972 /* tables must be aligned to 8 bytes here, but the kernel pages
2973 are much bigger, so we don't care (on i386) */
2974 /* workaround for 440MX */
2975 if (chip->fix_nocache)
2976 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2977 int_sta_masks = 0;
2978 for (i = 0; i < chip->bdbars_count; i++) {
2979 ichdev = &chip->ichd[i];
2980 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2981 (i * ICH_MAX_FRAGS * 2);
2982 ichdev->bdbar_addr = chip->bdbars.addr +
2983 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2984 int_sta_masks |= ichdev->int_sta_mask;
2985 }
2986 chip->int_sta_reg = device_type == DEVICE_ALI ?
2987 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2988 chip->int_sta_mask = int_sta_masks;
2989
2990 pci_set_master(pci);
2991
2992 switch(chip->device_type) {
2993 case DEVICE_INTEL_ICH4:
2994 /* ICH4 can have three codecs */
2995 chip->max_codecs = 3;
2996 chip->codec_bit = ich_codec_bits;
2997 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2998 break;
2999 case DEVICE_SIS:
3000 /* recent SIS7012 can have three codecs */
3001 chip->max_codecs = 3;
3002 chip->codec_bit = sis_codec_bits;
3003 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3004 break;
3005 default:
3006 /* others up to two codecs */
3007 chip->max_codecs = 2;
3008 chip->codec_bit = ich_codec_bits;
3009 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3010 break;
3011 }
3012 for (i = 0; i < chip->max_codecs; i++)
3013 chip->codec_isr_bits |= chip->codec_bit[i];
3014
3015 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3016 snd_intel8x0_free(chip);
3017 return err;
3018 }
3019
3020 /* request irq after initializaing int_sta_mask, etc */
3021 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3022 IRQF_SHARED, card->shortname, chip)) {
3023 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3024 snd_intel8x0_free(chip);
3025 return -EBUSY;
3026 }
3027 chip->irq = pci->irq;
3028
3029 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3030 snd_intel8x0_free(chip);
3031 return err;
3032 }
3033
3034 snd_card_set_dev(card, &pci->dev);
3035
3036 *r_intel8x0 = chip;
3037 return 0;
3038 }
3039
3040 static struct shortname_table {
3041 unsigned int id;
3042 const char *s;
3043 } shortnames[] __devinitdata = {
3044 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3045 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3046 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3047 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3048 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3049 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3050 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3051 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3052 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3053 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3054 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3055 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3056 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3057 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3058 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3059 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3060 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3061 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3062 { 0x003a, "NVidia MCP04" },
3063 { 0x746d, "AMD AMD8111" },
3064 { 0x7445, "AMD AMD768" },
3065 { 0x5455, "ALi M5455" },
3066 { 0, NULL },
3067 };
3068
3069 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3070 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3071 { } /* end */
3072 };
3073
3074 /* look up white/black list for SPDIF over ac-link */
3075 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3076 {
3077 const struct snd_pci_quirk *w;
3078
3079 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3080 if (w) {
3081 if (w->value)
3082 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3083 "AC-Link for %s\n", w->name);
3084 else
3085 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3086 "SPDIF DMA for %s\n", w->name);
3087 return w->value;
3088 }
3089 return 0;
3090 }
3091
3092 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3093 const struct pci_device_id *pci_id)
3094 {
3095 struct snd_card *card;
3096 struct intel8x0 *chip;
3097 int err;
3098 struct shortname_table *name;
3099
3100 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3101 if (err < 0)
3102 return err;
3103
3104 if (spdif_aclink < 0)
3105 spdif_aclink = check_default_spdif_aclink(pci);
3106
3107 strcpy(card->driver, "ICH");
3108 if (!spdif_aclink) {
3109 switch (pci_id->driver_data) {
3110 case DEVICE_NFORCE:
3111 strcpy(card->driver, "NFORCE");
3112 break;
3113 case DEVICE_INTEL_ICH4:
3114 strcpy(card->driver, "ICH4");
3115 }
3116 }
3117
3118 strcpy(card->shortname, "Intel ICH");
3119 for (name = shortnames; name->id; name++) {
3120 if (pci->device == name->id) {
3121 strcpy(card->shortname, name->s);
3122 break;
3123 }
3124 }
3125
3126 if (buggy_irq < 0) {
3127 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3128 * Needs to return IRQ_HANDLED for unknown irqs.
3129 */
3130 if (pci_id->driver_data == DEVICE_NFORCE)
3131 buggy_irq = 1;
3132 else
3133 buggy_irq = 0;
3134 }
3135
3136 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3137 &chip)) < 0) {
3138 snd_card_free(card);
3139 return err;
3140 }
3141 card->private_data = chip;
3142
3143 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3144 snd_card_free(card);
3145 return err;
3146 }
3147 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3148 snd_card_free(card);
3149 return err;
3150 }
3151
3152 snd_intel8x0_proc_init(chip);
3153
3154 snprintf(card->longname, sizeof(card->longname),
3155 "%s with %s at irq %i", card->shortname,
3156 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3157
3158 if (ac97_clock == 0 || ac97_clock == 1) {
3159 if (ac97_clock == 0) {
3160 if (intel8x0_in_clock_list(chip) == 0)
3161 intel8x0_measure_ac97_clock(chip);
3162 } else {
3163 intel8x0_measure_ac97_clock(chip);
3164 }
3165 }
3166
3167 if ((err = snd_card_register(card)) < 0) {
3168 snd_card_free(card);
3169 return err;
3170 }
3171 pci_set_drvdata(pci, card);
3172 return 0;
3173 }
3174
3175 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3176 {
3177 snd_card_free(pci_get_drvdata(pci));
3178 pci_set_drvdata(pci, NULL);
3179 }
3180
3181 static struct pci_driver driver = {
3182 .name = "Intel ICH",
3183 .id_table = snd_intel8x0_ids,
3184 .probe = snd_intel8x0_probe,
3185 .remove = __devexit_p(snd_intel8x0_remove),
3186 #ifdef CONFIG_PM
3187 .suspend = intel8x0_suspend,
3188 .resume = intel8x0_resume,
3189 #endif
3190 };
3191
3192
3193 static int __init alsa_card_intel8x0_init(void)
3194 {
3195 return pci_register_driver(&driver);
3196 }
3197
3198 static void __exit alsa_card_intel8x0_exit(void)
3199 {
3200 pci_unregister_driver(&driver);
3201 }
3202
3203 module_init(alsa_card_intel8x0_init)
3204 module_exit(alsa_card_intel8x0_exit)
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