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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy...
[mirror_ubuntu-zesty-kernel.git] / sound / pci / intel8x0.c
1 /*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29 #include <sound/driver.h>
30 #include <asm/io.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/moduleparam.h>
37 #include <sound/core.h>
38 #include <sound/pcm.h>
39 #include <sound/ac97_codec.h>
40 #include <sound/info.h>
41 #include <sound/initval.h>
42 /* for 440MX workaround */
43 #include <asm/pgtable.h>
44 #include <asm/cacheflush.h>
45
46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
58 "{Intel,ESB2},"
59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
67 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
68 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
69 static int ac97_clock;
70 static char *ac97_quirk;
71 static int buggy_semaphore;
72 static int buggy_irq = -1; /* auto-check */
73 static int xbox;
74 static int spdif_aclink = -1;
75
76 module_param(index, int, 0444);
77 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
78 module_param(id, charp, 0444);
79 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
80 module_param(ac97_clock, int, 0444);
81 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
82 module_param(ac97_quirk, charp, 0444);
83 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
84 module_param(buggy_semaphore, bool, 0444);
85 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
86 module_param(buggy_irq, bool, 0444);
87 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
88 module_param(xbox, bool, 0444);
89 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
90 module_param(spdif_aclink, int, 0444);
91 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
92
93 /* just for backward compatibility */
94 static int enable;
95 module_param(enable, bool, 0444);
96 static int joystick;
97 module_param(joystick, int, 0444);
98
99 /*
100 * Direct registers
101 */
102 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
103
104 #define ICHREG(x) ICH_REG_##x
105
106 #define DEFINE_REGSET(name,base) \
107 enum { \
108 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
109 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
110 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
111 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
112 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
113 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
114 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
115 };
116
117 /* busmaster blocks */
118 DEFINE_REGSET(OFF, 0); /* offset */
119 DEFINE_REGSET(PI, 0x00); /* PCM in */
120 DEFINE_REGSET(PO, 0x10); /* PCM out */
121 DEFINE_REGSET(MC, 0x20); /* Mic in */
122
123 /* ICH4 busmaster blocks */
124 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
125 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
126 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
127
128 /* values for each busmaster block */
129
130 /* LVI */
131 #define ICH_REG_LVI_MASK 0x1f
132
133 /* SR */
134 #define ICH_FIFOE 0x10 /* FIFO error */
135 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
136 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
137 #define ICH_CELV 0x02 /* current equals last valid */
138 #define ICH_DCH 0x01 /* DMA controller halted */
139
140 /* PIV */
141 #define ICH_REG_PIV_MASK 0x1f /* mask */
142
143 /* CR */
144 #define ICH_IOCE 0x10 /* interrupt on completion enable */
145 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
146 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
147 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
148 #define ICH_STARTBM 0x01 /* start busmaster operation */
149
150
151 /* global block */
152 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
153 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
154 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
155 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
156 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
157 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
158 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
159 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
160 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
161 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
162 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
163 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
164 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
165 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
166 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
167 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
168 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
169 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
170 #define ICH_ACLINK 0x00000008 /* AClink shut off */
171 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
172 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
173 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
174 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
175 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
176 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
177 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
178 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
179 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
180 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
181 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
182 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
183 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
184 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
185 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
186 #define ICH_MD3 0x00020000 /* modem power down semaphore */
187 #define ICH_AD3 0x00010000 /* audio power down semaphore */
188 #define ICH_RCS 0x00008000 /* read completion status */
189 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
190 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
191 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
192 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
193 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
194 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
195 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
196 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
197 #define ICH_POINT 0x00000040 /* playback interrupt */
198 #define ICH_PIINT 0x00000020 /* capture interrupt */
199 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
200 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
201 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
202 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
203 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
204 #define ICH_CAS 0x01 /* codec access semaphore */
205 #define ICH_REG_SDM 0x80
206 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
207 #define ICH_DI2L_SHIFT 6
208 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
209 #define ICH_DI1L_SHIFT 4
210 #define ICH_SE 0x00000008 /* steer enable */
211 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
212
213 #define ICH_MAX_FRAGS 32 /* max hw frags */
214
215
216 /*
217 * registers for Ali5455
218 */
219
220 /* ALi 5455 busmaster blocks */
221 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
222 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
223 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
224 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
225 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
226 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
227 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
228 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
229 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
230 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
231 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
232
233 enum {
234 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
235 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
236 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
237 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
238 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
239 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
240 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
241 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
242 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
243 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
244 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
245 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
246 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
247 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
248 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
249 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
250 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
251 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
252 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
253 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
254 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
255 };
256
257 #define ALI_CAS_SEM_BUSY 0x80000000
258 #define ALI_CPR_ADDR_SECONDARY 0x100
259 #define ALI_CPR_ADDR_READ 0x80
260 #define ALI_CSPSR_CODEC_READY 0x08
261 #define ALI_CSPSR_READ_OK 0x02
262 #define ALI_CSPSR_WRITE_OK 0x01
263
264 /* interrupts for the whole chip by interrupt status register finish */
265
266 #define ALI_INT_MICIN2 (1<<26)
267 #define ALI_INT_PCMIN2 (1<<25)
268 #define ALI_INT_I2SIN (1<<24)
269 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
270 #define ALI_INT_SPDIFIN (1<<22)
271 #define ALI_INT_LFEOUT (1<<21)
272 #define ALI_INT_CENTEROUT (1<<20)
273 #define ALI_INT_CODECSPDIFOUT (1<<19)
274 #define ALI_INT_MICIN (1<<18)
275 #define ALI_INT_PCMOUT (1<<17)
276 #define ALI_INT_PCMIN (1<<16)
277 #define ALI_INT_CPRAIS (1<<7) /* command port available */
278 #define ALI_INT_SPRAIS (1<<5) /* status port available */
279 #define ALI_INT_GPIO (1<<1)
280 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
281 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
282
283 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
284 #define ICH_ALI_SC_AC97_DBL (1<<30)
285 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
286 #define ICH_ALI_SC_IN_BITS (3<<18)
287 #define ICH_ALI_SC_OUT_BITS (3<<16)
288 #define ICH_ALI_SC_6CH_CFG (3<<14)
289 #define ICH_ALI_SC_PCM_4 (1<<8)
290 #define ICH_ALI_SC_PCM_6 (2<<8)
291 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
292
293 #define ICH_ALI_SS_SEC_ID (3<<5)
294 #define ICH_ALI_SS_PRI_ID (3<<3)
295
296 #define ICH_ALI_IF_AC97SP (1<<21)
297 #define ICH_ALI_IF_MC (1<<20)
298 #define ICH_ALI_IF_PI (1<<19)
299 #define ICH_ALI_IF_MC2 (1<<18)
300 #define ICH_ALI_IF_PI2 (1<<17)
301 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
302 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
303 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
304 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
305 #define ICH_ALI_IF_PO_SPDF (1<<3)
306 #define ICH_ALI_IF_PO (1<<1)
307
308 /*
309 *
310 */
311
312 enum {
313 ICHD_PCMIN,
314 ICHD_PCMOUT,
315 ICHD_MIC,
316 ICHD_MIC2,
317 ICHD_PCM2IN,
318 ICHD_SPBAR,
319 ICHD_LAST = ICHD_SPBAR
320 };
321 enum {
322 NVD_PCMIN,
323 NVD_PCMOUT,
324 NVD_MIC,
325 NVD_SPBAR,
326 NVD_LAST = NVD_SPBAR
327 };
328 enum {
329 ALID_PCMIN,
330 ALID_PCMOUT,
331 ALID_MIC,
332 ALID_AC97SPDIFOUT,
333 ALID_SPDIFIN,
334 ALID_SPDIFOUT,
335 ALID_LAST = ALID_SPDIFOUT
336 };
337
338 #define get_ichdev(substream) (substream->runtime->private_data)
339
340 struct ichdev {
341 unsigned int ichd; /* ich device number */
342 unsigned long reg_offset; /* offset to bmaddr */
343 u32 *bdbar; /* CPU address (32bit) */
344 unsigned int bdbar_addr; /* PCI bus address (32bit) */
345 struct snd_pcm_substream *substream;
346 unsigned int physbuf; /* physical address (32bit) */
347 unsigned int size;
348 unsigned int fragsize;
349 unsigned int fragsize1;
350 unsigned int position;
351 unsigned int pos_shift;
352 int frags;
353 int lvi;
354 int lvi_frag;
355 int civ;
356 int ack;
357 int ack_reload;
358 unsigned int ack_bit;
359 unsigned int roff_sr;
360 unsigned int roff_picb;
361 unsigned int int_sta_mask; /* interrupt status mask */
362 unsigned int ali_slot; /* ALI DMA slot */
363 struct ac97_pcm *pcm;
364 int pcm_open_flag;
365 unsigned int page_attr_changed: 1;
366 unsigned int suspended: 1;
367 };
368
369 struct intel8x0 {
370 unsigned int device_type;
371
372 int irq;
373
374 void __iomem *addr;
375 void __iomem *bmaddr;
376
377 struct pci_dev *pci;
378 struct snd_card *card;
379
380 int pcm_devs;
381 struct snd_pcm *pcm[6];
382 struct ichdev ichd[6];
383
384 unsigned multi4: 1,
385 multi6: 1,
386 dra: 1,
387 smp20bit: 1;
388 unsigned in_ac97_init: 1,
389 in_sdin_init: 1;
390 unsigned in_measurement: 1; /* during ac97 clock measurement */
391 unsigned fix_nocache: 1; /* workaround for 440MX */
392 unsigned buggy_irq: 1; /* workaround for buggy mobos */
393 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
394 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
395
396 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
397 unsigned int sdm_saved; /* SDM reg value */
398
399 struct snd_ac97_bus *ac97_bus;
400 struct snd_ac97 *ac97[3];
401 unsigned int ac97_sdin[3];
402 unsigned int max_codecs, ncodecs;
403 unsigned int *codec_bit;
404 unsigned int codec_isr_bits;
405 unsigned int codec_ready_bits;
406
407 spinlock_t reg_lock;
408
409 u32 bdbars_count;
410 struct snd_dma_buffer bdbars;
411 u32 int_sta_reg; /* interrupt status register */
412 u32 int_sta_mask; /* interrupt status mask */
413 };
414
415 static struct pci_device_id snd_intel8x0_ids[] = {
416 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
417 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
418 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
419 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
420 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
421 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
422 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
423 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
424 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
425 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
426 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
427 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
428 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
429 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
430 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
431 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
432 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
433 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
434 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
435 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
436 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
437 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
438 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
439 { 0, }
440 };
441
442 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
443
444 /*
445 * Lowlevel I/O - busmaster
446 */
447
448 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
449 {
450 return ioread8(chip->bmaddr + offset);
451 }
452
453 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
454 {
455 return ioread16(chip->bmaddr + offset);
456 }
457
458 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
459 {
460 return ioread32(chip->bmaddr + offset);
461 }
462
463 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
464 {
465 iowrite8(val, chip->bmaddr + offset);
466 }
467
468 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
469 {
470 iowrite16(val, chip->bmaddr + offset);
471 }
472
473 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
474 {
475 iowrite32(val, chip->bmaddr + offset);
476 }
477
478 /*
479 * Lowlevel I/O - AC'97 registers
480 */
481
482 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
483 {
484 return ioread16(chip->addr + offset);
485 }
486
487 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
488 {
489 iowrite16(val, chip->addr + offset);
490 }
491
492 /*
493 * Basic I/O
494 */
495
496 /*
497 * access to AC97 codec via normal i/o (for ICH and SIS7012)
498 */
499
500 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
501 {
502 int time;
503
504 if (codec > 2)
505 return -EIO;
506 if (chip->in_sdin_init) {
507 /* we don't know the ready bit assignment at the moment */
508 /* so we check any */
509 codec = chip->codec_isr_bits;
510 } else {
511 codec = chip->codec_bit[chip->ac97_sdin[codec]];
512 }
513
514 /* codec ready ? */
515 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
516 return -EIO;
517
518 if (chip->buggy_semaphore)
519 return 0; /* just ignore ... */
520
521 /* Anyone holding a semaphore for 1 msec should be shot... */
522 time = 100;
523 do {
524 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
525 return 0;
526 udelay(10);
527 } while (time--);
528
529 /* access to some forbidden (non existant) ac97 registers will not
530 * reset the semaphore. So even if you don't get the semaphore, still
531 * continue the access. We don't need the semaphore anyway. */
532 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
533 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
534 iagetword(chip, 0); /* clear semaphore flag */
535 /* I don't care about the semaphore */
536 return -EBUSY;
537 }
538
539 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
540 unsigned short reg,
541 unsigned short val)
542 {
543 struct intel8x0 *chip = ac97->private_data;
544
545 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
546 if (! chip->in_ac97_init)
547 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
548 }
549 iaputword(chip, reg + ac97->num * 0x80, val);
550 }
551
552 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
553 unsigned short reg)
554 {
555 struct intel8x0 *chip = ac97->private_data;
556 unsigned short res;
557 unsigned int tmp;
558
559 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
560 if (! chip->in_ac97_init)
561 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
562 res = 0xffff;
563 } else {
564 res = iagetword(chip, reg + ac97->num * 0x80);
565 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
566 /* reset RCS and preserve other R/WC bits */
567 iputdword(chip, ICHREG(GLOB_STA), tmp &
568 ~(chip->codec_ready_bits | ICH_GSCI));
569 if (! chip->in_ac97_init)
570 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
571 res = 0xffff;
572 }
573 }
574 return res;
575 }
576
577 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
578 unsigned int codec)
579 {
580 unsigned int tmp;
581
582 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
583 iagetword(chip, codec * 0x80);
584 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
585 /* reset RCS and preserve other R/WC bits */
586 iputdword(chip, ICHREG(GLOB_STA), tmp &
587 ~(chip->codec_ready_bits | ICH_GSCI));
588 }
589 }
590 }
591
592 /*
593 * access to AC97 for Ali5455
594 */
595 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
596 {
597 int count = 0;
598 for (count = 0; count < 0x7f; count++) {
599 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
600 if (val & mask)
601 return 0;
602 }
603 if (! chip->in_ac97_init)
604 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
605 return -EBUSY;
606 }
607
608 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
609 {
610 int time = 100;
611 if (chip->buggy_semaphore)
612 return 0; /* just ignore ... */
613 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
614 udelay(1);
615 if (! time && ! chip->in_ac97_init)
616 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
617 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
618 }
619
620 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
621 {
622 struct intel8x0 *chip = ac97->private_data;
623 unsigned short data = 0xffff;
624
625 if (snd_intel8x0_ali_codec_semaphore(chip))
626 goto __err;
627 reg |= ALI_CPR_ADDR_READ;
628 if (ac97->num)
629 reg |= ALI_CPR_ADDR_SECONDARY;
630 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
631 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
632 goto __err;
633 data = igetword(chip, ICHREG(ALI_SPR));
634 __err:
635 return data;
636 }
637
638 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
639 unsigned short val)
640 {
641 struct intel8x0 *chip = ac97->private_data;
642
643 if (snd_intel8x0_ali_codec_semaphore(chip))
644 return;
645 iputword(chip, ICHREG(ALI_CPR), val);
646 if (ac97->num)
647 reg |= ALI_CPR_ADDR_SECONDARY;
648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
649 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
650 }
651
652
653 /*
654 * DMA I/O
655 */
656 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
657 {
658 int idx;
659 u32 *bdbar = ichdev->bdbar;
660 unsigned long port = ichdev->reg_offset;
661
662 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
663 if (ichdev->size == ichdev->fragsize) {
664 ichdev->ack_reload = ichdev->ack = 2;
665 ichdev->fragsize1 = ichdev->fragsize >> 1;
666 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
667 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
668 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
669 ichdev->fragsize1 >> ichdev->pos_shift);
670 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
671 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
672 ichdev->fragsize1 >> ichdev->pos_shift);
673 }
674 ichdev->frags = 2;
675 } else {
676 ichdev->ack_reload = ichdev->ack = 1;
677 ichdev->fragsize1 = ichdev->fragsize;
678 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
679 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
680 (((idx >> 1) * ichdev->fragsize) %
681 ichdev->size));
682 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
683 ichdev->fragsize >> ichdev->pos_shift);
684 #if 0
685 printk("bdbar[%i] = 0x%x [0x%x]\n",
686 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
687 #endif
688 }
689 ichdev->frags = ichdev->size / ichdev->fragsize;
690 }
691 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
692 ichdev->civ = 0;
693 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
694 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
695 ichdev->position = 0;
696 #if 0
697 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
698 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
699 #endif
700 /* clear interrupts */
701 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
702 }
703
704 #ifdef __i386__
705 /*
706 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
707 * which aborts PCI busmaster for audio transfer. A workaround is to set
708 * the pages as non-cached. For details, see the errata in
709 * http://www.intel.com/design/chipsets/specupdt/245051.htm
710 */
711 static void fill_nocache(void *buf, int size, int nocache)
712 {
713 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
714 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
715 global_flush_tlb();
716 }
717 #else
718 #define fill_nocache(buf,size,nocache)
719 #endif
720
721 /*
722 * Interrupt handler
723 */
724
725 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
726 {
727 unsigned long port = ichdev->reg_offset;
728 int status, civ, i, step;
729 int ack = 0;
730
731 spin_lock(&chip->reg_lock);
732 status = igetbyte(chip, port + ichdev->roff_sr);
733 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
734 if (!(status & ICH_BCIS)) {
735 step = 0;
736 } else if (civ == ichdev->civ) {
737 // snd_printd("civ same %d\n", civ);
738 step = 1;
739 ichdev->civ++;
740 ichdev->civ &= ICH_REG_LVI_MASK;
741 } else {
742 step = civ - ichdev->civ;
743 if (step < 0)
744 step += ICH_REG_LVI_MASK + 1;
745 // if (step != 1)
746 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
747 ichdev->civ = civ;
748 }
749
750 ichdev->position += step * ichdev->fragsize1;
751 if (! chip->in_measurement)
752 ichdev->position %= ichdev->size;
753 ichdev->lvi += step;
754 ichdev->lvi &= ICH_REG_LVI_MASK;
755 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
756 for (i = 0; i < step; i++) {
757 ichdev->lvi_frag++;
758 ichdev->lvi_frag %= ichdev->frags;
759 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
760 #if 0
761 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
762 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
763 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
764 inl(port + 4), inb(port + ICH_REG_OFF_CR));
765 #endif
766 if (--ichdev->ack == 0) {
767 ichdev->ack = ichdev->ack_reload;
768 ack = 1;
769 }
770 }
771 spin_unlock(&chip->reg_lock);
772 if (ack && ichdev->substream) {
773 snd_pcm_period_elapsed(ichdev->substream);
774 }
775 iputbyte(chip, port + ichdev->roff_sr,
776 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
777 }
778
779 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
780 {
781 struct intel8x0 *chip = dev_id;
782 struct ichdev *ichdev;
783 unsigned int status;
784 unsigned int i;
785
786 status = igetdword(chip, chip->int_sta_reg);
787 if (status == 0xffffffff) /* we are not yet resumed */
788 return IRQ_NONE;
789
790 if ((status & chip->int_sta_mask) == 0) {
791 if (status) {
792 /* ack */
793 iputdword(chip, chip->int_sta_reg, status);
794 if (! chip->buggy_irq)
795 status = 0;
796 }
797 return IRQ_RETVAL(status);
798 }
799
800 for (i = 0; i < chip->bdbars_count; i++) {
801 ichdev = &chip->ichd[i];
802 if (status & ichdev->int_sta_mask)
803 snd_intel8x0_update(chip, ichdev);
804 }
805
806 /* ack them */
807 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
808
809 return IRQ_HANDLED;
810 }
811
812 /*
813 * PCM part
814 */
815
816 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
817 {
818 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
819 struct ichdev *ichdev = get_ichdev(substream);
820 unsigned char val = 0;
821 unsigned long port = ichdev->reg_offset;
822
823 switch (cmd) {
824 case SNDRV_PCM_TRIGGER_RESUME:
825 ichdev->suspended = 0;
826 /* fallthru */
827 case SNDRV_PCM_TRIGGER_START:
828 val = ICH_IOCE | ICH_STARTBM;
829 break;
830 case SNDRV_PCM_TRIGGER_SUSPEND:
831 ichdev->suspended = 1;
832 /* fallthru */
833 case SNDRV_PCM_TRIGGER_STOP:
834 val = 0;
835 break;
836 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
837 val = ICH_IOCE;
838 break;
839 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
840 val = ICH_IOCE | ICH_STARTBM;
841 break;
842 default:
843 return -EINVAL;
844 }
845 iputbyte(chip, port + ICH_REG_OFF_CR, val);
846 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
847 /* wait until DMA stopped */
848 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
849 /* reset whole DMA things */
850 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
851 }
852 return 0;
853 }
854
855 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
856 {
857 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
858 struct ichdev *ichdev = get_ichdev(substream);
859 unsigned long port = ichdev->reg_offset;
860 static int fiforeg[] = {
861 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
862 };
863 unsigned int val, fifo;
864
865 val = igetdword(chip, ICHREG(ALI_DMACR));
866 switch (cmd) {
867 case SNDRV_PCM_TRIGGER_RESUME:
868 ichdev->suspended = 0;
869 /* fallthru */
870 case SNDRV_PCM_TRIGGER_START:
871 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
872 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
873 /* clear FIFO for synchronization of channels */
874 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
875 fifo &= ~(0xff << (ichdev->ali_slot % 4));
876 fifo |= 0x83 << (ichdev->ali_slot % 4);
877 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
878 }
879 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
880 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
881 /* start DMA */
882 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
883 break;
884 case SNDRV_PCM_TRIGGER_SUSPEND:
885 ichdev->suspended = 1;
886 /* fallthru */
887 case SNDRV_PCM_TRIGGER_STOP:
888 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
889 /* pause */
890 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
891 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
892 while (igetbyte(chip, port + ICH_REG_OFF_CR))
893 ;
894 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
895 break;
896 /* reset whole DMA things */
897 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
898 /* clear interrupts */
899 iputbyte(chip, port + ICH_REG_OFF_SR,
900 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
901 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
902 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
903 break;
904 default:
905 return -EINVAL;
906 }
907 return 0;
908 }
909
910 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
911 struct snd_pcm_hw_params *hw_params)
912 {
913 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
914 struct ichdev *ichdev = get_ichdev(substream);
915 struct snd_pcm_runtime *runtime = substream->runtime;
916 int dbl = params_rate(hw_params) > 48000;
917 int err;
918
919 if (chip->fix_nocache && ichdev->page_attr_changed) {
920 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
921 ichdev->page_attr_changed = 0;
922 }
923 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
924 if (err < 0)
925 return err;
926 if (chip->fix_nocache) {
927 if (runtime->dma_area && ! ichdev->page_attr_changed) {
928 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
929 ichdev->page_attr_changed = 1;
930 }
931 }
932 if (ichdev->pcm_open_flag) {
933 snd_ac97_pcm_close(ichdev->pcm);
934 ichdev->pcm_open_flag = 0;
935 }
936 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
937 params_channels(hw_params),
938 ichdev->pcm->r[dbl].slots);
939 if (err >= 0) {
940 ichdev->pcm_open_flag = 1;
941 /* Force SPDIF setting */
942 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
943 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
944 params_rate(hw_params));
945 }
946 return err;
947 }
948
949 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
950 {
951 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
952 struct ichdev *ichdev = get_ichdev(substream);
953
954 if (ichdev->pcm_open_flag) {
955 snd_ac97_pcm_close(ichdev->pcm);
956 ichdev->pcm_open_flag = 0;
957 }
958 if (chip->fix_nocache && ichdev->page_attr_changed) {
959 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
960 ichdev->page_attr_changed = 0;
961 }
962 return snd_pcm_lib_free_pages(substream);
963 }
964
965 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
966 struct snd_pcm_runtime *runtime)
967 {
968 unsigned int cnt;
969 int dbl = runtime->rate > 48000;
970
971 spin_lock_irq(&chip->reg_lock);
972 switch (chip->device_type) {
973 case DEVICE_ALI:
974 cnt = igetdword(chip, ICHREG(ALI_SCR));
975 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
976 if (runtime->channels == 4 || dbl)
977 cnt |= ICH_ALI_SC_PCM_4;
978 else if (runtime->channels == 6)
979 cnt |= ICH_ALI_SC_PCM_6;
980 iputdword(chip, ICHREG(ALI_SCR), cnt);
981 break;
982 case DEVICE_SIS:
983 cnt = igetdword(chip, ICHREG(GLOB_CNT));
984 cnt &= ~ICH_SIS_PCM_246_MASK;
985 if (runtime->channels == 4 || dbl)
986 cnt |= ICH_SIS_PCM_4;
987 else if (runtime->channels == 6)
988 cnt |= ICH_SIS_PCM_6;
989 iputdword(chip, ICHREG(GLOB_CNT), cnt);
990 break;
991 default:
992 cnt = igetdword(chip, ICHREG(GLOB_CNT));
993 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
994 if (runtime->channels == 4 || dbl)
995 cnt |= ICH_PCM_4;
996 else if (runtime->channels == 6)
997 cnt |= ICH_PCM_6;
998 if (chip->device_type == DEVICE_NFORCE) {
999 /* reset to 2ch once to keep the 6 channel data in alignment,
1000 * to start from Front Left always
1001 */
1002 if (cnt & ICH_PCM_246_MASK) {
1003 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1004 spin_unlock_irq(&chip->reg_lock);
1005 msleep(50); /* grrr... */
1006 spin_lock_irq(&chip->reg_lock);
1007 }
1008 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1009 if (runtime->sample_bits > 16)
1010 cnt |= ICH_PCM_20BIT;
1011 }
1012 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1013 break;
1014 }
1015 spin_unlock_irq(&chip->reg_lock);
1016 }
1017
1018 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1019 {
1020 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1021 struct snd_pcm_runtime *runtime = substream->runtime;
1022 struct ichdev *ichdev = get_ichdev(substream);
1023
1024 ichdev->physbuf = runtime->dma_addr;
1025 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1026 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1027 if (ichdev->ichd == ICHD_PCMOUT) {
1028 snd_intel8x0_setup_pcm_out(chip, runtime);
1029 if (chip->device_type == DEVICE_INTEL_ICH4)
1030 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1031 }
1032 snd_intel8x0_setup_periods(chip, ichdev);
1033 return 0;
1034 }
1035
1036 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1037 {
1038 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1039 struct ichdev *ichdev = get_ichdev(substream);
1040 size_t ptr1, ptr;
1041 int civ, timeout = 100;
1042 unsigned int position;
1043
1044 spin_lock(&chip->reg_lock);
1045 do {
1046 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1047 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1048 position = ichdev->position;
1049 if (ptr1 == 0) {
1050 udelay(10);
1051 continue;
1052 }
1053 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1054 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1055 break;
1056 } while (timeout--);
1057 ptr1 <<= ichdev->pos_shift;
1058 ptr = ichdev->fragsize1 - ptr1;
1059 ptr += position;
1060 spin_unlock(&chip->reg_lock);
1061 if (ptr >= ichdev->size)
1062 return 0;
1063 return bytes_to_frames(substream->runtime, ptr);
1064 }
1065
1066 static struct snd_pcm_hardware snd_intel8x0_stream =
1067 {
1068 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1069 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1070 SNDRV_PCM_INFO_MMAP_VALID |
1071 SNDRV_PCM_INFO_PAUSE |
1072 SNDRV_PCM_INFO_RESUME),
1073 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1074 .rates = SNDRV_PCM_RATE_48000,
1075 .rate_min = 48000,
1076 .rate_max = 48000,
1077 .channels_min = 2,
1078 .channels_max = 2,
1079 .buffer_bytes_max = 128 * 1024,
1080 .period_bytes_min = 32,
1081 .period_bytes_max = 128 * 1024,
1082 .periods_min = 1,
1083 .periods_max = 1024,
1084 .fifo_size = 0,
1085 };
1086
1087 static unsigned int channels4[] = {
1088 2, 4,
1089 };
1090
1091 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1092 .count = ARRAY_SIZE(channels4),
1093 .list = channels4,
1094 .mask = 0,
1095 };
1096
1097 static unsigned int channels6[] = {
1098 2, 4, 6,
1099 };
1100
1101 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1102 .count = ARRAY_SIZE(channels6),
1103 .list = channels6,
1104 .mask = 0,
1105 };
1106
1107 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1108 {
1109 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1110 struct snd_pcm_runtime *runtime = substream->runtime;
1111 int err;
1112
1113 ichdev->substream = substream;
1114 runtime->hw = snd_intel8x0_stream;
1115 runtime->hw.rates = ichdev->pcm->rates;
1116 snd_pcm_limit_hw_rates(runtime);
1117 if (chip->device_type == DEVICE_SIS) {
1118 runtime->hw.buffer_bytes_max = 64*1024;
1119 runtime->hw.period_bytes_max = 64*1024;
1120 }
1121 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1122 return err;
1123 runtime->private_data = ichdev;
1124 return 0;
1125 }
1126
1127 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1128 {
1129 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1130 struct snd_pcm_runtime *runtime = substream->runtime;
1131 int err;
1132
1133 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1134 if (err < 0)
1135 return err;
1136
1137 if (chip->multi6) {
1138 runtime->hw.channels_max = 6;
1139 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1140 &hw_constraints_channels6);
1141 } else if (chip->multi4) {
1142 runtime->hw.channels_max = 4;
1143 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1144 &hw_constraints_channels4);
1145 }
1146 if (chip->dra) {
1147 snd_ac97_pcm_double_rate_rules(runtime);
1148 }
1149 if (chip->smp20bit) {
1150 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1151 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1152 }
1153 return 0;
1154 }
1155
1156 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1157 {
1158 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1159
1160 chip->ichd[ICHD_PCMOUT].substream = NULL;
1161 return 0;
1162 }
1163
1164 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1165 {
1166 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1167
1168 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1169 }
1170
1171 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1172 {
1173 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1174
1175 chip->ichd[ICHD_PCMIN].substream = NULL;
1176 return 0;
1177 }
1178
1179 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1180 {
1181 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1182
1183 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1184 }
1185
1186 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1187 {
1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189
1190 chip->ichd[ICHD_MIC].substream = NULL;
1191 return 0;
1192 }
1193
1194 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1195 {
1196 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1197
1198 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1199 }
1200
1201 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1202 {
1203 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1204
1205 chip->ichd[ICHD_MIC2].substream = NULL;
1206 return 0;
1207 }
1208
1209 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1210 {
1211 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1212
1213 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1214 }
1215
1216 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1217 {
1218 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1219
1220 chip->ichd[ICHD_PCM2IN].substream = NULL;
1221 return 0;
1222 }
1223
1224 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1225 {
1226 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1228
1229 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1230 }
1231
1232 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1233 {
1234 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1235 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1236
1237 chip->ichd[idx].substream = NULL;
1238 return 0;
1239 }
1240
1241 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1242 {
1243 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1244 unsigned int val;
1245
1246 spin_lock_irq(&chip->reg_lock);
1247 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1248 val |= ICH_ALI_IF_AC97SP;
1249 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1250 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1251 spin_unlock_irq(&chip->reg_lock);
1252
1253 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1254 }
1255
1256 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1257 {
1258 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1259 unsigned int val;
1260
1261 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1262 spin_lock_irq(&chip->reg_lock);
1263 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1264 val &= ~ICH_ALI_IF_AC97SP;
1265 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1266 spin_unlock_irq(&chip->reg_lock);
1267
1268 return 0;
1269 }
1270
1271 #if 0 // NYI
1272 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1273 {
1274 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1275
1276 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1277 }
1278
1279 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1280 {
1281 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1282
1283 chip->ichd[ALID_SPDIFIN].substream = NULL;
1284 return 0;
1285 }
1286
1287 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1288 {
1289 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1290
1291 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1292 }
1293
1294 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1295 {
1296 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1297
1298 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1299 return 0;
1300 }
1301 #endif
1302
1303 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1304 .open = snd_intel8x0_playback_open,
1305 .close = snd_intel8x0_playback_close,
1306 .ioctl = snd_pcm_lib_ioctl,
1307 .hw_params = snd_intel8x0_hw_params,
1308 .hw_free = snd_intel8x0_hw_free,
1309 .prepare = snd_intel8x0_pcm_prepare,
1310 .trigger = snd_intel8x0_pcm_trigger,
1311 .pointer = snd_intel8x0_pcm_pointer,
1312 };
1313
1314 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1315 .open = snd_intel8x0_capture_open,
1316 .close = snd_intel8x0_capture_close,
1317 .ioctl = snd_pcm_lib_ioctl,
1318 .hw_params = snd_intel8x0_hw_params,
1319 .hw_free = snd_intel8x0_hw_free,
1320 .prepare = snd_intel8x0_pcm_prepare,
1321 .trigger = snd_intel8x0_pcm_trigger,
1322 .pointer = snd_intel8x0_pcm_pointer,
1323 };
1324
1325 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1326 .open = snd_intel8x0_mic_open,
1327 .close = snd_intel8x0_mic_close,
1328 .ioctl = snd_pcm_lib_ioctl,
1329 .hw_params = snd_intel8x0_hw_params,
1330 .hw_free = snd_intel8x0_hw_free,
1331 .prepare = snd_intel8x0_pcm_prepare,
1332 .trigger = snd_intel8x0_pcm_trigger,
1333 .pointer = snd_intel8x0_pcm_pointer,
1334 };
1335
1336 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1337 .open = snd_intel8x0_mic2_open,
1338 .close = snd_intel8x0_mic2_close,
1339 .ioctl = snd_pcm_lib_ioctl,
1340 .hw_params = snd_intel8x0_hw_params,
1341 .hw_free = snd_intel8x0_hw_free,
1342 .prepare = snd_intel8x0_pcm_prepare,
1343 .trigger = snd_intel8x0_pcm_trigger,
1344 .pointer = snd_intel8x0_pcm_pointer,
1345 };
1346
1347 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1348 .open = snd_intel8x0_capture2_open,
1349 .close = snd_intel8x0_capture2_close,
1350 .ioctl = snd_pcm_lib_ioctl,
1351 .hw_params = snd_intel8x0_hw_params,
1352 .hw_free = snd_intel8x0_hw_free,
1353 .prepare = snd_intel8x0_pcm_prepare,
1354 .trigger = snd_intel8x0_pcm_trigger,
1355 .pointer = snd_intel8x0_pcm_pointer,
1356 };
1357
1358 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1359 .open = snd_intel8x0_spdif_open,
1360 .close = snd_intel8x0_spdif_close,
1361 .ioctl = snd_pcm_lib_ioctl,
1362 .hw_params = snd_intel8x0_hw_params,
1363 .hw_free = snd_intel8x0_hw_free,
1364 .prepare = snd_intel8x0_pcm_prepare,
1365 .trigger = snd_intel8x0_pcm_trigger,
1366 .pointer = snd_intel8x0_pcm_pointer,
1367 };
1368
1369 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1370 .open = snd_intel8x0_playback_open,
1371 .close = snd_intel8x0_playback_close,
1372 .ioctl = snd_pcm_lib_ioctl,
1373 .hw_params = snd_intel8x0_hw_params,
1374 .hw_free = snd_intel8x0_hw_free,
1375 .prepare = snd_intel8x0_pcm_prepare,
1376 .trigger = snd_intel8x0_ali_trigger,
1377 .pointer = snd_intel8x0_pcm_pointer,
1378 };
1379
1380 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1381 .open = snd_intel8x0_capture_open,
1382 .close = snd_intel8x0_capture_close,
1383 .ioctl = snd_pcm_lib_ioctl,
1384 .hw_params = snd_intel8x0_hw_params,
1385 .hw_free = snd_intel8x0_hw_free,
1386 .prepare = snd_intel8x0_pcm_prepare,
1387 .trigger = snd_intel8x0_ali_trigger,
1388 .pointer = snd_intel8x0_pcm_pointer,
1389 };
1390
1391 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1392 .open = snd_intel8x0_mic_open,
1393 .close = snd_intel8x0_mic_close,
1394 .ioctl = snd_pcm_lib_ioctl,
1395 .hw_params = snd_intel8x0_hw_params,
1396 .hw_free = snd_intel8x0_hw_free,
1397 .prepare = snd_intel8x0_pcm_prepare,
1398 .trigger = snd_intel8x0_ali_trigger,
1399 .pointer = snd_intel8x0_pcm_pointer,
1400 };
1401
1402 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1403 .open = snd_intel8x0_ali_ac97spdifout_open,
1404 .close = snd_intel8x0_ali_ac97spdifout_close,
1405 .ioctl = snd_pcm_lib_ioctl,
1406 .hw_params = snd_intel8x0_hw_params,
1407 .hw_free = snd_intel8x0_hw_free,
1408 .prepare = snd_intel8x0_pcm_prepare,
1409 .trigger = snd_intel8x0_ali_trigger,
1410 .pointer = snd_intel8x0_pcm_pointer,
1411 };
1412
1413 #if 0 // NYI
1414 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1415 .open = snd_intel8x0_ali_spdifin_open,
1416 .close = snd_intel8x0_ali_spdifin_close,
1417 .ioctl = snd_pcm_lib_ioctl,
1418 .hw_params = snd_intel8x0_hw_params,
1419 .hw_free = snd_intel8x0_hw_free,
1420 .prepare = snd_intel8x0_pcm_prepare,
1421 .trigger = snd_intel8x0_pcm_trigger,
1422 .pointer = snd_intel8x0_pcm_pointer,
1423 };
1424
1425 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1426 .open = snd_intel8x0_ali_spdifout_open,
1427 .close = snd_intel8x0_ali_spdifout_close,
1428 .ioctl = snd_pcm_lib_ioctl,
1429 .hw_params = snd_intel8x0_hw_params,
1430 .hw_free = snd_intel8x0_hw_free,
1431 .prepare = snd_intel8x0_pcm_prepare,
1432 .trigger = snd_intel8x0_pcm_trigger,
1433 .pointer = snd_intel8x0_pcm_pointer,
1434 };
1435 #endif // NYI
1436
1437 struct ich_pcm_table {
1438 char *suffix;
1439 struct snd_pcm_ops *playback_ops;
1440 struct snd_pcm_ops *capture_ops;
1441 size_t prealloc_size;
1442 size_t prealloc_max_size;
1443 int ac97_idx;
1444 };
1445
1446 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1447 struct ich_pcm_table *rec)
1448 {
1449 struct snd_pcm *pcm;
1450 int err;
1451 char name[32];
1452
1453 if (rec->suffix)
1454 sprintf(name, "Intel ICH - %s", rec->suffix);
1455 else
1456 strcpy(name, "Intel ICH");
1457 err = snd_pcm_new(chip->card, name, device,
1458 rec->playback_ops ? 1 : 0,
1459 rec->capture_ops ? 1 : 0, &pcm);
1460 if (err < 0)
1461 return err;
1462
1463 if (rec->playback_ops)
1464 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1465 if (rec->capture_ops)
1466 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1467
1468 pcm->private_data = chip;
1469 pcm->info_flags = 0;
1470 if (rec->suffix)
1471 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1472 else
1473 strcpy(pcm->name, chip->card->shortname);
1474 chip->pcm[device] = pcm;
1475
1476 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1477 snd_dma_pci_data(chip->pci),
1478 rec->prealloc_size, rec->prealloc_max_size);
1479
1480 return 0;
1481 }
1482
1483 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1484 {
1485 .playback_ops = &snd_intel8x0_playback_ops,
1486 .capture_ops = &snd_intel8x0_capture_ops,
1487 .prealloc_size = 64 * 1024,
1488 .prealloc_max_size = 128 * 1024,
1489 },
1490 {
1491 .suffix = "MIC ADC",
1492 .capture_ops = &snd_intel8x0_capture_mic_ops,
1493 .prealloc_size = 0,
1494 .prealloc_max_size = 128 * 1024,
1495 .ac97_idx = ICHD_MIC,
1496 },
1497 {
1498 .suffix = "MIC2 ADC",
1499 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1500 .prealloc_size = 0,
1501 .prealloc_max_size = 128 * 1024,
1502 .ac97_idx = ICHD_MIC2,
1503 },
1504 {
1505 .suffix = "ADC2",
1506 .capture_ops = &snd_intel8x0_capture2_ops,
1507 .prealloc_size = 0,
1508 .prealloc_max_size = 128 * 1024,
1509 .ac97_idx = ICHD_PCM2IN,
1510 },
1511 {
1512 .suffix = "IEC958",
1513 .playback_ops = &snd_intel8x0_spdif_ops,
1514 .prealloc_size = 64 * 1024,
1515 .prealloc_max_size = 128 * 1024,
1516 .ac97_idx = ICHD_SPBAR,
1517 },
1518 };
1519
1520 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1521 {
1522 .playback_ops = &snd_intel8x0_playback_ops,
1523 .capture_ops = &snd_intel8x0_capture_ops,
1524 .prealloc_size = 64 * 1024,
1525 .prealloc_max_size = 128 * 1024,
1526 },
1527 {
1528 .suffix = "MIC ADC",
1529 .capture_ops = &snd_intel8x0_capture_mic_ops,
1530 .prealloc_size = 0,
1531 .prealloc_max_size = 128 * 1024,
1532 .ac97_idx = NVD_MIC,
1533 },
1534 {
1535 .suffix = "IEC958",
1536 .playback_ops = &snd_intel8x0_spdif_ops,
1537 .prealloc_size = 64 * 1024,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = NVD_SPBAR,
1540 },
1541 };
1542
1543 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1544 {
1545 .playback_ops = &snd_intel8x0_ali_playback_ops,
1546 .capture_ops = &snd_intel8x0_ali_capture_ops,
1547 .prealloc_size = 64 * 1024,
1548 .prealloc_max_size = 128 * 1024,
1549 },
1550 {
1551 .suffix = "MIC ADC",
1552 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1553 .prealloc_size = 0,
1554 .prealloc_max_size = 128 * 1024,
1555 .ac97_idx = ALID_MIC,
1556 },
1557 {
1558 .suffix = "IEC958",
1559 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1560 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1561 .prealloc_size = 64 * 1024,
1562 .prealloc_max_size = 128 * 1024,
1563 .ac97_idx = ALID_AC97SPDIFOUT,
1564 },
1565 #if 0 // NYI
1566 {
1567 .suffix = "HW IEC958",
1568 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1569 .prealloc_size = 64 * 1024,
1570 .prealloc_max_size = 128 * 1024,
1571 },
1572 #endif
1573 };
1574
1575 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1576 {
1577 int i, tblsize, device, err;
1578 struct ich_pcm_table *tbl, *rec;
1579
1580 switch (chip->device_type) {
1581 case DEVICE_INTEL_ICH4:
1582 tbl = intel_pcms;
1583 tblsize = ARRAY_SIZE(intel_pcms);
1584 if (spdif_aclink)
1585 tblsize--;
1586 break;
1587 case DEVICE_NFORCE:
1588 tbl = nforce_pcms;
1589 tblsize = ARRAY_SIZE(nforce_pcms);
1590 if (spdif_aclink)
1591 tblsize--;
1592 break;
1593 case DEVICE_ALI:
1594 tbl = ali_pcms;
1595 tblsize = ARRAY_SIZE(ali_pcms);
1596 break;
1597 default:
1598 tbl = intel_pcms;
1599 tblsize = 2;
1600 break;
1601 }
1602
1603 device = 0;
1604 for (i = 0; i < tblsize; i++) {
1605 rec = tbl + i;
1606 if (i > 0 && rec->ac97_idx) {
1607 /* activate PCM only when associated AC'97 codec */
1608 if (! chip->ichd[rec->ac97_idx].pcm)
1609 continue;
1610 }
1611 err = snd_intel8x0_pcm1(chip, device, rec);
1612 if (err < 0)
1613 return err;
1614 device++;
1615 }
1616
1617 chip->pcm_devs = device;
1618 return 0;
1619 }
1620
1621
1622 /*
1623 * Mixer part
1624 */
1625
1626 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1627 {
1628 struct intel8x0 *chip = bus->private_data;
1629 chip->ac97_bus = NULL;
1630 }
1631
1632 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1633 {
1634 struct intel8x0 *chip = ac97->private_data;
1635 chip->ac97[ac97->num] = NULL;
1636 }
1637
1638 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1639 /* front PCM */
1640 {
1641 .exclusive = 1,
1642 .r = { {
1643 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1644 (1 << AC97_SLOT_PCM_RIGHT) |
1645 (1 << AC97_SLOT_PCM_CENTER) |
1646 (1 << AC97_SLOT_PCM_SLEFT) |
1647 (1 << AC97_SLOT_PCM_SRIGHT) |
1648 (1 << AC97_SLOT_LFE)
1649 },
1650 {
1651 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1652 (1 << AC97_SLOT_PCM_RIGHT) |
1653 (1 << AC97_SLOT_PCM_LEFT_0) |
1654 (1 << AC97_SLOT_PCM_RIGHT_0)
1655 }
1656 }
1657 },
1658 /* PCM IN #1 */
1659 {
1660 .stream = 1,
1661 .exclusive = 1,
1662 .r = { {
1663 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1664 (1 << AC97_SLOT_PCM_RIGHT)
1665 }
1666 }
1667 },
1668 /* MIC IN #1 */
1669 {
1670 .stream = 1,
1671 .exclusive = 1,
1672 .r = { {
1673 .slots = (1 << AC97_SLOT_MIC)
1674 }
1675 }
1676 },
1677 /* S/PDIF PCM */
1678 {
1679 .exclusive = 1,
1680 .spdif = 1,
1681 .r = { {
1682 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1683 (1 << AC97_SLOT_SPDIF_RIGHT2)
1684 }
1685 }
1686 },
1687 /* PCM IN #2 */
1688 {
1689 .stream = 1,
1690 .exclusive = 1,
1691 .r = { {
1692 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1693 (1 << AC97_SLOT_PCM_RIGHT)
1694 }
1695 }
1696 },
1697 /* MIC IN #2 */
1698 {
1699 .stream = 1,
1700 .exclusive = 1,
1701 .r = { {
1702 .slots = (1 << AC97_SLOT_MIC)
1703 }
1704 }
1705 },
1706 };
1707
1708 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1709 {
1710 .subvendor = 0x0e11,
1711 .subdevice = 0x008a,
1712 .name = "Compaq Evo W4000", /* AD1885 */
1713 .type = AC97_TUNE_HP_ONLY
1714 },
1715 {
1716 .subvendor = 0x0e11,
1717 .subdevice = 0x00b8,
1718 .name = "Compaq Evo D510C",
1719 .type = AC97_TUNE_HP_ONLY
1720 },
1721 {
1722 .subvendor = 0x0e11,
1723 .subdevice = 0x0860,
1724 .name = "HP/Compaq nx7010",
1725 .type = AC97_TUNE_MUTE_LED
1726 },
1727 {
1728 .subvendor = 0x1014,
1729 .subdevice = 0x1f00,
1730 .name = "MS-9128",
1731 .type = AC97_TUNE_ALC_JACK
1732 },
1733 {
1734 .subvendor = 0x1014,
1735 .subdevice = 0x0267,
1736 .name = "IBM NetVista A30p", /* AD1981B */
1737 .type = AC97_TUNE_HP_ONLY
1738 },
1739 {
1740 .subvendor = 0x1025,
1741 .subdevice = 0x0083,
1742 .name = "Acer Aspire 3003LCi",
1743 .type = AC97_TUNE_HP_ONLY
1744 },
1745 {
1746 .subvendor = 0x1028,
1747 .subdevice = 0x00d8,
1748 .name = "Dell Precision 530", /* AD1885 */
1749 .type = AC97_TUNE_HP_ONLY
1750 },
1751 {
1752 .subvendor = 0x1028,
1753 .subdevice = 0x010d,
1754 .name = "Dell", /* which model? AD1885 */
1755 .type = AC97_TUNE_HP_ONLY
1756 },
1757 {
1758 .subvendor = 0x1028,
1759 .subdevice = 0x0126,
1760 .name = "Dell Optiplex GX260", /* AD1981A */
1761 .type = AC97_TUNE_HP_ONLY
1762 },
1763 {
1764 .subvendor = 0x1028,
1765 .subdevice = 0x012c,
1766 .name = "Dell Precision 650", /* AD1981A */
1767 .type = AC97_TUNE_HP_ONLY
1768 },
1769 {
1770 .subvendor = 0x1028,
1771 .subdevice = 0x012d,
1772 .name = "Dell Precision 450", /* AD1981B*/
1773 .type = AC97_TUNE_HP_ONLY
1774 },
1775 {
1776 .subvendor = 0x1028,
1777 .subdevice = 0x0147,
1778 .name = "Dell", /* which model? AD1981B*/
1779 .type = AC97_TUNE_HP_ONLY
1780 },
1781 {
1782 .subvendor = 0x1028,
1783 .subdevice = 0x0151,
1784 .name = "Dell Optiplex GX270", /* AD1981B */
1785 .type = AC97_TUNE_HP_ONLY
1786 },
1787 {
1788 .subvendor = 0x1028,
1789 .subdevice = 0x014e,
1790 .name = "Dell D800", /* STAC9750/51 */
1791 .type = AC97_TUNE_HP_ONLY
1792 },
1793 {
1794 .subvendor = 0x1028,
1795 .subdevice = 0x0163,
1796 .name = "Dell Unknown", /* STAC9750/51 */
1797 .type = AC97_TUNE_HP_ONLY
1798 },
1799 {
1800 .subvendor = 0x1028,
1801 .subdevice = 0x0191,
1802 .name = "Dell Inspiron 8600",
1803 .type = AC97_TUNE_HP_ONLY
1804 },
1805 {
1806 .subvendor = 0x103c,
1807 .subdevice = 0x006d,
1808 .name = "HP zv5000",
1809 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1810 },
1811 { /* FIXME: which codec? */
1812 .subvendor = 0x103c,
1813 .subdevice = 0x00c3,
1814 .name = "HP xw6000",
1815 .type = AC97_TUNE_HP_ONLY
1816 },
1817 {
1818 .subvendor = 0x103c,
1819 .subdevice = 0x088c,
1820 .name = "HP nc8000",
1821 .type = AC97_TUNE_MUTE_LED
1822 },
1823 {
1824 .subvendor = 0x103c,
1825 .subdevice = 0x0890,
1826 .name = "HP nc6000",
1827 .type = AC97_TUNE_MUTE_LED
1828 },
1829 {
1830 .subvendor = 0x103c,
1831 .subdevice = 0x0934,
1832 .name = "HP nx8220",
1833 .type = AC97_TUNE_MUTE_LED
1834 },
1835 {
1836 .subvendor = 0x103c,
1837 .subdevice = 0x129d,
1838 .name = "HP xw8000",
1839 .type = AC97_TUNE_HP_ONLY
1840 },
1841 {
1842 .subvendor = 0x103c,
1843 .subdevice = 0x0938,
1844 .name = "HP nc4200",
1845 .type = AC97_TUNE_HP_MUTE_LED
1846 },
1847 {
1848 .subvendor = 0x103c,
1849 .subdevice = 0x099c,
1850 .name = "HP nx6110/nc6120",
1851 .type = AC97_TUNE_HP_MUTE_LED
1852 },
1853 {
1854 .subvendor = 0x103c,
1855 .subdevice = 0x0944,
1856 .name = "HP nc6220",
1857 .type = AC97_TUNE_HP_MUTE_LED
1858 },
1859 {
1860 .subvendor = 0x103c,
1861 .subdevice = 0x0934,
1862 .name = "HP nc8220",
1863 .type = AC97_TUNE_HP_MUTE_LED
1864 },
1865 {
1866 .subvendor = 0x103c,
1867 .subdevice = 0x12f1,
1868 .name = "HP xw8200", /* AD1981B*/
1869 .type = AC97_TUNE_HP_ONLY
1870 },
1871 {
1872 .subvendor = 0x103c,
1873 .subdevice = 0x12f2,
1874 .name = "HP xw6200",
1875 .type = AC97_TUNE_HP_ONLY
1876 },
1877 {
1878 .subvendor = 0x103c,
1879 .subdevice = 0x3008,
1880 .name = "HP xw4200", /* AD1981B*/
1881 .type = AC97_TUNE_HP_ONLY
1882 },
1883 {
1884 .subvendor = 0x104d,
1885 .subdevice = 0x8197,
1886 .name = "Sony S1XP",
1887 .type = AC97_TUNE_INV_EAPD
1888 },
1889 {
1890 .subvendor = 0x1043,
1891 .subdevice = 0x80f3,
1892 .name = "ASUS ICH5/AD1985",
1893 .type = AC97_TUNE_AD_SHARING
1894 },
1895 {
1896 .subvendor = 0x10cf,
1897 .subdevice = 0x11c3,
1898 .name = "Fujitsu-Siemens E4010",
1899 .type = AC97_TUNE_HP_ONLY
1900 },
1901 {
1902 .subvendor = 0x10cf,
1903 .subdevice = 0x1225,
1904 .name = "Fujitsu-Siemens T3010",
1905 .type = AC97_TUNE_HP_ONLY
1906 },
1907 {
1908 .subvendor = 0x10cf,
1909 .subdevice = 0x1253,
1910 .name = "Fujitsu S6210", /* STAC9750/51 */
1911 .type = AC97_TUNE_HP_ONLY
1912 },
1913 {
1914 .subvendor = 0x10cf,
1915 .subdevice = 0x12ec,
1916 .name = "Fujitsu-Siemens 4010",
1917 .type = AC97_TUNE_HP_ONLY
1918 },
1919 {
1920 .subvendor = 0x10cf,
1921 .subdevice = 0x12f2,
1922 .name = "Fujitsu-Siemens Celsius H320",
1923 .type = AC97_TUNE_SWAP_HP
1924 },
1925 {
1926 .subvendor = 0x10f1,
1927 .subdevice = 0x2665,
1928 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1929 .type = AC97_TUNE_HP_ONLY
1930 },
1931 {
1932 .subvendor = 0x10f1,
1933 .subdevice = 0x2885,
1934 .name = "AMD64 Mobo", /* ALC650 */
1935 .type = AC97_TUNE_HP_ONLY
1936 },
1937 {
1938 .subvendor = 0x10f1,
1939 .subdevice = 0x2895,
1940 .name = "Tyan Thunder K8WE",
1941 .type = AC97_TUNE_HP_ONLY
1942 },
1943 {
1944 .subvendor = 0x10f7,
1945 .subdevice = 0x834c,
1946 .name = "Panasonic CF-R4",
1947 .type = AC97_TUNE_HP_ONLY,
1948 },
1949 {
1950 .subvendor = 0x110a,
1951 .subdevice = 0x0056,
1952 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1953 .type = AC97_TUNE_HP_ONLY
1954 },
1955 {
1956 .subvendor = 0x11d4,
1957 .subdevice = 0x5375,
1958 .name = "ADI AD1985 (discrete)",
1959 .type = AC97_TUNE_HP_ONLY
1960 },
1961 {
1962 .subvendor = 0x1462,
1963 .subdevice = 0x5470,
1964 .name = "MSI P4 ATX 645 Ultra",
1965 .type = AC97_TUNE_HP_ONLY
1966 },
1967 {
1968 .subvendor = 0x1734,
1969 .subdevice = 0x0088,
1970 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1971 .type = AC97_TUNE_HP_ONLY
1972 },
1973 {
1974 .subvendor = 0x8086,
1975 .subdevice = 0x2000,
1976 .mask = 0xfff0,
1977 .name = "Intel ICH5/AD1985",
1978 .type = AC97_TUNE_AD_SHARING
1979 },
1980 {
1981 .subvendor = 0x8086,
1982 .subdevice = 0x4000,
1983 .mask = 0xfff0,
1984 .name = "Intel ICH5/AD1985",
1985 .type = AC97_TUNE_AD_SHARING
1986 },
1987 {
1988 .subvendor = 0x8086,
1989 .subdevice = 0x4856,
1990 .name = "Intel D845WN (82801BA)",
1991 .type = AC97_TUNE_SWAP_HP
1992 },
1993 {
1994 .subvendor = 0x8086,
1995 .subdevice = 0x4d44,
1996 .name = "Intel D850EMV2", /* AD1885 */
1997 .type = AC97_TUNE_HP_ONLY
1998 },
1999 {
2000 .subvendor = 0x8086,
2001 .subdevice = 0x4d56,
2002 .name = "Intel ICH/AD1885",
2003 .type = AC97_TUNE_HP_ONLY
2004 },
2005 {
2006 .subvendor = 0x8086,
2007 .subdevice = 0x6000,
2008 .mask = 0xfff0,
2009 .name = "Intel ICH5/AD1985",
2010 .type = AC97_TUNE_AD_SHARING
2011 },
2012 {
2013 .subvendor = 0x8086,
2014 .subdevice = 0xe000,
2015 .mask = 0xfff0,
2016 .name = "Intel ICH5/AD1985",
2017 .type = AC97_TUNE_AD_SHARING
2018 },
2019 #if 0 /* FIXME: this seems wrong on most boards */
2020 {
2021 .subvendor = 0x8086,
2022 .subdevice = 0xa000,
2023 .mask = 0xfff0,
2024 .name = "Intel ICH5/AD1985",
2025 .type = AC97_TUNE_HP_ONLY
2026 },
2027 #endif
2028 { } /* terminator */
2029 };
2030
2031 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2032 const char *quirk_override)
2033 {
2034 struct snd_ac97_bus *pbus;
2035 struct snd_ac97_template ac97;
2036 int err;
2037 unsigned int i, codecs;
2038 unsigned int glob_sta = 0;
2039 struct snd_ac97_bus_ops *ops;
2040 static struct snd_ac97_bus_ops standard_bus_ops = {
2041 .write = snd_intel8x0_codec_write,
2042 .read = snd_intel8x0_codec_read,
2043 };
2044 static struct snd_ac97_bus_ops ali_bus_ops = {
2045 .write = snd_intel8x0_ali_codec_write,
2046 .read = snd_intel8x0_ali_codec_read,
2047 };
2048
2049 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2050 if (!spdif_aclink) {
2051 switch (chip->device_type) {
2052 case DEVICE_NFORCE:
2053 chip->spdif_idx = NVD_SPBAR;
2054 break;
2055 case DEVICE_ALI:
2056 chip->spdif_idx = ALID_AC97SPDIFOUT;
2057 break;
2058 case DEVICE_INTEL_ICH4:
2059 chip->spdif_idx = ICHD_SPBAR;
2060 break;
2061 };
2062 }
2063
2064 chip->in_ac97_init = 1;
2065
2066 memset(&ac97, 0, sizeof(ac97));
2067 ac97.private_data = chip;
2068 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2069 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2070 if (chip->xbox)
2071 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2072 if (chip->device_type != DEVICE_ALI) {
2073 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2074 ops = &standard_bus_ops;
2075 chip->in_sdin_init = 1;
2076 codecs = 0;
2077 for (i = 0; i < chip->max_codecs; i++) {
2078 if (! (glob_sta & chip->codec_bit[i]))
2079 continue;
2080 if (chip->device_type == DEVICE_INTEL_ICH4) {
2081 snd_intel8x0_codec_read_test(chip, codecs);
2082 chip->ac97_sdin[codecs] =
2083 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2084 snd_assert(chip->ac97_sdin[codecs] < 3,
2085 chip->ac97_sdin[codecs] = 0);
2086 } else
2087 chip->ac97_sdin[codecs] = i;
2088 codecs++;
2089 }
2090 chip->in_sdin_init = 0;
2091 if (! codecs)
2092 codecs = 1;
2093 } else {
2094 ops = &ali_bus_ops;
2095 codecs = 1;
2096 /* detect the secondary codec */
2097 for (i = 0; i < 100; i++) {
2098 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2099 if (reg & 0x40) {
2100 codecs = 2;
2101 break;
2102 }
2103 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2104 udelay(1);
2105 }
2106 }
2107 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2108 goto __err;
2109 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2110 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2111 pbus->clock = ac97_clock;
2112 /* FIXME: my test board doesn't work well with VRA... */
2113 if (chip->device_type == DEVICE_ALI)
2114 pbus->no_vra = 1;
2115 else
2116 pbus->dra = 1;
2117 chip->ac97_bus = pbus;
2118 chip->ncodecs = codecs;
2119
2120 ac97.pci = chip->pci;
2121 for (i = 0; i < codecs; i++) {
2122 ac97.num = i;
2123 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2124 if (err != -EACCES)
2125 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2126 if (i == 0)
2127 goto __err;
2128 continue;
2129 }
2130 }
2131 /* tune up the primary codec */
2132 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2133 /* enable separate SDINs for ICH4 */
2134 if (chip->device_type == DEVICE_INTEL_ICH4)
2135 pbus->isdin = 1;
2136 /* find the available PCM streams */
2137 i = ARRAY_SIZE(ac97_pcm_defs);
2138 if (chip->device_type != DEVICE_INTEL_ICH4)
2139 i -= 2; /* do not allocate PCM2IN and MIC2 */
2140 if (chip->spdif_idx < 0)
2141 i--; /* do not allocate S/PDIF */
2142 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2143 if (err < 0)
2144 goto __err;
2145 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2146 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2147 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2148 if (chip->spdif_idx >= 0)
2149 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2150 if (chip->device_type == DEVICE_INTEL_ICH4) {
2151 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2152 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2153 }
2154 /* enable separate SDINs for ICH4 */
2155 if (chip->device_type == DEVICE_INTEL_ICH4) {
2156 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2157 u8 tmp = igetbyte(chip, ICHREG(SDM));
2158 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2159 if (pcm) {
2160 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2161 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2162 for (i = 1; i < 4; i++) {
2163 if (pcm->r[0].codec[i]) {
2164 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2165 break;
2166 }
2167 }
2168 } else {
2169 tmp &= ~ICH_SE; /* steer disable */
2170 }
2171 iputbyte(chip, ICHREG(SDM), tmp);
2172 }
2173 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2174 chip->multi4 = 1;
2175 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2176 chip->multi6 = 1;
2177 }
2178 if (pbus->pcms[0].r[1].rslots[0]) {
2179 chip->dra = 1;
2180 }
2181 if (chip->device_type == DEVICE_INTEL_ICH4) {
2182 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2183 chip->smp20bit = 1;
2184 }
2185 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2186 /* 48kHz only */
2187 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2188 }
2189 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2190 /* use slot 10/11 for SPDIF */
2191 u32 val;
2192 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2193 val |= ICH_PCM_SPDIF_1011;
2194 iputdword(chip, ICHREG(GLOB_CNT), val);
2195 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2196 }
2197 chip->in_ac97_init = 0;
2198 return 0;
2199
2200 __err:
2201 /* clear the cold-reset bit for the next chance */
2202 if (chip->device_type != DEVICE_ALI)
2203 iputdword(chip, ICHREG(GLOB_CNT),
2204 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2205 return err;
2206 }
2207
2208
2209 /*
2210 *
2211 */
2212
2213 static void do_ali_reset(struct intel8x0 *chip)
2214 {
2215 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2216 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2217 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2218 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2219 iputdword(chip, ICHREG(ALI_INTERFACECR),
2220 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2221 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2222 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2223 }
2224
2225 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2226 {
2227 unsigned long end_time;
2228 unsigned int cnt, status, nstatus;
2229
2230 /* put logic to right state */
2231 /* first clear status bits */
2232 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2233 if (chip->device_type == DEVICE_NFORCE)
2234 status |= ICH_NVSPINT;
2235 cnt = igetdword(chip, ICHREG(GLOB_STA));
2236 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2237
2238 /* ACLink on, 2 channels */
2239 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2240 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2241 #ifdef CONFIG_SND_AC97_POWER_SAVE
2242 /* do cold reset - the full ac97 powerdown may leave the controller
2243 * in a warm state but actually it cannot communicate with the codec.
2244 */
2245 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2246 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2247 udelay(10);
2248 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2249 msleep(1);
2250 #else
2251 /* finish cold or do warm reset */
2252 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2253 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2254 end_time = (jiffies + (HZ / 4)) + 1;
2255 do {
2256 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2257 goto __ok;
2258 schedule_timeout_uninterruptible(1);
2259 } while (time_after_eq(end_time, jiffies));
2260 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2261 igetdword(chip, ICHREG(GLOB_CNT)));
2262 return -EIO;
2263
2264 __ok:
2265 #endif
2266 if (probing) {
2267 /* wait for any codec ready status.
2268 * Once it becomes ready it should remain ready
2269 * as long as we do not disable the ac97 link.
2270 */
2271 end_time = jiffies + HZ;
2272 do {
2273 status = igetdword(chip, ICHREG(GLOB_STA)) &
2274 chip->codec_isr_bits;
2275 if (status)
2276 break;
2277 schedule_timeout_uninterruptible(1);
2278 } while (time_after_eq(end_time, jiffies));
2279 if (! status) {
2280 /* no codec is found */
2281 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2282 igetdword(chip, ICHREG(GLOB_STA)));
2283 return -EIO;
2284 }
2285
2286 /* wait for other codecs ready status. */
2287 end_time = jiffies + HZ / 4;
2288 while (status != chip->codec_isr_bits &&
2289 time_after_eq(end_time, jiffies)) {
2290 schedule_timeout_uninterruptible(1);
2291 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2292 chip->codec_isr_bits;
2293 }
2294
2295 } else {
2296 /* resume phase */
2297 int i;
2298 status = 0;
2299 for (i = 0; i < chip->ncodecs; i++)
2300 if (chip->ac97[i])
2301 status |= chip->codec_bit[chip->ac97_sdin[i]];
2302 /* wait until all the probed codecs are ready */
2303 end_time = jiffies + HZ;
2304 do {
2305 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2306 chip->codec_isr_bits;
2307 if (status == nstatus)
2308 break;
2309 schedule_timeout_uninterruptible(1);
2310 } while (time_after_eq(end_time, jiffies));
2311 }
2312
2313 if (chip->device_type == DEVICE_SIS) {
2314 /* unmute the output on SIS7012 */
2315 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2316 }
2317 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2318 /* enable SPDIF interrupt */
2319 unsigned int val;
2320 pci_read_config_dword(chip->pci, 0x4c, &val);
2321 val |= 0x1000000;
2322 pci_write_config_dword(chip->pci, 0x4c, val);
2323 }
2324 return 0;
2325 }
2326
2327 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2328 {
2329 u32 reg;
2330 int i = 0;
2331
2332 reg = igetdword(chip, ICHREG(ALI_SCR));
2333 if ((reg & 2) == 0) /* Cold required */
2334 reg |= 2;
2335 else
2336 reg |= 1; /* Warm */
2337 reg &= ~0x80000000; /* ACLink on */
2338 iputdword(chip, ICHREG(ALI_SCR), reg);
2339
2340 for (i = 0; i < HZ / 2; i++) {
2341 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2342 goto __ok;
2343 schedule_timeout_uninterruptible(1);
2344 }
2345 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2346 if (probing)
2347 return -EIO;
2348
2349 __ok:
2350 for (i = 0; i < HZ / 2; i++) {
2351 reg = igetdword(chip, ICHREG(ALI_RTSR));
2352 if (reg & 0x80) /* primary codec */
2353 break;
2354 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2355 schedule_timeout_uninterruptible(1);
2356 }
2357
2358 do_ali_reset(chip);
2359 return 0;
2360 }
2361
2362 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2363 {
2364 unsigned int i, timeout;
2365 int err;
2366
2367 if (chip->device_type != DEVICE_ALI) {
2368 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2369 return err;
2370 iagetword(chip, 0); /* clear semaphore flag */
2371 } else {
2372 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2373 return err;
2374 }
2375
2376 /* disable interrupts */
2377 for (i = 0; i < chip->bdbars_count; i++)
2378 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2379 /* reset channels */
2380 for (i = 0; i < chip->bdbars_count; i++)
2381 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2382 for (i = 0; i < chip->bdbars_count; i++) {
2383 timeout = 100000;
2384 while (--timeout != 0) {
2385 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2386 break;
2387 }
2388 if (timeout == 0)
2389 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2390 }
2391 /* initialize Buffer Descriptor Lists */
2392 for (i = 0; i < chip->bdbars_count; i++)
2393 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2394 chip->ichd[i].bdbar_addr);
2395 return 0;
2396 }
2397
2398 static int snd_intel8x0_free(struct intel8x0 *chip)
2399 {
2400 unsigned int i;
2401
2402 if (chip->irq < 0)
2403 goto __hw_end;
2404 /* disable interrupts */
2405 for (i = 0; i < chip->bdbars_count; i++)
2406 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2407 /* reset channels */
2408 for (i = 0; i < chip->bdbars_count; i++)
2409 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2410 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2411 /* stop the spdif interrupt */
2412 unsigned int val;
2413 pci_read_config_dword(chip->pci, 0x4c, &val);
2414 val &= ~0x1000000;
2415 pci_write_config_dword(chip->pci, 0x4c, val);
2416 }
2417 /* --- */
2418 synchronize_irq(chip->irq);
2419 __hw_end:
2420 if (chip->irq >= 0)
2421 free_irq(chip->irq, chip);
2422 if (chip->bdbars.area) {
2423 if (chip->fix_nocache)
2424 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2425 snd_dma_free_pages(&chip->bdbars);
2426 }
2427 if (chip->addr)
2428 pci_iounmap(chip->pci, chip->addr);
2429 if (chip->bmaddr)
2430 pci_iounmap(chip->pci, chip->bmaddr);
2431 pci_release_regions(chip->pci);
2432 pci_disable_device(chip->pci);
2433 kfree(chip);
2434 return 0;
2435 }
2436
2437 #ifdef CONFIG_PM
2438 /*
2439 * power management
2440 */
2441 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2442 {
2443 struct snd_card *card = pci_get_drvdata(pci);
2444 struct intel8x0 *chip = card->private_data;
2445 int i;
2446
2447 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2448 for (i = 0; i < chip->pcm_devs; i++)
2449 snd_pcm_suspend_all(chip->pcm[i]);
2450 /* clear nocache */
2451 if (chip->fix_nocache) {
2452 for (i = 0; i < chip->bdbars_count; i++) {
2453 struct ichdev *ichdev = &chip->ichd[i];
2454 if (ichdev->substream && ichdev->page_attr_changed) {
2455 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2456 if (runtime->dma_area)
2457 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2458 }
2459 }
2460 }
2461 for (i = 0; i < chip->ncodecs; i++)
2462 snd_ac97_suspend(chip->ac97[i]);
2463 if (chip->device_type == DEVICE_INTEL_ICH4)
2464 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2465
2466 if (chip->irq >= 0) {
2467 synchronize_irq(chip->irq);
2468 free_irq(chip->irq, chip);
2469 chip->irq = -1;
2470 }
2471 pci_disable_device(pci);
2472 pci_save_state(pci);
2473 pci_set_power_state(pci, pci_choose_state(pci, state));
2474 return 0;
2475 }
2476
2477 static int intel8x0_resume(struct pci_dev *pci)
2478 {
2479 struct snd_card *card = pci_get_drvdata(pci);
2480 struct intel8x0 *chip = card->private_data;
2481 int i;
2482
2483 pci_set_power_state(pci, PCI_D0);
2484 pci_restore_state(pci);
2485 if (pci_enable_device(pci) < 0) {
2486 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2487 "disabling device\n");
2488 snd_card_disconnect(card);
2489 return -EIO;
2490 }
2491 pci_set_master(pci);
2492 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2493 IRQF_SHARED, card->shortname, chip)) {
2494 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2495 "disabling device\n", pci->irq);
2496 snd_card_disconnect(card);
2497 return -EIO;
2498 }
2499 chip->irq = pci->irq;
2500 synchronize_irq(chip->irq);
2501 snd_intel8x0_chip_init(chip, 0);
2502
2503 /* re-initialize mixer stuff */
2504 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2505 /* enable separate SDINs for ICH4 */
2506 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2507 /* use slot 10/11 for SPDIF */
2508 iputdword(chip, ICHREG(GLOB_CNT),
2509 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2510 ICH_PCM_SPDIF_1011);
2511 }
2512
2513 /* refill nocache */
2514 if (chip->fix_nocache)
2515 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2516
2517 for (i = 0; i < chip->ncodecs; i++)
2518 snd_ac97_resume(chip->ac97[i]);
2519
2520 /* refill nocache */
2521 if (chip->fix_nocache) {
2522 for (i = 0; i < chip->bdbars_count; i++) {
2523 struct ichdev *ichdev = &chip->ichd[i];
2524 if (ichdev->substream && ichdev->page_attr_changed) {
2525 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2526 if (runtime->dma_area)
2527 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2528 }
2529 }
2530 }
2531
2532 /* resume status */
2533 for (i = 0; i < chip->bdbars_count; i++) {
2534 struct ichdev *ichdev = &chip->ichd[i];
2535 unsigned long port = ichdev->reg_offset;
2536 if (! ichdev->substream || ! ichdev->suspended)
2537 continue;
2538 if (ichdev->ichd == ICHD_PCMOUT)
2539 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2540 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2541 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2542 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2543 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2544 }
2545
2546 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2547 return 0;
2548 }
2549 #endif /* CONFIG_PM */
2550
2551 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2552
2553 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2554 {
2555 struct snd_pcm_substream *subs;
2556 struct ichdev *ichdev;
2557 unsigned long port;
2558 unsigned long pos, t;
2559 struct timeval start_time, stop_time;
2560
2561 if (chip->ac97_bus->clock != 48000)
2562 return; /* specified in module option */
2563
2564 subs = chip->pcm[0]->streams[0].substream;
2565 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2566 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2567 return;
2568 }
2569 ichdev = &chip->ichd[ICHD_PCMOUT];
2570 ichdev->physbuf = subs->dma_buffer.addr;
2571 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2572 ichdev->substream = NULL; /* don't process interrupts */
2573
2574 /* set rate */
2575 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2576 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2577 return;
2578 }
2579 snd_intel8x0_setup_periods(chip, ichdev);
2580 port = ichdev->reg_offset;
2581 spin_lock_irq(&chip->reg_lock);
2582 chip->in_measurement = 1;
2583 /* trigger */
2584 if (chip->device_type != DEVICE_ALI)
2585 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2586 else {
2587 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2588 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2589 }
2590 do_gettimeofday(&start_time);
2591 spin_unlock_irq(&chip->reg_lock);
2592 msleep(50);
2593 spin_lock_irq(&chip->reg_lock);
2594 /* check the position */
2595 pos = ichdev->fragsize1;
2596 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2597 pos += ichdev->position;
2598 chip->in_measurement = 0;
2599 do_gettimeofday(&stop_time);
2600 /* stop */
2601 if (chip->device_type == DEVICE_ALI) {
2602 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2603 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2604 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2605 ;
2606 } else {
2607 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2608 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2609 ;
2610 }
2611 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2612 spin_unlock_irq(&chip->reg_lock);
2613
2614 t = stop_time.tv_sec - start_time.tv_sec;
2615 t *= 1000000;
2616 t += stop_time.tv_usec - start_time.tv_usec;
2617 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2618 if (t == 0) {
2619 snd_printk(KERN_ERR "?? calculation error..\n");
2620 return;
2621 }
2622 pos = (pos / 4) * 1000;
2623 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2624 if (pos < 40000 || pos >= 60000)
2625 /* abnormal value. hw problem? */
2626 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2627 else if (pos < 47500 || pos > 48500)
2628 /* not 48000Hz, tuning the clock.. */
2629 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2630 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2631 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2632 }
2633
2634 #ifdef CONFIG_PROC_FS
2635 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2636 struct snd_info_buffer *buffer)
2637 {
2638 struct intel8x0 *chip = entry->private_data;
2639 unsigned int tmp;
2640
2641 snd_iprintf(buffer, "Intel8x0\n\n");
2642 if (chip->device_type == DEVICE_ALI)
2643 return;
2644 tmp = igetdword(chip, ICHREG(GLOB_STA));
2645 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2646 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2647 if (chip->device_type == DEVICE_INTEL_ICH4)
2648 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2649 snd_iprintf(buffer, "AC'97 codecs ready :");
2650 if (tmp & chip->codec_isr_bits) {
2651 int i;
2652 static const char *codecs[3] = {
2653 "primary", "secondary", "tertiary"
2654 };
2655 for (i = 0; i < chip->max_codecs; i++)
2656 if (tmp & chip->codec_bit[i])
2657 snd_iprintf(buffer, " %s", codecs[i]);
2658 } else
2659 snd_iprintf(buffer, " none");
2660 snd_iprintf(buffer, "\n");
2661 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2662 chip->device_type == DEVICE_SIS)
2663 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2664 chip->ac97_sdin[0],
2665 chip->ac97_sdin[1],
2666 chip->ac97_sdin[2]);
2667 }
2668
2669 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2670 {
2671 struct snd_info_entry *entry;
2672
2673 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2674 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2675 }
2676 #else
2677 #define snd_intel8x0_proc_init(x)
2678 #endif
2679
2680 static int snd_intel8x0_dev_free(struct snd_device *device)
2681 {
2682 struct intel8x0 *chip = device->device_data;
2683 return snd_intel8x0_free(chip);
2684 }
2685
2686 struct ich_reg_info {
2687 unsigned int int_sta_mask;
2688 unsigned int offset;
2689 };
2690
2691 static unsigned int ich_codec_bits[3] = {
2692 ICH_PCR, ICH_SCR, ICH_TCR
2693 };
2694 static unsigned int sis_codec_bits[3] = {
2695 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2696 };
2697
2698 static int __devinit snd_intel8x0_create(struct snd_card *card,
2699 struct pci_dev *pci,
2700 unsigned long device_type,
2701 struct intel8x0 ** r_intel8x0)
2702 {
2703 struct intel8x0 *chip;
2704 int err;
2705 unsigned int i;
2706 unsigned int int_sta_masks;
2707 struct ichdev *ichdev;
2708 static struct snd_device_ops ops = {
2709 .dev_free = snd_intel8x0_dev_free,
2710 };
2711
2712 static unsigned int bdbars[] = {
2713 3, /* DEVICE_INTEL */
2714 6, /* DEVICE_INTEL_ICH4 */
2715 3, /* DEVICE_SIS */
2716 6, /* DEVICE_ALI */
2717 4, /* DEVICE_NFORCE */
2718 };
2719 static struct ich_reg_info intel_regs[6] = {
2720 { ICH_PIINT, 0 },
2721 { ICH_POINT, 0x10 },
2722 { ICH_MCINT, 0x20 },
2723 { ICH_M2INT, 0x40 },
2724 { ICH_P2INT, 0x50 },
2725 { ICH_SPINT, 0x60 },
2726 };
2727 static struct ich_reg_info nforce_regs[4] = {
2728 { ICH_PIINT, 0 },
2729 { ICH_POINT, 0x10 },
2730 { ICH_MCINT, 0x20 },
2731 { ICH_NVSPINT, 0x70 },
2732 };
2733 static struct ich_reg_info ali_regs[6] = {
2734 { ALI_INT_PCMIN, 0x40 },
2735 { ALI_INT_PCMOUT, 0x50 },
2736 { ALI_INT_MICIN, 0x60 },
2737 { ALI_INT_CODECSPDIFOUT, 0x70 },
2738 { ALI_INT_SPDIFIN, 0xa0 },
2739 { ALI_INT_SPDIFOUT, 0xb0 },
2740 };
2741 struct ich_reg_info *tbl;
2742
2743 *r_intel8x0 = NULL;
2744
2745 if ((err = pci_enable_device(pci)) < 0)
2746 return err;
2747
2748 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2749 if (chip == NULL) {
2750 pci_disable_device(pci);
2751 return -ENOMEM;
2752 }
2753 spin_lock_init(&chip->reg_lock);
2754 chip->device_type = device_type;
2755 chip->card = card;
2756 chip->pci = pci;
2757 chip->irq = -1;
2758
2759 /* module parameters */
2760 chip->buggy_irq = buggy_irq;
2761 chip->buggy_semaphore = buggy_semaphore;
2762 if (xbox)
2763 chip->xbox = 1;
2764
2765 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2766 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2767 chip->fix_nocache = 1; /* enable workaround */
2768
2769 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2770 kfree(chip);
2771 pci_disable_device(pci);
2772 return err;
2773 }
2774
2775 if (device_type == DEVICE_ALI) {
2776 /* ALI5455 has no ac97 region */
2777 chip->bmaddr = pci_iomap(pci, 0, 0);
2778 goto port_inited;
2779 }
2780
2781 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2782 chip->addr = pci_iomap(pci, 2, 0);
2783 else
2784 chip->addr = pci_iomap(pci, 0, 0);
2785 if (!chip->addr) {
2786 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2787 snd_intel8x0_free(chip);
2788 return -EIO;
2789 }
2790 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2791 chip->bmaddr = pci_iomap(pci, 3, 0);
2792 else
2793 chip->bmaddr = pci_iomap(pci, 1, 0);
2794 if (!chip->bmaddr) {
2795 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2796 snd_intel8x0_free(chip);
2797 return -EIO;
2798 }
2799
2800 port_inited:
2801 chip->bdbars_count = bdbars[device_type];
2802
2803 /* initialize offsets */
2804 switch (device_type) {
2805 case DEVICE_NFORCE:
2806 tbl = nforce_regs;
2807 break;
2808 case DEVICE_ALI:
2809 tbl = ali_regs;
2810 break;
2811 default:
2812 tbl = intel_regs;
2813 break;
2814 }
2815 for (i = 0; i < chip->bdbars_count; i++) {
2816 ichdev = &chip->ichd[i];
2817 ichdev->ichd = i;
2818 ichdev->reg_offset = tbl[i].offset;
2819 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2820 if (device_type == DEVICE_SIS) {
2821 /* SiS 7012 swaps the registers */
2822 ichdev->roff_sr = ICH_REG_OFF_PICB;
2823 ichdev->roff_picb = ICH_REG_OFF_SR;
2824 } else {
2825 ichdev->roff_sr = ICH_REG_OFF_SR;
2826 ichdev->roff_picb = ICH_REG_OFF_PICB;
2827 }
2828 if (device_type == DEVICE_ALI)
2829 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2830 /* SIS7012 handles the pcm data in bytes, others are in samples */
2831 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2832 }
2833
2834 /* allocate buffer descriptor lists */
2835 /* the start of each lists must be aligned to 8 bytes */
2836 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2837 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2838 &chip->bdbars) < 0) {
2839 snd_intel8x0_free(chip);
2840 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2841 return -ENOMEM;
2842 }
2843 /* tables must be aligned to 8 bytes here, but the kernel pages
2844 are much bigger, so we don't care (on i386) */
2845 /* workaround for 440MX */
2846 if (chip->fix_nocache)
2847 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2848 int_sta_masks = 0;
2849 for (i = 0; i < chip->bdbars_count; i++) {
2850 ichdev = &chip->ichd[i];
2851 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2852 (i * ICH_MAX_FRAGS * 2);
2853 ichdev->bdbar_addr = chip->bdbars.addr +
2854 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2855 int_sta_masks |= ichdev->int_sta_mask;
2856 }
2857 chip->int_sta_reg = device_type == DEVICE_ALI ?
2858 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2859 chip->int_sta_mask = int_sta_masks;
2860
2861 /* request irq after initializaing int_sta_mask, etc */
2862 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2863 IRQF_SHARED, card->shortname, chip)) {
2864 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2865 snd_intel8x0_free(chip);
2866 return -EBUSY;
2867 }
2868 chip->irq = pci->irq;
2869 pci_set_master(pci);
2870 synchronize_irq(chip->irq);
2871
2872 switch(chip->device_type) {
2873 case DEVICE_INTEL_ICH4:
2874 /* ICH4 can have three codecs */
2875 chip->max_codecs = 3;
2876 chip->codec_bit = ich_codec_bits;
2877 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2878 break;
2879 case DEVICE_SIS:
2880 /* recent SIS7012 can have three codecs */
2881 chip->max_codecs = 3;
2882 chip->codec_bit = sis_codec_bits;
2883 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2884 break;
2885 default:
2886 /* others up to two codecs */
2887 chip->max_codecs = 2;
2888 chip->codec_bit = ich_codec_bits;
2889 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2890 break;
2891 }
2892 for (i = 0; i < chip->max_codecs; i++)
2893 chip->codec_isr_bits |= chip->codec_bit[i];
2894
2895 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2896 snd_intel8x0_free(chip);
2897 return err;
2898 }
2899
2900 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2901 snd_intel8x0_free(chip);
2902 return err;
2903 }
2904
2905 snd_card_set_dev(card, &pci->dev);
2906
2907 *r_intel8x0 = chip;
2908 return 0;
2909 }
2910
2911 static struct shortname_table {
2912 unsigned int id;
2913 const char *s;
2914 } shortnames[] __devinitdata = {
2915 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2916 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2917 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2918 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2919 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2920 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2921 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2922 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2923 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2924 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2925 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2926 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2927 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2928 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2929 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2930 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2931 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2932 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2933 { 0x003a, "NVidia MCP04" },
2934 { 0x746d, "AMD AMD8111" },
2935 { 0x7445, "AMD AMD768" },
2936 { 0x5455, "ALi M5455" },
2937 { 0, NULL },
2938 };
2939
2940 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
2941 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
2942 { } /* end */
2943 };
2944
2945 /* look up white/black list for SPDIF over ac-link */
2946 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
2947 {
2948 const struct snd_pci_quirk *w;
2949
2950 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
2951 if (w) {
2952 if (w->value)
2953 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
2954 "AC-Link for %s\n", w->name);
2955 else
2956 snd_printdd(KERN_INFO "intel8x0: Using integrated "
2957 "SPDIF DMA for %s\n", w->name);
2958 return w->value;
2959 }
2960 return 0;
2961 }
2962
2963 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2964 const struct pci_device_id *pci_id)
2965 {
2966 struct snd_card *card;
2967 struct intel8x0 *chip;
2968 int err;
2969 struct shortname_table *name;
2970
2971 card = snd_card_new(index, id, THIS_MODULE, 0);
2972 if (card == NULL)
2973 return -ENOMEM;
2974
2975 if (spdif_aclink < 0)
2976 spdif_aclink = check_default_spdif_aclink(pci);
2977
2978 strcpy(card->driver, "ICH");
2979 if (!spdif_aclink) {
2980 switch (pci_id->driver_data) {
2981 case DEVICE_NFORCE:
2982 strcpy(card->driver, "NFORCE");
2983 break;
2984 case DEVICE_INTEL_ICH4:
2985 strcpy(card->driver, "ICH4");
2986 }
2987 }
2988
2989 strcpy(card->shortname, "Intel ICH");
2990 for (name = shortnames; name->id; name++) {
2991 if (pci->device == name->id) {
2992 strcpy(card->shortname, name->s);
2993 break;
2994 }
2995 }
2996
2997 if (buggy_irq < 0) {
2998 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2999 * Needs to return IRQ_HANDLED for unknown irqs.
3000 */
3001 if (pci_id->driver_data == DEVICE_NFORCE)
3002 buggy_irq = 1;
3003 else
3004 buggy_irq = 0;
3005 }
3006
3007 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3008 &chip)) < 0) {
3009 snd_card_free(card);
3010 return err;
3011 }
3012 card->private_data = chip;
3013
3014 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3015 snd_card_free(card);
3016 return err;
3017 }
3018 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3019 snd_card_free(card);
3020 return err;
3021 }
3022
3023 snd_intel8x0_proc_init(chip);
3024
3025 snprintf(card->longname, sizeof(card->longname),
3026 "%s with %s at irq %i", card->shortname,
3027 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3028
3029 if (! ac97_clock)
3030 intel8x0_measure_ac97_clock(chip);
3031
3032 if ((err = snd_card_register(card)) < 0) {
3033 snd_card_free(card);
3034 return err;
3035 }
3036 pci_set_drvdata(pci, card);
3037 return 0;
3038 }
3039
3040 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3041 {
3042 snd_card_free(pci_get_drvdata(pci));
3043 pci_set_drvdata(pci, NULL);
3044 }
3045
3046 static struct pci_driver driver = {
3047 .name = "Intel ICH",
3048 .id_table = snd_intel8x0_ids,
3049 .probe = snd_intel8x0_probe,
3050 .remove = __devexit_p(snd_intel8x0_remove),
3051 #ifdef CONFIG_PM
3052 .suspend = intel8x0_suspend,
3053 .resume = intel8x0_resume,
3054 #endif
3055 };
3056
3057
3058 static int __init alsa_card_intel8x0_init(void)
3059 {
3060 return pci_register_driver(&driver);
3061 }
3062
3063 static void __exit alsa_card_intel8x0_exit(void)
3064 {
3065 pci_unregister_driver(&driver);
3066 }
3067
3068 module_init(alsa_card_intel8x0_init)
3069 module_exit(alsa_card_intel8x0_exit)
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