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Linux-2.6.12-rc2
[mirror_ubuntu-bionic-kernel.git] / sound / pci / intel8x0m.c
1 /*
2 * ALSA modem driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 * This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
7 * of ALSA ICH sound driver intel8x0.c .
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 #include <sound/driver.h>
27 #include <asm/io.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/slab.h>
33 #include <linux/moduleparam.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/ac97_codec.h>
37 #include <sound/info.h>
38 #include <sound/control.h>
39 #include <sound/initval.h>
40
41 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
42 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
43 MODULE_LICENSE("GPL");
44 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
45 "{Intel,82901AB-ICH0},"
46 "{Intel,82801BA-ICH2},"
47 "{Intel,82801CA-ICH3},"
48 "{Intel,82801DB-ICH4},"
49 "{Intel,ICH5},"
50 "{Intel,ICH6},"
51 "{Intel,ICH7},"
52 "{Intel,MX440},"
53 "{SiS,7013},"
54 "{NVidia,NForce Modem},"
55 "{NVidia,NForce2 Modem},"
56 "{NVidia,NForce2s Modem},"
57 "{NVidia,NForce3 Modem},"
58 "{AMD,AMD768}}");
59
60 static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */
61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
63 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard.");
71 module_param_array(ac97_clock, int, NULL, 0444);
72 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
73
74 /*
75 * Direct registers
76 */
77
78 #ifndef PCI_DEVICE_ID_INTEL_82801_6
79 #define PCI_DEVICE_ID_INTEL_82801_6 0x2416
80 #endif
81 #ifndef PCI_DEVICE_ID_INTEL_82901_6
82 #define PCI_DEVICE_ID_INTEL_82901_6 0x2426
83 #endif
84 #ifndef PCI_DEVICE_ID_INTEL_82801BA_6
85 #define PCI_DEVICE_ID_INTEL_82801BA_6 0x2446
86 #endif
87 #ifndef PCI_DEVICE_ID_INTEL_440MX_6
88 #define PCI_DEVICE_ID_INTEL_440MX_6 0x7196
89 #endif
90 #ifndef PCI_DEVICE_ID_INTEL_ICH3_6
91 #define PCI_DEVICE_ID_INTEL_ICH3_6 0x2486
92 #endif
93 #ifndef PCI_DEVICE_ID_INTEL_ICH4_6
94 #define PCI_DEVICE_ID_INTEL_ICH4_6 0x24c6
95 #endif
96 #ifndef PCI_DEVICE_ID_INTEL_ICH5_6
97 #define PCI_DEVICE_ID_INTEL_ICH5_6 0x24d6
98 #endif
99 #ifndef PCI_DEVICE_ID_INTEL_ICH6_6
100 #define PCI_DEVICE_ID_INTEL_ICH6_6 0x266d
101 #endif
102 #ifndef PCI_DEVICE_ID_INTEL_ICH7_6
103 #define PCI_DEVICE_ID_INTEL_ICH7_6 0x27dd
104 #endif
105 #ifndef PCI_DEVICE_ID_SI_7013
106 #define PCI_DEVICE_ID_SI_7013 0x7013
107 #endif
108 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_MODEM
109 #define PCI_DEVICE_ID_NVIDIA_MCP_MODEM 0x01c1
110 #endif
111 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_MODEM
112 #define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069
113 #endif
114 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM
115 #define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089
116 #endif
117 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_MODEM
118 #define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9
119 #endif
120
121
122 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
123
124 #define ICHREG(x) ICH_REG_##x
125
126 #define DEFINE_REGSET(name,base) \
127 enum { \
128 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
129 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
130 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
131 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
132 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
133 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
134 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
135 };
136
137 /* busmaster blocks */
138 DEFINE_REGSET(OFF, 0); /* offset */
139
140 /* values for each busmaster block */
141
142 /* LVI */
143 #define ICH_REG_LVI_MASK 0x1f
144
145 /* SR */
146 #define ICH_FIFOE 0x10 /* FIFO error */
147 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
148 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
149 #define ICH_CELV 0x02 /* current equals last valid */
150 #define ICH_DCH 0x01 /* DMA controller halted */
151
152 /* PIV */
153 #define ICH_REG_PIV_MASK 0x1f /* mask */
154
155 /* CR */
156 #define ICH_IOCE 0x10 /* interrupt on completion enable */
157 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
158 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
159 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
160 #define ICH_STARTBM 0x01 /* start busmaster operation */
161
162
163 /* global block */
164 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
165 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
166 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
167 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
168 #define ICH_ACLINK 0x00000008 /* AClink shut off */
169 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
170 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
171 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
172 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */
173 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
174 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
175 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
176 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
177 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
178 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
179 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
180 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
181 #define ICH_MD3 0x00020000 /* modem power down semaphore */
182 #define ICH_AD3 0x00010000 /* audio power down semaphore */
183 #define ICH_RCS 0x00008000 /* read completion status */
184 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
185 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
186 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
187 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
188 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
189 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
190 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
191 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
192 #define ICH_POINT 0x00000040 /* playback interrupt */
193 #define ICH_PIINT 0x00000020 /* capture interrupt */
194 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
195 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
196 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
197 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
198 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
199 #define ICH_CAS 0x01 /* codec access semaphore */
200
201 #define ICH_MAX_FRAGS 32 /* max hw frags */
202
203
204 /*
205 *
206 */
207
208 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
209 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
210
211 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
212
213 typedef struct {
214 unsigned int ichd; /* ich device number */
215 unsigned long reg_offset; /* offset to bmaddr */
216 u32 *bdbar; /* CPU address (32bit) */
217 unsigned int bdbar_addr; /* PCI bus address (32bit) */
218 snd_pcm_substream_t *substream;
219 unsigned int physbuf; /* physical address (32bit) */
220 unsigned int size;
221 unsigned int fragsize;
222 unsigned int fragsize1;
223 unsigned int position;
224 int frags;
225 int lvi;
226 int lvi_frag;
227 int civ;
228 int ack;
229 int ack_reload;
230 unsigned int ack_bit;
231 unsigned int roff_sr;
232 unsigned int roff_picb;
233 unsigned int int_sta_mask; /* interrupt status mask */
234 unsigned int ali_slot; /* ALI DMA slot */
235 ac97_t *ac97;
236 } ichdev_t;
237
238 typedef struct _snd_intel8x0m intel8x0_t;
239
240 struct _snd_intel8x0m {
241 unsigned int device_type;
242
243 int irq;
244
245 unsigned int mmio;
246 unsigned long addr;
247 void __iomem *remap_addr;
248 unsigned int bm_mmio;
249 unsigned long bmaddr;
250 void __iomem *remap_bmaddr;
251
252 struct pci_dev *pci;
253 snd_card_t *card;
254
255 int pcm_devs;
256 snd_pcm_t *pcm[2];
257 ichdev_t ichd[2];
258
259 unsigned int in_ac97_init: 1;
260
261 ac97_bus_t *ac97_bus;
262 ac97_t *ac97;
263
264 spinlock_t reg_lock;
265
266 struct snd_dma_buffer bdbars;
267 u32 bdbars_count;
268 u32 int_sta_reg; /* interrupt status register */
269 u32 int_sta_mask; /* interrupt status mask */
270 unsigned int pcm_pos_shift;
271 };
272
273 static struct pci_device_id snd_intel8x0m_ids[] = {
274 { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
275 { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
276 { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
277 { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
278 { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
279 { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
280 { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */
281 { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */
282 { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
283 { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
284 { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */
285 { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
286 { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
287 { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
288 { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
289 #if 0
290 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
291 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
292 #endif
293 { 0, }
294 };
295 static int snd_intel8x0m_switch_default_get(snd_kcontrol_t *kcontrol,
296 snd_ctl_elem_value_t *ucontrol);
297 static int snd_intel8x0m_switch_default_put(snd_kcontrol_t *kcontrol,
298 snd_ctl_elem_value_t *ucontrol);
299 static int snd_intel8x0m_switch_default_info(snd_kcontrol_t *kcontrol,
300 snd_ctl_elem_info_t *uinfo);
301
302 #define PRIVATE_VALUE_INITIALIZER(r,m) (((r) & 0xffff) << 16 | ((m) & 0xffff))
303 #define PRIVATE_VALUE_MASK(control) ((control)->private_value & 0xffff)
304 #define PRIVATE_VALUE_REG(control) (((control)->private_value >> 16) & 0xffff)
305
306 static snd_kcontrol_new_t snd_intel8x0m_mixer_switches[] __devinitdata = {
307 { .name = "Off-hook Switch",
308 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
309 .info = snd_intel8x0m_switch_default_info,
310 .get = snd_intel8x0m_switch_default_get,
311 .put = snd_intel8x0m_switch_default_put,
312 .private_value = PRIVATE_VALUE_INITIALIZER(AC97_GPIO_STATUS,AC97_GPIO_LINE1_OH)
313 }
314 };
315
316 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
317
318 static int snd_intel8x0m_switch_default_info(snd_kcontrol_t *kcontrol,
319 snd_ctl_elem_info_t *uinfo)
320 {
321 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
322 uinfo->count = 1;
323 uinfo->value.integer.min = 0;
324 uinfo->value.integer.max = 1;
325 return 0;
326 }
327
328 static int snd_intel8x0m_switch_default_get(snd_kcontrol_t *kcontrol,
329 snd_ctl_elem_value_t *ucontrol)
330 {
331 unsigned short mask = PRIVATE_VALUE_MASK(kcontrol);
332 unsigned short reg = PRIVATE_VALUE_REG(kcontrol);
333 intel8x0_t *chip = snd_kcontrol_chip(kcontrol);
334 unsigned int status;
335 status = snd_ac97_read(chip->ac97, reg) & mask ? 1 : 0;
336 ucontrol->value.integer.value[0] = status;
337 return 0;
338 }
339 static int snd_intel8x0m_switch_default_put(snd_kcontrol_t *kcontrol,
340 snd_ctl_elem_value_t *ucontrol)
341 {
342 unsigned short mask = PRIVATE_VALUE_MASK(kcontrol);
343 unsigned short reg = PRIVATE_VALUE_REG(kcontrol);
344 intel8x0_t *chip = snd_kcontrol_chip(kcontrol);
345 unsigned short new_status = ucontrol->value.integer.value[0] ? mask : ~mask;
346 return snd_ac97_update_bits(chip->ac97, reg,
347 mask, new_status);
348 }
349 /*
350 * Lowlevel I/O - busmaster
351 */
352
353 static u8 igetbyte(intel8x0_t *chip, u32 offset)
354 {
355 if (chip->bm_mmio)
356 return readb(chip->remap_bmaddr + offset);
357 else
358 return inb(chip->bmaddr + offset);
359 }
360
361 static u16 igetword(intel8x0_t *chip, u32 offset)
362 {
363 if (chip->bm_mmio)
364 return readw(chip->remap_bmaddr + offset);
365 else
366 return inw(chip->bmaddr + offset);
367 }
368
369 static u32 igetdword(intel8x0_t *chip, u32 offset)
370 {
371 if (chip->bm_mmio)
372 return readl(chip->remap_bmaddr + offset);
373 else
374 return inl(chip->bmaddr + offset);
375 }
376
377 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
378 {
379 if (chip->bm_mmio)
380 writeb(val, chip->remap_bmaddr + offset);
381 else
382 outb(val, chip->bmaddr + offset);
383 }
384
385 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
386 {
387 if (chip->bm_mmio)
388 writew(val, chip->remap_bmaddr + offset);
389 else
390 outw(val, chip->bmaddr + offset);
391 }
392
393 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
394 {
395 if (chip->bm_mmio)
396 writel(val, chip->remap_bmaddr + offset);
397 else
398 outl(val, chip->bmaddr + offset);
399 }
400
401 /*
402 * Lowlevel I/O - AC'97 registers
403 */
404
405 static u16 iagetword(intel8x0_t *chip, u32 offset)
406 {
407 if (chip->mmio)
408 return readw(chip->remap_addr + offset);
409 else
410 return inw(chip->addr + offset);
411 }
412
413 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
414 {
415 if (chip->mmio)
416 writew(val, chip->remap_addr + offset);
417 else
418 outw(val, chip->addr + offset);
419 }
420
421 /*
422 * Basic I/O
423 */
424
425 /*
426 * access to AC97 codec via normal i/o (for ICH and SIS7013)
427 */
428
429 /* return the GLOB_STA bit for the corresponding codec */
430 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
431 {
432 static unsigned int codec_bit[3] = {
433 ICH_PCR, ICH_SCR, ICH_TCR
434 };
435 snd_assert(codec < 3, return ICH_PCR);
436 return codec_bit[codec];
437 }
438
439 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
440 {
441 int time;
442
443 if (codec > 1)
444 return -EIO;
445 codec = get_ich_codec_bit(chip, codec);
446
447 /* codec ready ? */
448 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
449 return -EIO;
450
451 /* Anyone holding a semaphore for 1 msec should be shot... */
452 time = 100;
453 do {
454 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
455 return 0;
456 udelay(10);
457 } while (time--);
458
459 /* access to some forbidden (non existant) ac97 registers will not
460 * reset the semaphore. So even if you don't get the semaphore, still
461 * continue the access. We don't need the semaphore anyway. */
462 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
463 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
464 iagetword(chip, 0); /* clear semaphore flag */
465 /* I don't care about the semaphore */
466 return -EBUSY;
467 }
468
469 static void snd_intel8x0_codec_write(ac97_t *ac97,
470 unsigned short reg,
471 unsigned short val)
472 {
473 intel8x0_t *chip = ac97->private_data;
474
475 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
476 if (! chip->in_ac97_init)
477 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
478 }
479 iaputword(chip, reg + ac97->num * 0x80, val);
480 }
481
482 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
483 unsigned short reg)
484 {
485 intel8x0_t *chip = ac97->private_data;
486 unsigned short res;
487 unsigned int tmp;
488
489 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
490 if (! chip->in_ac97_init)
491 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
492 res = 0xffff;
493 } else {
494 res = iagetword(chip, reg + ac97->num * 0x80);
495 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
496 /* reset RCS and preserve other R/WC bits */
497 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
498 if (! chip->in_ac97_init)
499 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
500 res = 0xffff;
501 }
502 }
503 return res;
504 }
505
506
507 /*
508 * DMA I/O
509 */
510 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
511 {
512 int idx;
513 u32 *bdbar = ichdev->bdbar;
514 unsigned long port = ichdev->reg_offset;
515
516 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
517 if (ichdev->size == ichdev->fragsize) {
518 ichdev->ack_reload = ichdev->ack = 2;
519 ichdev->fragsize1 = ichdev->fragsize >> 1;
520 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
521 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
522 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
523 ichdev->fragsize1 >> chip->pcm_pos_shift);
524 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
525 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
526 ichdev->fragsize1 >> chip->pcm_pos_shift);
527 }
528 ichdev->frags = 2;
529 } else {
530 ichdev->ack_reload = ichdev->ack = 1;
531 ichdev->fragsize1 = ichdev->fragsize;
532 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
533 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
534 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
535 ichdev->fragsize >> chip->pcm_pos_shift);
536 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
537 }
538 ichdev->frags = ichdev->size / ichdev->fragsize;
539 }
540 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
541 ichdev->civ = 0;
542 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
543 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
544 ichdev->position = 0;
545 #if 0
546 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
547 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
548 #endif
549 /* clear interrupts */
550 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
551 }
552
553 /*
554 * Interrupt handler
555 */
556
557 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
558 {
559 unsigned long port = ichdev->reg_offset;
560 int civ, i, step;
561 int ack = 0;
562
563 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
564 if (civ == ichdev->civ) {
565 // snd_printd("civ same %d\n", civ);
566 step = 1;
567 ichdev->civ++;
568 ichdev->civ &= ICH_REG_LVI_MASK;
569 } else {
570 step = civ - ichdev->civ;
571 if (step < 0)
572 step += ICH_REG_LVI_MASK + 1;
573 // if (step != 1)
574 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
575 ichdev->civ = civ;
576 }
577
578 ichdev->position += step * ichdev->fragsize1;
579 ichdev->position %= ichdev->size;
580 ichdev->lvi += step;
581 ichdev->lvi &= ICH_REG_LVI_MASK;
582 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
583 for (i = 0; i < step; i++) {
584 ichdev->lvi_frag++;
585 ichdev->lvi_frag %= ichdev->frags;
586 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
587 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
588 if (--ichdev->ack == 0) {
589 ichdev->ack = ichdev->ack_reload;
590 ack = 1;
591 }
592 }
593 if (ack && ichdev->substream) {
594 spin_unlock(&chip->reg_lock);
595 snd_pcm_period_elapsed(ichdev->substream);
596 spin_lock(&chip->reg_lock);
597 }
598 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
599 }
600
601 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
602 {
603 intel8x0_t *chip = dev_id;
604 ichdev_t *ichdev;
605 unsigned int status;
606 unsigned int i;
607
608 spin_lock(&chip->reg_lock);
609 status = igetdword(chip, chip->int_sta_reg);
610 if (status == 0xffffffff) { /* we are not yet resumed */
611 spin_unlock(&chip->reg_lock);
612 return IRQ_NONE;
613 }
614 if ((status & chip->int_sta_mask) == 0) {
615 if (status)
616 iputdword(chip, chip->int_sta_reg, status);
617 spin_unlock(&chip->reg_lock);
618 return IRQ_NONE;
619 }
620
621 for (i = 0; i < chip->bdbars_count; i++) {
622 ichdev = &chip->ichd[i];
623 if (status & ichdev->int_sta_mask)
624 snd_intel8x0_update(chip, ichdev);
625 }
626
627 /* ack them */
628 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
629 spin_unlock(&chip->reg_lock);
630
631 return IRQ_HANDLED;
632 }
633
634 /*
635 * PCM part
636 */
637
638 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
639 {
640 intel8x0_t *chip = snd_pcm_substream_chip(substream);
641 ichdev_t *ichdev = get_ichdev(substream);
642 unsigned char val = 0;
643 unsigned long port = ichdev->reg_offset;
644
645 switch (cmd) {
646 case SNDRV_PCM_TRIGGER_START:
647 case SNDRV_PCM_TRIGGER_RESUME:
648 val = ICH_IOCE | ICH_STARTBM;
649 break;
650 case SNDRV_PCM_TRIGGER_STOP:
651 case SNDRV_PCM_TRIGGER_SUSPEND:
652 val = 0;
653 break;
654 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
655 val = ICH_IOCE;
656 break;
657 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
658 val = ICH_IOCE | ICH_STARTBM;
659 break;
660 default:
661 return -EINVAL;
662 }
663 iputbyte(chip, port + ICH_REG_OFF_CR, val);
664 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
665 /* wait until DMA stopped */
666 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
667 /* reset whole DMA things */
668 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
669 }
670 return 0;
671 }
672
673 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
674 snd_pcm_hw_params_t * hw_params)
675 {
676 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
677 }
678
679 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
680 {
681 return snd_pcm_lib_free_pages(substream);
682 }
683
684 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
685 {
686 intel8x0_t *chip = snd_pcm_substream_chip(substream);
687 ichdev_t *ichdev = get_ichdev(substream);
688 size_t ptr1, ptr;
689
690 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
691 if (ptr1 != 0)
692 ptr = ichdev->fragsize1 - ptr1;
693 else
694 ptr = 0;
695 ptr += ichdev->position;
696 if (ptr >= ichdev->size)
697 return 0;
698 return bytes_to_frames(substream->runtime, ptr);
699 }
700
701 static int snd_intel8x0m_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
702 {
703 /* hook off/on on start/stop */
704 /* Moved this to mixer control */
705 switch (cmd) {
706 case SNDRV_PCM_TRIGGER_START:
707 break;
708 case SNDRV_PCM_TRIGGER_STOP:
709 break;
710 default:
711 return -EINVAL;
712 }
713 return snd_intel8x0_pcm_trigger(substream,cmd);
714 }
715
716 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
717 {
718 intel8x0_t *chip = snd_pcm_substream_chip(substream);
719 snd_pcm_runtime_t *runtime = substream->runtime;
720 ichdev_t *ichdev = get_ichdev(substream);
721
722 ichdev->physbuf = runtime->dma_addr;
723 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
724 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
725 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
726 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
727 snd_intel8x0_setup_periods(chip, ichdev);
728 return 0;
729 }
730
731 static snd_pcm_hardware_t snd_intel8x0m_stream =
732 {
733 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
734 SNDRV_PCM_INFO_BLOCK_TRANSFER |
735 SNDRV_PCM_INFO_MMAP_VALID |
736 SNDRV_PCM_INFO_PAUSE |
737 SNDRV_PCM_INFO_RESUME),
738 .formats = SNDRV_PCM_FMTBIT_S16_LE,
739 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
740 .rate_min = 8000,
741 .rate_max = 16000,
742 .channels_min = 1,
743 .channels_max = 1,
744 .buffer_bytes_max = 64 * 1024,
745 .period_bytes_min = 32,
746 .period_bytes_max = 64 * 1024,
747 .periods_min = 1,
748 .periods_max = 1024,
749 .fifo_size = 0,
750 };
751
752
753 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
754 {
755 static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
756 static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
757 .count = ARRAY_SIZE(rates),
758 .list = rates,
759 .mask = 0,
760 };
761 snd_pcm_runtime_t *runtime = substream->runtime;
762 int err;
763
764 ichdev->substream = substream;
765 runtime->hw = snd_intel8x0m_stream;
766 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
767 if ( err < 0 )
768 return err;
769 runtime->private_data = ichdev;
770 return 0;
771 }
772
773 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
774 {
775 intel8x0_t *chip = snd_pcm_substream_chip(substream);
776
777 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
778 }
779
780 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
781 {
782 intel8x0_t *chip = snd_pcm_substream_chip(substream);
783
784 chip->ichd[ICHD_MDMOUT].substream = NULL;
785 return 0;
786 }
787
788 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
789 {
790 intel8x0_t *chip = snd_pcm_substream_chip(substream);
791
792 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
793 }
794
795 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
796 {
797 intel8x0_t *chip = snd_pcm_substream_chip(substream);
798
799 chip->ichd[ICHD_MDMIN].substream = NULL;
800 return 0;
801 }
802
803
804 static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
805 .open = snd_intel8x0m_playback_open,
806 .close = snd_intel8x0m_playback_close,
807 .ioctl = snd_pcm_lib_ioctl,
808 .hw_params = snd_intel8x0_hw_params,
809 .hw_free = snd_intel8x0_hw_free,
810 .prepare = snd_intel8x0m_pcm_prepare,
811 .trigger = snd_intel8x0m_pcm_trigger,
812 .pointer = snd_intel8x0_pcm_pointer,
813 };
814
815 static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
816 .open = snd_intel8x0m_capture_open,
817 .close = snd_intel8x0m_capture_close,
818 .ioctl = snd_pcm_lib_ioctl,
819 .hw_params = snd_intel8x0_hw_params,
820 .hw_free = snd_intel8x0_hw_free,
821 .prepare = snd_intel8x0m_pcm_prepare,
822 .trigger = snd_intel8x0m_pcm_trigger,
823 .pointer = snd_intel8x0_pcm_pointer,
824 };
825
826
827 struct ich_pcm_table {
828 char *suffix;
829 snd_pcm_ops_t *playback_ops;
830 snd_pcm_ops_t *capture_ops;
831 size_t prealloc_size;
832 size_t prealloc_max_size;
833 int ac97_idx;
834 };
835
836 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
837 {
838 snd_pcm_t *pcm;
839 int err;
840 char name[32];
841
842 if (rec->suffix)
843 sprintf(name, "Intel ICH - %s", rec->suffix);
844 else
845 strcpy(name, "Intel ICH");
846 err = snd_pcm_new(chip->card, name, device,
847 rec->playback_ops ? 1 : 0,
848 rec->capture_ops ? 1 : 0, &pcm);
849 if (err < 0)
850 return err;
851
852 if (rec->playback_ops)
853 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
854 if (rec->capture_ops)
855 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
856
857 pcm->private_data = chip;
858 pcm->info_flags = 0;
859 if (rec->suffix)
860 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
861 else
862 strcpy(pcm->name, chip->card->shortname);
863 chip->pcm[device] = pcm;
864
865 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
866 snd_dma_pci_data(chip->pci),
867 rec->prealloc_size,
868 rec->prealloc_max_size);
869
870 return 0;
871 }
872
873 static struct ich_pcm_table intel_pcms[] __devinitdata = {
874 {
875 .suffix = "Modem",
876 .playback_ops = &snd_intel8x0m_playback_ops,
877 .capture_ops = &snd_intel8x0m_capture_ops,
878 .prealloc_size = 32 * 1024,
879 .prealloc_max_size = 64 * 1024,
880 },
881 };
882
883 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
884 {
885 int i, tblsize, device, err;
886 struct ich_pcm_table *tbl, *rec;
887
888 #if 1
889 tbl = intel_pcms;
890 tblsize = 1;
891 #else
892 switch (chip->device_type) {
893 case DEVICE_NFORCE:
894 tbl = nforce_pcms;
895 tblsize = ARRAY_SIZE(nforce_pcms);
896 break;
897 case DEVICE_ALI:
898 tbl = ali_pcms;
899 tblsize = ARRAY_SIZE(ali_pcms);
900 break;
901 default:
902 tbl = intel_pcms;
903 tblsize = 2;
904 break;
905 }
906 #endif
907 device = 0;
908 for (i = 0; i < tblsize; i++) {
909 rec = tbl + i;
910 if (i > 0 && rec->ac97_idx) {
911 /* activate PCM only when associated AC'97 codec */
912 if (! chip->ichd[rec->ac97_idx].ac97)
913 continue;
914 }
915 err = snd_intel8x0_pcm1(chip, device, rec);
916 if (err < 0)
917 return err;
918 device++;
919 }
920
921 chip->pcm_devs = device;
922 return 0;
923 }
924
925
926 /*
927 * Mixer part
928 */
929
930 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
931 {
932 intel8x0_t *chip = bus->private_data;
933 chip->ac97_bus = NULL;
934 }
935
936 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
937 {
938 intel8x0_t *chip = ac97->private_data;
939 chip->ac97 = NULL;
940 }
941
942
943 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
944 {
945 ac97_bus_t *pbus;
946 ac97_template_t ac97;
947 ac97_t *x97;
948 int err;
949 unsigned int glob_sta = 0;
950 unsigned int idx;
951 static ac97_bus_ops_t ops = {
952 .write = snd_intel8x0_codec_write,
953 .read = snd_intel8x0_codec_read,
954 };
955
956 chip->in_ac97_init = 1;
957
958 memset(&ac97, 0, sizeof(ac97));
959 ac97.private_data = chip;
960 ac97.private_free = snd_intel8x0_mixer_free_ac97;
961 ac97.scaps = AC97_SCAP_SKIP_AUDIO;
962
963 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
964
965 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
966 goto __err;
967 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
968 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with audio driver */
969 if (ac97_clock >= 8000 && ac97_clock <= 48000)
970 pbus->clock = ac97_clock;
971 chip->ac97_bus = pbus;
972
973 ac97.pci = chip->pci;
974 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
975 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
976 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
977 if (ac97.num == 0)
978 goto __err;
979 return err;
980 }
981 chip->ac97 = x97;
982 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
983 chip->ichd[ICHD_MDMIN].ac97 = x97;
984 chip->ichd[ICHD_MDMOUT].ac97 = x97;
985 }
986 for (idx = 0; idx < ARRAY_SIZE(snd_intel8x0m_mixer_switches); idx++) {
987 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_intel8x0m_mixer_switches[idx], chip))) < 0)
988 goto __err;
989 }
990
991 chip->in_ac97_init = 0;
992 return 0;
993
994 __err:
995 /* clear the cold-reset bit for the next chance */
996 if (chip->device_type != DEVICE_ALI)
997 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
998 return err;
999 }
1000
1001
1002 /*
1003 *
1004 */
1005
1006 #define do_delay(chip) do {\
1007 set_current_state(TASK_UNINTERRUPTIBLE);\
1008 schedule_timeout(1);\
1009 } while (0)
1010
1011 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
1012 {
1013 unsigned long end_time;
1014 unsigned int cnt, status, nstatus;
1015
1016 /* put logic to right state */
1017 /* first clear status bits */
1018 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
1019 cnt = igetdword(chip, ICHREG(GLOB_STA));
1020 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
1021
1022 /* ACLink on, 2 channels */
1023 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1024 cnt &= ~(ICH_ACLINK);
1025 /* finish cold or do warm reset */
1026 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
1027 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1028 end_time = (jiffies + (HZ / 4)) + 1;
1029 do {
1030 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
1031 goto __ok;
1032 do_delay(chip);
1033 } while (time_after_eq(end_time, jiffies));
1034 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
1035 return -EIO;
1036
1037 __ok:
1038 if (probing) {
1039 /* wait for any codec ready status.
1040 * Once it becomes ready it should remain ready
1041 * as long as we do not disable the ac97 link.
1042 */
1043 end_time = jiffies + HZ;
1044 do {
1045 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1046 if (status)
1047 break;
1048 do_delay(chip);
1049 } while (time_after_eq(end_time, jiffies));
1050 if (! status) {
1051 /* no codec is found */
1052 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
1053 return -EIO;
1054 }
1055
1056 /* up to two codecs (modem cannot be tertiary with ICH4) */
1057 nstatus = ICH_PCR | ICH_SCR;
1058
1059 /* wait for other codecs ready status. */
1060 end_time = jiffies + HZ / 4;
1061 while (status != nstatus && time_after_eq(end_time, jiffies)) {
1062 do_delay(chip);
1063 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1064 }
1065
1066 } else {
1067 /* resume phase */
1068 status = 0;
1069 if (chip->ac97)
1070 status |= get_ich_codec_bit(chip, chip->ac97->num);
1071 /* wait until all the probed codecs are ready */
1072 end_time = jiffies + HZ;
1073 do {
1074 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1075 if (status == nstatus)
1076 break;
1077 do_delay(chip);
1078 } while (time_after_eq(end_time, jiffies));
1079 }
1080
1081 if (chip->device_type == DEVICE_SIS) {
1082 /* unmute the output on SIS7012 */
1083 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
1084 }
1085
1086 return 0;
1087 }
1088
1089 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
1090 {
1091 unsigned int i;
1092 int err;
1093
1094 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
1095 return err;
1096 iagetword(chip, 0); /* clear semaphore flag */
1097
1098 /* disable interrupts */
1099 for (i = 0; i < chip->bdbars_count; i++)
1100 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1101 /* reset channels */
1102 for (i = 0; i < chip->bdbars_count; i++)
1103 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1104 /* initialize Buffer Descriptor Lists */
1105 for (i = 0; i < chip->bdbars_count; i++)
1106 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
1107 return 0;
1108 }
1109
1110 static int snd_intel8x0_free(intel8x0_t *chip)
1111 {
1112 unsigned int i;
1113
1114 if (chip->irq < 0)
1115 goto __hw_end;
1116 /* disable interrupts */
1117 for (i = 0; i < chip->bdbars_count; i++)
1118 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1119 /* reset channels */
1120 for (i = 0; i < chip->bdbars_count; i++)
1121 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1122 /* --- */
1123 synchronize_irq(chip->irq);
1124 __hw_end:
1125 if (chip->bdbars.area)
1126 snd_dma_free_pages(&chip->bdbars);
1127 if (chip->remap_addr)
1128 iounmap(chip->remap_addr);
1129 if (chip->remap_bmaddr)
1130 iounmap(chip->remap_bmaddr);
1131 if (chip->irq >= 0)
1132 free_irq(chip->irq, (void *)chip);
1133 pci_release_regions(chip->pci);
1134 pci_disable_device(chip->pci);
1135 kfree(chip);
1136 return 0;
1137 }
1138
1139 #ifdef CONFIG_PM
1140 /*
1141 * power management
1142 */
1143 static int intel8x0m_suspend(snd_card_t *card, pm_message_t state)
1144 {
1145 intel8x0_t *chip = card->pm_private_data;
1146 int i;
1147
1148 for (i = 0; i < chip->pcm_devs; i++)
1149 snd_pcm_suspend_all(chip->pcm[i]);
1150 if (chip->ac97)
1151 snd_ac97_suspend(chip->ac97);
1152 pci_disable_device(chip->pci);
1153 return 0;
1154 }
1155
1156 static int intel8x0m_resume(snd_card_t *card)
1157 {
1158 intel8x0_t *chip = card->pm_private_data;
1159 pci_enable_device(chip->pci);
1160 pci_set_master(chip->pci);
1161 snd_intel8x0_chip_init(chip, 0);
1162 if (chip->ac97)
1163 snd_ac97_resume(chip->ac97);
1164
1165 return 0;
1166 }
1167 #endif /* CONFIG_PM */
1168
1169 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1170 snd_info_buffer_t * buffer)
1171 {
1172 intel8x0_t *chip = entry->private_data;
1173 unsigned int tmp;
1174
1175 snd_iprintf(buffer, "Intel8x0m\n\n");
1176 if (chip->device_type == DEVICE_ALI)
1177 return;
1178 tmp = igetdword(chip, ICHREG(GLOB_STA));
1179 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1180 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1181 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1182 tmp & ICH_PCR ? " primary" : "",
1183 tmp & ICH_SCR ? " secondary" : "",
1184 tmp & ICH_TCR ? " tertiary" : "",
1185 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1186 }
1187
1188 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1189 {
1190 snd_info_entry_t *entry;
1191
1192 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1193 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
1194 }
1195
1196 static int snd_intel8x0_dev_free(snd_device_t *device)
1197 {
1198 intel8x0_t *chip = device->device_data;
1199 return snd_intel8x0_free(chip);
1200 }
1201
1202 struct ich_reg_info {
1203 unsigned int int_sta_mask;
1204 unsigned int offset;
1205 };
1206
1207 static int __devinit snd_intel8x0m_create(snd_card_t * card,
1208 struct pci_dev *pci,
1209 unsigned long device_type,
1210 intel8x0_t ** r_intel8x0)
1211 {
1212 intel8x0_t *chip;
1213 int err;
1214 unsigned int i;
1215 unsigned int int_sta_masks;
1216 ichdev_t *ichdev;
1217 static snd_device_ops_t ops = {
1218 .dev_free = snd_intel8x0_dev_free,
1219 };
1220 static struct ich_reg_info intel_regs[2] = {
1221 { ICH_MIINT, 0 },
1222 { ICH_MOINT, 0x10 },
1223 };
1224 struct ich_reg_info *tbl;
1225
1226 *r_intel8x0 = NULL;
1227
1228 if ((err = pci_enable_device(pci)) < 0)
1229 return err;
1230
1231 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1232 if (chip == NULL) {
1233 pci_disable_device(pci);
1234 return -ENOMEM;
1235 }
1236 spin_lock_init(&chip->reg_lock);
1237 chip->device_type = device_type;
1238 chip->card = card;
1239 chip->pci = pci;
1240 chip->irq = -1;
1241
1242 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1243 kfree(chip);
1244 pci_disable_device(pci);
1245 return err;
1246 }
1247
1248 if (device_type == DEVICE_ALI) {
1249 /* ALI5455 has no ac97 region */
1250 chip->bmaddr = pci_resource_start(pci, 0);
1251 goto port_inited;
1252 }
1253
1254 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
1255 chip->mmio = 1;
1256 chip->addr = pci_resource_start(pci, 2);
1257 chip->remap_addr = ioremap_nocache(chip->addr,
1258 pci_resource_len(pci, 2));
1259 if (chip->remap_addr == NULL) {
1260 snd_printk("AC'97 space ioremap problem\n");
1261 snd_intel8x0_free(chip);
1262 return -EIO;
1263 }
1264 } else {
1265 chip->addr = pci_resource_start(pci, 0);
1266 }
1267 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
1268 chip->bm_mmio = 1;
1269 chip->bmaddr = pci_resource_start(pci, 3);
1270 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
1271 pci_resource_len(pci, 3));
1272 if (chip->remap_bmaddr == NULL) {
1273 snd_printk("Controller space ioremap problem\n");
1274 snd_intel8x0_free(chip);
1275 return -EIO;
1276 }
1277 } else {
1278 chip->bmaddr = pci_resource_start(pci, 1);
1279 }
1280
1281 port_inited:
1282 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1283 snd_printk("unable to grab IRQ %d\n", pci->irq);
1284 snd_intel8x0_free(chip);
1285 return -EBUSY;
1286 }
1287 chip->irq = pci->irq;
1288 pci_set_master(pci);
1289 synchronize_irq(chip->irq);
1290
1291 /* initialize offsets */
1292 chip->bdbars_count = 2;
1293 tbl = intel_regs;
1294
1295 for (i = 0; i < chip->bdbars_count; i++) {
1296 ichdev = &chip->ichd[i];
1297 ichdev->ichd = i;
1298 ichdev->reg_offset = tbl[i].offset;
1299 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1300 if (device_type == DEVICE_SIS) {
1301 /* SiS 7013 swaps the registers */
1302 ichdev->roff_sr = ICH_REG_OFF_PICB;
1303 ichdev->roff_picb = ICH_REG_OFF_SR;
1304 } else {
1305 ichdev->roff_sr = ICH_REG_OFF_SR;
1306 ichdev->roff_picb = ICH_REG_OFF_PICB;
1307 }
1308 if (device_type == DEVICE_ALI)
1309 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1310 }
1311 /* SIS7013 handles the pcm data in bytes, others are in words */
1312 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1313
1314 /* allocate buffer descriptor lists */
1315 /* the start of each lists must be aligned to 8 bytes */
1316 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1317 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1318 &chip->bdbars) < 0) {
1319 snd_intel8x0_free(chip);
1320 return -ENOMEM;
1321 }
1322 /* tables must be aligned to 8 bytes here, but the kernel pages
1323 are much bigger, so we don't care (on i386) */
1324 int_sta_masks = 0;
1325 for (i = 0; i < chip->bdbars_count; i++) {
1326 ichdev = &chip->ichd[i];
1327 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1328 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1329 int_sta_masks |= ichdev->int_sta_mask;
1330 }
1331 chip->int_sta_reg = ICH_REG_GLOB_STA;
1332 chip->int_sta_mask = int_sta_masks;
1333
1334 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1335 snd_intel8x0_free(chip);
1336 return err;
1337 }
1338
1339 snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
1340
1341 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1342 snd_intel8x0_free(chip);
1343 return err;
1344 }
1345
1346 snd_card_set_dev(card, &pci->dev);
1347
1348 *r_intel8x0 = chip;
1349 return 0;
1350 }
1351
1352 static struct shortname_table {
1353 unsigned int id;
1354 const char *s;
1355 } shortnames[] __devinitdata = {
1356 { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" },
1357 { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" },
1358 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1359 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1360 { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" },
1361 { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" },
1362 { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" },
1363 { PCI_DEVICE_ID_INTEL_ICH6_6, "Intel ICH6" },
1364 { PCI_DEVICE_ID_INTEL_ICH7_6, "Intel ICH7" },
1365 { 0x7446, "AMD AMD768" },
1366 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1367 { PCI_DEVICE_ID_NVIDIA_MCP_MODEM, "NVidia nForce" },
1368 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1369 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1370 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1371 #if 0
1372 { 0x5455, "ALi M5455" },
1373 { 0x746d, "AMD AMD8111" },
1374 #endif
1375 { 0 },
1376 };
1377
1378 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1379 const struct pci_device_id *pci_id)
1380 {
1381 static int dev;
1382 snd_card_t *card;
1383 intel8x0_t *chip;
1384 int err;
1385 struct shortname_table *name;
1386
1387 if (dev >= SNDRV_CARDS)
1388 return -ENODEV;
1389 if (!enable[dev]) {
1390 dev++;
1391 return -ENOENT;
1392 }
1393
1394 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1395 if (card == NULL)
1396 return -ENOMEM;
1397
1398 strcpy(card->driver, "ICH-MODEM");
1399 strcpy(card->shortname, "Intel ICH");
1400 for (name = shortnames; name->id; name++) {
1401 if (pci->device == name->id) {
1402 strcpy(card->shortname, name->s);
1403 break;
1404 }
1405 }
1406 strcat(card->shortname," Modem");
1407
1408 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1409 snd_card_free(card);
1410 return err;
1411 }
1412
1413 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
1414 snd_card_free(card);
1415 return err;
1416 }
1417 if ((err = snd_intel8x0_pcm(chip)) < 0) {
1418 snd_card_free(card);
1419 return err;
1420 }
1421
1422 snd_intel8x0m_proc_init(chip);
1423
1424 sprintf(card->longname, "%s at 0x%lx, irq %i",
1425 card->shortname, chip->addr, chip->irq);
1426
1427 if ((err = snd_card_register(card)) < 0) {
1428 snd_card_free(card);
1429 return err;
1430 }
1431 pci_set_drvdata(pci, card);
1432 dev++;
1433 return 0;
1434 }
1435
1436 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1437 {
1438 snd_card_free(pci_get_drvdata(pci));
1439 pci_set_drvdata(pci, NULL);
1440 }
1441
1442 static struct pci_driver driver = {
1443 .name = "Intel ICH Modem",
1444 .id_table = snd_intel8x0m_ids,
1445 .probe = snd_intel8x0m_probe,
1446 .remove = __devexit_p(snd_intel8x0m_remove),
1447 SND_PCI_PM_CALLBACKS
1448 };
1449
1450
1451 static int __init alsa_card_intel8x0m_init(void)
1452 {
1453 return pci_module_init(&driver);
1454 }
1455
1456 static void __exit alsa_card_intel8x0m_exit(void)
1457 {
1458 pci_unregister_driver(&driver);
1459 }
1460
1461 module_init(alsa_card_intel8x0m_init)
1462 module_exit(alsa_card_intel8x0m_exit)
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