3 * ALSA driver for the digigram lx6464es interface
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
25 /* #define RMH_DEBUG 1 */
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
34 /* low-level register access */
36 static const unsigned long dsp_port_offsets
[] = {
69 static void __iomem
*lx_dsp_register(struct lx6464es
*chip
, int port
)
71 void __iomem
*base_address
= chip
->port_dsp_bar
;
72 return base_address
+ dsp_port_offsets
[port
]*4;
75 unsigned long lx_dsp_reg_read(struct lx6464es
*chip
, int port
)
77 void __iomem
*address
= lx_dsp_register(chip
, port
);
78 return ioread32(address
);
81 void lx_dsp_reg_readbuf(struct lx6464es
*chip
, int port
, u32
*data
, u32 len
)
83 void __iomem
*address
= lx_dsp_register(chip
, port
);
84 memcpy_fromio(data
, address
, len
*sizeof(u32
));
88 void lx_dsp_reg_write(struct lx6464es
*chip
, int port
, unsigned data
)
90 void __iomem
*address
= lx_dsp_register(chip
, port
);
91 iowrite32(data
, address
);
94 void lx_dsp_reg_writebuf(struct lx6464es
*chip
, int port
, const u32
*data
,
97 void __iomem
*address
= lx_dsp_register(chip
, port
);
98 memcpy_toio(address
, data
, len
*sizeof(u32
));
102 static const unsigned long plx_port_offsets
[] = {
117 static void __iomem
*lx_plx_register(struct lx6464es
*chip
, int port
)
119 void __iomem
*base_address
= chip
->port_plx_remapped
;
120 return base_address
+ plx_port_offsets
[port
];
123 unsigned long lx_plx_reg_read(struct lx6464es
*chip
, int port
)
125 void __iomem
*address
= lx_plx_register(chip
, port
);
126 return ioread32(address
);
129 void lx_plx_reg_write(struct lx6464es
*chip
, int port
, u32 data
)
131 void __iomem
*address
= lx_plx_register(chip
, port
);
132 iowrite32(data
, address
);
135 u32
lx_plx_mbox_read(struct lx6464es
*chip
, int mbox_nr
)
141 index
= ePLX_MBOX1
; break;
143 index
= ePLX_MBOX2
; break;
145 index
= ePLX_MBOX3
; break;
147 index
= ePLX_MBOX4
; break;
149 index
= ePLX_MBOX5
; break;
151 index
= ePLX_MBOX6
; break;
153 index
= ePLX_MBOX7
; break;
154 case 0: /* reserved for HF flags */
160 return lx_plx_reg_read(chip
, index
);
163 int lx_plx_mbox_write(struct lx6464es
*chip
, int mbox_nr
, u32 value
)
169 index
= ePLX_MBOX1
; break;
171 index
= ePLX_MBOX3
; break;
173 index
= ePLX_MBOX4
; break;
175 index
= ePLX_MBOX5
; break;
177 index
= ePLX_MBOX6
; break;
179 index
= ePLX_MBOX7
; break;
180 case 0: /* reserved for HF flags */
181 case 2: /* reserved for Pipe States
182 * the DSP keeps an image of it */
187 lx_plx_reg_write(chip
, index
, value
);
194 #ifdef CONFIG_SND_DEBUG
195 #define CMD_NAME(a) a
197 #define CMD_NAME(a) NULL
200 #define Reg_CSM_MR 0x00000002
201 #define Reg_CSM_MC 0x00000001
203 struct dsp_cmd_info
{
204 u32 dcCodeOp
; /* Op Code of the command (usually 1st 24-bits
206 u16 dcCmdLength
; /* Command length in words of 24 bits.*/
207 u16 dcStatusType
; /* Status type: 0 for fixed length, 1 for
209 u16 dcStatusLength
; /* Status length (if fixed).*/
214 Initialization and control data for the Microblaze interface
216 the opcode field of the command set at the proper offset
218 the number of command words
220 offset in the status registers: 0 means that the return value may be
221 different from 0, and must be read
223 the number of status words (in addition to the return value)
226 static struct dsp_cmd_info dsp_commands
[] =
228 { (CMD_00_INFO_DEBUG
<< OPCODE_OFFSET
) , 1 /*custom*/
229 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") },
230 { (CMD_01_GET_SYS_CFG
<< OPCODE_OFFSET
) , 1 /**/
231 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") },
232 { (CMD_02_SET_GRANULARITY
<< OPCODE_OFFSET
) , 1 /**/
233 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") },
234 { (CMD_03_SET_TIMER_IRQ
<< OPCODE_OFFSET
) , 1 /**/
235 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") },
236 { (CMD_04_GET_EVENT
<< OPCODE_OFFSET
) , 1 /**/
237 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") },
238 { (CMD_05_GET_PIPES
<< OPCODE_OFFSET
) , 1 /**/
239 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") },
240 { (CMD_06_ALLOCATE_PIPE
<< OPCODE_OFFSET
) , 1 /**/
241 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") },
242 { (CMD_07_RELEASE_PIPE
<< OPCODE_OFFSET
) , 1 /**/
243 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") },
244 { (CMD_08_ASK_BUFFERS
<< OPCODE_OFFSET
) , 1 /**/
245 , 1 , MAX_STREAM_BUFFER
, CMD_NAME("ASK_BUFFERS") },
246 { (CMD_09_STOP_PIPE
<< OPCODE_OFFSET
) , 1 /**/
247 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") },
248 { (CMD_0A_GET_PIPE_SPL_COUNT
<< OPCODE_OFFSET
) , 1 /**/
249 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") },
250 { (CMD_0B_TOGGLE_PIPE_STATE
<< OPCODE_OFFSET
) , 1 /*up to 5*/
251 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") },
252 { (CMD_0C_DEF_STREAM
<< OPCODE_OFFSET
) , 1 /*up to 4*/
253 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") },
254 { (CMD_0D_SET_MUTE
<< OPCODE_OFFSET
) , 3 /**/
255 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") },
256 { (CMD_0E_GET_STREAM_SPL_COUNT
<< OPCODE_OFFSET
) , 1/**/
257 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") },
258 { (CMD_0F_UPDATE_BUFFER
<< OPCODE_OFFSET
) , 3 /*up to 4*/
259 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") },
260 { (CMD_10_GET_BUFFER
<< OPCODE_OFFSET
) , 1 /**/
261 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") },
262 { (CMD_11_CANCEL_BUFFER
<< OPCODE_OFFSET
) , 1 /**/
263 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") },
264 { (CMD_12_GET_PEAK
<< OPCODE_OFFSET
) , 1 /**/
265 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") },
266 { (CMD_13_SET_STREAM_STATE
<< OPCODE_OFFSET
) , 1 /**/
267 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") },
270 static void lx_message_init(struct lx_rmh
*rmh
, enum cmd_mb_opcodes cmd
)
272 snd_BUG_ON(cmd
>= CMD_14_INVALID
);
274 rmh
->cmd
[0] = dsp_commands
[cmd
].dcCodeOp
;
275 rmh
->cmd_len
= dsp_commands
[cmd
].dcCmdLength
;
276 rmh
->stat_len
= dsp_commands
[cmd
].dcStatusLength
;
277 rmh
->dsp_stat
= dsp_commands
[cmd
].dcStatusType
;
279 memset(&rmh
->cmd
[1], 0, (REG_CRM_NUMBER
- 1) * sizeof(u32
));
281 #ifdef CONFIG_SND_DEBUG
282 memset(rmh
->stat
, 0, REG_CRM_NUMBER
* sizeof(u32
));
290 #define LXRMH "lx6464es rmh: "
291 static void lx_message_dump(struct lx_rmh
*rmh
)
293 u8 idx
= rmh
->cmd_idx
;
296 snd_printk(LXRMH
"command %s\n", dsp_commands
[idx
].dcOpName
);
298 for (i
= 0; i
!= rmh
->cmd_len
; ++i
)
299 snd_printk(LXRMH
"\tcmd[%d] %08x\n", i
, rmh
->cmd
[i
]);
301 for (i
= 0; i
!= rmh
->stat_len
; ++i
)
302 snd_printk(LXRMH
"\tstat[%d]: %08x\n", i
, rmh
->stat
[i
]);
306 static inline void lx_message_dump(struct lx_rmh
*rmh
)
312 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
313 #define XILINX_TIMEOUT_MS 40
314 #define XILINX_POLL_NO_SLEEP 100
315 #define XILINX_POLL_ITERATIONS 150
318 static int lx_message_send_atomic(struct lx6464es
*chip
, struct lx_rmh
*rmh
)
320 u32 reg
= ED_DSP_TIMED_OUT
;
323 if (lx_dsp_reg_read(chip
, eReg_CSM
) & (Reg_CSM_MC
| Reg_CSM_MR
)) {
324 snd_printk(KERN_ERR LXP
"PIOSendMessage eReg_CSM %x\n", reg
);
329 lx_dsp_reg_writebuf(chip
, eReg_CRM1
, rmh
->cmd
, rmh
->cmd_len
);
331 /* MicoBlaze gogogo */
332 lx_dsp_reg_write(chip
, eReg_CSM
, Reg_CSM_MC
);
334 /* wait for device to answer */
335 for (dwloop
= 0; dwloop
!= XILINX_TIMEOUT_MS
* 1000; ++dwloop
) {
336 if (lx_dsp_reg_read(chip
, eReg_CSM
) & Reg_CSM_MR
) {
337 if (rmh
->dsp_stat
== 0)
338 reg
= lx_dsp_reg_read(chip
, eReg_CRM1
);
341 goto polling_successful
;
345 snd_printk(KERN_WARNING LXP
"TIMEOUT lx_message_send_atomic! "
349 if ((reg
& ERROR_VALUE
) == 0) {
352 snd_BUG_ON(rmh
->stat_len
>= (REG_CRM_NUMBER
-1));
353 lx_dsp_reg_readbuf(chip
, eReg_CRM2
, rmh
->stat
,
357 snd_printk(LXP
"rmh error: %08x\n", reg
);
359 /* clear Reg_CSM_MR */
360 lx_dsp_reg_write(chip
, eReg_CSM
, 0);
363 case ED_DSP_TIMED_OUT
:
364 snd_printk(KERN_WARNING LXP
"lx_message_send: dsp timeout\n");
368 snd_printk(KERN_WARNING LXP
"lx_message_send: dsp crashed\n");
372 lx_message_dump(rmh
);
378 /* low-level dsp access */
379 int __devinit
lx_dsp_get_version(struct lx6464es
*chip
, u32
*rdsp_version
)
384 spin_lock_irqsave(&chip
->msg_lock
, flags
);
386 lx_message_init(&chip
->rmh
, CMD_01_GET_SYS_CFG
);
387 ret
= lx_message_send_atomic(chip
, &chip
->rmh
);
389 *rdsp_version
= chip
->rmh
.stat
[1];
390 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
394 int lx_dsp_get_clock_frequency(struct lx6464es
*chip
, u32
*rfreq
)
402 spin_lock_irqsave(&chip
->msg_lock
, flags
);
404 lx_message_init(&chip
->rmh
, CMD_01_GET_SYS_CFG
);
405 ret
= lx_message_send_atomic(chip
, &chip
->rmh
);
408 freq_raw
= chip
->rmh
.stat
[0] >> FREQ_FIELD_OFFSET
;
409 freq
= freq_raw
& XES_FREQ_COUNT8_MASK
;
411 if ((freq
< XES_FREQ_COUNT8_48_MAX
) ||
412 (freq
> XES_FREQ_COUNT8_44_MIN
))
413 frequency
= 0; /* unknown */
414 else if (freq
>= XES_FREQ_COUNT8_44_MAX
)
420 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
422 *rfreq
= frequency
* chip
->freq_ratio
;
427 int lx_dsp_get_mac(struct lx6464es
*chip
)
431 macmsb
= lx_dsp_reg_read(chip
, eReg_ADMACESMSB
) & 0x00FFFFFF;
432 maclsb
= lx_dsp_reg_read(chip
, eReg_ADMACESLSB
) & 0x00FFFFFF;
434 /* todo: endianess handling */
435 chip
->mac_address
[5] = ((u8
*)(&maclsb
))[0];
436 chip
->mac_address
[4] = ((u8
*)(&maclsb
))[1];
437 chip
->mac_address
[3] = ((u8
*)(&maclsb
))[2];
438 chip
->mac_address
[2] = ((u8
*)(&macmsb
))[0];
439 chip
->mac_address
[1] = ((u8
*)(&macmsb
))[1];
440 chip
->mac_address
[0] = ((u8
*)(&macmsb
))[2];
446 int lx_dsp_set_granularity(struct lx6464es
*chip
, u32 gran
)
451 spin_lock_irqsave(&chip
->msg_lock
, flags
);
453 lx_message_init(&chip
->rmh
, CMD_02_SET_GRANULARITY
);
454 chip
->rmh
.cmd
[0] |= gran
;
456 ret
= lx_message_send_atomic(chip
, &chip
->rmh
);
457 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
461 int lx_dsp_read_async_events(struct lx6464es
*chip
, u32
*data
)
466 spin_lock_irqsave(&chip
->msg_lock
, flags
);
468 lx_message_init(&chip
->rmh
, CMD_04_GET_EVENT
);
469 chip
->rmh
.stat_len
= 9; /* we don't necessarily need the full length */
471 ret
= lx_message_send_atomic(chip
, &chip
->rmh
);
474 memcpy(data
, chip
->rmh
.stat
, chip
->rmh
.stat_len
* sizeof(u32
));
476 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
480 #define CSES_TIMEOUT 100 /* microseconds */
481 #define CSES_CE 0x0001
482 #define CSES_BROADCAST 0x0002
483 #define CSES_UPDATE_LDSV 0x0004
485 int lx_dsp_es_check_pipeline(struct lx6464es
*chip
)
489 for (i
= 0; i
!= CSES_TIMEOUT
; ++i
) {
491 * le bit CSES_UPDATE_LDSV est à1 dés que le macprog
492 * est pret. il re-passe à0 lorsque le premier read a
493 * été fait. pour l'instant on retire le test car ce bit
494 * passe a 1 environ 200 à400 ms aprés que le registre
495 * confES àété écrit (kick du xilinx ES).
497 * On ne teste que le bit CE.
500 u32 cses
= lx_dsp_reg_read(chip
, eReg_CSES
);
502 if ((cses
& CSES_CE
) == 0)
512 #define PIPE_INFO_TO_CMD(capture, pipe) \
513 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
517 /* low-level pipe handling */
518 int lx_pipe_allocate(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
524 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
526 spin_lock_irqsave(&chip
->msg_lock
, flags
);
527 lx_message_init(&chip
->rmh
, CMD_06_ALLOCATE_PIPE
);
529 chip
->rmh
.cmd
[0] |= pipe_cmd
;
530 chip
->rmh
.cmd
[0] |= channels
;
532 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
533 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
536 snd_printk(KERN_ERR
"lx6464es: could not allocate pipe\n");
541 int lx_pipe_release(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
546 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
548 spin_lock_irqsave(&chip
->msg_lock
, flags
);
549 lx_message_init(&chip
->rmh
, CMD_07_RELEASE_PIPE
);
551 chip
->rmh
.cmd
[0] |= pipe_cmd
;
553 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
554 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
559 int lx_buffer_ask(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
560 u32
*r_needed
, u32
*r_freed
, u32
*size_array
)
565 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
567 #ifdef CONFIG_SND_DEBUG
569 memset(size_array
, 0, sizeof(u32
)*MAX_STREAM_BUFFER
);
575 spin_lock_irqsave(&chip
->msg_lock
, flags
);
576 lx_message_init(&chip
->rmh
, CMD_08_ASK_BUFFERS
);
578 chip
->rmh
.cmd
[0] |= pipe_cmd
;
580 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
584 for (i
= 0; i
< MAX_STREAM_BUFFER
; ++i
) {
585 u32 stat
= chip
->rmh
.stat
[i
];
586 if (stat
& (BF_EOB
<< BUFF_FLAGS_OFFSET
)) {
590 size_array
[i
] = stat
& MASK_DATA_SIZE
;
591 } else if ((stat
& (BF_VALID
<< BUFF_FLAGS_OFFSET
))
598 snd_printdd(LXP
"CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
599 *r_needed
, *r_freed
);
600 for (i
= 0; i
< MAX_STREAM_BUFFER
; ++i
) {
601 for (i
= 0; i
!= chip
->rmh
.stat_len
; ++i
)
602 snd_printdd(" stat[%d]: %x, %x\n", i
,
604 chip
->rmh
.stat
[i
] & MASK_DATA_SIZE
);
609 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
614 int lx_pipe_stop(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
619 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
621 spin_lock_irqsave(&chip
->msg_lock
, flags
);
622 lx_message_init(&chip
->rmh
, CMD_09_STOP_PIPE
);
624 chip
->rmh
.cmd
[0] |= pipe_cmd
;
626 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
628 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
632 static int lx_pipe_toggle_state(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
637 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
639 spin_lock_irqsave(&chip
->msg_lock
, flags
);
640 lx_message_init(&chip
->rmh
, CMD_0B_TOGGLE_PIPE_STATE
);
642 chip
->rmh
.cmd
[0] |= pipe_cmd
;
644 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
646 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
651 int lx_pipe_start(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
655 err
= lx_pipe_wait_for_idle(chip
, pipe
, is_capture
);
659 err
= lx_pipe_toggle_state(chip
, pipe
, is_capture
);
664 int lx_pipe_pause(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
668 err
= lx_pipe_wait_for_start(chip
, pipe
, is_capture
);
672 err
= lx_pipe_toggle_state(chip
, pipe
, is_capture
);
678 int lx_pipe_sample_count(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
684 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
686 spin_lock_irqsave(&chip
->msg_lock
, flags
);
687 lx_message_init(&chip
->rmh
, CMD_0A_GET_PIPE_SPL_COUNT
);
689 chip
->rmh
.cmd
[0] |= pipe_cmd
;
690 chip
->rmh
.stat_len
= 2; /* need all words here! */
692 err
= lx_message_send_atomic(chip
, &chip
->rmh
); /* don't sleep! */
696 "lx6464es: could not query pipe's sample count\n");
698 *rsample_count
= ((u64
)(chip
->rmh
.stat
[0] & MASK_SPL_COUNT_HI
)
700 + chip
->rmh
.stat
[1]; /* lo part */
703 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
707 int lx_pipe_state(struct lx6464es
*chip
, u32 pipe
, int is_capture
, u16
*rstate
)
712 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
714 spin_lock_irqsave(&chip
->msg_lock
, flags
);
715 lx_message_init(&chip
->rmh
, CMD_0A_GET_PIPE_SPL_COUNT
);
717 chip
->rmh
.cmd
[0] |= pipe_cmd
;
719 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
722 snd_printk(KERN_ERR
"lx6464es: could not query pipe's state\n");
724 *rstate
= (chip
->rmh
.stat
[0] >> PSTATE_OFFSET
) & 0x0F;
726 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
730 static int lx_pipe_wait_for_state(struct lx6464es
*chip
, u32 pipe
,
731 int is_capture
, u16 state
)
735 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
737 for (i
= 0; i
!= 50; ++i
) {
739 int err
= lx_pipe_state(chip
, pipe
, is_capture
, ¤t_state
);
744 if (current_state
== state
)
753 int lx_pipe_wait_for_start(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
755 return lx_pipe_wait_for_state(chip
, pipe
, is_capture
, PSTATE_RUN
);
758 int lx_pipe_wait_for_idle(struct lx6464es
*chip
, u32 pipe
, int is_capture
)
760 return lx_pipe_wait_for_state(chip
, pipe
, is_capture
, PSTATE_IDLE
);
763 /* low-level stream handling */
764 int lx_stream_set_state(struct lx6464es
*chip
, u32 pipe
,
765 int is_capture
, enum stream_state_t state
)
770 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
772 spin_lock_irqsave(&chip
->msg_lock
, flags
);
773 lx_message_init(&chip
->rmh
, CMD_13_SET_STREAM_STATE
);
775 chip
->rmh
.cmd
[0] |= pipe_cmd
;
776 chip
->rmh
.cmd
[0] |= state
;
778 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
779 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
784 int lx_stream_set_format(struct lx6464es
*chip
, struct snd_pcm_runtime
*runtime
,
785 u32 pipe
, int is_capture
)
790 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
792 u32 channels
= runtime
->channels
;
794 if (runtime
->channels
!= channels
)
795 snd_printk(KERN_ERR LXP
"channel count mismatch: %d vs %d",
796 runtime
->channels
, channels
);
798 spin_lock_irqsave(&chip
->msg_lock
, flags
);
799 lx_message_init(&chip
->rmh
, CMD_0C_DEF_STREAM
);
801 chip
->rmh
.cmd
[0] |= pipe_cmd
;
803 if (runtime
->sample_bits
== 16)
805 chip
->rmh
.cmd
[0] |= (STREAM_FMT_16b
<< STREAM_FMT_OFFSET
);
807 if (snd_pcm_format_little_endian(runtime
->format
))
808 /* little endian/intel format */
809 chip
->rmh
.cmd
[0] |= (STREAM_FMT_intel
<< STREAM_FMT_OFFSET
);
811 chip
->rmh
.cmd
[0] |= channels
-1;
813 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
814 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
819 int lx_stream_state(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
825 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
827 spin_lock_irqsave(&chip
->msg_lock
, flags
);
828 lx_message_init(&chip
->rmh
, CMD_0E_GET_STREAM_SPL_COUNT
);
830 chip
->rmh
.cmd
[0] |= pipe_cmd
;
832 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
834 *rstate
= (chip
->rmh
.stat
[0] & SF_START
) ? START_STATE
: PAUSE_STATE
;
836 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
840 int lx_stream_sample_position(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
846 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
848 spin_lock_irqsave(&chip
->msg_lock
, flags
);
849 lx_message_init(&chip
->rmh
, CMD_0E_GET_STREAM_SPL_COUNT
);
851 chip
->rmh
.cmd
[0] |= pipe_cmd
;
853 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
855 *r_bytepos
= ((u64
) (chip
->rmh
.stat
[0] & MASK_SPL_COUNT_HI
)
857 + chip
->rmh
.stat
[1]; /* lo part */
859 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
863 /* low-level buffer handling */
864 int lx_buffer_give(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
865 u32 buffer_size
, u32 buf_address_lo
, u32 buf_address_hi
,
871 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
873 spin_lock_irqsave(&chip
->msg_lock
, flags
);
874 lx_message_init(&chip
->rmh
, CMD_0F_UPDATE_BUFFER
);
876 chip
->rmh
.cmd
[0] |= pipe_cmd
;
877 chip
->rmh
.cmd
[0] |= BF_NOTIFY_EOB
; /* request interrupt notification */
879 /* todo: pause request, circular buffer */
881 chip
->rmh
.cmd
[1] = buffer_size
& MASK_DATA_SIZE
;
882 chip
->rmh
.cmd
[2] = buf_address_lo
;
884 if (buf_address_hi
) {
885 chip
->rmh
.cmd_len
= 4;
886 chip
->rmh
.cmd
[3] = buf_address_hi
;
887 chip
->rmh
.cmd
[0] |= BF_64BITS_ADR
;
890 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
893 *r_buffer_index
= chip
->rmh
.stat
[0];
897 if (err
== EB_RBUFFERS_TABLE_OVERFLOW
)
898 snd_printk(LXP
"lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
900 if (err
== EB_INVALID_STREAM
)
901 snd_printk(LXP
"lx_buffer_give EB_INVALID_STREAM\n");
903 if (err
== EB_CMD_REFUSED
)
904 snd_printk(LXP
"lx_buffer_give EB_CMD_REFUSED\n");
907 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
911 int lx_buffer_free(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
917 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
919 spin_lock_irqsave(&chip
->msg_lock
, flags
);
920 lx_message_init(&chip
->rmh
, CMD_11_CANCEL_BUFFER
);
922 chip
->rmh
.cmd
[0] |= pipe_cmd
;
923 chip
->rmh
.cmd
[0] |= MASK_BUFFER_ID
; /* ask for the current buffer: the
924 * microblaze will seek for it */
926 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
929 *r_buffer_size
= chip
->rmh
.stat
[0] & MASK_DATA_SIZE
;
931 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
935 int lx_buffer_cancel(struct lx6464es
*chip
, u32 pipe
, int is_capture
,
941 u32 pipe_cmd
= PIPE_INFO_TO_CMD(is_capture
, pipe
);
943 spin_lock_irqsave(&chip
->msg_lock
, flags
);
944 lx_message_init(&chip
->rmh
, CMD_11_CANCEL_BUFFER
);
946 chip
->rmh
.cmd
[0] |= pipe_cmd
;
947 chip
->rmh
.cmd
[0] |= buffer_index
;
949 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
951 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
956 /* low-level gain/peak handling
958 * \todo: can we unmute capture/playback channels independently?
961 int lx_level_unmute(struct lx6464es
*chip
, int is_capture
, int unmute
)
966 /* bit set to 1: channel muted */
967 u64 mute_mask
= unmute
? 0 : 0xFFFFFFFFFFFFFFFFLLU
;
969 spin_lock_irqsave(&chip
->msg_lock
, flags
);
970 lx_message_init(&chip
->rmh
, CMD_0D_SET_MUTE
);
972 chip
->rmh
.cmd
[0] |= PIPE_INFO_TO_CMD(is_capture
, 0);
974 chip
->rmh
.cmd
[1] = (u32
)(mute_mask
>> (u64
)32); /* hi part */
975 chip
->rmh
.cmd
[2] = (u32
)(mute_mask
& (u64
)0xFFFFFFFF); /* lo part */
977 snd_printk("mute %x %x %x\n", chip
->rmh
.cmd
[0], chip
->rmh
.cmd
[1],
980 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
982 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
986 static u32 peak_map
[] = {
987 0x00000109, /* -90.308dB */
988 0x0000083B, /* -72.247dB */
989 0x000020C4, /* -60.205dB */
990 0x00008273, /* -48.030dB */
991 0x00020756, /* -36.005dB */
992 0x00040C37, /* -30.001dB */
993 0x00081385, /* -24.002dB */
994 0x00101D3F, /* -18.000dB */
995 0x0016C310, /* -15.000dB */
996 0x002026F2, /* -12.001dB */
997 0x002D6A86, /* -9.000dB */
998 0x004026E6, /* -6.004dB */
999 0x005A9DF6, /* -3.000dB */
1000 0x0065AC8B, /* -2.000dB */
1001 0x00721481, /* -1.000dB */
1002 0x007FFFFF, /* FS */
1005 int lx_level_peaks(struct lx6464es
*chip
, int is_capture
, int channels
,
1009 unsigned long flags
;
1011 spin_lock_irqsave(&chip
->msg_lock
, flags
);
1013 for (i
= 0; i
< channels
; i
+= 4) {
1016 lx_message_init(&chip
->rmh
, CMD_12_GET_PEAK
);
1017 chip
->rmh
.cmd
[0] |= PIPE_INFO_TO_CMD(is_capture
, i
);
1019 err
= lx_message_send_atomic(chip
, &chip
->rmh
);
1022 s0
= peak_map
[chip
->rmh
.stat
[0] & 0x0F];
1023 s1
= peak_map
[(chip
->rmh
.stat
[0] >> 4) & 0xf];
1024 s2
= peak_map
[(chip
->rmh
.stat
[0] >> 8) & 0xf];
1025 s3
= peak_map
[(chip
->rmh
.stat
[0] >> 12) & 0xf];
1027 s0
= s1
= s2
= s3
= 0;
1037 spin_unlock_irqrestore(&chip
->msg_lock
, flags
);
1041 /* interrupt handling */
1042 #define PCX_IRQ_NONE 0
1043 #define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nÃ\83¸ 13 */
1044 #define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nÃ\83¸ 08 */
1045 #define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nÃ\83¸ 09 */
1047 static u32
lx_interrupt_test_ack(struct lx6464es
*chip
)
1049 u32 irqcs
= lx_plx_reg_read(chip
, ePLX_IRQCS
);
1051 /* Test if PCI Doorbell interrupt is active */
1052 if (irqcs
& IRQCS_ACTIVE_PCIDB
) {
1054 irqcs
= PCX_IRQ_NONE
;
1056 while ((temp
= lx_plx_reg_read(chip
, ePLX_L2PCIDB
))) {
1059 lx_plx_reg_write(chip
, ePLX_L2PCIDB
, temp
);
1064 return PCX_IRQ_NONE
;
1067 static int lx_interrupt_ack(struct lx6464es
*chip
, u32
*r_irqsrc
,
1068 int *r_async_pending
, int *r_async_escmd
)
1071 u32 irqsrc
= lx_interrupt_test_ack(chip
);
1073 if (irqsrc
== PCX_IRQ_NONE
)
1078 irq_async
= irqsrc
& MASK_SYS_ASYNC_EVENTS
; /* + EtherSound response
1079 * (set by xilinx) + EOB */
1081 if (irq_async
& MASK_SYS_STATUS_ESA
) {
1082 irq_async
&= ~MASK_SYS_STATUS_ESA
;
1087 /* snd_printd("interrupt: async event pending\n"); */
1088 *r_async_pending
= 1;
1094 static int lx_interrupt_handle_async_events(struct lx6464es
*chip
, u32 irqsrc
,
1095 int *r_freq_changed
,
1096 u64
*r_notified_in_pipe_mask
,
1097 u64
*r_notified_out_pipe_mask
)
1100 u32 stat
[9]; /* answer from CMD_04_GET_EVENT */
1102 /* On peut optimiser pour ne pas lire les evenements vides
1103 * les mots de rÃ\83©ponse sont dans l'ordre suivant :
1104 * Stat[0] mot de status gÃ\83©nÃ\83©ral
1105 * Stat[1] fin de buffer OUT pF
1106 * Stat[2] fin de buffer OUT pf
1107 * Stat[3] fin de buffer IN pF
1108 * Stat[4] fin de buffer IN pf
1109 * Stat[5] underrun poid fort
1110 * Stat[6] underrun poid faible
1111 * Stat[7] overrun poid fort
1112 * Stat[8] overrun poid faible
1118 int has_underrun
= (irqsrc
& MASK_SYS_STATUS_URUN
) ? 1 : 0;
1119 int has_overrun
= (irqsrc
& MASK_SYS_STATUS_ORUN
) ? 1 : 0;
1121 int eb_pending_out
= (irqsrc
& MASK_SYS_STATUS_EOBO
) ? 1 : 0;
1122 int eb_pending_in
= (irqsrc
& MASK_SYS_STATUS_EOBI
) ? 1 : 0;
1124 *r_freq_changed
= (irqsrc
& MASK_SYS_STATUS_FREQ
) ? 1 : 0;
1126 err
= lx_dsp_read_async_events(chip
, stat
);
1130 if (eb_pending_in
) {
1131 *r_notified_in_pipe_mask
= ((u64
)stat
[3] << 32)
1133 snd_printdd(LXP
"interrupt: EOBI pending %llx\n",
1134 *r_notified_in_pipe_mask
);
1136 if (eb_pending_out
) {
1137 *r_notified_out_pipe_mask
= ((u64
)stat
[1] << 32)
1139 snd_printdd(LXP
"interrupt: EOBO pending %llx\n",
1140 *r_notified_out_pipe_mask
);
1143 orun_mask
= ((u64
)stat
[7] << 32) + stat
[8];
1144 urun_mask
= ((u64
)stat
[5] << 32) + stat
[6];
1146 /* todo: handle xrun notification */
1151 static int lx_interrupt_request_new_buffer(struct lx6464es
*chip
,
1152 struct lx_stream
*lx_stream
)
1154 struct snd_pcm_substream
*substream
= lx_stream
->stream
;
1155 const unsigned int is_capture
= lx_stream
->is_capture
;
1157 unsigned long flags
;
1159 const u32 channels
= substream
->runtime
->channels
;
1160 const u32 bytes_per_frame
= channels
* 3;
1161 const u32 period_size
= substream
->runtime
->period_size
;
1162 const u32 period_bytes
= period_size
* bytes_per_frame
;
1163 const u32 pos
= lx_stream
->frame_pos
;
1164 const u32 next_pos
= ((pos
+1) == substream
->runtime
->periods
) ?
1167 dma_addr_t buf
= substream
->dma_buffer
.addr
+ pos
* period_bytes
;
1170 u32 buffer_index
= 0;
1173 u32 size_array
[MAX_STREAM_BUFFER
];
1175 snd_printdd("->lx_interrupt_request_new_buffer\n");
1177 spin_lock_irqsave(&chip
->lock
, flags
);
1179 err
= lx_buffer_ask(chip
, 0, is_capture
, &needed
, &freed
, size_array
);
1180 snd_printdd(LXP
"interrupt: needed %d, freed %d\n", needed
, freed
);
1182 unpack_pointer(buf
, &buf_lo
, &buf_hi
);
1183 err
= lx_buffer_give(chip
, 0, is_capture
, period_bytes
, buf_lo
, buf_hi
,
1185 snd_printdd(LXP
"interrupt: gave buffer index %x on %p (%d bytes)\n",
1186 buffer_index
, (void *)buf
, period_bytes
);
1188 lx_stream
->frame_pos
= next_pos
;
1189 spin_unlock_irqrestore(&chip
->lock
, flags
);
1194 void lx_tasklet_playback(unsigned long data
)
1196 struct lx6464es
*chip
= (struct lx6464es
*)data
;
1197 struct lx_stream
*lx_stream
= &chip
->playback_stream
;
1200 snd_printdd("->lx_tasklet_playback\n");
1202 err
= lx_interrupt_request_new_buffer(chip
, lx_stream
);
1204 snd_printk(KERN_ERR LXP
1205 "cannot request new buffer for playback\n");
1207 snd_pcm_period_elapsed(lx_stream
->stream
);
1210 void lx_tasklet_capture(unsigned long data
)
1212 struct lx6464es
*chip
= (struct lx6464es
*)data
;
1213 struct lx_stream
*lx_stream
= &chip
->capture_stream
;
1216 snd_printdd("->lx_tasklet_capture\n");
1217 err
= lx_interrupt_request_new_buffer(chip
, lx_stream
);
1219 snd_printk(KERN_ERR LXP
1220 "cannot request new buffer for capture\n");
1222 snd_pcm_period_elapsed(lx_stream
->stream
);
1227 static int lx_interrupt_handle_audio_transfer(struct lx6464es
*chip
,
1228 u64 notified_in_pipe_mask
,
1229 u64 notified_out_pipe_mask
)
1233 if (notified_in_pipe_mask
) {
1234 snd_printdd(LXP
"requesting audio transfer for capture\n");
1235 tasklet_hi_schedule(&chip
->tasklet_capture
);
1238 if (notified_out_pipe_mask
) {
1239 snd_printdd(LXP
"requesting audio transfer for playback\n");
1240 tasklet_hi_schedule(&chip
->tasklet_playback
);
1247 irqreturn_t
lx_interrupt(int irq
, void *dev_id
)
1249 struct lx6464es
*chip
= dev_id
;
1250 int async_pending
, async_escmd
;
1253 spin_lock(&chip
->lock
);
1255 snd_printdd("**************************************************\n");
1257 if (!lx_interrupt_ack(chip
, &irqsrc
, &async_pending
, &async_escmd
)) {
1258 spin_unlock(&chip
->lock
);
1259 snd_printdd("IRQ_NONE\n");
1260 return IRQ_NONE
; /* this device did not cause the interrupt */
1263 if (irqsrc
& MASK_SYS_STATUS_CMD_DONE
)
1267 if (irqsrc
& MASK_SYS_STATUS_EOBI
)
1268 snd_printdd(LXP
"interrupt: EOBI\n");
1270 if (irqsrc
& MASK_SYS_STATUS_EOBO
)
1271 snd_printdd(LXP
"interrupt: EOBO\n");
1273 if (irqsrc
& MASK_SYS_STATUS_URUN
)
1274 snd_printdd(LXP
"interrupt: URUN\n");
1276 if (irqsrc
& MASK_SYS_STATUS_ORUN
)
1277 snd_printdd(LXP
"interrupt: ORUN\n");
1280 if (async_pending
) {
1281 u64 notified_in_pipe_mask
= 0;
1282 u64 notified_out_pipe_mask
= 0;
1286 /* handle async events */
1287 err
= lx_interrupt_handle_async_events(chip
, irqsrc
,
1289 ¬ified_in_pipe_mask
,
1290 ¬ified_out_pipe_mask
);
1292 snd_printk(KERN_ERR LXP
1293 "error handling async events\n");
1295 err
= lx_interrupt_handle_audio_transfer(chip
,
1296 notified_in_pipe_mask
,
1297 notified_out_pipe_mask
1300 snd_printk(KERN_ERR LXP
1301 "error during audio transfer\n");
1306 /* backdoor for ethersound commands
1308 * for now, we do not need this
1312 snd_printdd("lx6464es: interrupt requests escmd handling\n");
1317 spin_unlock(&chip
->lock
);
1318 return IRQ_HANDLED
; /* this device caused the interrupt */
1322 static void lx_irq_set(struct lx6464es
*chip
, int enable
)
1324 u32 reg
= lx_plx_reg_read(chip
, ePLX_IRQCS
);
1326 /* enable/disable interrupts
1328 * Set the Doorbell and PCI interrupt enable bits
1332 reg
|= (IRQCS_ENABLE_PCIIRQ
| IRQCS_ENABLE_PCIDB
);
1334 reg
&= ~(IRQCS_ENABLE_PCIIRQ
| IRQCS_ENABLE_PCIDB
);
1335 lx_plx_reg_write(chip
, ePLX_IRQCS
, reg
);
1338 void lx_irq_enable(struct lx6464es
*chip
)
1340 snd_printdd("->lx_irq_enable\n");
1341 lx_irq_set(chip
, 1);
1344 void lx_irq_disable(struct lx6464es
*chip
)
1346 snd_printdd("->lx_irq_disable\n");
1347 lx_irq_set(chip
, 0);