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[mirror_ubuntu-eoan-kernel.git] / sound / pci / oxygen / oxygen_pcm.c
1 /*
2 * C-Media CMI8788 driver - PCM code
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include "oxygen.h"
26
27 static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
28 [PCM_A] = {
29 .info = SNDRV_PCM_INFO_MMAP |
30 SNDRV_PCM_INFO_MMAP_VALID |
31 SNDRV_PCM_INFO_INTERLEAVED |
32 SNDRV_PCM_INFO_PAUSE |
33 SNDRV_PCM_INFO_SYNC_START,
34 .formats = SNDRV_PCM_FMTBIT_S16_LE |
35 SNDRV_PCM_FMTBIT_S32_LE,
36 .rates = SNDRV_PCM_RATE_32000 |
37 SNDRV_PCM_RATE_44100 |
38 SNDRV_PCM_RATE_48000 |
39 SNDRV_PCM_RATE_64000 |
40 SNDRV_PCM_RATE_88200 |
41 SNDRV_PCM_RATE_96000 |
42 SNDRV_PCM_RATE_176400 |
43 SNDRV_PCM_RATE_192000,
44 .rate_min = 32000,
45 .rate_max = 192000,
46 .channels_min = 2,
47 .channels_max = 2,
48 .buffer_bytes_max = 256 * 1024,
49 .period_bytes_min = 128,
50 .period_bytes_max = 128 * 1024,
51 .periods_min = 2,
52 .periods_max = 2048,
53 },
54 [PCM_B] = {
55 .info = SNDRV_PCM_INFO_MMAP |
56 SNDRV_PCM_INFO_MMAP_VALID |
57 SNDRV_PCM_INFO_INTERLEAVED |
58 SNDRV_PCM_INFO_PAUSE |
59 SNDRV_PCM_INFO_SYNC_START,
60 .formats = SNDRV_PCM_FMTBIT_S16_LE |
61 SNDRV_PCM_FMTBIT_S32_LE,
62 .rates = SNDRV_PCM_RATE_32000 |
63 SNDRV_PCM_RATE_44100 |
64 SNDRV_PCM_RATE_48000 |
65 SNDRV_PCM_RATE_64000 |
66 SNDRV_PCM_RATE_88200 |
67 SNDRV_PCM_RATE_96000 |
68 SNDRV_PCM_RATE_176400 |
69 SNDRV_PCM_RATE_192000,
70 .rate_min = 32000,
71 .rate_max = 192000,
72 .channels_min = 2,
73 .channels_max = 2,
74 .buffer_bytes_max = 256 * 1024,
75 .period_bytes_min = 128,
76 .period_bytes_max = 128 * 1024,
77 .periods_min = 2,
78 .periods_max = 2048,
79 },
80 [PCM_C] = {
81 .info = SNDRV_PCM_INFO_MMAP |
82 SNDRV_PCM_INFO_MMAP_VALID |
83 SNDRV_PCM_INFO_INTERLEAVED |
84 SNDRV_PCM_INFO_PAUSE |
85 SNDRV_PCM_INFO_SYNC_START,
86 .formats = SNDRV_PCM_FMTBIT_S16_LE |
87 SNDRV_PCM_FMTBIT_S32_LE,
88 .rates = SNDRV_PCM_RATE_32000 |
89 SNDRV_PCM_RATE_44100 |
90 SNDRV_PCM_RATE_48000 |
91 SNDRV_PCM_RATE_64000 |
92 SNDRV_PCM_RATE_88200 |
93 SNDRV_PCM_RATE_96000 |
94 SNDRV_PCM_RATE_176400 |
95 SNDRV_PCM_RATE_192000,
96 .rate_min = 32000,
97 .rate_max = 192000,
98 .channels_min = 2,
99 .channels_max = 2,
100 .buffer_bytes_max = 256 * 1024,
101 .period_bytes_min = 128,
102 .period_bytes_max = 128 * 1024,
103 .periods_min = 2,
104 .periods_max = 2048,
105 },
106 [PCM_SPDIF] = {
107 .info = SNDRV_PCM_INFO_MMAP |
108 SNDRV_PCM_INFO_MMAP_VALID |
109 SNDRV_PCM_INFO_INTERLEAVED |
110 SNDRV_PCM_INFO_PAUSE |
111 SNDRV_PCM_INFO_SYNC_START,
112 .formats = SNDRV_PCM_FMTBIT_S16_LE |
113 SNDRV_PCM_FMTBIT_S32_LE,
114 .rates = SNDRV_PCM_RATE_32000 |
115 SNDRV_PCM_RATE_44100 |
116 SNDRV_PCM_RATE_48000 |
117 SNDRV_PCM_RATE_64000 |
118 SNDRV_PCM_RATE_88200 |
119 SNDRV_PCM_RATE_96000 |
120 SNDRV_PCM_RATE_176400 |
121 SNDRV_PCM_RATE_192000,
122 .rate_min = 32000,
123 .rate_max = 192000,
124 .channels_min = 2,
125 .channels_max = 2,
126 .buffer_bytes_max = 256 * 1024,
127 .period_bytes_min = 128,
128 .period_bytes_max = 128 * 1024,
129 .periods_min = 2,
130 .periods_max = 2048,
131 },
132 [PCM_MULTICH] = {
133 .info = SNDRV_PCM_INFO_MMAP |
134 SNDRV_PCM_INFO_MMAP_VALID |
135 SNDRV_PCM_INFO_INTERLEAVED |
136 SNDRV_PCM_INFO_PAUSE |
137 SNDRV_PCM_INFO_SYNC_START,
138 .formats = SNDRV_PCM_FMTBIT_S16_LE |
139 SNDRV_PCM_FMTBIT_S32_LE,
140 .rates = SNDRV_PCM_RATE_32000 |
141 SNDRV_PCM_RATE_44100 |
142 SNDRV_PCM_RATE_48000 |
143 SNDRV_PCM_RATE_64000 |
144 SNDRV_PCM_RATE_88200 |
145 SNDRV_PCM_RATE_96000 |
146 SNDRV_PCM_RATE_176400 |
147 SNDRV_PCM_RATE_192000,
148 .rate_min = 32000,
149 .rate_max = 192000,
150 .channels_min = 2,
151 .channels_max = 8,
152 .buffer_bytes_max = 2048 * 1024,
153 .period_bytes_min = 128,
154 .period_bytes_max = 256 * 1024,
155 .periods_min = 2,
156 .periods_max = 16384,
157 },
158 [PCM_AC97] = {
159 .info = SNDRV_PCM_INFO_MMAP |
160 SNDRV_PCM_INFO_MMAP_VALID |
161 SNDRV_PCM_INFO_INTERLEAVED |
162 SNDRV_PCM_INFO_PAUSE |
163 SNDRV_PCM_INFO_SYNC_START,
164 .formats = SNDRV_PCM_FMTBIT_S16_LE,
165 .rates = SNDRV_PCM_RATE_48000,
166 .rate_min = 48000,
167 .rate_max = 48000,
168 .channels_min = 2,
169 .channels_max = 2,
170 .buffer_bytes_max = 256 * 1024,
171 .period_bytes_min = 128,
172 .period_bytes_max = 128 * 1024,
173 .periods_min = 2,
174 .periods_max = 2048,
175 },
176 };
177
178 static inline unsigned int
179 oxygen_substream_channel(struct snd_pcm_substream *substream)
180 {
181 return (unsigned int)(uintptr_t)substream->runtime->private_data;
182 }
183
184 static int oxygen_open(struct snd_pcm_substream *substream,
185 unsigned int channel)
186 {
187 struct oxygen *chip = snd_pcm_substream_chip(substream);
188 struct snd_pcm_runtime *runtime = substream->runtime;
189 int err;
190
191 runtime->private_data = (void *)(uintptr_t)channel;
192 runtime->hw = oxygen_hardware[channel];
193 if (chip->model->pcm_hardware_filter)
194 chip->model->pcm_hardware_filter(channel, &runtime->hw);
195 err = snd_pcm_hw_constraint_step(runtime, 0,
196 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
197 if (err < 0)
198 return err;
199 err = snd_pcm_hw_constraint_step(runtime, 0,
200 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
201 if (err < 0)
202 return err;
203 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
204 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
205 if (err < 0)
206 return err;
207 }
208 if (runtime->hw.channels_max > 2) {
209 err = snd_pcm_hw_constraint_step(runtime, 0,
210 SNDRV_PCM_HW_PARAM_CHANNELS,
211 2);
212 if (err < 0)
213 return err;
214 }
215 snd_pcm_set_sync(substream);
216 chip->streams[channel] = substream;
217
218 mutex_lock(&chip->mutex);
219 chip->pcm_active |= 1 << channel;
220 if (channel == PCM_SPDIF) {
221 chip->spdif_pcm_bits = chip->spdif_bits;
222 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
223 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
224 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
225 SNDRV_CTL_EVENT_MASK_INFO,
226 &chip->controls[CONTROL_SPDIF_PCM]->id);
227 }
228 mutex_unlock(&chip->mutex);
229
230 return 0;
231 }
232
233 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
234 {
235 return oxygen_open(substream, PCM_A);
236 }
237
238 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
239 {
240 return oxygen_open(substream, PCM_B);
241 }
242
243 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
244 {
245 return oxygen_open(substream, PCM_C);
246 }
247
248 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
249 {
250 return oxygen_open(substream, PCM_SPDIF);
251 }
252
253 static int oxygen_multich_open(struct snd_pcm_substream *substream)
254 {
255 return oxygen_open(substream, PCM_MULTICH);
256 }
257
258 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
259 {
260 return oxygen_open(substream, PCM_AC97);
261 }
262
263 static int oxygen_close(struct snd_pcm_substream *substream)
264 {
265 struct oxygen *chip = snd_pcm_substream_chip(substream);
266 unsigned int channel = oxygen_substream_channel(substream);
267
268 mutex_lock(&chip->mutex);
269 chip->pcm_active &= ~(1 << channel);
270 if (channel == PCM_SPDIF) {
271 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
272 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
273 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
274 SNDRV_CTL_EVENT_MASK_INFO,
275 &chip->controls[CONTROL_SPDIF_PCM]->id);
276 }
277 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
278 oxygen_update_spdif_source(chip);
279 mutex_unlock(&chip->mutex);
280
281 chip->streams[channel] = NULL;
282 return 0;
283 }
284
285 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
286 {
287 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
288 return OXYGEN_FORMAT_24;
289 else
290 return OXYGEN_FORMAT_16;
291 }
292
293 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
294 {
295 switch (params_rate(hw_params)) {
296 case 32000:
297 return OXYGEN_RATE_32000;
298 case 44100:
299 return OXYGEN_RATE_44100;
300 default: /* 48000 */
301 return OXYGEN_RATE_48000;
302 case 64000:
303 return OXYGEN_RATE_64000;
304 case 88200:
305 return OXYGEN_RATE_88200;
306 case 96000:
307 return OXYGEN_RATE_96000;
308 case 176400:
309 return OXYGEN_RATE_176400;
310 case 192000:
311 return OXYGEN_RATE_192000;
312 }
313 }
314
315 static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
316 {
317 return params_rate(hw_params) <= 96000
318 ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
319 }
320
321 static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
322 {
323 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
324 return OXYGEN_I2S_BITS_24;
325 else
326 return OXYGEN_I2S_BITS_16;
327 }
328
329 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
330 {
331 switch (params_channels(hw_params)) {
332 default: /* 2 */
333 return OXYGEN_PLAY_CHANNELS_2;
334 case 4:
335 return OXYGEN_PLAY_CHANNELS_4;
336 case 6:
337 return OXYGEN_PLAY_CHANNELS_6;
338 case 8:
339 return OXYGEN_PLAY_CHANNELS_8;
340 }
341 }
342
343 static const unsigned int channel_base_registers[PCM_COUNT] = {
344 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
345 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
346 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
347 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
348 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
349 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
350 };
351
352 static int oxygen_hw_params(struct snd_pcm_substream *substream,
353 struct snd_pcm_hw_params *hw_params)
354 {
355 struct oxygen *chip = snd_pcm_substream_chip(substream);
356 unsigned int channel = oxygen_substream_channel(substream);
357 int err;
358
359 err = snd_pcm_lib_malloc_pages(substream,
360 params_buffer_bytes(hw_params));
361 if (err < 0)
362 return err;
363
364 oxygen_write32(chip, channel_base_registers[channel],
365 (u32)substream->runtime->dma_addr);
366 if (channel == PCM_MULTICH) {
367 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
368 params_buffer_bytes(hw_params) / 4 - 1);
369 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
370 params_period_bytes(hw_params) / 4 - 1);
371 } else {
372 oxygen_write16(chip, channel_base_registers[channel] + 4,
373 params_buffer_bytes(hw_params) / 4 - 1);
374 oxygen_write16(chip, channel_base_registers[channel] + 6,
375 params_period_bytes(hw_params) / 4 - 1);
376 }
377 return 0;
378 }
379
380 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
381 struct snd_pcm_hw_params *hw_params)
382 {
383 struct oxygen *chip = snd_pcm_substream_chip(substream);
384 int err;
385
386 err = oxygen_hw_params(substream, hw_params);
387 if (err < 0)
388 return err;
389
390 spin_lock_irq(&chip->reg_lock);
391 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
392 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
393 OXYGEN_REC_FORMAT_A_MASK);
394 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
395 oxygen_rate(hw_params) |
396 oxygen_i2s_mclk(hw_params) |
397 chip->model->adc_i2s_format |
398 oxygen_i2s_bits(hw_params),
399 OXYGEN_I2S_RATE_MASK |
400 OXYGEN_I2S_FORMAT_MASK |
401 OXYGEN_I2S_MCLK_MASK |
402 OXYGEN_I2S_BITS_MASK);
403 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
404 OXYGEN_REC_A_ROUTE_I2S_ADC_1,
405 OXYGEN_REC_A_ROUTE_MASK);
406 spin_unlock_irq(&chip->reg_lock);
407
408 mutex_lock(&chip->mutex);
409 chip->model->set_adc_params(chip, hw_params);
410 mutex_unlock(&chip->mutex);
411 return 0;
412 }
413
414 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
415 struct snd_pcm_hw_params *hw_params)
416 {
417 struct oxygen *chip = snd_pcm_substream_chip(substream);
418 int err;
419
420 err = oxygen_hw_params(substream, hw_params);
421 if (err < 0)
422 return err;
423
424 spin_lock_irq(&chip->reg_lock);
425 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
426 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
427 OXYGEN_REC_FORMAT_B_MASK);
428 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
429 oxygen_rate(hw_params) |
430 oxygen_i2s_mclk(hw_params) |
431 chip->model->adc_i2s_format |
432 oxygen_i2s_bits(hw_params),
433 OXYGEN_I2S_RATE_MASK |
434 OXYGEN_I2S_FORMAT_MASK |
435 OXYGEN_I2S_MCLK_MASK |
436 OXYGEN_I2S_BITS_MASK);
437 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
438 OXYGEN_REC_B_ROUTE_I2S_ADC_2,
439 OXYGEN_REC_B_ROUTE_MASK);
440 spin_unlock_irq(&chip->reg_lock);
441
442 mutex_lock(&chip->mutex);
443 chip->model->set_adc_params(chip, hw_params);
444 mutex_unlock(&chip->mutex);
445 return 0;
446 }
447
448 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
449 struct snd_pcm_hw_params *hw_params)
450 {
451 struct oxygen *chip = snd_pcm_substream_chip(substream);
452 int err;
453
454 err = oxygen_hw_params(substream, hw_params);
455 if (err < 0)
456 return err;
457
458 spin_lock_irq(&chip->reg_lock);
459 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
460 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
461 OXYGEN_REC_FORMAT_C_MASK);
462 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
463 OXYGEN_REC_C_ROUTE_SPDIF,
464 OXYGEN_REC_C_ROUTE_MASK);
465 spin_unlock_irq(&chip->reg_lock);
466 return 0;
467 }
468
469 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
470 struct snd_pcm_hw_params *hw_params)
471 {
472 struct oxygen *chip = snd_pcm_substream_chip(substream);
473 int err;
474
475 err = oxygen_hw_params(substream, hw_params);
476 if (err < 0)
477 return err;
478
479 spin_lock_irq(&chip->reg_lock);
480 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
481 OXYGEN_SPDIF_OUT_ENABLE);
482 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
483 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
484 OXYGEN_SPDIF_FORMAT_MASK);
485 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
486 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
487 OXYGEN_SPDIF_OUT_RATE_MASK);
488 oxygen_update_spdif_source(chip);
489 spin_unlock_irq(&chip->reg_lock);
490 return 0;
491 }
492
493 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
494 struct snd_pcm_hw_params *hw_params)
495 {
496 struct oxygen *chip = snd_pcm_substream_chip(substream);
497 int err;
498
499 err = oxygen_hw_params(substream, hw_params);
500 if (err < 0)
501 return err;
502
503 spin_lock_irq(&chip->reg_lock);
504 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
505 oxygen_play_channels(hw_params),
506 OXYGEN_PLAY_CHANNELS_MASK);
507 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
508 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
509 OXYGEN_MULTICH_FORMAT_MASK);
510 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
511 oxygen_rate(hw_params) |
512 chip->model->dac_i2s_format |
513 oxygen_i2s_bits(hw_params),
514 OXYGEN_I2S_RATE_MASK |
515 OXYGEN_I2S_FORMAT_MASK |
516 OXYGEN_I2S_BITS_MASK);
517 oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING,
518 OXYGEN_PLAY_MULTICH_I2S_DAC,
519 OXYGEN_PLAY_MUTE01 | OXYGEN_PLAY_MUTE23 |
520 OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67 |
521 OXYGEN_PLAY_MULTICH_MASK);
522 oxygen_update_dac_routing(chip);
523 oxygen_update_spdif_source(chip);
524 spin_unlock_irq(&chip->reg_lock);
525
526 mutex_lock(&chip->mutex);
527 chip->model->set_dac_params(chip, hw_params);
528 mutex_unlock(&chip->mutex);
529 return 0;
530 }
531
532 static int oxygen_hw_free(struct snd_pcm_substream *substream)
533 {
534 struct oxygen *chip = snd_pcm_substream_chip(substream);
535 unsigned int channel = oxygen_substream_channel(substream);
536
537 spin_lock_irq(&chip->reg_lock);
538 chip->interrupt_mask &= ~(1 << channel);
539 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
540 spin_unlock_irq(&chip->reg_lock);
541
542 return snd_pcm_lib_free_pages(substream);
543 }
544
545 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
546 {
547 struct oxygen *chip = snd_pcm_substream_chip(substream);
548
549 spin_lock_irq(&chip->reg_lock);
550 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
551 OXYGEN_SPDIF_OUT_ENABLE);
552 spin_unlock_irq(&chip->reg_lock);
553 return oxygen_hw_free(substream);
554 }
555
556 static int oxygen_prepare(struct snd_pcm_substream *substream)
557 {
558 struct oxygen *chip = snd_pcm_substream_chip(substream);
559 unsigned int channel = oxygen_substream_channel(substream);
560 unsigned int channel_mask = 1 << channel;
561
562 spin_lock_irq(&chip->reg_lock);
563 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
564 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
565
566 chip->interrupt_mask |= channel_mask;
567 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
568 spin_unlock_irq(&chip->reg_lock);
569 return 0;
570 }
571
572 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
573 {
574 struct oxygen *chip = snd_pcm_substream_chip(substream);
575 struct snd_pcm_substream *s;
576 unsigned int mask = 0;
577 int pausing;
578
579 switch (cmd) {
580 case SNDRV_PCM_TRIGGER_STOP:
581 case SNDRV_PCM_TRIGGER_START:
582 pausing = 0;
583 break;
584 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
585 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
586 pausing = 1;
587 break;
588 default:
589 return -EINVAL;
590 }
591
592 snd_pcm_group_for_each_entry(s, substream) {
593 if (snd_pcm_substream_chip(s) == chip) {
594 mask |= 1 << oxygen_substream_channel(s);
595 snd_pcm_trigger_done(s, substream);
596 }
597 }
598
599 spin_lock(&chip->reg_lock);
600 if (!pausing) {
601 if (cmd == SNDRV_PCM_TRIGGER_START)
602 chip->pcm_running |= mask;
603 else
604 chip->pcm_running &= ~mask;
605 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
606 } else {
607 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
608 oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
609 else
610 oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
611 }
612 spin_unlock(&chip->reg_lock);
613 return 0;
614 }
615
616 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
617 {
618 struct oxygen *chip = snd_pcm_substream_chip(substream);
619 struct snd_pcm_runtime *runtime = substream->runtime;
620 unsigned int channel = oxygen_substream_channel(substream);
621 u32 curr_addr;
622
623 /* no spinlock, this read should be atomic */
624 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
625 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
626 }
627
628 static struct snd_pcm_ops oxygen_rec_a_ops = {
629 .open = oxygen_rec_a_open,
630 .close = oxygen_close,
631 .ioctl = snd_pcm_lib_ioctl,
632 .hw_params = oxygen_rec_a_hw_params,
633 .hw_free = oxygen_hw_free,
634 .prepare = oxygen_prepare,
635 .trigger = oxygen_trigger,
636 .pointer = oxygen_pointer,
637 };
638
639 static struct snd_pcm_ops oxygen_rec_b_ops = {
640 .open = oxygen_rec_b_open,
641 .close = oxygen_close,
642 .ioctl = snd_pcm_lib_ioctl,
643 .hw_params = oxygen_rec_b_hw_params,
644 .hw_free = oxygen_hw_free,
645 .prepare = oxygen_prepare,
646 .trigger = oxygen_trigger,
647 .pointer = oxygen_pointer,
648 };
649
650 static struct snd_pcm_ops oxygen_rec_c_ops = {
651 .open = oxygen_rec_c_open,
652 .close = oxygen_close,
653 .ioctl = snd_pcm_lib_ioctl,
654 .hw_params = oxygen_rec_c_hw_params,
655 .hw_free = oxygen_hw_free,
656 .prepare = oxygen_prepare,
657 .trigger = oxygen_trigger,
658 .pointer = oxygen_pointer,
659 };
660
661 static struct snd_pcm_ops oxygen_spdif_ops = {
662 .open = oxygen_spdif_open,
663 .close = oxygen_close,
664 .ioctl = snd_pcm_lib_ioctl,
665 .hw_params = oxygen_spdif_hw_params,
666 .hw_free = oxygen_spdif_hw_free,
667 .prepare = oxygen_prepare,
668 .trigger = oxygen_trigger,
669 .pointer = oxygen_pointer,
670 };
671
672 static struct snd_pcm_ops oxygen_multich_ops = {
673 .open = oxygen_multich_open,
674 .close = oxygen_close,
675 .ioctl = snd_pcm_lib_ioctl,
676 .hw_params = oxygen_multich_hw_params,
677 .hw_free = oxygen_hw_free,
678 .prepare = oxygen_prepare,
679 .trigger = oxygen_trigger,
680 .pointer = oxygen_pointer,
681 };
682
683 static struct snd_pcm_ops oxygen_ac97_ops = {
684 .open = oxygen_ac97_open,
685 .close = oxygen_close,
686 .ioctl = snd_pcm_lib_ioctl,
687 .hw_params = oxygen_hw_params,
688 .hw_free = oxygen_hw_free,
689 .prepare = oxygen_prepare,
690 .trigger = oxygen_trigger,
691 .pointer = oxygen_pointer,
692 };
693
694 static void oxygen_pcm_free(struct snd_pcm *pcm)
695 {
696 snd_pcm_lib_preallocate_free_for_all(pcm);
697 }
698
699 int __devinit oxygen_pcm_init(struct oxygen *chip)
700 {
701 struct snd_pcm *pcm;
702 int outs, ins;
703 int err;
704
705 outs = 1; /* OXYGEN_CHANNEL_MULTICH is always used */
706 ins = !!(chip->model->used_channels & (OXYGEN_CHANNEL_A |
707 OXYGEN_CHANNEL_B));
708 err = snd_pcm_new(chip->card, "Analog", 0, outs, ins, &pcm);
709 if (err < 0)
710 return err;
711 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
712 if (chip->model->used_channels & OXYGEN_CHANNEL_A)
713 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
714 &oxygen_rec_a_ops);
715 else if (chip->model->used_channels & OXYGEN_CHANNEL_B)
716 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
717 &oxygen_rec_b_ops);
718 pcm->private_data = chip;
719 pcm->private_free = oxygen_pcm_free;
720 strcpy(pcm->name, "Analog");
721 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
722 SNDRV_DMA_TYPE_DEV,
723 snd_dma_pci_data(chip->pci),
724 512 * 1024, 2048 * 1024);
725 if (ins)
726 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
727 SNDRV_DMA_TYPE_DEV,
728 snd_dma_pci_data(chip->pci),
729 128 * 1024, 256 * 1024);
730
731 outs = !!(chip->model->used_channels & OXYGEN_CHANNEL_SPDIF);
732 ins = !!(chip->model->used_channels & OXYGEN_CHANNEL_C);
733 if (outs | ins) {
734 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
735 if (err < 0)
736 return err;
737 if (outs)
738 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
739 &oxygen_spdif_ops);
740 if (ins)
741 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
742 &oxygen_rec_c_ops);
743 pcm->private_data = chip;
744 pcm->private_free = oxygen_pcm_free;
745 strcpy(pcm->name, "Digital");
746 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
747 snd_dma_pci_data(chip->pci),
748 128 * 1024, 256 * 1024);
749 }
750
751 outs = chip->has_ac97_1 &&
752 (chip->model->used_channels & OXYGEN_CHANNEL_AC97);
753 ins = (chip->model->used_channels & (OXYGEN_CHANNEL_A |
754 OXYGEN_CHANNEL_B))
755 == (OXYGEN_CHANNEL_A | OXYGEN_CHANNEL_B);
756 if (outs | ins) {
757 err = snd_pcm_new(chip->card, ins ? "Analog2" : "AC97",
758 2, outs, ins, &pcm);
759 if (err < 0)
760 return err;
761 if (outs)
762 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
763 &oxygen_ac97_ops);
764 if (ins)
765 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
766 &oxygen_rec_b_ops);
767 pcm->private_data = chip;
768 pcm->private_free = oxygen_pcm_free;
769 strcpy(pcm->name, ins ? "Analog 2" : "Front Panel");
770 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
771 snd_dma_pci_data(chip->pci),
772 128 * 1024, 256 * 1024);
773 }
774 return 0;
775 }
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