1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
6 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
8 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
20 #include <sound/core.h>
21 #include <sound/info.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/asoundef.h>
26 #include <sound/initval.h>
28 /* note, two last pcis should be equal, it is not a bug */
30 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
31 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
33 MODULE_LICENSE("GPL");
35 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
36 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
37 static bool enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable this card */
39 module_param_array(index
, int, NULL
, 0444);
40 MODULE_PARM_DESC(index
, "Index value for RME Digi96 soundcard.");
41 module_param_array(id
, charp
, NULL
, 0444);
42 MODULE_PARM_DESC(id
, "ID string for RME Digi96 soundcard.");
43 module_param_array(enable
, bool, NULL
, 0444);
44 MODULE_PARM_DESC(enable
, "Enable RME Digi96 soundcard.");
47 * Defines for RME Digi96 series, from internal RME reference documents
51 #define RME96_SPDIF_NCHANNELS 2
53 /* Playback and capture buffer size */
54 #define RME96_BUFFER_SIZE 0x10000
57 #define RME96_IO_SIZE 0x60000
60 #define RME96_IO_PLAY_BUFFER 0x0
61 #define RME96_IO_REC_BUFFER 0x10000
62 #define RME96_IO_CONTROL_REGISTER 0x20000
63 #define RME96_IO_ADDITIONAL_REG 0x20004
64 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
65 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
66 #define RME96_IO_SET_PLAY_POS 0x40000
67 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
68 #define RME96_IO_SET_REC_POS 0x50000
69 #define RME96_IO_RESET_REC_POS 0x5FFFC
70 #define RME96_IO_GET_PLAY_POS 0x20000
71 #define RME96_IO_GET_REC_POS 0x30000
73 /* Write control register bits */
74 #define RME96_WCR_START (1 << 0)
75 #define RME96_WCR_START_2 (1 << 1)
76 #define RME96_WCR_GAIN_0 (1 << 2)
77 #define RME96_WCR_GAIN_1 (1 << 3)
78 #define RME96_WCR_MODE24 (1 << 4)
79 #define RME96_WCR_MODE24_2 (1 << 5)
80 #define RME96_WCR_BM (1 << 6)
81 #define RME96_WCR_BM_2 (1 << 7)
82 #define RME96_WCR_ADAT (1 << 8)
83 #define RME96_WCR_FREQ_0 (1 << 9)
84 #define RME96_WCR_FREQ_1 (1 << 10)
85 #define RME96_WCR_DS (1 << 11)
86 #define RME96_WCR_PRO (1 << 12)
87 #define RME96_WCR_EMP (1 << 13)
88 #define RME96_WCR_SEL (1 << 14)
89 #define RME96_WCR_MASTER (1 << 15)
90 #define RME96_WCR_PD (1 << 16)
91 #define RME96_WCR_INP_0 (1 << 17)
92 #define RME96_WCR_INP_1 (1 << 18)
93 #define RME96_WCR_THRU_0 (1 << 19)
94 #define RME96_WCR_THRU_1 (1 << 20)
95 #define RME96_WCR_THRU_2 (1 << 21)
96 #define RME96_WCR_THRU_3 (1 << 22)
97 #define RME96_WCR_THRU_4 (1 << 23)
98 #define RME96_WCR_THRU_5 (1 << 24)
99 #define RME96_WCR_THRU_6 (1 << 25)
100 #define RME96_WCR_THRU_7 (1 << 26)
101 #define RME96_WCR_DOLBY (1 << 27)
102 #define RME96_WCR_MONITOR_0 (1 << 28)
103 #define RME96_WCR_MONITOR_1 (1 << 29)
104 #define RME96_WCR_ISEL (1 << 30)
105 #define RME96_WCR_IDIS (1 << 31)
107 #define RME96_WCR_BITPOS_GAIN_0 2
108 #define RME96_WCR_BITPOS_GAIN_1 3
109 #define RME96_WCR_BITPOS_FREQ_0 9
110 #define RME96_WCR_BITPOS_FREQ_1 10
111 #define RME96_WCR_BITPOS_INP_0 17
112 #define RME96_WCR_BITPOS_INP_1 18
113 #define RME96_WCR_BITPOS_MONITOR_0 28
114 #define RME96_WCR_BITPOS_MONITOR_1 29
116 /* Read control register bits */
117 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
118 #define RME96_RCR_IRQ_2 (1 << 16)
119 #define RME96_RCR_T_OUT (1 << 17)
120 #define RME96_RCR_DEV_ID_0 (1 << 21)
121 #define RME96_RCR_DEV_ID_1 (1 << 22)
122 #define RME96_RCR_LOCK (1 << 23)
123 #define RME96_RCR_VERF (1 << 26)
124 #define RME96_RCR_F0 (1 << 27)
125 #define RME96_RCR_F1 (1 << 28)
126 #define RME96_RCR_F2 (1 << 29)
127 #define RME96_RCR_AUTOSYNC (1 << 30)
128 #define RME96_RCR_IRQ (1 << 31)
130 #define RME96_RCR_BITPOS_F0 27
131 #define RME96_RCR_BITPOS_F1 28
132 #define RME96_RCR_BITPOS_F2 29
134 /* Additional register bits */
135 #define RME96_AR_WSEL (1 << 0)
136 #define RME96_AR_ANALOG (1 << 1)
137 #define RME96_AR_FREQPAD_0 (1 << 2)
138 #define RME96_AR_FREQPAD_1 (1 << 3)
139 #define RME96_AR_FREQPAD_2 (1 << 4)
140 #define RME96_AR_PD2 (1 << 5)
141 #define RME96_AR_DAC_EN (1 << 6)
142 #define RME96_AR_CLATCH (1 << 7)
143 #define RME96_AR_CCLK (1 << 8)
144 #define RME96_AR_CDATA (1 << 9)
146 #define RME96_AR_BITPOS_F0 2
147 #define RME96_AR_BITPOS_F1 3
148 #define RME96_AR_BITPOS_F2 4
151 #define RME96_MONITOR_TRACKS_1_2 0
152 #define RME96_MONITOR_TRACKS_3_4 1
153 #define RME96_MONITOR_TRACKS_5_6 2
154 #define RME96_MONITOR_TRACKS_7_8 3
157 #define RME96_ATTENUATION_0 0
158 #define RME96_ATTENUATION_6 1
159 #define RME96_ATTENUATION_12 2
160 #define RME96_ATTENUATION_18 3
163 #define RME96_INPUT_OPTICAL 0
164 #define RME96_INPUT_COAXIAL 1
165 #define RME96_INPUT_INTERNAL 2
166 #define RME96_INPUT_XLR 3
167 #define RME96_INPUT_ANALOG 4
170 #define RME96_CLOCKMODE_SLAVE 0
171 #define RME96_CLOCKMODE_MASTER 1
172 #define RME96_CLOCKMODE_WORDCLOCK 2
174 /* Block sizes in bytes */
175 #define RME96_SMALL_BLOCK_SIZE 2048
176 #define RME96_LARGE_BLOCK_SIZE 8192
179 #define RME96_AD1852_VOL_BITS 14
180 #define RME96_AD1855_VOL_BITS 10
182 /* Defines for snd_rme96_trigger */
183 #define RME96_TB_START_PLAYBACK 1
184 #define RME96_TB_START_CAPTURE 2
185 #define RME96_TB_STOP_PLAYBACK 4
186 #define RME96_TB_STOP_CAPTURE 8
187 #define RME96_TB_RESET_PLAYPOS 16
188 #define RME96_TB_RESET_CAPTUREPOS 32
189 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
190 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
191 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
192 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
193 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
194 | RME96_RESUME_CAPTURE)
195 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
196 | RME96_TB_RESET_PLAYPOS)
197 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
198 | RME96_TB_RESET_CAPTUREPOS)
199 #define RME96_START_BOTH (RME96_START_PLAYBACK \
200 | RME96_START_CAPTURE)
201 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
202 | RME96_TB_CLEAR_PLAYBACK_IRQ)
203 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
204 | RME96_TB_CLEAR_CAPTURE_IRQ)
205 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
206 | RME96_STOP_CAPTURE)
212 void __iomem
*iobase
;
214 u32 wcreg
; /* cached write control register value */
215 u32 wcreg_spdif
; /* S/PDIF setup */
216 u32 wcreg_spdif_stream
; /* S/PDIF setup (temporary) */
217 u32 rcreg
; /* cached read control register value */
218 u32 areg
; /* cached additional register value */
219 u16 vol
[2]; /* cached volume of analog output */
221 u8 rev
; /* card revision number */
223 #ifdef CONFIG_PM_SLEEP
224 u32 playback_pointer
;
226 void *playback_suspend_buffer
;
227 void *capture_suspend_buffer
;
230 struct snd_pcm_substream
*playback_substream
;
231 struct snd_pcm_substream
*capture_substream
;
233 int playback_frlog
; /* log2 of framesize */
236 size_t playback_periodsize
; /* in bytes, zero if not used */
237 size_t capture_periodsize
; /* in bytes, zero if not used */
239 struct snd_card
*card
;
240 struct snd_pcm
*spdif_pcm
;
241 struct snd_pcm
*adat_pcm
;
243 struct snd_kcontrol
*spdif_ctl
;
246 static const struct pci_device_id snd_rme96_ids
[] = {
247 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96
), 0, },
248 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96_8
), 0, },
249 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96_8_PRO
), 0, },
250 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
), 0, },
254 MODULE_DEVICE_TABLE(pci
, snd_rme96_ids
);
256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
258 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
259 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
260 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
261 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
262 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
263 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
264 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
267 snd_rme96_playback_prepare(struct snd_pcm_substream
*substream
);
270 snd_rme96_capture_prepare(struct snd_pcm_substream
*substream
);
273 snd_rme96_playback_trigger(struct snd_pcm_substream
*substream
,
277 snd_rme96_capture_trigger(struct snd_pcm_substream
*substream
,
280 static snd_pcm_uframes_t
281 snd_rme96_playback_pointer(struct snd_pcm_substream
*substream
);
283 static snd_pcm_uframes_t
284 snd_rme96_capture_pointer(struct snd_pcm_substream
*substream
);
286 static void snd_rme96_proc_init(struct rme96
*rme96
);
289 snd_rme96_create_switches(struct snd_card
*card
,
290 struct rme96
*rme96
);
293 snd_rme96_getinputtype(struct rme96
*rme96
);
295 static inline unsigned int
296 snd_rme96_playback_ptr(struct rme96
*rme96
)
298 return (readl(rme96
->iobase
+ RME96_IO_GET_PLAY_POS
)
299 & RME96_RCR_AUDIO_ADDR_MASK
) >> rme96
->playback_frlog
;
302 static inline unsigned int
303 snd_rme96_capture_ptr(struct rme96
*rme96
)
305 return (readl(rme96
->iobase
+ RME96_IO_GET_REC_POS
)
306 & RME96_RCR_AUDIO_ADDR_MASK
) >> rme96
->capture_frlog
;
310 snd_rme96_playback_silence(struct snd_pcm_substream
*substream
,
311 int channel
, unsigned long pos
, unsigned long count
)
313 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
315 memset_io(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
,
321 snd_rme96_playback_copy(struct snd_pcm_substream
*substream
,
322 int channel
, unsigned long pos
,
323 void __user
*src
, unsigned long count
)
325 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
327 return copy_from_user_toio(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
,
332 snd_rme96_playback_copy_kernel(struct snd_pcm_substream
*substream
,
333 int channel
, unsigned long pos
,
334 void *src
, unsigned long count
)
336 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
338 memcpy_toio(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
, src
, count
);
343 snd_rme96_capture_copy(struct snd_pcm_substream
*substream
,
344 int channel
, unsigned long pos
,
345 void __user
*dst
, unsigned long count
)
347 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
349 return copy_to_user_fromio(dst
,
350 rme96
->iobase
+ RME96_IO_REC_BUFFER
+ pos
,
355 snd_rme96_capture_copy_kernel(struct snd_pcm_substream
*substream
,
356 int channel
, unsigned long pos
,
357 void *dst
, unsigned long count
)
359 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
361 memcpy_fromio(dst
, rme96
->iobase
+ RME96_IO_REC_BUFFER
+ pos
, count
);
366 * Digital output capabilities (S/PDIF)
368 static const struct snd_pcm_hardware snd_rme96_playback_spdif_info
=
370 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
371 SNDRV_PCM_INFO_MMAP_VALID
|
372 SNDRV_PCM_INFO_SYNC_START
|
373 SNDRV_PCM_INFO_RESUME
|
374 SNDRV_PCM_INFO_INTERLEAVED
|
375 SNDRV_PCM_INFO_PAUSE
),
376 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
377 SNDRV_PCM_FMTBIT_S32_LE
),
378 .rates
= (SNDRV_PCM_RATE_32000
|
379 SNDRV_PCM_RATE_44100
|
380 SNDRV_PCM_RATE_48000
|
381 SNDRV_PCM_RATE_64000
|
382 SNDRV_PCM_RATE_88200
|
383 SNDRV_PCM_RATE_96000
),
388 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
389 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
390 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
391 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
392 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
397 * Digital input capabilities (S/PDIF)
399 static const struct snd_pcm_hardware snd_rme96_capture_spdif_info
=
401 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
402 SNDRV_PCM_INFO_MMAP_VALID
|
403 SNDRV_PCM_INFO_SYNC_START
|
404 SNDRV_PCM_INFO_RESUME
|
405 SNDRV_PCM_INFO_INTERLEAVED
|
406 SNDRV_PCM_INFO_PAUSE
),
407 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
408 SNDRV_PCM_FMTBIT_S32_LE
),
409 .rates
= (SNDRV_PCM_RATE_32000
|
410 SNDRV_PCM_RATE_44100
|
411 SNDRV_PCM_RATE_48000
|
412 SNDRV_PCM_RATE_64000
|
413 SNDRV_PCM_RATE_88200
|
414 SNDRV_PCM_RATE_96000
),
419 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
420 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
421 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
422 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
423 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
428 * Digital output capabilities (ADAT)
430 static const struct snd_pcm_hardware snd_rme96_playback_adat_info
=
432 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
433 SNDRV_PCM_INFO_MMAP_VALID
|
434 SNDRV_PCM_INFO_SYNC_START
|
435 SNDRV_PCM_INFO_RESUME
|
436 SNDRV_PCM_INFO_INTERLEAVED
|
437 SNDRV_PCM_INFO_PAUSE
),
438 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
439 SNDRV_PCM_FMTBIT_S32_LE
),
440 .rates
= (SNDRV_PCM_RATE_44100
|
441 SNDRV_PCM_RATE_48000
),
446 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
447 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
448 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
449 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
450 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
455 * Digital input capabilities (ADAT)
457 static const struct snd_pcm_hardware snd_rme96_capture_adat_info
=
459 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
460 SNDRV_PCM_INFO_MMAP_VALID
|
461 SNDRV_PCM_INFO_SYNC_START
|
462 SNDRV_PCM_INFO_RESUME
|
463 SNDRV_PCM_INFO_INTERLEAVED
|
464 SNDRV_PCM_INFO_PAUSE
),
465 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
466 SNDRV_PCM_FMTBIT_S32_LE
),
467 .rates
= (SNDRV_PCM_RATE_44100
|
468 SNDRV_PCM_RATE_48000
),
473 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
474 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
475 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
476 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
477 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
482 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
483 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
484 * on the falling edge of CCLK and be stable on the rising edge. The rising
485 * edge of CLATCH after the last data bit clocks in the whole data word.
486 * A fast processor could probably drive the SPI interface faster than the
487 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
488 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
490 * NOTE: increased delay from 1 to 10, since there where problems setting
494 snd_rme96_write_SPI(struct rme96
*rme96
, u16 val
)
498 for (i
= 0; i
< 16; i
++) {
500 rme96
->areg
|= RME96_AR_CDATA
;
502 rme96
->areg
&= ~RME96_AR_CDATA
;
504 rme96
->areg
&= ~(RME96_AR_CCLK
| RME96_AR_CLATCH
);
505 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
507 rme96
->areg
|= RME96_AR_CCLK
;
508 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
512 rme96
->areg
&= ~(RME96_AR_CCLK
| RME96_AR_CDATA
);
513 rme96
->areg
|= RME96_AR_CLATCH
;
514 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
516 rme96
->areg
&= ~RME96_AR_CLATCH
;
517 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
521 snd_rme96_apply_dac_volume(struct rme96
*rme96
)
523 if (RME96_DAC_IS_1852(rme96
)) {
524 snd_rme96_write_SPI(rme96
, (rme96
->vol
[0] << 2) | 0x0);
525 snd_rme96_write_SPI(rme96
, (rme96
->vol
[1] << 2) | 0x2);
526 } else if (RME96_DAC_IS_1855(rme96
)) {
527 snd_rme96_write_SPI(rme96
, (rme96
->vol
[0] & 0x3FF) | 0x000);
528 snd_rme96_write_SPI(rme96
, (rme96
->vol
[1] & 0x3FF) | 0x400);
533 snd_rme96_reset_dac(struct rme96
*rme96
)
535 writel(rme96
->wcreg
| RME96_WCR_PD
,
536 rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
537 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
541 snd_rme96_getmontracks(struct rme96
*rme96
)
543 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_MONITOR_0
) & 1) +
544 (((rme96
->wcreg
>> RME96_WCR_BITPOS_MONITOR_1
) & 1) << 1);
548 snd_rme96_setmontracks(struct rme96
*rme96
,
552 rme96
->wcreg
|= RME96_WCR_MONITOR_0
;
554 rme96
->wcreg
&= ~RME96_WCR_MONITOR_0
;
557 rme96
->wcreg
|= RME96_WCR_MONITOR_1
;
559 rme96
->wcreg
&= ~RME96_WCR_MONITOR_1
;
561 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
566 snd_rme96_getattenuation(struct rme96
*rme96
)
568 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_GAIN_0
) & 1) +
569 (((rme96
->wcreg
>> RME96_WCR_BITPOS_GAIN_1
) & 1) << 1);
573 snd_rme96_setattenuation(struct rme96
*rme96
,
576 switch (attenuation
) {
578 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_GAIN_0
) &
582 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_GAIN_0
) &
586 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_GAIN_0
) |
590 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_GAIN_0
) |
596 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
601 snd_rme96_capture_getrate(struct rme96
*rme96
,
607 if (rme96
->areg
& RME96_AR_ANALOG
) {
608 /* Analog input, overrides S/PDIF setting */
609 n
= ((rme96
->areg
>> RME96_AR_BITPOS_F0
) & 1) +
610 (((rme96
->areg
>> RME96_AR_BITPOS_F1
) & 1) << 1);
624 return (rme96
->areg
& RME96_AR_BITPOS_F2
) ? rate
<< 1 : rate
;
627 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
628 if (rme96
->rcreg
& RME96_RCR_LOCK
) {
631 if (rme96
->rcreg
& RME96_RCR_T_OUT
) {
637 if (rme96
->rcreg
& RME96_RCR_VERF
) {
642 n
= ((rme96
->rcreg
>> RME96_RCR_BITPOS_F0
) & 1) +
643 (((rme96
->rcreg
>> RME96_RCR_BITPOS_F1
) & 1) << 1) +
644 (((rme96
->rcreg
>> RME96_RCR_BITPOS_F2
) & 1) << 2);
648 if (rme96
->rcreg
& RME96_RCR_T_OUT
) {
652 case 3: return 96000;
653 case 4: return 88200;
654 case 5: return 48000;
655 case 6: return 44100;
656 case 7: return 32000;
664 snd_rme96_playback_getrate(struct rme96
*rme96
)
668 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
669 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
) {
670 rate
= snd_rme96_capture_getrate(rme96
, &dummy
);
677 rate
= ((rme96
->wcreg
>> RME96_WCR_BITPOS_FREQ_0
) & 1) +
678 (((rme96
->wcreg
>> RME96_WCR_BITPOS_FREQ_1
) & 1) << 1);
692 return (rme96
->wcreg
& RME96_WCR_DS
) ? rate
<< 1 : rate
;
696 snd_rme96_playback_setrate(struct rme96
*rme96
,
701 ds
= rme96
->wcreg
& RME96_WCR_DS
;
704 rme96
->wcreg
&= ~RME96_WCR_DS
;
705 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) &
709 rme96
->wcreg
&= ~RME96_WCR_DS
;
710 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_1
) &
714 rme96
->wcreg
&= ~RME96_WCR_DS
;
715 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) |
719 rme96
->wcreg
|= RME96_WCR_DS
;
720 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) &
724 rme96
->wcreg
|= RME96_WCR_DS
;
725 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_1
) &
729 rme96
->wcreg
|= RME96_WCR_DS
;
730 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) |
736 if ((!ds
&& rme96
->wcreg
& RME96_WCR_DS
) ||
737 (ds
&& !(rme96
->wcreg
& RME96_WCR_DS
)))
739 /* change to/from double-speed: reset the DAC (if available) */
740 snd_rme96_reset_dac(rme96
);
741 return 1; /* need to restore volume */
743 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
749 snd_rme96_capture_analog_setrate(struct rme96
*rme96
,
754 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) &
755 ~RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
758 rme96
->areg
= ((rme96
->areg
& ~RME96_AR_FREQPAD_0
) |
759 RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
762 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) |
763 RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
766 if (rme96
->rev
< 4) {
769 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) &
770 ~RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
773 if (rme96
->rev
< 4) {
776 rme96
->areg
= ((rme96
->areg
& ~RME96_AR_FREQPAD_0
) |
777 RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
780 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) |
781 RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
786 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
791 snd_rme96_setclockmode(struct rme96
*rme96
,
795 case RME96_CLOCKMODE_SLAVE
:
797 rme96
->wcreg
&= ~RME96_WCR_MASTER
;
798 rme96
->areg
&= ~RME96_AR_WSEL
;
800 case RME96_CLOCKMODE_MASTER
:
802 rme96
->wcreg
|= RME96_WCR_MASTER
;
803 rme96
->areg
&= ~RME96_AR_WSEL
;
805 case RME96_CLOCKMODE_WORDCLOCK
:
806 /* Word clock is a master mode */
807 rme96
->wcreg
|= RME96_WCR_MASTER
;
808 rme96
->areg
|= RME96_AR_WSEL
;
813 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
814 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
819 snd_rme96_getclockmode(struct rme96
*rme96
)
821 if (rme96
->areg
& RME96_AR_WSEL
) {
822 return RME96_CLOCKMODE_WORDCLOCK
;
824 return (rme96
->wcreg
& RME96_WCR_MASTER
) ? RME96_CLOCKMODE_MASTER
:
825 RME96_CLOCKMODE_SLAVE
;
829 snd_rme96_setinputtype(struct rme96
*rme96
,
835 case RME96_INPUT_OPTICAL
:
836 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_INP_0
) &
839 case RME96_INPUT_COAXIAL
:
840 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_INP_0
) &
843 case RME96_INPUT_INTERNAL
:
844 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_INP_0
) |
847 case RME96_INPUT_XLR
:
848 if ((rme96
->pci
->device
!= PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&&
849 rme96
->pci
->device
!= PCI_DEVICE_ID_RME_DIGI96_8_PRO
) ||
850 (rme96
->pci
->device
== PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&&
853 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
856 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_INP_0
) |
859 case RME96_INPUT_ANALOG
:
860 if (!RME96_HAS_ANALOG_IN(rme96
)) {
863 rme96
->areg
|= RME96_AR_ANALOG
;
864 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
865 if (rme96
->rev
< 4) {
867 * Revision less than 004 does not support 64 and
870 if (snd_rme96_capture_getrate(rme96
, &n
) == 88200) {
871 snd_rme96_capture_analog_setrate(rme96
, 44100);
873 if (snd_rme96_capture_getrate(rme96
, &n
) == 64000) {
874 snd_rme96_capture_analog_setrate(rme96
, 32000);
881 if (type
!= RME96_INPUT_ANALOG
&& RME96_HAS_ANALOG_IN(rme96
)) {
882 rme96
->areg
&= ~RME96_AR_ANALOG
;
883 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
885 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
890 snd_rme96_getinputtype(struct rme96
*rme96
)
892 if (rme96
->areg
& RME96_AR_ANALOG
) {
893 return RME96_INPUT_ANALOG
;
895 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_INP_0
) & 1) +
896 (((rme96
->wcreg
>> RME96_WCR_BITPOS_INP_1
) & 1) << 1);
900 snd_rme96_setframelog(struct rme96
*rme96
,
906 if (n_channels
== 2) {
909 /* assume 8 channels */
913 frlog
+= (rme96
->wcreg
& RME96_WCR_MODE24
) ? 2 : 1;
914 rme96
->playback_frlog
= frlog
;
916 frlog
+= (rme96
->wcreg
& RME96_WCR_MODE24_2
) ? 2 : 1;
917 rme96
->capture_frlog
= frlog
;
922 snd_rme96_playback_setformat(struct rme96
*rme96
, snd_pcm_format_t format
)
925 case SNDRV_PCM_FORMAT_S16_LE
:
926 rme96
->wcreg
&= ~RME96_WCR_MODE24
;
928 case SNDRV_PCM_FORMAT_S32_LE
:
929 rme96
->wcreg
|= RME96_WCR_MODE24
;
934 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
939 snd_rme96_capture_setformat(struct rme96
*rme96
, snd_pcm_format_t format
)
942 case SNDRV_PCM_FORMAT_S16_LE
:
943 rme96
->wcreg
&= ~RME96_WCR_MODE24_2
;
945 case SNDRV_PCM_FORMAT_S32_LE
:
946 rme96
->wcreg
|= RME96_WCR_MODE24_2
;
951 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
956 snd_rme96_set_period_properties(struct rme96
*rme96
,
959 switch (period_bytes
) {
960 case RME96_LARGE_BLOCK_SIZE
:
961 rme96
->wcreg
&= ~RME96_WCR_ISEL
;
963 case RME96_SMALL_BLOCK_SIZE
:
964 rme96
->wcreg
|= RME96_WCR_ISEL
;
970 rme96
->wcreg
&= ~RME96_WCR_IDIS
;
971 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
975 snd_rme96_playback_hw_params(struct snd_pcm_substream
*substream
,
976 struct snd_pcm_hw_params
*params
)
978 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
979 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
980 int err
, rate
, dummy
;
981 bool apply_dac_volume
= false;
983 runtime
->dma_area
= (void __force
*)(rme96
->iobase
+
984 RME96_IO_PLAY_BUFFER
);
985 runtime
->dma_addr
= rme96
->port
+ RME96_IO_PLAY_BUFFER
;
986 runtime
->dma_bytes
= RME96_BUFFER_SIZE
;
988 spin_lock_irq(&rme96
->lock
);
990 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
991 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
)
992 rate
= snd_rme96_capture_getrate(rme96
, &dummy
);
995 if ((int)params_rate(params
) != rate
) {
1000 err
= snd_rme96_playback_setrate(rme96
, params_rate(params
));
1003 apply_dac_volume
= err
> 0; /* need to restore volume later? */
1006 err
= snd_rme96_playback_setformat(rme96
, params_format(params
));
1009 snd_rme96_setframelog(rme96
, params_channels(params
), 1);
1010 if (rme96
->capture_periodsize
!= 0) {
1011 if (params_period_size(params
) << rme96
->playback_frlog
!=
1012 rme96
->capture_periodsize
)
1018 rme96
->playback_periodsize
=
1019 params_period_size(params
) << rme96
->playback_frlog
;
1020 snd_rme96_set_period_properties(rme96
, rme96
->playback_periodsize
);
1022 if ((rme96
->wcreg
& RME96_WCR_ADAT
) == 0) {
1023 rme96
->wcreg
&= ~(RME96_WCR_PRO
| RME96_WCR_DOLBY
| RME96_WCR_EMP
);
1024 writel(rme96
->wcreg
|= rme96
->wcreg_spdif_stream
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1029 spin_unlock_irq(&rme96
->lock
);
1030 if (apply_dac_volume
) {
1031 usleep_range(3000, 10000);
1032 snd_rme96_apply_dac_volume(rme96
);
1039 snd_rme96_capture_hw_params(struct snd_pcm_substream
*substream
,
1040 struct snd_pcm_hw_params
*params
)
1042 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1043 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1044 int err
, isadat
, rate
;
1046 runtime
->dma_area
= (void __force
*)(rme96
->iobase
+
1047 RME96_IO_REC_BUFFER
);
1048 runtime
->dma_addr
= rme96
->port
+ RME96_IO_REC_BUFFER
;
1049 runtime
->dma_bytes
= RME96_BUFFER_SIZE
;
1051 spin_lock_irq(&rme96
->lock
);
1052 err
= snd_rme96_capture_setformat(rme96
, params_format(params
));
1054 spin_unlock_irq(&rme96
->lock
);
1057 if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1058 err
= snd_rme96_capture_analog_setrate(rme96
, params_rate(params
));
1060 spin_unlock_irq(&rme96
->lock
);
1064 rate
= snd_rme96_capture_getrate(rme96
, &isadat
);
1066 if ((int)params_rate(params
) != rate
) {
1067 spin_unlock_irq(&rme96
->lock
);
1070 if ((isadat
&& runtime
->hw
.channels_min
== 2) ||
1071 (!isadat
&& runtime
->hw
.channels_min
== 8)) {
1072 spin_unlock_irq(&rme96
->lock
);
1077 snd_rme96_setframelog(rme96
, params_channels(params
), 0);
1078 if (rme96
->playback_periodsize
!= 0) {
1079 if (params_period_size(params
) << rme96
->capture_frlog
!=
1080 rme96
->playback_periodsize
)
1082 spin_unlock_irq(&rme96
->lock
);
1086 rme96
->capture_periodsize
=
1087 params_period_size(params
) << rme96
->capture_frlog
;
1088 snd_rme96_set_period_properties(rme96
, rme96
->capture_periodsize
);
1089 spin_unlock_irq(&rme96
->lock
);
1095 snd_rme96_trigger(struct rme96
*rme96
,
1098 if (op
& RME96_TB_RESET_PLAYPOS
)
1099 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1100 if (op
& RME96_TB_RESET_CAPTUREPOS
)
1101 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1102 if (op
& RME96_TB_CLEAR_PLAYBACK_IRQ
) {
1103 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1104 if (rme96
->rcreg
& RME96_RCR_IRQ
)
1105 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_PLAY_IRQ
);
1107 if (op
& RME96_TB_CLEAR_CAPTURE_IRQ
) {
1108 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1109 if (rme96
->rcreg
& RME96_RCR_IRQ_2
)
1110 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_REC_IRQ
);
1112 if (op
& RME96_TB_START_PLAYBACK
)
1113 rme96
->wcreg
|= RME96_WCR_START
;
1114 if (op
& RME96_TB_STOP_PLAYBACK
)
1115 rme96
->wcreg
&= ~RME96_WCR_START
;
1116 if (op
& RME96_TB_START_CAPTURE
)
1117 rme96
->wcreg
|= RME96_WCR_START_2
;
1118 if (op
& RME96_TB_STOP_CAPTURE
)
1119 rme96
->wcreg
&= ~RME96_WCR_START_2
;
1120 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1126 snd_rme96_interrupt(int irq
,
1129 struct rme96
*rme96
= (struct rme96
*)dev_id
;
1131 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1132 /* fastpath out, to ease interrupt sharing */
1133 if (!((rme96
->rcreg
& RME96_RCR_IRQ
) ||
1134 (rme96
->rcreg
& RME96_RCR_IRQ_2
)))
1139 if (rme96
->rcreg
& RME96_RCR_IRQ
) {
1141 snd_pcm_period_elapsed(rme96
->playback_substream
);
1142 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_PLAY_IRQ
);
1144 if (rme96
->rcreg
& RME96_RCR_IRQ_2
) {
1146 snd_pcm_period_elapsed(rme96
->capture_substream
);
1147 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_REC_IRQ
);
1152 static const unsigned int period_bytes
[] = { RME96_SMALL_BLOCK_SIZE
, RME96_LARGE_BLOCK_SIZE
};
1154 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes
= {
1155 .count
= ARRAY_SIZE(period_bytes
),
1156 .list
= period_bytes
,
1161 rme96_set_buffer_size_constraint(struct rme96
*rme96
,
1162 struct snd_pcm_runtime
*runtime
)
1166 snd_pcm_hw_constraint_single(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1168 size
= rme96
->playback_periodsize
;
1170 size
= rme96
->capture_periodsize
;
1172 snd_pcm_hw_constraint_single(runtime
,
1173 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1176 snd_pcm_hw_constraint_list(runtime
, 0,
1177 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1178 &hw_constraints_period_bytes
);
1182 snd_rme96_playback_spdif_open(struct snd_pcm_substream
*substream
)
1185 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1186 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1188 snd_pcm_set_sync(substream
);
1189 spin_lock_irq(&rme96
->lock
);
1190 if (rme96
->playback_substream
) {
1191 spin_unlock_irq(&rme96
->lock
);
1194 rme96
->wcreg
&= ~RME96_WCR_ADAT
;
1195 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1196 rme96
->playback_substream
= substream
;
1197 spin_unlock_irq(&rme96
->lock
);
1199 runtime
->hw
= snd_rme96_playback_spdif_info
;
1200 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
1201 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
) {
1202 rate
= snd_rme96_capture_getrate(rme96
, &dummy
);
1205 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1206 runtime
->hw
.rate_min
= rate
;
1207 runtime
->hw
.rate_max
= rate
;
1210 rme96_set_buffer_size_constraint(rme96
, runtime
);
1212 rme96
->wcreg_spdif_stream
= rme96
->wcreg_spdif
;
1213 rme96
->spdif_ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1214 snd_ctl_notify(rme96
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
1215 SNDRV_CTL_EVENT_MASK_INFO
, &rme96
->spdif_ctl
->id
);
1220 snd_rme96_capture_spdif_open(struct snd_pcm_substream
*substream
)
1223 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1224 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1226 snd_pcm_set_sync(substream
);
1227 runtime
->hw
= snd_rme96_capture_spdif_info
;
1228 if (snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
) {
1229 rate
= snd_rme96_capture_getrate(rme96
, &isadat
);
1233 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1234 runtime
->hw
.rate_min
= rate
;
1235 runtime
->hw
.rate_max
= rate
;
1239 spin_lock_irq(&rme96
->lock
);
1240 if (rme96
->capture_substream
) {
1241 spin_unlock_irq(&rme96
->lock
);
1244 rme96
->capture_substream
= substream
;
1245 spin_unlock_irq(&rme96
->lock
);
1247 rme96_set_buffer_size_constraint(rme96
, runtime
);
1252 snd_rme96_playback_adat_open(struct snd_pcm_substream
*substream
)
1255 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1256 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1258 snd_pcm_set_sync(substream
);
1259 spin_lock_irq(&rme96
->lock
);
1260 if (rme96
->playback_substream
) {
1261 spin_unlock_irq(&rme96
->lock
);
1264 rme96
->wcreg
|= RME96_WCR_ADAT
;
1265 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1266 rme96
->playback_substream
= substream
;
1267 spin_unlock_irq(&rme96
->lock
);
1269 runtime
->hw
= snd_rme96_playback_adat_info
;
1270 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
1271 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
) {
1272 rate
= snd_rme96_capture_getrate(rme96
, &dummy
);
1275 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1276 runtime
->hw
.rate_min
= rate
;
1277 runtime
->hw
.rate_max
= rate
;
1281 rme96_set_buffer_size_constraint(rme96
, runtime
);
1286 snd_rme96_capture_adat_open(struct snd_pcm_substream
*substream
)
1289 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1290 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1292 snd_pcm_set_sync(substream
);
1293 runtime
->hw
= snd_rme96_capture_adat_info
;
1294 if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1295 /* makes no sense to use analog input. Note that analog
1296 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1299 rate
= snd_rme96_capture_getrate(rme96
, &isadat
);
1304 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1305 runtime
->hw
.rate_min
= rate
;
1306 runtime
->hw
.rate_max
= rate
;
1309 spin_lock_irq(&rme96
->lock
);
1310 if (rme96
->capture_substream
) {
1311 spin_unlock_irq(&rme96
->lock
);
1314 rme96
->capture_substream
= substream
;
1315 spin_unlock_irq(&rme96
->lock
);
1317 rme96_set_buffer_size_constraint(rme96
, runtime
);
1322 snd_rme96_playback_close(struct snd_pcm_substream
*substream
)
1324 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1327 spin_lock_irq(&rme96
->lock
);
1328 if (RME96_ISPLAYING(rme96
)) {
1329 snd_rme96_trigger(rme96
, RME96_STOP_PLAYBACK
);
1331 rme96
->playback_substream
= NULL
;
1332 rme96
->playback_periodsize
= 0;
1333 spdif
= (rme96
->wcreg
& RME96_WCR_ADAT
) == 0;
1334 spin_unlock_irq(&rme96
->lock
);
1336 rme96
->spdif_ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1337 snd_ctl_notify(rme96
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
1338 SNDRV_CTL_EVENT_MASK_INFO
, &rme96
->spdif_ctl
->id
);
1344 snd_rme96_capture_close(struct snd_pcm_substream
*substream
)
1346 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1348 spin_lock_irq(&rme96
->lock
);
1349 if (RME96_ISRECORDING(rme96
)) {
1350 snd_rme96_trigger(rme96
, RME96_STOP_CAPTURE
);
1352 rme96
->capture_substream
= NULL
;
1353 rme96
->capture_periodsize
= 0;
1354 spin_unlock_irq(&rme96
->lock
);
1359 snd_rme96_playback_prepare(struct snd_pcm_substream
*substream
)
1361 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1363 spin_lock_irq(&rme96
->lock
);
1364 if (RME96_ISPLAYING(rme96
)) {
1365 snd_rme96_trigger(rme96
, RME96_STOP_PLAYBACK
);
1367 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1368 spin_unlock_irq(&rme96
->lock
);
1373 snd_rme96_capture_prepare(struct snd_pcm_substream
*substream
)
1375 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1377 spin_lock_irq(&rme96
->lock
);
1378 if (RME96_ISRECORDING(rme96
)) {
1379 snd_rme96_trigger(rme96
, RME96_STOP_CAPTURE
);
1381 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1382 spin_unlock_irq(&rme96
->lock
);
1387 snd_rme96_playback_trigger(struct snd_pcm_substream
*substream
,
1390 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1391 struct snd_pcm_substream
*s
;
1394 snd_pcm_group_for_each_entry(s
, substream
) {
1395 if (snd_pcm_substream_chip(s
) == rme96
)
1396 snd_pcm_trigger_done(s
, substream
);
1399 sync
= (rme96
->playback_substream
&& rme96
->capture_substream
) &&
1400 (rme96
->playback_substream
->group
==
1401 rme96
->capture_substream
->group
);
1404 case SNDRV_PCM_TRIGGER_START
:
1405 if (!RME96_ISPLAYING(rme96
)) {
1406 if (substream
!= rme96
->playback_substream
)
1408 snd_rme96_trigger(rme96
, sync
? RME96_START_BOTH
1409 : RME96_START_PLAYBACK
);
1413 case SNDRV_PCM_TRIGGER_SUSPEND
:
1414 case SNDRV_PCM_TRIGGER_STOP
:
1415 if (RME96_ISPLAYING(rme96
)) {
1416 if (substream
!= rme96
->playback_substream
)
1418 snd_rme96_trigger(rme96
, sync
? RME96_STOP_BOTH
1419 : RME96_STOP_PLAYBACK
);
1423 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1424 if (RME96_ISPLAYING(rme96
))
1425 snd_rme96_trigger(rme96
, sync
? RME96_STOP_BOTH
1426 : RME96_STOP_PLAYBACK
);
1429 case SNDRV_PCM_TRIGGER_RESUME
:
1430 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1431 if (!RME96_ISPLAYING(rme96
))
1432 snd_rme96_trigger(rme96
, sync
? RME96_RESUME_BOTH
1433 : RME96_RESUME_PLAYBACK
);
1444 snd_rme96_capture_trigger(struct snd_pcm_substream
*substream
,
1447 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1448 struct snd_pcm_substream
*s
;
1451 snd_pcm_group_for_each_entry(s
, substream
) {
1452 if (snd_pcm_substream_chip(s
) == rme96
)
1453 snd_pcm_trigger_done(s
, substream
);
1456 sync
= (rme96
->playback_substream
&& rme96
->capture_substream
) &&
1457 (rme96
->playback_substream
->group
==
1458 rme96
->capture_substream
->group
);
1461 case SNDRV_PCM_TRIGGER_START
:
1462 if (!RME96_ISRECORDING(rme96
)) {
1463 if (substream
!= rme96
->capture_substream
)
1465 snd_rme96_trigger(rme96
, sync
? RME96_START_BOTH
1466 : RME96_START_CAPTURE
);
1470 case SNDRV_PCM_TRIGGER_SUSPEND
:
1471 case SNDRV_PCM_TRIGGER_STOP
:
1472 if (RME96_ISRECORDING(rme96
)) {
1473 if (substream
!= rme96
->capture_substream
)
1475 snd_rme96_trigger(rme96
, sync
? RME96_STOP_BOTH
1476 : RME96_STOP_CAPTURE
);
1480 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1481 if (RME96_ISRECORDING(rme96
))
1482 snd_rme96_trigger(rme96
, sync
? RME96_STOP_BOTH
1483 : RME96_STOP_CAPTURE
);
1486 case SNDRV_PCM_TRIGGER_RESUME
:
1487 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1488 if (!RME96_ISRECORDING(rme96
))
1489 snd_rme96_trigger(rme96
, sync
? RME96_RESUME_BOTH
1490 : RME96_RESUME_CAPTURE
);
1500 static snd_pcm_uframes_t
1501 snd_rme96_playback_pointer(struct snd_pcm_substream
*substream
)
1503 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1504 return snd_rme96_playback_ptr(rme96
);
1507 static snd_pcm_uframes_t
1508 snd_rme96_capture_pointer(struct snd_pcm_substream
*substream
)
1510 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1511 return snd_rme96_capture_ptr(rme96
);
1514 static const struct snd_pcm_ops snd_rme96_playback_spdif_ops
= {
1515 .open
= snd_rme96_playback_spdif_open
,
1516 .close
= snd_rme96_playback_close
,
1517 .hw_params
= snd_rme96_playback_hw_params
,
1518 .prepare
= snd_rme96_playback_prepare
,
1519 .trigger
= snd_rme96_playback_trigger
,
1520 .pointer
= snd_rme96_playback_pointer
,
1521 .copy_user
= snd_rme96_playback_copy
,
1522 .copy_kernel
= snd_rme96_playback_copy_kernel
,
1523 .fill_silence
= snd_rme96_playback_silence
,
1524 .mmap
= snd_pcm_lib_mmap_iomem
,
1527 static const struct snd_pcm_ops snd_rme96_capture_spdif_ops
= {
1528 .open
= snd_rme96_capture_spdif_open
,
1529 .close
= snd_rme96_capture_close
,
1530 .hw_params
= snd_rme96_capture_hw_params
,
1531 .prepare
= snd_rme96_capture_prepare
,
1532 .trigger
= snd_rme96_capture_trigger
,
1533 .pointer
= snd_rme96_capture_pointer
,
1534 .copy_user
= snd_rme96_capture_copy
,
1535 .copy_kernel
= snd_rme96_capture_copy_kernel
,
1536 .mmap
= snd_pcm_lib_mmap_iomem
,
1539 static const struct snd_pcm_ops snd_rme96_playback_adat_ops
= {
1540 .open
= snd_rme96_playback_adat_open
,
1541 .close
= snd_rme96_playback_close
,
1542 .hw_params
= snd_rme96_playback_hw_params
,
1543 .prepare
= snd_rme96_playback_prepare
,
1544 .trigger
= snd_rme96_playback_trigger
,
1545 .pointer
= snd_rme96_playback_pointer
,
1546 .copy_user
= snd_rme96_playback_copy
,
1547 .copy_kernel
= snd_rme96_playback_copy_kernel
,
1548 .fill_silence
= snd_rme96_playback_silence
,
1549 .mmap
= snd_pcm_lib_mmap_iomem
,
1552 static const struct snd_pcm_ops snd_rme96_capture_adat_ops
= {
1553 .open
= snd_rme96_capture_adat_open
,
1554 .close
= snd_rme96_capture_close
,
1555 .hw_params
= snd_rme96_capture_hw_params
,
1556 .prepare
= snd_rme96_capture_prepare
,
1557 .trigger
= snd_rme96_capture_trigger
,
1558 .pointer
= snd_rme96_capture_pointer
,
1559 .copy_user
= snd_rme96_capture_copy
,
1560 .copy_kernel
= snd_rme96_capture_copy_kernel
,
1561 .mmap
= snd_pcm_lib_mmap_iomem
,
1565 snd_rme96_free(struct rme96
*rme96
)
1567 if (rme96
->irq
>= 0) {
1568 snd_rme96_trigger(rme96
, RME96_STOP_BOTH
);
1569 rme96
->areg
&= ~RME96_AR_DAC_EN
;
1570 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1572 #ifdef CONFIG_PM_SLEEP
1573 vfree(rme96
->playback_suspend_buffer
);
1574 vfree(rme96
->capture_suspend_buffer
);
1579 snd_rme96_free_spdif_pcm(struct snd_pcm
*pcm
)
1581 struct rme96
*rme96
= pcm
->private_data
;
1582 rme96
->spdif_pcm
= NULL
;
1586 snd_rme96_free_adat_pcm(struct snd_pcm
*pcm
)
1588 struct rme96
*rme96
= pcm
->private_data
;
1589 rme96
->adat_pcm
= NULL
;
1593 snd_rme96_create(struct rme96
*rme96
)
1595 struct pci_dev
*pci
= rme96
->pci
;
1599 spin_lock_init(&rme96
->lock
);
1601 err
= pcim_enable_device(pci
);
1605 err
= pci_request_regions(pci
, "RME96");
1608 rme96
->port
= pci_resource_start(rme96
->pci
, 0);
1610 rme96
->iobase
= devm_ioremap(&pci
->dev
, rme96
->port
, RME96_IO_SIZE
);
1611 if (!rme96
->iobase
) {
1612 dev_err(rme96
->card
->dev
,
1613 "unable to remap memory region 0x%lx-0x%lx\n",
1614 rme96
->port
, rme96
->port
+ RME96_IO_SIZE
- 1);
1618 if (devm_request_irq(&pci
->dev
, pci
->irq
, snd_rme96_interrupt
,
1619 IRQF_SHARED
, KBUILD_MODNAME
, rme96
)) {
1620 dev_err(rme96
->card
->dev
, "unable to grab IRQ %d\n", pci
->irq
);
1623 rme96
->irq
= pci
->irq
;
1624 rme96
->card
->sync_irq
= rme96
->irq
;
1626 /* read the card's revision number */
1627 pci_read_config_byte(pci
, 8, &rme96
->rev
);
1629 /* set up ALSA pcm device for S/PDIF */
1630 err
= snd_pcm_new(rme96
->card
, "Digi96 IEC958", 0,
1631 1, 1, &rme96
->spdif_pcm
);
1635 rme96
->spdif_pcm
->private_data
= rme96
;
1636 rme96
->spdif_pcm
->private_free
= snd_rme96_free_spdif_pcm
;
1637 strcpy(rme96
->spdif_pcm
->name
, "Digi96 IEC958");
1638 snd_pcm_set_ops(rme96
->spdif_pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_rme96_playback_spdif_ops
);
1639 snd_pcm_set_ops(rme96
->spdif_pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_rme96_capture_spdif_ops
);
1641 rme96
->spdif_pcm
->info_flags
= 0;
1643 /* set up ALSA pcm device for ADAT */
1644 if (pci
->device
== PCI_DEVICE_ID_RME_DIGI96
) {
1645 /* ADAT is not available on the base model */
1646 rme96
->adat_pcm
= NULL
;
1648 err
= snd_pcm_new(rme96
->card
, "Digi96 ADAT", 1,
1649 1, 1, &rme96
->adat_pcm
);
1652 rme96
->adat_pcm
->private_data
= rme96
;
1653 rme96
->adat_pcm
->private_free
= snd_rme96_free_adat_pcm
;
1654 strcpy(rme96
->adat_pcm
->name
, "Digi96 ADAT");
1655 snd_pcm_set_ops(rme96
->adat_pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_rme96_playback_adat_ops
);
1656 snd_pcm_set_ops(rme96
->adat_pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_rme96_capture_adat_ops
);
1658 rme96
->adat_pcm
->info_flags
= 0;
1661 rme96
->playback_periodsize
= 0;
1662 rme96
->capture_periodsize
= 0;
1664 /* make sure playback/capture is stopped, if by some reason active */
1665 snd_rme96_trigger(rme96
, RME96_STOP_BOTH
);
1667 /* set default values in registers */
1669 RME96_WCR_FREQ_1
| /* set 44.1 kHz playback */
1670 RME96_WCR_SEL
| /* normal playback */
1671 RME96_WCR_MASTER
| /* set to master clock mode */
1672 RME96_WCR_INP_0
; /* set coaxial input */
1674 rme96
->areg
= RME96_AR_FREQPAD_1
; /* set 44.1 kHz analog capture */
1676 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1677 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1680 writel(rme96
->areg
| RME96_AR_PD2
,
1681 rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1682 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1684 /* reset and enable the DAC (order is important). */
1685 snd_rme96_reset_dac(rme96
);
1686 rme96
->areg
|= RME96_AR_DAC_EN
;
1687 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1689 /* reset playback and record buffer pointers */
1690 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1691 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1694 rme96
->vol
[0] = rme96
->vol
[1] = 0;
1695 if (RME96_HAS_ANALOG_OUT(rme96
)) {
1696 snd_rme96_apply_dac_volume(rme96
);
1699 /* init switch interface */
1700 err
= snd_rme96_create_switches(rme96
->card
, rme96
);
1704 /* init proc interface */
1705 snd_rme96_proc_init(rme96
);
1715 snd_rme96_proc_read(struct snd_info_entry
*entry
, struct snd_info_buffer
*buffer
)
1718 struct rme96
*rme96
= entry
->private_data
;
1720 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1722 snd_iprintf(buffer
, rme96
->card
->longname
);
1723 snd_iprintf(buffer
, " (index #%d)\n", rme96
->card
->number
+ 1);
1725 snd_iprintf(buffer
, "\nGeneral settings\n");
1726 if (rme96
->wcreg
& RME96_WCR_IDIS
) {
1727 snd_iprintf(buffer
, " period size: N/A (interrupts "
1729 } else if (rme96
->wcreg
& RME96_WCR_ISEL
) {
1730 snd_iprintf(buffer
, " period size: 2048 bytes\n");
1732 snd_iprintf(buffer
, " period size: 8192 bytes\n");
1734 snd_iprintf(buffer
, "\nInput settings\n");
1735 switch (snd_rme96_getinputtype(rme96
)) {
1736 case RME96_INPUT_OPTICAL
:
1737 snd_iprintf(buffer
, " input: optical");
1739 case RME96_INPUT_COAXIAL
:
1740 snd_iprintf(buffer
, " input: coaxial");
1742 case RME96_INPUT_INTERNAL
:
1743 snd_iprintf(buffer
, " input: internal");
1745 case RME96_INPUT_XLR
:
1746 snd_iprintf(buffer
, " input: XLR");
1748 case RME96_INPUT_ANALOG
:
1749 snd_iprintf(buffer
, " input: analog");
1752 if (snd_rme96_capture_getrate(rme96
, &n
) < 0) {
1753 snd_iprintf(buffer
, "\n sample rate: no valid signal\n");
1756 snd_iprintf(buffer
, " (8 channels)\n");
1758 snd_iprintf(buffer
, " (2 channels)\n");
1760 snd_iprintf(buffer
, " sample rate: %d Hz\n",
1761 snd_rme96_capture_getrate(rme96
, &n
));
1763 if (rme96
->wcreg
& RME96_WCR_MODE24_2
) {
1764 snd_iprintf(buffer
, " sample format: 24 bit\n");
1766 snd_iprintf(buffer
, " sample format: 16 bit\n");
1769 snd_iprintf(buffer
, "\nOutput settings\n");
1770 if (rme96
->wcreg
& RME96_WCR_SEL
) {
1771 snd_iprintf(buffer
, " output signal: normal playback\n");
1773 snd_iprintf(buffer
, " output signal: same as input\n");
1775 snd_iprintf(buffer
, " sample rate: %d Hz\n",
1776 snd_rme96_playback_getrate(rme96
));
1777 if (rme96
->wcreg
& RME96_WCR_MODE24
) {
1778 snd_iprintf(buffer
, " sample format: 24 bit\n");
1780 snd_iprintf(buffer
, " sample format: 16 bit\n");
1782 if (rme96
->areg
& RME96_AR_WSEL
) {
1783 snd_iprintf(buffer
, " sample clock source: word clock\n");
1784 } else if (rme96
->wcreg
& RME96_WCR_MASTER
) {
1785 snd_iprintf(buffer
, " sample clock source: internal\n");
1786 } else if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1787 snd_iprintf(buffer
, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1788 } else if (snd_rme96_capture_getrate(rme96
, &n
) < 0) {
1789 snd_iprintf(buffer
, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1791 snd_iprintf(buffer
, " sample clock source: autosync\n");
1793 if (rme96
->wcreg
& RME96_WCR_PRO
) {
1794 snd_iprintf(buffer
, " format: AES/EBU (professional)\n");
1796 snd_iprintf(buffer
, " format: IEC958 (consumer)\n");
1798 if (rme96
->wcreg
& RME96_WCR_EMP
) {
1799 snd_iprintf(buffer
, " emphasis: on\n");
1801 snd_iprintf(buffer
, " emphasis: off\n");
1803 if (rme96
->wcreg
& RME96_WCR_DOLBY
) {
1804 snd_iprintf(buffer
, " non-audio (dolby): on\n");
1806 snd_iprintf(buffer
, " non-audio (dolby): off\n");
1808 if (RME96_HAS_ANALOG_IN(rme96
)) {
1809 snd_iprintf(buffer
, "\nAnalog output settings\n");
1810 switch (snd_rme96_getmontracks(rme96
)) {
1811 case RME96_MONITOR_TRACKS_1_2
:
1812 snd_iprintf(buffer
, " monitored ADAT tracks: 1+2\n");
1814 case RME96_MONITOR_TRACKS_3_4
:
1815 snd_iprintf(buffer
, " monitored ADAT tracks: 3+4\n");
1817 case RME96_MONITOR_TRACKS_5_6
:
1818 snd_iprintf(buffer
, " monitored ADAT tracks: 5+6\n");
1820 case RME96_MONITOR_TRACKS_7_8
:
1821 snd_iprintf(buffer
, " monitored ADAT tracks: 7+8\n");
1824 switch (snd_rme96_getattenuation(rme96
)) {
1825 case RME96_ATTENUATION_0
:
1826 snd_iprintf(buffer
, " attenuation: 0 dB\n");
1828 case RME96_ATTENUATION_6
:
1829 snd_iprintf(buffer
, " attenuation: -6 dB\n");
1831 case RME96_ATTENUATION_12
:
1832 snd_iprintf(buffer
, " attenuation: -12 dB\n");
1834 case RME96_ATTENUATION_18
:
1835 snd_iprintf(buffer
, " attenuation: -18 dB\n");
1838 snd_iprintf(buffer
, " volume left: %u\n", rme96
->vol
[0]);
1839 snd_iprintf(buffer
, " volume right: %u\n", rme96
->vol
[1]);
1843 static void snd_rme96_proc_init(struct rme96
*rme96
)
1845 snd_card_ro_proc_new(rme96
->card
, "rme96", rme96
, snd_rme96_proc_read
);
1852 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1855 snd_rme96_get_loopback_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1857 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1859 spin_lock_irq(&rme96
->lock
);
1860 ucontrol
->value
.integer
.value
[0] = rme96
->wcreg
& RME96_WCR_SEL
? 0 : 1;
1861 spin_unlock_irq(&rme96
->lock
);
1865 snd_rme96_put_loopback_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1867 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1871 val
= ucontrol
->value
.integer
.value
[0] ? 0 : RME96_WCR_SEL
;
1872 spin_lock_irq(&rme96
->lock
);
1873 val
= (rme96
->wcreg
& ~RME96_WCR_SEL
) | val
;
1874 change
= val
!= rme96
->wcreg
;
1876 writel(val
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1877 spin_unlock_irq(&rme96
->lock
);
1882 snd_rme96_info_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1884 static const char * const _texts
[5] = {
1885 "Optical", "Coaxial", "Internal", "XLR", "Analog"
1887 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1888 const char *texts
[5] = {
1889 _texts
[0], _texts
[1], _texts
[2], _texts
[3], _texts
[4]
1893 switch (rme96
->pci
->device
) {
1894 case PCI_DEVICE_ID_RME_DIGI96
:
1895 case PCI_DEVICE_ID_RME_DIGI96_8
:
1898 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1901 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1902 if (rme96
->rev
> 4) {
1905 texts
[3] = _texts
[4]; /* Analog instead of XLR */
1915 return snd_ctl_enum_info(uinfo
, 1, num_items
, texts
);
1918 snd_rme96_get_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1920 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1921 unsigned int items
= 3;
1923 spin_lock_irq(&rme96
->lock
);
1924 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getinputtype(rme96
);
1926 switch (rme96
->pci
->device
) {
1927 case PCI_DEVICE_ID_RME_DIGI96
:
1928 case PCI_DEVICE_ID_RME_DIGI96_8
:
1931 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1934 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1935 if (rme96
->rev
> 4) {
1936 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1937 if (ucontrol
->value
.enumerated
.item
[0] == RME96_INPUT_ANALOG
) {
1938 ucontrol
->value
.enumerated
.item
[0] = RME96_INPUT_XLR
;
1949 if (ucontrol
->value
.enumerated
.item
[0] >= items
) {
1950 ucontrol
->value
.enumerated
.item
[0] = items
- 1;
1953 spin_unlock_irq(&rme96
->lock
);
1957 snd_rme96_put_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1959 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1961 int change
, items
= 3;
1963 switch (rme96
->pci
->device
) {
1964 case PCI_DEVICE_ID_RME_DIGI96
:
1965 case PCI_DEVICE_ID_RME_DIGI96_8
:
1968 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1971 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1972 if (rme96
->rev
> 4) {
1982 val
= ucontrol
->value
.enumerated
.item
[0] % items
;
1984 /* special case for PST */
1985 if (rme96
->pci
->device
== PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&& rme96
->rev
> 4) {
1986 if (val
== RME96_INPUT_XLR
) {
1987 val
= RME96_INPUT_ANALOG
;
1991 spin_lock_irq(&rme96
->lock
);
1992 change
= (int)val
!= snd_rme96_getinputtype(rme96
);
1993 snd_rme96_setinputtype(rme96
, val
);
1994 spin_unlock_irq(&rme96
->lock
);
1999 snd_rme96_info_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2001 static const char * const texts
[3] = { "AutoSync", "Internal", "Word" };
2003 return snd_ctl_enum_info(uinfo
, 1, 3, texts
);
2006 snd_rme96_get_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2008 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2010 spin_lock_irq(&rme96
->lock
);
2011 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getclockmode(rme96
);
2012 spin_unlock_irq(&rme96
->lock
);
2016 snd_rme96_put_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2018 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2022 val
= ucontrol
->value
.enumerated
.item
[0] % 3;
2023 spin_lock_irq(&rme96
->lock
);
2024 change
= (int)val
!= snd_rme96_getclockmode(rme96
);
2025 snd_rme96_setclockmode(rme96
, val
);
2026 spin_unlock_irq(&rme96
->lock
);
2031 snd_rme96_info_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2033 static const char * const texts
[4] = {
2034 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2037 return snd_ctl_enum_info(uinfo
, 1, 4, texts
);
2040 snd_rme96_get_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2042 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2044 spin_lock_irq(&rme96
->lock
);
2045 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getattenuation(rme96
);
2046 spin_unlock_irq(&rme96
->lock
);
2050 snd_rme96_put_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2052 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2056 val
= ucontrol
->value
.enumerated
.item
[0] % 4;
2057 spin_lock_irq(&rme96
->lock
);
2059 change
= (int)val
!= snd_rme96_getattenuation(rme96
);
2060 snd_rme96_setattenuation(rme96
, val
);
2061 spin_unlock_irq(&rme96
->lock
);
2066 snd_rme96_info_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2068 static const char * const texts
[4] = { "1+2", "3+4", "5+6", "7+8" };
2070 return snd_ctl_enum_info(uinfo
, 1, 4, texts
);
2073 snd_rme96_get_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2075 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2077 spin_lock_irq(&rme96
->lock
);
2078 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getmontracks(rme96
);
2079 spin_unlock_irq(&rme96
->lock
);
2083 snd_rme96_put_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2085 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2089 val
= ucontrol
->value
.enumerated
.item
[0] % 4;
2090 spin_lock_irq(&rme96
->lock
);
2091 change
= (int)val
!= snd_rme96_getmontracks(rme96
);
2092 snd_rme96_setmontracks(rme96
, val
);
2093 spin_unlock_irq(&rme96
->lock
);
2097 static u32
snd_rme96_convert_from_aes(struct snd_aes_iec958
*aes
)
2100 val
|= (aes
->status
[0] & IEC958_AES0_PROFESSIONAL
) ? RME96_WCR_PRO
: 0;
2101 val
|= (aes
->status
[0] & IEC958_AES0_NONAUDIO
) ? RME96_WCR_DOLBY
: 0;
2102 if (val
& RME96_WCR_PRO
)
2103 val
|= (aes
->status
[0] & IEC958_AES0_PRO_EMPHASIS_5015
) ? RME96_WCR_EMP
: 0;
2105 val
|= (aes
->status
[0] & IEC958_AES0_CON_EMPHASIS_5015
) ? RME96_WCR_EMP
: 0;
2109 static void snd_rme96_convert_to_aes(struct snd_aes_iec958
*aes
, u32 val
)
2111 aes
->status
[0] = ((val
& RME96_WCR_PRO
) ? IEC958_AES0_PROFESSIONAL
: 0) |
2112 ((val
& RME96_WCR_DOLBY
) ? IEC958_AES0_NONAUDIO
: 0);
2113 if (val
& RME96_WCR_PRO
)
2114 aes
->status
[0] |= (val
& RME96_WCR_EMP
) ? IEC958_AES0_PRO_EMPHASIS_5015
: 0;
2116 aes
->status
[0] |= (val
& RME96_WCR_EMP
) ? IEC958_AES0_CON_EMPHASIS_5015
: 0;
2119 static int snd_rme96_control_spdif_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2121 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2126 static int snd_rme96_control_spdif_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2128 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2130 snd_rme96_convert_to_aes(&ucontrol
->value
.iec958
, rme96
->wcreg_spdif
);
2134 static int snd_rme96_control_spdif_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2136 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2140 val
= snd_rme96_convert_from_aes(&ucontrol
->value
.iec958
);
2141 spin_lock_irq(&rme96
->lock
);
2142 change
= val
!= rme96
->wcreg_spdif
;
2143 rme96
->wcreg_spdif
= val
;
2144 spin_unlock_irq(&rme96
->lock
);
2148 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2150 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2155 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2157 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2159 snd_rme96_convert_to_aes(&ucontrol
->value
.iec958
, rme96
->wcreg_spdif_stream
);
2163 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2165 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2169 val
= snd_rme96_convert_from_aes(&ucontrol
->value
.iec958
);
2170 spin_lock_irq(&rme96
->lock
);
2171 change
= val
!= rme96
->wcreg_spdif_stream
;
2172 rme96
->wcreg_spdif_stream
= val
;
2173 rme96
->wcreg
&= ~(RME96_WCR_PRO
| RME96_WCR_DOLBY
| RME96_WCR_EMP
);
2174 rme96
->wcreg
|= val
;
2175 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
2176 spin_unlock_irq(&rme96
->lock
);
2180 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2182 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2187 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2189 ucontrol
->value
.iec958
.status
[0] = kcontrol
->private_value
;
2194 snd_rme96_dac_volume_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2196 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2198 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2200 uinfo
->value
.integer
.min
= 0;
2201 uinfo
->value
.integer
.max
= RME96_185X_MAX_OUT(rme96
);
2206 snd_rme96_dac_volume_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*u
)
2208 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2210 spin_lock_irq(&rme96
->lock
);
2211 u
->value
.integer
.value
[0] = rme96
->vol
[0];
2212 u
->value
.integer
.value
[1] = rme96
->vol
[1];
2213 spin_unlock_irq(&rme96
->lock
);
2219 snd_rme96_dac_volume_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*u
)
2221 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2223 unsigned int vol
, maxvol
;
2226 if (!RME96_HAS_ANALOG_OUT(rme96
))
2228 maxvol
= RME96_185X_MAX_OUT(rme96
);
2229 spin_lock_irq(&rme96
->lock
);
2230 vol
= u
->value
.integer
.value
[0];
2231 if (vol
!= rme96
->vol
[0] && vol
<= maxvol
) {
2232 rme96
->vol
[0] = vol
;
2235 vol
= u
->value
.integer
.value
[1];
2236 if (vol
!= rme96
->vol
[1] && vol
<= maxvol
) {
2237 rme96
->vol
[1] = vol
;
2241 snd_rme96_apply_dac_volume(rme96
);
2242 spin_unlock_irq(&rme96
->lock
);
2247 static const struct snd_kcontrol_new snd_rme96_controls
[] = {
2249 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2250 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2251 .info
= snd_rme96_control_spdif_info
,
2252 .get
= snd_rme96_control_spdif_get
,
2253 .put
= snd_rme96_control_spdif_put
2256 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
2257 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2258 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2259 .info
= snd_rme96_control_spdif_stream_info
,
2260 .get
= snd_rme96_control_spdif_stream_get
,
2261 .put
= snd_rme96_control_spdif_stream_put
2264 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2265 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2266 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
2267 .info
= snd_rme96_control_spdif_mask_info
,
2268 .get
= snd_rme96_control_spdif_mask_get
,
2269 .private_value
= IEC958_AES0_NONAUDIO
|
2270 IEC958_AES0_PROFESSIONAL
|
2271 IEC958_AES0_CON_EMPHASIS
2274 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2275 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2276 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PRO_MASK
),
2277 .info
= snd_rme96_control_spdif_mask_info
,
2278 .get
= snd_rme96_control_spdif_mask_get
,
2279 .private_value
= IEC958_AES0_NONAUDIO
|
2280 IEC958_AES0_PROFESSIONAL
|
2281 IEC958_AES0_PRO_EMPHASIS
2284 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2285 .name
= "Input Connector",
2286 .info
= snd_rme96_info_inputtype_control
,
2287 .get
= snd_rme96_get_inputtype_control
,
2288 .put
= snd_rme96_put_inputtype_control
2291 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2292 .name
= "Loopback Input",
2293 .info
= snd_rme96_info_loopback_control
,
2294 .get
= snd_rme96_get_loopback_control
,
2295 .put
= snd_rme96_put_loopback_control
2298 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2299 .name
= "Sample Clock Source",
2300 .info
= snd_rme96_info_clockmode_control
,
2301 .get
= snd_rme96_get_clockmode_control
,
2302 .put
= snd_rme96_put_clockmode_control
2305 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2306 .name
= "Monitor Tracks",
2307 .info
= snd_rme96_info_montracks_control
,
2308 .get
= snd_rme96_get_montracks_control
,
2309 .put
= snd_rme96_put_montracks_control
2312 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2313 .name
= "Attenuation",
2314 .info
= snd_rme96_info_attenuation_control
,
2315 .get
= snd_rme96_get_attenuation_control
,
2316 .put
= snd_rme96_put_attenuation_control
2319 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2320 .name
= "DAC Playback Volume",
2321 .info
= snd_rme96_dac_volume_info
,
2322 .get
= snd_rme96_dac_volume_get
,
2323 .put
= snd_rme96_dac_volume_put
2328 snd_rme96_create_switches(struct snd_card
*card
,
2329 struct rme96
*rme96
)
2332 struct snd_kcontrol
*kctl
;
2334 for (idx
= 0; idx
< 7; idx
++) {
2335 kctl
= snd_ctl_new1(&snd_rme96_controls
[idx
], rme96
);
2336 err
= snd_ctl_add(card
, kctl
);
2339 if (idx
== 1) /* IEC958 (S/PDIF) Stream */
2340 rme96
->spdif_ctl
= kctl
;
2343 if (RME96_HAS_ANALOG_OUT(rme96
)) {
2344 for (idx
= 7; idx
< 10; idx
++) {
2345 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_rme96_controls
[idx
], rme96
));
2355 * Card initialisation
2358 #ifdef CONFIG_PM_SLEEP
2360 static int rme96_suspend(struct device
*dev
)
2362 struct snd_card
*card
= dev_get_drvdata(dev
);
2363 struct rme96
*rme96
= card
->private_data
;
2365 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
2367 /* save capture & playback pointers */
2368 rme96
->playback_pointer
= readl(rme96
->iobase
+ RME96_IO_GET_PLAY_POS
)
2369 & RME96_RCR_AUDIO_ADDR_MASK
;
2370 rme96
->capture_pointer
= readl(rme96
->iobase
+ RME96_IO_GET_REC_POS
)
2371 & RME96_RCR_AUDIO_ADDR_MASK
;
2373 /* save playback and capture buffers */
2374 memcpy_fromio(rme96
->playback_suspend_buffer
,
2375 rme96
->iobase
+ RME96_IO_PLAY_BUFFER
, RME96_BUFFER_SIZE
);
2376 memcpy_fromio(rme96
->capture_suspend_buffer
,
2377 rme96
->iobase
+ RME96_IO_REC_BUFFER
, RME96_BUFFER_SIZE
);
2379 /* disable the DAC */
2380 rme96
->areg
&= ~RME96_AR_DAC_EN
;
2381 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
2385 static int rme96_resume(struct device
*dev
)
2387 struct snd_card
*card
= dev_get_drvdata(dev
);
2388 struct rme96
*rme96
= card
->private_data
;
2390 /* reset playback and record buffer pointers */
2391 writel(0, rme96
->iobase
+ RME96_IO_SET_PLAY_POS
2392 + rme96
->playback_pointer
);
2393 writel(0, rme96
->iobase
+ RME96_IO_SET_REC_POS
2394 + rme96
->capture_pointer
);
2396 /* restore playback and capture buffers */
2397 memcpy_toio(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
,
2398 rme96
->playback_suspend_buffer
, RME96_BUFFER_SIZE
);
2399 memcpy_toio(rme96
->iobase
+ RME96_IO_REC_BUFFER
,
2400 rme96
->capture_suspend_buffer
, RME96_BUFFER_SIZE
);
2403 writel(rme96
->areg
| RME96_AR_PD2
,
2404 rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
2405 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
2407 /* reset and enable DAC, restore analog volume */
2408 snd_rme96_reset_dac(rme96
);
2409 rme96
->areg
|= RME96_AR_DAC_EN
;
2410 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
2411 if (RME96_HAS_ANALOG_OUT(rme96
)) {
2412 usleep_range(3000, 10000);
2413 snd_rme96_apply_dac_volume(rme96
);
2416 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2421 static SIMPLE_DEV_PM_OPS(rme96_pm
, rme96_suspend
, rme96_resume
);
2422 #define RME96_PM_OPS &rme96_pm
2424 #define RME96_PM_OPS NULL
2425 #endif /* CONFIG_PM_SLEEP */
2427 static void snd_rme96_card_free(struct snd_card
*card
)
2429 snd_rme96_free(card
->private_data
);
2433 snd_rme96_probe(struct pci_dev
*pci
,
2434 const struct pci_device_id
*pci_id
)
2437 struct rme96
*rme96
;
2438 struct snd_card
*card
;
2442 if (dev
>= SNDRV_CARDS
) {
2449 err
= snd_devm_card_new(&pci
->dev
, index
[dev
], id
[dev
], THIS_MODULE
,
2450 sizeof(*rme96
), &card
);
2453 card
->private_free
= snd_rme96_card_free
;
2454 rme96
= card
->private_data
;
2457 err
= snd_rme96_create(rme96
);
2461 #ifdef CONFIG_PM_SLEEP
2462 rme96
->playback_suspend_buffer
= vmalloc(RME96_BUFFER_SIZE
);
2463 if (!rme96
->playback_suspend_buffer
)
2465 rme96
->capture_suspend_buffer
= vmalloc(RME96_BUFFER_SIZE
);
2466 if (!rme96
->capture_suspend_buffer
)
2470 strcpy(card
->driver
, "Digi96");
2471 switch (rme96
->pci
->device
) {
2472 case PCI_DEVICE_ID_RME_DIGI96
:
2473 strcpy(card
->shortname
, "RME Digi96");
2475 case PCI_DEVICE_ID_RME_DIGI96_8
:
2476 strcpy(card
->shortname
, "RME Digi96/8");
2478 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
2479 strcpy(card
->shortname
, "RME Digi96/8 PRO");
2481 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
2482 pci_read_config_byte(rme96
->pci
, 8, &val
);
2484 strcpy(card
->shortname
, "RME Digi96/8 PAD");
2486 strcpy(card
->shortname
, "RME Digi96/8 PST");
2490 sprintf(card
->longname
, "%s at 0x%lx, irq %d", card
->shortname
,
2491 rme96
->port
, rme96
->irq
);
2492 err
= snd_card_register(card
);
2496 pci_set_drvdata(pci
, card
);
2501 static struct pci_driver rme96_driver
= {
2502 .name
= KBUILD_MODNAME
,
2503 .id_table
= snd_rme96_ids
,
2504 .probe
= snd_rme96_probe
,
2510 module_pci_driver(rme96_driver
);