1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
5 * Copyright (c) 2002 Paul Davis
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
19 #include <linux/nospec.h>
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
34 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
35 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
36 static bool enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable this card */
38 module_param_array(index
, int, NULL
, 0444);
39 MODULE_PARM_DESC(index
, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id
, charp
, NULL
, 0444);
41 MODULE_PARM_DESC(id
, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable
, bool, NULL
, 0444);
43 MODULE_PARM_DESC(enable
, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_FIRMWARE("rpm_firmware.bin");
48 MODULE_FIRMWARE("multiface_firmware.bin");
49 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
50 MODULE_FIRMWARE("digiface_firmware.bin");
51 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
53 #define HDSP_MAX_CHANNELS 26
54 #define HDSP_MAX_DS_CHANNELS 14
55 #define HDSP_MAX_QS_CHANNELS 8
56 #define DIGIFACE_SS_CHANNELS 26
57 #define DIGIFACE_DS_CHANNELS 14
58 #define MULTIFACE_SS_CHANNELS 18
59 #define MULTIFACE_DS_CHANNELS 14
60 #define H9652_SS_CHANNELS 26
61 #define H9652_DS_CHANNELS 14
62 /* This does not include possible Analog Extension Boards
63 AEBs are detected at card initialization
65 #define H9632_SS_CHANNELS 12
66 #define H9632_DS_CHANNELS 8
67 #define H9632_QS_CHANNELS 4
68 #define RPM_CHANNELS 6
70 /* Write registers. These are defined as byte-offsets from the iobase value.
72 #define HDSP_resetPointer 0
73 #define HDSP_freqReg 0
74 #define HDSP_outputBufferAddress 32
75 #define HDSP_inputBufferAddress 36
76 #define HDSP_controlRegister 64
77 #define HDSP_interruptConfirmation 96
78 #define HDSP_outputEnable 128
79 #define HDSP_control2Reg 256
80 #define HDSP_midiDataOut0 352
81 #define HDSP_midiDataOut1 356
82 #define HDSP_fifoData 368
83 #define HDSP_inputEnable 384
85 /* Read registers. These are defined as byte-offsets from the iobase value
88 #define HDSP_statusRegister 0
89 #define HDSP_timecode 128
90 #define HDSP_status2Register 192
91 #define HDSP_midiDataIn0 360
92 #define HDSP_midiDataIn1 364
93 #define HDSP_midiStatusOut0 384
94 #define HDSP_midiStatusOut1 388
95 #define HDSP_midiStatusIn0 392
96 #define HDSP_midiStatusIn1 396
97 #define HDSP_fifoStatus 400
99 /* the meters are regular i/o-mapped registers, but offset
100 considerably from the rest. the peak registers are reset
101 when read; the least-significant 4 bits are full-scale counters;
102 the actual peak value is in the most-significant 24 bits.
105 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
106 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
107 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
108 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
109 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
112 /* This is for H9652 cards
113 Peak values are read downward from the base
114 Rms values are read upward
115 There are rms values for the outputs too
116 26*3 values are read in ss mode
117 14*3 in ds mode, with no gap between values
119 #define HDSP_9652_peakBase 7164
120 #define HDSP_9652_rmsBase 4096
122 /* c.f. the hdsp_9632_meters_t struct */
123 #define HDSP_9632_metersBase 4096
125 #define HDSP_IO_EXTENT 7168
127 /* control2 register bits */
129 #define HDSP_TMS 0x01
130 #define HDSP_TCK 0x02
131 #define HDSP_TDI 0x04
132 #define HDSP_JTAG 0x08
133 #define HDSP_PWDN 0x10
134 #define HDSP_PROGRAM 0x020
135 #define HDSP_CONFIG_MODE_0 0x040
136 #define HDSP_CONFIG_MODE_1 0x080
137 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
138 #define HDSP_BIGENDIAN_MODE 0x200
139 #define HDSP_RD_MULTIPLE 0x400
140 #define HDSP_9652_ENABLE_MIXER 0x800
141 #define HDSP_S200 0x800
142 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
143 #define HDSP_CYCLIC_MODE 0x1000
144 #define HDSP_TDO 0x10000000
146 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
147 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
149 /* Control Register bits */
151 #define HDSP_Start (1<<0) /* start engine */
152 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
153 #define HDSP_Latency1 (1<<2) /* [ see above ] */
154 #define HDSP_Latency2 (1<<3) /* [ see above ] */
155 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
156 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
157 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
158 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
159 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
160 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
161 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
162 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
163 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
164 #define HDSP_SyncRef2 (1<<13)
165 #define HDSP_SPDIFInputSelect0 (1<<14)
166 #define HDSP_SPDIFInputSelect1 (1<<15)
167 #define HDSP_SyncRef0 (1<<16)
168 #define HDSP_SyncRef1 (1<<17)
169 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
170 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
171 #define HDSP_Midi0InterruptEnable (1<<22)
172 #define HDSP_Midi1InterruptEnable (1<<23)
173 #define HDSP_LineOut (1<<24)
174 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
175 #define HDSP_ADGain1 (1<<26)
176 #define HDSP_DAGain0 (1<<27)
177 #define HDSP_DAGain1 (1<<28)
178 #define HDSP_PhoneGain0 (1<<29)
179 #define HDSP_PhoneGain1 (1<<30)
180 #define HDSP_QuadSpeed (1<<31)
182 /* RPM uses some of the registers for special purposes */
183 #define HDSP_RPM_Inp12 0x04A00
184 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
185 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
186 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
187 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
188 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
190 #define HDSP_RPM_Inp34 0x32000
191 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
192 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
193 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
194 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
195 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
197 #define HDSP_RPM_Bypass 0x01000
199 #define HDSP_RPM_Disconnect 0x00001
201 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
202 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
203 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
204 #define HDSP_ADGainLowGain 0
206 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
207 #define HDSP_DAGainHighGain HDSP_DAGainMask
208 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
209 #define HDSP_DAGainMinus10dBV 0
211 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
212 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
213 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
214 #define HDSP_PhoneGainMinus12dB 0
216 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
217 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
219 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
220 #define HDSP_SPDIFInputADAT1 0
221 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
222 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
225 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
226 #define HDSP_SyncRef_ADAT1 0
227 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
228 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
229 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
230 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
231 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
233 /* Sample Clock Sources */
235 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
236 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
237 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
238 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
239 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
240 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
241 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
242 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
243 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
244 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
246 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
248 #define HDSP_SYNC_FROM_WORD 0
249 #define HDSP_SYNC_FROM_SPDIF 1
250 #define HDSP_SYNC_FROM_ADAT1 2
251 #define HDSP_SYNC_FROM_ADAT_SYNC 3
252 #define HDSP_SYNC_FROM_ADAT2 4
253 #define HDSP_SYNC_FROM_ADAT3 5
255 /* SyncCheck status */
257 #define HDSP_SYNC_CHECK_NO_LOCK 0
258 #define HDSP_SYNC_CHECK_LOCK 1
259 #define HDSP_SYNC_CHECK_SYNC 2
261 /* AutoSync references - used by "autosync_ref" control switch */
263 #define HDSP_AUTOSYNC_FROM_WORD 0
264 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
265 #define HDSP_AUTOSYNC_FROM_SPDIF 2
266 #define HDSP_AUTOSYNC_FROM_NONE 3
267 #define HDSP_AUTOSYNC_FROM_ADAT1 4
268 #define HDSP_AUTOSYNC_FROM_ADAT2 5
269 #define HDSP_AUTOSYNC_FROM_ADAT3 6
271 /* Possible sources of S/PDIF input */
273 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
274 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
275 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
276 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
278 #define HDSP_Frequency32KHz HDSP_Frequency0
279 #define HDSP_Frequency44_1KHz HDSP_Frequency1
280 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
281 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
282 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
283 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
284 /* For H9632 cards */
285 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
286 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
287 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
288 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
289 return 104857600000000 / rate; // 100 MHz
290 return 110100480000000 / rate; // 105 MHz
292 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
294 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
295 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
297 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
298 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
300 /* Status Register bits */
302 #define HDSP_audioIRQPending (1<<0)
303 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
304 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
305 #define HDSP_Lock1 (1<<2)
306 #define HDSP_Lock0 (1<<3)
307 #define HDSP_SPDIFSync (1<<4)
308 #define HDSP_TimecodeLock (1<<5)
309 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
310 #define HDSP_Sync2 (1<<16)
311 #define HDSP_Sync1 (1<<17)
312 #define HDSP_Sync0 (1<<18)
313 #define HDSP_DoubleSpeedStatus (1<<19)
314 #define HDSP_ConfigError (1<<20)
315 #define HDSP_DllError (1<<21)
316 #define HDSP_spdifFrequency0 (1<<22)
317 #define HDSP_spdifFrequency1 (1<<23)
318 #define HDSP_spdifFrequency2 (1<<24)
319 #define HDSP_SPDIFErrorFlag (1<<25)
320 #define HDSP_BufferID (1<<26)
321 #define HDSP_TimecodeSync (1<<27)
322 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
323 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
324 #define HDSP_midi0IRQPending (1<<30)
325 #define HDSP_midi1IRQPending (1<<31)
327 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
328 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
329 HDSP_spdifFrequency1|\
330 HDSP_spdifFrequency2|\
331 HDSP_spdifFrequency3)
333 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
334 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
335 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
337 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
338 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
339 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
341 /* This is for H9632 cards */
342 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
343 HDSP_spdifFrequency1|\
344 HDSP_spdifFrequency2)
345 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
346 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
348 /* Status2 Register bits */
350 #define HDSP_version0 (1<<0)
351 #define HDSP_version1 (1<<1)
352 #define HDSP_version2 (1<<2)
353 #define HDSP_wc_lock (1<<3)
354 #define HDSP_wc_sync (1<<4)
355 #define HDSP_inp_freq0 (1<<5)
356 #define HDSP_inp_freq1 (1<<6)
357 #define HDSP_inp_freq2 (1<<7)
358 #define HDSP_SelSyncRef0 (1<<8)
359 #define HDSP_SelSyncRef1 (1<<9)
360 #define HDSP_SelSyncRef2 (1<<10)
362 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
364 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
365 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
366 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
367 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
368 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
369 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
370 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
371 /* FIXME : more values for 9632 cards ? */
373 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
374 #define HDSP_SelSyncRef_ADAT1 0
375 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
376 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
377 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
378 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
379 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
381 /* Card state flags */
383 #define HDSP_InitializationComplete (1<<0)
384 #define HDSP_FirmwareLoaded (1<<1)
385 #define HDSP_FirmwareCached (1<<2)
387 /* FIFO wait times, defined in terms of 1/10ths of msecs */
389 #define HDSP_LONG_WAIT 5000
390 #define HDSP_SHORT_WAIT 30
392 #define UNITY_GAIN 32768
393 #define MINUS_INFINITY_GAIN 0
395 /* the size of a substream (1 mono data stream) */
397 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
398 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
400 /* the size of the area we need to allocate for DMA transfers. the
401 size is the same regardless of the number of channels - the
402 Multiface still uses the same memory area.
404 Note that we allocate 1 more channel than is apparently needed
405 because the h/w seems to write 1 byte beyond the end of the last
409 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
410 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
412 #define HDSP_FIRMWARE_SIZE (24413 * 4)
414 struct hdsp_9632_meters
{
416 u32 playback_peak
[16];
420 u32 input_rms_low
[16];
421 u32 playback_rms_low
[16];
422 u32 output_rms_low
[16];
424 u32 input_rms_high
[16];
425 u32 playback_rms_high
[16];
426 u32 output_rms_high
[16];
427 u32 xxx_rms_high
[16];
433 struct snd_rawmidi
*rmidi
;
434 struct snd_rawmidi_substream
*input
;
435 struct snd_rawmidi_substream
*output
;
436 char istimer
; /* timer in use */
437 struct timer_list timer
;
444 struct snd_pcm_substream
*capture_substream
;
445 struct snd_pcm_substream
*playback_substream
;
446 struct hdsp_midi midi
[2];
447 struct work_struct midi_work
;
450 u32 control_register
; /* cached value */
451 u32 control2_register
; /* cached value */
453 u32 creg_spdif_stream
;
454 int clock_source_locked
;
455 char *card_name
; /* digiface/multiface/rpm */
456 enum HDSP_IO_Type io_type
; /* ditto, but for code use */
457 unsigned short firmware_rev
;
458 unsigned short state
; /* stores state bits */
459 const struct firmware
*firmware
;
461 size_t period_bytes
; /* guess what this is */
462 unsigned char max_channels
;
463 unsigned char qs_in_channels
; /* quad speed mode for H9632 */
464 unsigned char ds_in_channels
;
465 unsigned char ss_in_channels
; /* different for multiface/digiface */
466 unsigned char qs_out_channels
;
467 unsigned char ds_out_channels
;
468 unsigned char ss_out_channels
;
469 u32 io_loopback
; /* output loopback channel states*/
471 struct snd_dma_buffer capture_dma_buf
;
472 struct snd_dma_buffer playback_dma_buf
;
473 unsigned char *capture_buffer
; /* suitably aligned address */
474 unsigned char *playback_buffer
; /* suitably aligned address */
479 int system_sample_rate
;
480 const char *channel_map
;
484 void __iomem
*iobase
;
485 struct snd_card
*card
;
487 struct snd_hwdep
*hwdep
;
489 struct snd_kcontrol
*spdif_ctl
;
490 unsigned short mixer_matrix
[HDSP_MATRIX_MIXER_SIZE
];
491 unsigned int dds_value
; /* last value written to freq register */
494 /* These tables map the ALSA channels 1..N to the channels that we
495 need to use in order to find the relevant channel buffer. RME
496 refer to this kind of mapping as between "the ADAT channel and
497 the DMA channel." We index it using the logical audio channel,
498 and the value is the DMA channel (i.e. channel buffer number)
499 where the data for that channel can be read/written from/to.
502 static const char channel_map_df_ss
[HDSP_MAX_CHANNELS
] = {
503 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
504 18, 19, 20, 21, 22, 23, 24, 25
507 static const char channel_map_mf_ss
[HDSP_MAX_CHANNELS
] = { /* Multiface */
509 0, 1, 2, 3, 4, 5, 6, 7,
511 16, 17, 18, 19, 20, 21, 22, 23,
514 -1, -1, -1, -1, -1, -1, -1, -1
517 static const char channel_map_ds
[HDSP_MAX_CHANNELS
] = {
518 /* ADAT channels are remapped */
519 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
520 /* channels 12 and 13 are S/PDIF */
522 /* others don't exist */
523 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
526 static const char channel_map_H9632_ss
[HDSP_MAX_CHANNELS
] = {
528 0, 1, 2, 3, 4, 5, 6, 7,
533 /* AO4S-192 and AI4S-192 extension boards */
535 /* others don't exist */
536 -1, -1, -1, -1, -1, -1, -1, -1,
540 static const char channel_map_H9632_ds
[HDSP_MAX_CHANNELS
] = {
547 /* AO4S-192 and AI4S-192 extension boards */
549 /* others don't exist */
550 -1, -1, -1, -1, -1, -1, -1, -1,
551 -1, -1, -1, -1, -1, -1
554 static const char channel_map_H9632_qs
[HDSP_MAX_CHANNELS
] = {
555 /* ADAT is disabled in this mode */
560 /* AO4S-192 and AI4S-192 extension boards */
562 /* others don't exist */
563 -1, -1, -1, -1, -1, -1, -1, -1,
564 -1, -1, -1, -1, -1, -1, -1, -1,
568 static int snd_hammerfall_get_buffer(struct pci_dev
*pci
, struct snd_dma_buffer
*dmab
, size_t size
)
570 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, &pci
->dev
, size
, dmab
);
573 static void snd_hammerfall_free_buffer(struct snd_dma_buffer
*dmab
, struct pci_dev
*pci
)
576 snd_dma_free_pages(dmab
);
580 static const struct pci_device_id snd_hdsp_ids
[] = {
582 .vendor
= PCI_VENDOR_ID_XILINX
,
583 .device
= PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
,
584 .subvendor
= PCI_ANY_ID
,
585 .subdevice
= PCI_ANY_ID
,
586 }, /* RME Hammerfall-DSP */
590 MODULE_DEVICE_TABLE(pci
, snd_hdsp_ids
);
593 static int snd_hdsp_create_alsa_devices(struct snd_card
*card
, struct hdsp
*hdsp
);
594 static int snd_hdsp_create_pcm(struct snd_card
*card
, struct hdsp
*hdsp
);
595 static int snd_hdsp_enable_io (struct hdsp
*hdsp
);
596 static void snd_hdsp_initialize_midi_flush (struct hdsp
*hdsp
);
597 static void snd_hdsp_initialize_channels (struct hdsp
*hdsp
);
598 static int hdsp_fifo_wait(struct hdsp
*hdsp
, int count
, int timeout
);
599 static int hdsp_autosync_ref(struct hdsp
*hdsp
);
600 static int snd_hdsp_set_defaults(struct hdsp
*hdsp
);
601 static void snd_hdsp_9652_enable_mixer (struct hdsp
*hdsp
);
603 static int hdsp_playback_to_output_key (struct hdsp
*hdsp
, int in
, int out
)
605 switch (hdsp
->io_type
) {
610 if (hdsp
->firmware_rev
== 0xa)
611 return (64 * out
) + (32 + (in
));
613 return (52 * out
) + (26 + (in
));
615 return (32 * out
) + (16 + (in
));
617 return (52 * out
) + (26 + (in
));
621 static int hdsp_input_to_output_key (struct hdsp
*hdsp
, int in
, int out
)
623 switch (hdsp
->io_type
) {
628 if (hdsp
->firmware_rev
== 0xa)
629 return (64 * out
) + in
;
631 return (52 * out
) + in
;
633 return (32 * out
) + in
;
635 return (52 * out
) + in
;
639 static void hdsp_write(struct hdsp
*hdsp
, int reg
, int val
)
641 writel(val
, hdsp
->iobase
+ reg
);
644 static unsigned int hdsp_read(struct hdsp
*hdsp
, int reg
)
646 return readl (hdsp
->iobase
+ reg
);
649 static int hdsp_check_for_iobox (struct hdsp
*hdsp
)
653 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
) return 0;
654 for (i
= 0; i
< 500; i
++) {
655 if (0 == (hdsp_read(hdsp
, HDSP_statusRegister
) &
658 dev_dbg(hdsp
->card
->dev
,
659 "IO box found after %d ms\n",
666 dev_err(hdsp
->card
->dev
, "no IO box connected!\n");
667 hdsp
->state
&= ~HDSP_FirmwareLoaded
;
671 static int hdsp_wait_for_iobox(struct hdsp
*hdsp
, unsigned int loops
,
676 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
)
679 for (i
= 0; i
!= loops
; ++i
) {
680 if (hdsp_read(hdsp
, HDSP_statusRegister
) & HDSP_ConfigError
)
683 dev_dbg(hdsp
->card
->dev
, "iobox found after %ums!\n",
689 dev_info(hdsp
->card
->dev
, "no IO box connected!\n");
690 hdsp
->state
&= ~HDSP_FirmwareLoaded
;
694 static int snd_hdsp_load_firmware_from_cache(struct hdsp
*hdsp
) {
700 if (hdsp
->fw_uploaded
)
701 cache
= hdsp
->fw_uploaded
;
705 cache
= (u32
*)hdsp
->firmware
->data
;
710 if ((hdsp_read (hdsp
, HDSP_statusRegister
) & HDSP_DllError
) != 0) {
712 dev_info(hdsp
->card
->dev
, "loading firmware\n");
714 hdsp_write (hdsp
, HDSP_control2Reg
, HDSP_S_PROGRAM
);
715 hdsp_write (hdsp
, HDSP_fifoData
, 0);
717 if (hdsp_fifo_wait (hdsp
, 0, HDSP_LONG_WAIT
)) {
718 dev_info(hdsp
->card
->dev
,
719 "timeout waiting for download preparation\n");
720 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S200
);
724 hdsp_write (hdsp
, HDSP_control2Reg
, HDSP_S_LOAD
);
726 for (i
= 0; i
< HDSP_FIRMWARE_SIZE
/ 4; ++i
) {
727 hdsp_write(hdsp
, HDSP_fifoData
, cache
[i
]);
728 if (hdsp_fifo_wait (hdsp
, 127, HDSP_LONG_WAIT
)) {
729 dev_info(hdsp
->card
->dev
,
730 "timeout during firmware loading\n");
731 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S200
);
736 hdsp_fifo_wait(hdsp
, 3, HDSP_LONG_WAIT
);
737 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S200
);
740 #ifdef SNDRV_BIG_ENDIAN
741 hdsp
->control2_register
= HDSP_BIGENDIAN_MODE
;
743 hdsp
->control2_register
= 0;
745 hdsp_write (hdsp
, HDSP_control2Reg
, hdsp
->control2_register
);
746 dev_info(hdsp
->card
->dev
, "finished firmware loading\n");
749 if (hdsp
->state
& HDSP_InitializationComplete
) {
750 dev_info(hdsp
->card
->dev
,
751 "firmware loaded from cache, restoring defaults\n");
752 spin_lock_irqsave(&hdsp
->lock
, flags
);
753 snd_hdsp_set_defaults(hdsp
);
754 spin_unlock_irqrestore(&hdsp
->lock
, flags
);
757 hdsp
->state
|= HDSP_FirmwareLoaded
;
762 static int hdsp_get_iobox_version (struct hdsp
*hdsp
)
764 if ((hdsp_read (hdsp
, HDSP_statusRegister
) & HDSP_DllError
) != 0) {
766 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S_LOAD
);
767 hdsp_write(hdsp
, HDSP_fifoData
, 0);
769 if (hdsp_fifo_wait(hdsp
, 0, HDSP_SHORT_WAIT
) < 0) {
770 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S300
);
771 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S_LOAD
);
774 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S200
| HDSP_PROGRAM
);
775 hdsp_write (hdsp
, HDSP_fifoData
, 0);
776 if (hdsp_fifo_wait(hdsp
, 0, HDSP_SHORT_WAIT
) < 0)
779 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S_LOAD
);
780 hdsp_write(hdsp
, HDSP_fifoData
, 0);
781 if (hdsp_fifo_wait(hdsp
, 0, HDSP_SHORT_WAIT
) == 0) {
782 hdsp
->io_type
= Digiface
;
783 dev_info(hdsp
->card
->dev
, "Digiface found\n");
787 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S300
);
788 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S_LOAD
);
789 hdsp_write(hdsp
, HDSP_fifoData
, 0);
790 if (hdsp_fifo_wait(hdsp
, 0, HDSP_SHORT_WAIT
) == 0)
793 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S300
);
794 hdsp_write(hdsp
, HDSP_control2Reg
, HDSP_S_LOAD
);
795 hdsp_write(hdsp
, HDSP_fifoData
, 0);
796 if (hdsp_fifo_wait(hdsp
, 0, HDSP_SHORT_WAIT
) < 0)
800 dev_info(hdsp
->card
->dev
, "RPM found\n");
803 /* firmware was already loaded, get iobox type */
804 if (hdsp_read(hdsp
, HDSP_status2Register
) & HDSP_version2
)
806 else if (hdsp_read(hdsp
, HDSP_status2Register
) & HDSP_version1
)
807 hdsp
->io_type
= Multiface
;
809 hdsp
->io_type
= Digiface
;
814 hdsp
->io_type
= Multiface
;
815 dev_info(hdsp
->card
->dev
, "Multiface found\n");
820 static int hdsp_request_fw_loader(struct hdsp
*hdsp
);
822 static int hdsp_check_for_firmware (struct hdsp
*hdsp
, int load_on_demand
)
824 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
)
826 if ((hdsp_read (hdsp
, HDSP_statusRegister
) & HDSP_DllError
) != 0) {
827 hdsp
->state
&= ~HDSP_FirmwareLoaded
;
828 if (! load_on_demand
)
830 dev_err(hdsp
->card
->dev
, "firmware not present.\n");
831 /* try to load firmware */
832 if (! (hdsp
->state
& HDSP_FirmwareCached
)) {
833 if (! hdsp_request_fw_loader(hdsp
))
835 dev_err(hdsp
->card
->dev
,
836 "No firmware loaded nor cached, please upload firmware.\n");
839 if (snd_hdsp_load_firmware_from_cache(hdsp
) != 0) {
840 dev_err(hdsp
->card
->dev
,
841 "Firmware loading from cache failed, please upload manually.\n");
849 static int hdsp_fifo_wait(struct hdsp
*hdsp
, int count
, int timeout
)
853 /* the fifoStatus registers reports on how many words
854 are available in the command FIFO.
857 for (i
= 0; i
< timeout
; i
++) {
859 if ((int)(hdsp_read (hdsp
, HDSP_fifoStatus
) & 0xff) <= count
)
862 /* not very friendly, but we only do this during a firmware
863 load and changing the mixer, so we just put up with it.
869 dev_warn(hdsp
->card
->dev
,
870 "wait for FIFO status <= %d failed after %d iterations\n",
875 static int hdsp_read_gain (struct hdsp
*hdsp
, unsigned int addr
)
877 if (addr
>= HDSP_MATRIX_MIXER_SIZE
)
880 return hdsp
->mixer_matrix
[addr
];
883 static int hdsp_write_gain(struct hdsp
*hdsp
, unsigned int addr
, unsigned short data
)
887 if (addr
>= HDSP_MATRIX_MIXER_SIZE
)
890 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
) {
892 /* from martin bjornsen:
894 "You can only write dwords to the
895 mixer memory which contain two
896 mixer values in the low and high
897 word. So if you want to change
898 value 0 you have to read value 1
899 from the cache and write both to
900 the first dword in the mixer
904 if (hdsp
->io_type
== H9632
&& addr
>= 512)
907 if (hdsp
->io_type
== H9652
&& addr
>= 1352)
910 hdsp
->mixer_matrix
[addr
] = data
;
913 /* `addr' addresses a 16-bit wide address, but
914 the address space accessed via hdsp_write
915 uses byte offsets. put another way, addr
916 varies from 0 to 1351, but to access the
917 corresponding memory location, we need
918 to access 0 to 2703 ...
922 hdsp_write (hdsp
, 4096 + (ad
*4),
923 (hdsp
->mixer_matrix
[(addr
&0x7fe)+1] << 16) +
924 hdsp
->mixer_matrix
[addr
&0x7fe]);
930 ad
= (addr
<< 16) + data
;
932 if (hdsp_fifo_wait(hdsp
, 127, HDSP_LONG_WAIT
))
935 hdsp_write (hdsp
, HDSP_fifoData
, ad
);
936 hdsp
->mixer_matrix
[addr
] = data
;
943 static int snd_hdsp_use_is_exclusive(struct hdsp
*hdsp
)
948 spin_lock_irqsave(&hdsp
->lock
, flags
);
949 if ((hdsp
->playback_pid
!= hdsp
->capture_pid
) &&
950 (hdsp
->playback_pid
>= 0) && (hdsp
->capture_pid
>= 0))
952 spin_unlock_irqrestore(&hdsp
->lock
, flags
);
956 static int hdsp_spdif_sample_rate(struct hdsp
*hdsp
)
958 unsigned int status
= hdsp_read(hdsp
, HDSP_statusRegister
);
959 unsigned int rate_bits
= (status
& HDSP_spdifFrequencyMask
);
961 /* For the 9632, the mask is different */
962 if (hdsp
->io_type
== H9632
)
963 rate_bits
= (status
& HDSP_spdifFrequencyMask_9632
);
965 if (status
& HDSP_SPDIFErrorFlag
)
969 case HDSP_spdifFrequency32KHz
: return 32000;
970 case HDSP_spdifFrequency44_1KHz
: return 44100;
971 case HDSP_spdifFrequency48KHz
: return 48000;
972 case HDSP_spdifFrequency64KHz
: return 64000;
973 case HDSP_spdifFrequency88_2KHz
: return 88200;
974 case HDSP_spdifFrequency96KHz
: return 96000;
975 case HDSP_spdifFrequency128KHz
:
976 if (hdsp
->io_type
== H9632
) return 128000;
978 case HDSP_spdifFrequency176_4KHz
:
979 if (hdsp
->io_type
== H9632
) return 176400;
981 case HDSP_spdifFrequency192KHz
:
982 if (hdsp
->io_type
== H9632
) return 192000;
987 dev_warn(hdsp
->card
->dev
,
988 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
993 static int hdsp_external_sample_rate(struct hdsp
*hdsp
)
995 unsigned int status2
= hdsp_read(hdsp
, HDSP_status2Register
);
996 unsigned int rate_bits
= status2
& HDSP_systemFrequencyMask
;
998 /* For the 9632 card, there seems to be no bit for indicating external
999 * sample rate greater than 96kHz. The card reports the corresponding
1000 * single speed. So the best means seems to get spdif rate when
1001 * autosync reference is spdif */
1002 if (hdsp
->io_type
== H9632
&&
1003 hdsp_autosync_ref(hdsp
) == HDSP_AUTOSYNC_FROM_SPDIF
)
1004 return hdsp_spdif_sample_rate(hdsp
);
1006 switch (rate_bits
) {
1007 case HDSP_systemFrequency32
: return 32000;
1008 case HDSP_systemFrequency44_1
: return 44100;
1009 case HDSP_systemFrequency48
: return 48000;
1010 case HDSP_systemFrequency64
: return 64000;
1011 case HDSP_systemFrequency88_2
: return 88200;
1012 case HDSP_systemFrequency96
: return 96000;
1018 static void hdsp_compute_period_size(struct hdsp
*hdsp
)
1020 hdsp
->period_bytes
= 1 << ((hdsp_decode_latency(hdsp
->control_register
) + 8));
1023 static snd_pcm_uframes_t
hdsp_hw_pointer(struct hdsp
*hdsp
)
1027 position
= hdsp_read(hdsp
, HDSP_statusRegister
);
1029 if (!hdsp
->precise_ptr
)
1030 return (position
& HDSP_BufferID
) ? (hdsp
->period_bytes
/ 4) : 0;
1032 position
&= HDSP_BufferPositionMask
;
1034 position
&= (hdsp
->period_bytes
/2) - 1;
1038 static void hdsp_reset_hw_pointer(struct hdsp
*hdsp
)
1040 hdsp_write (hdsp
, HDSP_resetPointer
, 0);
1041 if (hdsp
->io_type
== H9632
&& hdsp
->firmware_rev
>= 152)
1042 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1043 * requires (?) to write again DDS value after a reset pointer
1044 * (at least, it works like this) */
1045 hdsp_write (hdsp
, HDSP_freqReg
, hdsp
->dds_value
);
1048 static void hdsp_start_audio(struct hdsp
*s
)
1050 s
->control_register
|= (HDSP_AudioInterruptEnable
| HDSP_Start
);
1051 hdsp_write(s
, HDSP_controlRegister
, s
->control_register
);
1054 static void hdsp_stop_audio(struct hdsp
*s
)
1056 s
->control_register
&= ~(HDSP_Start
| HDSP_AudioInterruptEnable
);
1057 hdsp_write(s
, HDSP_controlRegister
, s
->control_register
);
1060 static void hdsp_silence_playback(struct hdsp
*hdsp
)
1062 memset(hdsp
->playback_buffer
, 0, HDSP_DMA_AREA_BYTES
);
1065 static int hdsp_set_interrupt_interval(struct hdsp
*s
, unsigned int frames
)
1069 spin_lock_irq(&s
->lock
);
1078 s
->control_register
&= ~HDSP_LatencyMask
;
1079 s
->control_register
|= hdsp_encode_latency(n
);
1081 hdsp_write(s
, HDSP_controlRegister
, s
->control_register
);
1083 hdsp_compute_period_size(s
);
1085 spin_unlock_irq(&s
->lock
);
1090 static void hdsp_set_dds_value(struct hdsp
*hdsp
, int rate
)
1096 else if (rate
>= 56000)
1100 n
= div_u64(n
, rate
);
1101 /* n should be less than 2^32 for being written to FREQ register */
1102 snd_BUG_ON(n
>> 32);
1103 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1104 value to write it after a reset */
1105 hdsp
->dds_value
= n
;
1106 hdsp_write(hdsp
, HDSP_freqReg
, hdsp
->dds_value
);
1109 static int hdsp_set_rate(struct hdsp
*hdsp
, int rate
, int called_internally
)
1111 int reject_if_open
= 0;
1115 /* ASSUMPTION: hdsp->lock is either held, or
1116 there is no need for it (e.g. during module
1120 if (!(hdsp
->control_register
& HDSP_ClockModeMaster
)) {
1121 if (called_internally
) {
1122 /* request from ctl or card initialization */
1123 dev_err(hdsp
->card
->dev
,
1124 "device is not running as a clock master: cannot set sample rate.\n");
1127 /* hw_param request while in AutoSync mode */
1128 int external_freq
= hdsp_external_sample_rate(hdsp
);
1129 int spdif_freq
= hdsp_spdif_sample_rate(hdsp
);
1131 if ((spdif_freq
== external_freq
*2) && (hdsp_autosync_ref(hdsp
) >= HDSP_AUTOSYNC_FROM_ADAT1
))
1132 dev_info(hdsp
->card
->dev
,
1133 "Detected ADAT in double speed mode\n");
1134 else if (hdsp
->io_type
== H9632
&& (spdif_freq
== external_freq
*4) && (hdsp_autosync_ref(hdsp
) >= HDSP_AUTOSYNC_FROM_ADAT1
))
1135 dev_info(hdsp
->card
->dev
,
1136 "Detected ADAT in quad speed mode\n");
1137 else if (rate
!= external_freq
) {
1138 dev_info(hdsp
->card
->dev
,
1139 "No AutoSync source for requested rate\n");
1145 current_rate
= hdsp
->system_sample_rate
;
1147 /* Changing from a "single speed" to a "double speed" rate is
1148 not allowed if any substreams are open. This is because
1149 such a change causes a shift in the location of
1150 the DMA buffers and a reduction in the number of available
1153 Note that a similar but essentially insoluble problem
1154 exists for externally-driven rate changes. All we can do
1155 is to flag rate changes in the read/write routines. */
1157 if (rate
> 96000 && hdsp
->io_type
!= H9632
)
1162 if (current_rate
> 48000)
1164 rate_bits
= HDSP_Frequency32KHz
;
1167 if (current_rate
> 48000)
1169 rate_bits
= HDSP_Frequency44_1KHz
;
1172 if (current_rate
> 48000)
1174 rate_bits
= HDSP_Frequency48KHz
;
1177 if (current_rate
<= 48000 || current_rate
> 96000)
1179 rate_bits
= HDSP_Frequency64KHz
;
1182 if (current_rate
<= 48000 || current_rate
> 96000)
1184 rate_bits
= HDSP_Frequency88_2KHz
;
1187 if (current_rate
<= 48000 || current_rate
> 96000)
1189 rate_bits
= HDSP_Frequency96KHz
;
1192 if (current_rate
< 128000)
1194 rate_bits
= HDSP_Frequency128KHz
;
1197 if (current_rate
< 128000)
1199 rate_bits
= HDSP_Frequency176_4KHz
;
1202 if (current_rate
< 128000)
1204 rate_bits
= HDSP_Frequency192KHz
;
1210 if (reject_if_open
&& (hdsp
->capture_pid
>= 0 || hdsp
->playback_pid
>= 0)) {
1211 dev_warn(hdsp
->card
->dev
,
1212 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1214 hdsp
->playback_pid
);
1218 hdsp
->control_register
&= ~HDSP_FrequencyMask
;
1219 hdsp
->control_register
|= rate_bits
;
1220 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
1222 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1223 if (hdsp
->io_type
== H9632
&& hdsp
->firmware_rev
>= 152)
1224 hdsp_set_dds_value(hdsp
, rate
);
1226 if (rate
>= 128000) {
1227 hdsp
->channel_map
= channel_map_H9632_qs
;
1228 } else if (rate
> 48000) {
1229 if (hdsp
->io_type
== H9632
)
1230 hdsp
->channel_map
= channel_map_H9632_ds
;
1232 hdsp
->channel_map
= channel_map_ds
;
1234 switch (hdsp
->io_type
) {
1237 hdsp
->channel_map
= channel_map_mf_ss
;
1241 hdsp
->channel_map
= channel_map_df_ss
;
1244 hdsp
->channel_map
= channel_map_H9632_ss
;
1247 /* should never happen */
1252 hdsp
->system_sample_rate
= rate
;
1257 /*----------------------------------------------------------------------------
1259 ----------------------------------------------------------------------------*/
1261 static unsigned char snd_hdsp_midi_read_byte (struct hdsp
*hdsp
, int id
)
1263 /* the hardware already does the relevant bit-mask with 0xff */
1265 return hdsp_read(hdsp
, HDSP_midiDataIn1
);
1267 return hdsp_read(hdsp
, HDSP_midiDataIn0
);
1270 static void snd_hdsp_midi_write_byte (struct hdsp
*hdsp
, int id
, int val
)
1272 /* the hardware already does the relevant bit-mask with 0xff */
1274 hdsp_write(hdsp
, HDSP_midiDataOut1
, val
);
1276 hdsp_write(hdsp
, HDSP_midiDataOut0
, val
);
1279 static int snd_hdsp_midi_input_available (struct hdsp
*hdsp
, int id
)
1282 return (hdsp_read(hdsp
, HDSP_midiStatusIn1
) & 0xff);
1284 return (hdsp_read(hdsp
, HDSP_midiStatusIn0
) & 0xff);
1287 static int snd_hdsp_midi_output_possible (struct hdsp
*hdsp
, int id
)
1289 int fifo_bytes_used
;
1292 fifo_bytes_used
= hdsp_read(hdsp
, HDSP_midiStatusOut1
) & 0xff;
1294 fifo_bytes_used
= hdsp_read(hdsp
, HDSP_midiStatusOut0
) & 0xff;
1296 if (fifo_bytes_used
< 128)
1297 return 128 - fifo_bytes_used
;
1302 static void snd_hdsp_flush_midi_input (struct hdsp
*hdsp
, int id
)
1304 while (snd_hdsp_midi_input_available (hdsp
, id
))
1305 snd_hdsp_midi_read_byte (hdsp
, id
);
1308 static int snd_hdsp_midi_output_write (struct hdsp_midi
*hmidi
)
1310 unsigned long flags
;
1314 unsigned char buf
[128];
1316 /* Output is not interrupt driven */
1318 spin_lock_irqsave (&hmidi
->lock
, flags
);
1319 if (hmidi
->output
) {
1320 if (!snd_rawmidi_transmit_empty (hmidi
->output
)) {
1321 if ((n_pending
= snd_hdsp_midi_output_possible (hmidi
->hdsp
, hmidi
->id
)) > 0) {
1322 if (n_pending
> (int)sizeof (buf
))
1323 n_pending
= sizeof (buf
);
1325 if ((to_write
= snd_rawmidi_transmit (hmidi
->output
, buf
, n_pending
)) > 0) {
1326 for (i
= 0; i
< to_write
; ++i
)
1327 snd_hdsp_midi_write_byte (hmidi
->hdsp
, hmidi
->id
, buf
[i
]);
1332 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1336 static int snd_hdsp_midi_input_read (struct hdsp_midi
*hmidi
)
1338 unsigned char buf
[128]; /* this buffer is designed to match the MIDI input FIFO size */
1339 unsigned long flags
;
1343 spin_lock_irqsave (&hmidi
->lock
, flags
);
1344 if ((n_pending
= snd_hdsp_midi_input_available (hmidi
->hdsp
, hmidi
->id
)) > 0) {
1346 if (n_pending
> (int)sizeof (buf
))
1347 n_pending
= sizeof (buf
);
1348 for (i
= 0; i
< n_pending
; ++i
)
1349 buf
[i
] = snd_hdsp_midi_read_byte (hmidi
->hdsp
, hmidi
->id
);
1351 snd_rawmidi_receive (hmidi
->input
, buf
, n_pending
);
1353 /* flush the MIDI input FIFO */
1355 snd_hdsp_midi_read_byte (hmidi
->hdsp
, hmidi
->id
);
1360 hmidi
->hdsp
->control_register
|= HDSP_Midi1InterruptEnable
;
1362 hmidi
->hdsp
->control_register
|= HDSP_Midi0InterruptEnable
;
1363 hdsp_write(hmidi
->hdsp
, HDSP_controlRegister
, hmidi
->hdsp
->control_register
);
1364 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1365 return snd_hdsp_midi_output_write (hmidi
);
1368 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream
*substream
, int up
)
1371 struct hdsp_midi
*hmidi
;
1372 unsigned long flags
;
1375 hmidi
= (struct hdsp_midi
*) substream
->rmidi
->private_data
;
1377 ie
= hmidi
->id
? HDSP_Midi1InterruptEnable
: HDSP_Midi0InterruptEnable
;
1378 spin_lock_irqsave (&hdsp
->lock
, flags
);
1380 if (!(hdsp
->control_register
& ie
)) {
1381 snd_hdsp_flush_midi_input (hdsp
, hmidi
->id
);
1382 hdsp
->control_register
|= ie
;
1385 hdsp
->control_register
&= ~ie
;
1388 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
1389 spin_unlock_irqrestore (&hdsp
->lock
, flags
);
1392 static void snd_hdsp_midi_output_timer(struct timer_list
*t
)
1394 struct hdsp_midi
*hmidi
= from_timer(hmidi
, t
, timer
);
1395 unsigned long flags
;
1397 snd_hdsp_midi_output_write(hmidi
);
1398 spin_lock_irqsave (&hmidi
->lock
, flags
);
1400 /* this does not bump hmidi->istimer, because the
1401 kernel automatically removed the timer when it
1402 expired, and we are now adding it back, thus
1403 leaving istimer wherever it was set before.
1407 mod_timer(&hmidi
->timer
, 1 + jiffies
);
1409 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1412 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream
*substream
, int up
)
1414 struct hdsp_midi
*hmidi
;
1415 unsigned long flags
;
1417 hmidi
= (struct hdsp_midi
*) substream
->rmidi
->private_data
;
1418 spin_lock_irqsave (&hmidi
->lock
, flags
);
1420 if (!hmidi
->istimer
) {
1421 timer_setup(&hmidi
->timer
, snd_hdsp_midi_output_timer
,
1423 mod_timer(&hmidi
->timer
, 1 + jiffies
);
1427 if (hmidi
->istimer
&& --hmidi
->istimer
<= 0)
1428 del_timer (&hmidi
->timer
);
1430 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1432 snd_hdsp_midi_output_write(hmidi
);
1435 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream
*substream
)
1437 struct hdsp_midi
*hmidi
;
1439 hmidi
= (struct hdsp_midi
*) substream
->rmidi
->private_data
;
1440 spin_lock_irq (&hmidi
->lock
);
1441 snd_hdsp_flush_midi_input (hmidi
->hdsp
, hmidi
->id
);
1442 hmidi
->input
= substream
;
1443 spin_unlock_irq (&hmidi
->lock
);
1448 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream
*substream
)
1450 struct hdsp_midi
*hmidi
;
1452 hmidi
= (struct hdsp_midi
*) substream
->rmidi
->private_data
;
1453 spin_lock_irq (&hmidi
->lock
);
1454 hmidi
->output
= substream
;
1455 spin_unlock_irq (&hmidi
->lock
);
1460 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream
*substream
)
1462 struct hdsp_midi
*hmidi
;
1464 snd_hdsp_midi_input_trigger (substream
, 0);
1466 hmidi
= (struct hdsp_midi
*) substream
->rmidi
->private_data
;
1467 spin_lock_irq (&hmidi
->lock
);
1468 hmidi
->input
= NULL
;
1469 spin_unlock_irq (&hmidi
->lock
);
1474 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream
*substream
)
1476 struct hdsp_midi
*hmidi
;
1478 snd_hdsp_midi_output_trigger (substream
, 0);
1480 hmidi
= (struct hdsp_midi
*) substream
->rmidi
->private_data
;
1481 spin_lock_irq (&hmidi
->lock
);
1482 hmidi
->output
= NULL
;
1483 spin_unlock_irq (&hmidi
->lock
);
1488 static const struct snd_rawmidi_ops snd_hdsp_midi_output
=
1490 .open
= snd_hdsp_midi_output_open
,
1491 .close
= snd_hdsp_midi_output_close
,
1492 .trigger
= snd_hdsp_midi_output_trigger
,
1495 static const struct snd_rawmidi_ops snd_hdsp_midi_input
=
1497 .open
= snd_hdsp_midi_input_open
,
1498 .close
= snd_hdsp_midi_input_close
,
1499 .trigger
= snd_hdsp_midi_input_trigger
,
1502 static int snd_hdsp_create_midi (struct snd_card
*card
, struct hdsp
*hdsp
, int id
)
1506 hdsp
->midi
[id
].id
= id
;
1507 hdsp
->midi
[id
].rmidi
= NULL
;
1508 hdsp
->midi
[id
].input
= NULL
;
1509 hdsp
->midi
[id
].output
= NULL
;
1510 hdsp
->midi
[id
].hdsp
= hdsp
;
1511 hdsp
->midi
[id
].istimer
= 0;
1512 hdsp
->midi
[id
].pending
= 0;
1513 spin_lock_init (&hdsp
->midi
[id
].lock
);
1515 snprintf(buf
, sizeof(buf
), "%s MIDI %d", card
->shortname
, id
+ 1);
1516 if (snd_rawmidi_new (card
, buf
, id
, 1, 1, &hdsp
->midi
[id
].rmidi
) < 0)
1519 sprintf(hdsp
->midi
[id
].rmidi
->name
, "HDSP MIDI %d", id
+1);
1520 hdsp
->midi
[id
].rmidi
->private_data
= &hdsp
->midi
[id
];
1522 snd_rawmidi_set_ops (hdsp
->midi
[id
].rmidi
, SNDRV_RAWMIDI_STREAM_OUTPUT
, &snd_hdsp_midi_output
);
1523 snd_rawmidi_set_ops (hdsp
->midi
[id
].rmidi
, SNDRV_RAWMIDI_STREAM_INPUT
, &snd_hdsp_midi_input
);
1525 hdsp
->midi
[id
].rmidi
->info_flags
|= SNDRV_RAWMIDI_INFO_OUTPUT
|
1526 SNDRV_RAWMIDI_INFO_INPUT
|
1527 SNDRV_RAWMIDI_INFO_DUPLEX
;
1532 /*-----------------------------------------------------------------------------
1534 ----------------------------------------------------------------------------*/
1536 static u32
snd_hdsp_convert_from_aes(struct snd_aes_iec958
*aes
)
1539 val
|= (aes
->status
[0] & IEC958_AES0_PROFESSIONAL
) ? HDSP_SPDIFProfessional
: 0;
1540 val
|= (aes
->status
[0] & IEC958_AES0_NONAUDIO
) ? HDSP_SPDIFNonAudio
: 0;
1541 if (val
& HDSP_SPDIFProfessional
)
1542 val
|= (aes
->status
[0] & IEC958_AES0_PRO_EMPHASIS_5015
) ? HDSP_SPDIFEmphasis
: 0;
1544 val
|= (aes
->status
[0] & IEC958_AES0_CON_EMPHASIS_5015
) ? HDSP_SPDIFEmphasis
: 0;
1548 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958
*aes
, u32 val
)
1550 aes
->status
[0] = ((val
& HDSP_SPDIFProfessional
) ? IEC958_AES0_PROFESSIONAL
: 0) |
1551 ((val
& HDSP_SPDIFNonAudio
) ? IEC958_AES0_NONAUDIO
: 0);
1552 if (val
& HDSP_SPDIFProfessional
)
1553 aes
->status
[0] |= (val
& HDSP_SPDIFEmphasis
) ? IEC958_AES0_PRO_EMPHASIS_5015
: 0;
1555 aes
->status
[0] |= (val
& HDSP_SPDIFEmphasis
) ? IEC958_AES0_CON_EMPHASIS_5015
: 0;
1558 static int snd_hdsp_control_spdif_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1560 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1565 static int snd_hdsp_control_spdif_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1567 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1569 snd_hdsp_convert_to_aes(&ucontrol
->value
.iec958
, hdsp
->creg_spdif
);
1573 static int snd_hdsp_control_spdif_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1575 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1579 val
= snd_hdsp_convert_from_aes(&ucontrol
->value
.iec958
);
1580 spin_lock_irq(&hdsp
->lock
);
1581 change
= val
!= hdsp
->creg_spdif
;
1582 hdsp
->creg_spdif
= val
;
1583 spin_unlock_irq(&hdsp
->lock
);
1587 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1589 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1594 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1596 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1598 snd_hdsp_convert_to_aes(&ucontrol
->value
.iec958
, hdsp
->creg_spdif_stream
);
1602 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1604 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1608 val
= snd_hdsp_convert_from_aes(&ucontrol
->value
.iec958
);
1609 spin_lock_irq(&hdsp
->lock
);
1610 change
= val
!= hdsp
->creg_spdif_stream
;
1611 hdsp
->creg_spdif_stream
= val
;
1612 hdsp
->control_register
&= ~(HDSP_SPDIFProfessional
| HDSP_SPDIFNonAudio
| HDSP_SPDIFEmphasis
);
1613 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
|= val
);
1614 spin_unlock_irq(&hdsp
->lock
);
1618 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1620 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1625 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1627 ucontrol
->value
.iec958
.status
[0] = kcontrol
->private_value
;
1631 #define HDSP_SPDIF_IN(xname, xindex) \
1632 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1635 .info = snd_hdsp_info_spdif_in, \
1636 .get = snd_hdsp_get_spdif_in, \
1637 .put = snd_hdsp_put_spdif_in }
1639 static unsigned int hdsp_spdif_in(struct hdsp
*hdsp
)
1641 return hdsp_decode_spdif_in(hdsp
->control_register
& HDSP_SPDIFInputMask
);
1644 static int hdsp_set_spdif_input(struct hdsp
*hdsp
, int in
)
1646 hdsp
->control_register
&= ~HDSP_SPDIFInputMask
;
1647 hdsp
->control_register
|= hdsp_encode_spdif_in(in
);
1648 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
1652 static int snd_hdsp_info_spdif_in(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1654 static const char * const texts
[4] = {
1655 "Optical", "Coaxial", "Internal", "AES"
1657 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1659 return snd_ctl_enum_info(uinfo
, 1, (hdsp
->io_type
== H9632
) ? 4 : 3,
1663 static int snd_hdsp_get_spdif_in(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1665 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1667 ucontrol
->value
.enumerated
.item
[0] = hdsp_spdif_in(hdsp
);
1671 static int snd_hdsp_put_spdif_in(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1673 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1677 if (!snd_hdsp_use_is_exclusive(hdsp
))
1679 val
= ucontrol
->value
.enumerated
.item
[0] % ((hdsp
->io_type
== H9632
) ? 4 : 3);
1680 spin_lock_irq(&hdsp
->lock
);
1681 change
= val
!= hdsp_spdif_in(hdsp
);
1683 hdsp_set_spdif_input(hdsp
, val
);
1684 spin_unlock_irq(&hdsp
->lock
);
1688 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1689 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1691 .private_value = xindex, \
1692 .info = snd_hdsp_info_toggle_setting, \
1693 .get = snd_hdsp_get_toggle_setting, \
1694 .put = snd_hdsp_put_toggle_setting \
1697 static int hdsp_toggle_setting(struct hdsp
*hdsp
, u32 regmask
)
1699 return (hdsp
->control_register
& regmask
) ? 1 : 0;
1702 static int hdsp_set_toggle_setting(struct hdsp
*hdsp
, u32 regmask
, int out
)
1705 hdsp
->control_register
|= regmask
;
1707 hdsp
->control_register
&= ~regmask
;
1708 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
1713 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1715 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol
*kcontrol
,
1716 struct snd_ctl_elem_value
*ucontrol
)
1718 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1719 u32 regmask
= kcontrol
->private_value
;
1721 spin_lock_irq(&hdsp
->lock
);
1722 ucontrol
->value
.integer
.value
[0] = hdsp_toggle_setting(hdsp
, regmask
);
1723 spin_unlock_irq(&hdsp
->lock
);
1727 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol
*kcontrol
,
1728 struct snd_ctl_elem_value
*ucontrol
)
1730 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1731 u32 regmask
= kcontrol
->private_value
;
1735 if (!snd_hdsp_use_is_exclusive(hdsp
))
1737 val
= ucontrol
->value
.integer
.value
[0] & 1;
1738 spin_lock_irq(&hdsp
->lock
);
1739 change
= (int) val
!= hdsp_toggle_setting(hdsp
, regmask
);
1741 hdsp_set_toggle_setting(hdsp
, regmask
, val
);
1742 spin_unlock_irq(&hdsp
->lock
);
1746 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1747 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1750 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1751 .info = snd_hdsp_info_spdif_sample_rate, \
1752 .get = snd_hdsp_get_spdif_sample_rate \
1755 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1757 static const char * const texts
[] = {
1758 "32000", "44100", "48000", "64000", "88200", "96000",
1759 "None", "128000", "176400", "192000"
1761 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1763 return snd_ctl_enum_info(uinfo
, 1, (hdsp
->io_type
== H9632
) ? 10 : 7,
1767 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1769 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1771 switch (hdsp_spdif_sample_rate(hdsp
)) {
1773 ucontrol
->value
.enumerated
.item
[0] = 0;
1776 ucontrol
->value
.enumerated
.item
[0] = 1;
1779 ucontrol
->value
.enumerated
.item
[0] = 2;
1782 ucontrol
->value
.enumerated
.item
[0] = 3;
1785 ucontrol
->value
.enumerated
.item
[0] = 4;
1788 ucontrol
->value
.enumerated
.item
[0] = 5;
1791 ucontrol
->value
.enumerated
.item
[0] = 7;
1794 ucontrol
->value
.enumerated
.item
[0] = 8;
1797 ucontrol
->value
.enumerated
.item
[0] = 9;
1800 ucontrol
->value
.enumerated
.item
[0] = 6;
1805 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1806 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1809 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1810 .info = snd_hdsp_info_system_sample_rate, \
1811 .get = snd_hdsp_get_system_sample_rate \
1814 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1816 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
1821 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1823 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1825 ucontrol
->value
.enumerated
.item
[0] = hdsp
->system_sample_rate
;
1829 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1833 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1834 .info = snd_hdsp_info_autosync_sample_rate, \
1835 .get = snd_hdsp_get_autosync_sample_rate \
1838 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1840 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1841 static const char * const texts
[] = {
1842 "32000", "44100", "48000", "64000", "88200", "96000",
1843 "None", "128000", "176400", "192000"
1846 return snd_ctl_enum_info(uinfo
, 1, (hdsp
->io_type
== H9632
) ? 10 : 7,
1850 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1852 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1854 switch (hdsp_external_sample_rate(hdsp
)) {
1856 ucontrol
->value
.enumerated
.item
[0] = 0;
1859 ucontrol
->value
.enumerated
.item
[0] = 1;
1862 ucontrol
->value
.enumerated
.item
[0] = 2;
1865 ucontrol
->value
.enumerated
.item
[0] = 3;
1868 ucontrol
->value
.enumerated
.item
[0] = 4;
1871 ucontrol
->value
.enumerated
.item
[0] = 5;
1874 ucontrol
->value
.enumerated
.item
[0] = 7;
1877 ucontrol
->value
.enumerated
.item
[0] = 8;
1880 ucontrol
->value
.enumerated
.item
[0] = 9;
1883 ucontrol
->value
.enumerated
.item
[0] = 6;
1888 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1889 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1892 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1893 .info = snd_hdsp_info_system_clock_mode, \
1894 .get = snd_hdsp_get_system_clock_mode \
1897 static int hdsp_system_clock_mode(struct hdsp
*hdsp
)
1899 if (hdsp
->control_register
& HDSP_ClockModeMaster
)
1901 else if (hdsp_external_sample_rate(hdsp
) != hdsp
->system_sample_rate
)
1906 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1908 static const char * const texts
[] = {"Master", "Slave" };
1910 return snd_ctl_enum_info(uinfo
, 1, 2, texts
);
1913 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1915 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
1917 ucontrol
->value
.enumerated
.item
[0] = hdsp_system_clock_mode(hdsp
);
1921 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1922 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1925 .info = snd_hdsp_info_clock_source, \
1926 .get = snd_hdsp_get_clock_source, \
1927 .put = snd_hdsp_put_clock_source \
1930 static int hdsp_clock_source(struct hdsp
*hdsp
)
1932 if (hdsp
->control_register
& HDSP_ClockModeMaster
) {
1933 switch (hdsp
->system_sample_rate
) {
1960 static int hdsp_set_clock_source(struct hdsp
*hdsp
, int mode
)
1964 case HDSP_CLOCK_SOURCE_AUTOSYNC
:
1965 if (hdsp_external_sample_rate(hdsp
) != 0) {
1966 if (!hdsp_set_rate(hdsp
, hdsp_external_sample_rate(hdsp
), 1)) {
1967 hdsp
->control_register
&= ~HDSP_ClockModeMaster
;
1968 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
1973 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ
:
1976 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ
:
1979 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ
:
1982 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ
:
1985 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ
:
1988 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ
:
1991 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ
:
1994 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ
:
1997 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ
:
2003 hdsp
->control_register
|= HDSP_ClockModeMaster
;
2004 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
2005 hdsp_set_rate(hdsp
, rate
, 1);
2009 static int snd_hdsp_info_clock_source(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2011 static const char * const texts
[] = {
2012 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2013 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2014 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2015 "Internal 192.0 KHz"
2017 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2019 return snd_ctl_enum_info(uinfo
, 1, (hdsp
->io_type
== H9632
) ? 10 : 7,
2023 static int snd_hdsp_get_clock_source(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2025 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2027 ucontrol
->value
.enumerated
.item
[0] = hdsp_clock_source(hdsp
);
2031 static int snd_hdsp_put_clock_source(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2033 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2037 if (!snd_hdsp_use_is_exclusive(hdsp
))
2039 val
= ucontrol
->value
.enumerated
.item
[0];
2040 if (val
< 0) val
= 0;
2041 if (hdsp
->io_type
== H9632
) {
2048 spin_lock_irq(&hdsp
->lock
);
2049 if (val
!= hdsp_clock_source(hdsp
))
2050 change
= (hdsp_set_clock_source(hdsp
, val
) == 0) ? 1 : 0;
2053 spin_unlock_irq(&hdsp
->lock
);
2057 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2059 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2061 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2063 ucontrol
->value
.integer
.value
[0] = hdsp
->clock_source_locked
;
2067 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2069 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2072 change
= (int)ucontrol
->value
.integer
.value
[0] != hdsp
->clock_source_locked
;
2074 hdsp
->clock_source_locked
= !!ucontrol
->value
.integer
.value
[0];
2078 #define HDSP_DA_GAIN(xname, xindex) \
2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2082 .info = snd_hdsp_info_da_gain, \
2083 .get = snd_hdsp_get_da_gain, \
2084 .put = snd_hdsp_put_da_gain \
2087 static int hdsp_da_gain(struct hdsp
*hdsp
)
2089 switch (hdsp
->control_register
& HDSP_DAGainMask
) {
2090 case HDSP_DAGainHighGain
:
2092 case HDSP_DAGainPlus4dBu
:
2094 case HDSP_DAGainMinus10dBV
:
2101 static int hdsp_set_da_gain(struct hdsp
*hdsp
, int mode
)
2103 hdsp
->control_register
&= ~HDSP_DAGainMask
;
2106 hdsp
->control_register
|= HDSP_DAGainHighGain
;
2109 hdsp
->control_register
|= HDSP_DAGainPlus4dBu
;
2112 hdsp
->control_register
|= HDSP_DAGainMinus10dBV
;
2118 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
2122 static int snd_hdsp_info_da_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2124 static const char * const texts
[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2126 return snd_ctl_enum_info(uinfo
, 1, 3, texts
);
2129 static int snd_hdsp_get_da_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2131 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2133 ucontrol
->value
.enumerated
.item
[0] = hdsp_da_gain(hdsp
);
2137 static int snd_hdsp_put_da_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2139 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2143 if (!snd_hdsp_use_is_exclusive(hdsp
))
2145 val
= ucontrol
->value
.enumerated
.item
[0];
2146 if (val
< 0) val
= 0;
2147 if (val
> 2) val
= 2;
2148 spin_lock_irq(&hdsp
->lock
);
2149 if (val
!= hdsp_da_gain(hdsp
))
2150 change
= (hdsp_set_da_gain(hdsp
, val
) == 0) ? 1 : 0;
2153 spin_unlock_irq(&hdsp
->lock
);
2157 #define HDSP_AD_GAIN(xname, xindex) \
2158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2161 .info = snd_hdsp_info_ad_gain, \
2162 .get = snd_hdsp_get_ad_gain, \
2163 .put = snd_hdsp_put_ad_gain \
2166 static int hdsp_ad_gain(struct hdsp
*hdsp
)
2168 switch (hdsp
->control_register
& HDSP_ADGainMask
) {
2169 case HDSP_ADGainMinus10dBV
:
2171 case HDSP_ADGainPlus4dBu
:
2173 case HDSP_ADGainLowGain
:
2180 static int hdsp_set_ad_gain(struct hdsp
*hdsp
, int mode
)
2182 hdsp
->control_register
&= ~HDSP_ADGainMask
;
2185 hdsp
->control_register
|= HDSP_ADGainMinus10dBV
;
2188 hdsp
->control_register
|= HDSP_ADGainPlus4dBu
;
2191 hdsp
->control_register
|= HDSP_ADGainLowGain
;
2197 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
2201 static int snd_hdsp_info_ad_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2203 static const char * const texts
[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2205 return snd_ctl_enum_info(uinfo
, 1, 3, texts
);
2208 static int snd_hdsp_get_ad_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2210 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2212 ucontrol
->value
.enumerated
.item
[0] = hdsp_ad_gain(hdsp
);
2216 static int snd_hdsp_put_ad_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2218 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2222 if (!snd_hdsp_use_is_exclusive(hdsp
))
2224 val
= ucontrol
->value
.enumerated
.item
[0];
2225 if (val
< 0) val
= 0;
2226 if (val
> 2) val
= 2;
2227 spin_lock_irq(&hdsp
->lock
);
2228 if (val
!= hdsp_ad_gain(hdsp
))
2229 change
= (hdsp_set_ad_gain(hdsp
, val
) == 0) ? 1 : 0;
2232 spin_unlock_irq(&hdsp
->lock
);
2236 #define HDSP_PHONE_GAIN(xname, xindex) \
2237 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2240 .info = snd_hdsp_info_phone_gain, \
2241 .get = snd_hdsp_get_phone_gain, \
2242 .put = snd_hdsp_put_phone_gain \
2245 static int hdsp_phone_gain(struct hdsp
*hdsp
)
2247 switch (hdsp
->control_register
& HDSP_PhoneGainMask
) {
2248 case HDSP_PhoneGain0dB
:
2250 case HDSP_PhoneGainMinus6dB
:
2252 case HDSP_PhoneGainMinus12dB
:
2259 static int hdsp_set_phone_gain(struct hdsp
*hdsp
, int mode
)
2261 hdsp
->control_register
&= ~HDSP_PhoneGainMask
;
2264 hdsp
->control_register
|= HDSP_PhoneGain0dB
;
2267 hdsp
->control_register
|= HDSP_PhoneGainMinus6dB
;
2270 hdsp
->control_register
|= HDSP_PhoneGainMinus12dB
;
2276 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
2280 static int snd_hdsp_info_phone_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2282 static const char * const texts
[] = {"0 dB", "-6 dB", "-12 dB"};
2284 return snd_ctl_enum_info(uinfo
, 1, 3, texts
);
2287 static int snd_hdsp_get_phone_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2289 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2291 ucontrol
->value
.enumerated
.item
[0] = hdsp_phone_gain(hdsp
);
2295 static int snd_hdsp_put_phone_gain(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2297 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2301 if (!snd_hdsp_use_is_exclusive(hdsp
))
2303 val
= ucontrol
->value
.enumerated
.item
[0];
2304 if (val
< 0) val
= 0;
2305 if (val
> 2) val
= 2;
2306 spin_lock_irq(&hdsp
->lock
);
2307 if (val
!= hdsp_phone_gain(hdsp
))
2308 change
= (hdsp_set_phone_gain(hdsp
, val
) == 0) ? 1 : 0;
2311 spin_unlock_irq(&hdsp
->lock
);
2315 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2316 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2319 .info = snd_hdsp_info_pref_sync_ref, \
2320 .get = snd_hdsp_get_pref_sync_ref, \
2321 .put = snd_hdsp_put_pref_sync_ref \
2324 static int hdsp_pref_sync_ref(struct hdsp
*hdsp
)
2326 /* Notice that this looks at the requested sync source,
2327 not the one actually in use.
2330 switch (hdsp
->control_register
& HDSP_SyncRefMask
) {
2331 case HDSP_SyncRef_ADAT1
:
2332 return HDSP_SYNC_FROM_ADAT1
;
2333 case HDSP_SyncRef_ADAT2
:
2334 return HDSP_SYNC_FROM_ADAT2
;
2335 case HDSP_SyncRef_ADAT3
:
2336 return HDSP_SYNC_FROM_ADAT3
;
2337 case HDSP_SyncRef_SPDIF
:
2338 return HDSP_SYNC_FROM_SPDIF
;
2339 case HDSP_SyncRef_WORD
:
2340 return HDSP_SYNC_FROM_WORD
;
2341 case HDSP_SyncRef_ADAT_SYNC
:
2342 return HDSP_SYNC_FROM_ADAT_SYNC
;
2344 return HDSP_SYNC_FROM_WORD
;
2349 static int hdsp_set_pref_sync_ref(struct hdsp
*hdsp
, int pref
)
2351 hdsp
->control_register
&= ~HDSP_SyncRefMask
;
2353 case HDSP_SYNC_FROM_ADAT1
:
2354 hdsp
->control_register
&= ~HDSP_SyncRefMask
; /* clear SyncRef bits */
2356 case HDSP_SYNC_FROM_ADAT2
:
2357 hdsp
->control_register
|= HDSP_SyncRef_ADAT2
;
2359 case HDSP_SYNC_FROM_ADAT3
:
2360 hdsp
->control_register
|= HDSP_SyncRef_ADAT3
;
2362 case HDSP_SYNC_FROM_SPDIF
:
2363 hdsp
->control_register
|= HDSP_SyncRef_SPDIF
;
2365 case HDSP_SYNC_FROM_WORD
:
2366 hdsp
->control_register
|= HDSP_SyncRef_WORD
;
2368 case HDSP_SYNC_FROM_ADAT_SYNC
:
2369 hdsp
->control_register
|= HDSP_SyncRef_ADAT_SYNC
;
2374 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
2378 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2380 static const char * const texts
[] = {
2381 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2383 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2386 switch (hdsp
->io_type
) {
2401 return snd_ctl_enum_info(uinfo
, 1, num_items
, texts
);
2404 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2406 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2408 ucontrol
->value
.enumerated
.item
[0] = hdsp_pref_sync_ref(hdsp
);
2412 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2414 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2418 if (!snd_hdsp_use_is_exclusive(hdsp
))
2421 switch (hdsp
->io_type
) {
2436 val
= ucontrol
->value
.enumerated
.item
[0] % max
;
2437 spin_lock_irq(&hdsp
->lock
);
2438 change
= (int)val
!= hdsp_pref_sync_ref(hdsp
);
2439 hdsp_set_pref_sync_ref(hdsp
, val
);
2440 spin_unlock_irq(&hdsp
->lock
);
2444 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2445 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2448 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2449 .info = snd_hdsp_info_autosync_ref, \
2450 .get = snd_hdsp_get_autosync_ref, \
2453 static int hdsp_autosync_ref(struct hdsp
*hdsp
)
2455 /* This looks at the autosync selected sync reference */
2456 unsigned int status2
= hdsp_read(hdsp
, HDSP_status2Register
);
2458 switch (status2
& HDSP_SelSyncRefMask
) {
2459 case HDSP_SelSyncRef_WORD
:
2460 return HDSP_AUTOSYNC_FROM_WORD
;
2461 case HDSP_SelSyncRef_ADAT_SYNC
:
2462 return HDSP_AUTOSYNC_FROM_ADAT_SYNC
;
2463 case HDSP_SelSyncRef_SPDIF
:
2464 return HDSP_AUTOSYNC_FROM_SPDIF
;
2465 case HDSP_SelSyncRefMask
:
2466 return HDSP_AUTOSYNC_FROM_NONE
;
2467 case HDSP_SelSyncRef_ADAT1
:
2468 return HDSP_AUTOSYNC_FROM_ADAT1
;
2469 case HDSP_SelSyncRef_ADAT2
:
2470 return HDSP_AUTOSYNC_FROM_ADAT2
;
2471 case HDSP_SelSyncRef_ADAT3
:
2472 return HDSP_AUTOSYNC_FROM_ADAT3
;
2474 return HDSP_AUTOSYNC_FROM_WORD
;
2479 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2481 static const char * const texts
[] = {
2482 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2485 return snd_ctl_enum_info(uinfo
, 1, 7, texts
);
2488 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2490 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2492 ucontrol
->value
.enumerated
.item
[0] = hdsp_autosync_ref(hdsp
);
2496 #define HDSP_PRECISE_POINTER(xname, xindex) \
2497 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2500 .info = snd_hdsp_info_precise_pointer, \
2501 .get = snd_hdsp_get_precise_pointer, \
2502 .put = snd_hdsp_put_precise_pointer \
2505 static int hdsp_set_precise_pointer(struct hdsp
*hdsp
, int precise
)
2508 hdsp
->precise_ptr
= 1;
2510 hdsp
->precise_ptr
= 0;
2514 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2516 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2518 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2520 spin_lock_irq(&hdsp
->lock
);
2521 ucontrol
->value
.integer
.value
[0] = hdsp
->precise_ptr
;
2522 spin_unlock_irq(&hdsp
->lock
);
2526 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2528 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2532 if (!snd_hdsp_use_is_exclusive(hdsp
))
2534 val
= ucontrol
->value
.integer
.value
[0] & 1;
2535 spin_lock_irq(&hdsp
->lock
);
2536 change
= (int)val
!= hdsp
->precise_ptr
;
2537 hdsp_set_precise_pointer(hdsp
, val
);
2538 spin_unlock_irq(&hdsp
->lock
);
2542 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2543 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2546 .info = snd_hdsp_info_use_midi_work, \
2547 .get = snd_hdsp_get_use_midi_work, \
2548 .put = snd_hdsp_put_use_midi_work \
2551 static int hdsp_set_use_midi_work(struct hdsp
*hdsp
, int use_work
)
2554 hdsp
->use_midi_work
= 1;
2556 hdsp
->use_midi_work
= 0;
2560 #define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info
2562 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2564 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2566 spin_lock_irq(&hdsp
->lock
);
2567 ucontrol
->value
.integer
.value
[0] = hdsp
->use_midi_work
;
2568 spin_unlock_irq(&hdsp
->lock
);
2572 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2574 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2578 if (!snd_hdsp_use_is_exclusive(hdsp
))
2580 val
= ucontrol
->value
.integer
.value
[0] & 1;
2581 spin_lock_irq(&hdsp
->lock
);
2582 change
= (int)val
!= hdsp
->use_midi_work
;
2583 hdsp_set_use_midi_work(hdsp
, val
);
2584 spin_unlock_irq(&hdsp
->lock
);
2588 #define HDSP_MIXER(xname, xindex) \
2589 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2593 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2594 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2595 .info = snd_hdsp_info_mixer, \
2596 .get = snd_hdsp_get_mixer, \
2597 .put = snd_hdsp_put_mixer \
2600 static int snd_hdsp_info_mixer(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2602 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2604 uinfo
->value
.integer
.min
= 0;
2605 uinfo
->value
.integer
.max
= 65536;
2606 uinfo
->value
.integer
.step
= 1;
2610 static int snd_hdsp_get_mixer(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2612 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2617 source
= ucontrol
->value
.integer
.value
[0];
2618 destination
= ucontrol
->value
.integer
.value
[1];
2620 if (source
>= hdsp
->max_channels
)
2621 addr
= hdsp_playback_to_output_key(hdsp
,source
-hdsp
->max_channels
,destination
);
2623 addr
= hdsp_input_to_output_key(hdsp
,source
, destination
);
2625 spin_lock_irq(&hdsp
->lock
);
2626 ucontrol
->value
.integer
.value
[2] = hdsp_read_gain (hdsp
, addr
);
2627 spin_unlock_irq(&hdsp
->lock
);
2631 static int snd_hdsp_put_mixer(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2633 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2640 if (!snd_hdsp_use_is_exclusive(hdsp
))
2643 source
= ucontrol
->value
.integer
.value
[0];
2644 destination
= ucontrol
->value
.integer
.value
[1];
2646 if (source
>= hdsp
->max_channels
)
2647 addr
= hdsp_playback_to_output_key(hdsp
,source
-hdsp
->max_channels
, destination
);
2649 addr
= hdsp_input_to_output_key(hdsp
,source
, destination
);
2651 gain
= ucontrol
->value
.integer
.value
[2];
2653 spin_lock_irq(&hdsp
->lock
);
2654 change
= gain
!= hdsp_read_gain(hdsp
, addr
);
2656 hdsp_write_gain(hdsp
, addr
, gain
);
2657 spin_unlock_irq(&hdsp
->lock
);
2661 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2662 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2665 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2666 .info = snd_hdsp_info_sync_check, \
2667 .get = snd_hdsp_get_wc_sync_check \
2670 static int snd_hdsp_info_sync_check(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2672 static const char * const texts
[] = {"No Lock", "Lock", "Sync" };
2674 return snd_ctl_enum_info(uinfo
, 1, 3, texts
);
2677 static int hdsp_wc_sync_check(struct hdsp
*hdsp
)
2679 int status2
= hdsp_read(hdsp
, HDSP_status2Register
);
2680 if (status2
& HDSP_wc_lock
) {
2681 if (status2
& HDSP_wc_sync
)
2690 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2692 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2694 ucontrol
->value
.enumerated
.item
[0] = hdsp_wc_sync_check(hdsp
);
2698 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2699 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2702 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2703 .info = snd_hdsp_info_sync_check, \
2704 .get = snd_hdsp_get_spdif_sync_check \
2707 static int hdsp_spdif_sync_check(struct hdsp
*hdsp
)
2709 int status
= hdsp_read(hdsp
, HDSP_statusRegister
);
2710 if (status
& HDSP_SPDIFErrorFlag
)
2713 if (status
& HDSP_SPDIFSync
)
2721 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2723 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2725 ucontrol
->value
.enumerated
.item
[0] = hdsp_spdif_sync_check(hdsp
);
2729 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2730 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2733 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2734 .info = snd_hdsp_info_sync_check, \
2735 .get = snd_hdsp_get_adatsync_sync_check \
2738 static int hdsp_adatsync_sync_check(struct hdsp
*hdsp
)
2740 int status
= hdsp_read(hdsp
, HDSP_statusRegister
);
2741 if (status
& HDSP_TimecodeLock
) {
2742 if (status
& HDSP_TimecodeSync
)
2750 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2752 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2754 ucontrol
->value
.enumerated
.item
[0] = hdsp_adatsync_sync_check(hdsp
);
2758 #define HDSP_ADAT_SYNC_CHECK \
2759 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2760 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2761 .info = snd_hdsp_info_sync_check, \
2762 .get = snd_hdsp_get_adat_sync_check \
2765 static int hdsp_adat_sync_check(struct hdsp
*hdsp
, int idx
)
2767 int status
= hdsp_read(hdsp
, HDSP_statusRegister
);
2769 if (status
& (HDSP_Lock0
>>idx
)) {
2770 if (status
& (HDSP_Sync0
>>idx
))
2778 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2781 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2783 offset
= ucontrol
->id
.index
- 1;
2784 if (snd_BUG_ON(offset
< 0))
2787 switch (hdsp
->io_type
) {
2802 ucontrol
->value
.enumerated
.item
[0] = hdsp_adat_sync_check(hdsp
, offset
);
2806 #define HDSP_DDS_OFFSET(xname, xindex) \
2807 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2810 .info = snd_hdsp_info_dds_offset, \
2811 .get = snd_hdsp_get_dds_offset, \
2812 .put = snd_hdsp_put_dds_offset \
2815 static int hdsp_dds_offset(struct hdsp
*hdsp
)
2818 unsigned int dds_value
= hdsp
->dds_value
;
2819 int system_sample_rate
= hdsp
->system_sample_rate
;
2826 * dds_value = n / rate
2827 * rate = n / dds_value
2829 n
= div_u64(n
, dds_value
);
2830 if (system_sample_rate
>= 112000)
2832 else if (system_sample_rate
>= 56000)
2834 return ((int)n
) - system_sample_rate
;
2837 static int hdsp_set_dds_offset(struct hdsp
*hdsp
, int offset_hz
)
2839 int rate
= hdsp
->system_sample_rate
+ offset_hz
;
2840 hdsp_set_dds_value(hdsp
, rate
);
2844 static int snd_hdsp_info_dds_offset(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2846 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2848 uinfo
->value
.integer
.min
= -5000;
2849 uinfo
->value
.integer
.max
= 5000;
2853 static int snd_hdsp_get_dds_offset(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2855 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2857 ucontrol
->value
.integer
.value
[0] = hdsp_dds_offset(hdsp
);
2861 static int snd_hdsp_put_dds_offset(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2863 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2867 if (!snd_hdsp_use_is_exclusive(hdsp
))
2869 val
= ucontrol
->value
.integer
.value
[0];
2870 spin_lock_irq(&hdsp
->lock
);
2871 if (val
!= hdsp_dds_offset(hdsp
))
2872 change
= (hdsp_set_dds_offset(hdsp
, val
) == 0) ? 1 : 0;
2875 spin_unlock_irq(&hdsp
->lock
);
2879 static const struct snd_kcontrol_new snd_hdsp_9632_controls
[] = {
2880 HDSP_DA_GAIN("DA Gain", 0),
2881 HDSP_AD_GAIN("AD Gain", 0),
2882 HDSP_PHONE_GAIN("Phones Gain", 0),
2883 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable
),
2884 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2887 static const struct snd_kcontrol_new snd_hdsp_controls
[] = {
2889 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2890 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2891 .info
= snd_hdsp_control_spdif_info
,
2892 .get
= snd_hdsp_control_spdif_get
,
2893 .put
= snd_hdsp_control_spdif_put
,
2896 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
2897 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2898 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2899 .info
= snd_hdsp_control_spdif_stream_info
,
2900 .get
= snd_hdsp_control_spdif_stream_get
,
2901 .put
= snd_hdsp_control_spdif_stream_put
,
2904 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2905 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2906 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
2907 .info
= snd_hdsp_control_spdif_mask_info
,
2908 .get
= snd_hdsp_control_spdif_mask_get
,
2909 .private_value
= IEC958_AES0_NONAUDIO
|
2910 IEC958_AES0_PROFESSIONAL
|
2911 IEC958_AES0_CON_EMPHASIS
,
2914 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2915 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2916 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PRO_MASK
),
2917 .info
= snd_hdsp_control_spdif_mask_info
,
2918 .get
= snd_hdsp_control_spdif_mask_get
,
2919 .private_value
= IEC958_AES0_NONAUDIO
|
2920 IEC958_AES0_PROFESSIONAL
|
2921 IEC958_AES0_PRO_EMPHASIS
,
2923 HDSP_MIXER("Mixer", 0),
2924 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2925 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut
),
2926 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional
),
2927 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis
),
2928 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio
),
2929 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2930 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2932 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2933 .name
= "Sample Clock Source Locking",
2934 .info
= snd_hdsp_info_clock_source_lock
,
2935 .get
= snd_hdsp_get_clock_source_lock
,
2936 .put
= snd_hdsp_put_clock_source_lock
,
2938 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2939 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2940 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2941 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2942 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2943 /* 'External Rate' complies with the alsa control naming scheme */
2944 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2945 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2946 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2947 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2948 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut
),
2949 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2950 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2954 static int hdsp_rpm_input12(struct hdsp
*hdsp
)
2956 switch (hdsp
->control_register
& HDSP_RPM_Inp12
) {
2957 case HDSP_RPM_Inp12_Phon_6dB
:
2959 case HDSP_RPM_Inp12_Phon_n6dB
:
2961 case HDSP_RPM_Inp12_Line_0dB
:
2963 case HDSP_RPM_Inp12_Line_n6dB
:
2970 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2972 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
2974 ucontrol
->value
.enumerated
.item
[0] = hdsp_rpm_input12(hdsp
);
2979 static int hdsp_set_rpm_input12(struct hdsp
*hdsp
, int mode
)
2981 hdsp
->control_register
&= ~HDSP_RPM_Inp12
;
2984 hdsp
->control_register
|= HDSP_RPM_Inp12_Phon_6dB
;
2989 hdsp
->control_register
|= HDSP_RPM_Inp12_Phon_n6dB
;
2992 hdsp
->control_register
|= HDSP_RPM_Inp12_Line_0dB
;
2995 hdsp
->control_register
|= HDSP_RPM_Inp12_Line_n6dB
;
3001 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3006 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3008 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3012 if (!snd_hdsp_use_is_exclusive(hdsp
))
3014 val
= ucontrol
->value
.enumerated
.item
[0];
3019 spin_lock_irq(&hdsp
->lock
);
3020 if (val
!= hdsp_rpm_input12(hdsp
))
3021 change
= (hdsp_set_rpm_input12(hdsp
, val
) == 0) ? 1 : 0;
3024 spin_unlock_irq(&hdsp
->lock
);
3029 static int snd_hdsp_info_rpm_input(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
3031 static const char * const texts
[] = {
3032 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3035 return snd_ctl_enum_info(uinfo
, 1, 5, texts
);
3039 static int hdsp_rpm_input34(struct hdsp
*hdsp
)
3041 switch (hdsp
->control_register
& HDSP_RPM_Inp34
) {
3042 case HDSP_RPM_Inp34_Phon_6dB
:
3044 case HDSP_RPM_Inp34_Phon_n6dB
:
3046 case HDSP_RPM_Inp34_Line_0dB
:
3048 case HDSP_RPM_Inp34_Line_n6dB
:
3055 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3057 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3059 ucontrol
->value
.enumerated
.item
[0] = hdsp_rpm_input34(hdsp
);
3064 static int hdsp_set_rpm_input34(struct hdsp
*hdsp
, int mode
)
3066 hdsp
->control_register
&= ~HDSP_RPM_Inp34
;
3069 hdsp
->control_register
|= HDSP_RPM_Inp34_Phon_6dB
;
3074 hdsp
->control_register
|= HDSP_RPM_Inp34_Phon_n6dB
;
3077 hdsp
->control_register
|= HDSP_RPM_Inp34_Line_0dB
;
3080 hdsp
->control_register
|= HDSP_RPM_Inp34_Line_n6dB
;
3086 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3091 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3093 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3097 if (!snd_hdsp_use_is_exclusive(hdsp
))
3099 val
= ucontrol
->value
.enumerated
.item
[0];
3104 spin_lock_irq(&hdsp
->lock
);
3105 if (val
!= hdsp_rpm_input34(hdsp
))
3106 change
= (hdsp_set_rpm_input34(hdsp
, val
) == 0) ? 1 : 0;
3109 spin_unlock_irq(&hdsp
->lock
);
3114 /* RPM Bypass switch */
3115 static int hdsp_rpm_bypass(struct hdsp
*hdsp
)
3117 return (hdsp
->control_register
& HDSP_RPM_Bypass
) ? 1 : 0;
3121 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3123 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3125 ucontrol
->value
.integer
.value
[0] = hdsp_rpm_bypass(hdsp
);
3130 static int hdsp_set_rpm_bypass(struct hdsp
*hdsp
, int on
)
3133 hdsp
->control_register
|= HDSP_RPM_Bypass
;
3135 hdsp
->control_register
&= ~HDSP_RPM_Bypass
;
3136 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3141 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3143 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3147 if (!snd_hdsp_use_is_exclusive(hdsp
))
3149 val
= ucontrol
->value
.integer
.value
[0] & 1;
3150 spin_lock_irq(&hdsp
->lock
);
3151 change
= (int)val
!= hdsp_rpm_bypass(hdsp
);
3152 hdsp_set_rpm_bypass(hdsp
, val
);
3153 spin_unlock_irq(&hdsp
->lock
);
3158 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
3160 static const char * const texts
[] = {"On", "Off"};
3162 return snd_ctl_enum_info(uinfo
, 1, 2, texts
);
3166 /* RPM Disconnect switch */
3167 static int hdsp_rpm_disconnect(struct hdsp
*hdsp
)
3169 return (hdsp
->control_register
& HDSP_RPM_Disconnect
) ? 1 : 0;
3173 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3175 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3177 ucontrol
->value
.integer
.value
[0] = hdsp_rpm_disconnect(hdsp
);
3182 static int hdsp_set_rpm_disconnect(struct hdsp
*hdsp
, int on
)
3185 hdsp
->control_register
|= HDSP_RPM_Disconnect
;
3187 hdsp
->control_register
&= ~HDSP_RPM_Disconnect
;
3188 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3193 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
3195 struct hdsp
*hdsp
= snd_kcontrol_chip(kcontrol
);
3199 if (!snd_hdsp_use_is_exclusive(hdsp
))
3201 val
= ucontrol
->value
.integer
.value
[0] & 1;
3202 spin_lock_irq(&hdsp
->lock
);
3203 change
= (int)val
!= hdsp_rpm_disconnect(hdsp
);
3204 hdsp_set_rpm_disconnect(hdsp
, val
);
3205 spin_unlock_irq(&hdsp
->lock
);
3209 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
3211 static const char * const texts
[] = {"On", "Off"};
3213 return snd_ctl_enum_info(uinfo
, 1, 2, texts
);
3216 static const struct snd_kcontrol_new snd_hdsp_rpm_controls
[] = {
3218 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
3219 .name
= "RPM Bypass",
3220 .get
= snd_hdsp_get_rpm_bypass
,
3221 .put
= snd_hdsp_put_rpm_bypass
,
3222 .info
= snd_hdsp_info_rpm_bypass
3225 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
3226 .name
= "RPM Disconnect",
3227 .get
= snd_hdsp_get_rpm_disconnect
,
3228 .put
= snd_hdsp_put_rpm_disconnect
,
3229 .info
= snd_hdsp_info_rpm_disconnect
3232 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
3233 .name
= "Input 1/2",
3234 .get
= snd_hdsp_get_rpm_input12
,
3235 .put
= snd_hdsp_put_rpm_input12
,
3236 .info
= snd_hdsp_info_rpm_input
3239 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
3240 .name
= "Input 3/4",
3241 .get
= snd_hdsp_get_rpm_input34
,
3242 .put
= snd_hdsp_put_rpm_input34
,
3243 .info
= snd_hdsp_info_rpm_input
3245 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3246 HDSP_MIXER("Mixer", 0)
3249 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb
=
3250 HDSP_TOGGLE_SETTING("Analog Extension Board",
3251 HDSP_AnalogExtensionBoard
);
3252 static struct snd_kcontrol_new snd_hdsp_adat_sync_check
= HDSP_ADAT_SYNC_CHECK
;
3255 static bool hdsp_loopback_get(struct hdsp
*const hdsp
, const u8 channel
)
3257 return hdsp
->io_loopback
& (1 << channel
);
3260 static int hdsp_loopback_set(struct hdsp
*const hdsp
, const u8 channel
, const bool enable
)
3262 if (hdsp_loopback_get(hdsp
, channel
) == enable
)
3265 hdsp
->io_loopback
^= (1 << channel
);
3267 hdsp_write(hdsp
, HDSP_inputEnable
+ (4 * (hdsp
->max_channels
+ channel
)), enable
);
3272 static int snd_hdsp_loopback_get(struct snd_kcontrol
*const kcontrol
,
3273 struct snd_ctl_elem_value
*const ucontrol
)
3275 struct hdsp
*const hdsp
= snd_kcontrol_chip(kcontrol
);
3276 const u8 channel
= snd_ctl_get_ioff(kcontrol
, &ucontrol
->id
);
3278 if (channel
>= hdsp
->max_channels
)
3281 ucontrol
->value
.integer
.value
[0] = hdsp_loopback_get(hdsp
, channel
);
3286 static int snd_hdsp_loopback_put(struct snd_kcontrol
*const kcontrol
,
3287 struct snd_ctl_elem_value
*const ucontrol
)
3289 struct hdsp
*const hdsp
= snd_kcontrol_chip(kcontrol
);
3290 const u8 channel
= snd_ctl_get_ioff(kcontrol
, &ucontrol
->id
);
3291 const bool enable
= ucontrol
->value
.integer
.value
[0] & 1;
3293 if (channel
>= hdsp
->max_channels
)
3296 return hdsp_loopback_set(hdsp
, channel
, enable
);
3299 static struct snd_kcontrol_new snd_hdsp_loopback_control
= {
3300 .iface
= SNDRV_CTL_ELEM_IFACE_HWDEP
,
3301 .name
= "Output Loopback",
3302 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
,
3303 .info
= snd_ctl_boolean_mono_info
,
3304 .get
= snd_hdsp_loopback_get
,
3305 .put
= snd_hdsp_loopback_put
3308 static int snd_hdsp_create_controls(struct snd_card
*card
, struct hdsp
*hdsp
)
3312 struct snd_kcontrol
*kctl
;
3314 if (hdsp
->io_type
== RPM
) {
3315 /* RPM Bypass, Disconnect and Input switches */
3316 for (idx
= 0; idx
< ARRAY_SIZE(snd_hdsp_rpm_controls
); idx
++) {
3317 err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_hdsp_rpm_controls
[idx
], hdsp
));
3324 for (idx
= 0; idx
< ARRAY_SIZE(snd_hdsp_controls
); idx
++) {
3325 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_hdsp_controls
[idx
], hdsp
))) < 0)
3327 if (idx
== 1) /* IEC958 (S/PDIF) Stream */
3328 hdsp
->spdif_ctl
= kctl
;
3331 /* ADAT SyncCheck status */
3332 snd_hdsp_adat_sync_check
.name
= "ADAT Lock Status";
3333 snd_hdsp_adat_sync_check
.index
= 1;
3334 if ((err
= snd_ctl_add (card
, kctl
= snd_ctl_new1(&snd_hdsp_adat_sync_check
, hdsp
))))
3336 if (hdsp
->io_type
== Digiface
|| hdsp
->io_type
== H9652
) {
3337 for (idx
= 1; idx
< 3; ++idx
) {
3338 snd_hdsp_adat_sync_check
.index
= idx
+1;
3339 if ((err
= snd_ctl_add (card
, kctl
= snd_ctl_new1(&snd_hdsp_adat_sync_check
, hdsp
))))
3344 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3345 if (hdsp
->io_type
== H9632
) {
3346 for (idx
= 0; idx
< ARRAY_SIZE(snd_hdsp_9632_controls
); idx
++) {
3347 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_hdsp_9632_controls
[idx
], hdsp
))) < 0)
3352 /* Output loopback controls for H9632 cards */
3353 if (hdsp
->io_type
== H9632
) {
3354 snd_hdsp_loopback_control
.count
= hdsp
->max_channels
;
3355 kctl
= snd_ctl_new1(&snd_hdsp_loopback_control
, hdsp
);
3358 err
= snd_ctl_add(card
, kctl
);
3363 /* AEB control for H96xx card */
3364 if (hdsp
->io_type
== H9632
|| hdsp
->io_type
== H9652
) {
3365 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_hdsp_96xx_aeb
, hdsp
))) < 0)
3372 /*------------------------------------------------------------
3374 ------------------------------------------------------------*/
3377 snd_hdsp_proc_read(struct snd_info_entry
*entry
, struct snd_info_buffer
*buffer
)
3379 struct hdsp
*hdsp
= entry
->private_data
;
3380 unsigned int status
;
3381 unsigned int status2
;
3382 char *pref_sync_ref
;
3384 char *system_clock_mode
;
3388 status
= hdsp_read(hdsp
, HDSP_statusRegister
);
3389 status2
= hdsp_read(hdsp
, HDSP_status2Register
);
3391 snd_iprintf(buffer
, "%s (Card #%d)\n", hdsp
->card_name
,
3392 hdsp
->card
->number
+ 1);
3393 snd_iprintf(buffer
, "Buffers: capture %p playback %p\n",
3394 hdsp
->capture_buffer
, hdsp
->playback_buffer
);
3395 snd_iprintf(buffer
, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3396 hdsp
->irq
, hdsp
->port
, (unsigned long)hdsp
->iobase
);
3397 snd_iprintf(buffer
, "Control register: 0x%x\n", hdsp
->control_register
);
3398 snd_iprintf(buffer
, "Control2 register: 0x%x\n",
3399 hdsp
->control2_register
);
3400 snd_iprintf(buffer
, "Status register: 0x%x\n", status
);
3401 snd_iprintf(buffer
, "Status2 register: 0x%x\n", status2
);
3403 if (hdsp_check_for_iobox(hdsp
)) {
3404 snd_iprintf(buffer
, "No I/O box connected.\n"
3405 "Please connect one and upload firmware.\n");
3409 if (hdsp_check_for_firmware(hdsp
, 0)) {
3410 if (hdsp
->state
& HDSP_FirmwareCached
) {
3411 if (snd_hdsp_load_firmware_from_cache(hdsp
) != 0) {
3412 snd_iprintf(buffer
, "Firmware loading from "
3414 "please upload manually.\n");
3420 err
= hdsp_request_fw_loader(hdsp
);
3423 "No firmware loaded nor cached, "
3424 "please upload firmware.\n");
3430 snd_iprintf(buffer
, "FIFO status: %d\n", hdsp_read(hdsp
, HDSP_fifoStatus
) & 0xff);
3431 snd_iprintf(buffer
, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp
, HDSP_midiStatusOut0
));
3432 snd_iprintf(buffer
, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp
, HDSP_midiStatusIn0
));
3433 snd_iprintf(buffer
, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp
, HDSP_midiStatusOut1
));
3434 snd_iprintf(buffer
, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp
, HDSP_midiStatusIn1
));
3435 snd_iprintf(buffer
, "Use Midi Tasklet: %s\n", hdsp
->use_midi_work
? "on" : "off");
3437 snd_iprintf(buffer
, "\n");
3439 x
= 1 << (6 + hdsp_decode_latency(hdsp
->control_register
& HDSP_LatencyMask
));
3441 snd_iprintf(buffer
, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x
, (unsigned long) hdsp
->period_bytes
);
3442 snd_iprintf(buffer
, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp
));
3443 snd_iprintf(buffer
, "Precise pointer: %s\n", hdsp
->precise_ptr
? "on" : "off");
3444 snd_iprintf(buffer
, "Line out: %s\n", (hdsp
->control_register
& HDSP_LineOut
) ? "on" : "off");
3446 snd_iprintf(buffer
, "Firmware version: %d\n", (status2
&HDSP_version0
)|(status2
&HDSP_version1
)<<1|(status2
&HDSP_version2
)<<2);
3448 snd_iprintf(buffer
, "\n");
3450 switch (hdsp_clock_source(hdsp
)) {
3451 case HDSP_CLOCK_SOURCE_AUTOSYNC
:
3452 clock_source
= "AutoSync";
3454 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ
:
3455 clock_source
= "Internal 32 kHz";
3457 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ
:
3458 clock_source
= "Internal 44.1 kHz";
3460 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ
:
3461 clock_source
= "Internal 48 kHz";
3463 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ
:
3464 clock_source
= "Internal 64 kHz";
3466 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ
:
3467 clock_source
= "Internal 88.2 kHz";
3469 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ
:
3470 clock_source
= "Internal 96 kHz";
3472 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ
:
3473 clock_source
= "Internal 128 kHz";
3475 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ
:
3476 clock_source
= "Internal 176.4 kHz";
3478 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ
:
3479 clock_source
= "Internal 192 kHz";
3482 clock_source
= "Error";
3484 snd_iprintf (buffer
, "Sample Clock Source: %s\n", clock_source
);
3486 if (hdsp_system_clock_mode(hdsp
))
3487 system_clock_mode
= "Slave";
3489 system_clock_mode
= "Master";
3491 switch (hdsp_pref_sync_ref (hdsp
)) {
3492 case HDSP_SYNC_FROM_WORD
:
3493 pref_sync_ref
= "Word Clock";
3495 case HDSP_SYNC_FROM_ADAT_SYNC
:
3496 pref_sync_ref
= "ADAT Sync";
3498 case HDSP_SYNC_FROM_SPDIF
:
3499 pref_sync_ref
= "SPDIF";
3501 case HDSP_SYNC_FROM_ADAT1
:
3502 pref_sync_ref
= "ADAT1";
3504 case HDSP_SYNC_FROM_ADAT2
:
3505 pref_sync_ref
= "ADAT2";
3507 case HDSP_SYNC_FROM_ADAT3
:
3508 pref_sync_ref
= "ADAT3";
3511 pref_sync_ref
= "Word Clock";
3514 snd_iprintf (buffer
, "Preferred Sync Reference: %s\n", pref_sync_ref
);
3516 switch (hdsp_autosync_ref (hdsp
)) {
3517 case HDSP_AUTOSYNC_FROM_WORD
:
3518 autosync_ref
= "Word Clock";
3520 case HDSP_AUTOSYNC_FROM_ADAT_SYNC
:
3521 autosync_ref
= "ADAT Sync";
3523 case HDSP_AUTOSYNC_FROM_SPDIF
:
3524 autosync_ref
= "SPDIF";
3526 case HDSP_AUTOSYNC_FROM_NONE
:
3527 autosync_ref
= "None";
3529 case HDSP_AUTOSYNC_FROM_ADAT1
:
3530 autosync_ref
= "ADAT1";
3532 case HDSP_AUTOSYNC_FROM_ADAT2
:
3533 autosync_ref
= "ADAT2";
3535 case HDSP_AUTOSYNC_FROM_ADAT3
:
3536 autosync_ref
= "ADAT3";
3539 autosync_ref
= "---";
3542 snd_iprintf (buffer
, "AutoSync Reference: %s\n", autosync_ref
);
3544 snd_iprintf (buffer
, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp
));
3546 snd_iprintf (buffer
, "System Clock Mode: %s\n", system_clock_mode
);
3548 snd_iprintf (buffer
, "System Clock Frequency: %d\n", hdsp
->system_sample_rate
);
3549 snd_iprintf (buffer
, "System Clock Locked: %s\n", hdsp
->clock_source_locked
? "Yes" : "No");
3551 snd_iprintf(buffer
, "\n");
3553 if (hdsp
->io_type
!= RPM
) {
3554 switch (hdsp_spdif_in(hdsp
)) {
3555 case HDSP_SPDIFIN_OPTICAL
:
3556 snd_iprintf(buffer
, "IEC958 input: Optical\n");
3558 case HDSP_SPDIFIN_COAXIAL
:
3559 snd_iprintf(buffer
, "IEC958 input: Coaxial\n");
3561 case HDSP_SPDIFIN_INTERNAL
:
3562 snd_iprintf(buffer
, "IEC958 input: Internal\n");
3564 case HDSP_SPDIFIN_AES
:
3565 snd_iprintf(buffer
, "IEC958 input: AES\n");
3568 snd_iprintf(buffer
, "IEC958 input: ???\n");
3573 if (RPM
== hdsp
->io_type
) {
3574 if (hdsp
->control_register
& HDSP_RPM_Bypass
)
3575 snd_iprintf(buffer
, "RPM Bypass: disabled\n");
3577 snd_iprintf(buffer
, "RPM Bypass: enabled\n");
3578 if (hdsp
->control_register
& HDSP_RPM_Disconnect
)
3579 snd_iprintf(buffer
, "RPM disconnected\n");
3581 snd_iprintf(buffer
, "RPM connected\n");
3583 switch (hdsp
->control_register
& HDSP_RPM_Inp12
) {
3584 case HDSP_RPM_Inp12_Phon_6dB
:
3585 snd_iprintf(buffer
, "Input 1/2: Phono, 6dB\n");
3587 case HDSP_RPM_Inp12_Phon_0dB
:
3588 snd_iprintf(buffer
, "Input 1/2: Phono, 0dB\n");
3590 case HDSP_RPM_Inp12_Phon_n6dB
:
3591 snd_iprintf(buffer
, "Input 1/2: Phono, -6dB\n");
3593 case HDSP_RPM_Inp12_Line_0dB
:
3594 snd_iprintf(buffer
, "Input 1/2: Line, 0dB\n");
3596 case HDSP_RPM_Inp12_Line_n6dB
:
3597 snd_iprintf(buffer
, "Input 1/2: Line, -6dB\n");
3600 snd_iprintf(buffer
, "Input 1/2: ???\n");
3603 switch (hdsp
->control_register
& HDSP_RPM_Inp34
) {
3604 case HDSP_RPM_Inp34_Phon_6dB
:
3605 snd_iprintf(buffer
, "Input 3/4: Phono, 6dB\n");
3607 case HDSP_RPM_Inp34_Phon_0dB
:
3608 snd_iprintf(buffer
, "Input 3/4: Phono, 0dB\n");
3610 case HDSP_RPM_Inp34_Phon_n6dB
:
3611 snd_iprintf(buffer
, "Input 3/4: Phono, -6dB\n");
3613 case HDSP_RPM_Inp34_Line_0dB
:
3614 snd_iprintf(buffer
, "Input 3/4: Line, 0dB\n");
3616 case HDSP_RPM_Inp34_Line_n6dB
:
3617 snd_iprintf(buffer
, "Input 3/4: Line, -6dB\n");
3620 snd_iprintf(buffer
, "Input 3/4: ???\n");
3624 if (hdsp
->control_register
& HDSP_SPDIFOpticalOut
)
3625 snd_iprintf(buffer
, "IEC958 output: Coaxial & ADAT1\n");
3627 snd_iprintf(buffer
, "IEC958 output: Coaxial only\n");
3629 if (hdsp
->control_register
& HDSP_SPDIFProfessional
)
3630 snd_iprintf(buffer
, "IEC958 quality: Professional\n");
3632 snd_iprintf(buffer
, "IEC958 quality: Consumer\n");
3634 if (hdsp
->control_register
& HDSP_SPDIFEmphasis
)
3635 snd_iprintf(buffer
, "IEC958 emphasis: on\n");
3637 snd_iprintf(buffer
, "IEC958 emphasis: off\n");
3639 if (hdsp
->control_register
& HDSP_SPDIFNonAudio
)
3640 snd_iprintf(buffer
, "IEC958 NonAudio: on\n");
3642 snd_iprintf(buffer
, "IEC958 NonAudio: off\n");
3643 x
= hdsp_spdif_sample_rate(hdsp
);
3645 snd_iprintf(buffer
, "IEC958 sample rate: %d\n", x
);
3647 snd_iprintf(buffer
, "IEC958 sample rate: Error flag set\n");
3649 snd_iprintf(buffer
, "\n");
3652 x
= status
& HDSP_Sync0
;
3653 if (status
& HDSP_Lock0
)
3654 snd_iprintf(buffer
, "ADAT1: %s\n", x
? "Sync" : "Lock");
3656 snd_iprintf(buffer
, "ADAT1: No Lock\n");
3658 switch (hdsp
->io_type
) {
3661 x
= status
& HDSP_Sync1
;
3662 if (status
& HDSP_Lock1
)
3663 snd_iprintf(buffer
, "ADAT2: %s\n", x
? "Sync" : "Lock");
3665 snd_iprintf(buffer
, "ADAT2: No Lock\n");
3666 x
= status
& HDSP_Sync2
;
3667 if (status
& HDSP_Lock2
)
3668 snd_iprintf(buffer
, "ADAT3: %s\n", x
? "Sync" : "Lock");
3670 snd_iprintf(buffer
, "ADAT3: No Lock\n");
3677 x
= status
& HDSP_SPDIFSync
;
3678 if (status
& HDSP_SPDIFErrorFlag
)
3679 snd_iprintf (buffer
, "SPDIF: No Lock\n");
3681 snd_iprintf (buffer
, "SPDIF: %s\n", x
? "Sync" : "Lock");
3683 x
= status2
& HDSP_wc_sync
;
3684 if (status2
& HDSP_wc_lock
)
3685 snd_iprintf (buffer
, "Word Clock: %s\n", x
? "Sync" : "Lock");
3687 snd_iprintf (buffer
, "Word Clock: No Lock\n");
3689 x
= status
& HDSP_TimecodeSync
;
3690 if (status
& HDSP_TimecodeLock
)
3691 snd_iprintf(buffer
, "ADAT Sync: %s\n", x
? "Sync" : "Lock");
3693 snd_iprintf(buffer
, "ADAT Sync: No Lock\n");
3695 snd_iprintf(buffer
, "\n");
3697 /* Informations about H9632 specific controls */
3698 if (hdsp
->io_type
== H9632
) {
3701 switch (hdsp_ad_gain(hdsp
)) {
3712 snd_iprintf(buffer
, "AD Gain : %s\n", tmp
);
3714 switch (hdsp_da_gain(hdsp
)) {
3725 snd_iprintf(buffer
, "DA Gain : %s\n", tmp
);
3727 switch (hdsp_phone_gain(hdsp
)) {
3738 snd_iprintf(buffer
, "Phones Gain : %s\n", tmp
);
3740 snd_iprintf(buffer
, "XLR Breakout Cable : %s\n",
3741 hdsp_toggle_setting(hdsp
, HDSP_XLRBreakoutCable
) ?
3744 if (hdsp
->control_register
& HDSP_AnalogExtensionBoard
)
3745 snd_iprintf(buffer
, "AEB : on (ADAT1 internal)\n");
3747 snd_iprintf(buffer
, "AEB : off (ADAT1 external)\n");
3748 snd_iprintf(buffer
, "\n");
3753 static void snd_hdsp_proc_init(struct hdsp
*hdsp
)
3755 snd_card_ro_proc_new(hdsp
->card
, "hdsp", hdsp
, snd_hdsp_proc_read
);
3758 static void snd_hdsp_free_buffers(struct hdsp
*hdsp
)
3760 snd_hammerfall_free_buffer(&hdsp
->capture_dma_buf
, hdsp
->pci
);
3761 snd_hammerfall_free_buffer(&hdsp
->playback_dma_buf
, hdsp
->pci
);
3764 static int snd_hdsp_initialize_memory(struct hdsp
*hdsp
)
3766 unsigned long pb_bus
, cb_bus
;
3768 if (snd_hammerfall_get_buffer(hdsp
->pci
, &hdsp
->capture_dma_buf
, HDSP_DMA_AREA_BYTES
) < 0 ||
3769 snd_hammerfall_get_buffer(hdsp
->pci
, &hdsp
->playback_dma_buf
, HDSP_DMA_AREA_BYTES
) < 0) {
3770 if (hdsp
->capture_dma_buf
.area
)
3771 snd_dma_free_pages(&hdsp
->capture_dma_buf
);
3772 dev_err(hdsp
->card
->dev
,
3773 "%s: no buffers available\n", hdsp
->card_name
);
3777 /* Align to bus-space 64K boundary */
3779 cb_bus
= ALIGN(hdsp
->capture_dma_buf
.addr
, 0x10000ul
);
3780 pb_bus
= ALIGN(hdsp
->playback_dma_buf
.addr
, 0x10000ul
);
3782 /* Tell the card where it is */
3784 hdsp_write(hdsp
, HDSP_inputBufferAddress
, cb_bus
);
3785 hdsp_write(hdsp
, HDSP_outputBufferAddress
, pb_bus
);
3787 hdsp
->capture_buffer
= hdsp
->capture_dma_buf
.area
+ (cb_bus
- hdsp
->capture_dma_buf
.addr
);
3788 hdsp
->playback_buffer
= hdsp
->playback_dma_buf
.area
+ (pb_bus
- hdsp
->playback_dma_buf
.addr
);
3793 static int snd_hdsp_set_defaults(struct hdsp
*hdsp
)
3797 /* ASSUMPTION: hdsp->lock is either held, or
3798 there is no need to hold it (e.g. during module
3804 SPDIF Input via Coax
3806 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3807 which implies 2 4096 sample, 32Kbyte periods).
3811 hdsp
->control_register
= HDSP_ClockModeMaster
|
3812 HDSP_SPDIFInputCoaxial
|
3813 hdsp_encode_latency(7) |
3817 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3819 #ifdef SNDRV_BIG_ENDIAN
3820 hdsp
->control2_register
= HDSP_BIGENDIAN_MODE
;
3822 hdsp
->control2_register
= 0;
3824 if (hdsp
->io_type
== H9652
)
3825 snd_hdsp_9652_enable_mixer (hdsp
);
3827 hdsp_write (hdsp
, HDSP_control2Reg
, hdsp
->control2_register
);
3829 hdsp_reset_hw_pointer(hdsp
);
3830 hdsp_compute_period_size(hdsp
);
3832 /* silence everything */
3834 for (i
= 0; i
< HDSP_MATRIX_MIXER_SIZE
; ++i
)
3835 hdsp
->mixer_matrix
[i
] = MINUS_INFINITY_GAIN
;
3837 for (i
= 0; i
< ((hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
) ? 1352 : HDSP_MATRIX_MIXER_SIZE
); ++i
) {
3838 if (hdsp_write_gain (hdsp
, i
, MINUS_INFINITY_GAIN
))
3842 /* H9632 specific defaults */
3843 if (hdsp
->io_type
== H9632
) {
3844 hdsp
->control_register
|= (HDSP_DAGainPlus4dBu
| HDSP_ADGainPlus4dBu
| HDSP_PhoneGain0dB
);
3845 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3848 /* set a default rate so that the channel map is set up.
3851 hdsp_set_rate(hdsp
, 48000, 1);
3856 static void hdsp_midi_work(struct work_struct
*work
)
3858 struct hdsp
*hdsp
= container_of(work
, struct hdsp
, midi_work
);
3860 if (hdsp
->midi
[0].pending
)
3861 snd_hdsp_midi_input_read (&hdsp
->midi
[0]);
3862 if (hdsp
->midi
[1].pending
)
3863 snd_hdsp_midi_input_read (&hdsp
->midi
[1]);
3866 static irqreturn_t
snd_hdsp_interrupt(int irq
, void *dev_id
)
3868 struct hdsp
*hdsp
= (struct hdsp
*) dev_id
;
3869 unsigned int status
;
3873 unsigned int midi0status
;
3874 unsigned int midi1status
;
3877 status
= hdsp_read(hdsp
, HDSP_statusRegister
);
3879 audio
= status
& HDSP_audioIRQPending
;
3880 midi0
= status
& HDSP_midi0IRQPending
;
3881 midi1
= status
& HDSP_midi1IRQPending
;
3883 if (!audio
&& !midi0
&& !midi1
)
3886 hdsp_write(hdsp
, HDSP_interruptConfirmation
, 0);
3888 midi0status
= hdsp_read (hdsp
, HDSP_midiStatusIn0
) & 0xff;
3889 midi1status
= hdsp_read (hdsp
, HDSP_midiStatusIn1
) & 0xff;
3891 if (!(hdsp
->state
& HDSP_InitializationComplete
))
3895 if (hdsp
->capture_substream
)
3896 snd_pcm_period_elapsed(hdsp
->pcm
->streams
[SNDRV_PCM_STREAM_CAPTURE
].substream
);
3898 if (hdsp
->playback_substream
)
3899 snd_pcm_period_elapsed(hdsp
->pcm
->streams
[SNDRV_PCM_STREAM_PLAYBACK
].substream
);
3902 if (midi0
&& midi0status
) {
3903 if (hdsp
->use_midi_work
) {
3904 /* we disable interrupts for this input until processing is done */
3905 hdsp
->control_register
&= ~HDSP_Midi0InterruptEnable
;
3906 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3907 hdsp
->midi
[0].pending
= 1;
3910 snd_hdsp_midi_input_read (&hdsp
->midi
[0]);
3913 if (hdsp
->io_type
!= Multiface
&& hdsp
->io_type
!= RPM
&& hdsp
->io_type
!= H9632
&& midi1
&& midi1status
) {
3914 if (hdsp
->use_midi_work
) {
3915 /* we disable interrupts for this input until processing is done */
3916 hdsp
->control_register
&= ~HDSP_Midi1InterruptEnable
;
3917 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
3918 hdsp
->midi
[1].pending
= 1;
3921 snd_hdsp_midi_input_read (&hdsp
->midi
[1]);
3924 if (hdsp
->use_midi_work
&& schedule
)
3925 queue_work(system_highpri_wq
, &hdsp
->midi_work
);
3929 static snd_pcm_uframes_t
snd_hdsp_hw_pointer(struct snd_pcm_substream
*substream
)
3931 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
3932 return hdsp_hw_pointer(hdsp
);
3935 static char *hdsp_channel_buffer_location(struct hdsp
*hdsp
,
3942 if (snd_BUG_ON(channel
< 0 || channel
>= hdsp
->max_channels
))
3945 if ((mapped_channel
= hdsp
->channel_map
[channel
]) < 0)
3948 if (stream
== SNDRV_PCM_STREAM_CAPTURE
)
3949 return hdsp
->capture_buffer
+ (mapped_channel
* HDSP_CHANNEL_BUFFER_BYTES
);
3951 return hdsp
->playback_buffer
+ (mapped_channel
* HDSP_CHANNEL_BUFFER_BYTES
);
3954 static int snd_hdsp_playback_copy(struct snd_pcm_substream
*substream
,
3955 int channel
, unsigned long pos
,
3956 void __user
*src
, unsigned long count
)
3958 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
3961 if (snd_BUG_ON(pos
+ count
> HDSP_CHANNEL_BUFFER_BYTES
))
3964 channel_buf
= hdsp_channel_buffer_location (hdsp
, substream
->pstr
->stream
, channel
);
3965 if (snd_BUG_ON(!channel_buf
))
3967 if (copy_from_user(channel_buf
+ pos
, src
, count
))
3972 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream
*substream
,
3973 int channel
, unsigned long pos
,
3974 void *src
, unsigned long count
)
3976 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
3979 channel_buf
= hdsp_channel_buffer_location(hdsp
, substream
->pstr
->stream
, channel
);
3980 if (snd_BUG_ON(!channel_buf
))
3982 memcpy(channel_buf
+ pos
, src
, count
);
3986 static int snd_hdsp_capture_copy(struct snd_pcm_substream
*substream
,
3987 int channel
, unsigned long pos
,
3988 void __user
*dst
, unsigned long count
)
3990 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
3993 if (snd_BUG_ON(pos
+ count
> HDSP_CHANNEL_BUFFER_BYTES
))
3996 channel_buf
= hdsp_channel_buffer_location (hdsp
, substream
->pstr
->stream
, channel
);
3997 if (snd_BUG_ON(!channel_buf
))
3999 if (copy_to_user(dst
, channel_buf
+ pos
, count
))
4004 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream
*substream
,
4005 int channel
, unsigned long pos
,
4006 void *dst
, unsigned long count
)
4008 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4011 channel_buf
= hdsp_channel_buffer_location(hdsp
, substream
->pstr
->stream
, channel
);
4012 if (snd_BUG_ON(!channel_buf
))
4014 memcpy(dst
, channel_buf
+ pos
, count
);
4018 static int snd_hdsp_hw_silence(struct snd_pcm_substream
*substream
,
4019 int channel
, unsigned long pos
,
4020 unsigned long count
)
4022 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4025 channel_buf
= hdsp_channel_buffer_location (hdsp
, substream
->pstr
->stream
, channel
);
4026 if (snd_BUG_ON(!channel_buf
))
4028 memset(channel_buf
+ pos
, 0, count
);
4032 static int snd_hdsp_reset(struct snd_pcm_substream
*substream
)
4034 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
4035 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4036 struct snd_pcm_substream
*other
;
4037 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
4038 other
= hdsp
->capture_substream
;
4040 other
= hdsp
->playback_substream
;
4042 runtime
->status
->hw_ptr
= hdsp_hw_pointer(hdsp
);
4044 runtime
->status
->hw_ptr
= 0;
4046 struct snd_pcm_substream
*s
;
4047 struct snd_pcm_runtime
*oruntime
= other
->runtime
;
4048 snd_pcm_group_for_each_entry(s
, substream
) {
4050 oruntime
->status
->hw_ptr
= runtime
->status
->hw_ptr
;
4058 static int snd_hdsp_hw_params(struct snd_pcm_substream
*substream
,
4059 struct snd_pcm_hw_params
*params
)
4061 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4066 if (hdsp_check_for_iobox (hdsp
))
4069 if (hdsp_check_for_firmware(hdsp
, 1))
4072 spin_lock_irq(&hdsp
->lock
);
4074 if (substream
->pstr
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
4075 hdsp
->control_register
&= ~(HDSP_SPDIFProfessional
| HDSP_SPDIFNonAudio
| HDSP_SPDIFEmphasis
);
4076 hdsp_write(hdsp
, HDSP_controlRegister
, hdsp
->control_register
|= hdsp
->creg_spdif_stream
);
4077 this_pid
= hdsp
->playback_pid
;
4078 other_pid
= hdsp
->capture_pid
;
4080 this_pid
= hdsp
->capture_pid
;
4081 other_pid
= hdsp
->playback_pid
;
4084 if ((other_pid
> 0) && (this_pid
!= other_pid
)) {
4086 /* The other stream is open, and not by the same
4087 task as this one. Make sure that the parameters
4088 that matter are the same.
4091 if (params_rate(params
) != hdsp
->system_sample_rate
) {
4092 spin_unlock_irq(&hdsp
->lock
);
4093 _snd_pcm_hw_param_setempty(params
, SNDRV_PCM_HW_PARAM_RATE
);
4097 if (params_period_size(params
) != hdsp
->period_bytes
/ 4) {
4098 spin_unlock_irq(&hdsp
->lock
);
4099 _snd_pcm_hw_param_setempty(params
, SNDRV_PCM_HW_PARAM_PERIOD_SIZE
);
4105 spin_unlock_irq(&hdsp
->lock
);
4109 spin_unlock_irq(&hdsp
->lock
);
4112 /* how to make sure that the rate matches an externally-set one ?
4115 spin_lock_irq(&hdsp
->lock
);
4116 if (! hdsp
->clock_source_locked
) {
4117 if ((err
= hdsp_set_rate(hdsp
, params_rate(params
), 0)) < 0) {
4118 spin_unlock_irq(&hdsp
->lock
);
4119 _snd_pcm_hw_param_setempty(params
, SNDRV_PCM_HW_PARAM_RATE
);
4123 spin_unlock_irq(&hdsp
->lock
);
4125 if ((err
= hdsp_set_interrupt_interval(hdsp
, params_period_size(params
))) < 0) {
4126 _snd_pcm_hw_param_setempty(params
, SNDRV_PCM_HW_PARAM_PERIOD_SIZE
);
4133 static int snd_hdsp_channel_info(struct snd_pcm_substream
*substream
,
4134 struct snd_pcm_channel_info
*info
)
4136 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4137 unsigned int channel
= info
->channel
;
4139 if (snd_BUG_ON(channel
>= hdsp
->max_channels
))
4141 channel
= array_index_nospec(channel
, hdsp
->max_channels
);
4143 if (hdsp
->channel_map
[channel
] < 0)
4146 info
->offset
= hdsp
->channel_map
[channel
] * HDSP_CHANNEL_BUFFER_BYTES
;
4152 static int snd_hdsp_ioctl(struct snd_pcm_substream
*substream
,
4153 unsigned int cmd
, void *arg
)
4156 case SNDRV_PCM_IOCTL1_RESET
:
4157 return snd_hdsp_reset(substream
);
4158 case SNDRV_PCM_IOCTL1_CHANNEL_INFO
:
4159 return snd_hdsp_channel_info(substream
, arg
);
4164 return snd_pcm_lib_ioctl(substream
, cmd
, arg
);
4167 static int snd_hdsp_trigger(struct snd_pcm_substream
*substream
, int cmd
)
4169 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4170 struct snd_pcm_substream
*other
;
4173 if (hdsp_check_for_iobox (hdsp
))
4176 if (hdsp_check_for_firmware(hdsp
, 0)) /* no auto-loading in trigger */
4179 spin_lock(&hdsp
->lock
);
4180 running
= hdsp
->running
;
4182 case SNDRV_PCM_TRIGGER_START
:
4183 running
|= 1 << substream
->stream
;
4185 case SNDRV_PCM_TRIGGER_STOP
:
4186 running
&= ~(1 << substream
->stream
);
4190 spin_unlock(&hdsp
->lock
);
4193 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
4194 other
= hdsp
->capture_substream
;
4196 other
= hdsp
->playback_substream
;
4199 struct snd_pcm_substream
*s
;
4200 snd_pcm_group_for_each_entry(s
, substream
) {
4202 snd_pcm_trigger_done(s
, substream
);
4203 if (cmd
== SNDRV_PCM_TRIGGER_START
)
4204 running
|= 1 << s
->stream
;
4206 running
&= ~(1 << s
->stream
);
4210 if (cmd
== SNDRV_PCM_TRIGGER_START
) {
4211 if (!(running
& (1 << SNDRV_PCM_STREAM_PLAYBACK
)) &&
4212 substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
4213 hdsp_silence_playback(hdsp
);
4216 substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
4217 hdsp_silence_playback(hdsp
);
4220 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
4221 hdsp_silence_playback(hdsp
);
4224 snd_pcm_trigger_done(substream
, substream
);
4225 if (!hdsp
->running
&& running
)
4226 hdsp_start_audio(hdsp
);
4227 else if (hdsp
->running
&& !running
)
4228 hdsp_stop_audio(hdsp
);
4229 hdsp
->running
= running
;
4230 spin_unlock(&hdsp
->lock
);
4235 static int snd_hdsp_prepare(struct snd_pcm_substream
*substream
)
4237 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4240 if (hdsp_check_for_iobox (hdsp
))
4243 if (hdsp_check_for_firmware(hdsp
, 1))
4246 spin_lock_irq(&hdsp
->lock
);
4248 hdsp_reset_hw_pointer(hdsp
);
4249 spin_unlock_irq(&hdsp
->lock
);
4253 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo
=
4255 .info
= (SNDRV_PCM_INFO_MMAP
|
4256 SNDRV_PCM_INFO_MMAP_VALID
|
4257 SNDRV_PCM_INFO_NONINTERLEAVED
|
4258 SNDRV_PCM_INFO_SYNC_START
|
4259 SNDRV_PCM_INFO_DOUBLE
),
4260 #ifdef SNDRV_BIG_ENDIAN
4261 .formats
= SNDRV_PCM_FMTBIT_S32_BE
,
4263 .formats
= SNDRV_PCM_FMTBIT_S32_LE
,
4265 .rates
= (SNDRV_PCM_RATE_32000
|
4266 SNDRV_PCM_RATE_44100
|
4267 SNDRV_PCM_RATE_48000
|
4268 SNDRV_PCM_RATE_64000
|
4269 SNDRV_PCM_RATE_88200
|
4270 SNDRV_PCM_RATE_96000
),
4274 .channels_max
= HDSP_MAX_CHANNELS
,
4275 .buffer_bytes_max
= HDSP_CHANNEL_BUFFER_BYTES
* HDSP_MAX_CHANNELS
,
4276 .period_bytes_min
= (64 * 4) * 10,
4277 .period_bytes_max
= (8192 * 4) * HDSP_MAX_CHANNELS
,
4283 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo
=
4285 .info
= (SNDRV_PCM_INFO_MMAP
|
4286 SNDRV_PCM_INFO_MMAP_VALID
|
4287 SNDRV_PCM_INFO_NONINTERLEAVED
|
4288 SNDRV_PCM_INFO_SYNC_START
),
4289 #ifdef SNDRV_BIG_ENDIAN
4290 .formats
= SNDRV_PCM_FMTBIT_S32_BE
,
4292 .formats
= SNDRV_PCM_FMTBIT_S32_LE
,
4294 .rates
= (SNDRV_PCM_RATE_32000
|
4295 SNDRV_PCM_RATE_44100
|
4296 SNDRV_PCM_RATE_48000
|
4297 SNDRV_PCM_RATE_64000
|
4298 SNDRV_PCM_RATE_88200
|
4299 SNDRV_PCM_RATE_96000
),
4303 .channels_max
= HDSP_MAX_CHANNELS
,
4304 .buffer_bytes_max
= HDSP_CHANNEL_BUFFER_BYTES
* HDSP_MAX_CHANNELS
,
4305 .period_bytes_min
= (64 * 4) * 10,
4306 .period_bytes_max
= (8192 * 4) * HDSP_MAX_CHANNELS
,
4312 static const unsigned int hdsp_period_sizes
[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4314 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes
= {
4315 .count
= ARRAY_SIZE(hdsp_period_sizes
),
4316 .list
= hdsp_period_sizes
,
4320 static const unsigned int hdsp_9632_sample_rates
[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4322 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates
= {
4323 .count
= ARRAY_SIZE(hdsp_9632_sample_rates
),
4324 .list
= hdsp_9632_sample_rates
,
4328 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params
*params
,
4329 struct snd_pcm_hw_rule
*rule
)
4331 struct hdsp
*hdsp
= rule
->private;
4332 struct snd_interval
*c
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
4333 if (hdsp
->io_type
== H9632
) {
4334 unsigned int list
[3];
4335 list
[0] = hdsp
->qs_in_channels
;
4336 list
[1] = hdsp
->ds_in_channels
;
4337 list
[2] = hdsp
->ss_in_channels
;
4338 return snd_interval_list(c
, 3, list
, 0);
4340 unsigned int list
[2];
4341 list
[0] = hdsp
->ds_in_channels
;
4342 list
[1] = hdsp
->ss_in_channels
;
4343 return snd_interval_list(c
, 2, list
, 0);
4347 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params
*params
,
4348 struct snd_pcm_hw_rule
*rule
)
4350 unsigned int list
[3];
4351 struct hdsp
*hdsp
= rule
->private;
4352 struct snd_interval
*c
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
4353 if (hdsp
->io_type
== H9632
) {
4354 list
[0] = hdsp
->qs_out_channels
;
4355 list
[1] = hdsp
->ds_out_channels
;
4356 list
[2] = hdsp
->ss_out_channels
;
4357 return snd_interval_list(c
, 3, list
, 0);
4359 list
[0] = hdsp
->ds_out_channels
;
4360 list
[1] = hdsp
->ss_out_channels
;
4362 return snd_interval_list(c
, 2, list
, 0);
4365 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params
*params
,
4366 struct snd_pcm_hw_rule
*rule
)
4368 struct hdsp
*hdsp
= rule
->private;
4369 struct snd_interval
*c
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
4370 struct snd_interval
*r
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
4371 if (r
->min
> 96000 && hdsp
->io_type
== H9632
) {
4372 struct snd_interval t
= {
4373 .min
= hdsp
->qs_in_channels
,
4374 .max
= hdsp
->qs_in_channels
,
4377 return snd_interval_refine(c
, &t
);
4378 } else if (r
->min
> 48000 && r
->max
<= 96000) {
4379 struct snd_interval t
= {
4380 .min
= hdsp
->ds_in_channels
,
4381 .max
= hdsp
->ds_in_channels
,
4384 return snd_interval_refine(c
, &t
);
4385 } else if (r
->max
< 64000) {
4386 struct snd_interval t
= {
4387 .min
= hdsp
->ss_in_channels
,
4388 .max
= hdsp
->ss_in_channels
,
4391 return snd_interval_refine(c
, &t
);
4396 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params
*params
,
4397 struct snd_pcm_hw_rule
*rule
)
4399 struct hdsp
*hdsp
= rule
->private;
4400 struct snd_interval
*c
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
4401 struct snd_interval
*r
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
4402 if (r
->min
> 96000 && hdsp
->io_type
== H9632
) {
4403 struct snd_interval t
= {
4404 .min
= hdsp
->qs_out_channels
,
4405 .max
= hdsp
->qs_out_channels
,
4408 return snd_interval_refine(c
, &t
);
4409 } else if (r
->min
> 48000 && r
->max
<= 96000) {
4410 struct snd_interval t
= {
4411 .min
= hdsp
->ds_out_channels
,
4412 .max
= hdsp
->ds_out_channels
,
4415 return snd_interval_refine(c
, &t
);
4416 } else if (r
->max
< 64000) {
4417 struct snd_interval t
= {
4418 .min
= hdsp
->ss_out_channels
,
4419 .max
= hdsp
->ss_out_channels
,
4422 return snd_interval_refine(c
, &t
);
4427 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params
*params
,
4428 struct snd_pcm_hw_rule
*rule
)
4430 struct hdsp
*hdsp
= rule
->private;
4431 struct snd_interval
*c
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
4432 struct snd_interval
*r
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
4433 if (c
->min
>= hdsp
->ss_out_channels
) {
4434 struct snd_interval t
= {
4439 return snd_interval_refine(r
, &t
);
4440 } else if (c
->max
<= hdsp
->qs_out_channels
&& hdsp
->io_type
== H9632
) {
4441 struct snd_interval t
= {
4446 return snd_interval_refine(r
, &t
);
4447 } else if (c
->max
<= hdsp
->ds_out_channels
) {
4448 struct snd_interval t
= {
4453 return snd_interval_refine(r
, &t
);
4458 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params
*params
,
4459 struct snd_pcm_hw_rule
*rule
)
4461 struct hdsp
*hdsp
= rule
->private;
4462 struct snd_interval
*c
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
4463 struct snd_interval
*r
= hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
4464 if (c
->min
>= hdsp
->ss_in_channels
) {
4465 struct snd_interval t
= {
4470 return snd_interval_refine(r
, &t
);
4471 } else if (c
->max
<= hdsp
->qs_in_channels
&& hdsp
->io_type
== H9632
) {
4472 struct snd_interval t
= {
4477 return snd_interval_refine(r
, &t
);
4478 } else if (c
->max
<= hdsp
->ds_in_channels
) {
4479 struct snd_interval t
= {
4484 return snd_interval_refine(r
, &t
);
4489 static int snd_hdsp_playback_open(struct snd_pcm_substream
*substream
)
4491 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4492 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
4494 if (hdsp_check_for_iobox (hdsp
))
4497 if (hdsp_check_for_firmware(hdsp
, 1))
4500 spin_lock_irq(&hdsp
->lock
);
4502 snd_pcm_set_sync(substream
);
4504 runtime
->hw
= snd_hdsp_playback_subinfo
;
4505 runtime
->dma_area
= hdsp
->playback_buffer
;
4506 runtime
->dma_bytes
= HDSP_DMA_AREA_BYTES
;
4508 hdsp
->playback_pid
= current
->pid
;
4509 hdsp
->playback_substream
= substream
;
4511 spin_unlock_irq(&hdsp
->lock
);
4513 snd_pcm_hw_constraint_msbits(runtime
, 0, 32, 24);
4514 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE
, &hdsp_hw_constraints_period_sizes
);
4515 if (hdsp
->clock_source_locked
) {
4516 runtime
->hw
.rate_min
= runtime
->hw
.rate_max
= hdsp
->system_sample_rate
;
4517 } else if (hdsp
->io_type
== H9632
) {
4518 runtime
->hw
.rate_max
= 192000;
4519 runtime
->hw
.rates
= SNDRV_PCM_RATE_KNOT
;
4520 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
, &hdsp_hw_constraints_9632_sample_rates
);
4522 if (hdsp
->io_type
== H9632
) {
4523 runtime
->hw
.channels_min
= hdsp
->qs_out_channels
;
4524 runtime
->hw
.channels_max
= hdsp
->ss_out_channels
;
4527 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
4528 snd_hdsp_hw_rule_out_channels
, hdsp
,
4529 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
4530 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
4531 snd_hdsp_hw_rule_out_channels_rate
, hdsp
,
4532 SNDRV_PCM_HW_PARAM_RATE
, -1);
4533 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
4534 snd_hdsp_hw_rule_rate_out_channels
, hdsp
,
4535 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
4537 if (RPM
!= hdsp
->io_type
) {
4538 hdsp
->creg_spdif_stream
= hdsp
->creg_spdif
;
4539 hdsp
->spdif_ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
4540 snd_ctl_notify(hdsp
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
4541 SNDRV_CTL_EVENT_MASK_INFO
, &hdsp
->spdif_ctl
->id
);
4546 static int snd_hdsp_playback_release(struct snd_pcm_substream
*substream
)
4548 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4550 spin_lock_irq(&hdsp
->lock
);
4552 hdsp
->playback_pid
= -1;
4553 hdsp
->playback_substream
= NULL
;
4555 spin_unlock_irq(&hdsp
->lock
);
4557 if (RPM
!= hdsp
->io_type
) {
4558 hdsp
->spdif_ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
4559 snd_ctl_notify(hdsp
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
4560 SNDRV_CTL_EVENT_MASK_INFO
, &hdsp
->spdif_ctl
->id
);
4566 static int snd_hdsp_capture_open(struct snd_pcm_substream
*substream
)
4568 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4569 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
4571 if (hdsp_check_for_iobox (hdsp
))
4574 if (hdsp_check_for_firmware(hdsp
, 1))
4577 spin_lock_irq(&hdsp
->lock
);
4579 snd_pcm_set_sync(substream
);
4581 runtime
->hw
= snd_hdsp_capture_subinfo
;
4582 runtime
->dma_area
= hdsp
->capture_buffer
;
4583 runtime
->dma_bytes
= HDSP_DMA_AREA_BYTES
;
4585 hdsp
->capture_pid
= current
->pid
;
4586 hdsp
->capture_substream
= substream
;
4588 spin_unlock_irq(&hdsp
->lock
);
4590 snd_pcm_hw_constraint_msbits(runtime
, 0, 32, 24);
4591 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE
, &hdsp_hw_constraints_period_sizes
);
4592 if (hdsp
->io_type
== H9632
) {
4593 runtime
->hw
.channels_min
= hdsp
->qs_in_channels
;
4594 runtime
->hw
.channels_max
= hdsp
->ss_in_channels
;
4595 runtime
->hw
.rate_max
= 192000;
4596 runtime
->hw
.rates
= SNDRV_PCM_RATE_KNOT
;
4597 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
, &hdsp_hw_constraints_9632_sample_rates
);
4599 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
4600 snd_hdsp_hw_rule_in_channels
, hdsp
,
4601 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
4602 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
4603 snd_hdsp_hw_rule_in_channels_rate
, hdsp
,
4604 SNDRV_PCM_HW_PARAM_RATE
, -1);
4605 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
4606 snd_hdsp_hw_rule_rate_in_channels
, hdsp
,
4607 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
4611 static int snd_hdsp_capture_release(struct snd_pcm_substream
*substream
)
4613 struct hdsp
*hdsp
= snd_pcm_substream_chip(substream
);
4615 spin_lock_irq(&hdsp
->lock
);
4617 hdsp
->capture_pid
= -1;
4618 hdsp
->capture_substream
= NULL
;
4620 spin_unlock_irq(&hdsp
->lock
);
4624 /* helper functions for copying meter values */
4625 static inline int copy_u32_le(void __user
*dest
, void __iomem
*src
)
4627 u32 val
= readl(src
);
4628 return copy_to_user(dest
, &val
, 4);
4631 static inline int copy_u64_le(void __user
*dest
, void __iomem
*src_low
, void __iomem
*src_high
)
4633 u32 rms_low
, rms_high
;
4635 rms_low
= readl(src_low
);
4636 rms_high
= readl(src_high
);
4637 rms
= ((u64
)rms_high
<< 32) | rms_low
;
4638 return copy_to_user(dest
, &rms
, 8);
4641 static inline int copy_u48_le(void __user
*dest
, void __iomem
*src_low
, void __iomem
*src_high
)
4643 u32 rms_low
, rms_high
;
4645 rms_low
= readl(src_low
) & 0xffffff00;
4646 rms_high
= readl(src_high
) & 0xffffff00;
4647 rms
= ((u64
)rms_high
<< 32) | rms_low
;
4648 return copy_to_user(dest
, &rms
, 8);
4651 static int hdsp_9652_get_peak(struct hdsp
*hdsp
, struct hdsp_peak_rms __user
*peak_rms
)
4653 int doublespeed
= 0;
4654 int i
, j
, channels
, ofs
;
4656 if (hdsp_read (hdsp
, HDSP_statusRegister
) & HDSP_DoubleSpeedStatus
)
4658 channels
= doublespeed
? 14 : 26;
4659 for (i
= 0, j
= 0; i
< 26; ++i
) {
4660 if (doublespeed
&& (i
& 4))
4662 ofs
= HDSP_9652_peakBase
- j
* 4;
4663 if (copy_u32_le(&peak_rms
->input_peaks
[i
], hdsp
->iobase
+ ofs
))
4665 ofs
-= channels
* 4;
4666 if (copy_u32_le(&peak_rms
->playback_peaks
[i
], hdsp
->iobase
+ ofs
))
4668 ofs
-= channels
* 4;
4669 if (copy_u32_le(&peak_rms
->output_peaks
[i
], hdsp
->iobase
+ ofs
))
4671 ofs
= HDSP_9652_rmsBase
+ j
* 8;
4672 if (copy_u48_le(&peak_rms
->input_rms
[i
], hdsp
->iobase
+ ofs
,
4673 hdsp
->iobase
+ ofs
+ 4))
4675 ofs
+= channels
* 8;
4676 if (copy_u48_le(&peak_rms
->playback_rms
[i
], hdsp
->iobase
+ ofs
,
4677 hdsp
->iobase
+ ofs
+ 4))
4679 ofs
+= channels
* 8;
4680 if (copy_u48_le(&peak_rms
->output_rms
[i
], hdsp
->iobase
+ ofs
,
4681 hdsp
->iobase
+ ofs
+ 4))
4688 static int hdsp_9632_get_peak(struct hdsp
*hdsp
, struct hdsp_peak_rms __user
*peak_rms
)
4691 struct hdsp_9632_meters __iomem
*m
;
4692 int doublespeed
= 0;
4694 if (hdsp_read (hdsp
, HDSP_statusRegister
) & HDSP_DoubleSpeedStatus
)
4696 m
= (struct hdsp_9632_meters __iomem
*)(hdsp
->iobase
+HDSP_9632_metersBase
);
4697 for (i
= 0, j
= 0; i
< 16; ++i
, ++j
) {
4698 if (copy_u32_le(&peak_rms
->input_peaks
[i
], &m
->input_peak
[j
]))
4700 if (copy_u32_le(&peak_rms
->playback_peaks
[i
], &m
->playback_peak
[j
]))
4702 if (copy_u32_le(&peak_rms
->output_peaks
[i
], &m
->output_peak
[j
]))
4704 if (copy_u64_le(&peak_rms
->input_rms
[i
], &m
->input_rms_low
[j
],
4705 &m
->input_rms_high
[j
]))
4707 if (copy_u64_le(&peak_rms
->playback_rms
[i
], &m
->playback_rms_low
[j
],
4708 &m
->playback_rms_high
[j
]))
4710 if (copy_u64_le(&peak_rms
->output_rms
[i
], &m
->output_rms_low
[j
],
4711 &m
->output_rms_high
[j
]))
4713 if (doublespeed
&& i
== 3) i
+= 4;
4718 static int hdsp_get_peak(struct hdsp
*hdsp
, struct hdsp_peak_rms __user
*peak_rms
)
4722 for (i
= 0; i
< 26; i
++) {
4723 if (copy_u32_le(&peak_rms
->playback_peaks
[i
],
4724 hdsp
->iobase
+ HDSP_playbackPeakLevel
+ i
* 4))
4726 if (copy_u32_le(&peak_rms
->input_peaks
[i
],
4727 hdsp
->iobase
+ HDSP_inputPeakLevel
+ i
* 4))
4730 for (i
= 0; i
< 28; i
++) {
4731 if (copy_u32_le(&peak_rms
->output_peaks
[i
],
4732 hdsp
->iobase
+ HDSP_outputPeakLevel
+ i
* 4))
4735 for (i
= 0; i
< 26; ++i
) {
4736 if (copy_u64_le(&peak_rms
->playback_rms
[i
],
4737 hdsp
->iobase
+ HDSP_playbackRmsLevel
+ i
* 8 + 4,
4738 hdsp
->iobase
+ HDSP_playbackRmsLevel
+ i
* 8))
4740 if (copy_u64_le(&peak_rms
->input_rms
[i
],
4741 hdsp
->iobase
+ HDSP_inputRmsLevel
+ i
* 8 + 4,
4742 hdsp
->iobase
+ HDSP_inputRmsLevel
+ i
* 8))
4748 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep
*hw
, struct file
*file
, unsigned int cmd
, unsigned long arg
)
4750 struct hdsp
*hdsp
= hw
->private_data
;
4751 void __user
*argp
= (void __user
*)arg
;
4755 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS
: {
4756 struct hdsp_peak_rms __user
*peak_rms
= (struct hdsp_peak_rms __user
*)arg
;
4758 err
= hdsp_check_for_iobox(hdsp
);
4762 err
= hdsp_check_for_firmware(hdsp
, 1);
4766 if (!(hdsp
->state
& HDSP_FirmwareLoaded
)) {
4767 dev_err(hdsp
->card
->dev
,
4768 "firmware needs to be uploaded to the card.\n");
4772 switch (hdsp
->io_type
) {
4774 return hdsp_9652_get_peak(hdsp
, peak_rms
);
4776 return hdsp_9632_get_peak(hdsp
, peak_rms
);
4778 return hdsp_get_peak(hdsp
, peak_rms
);
4781 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO
: {
4782 struct hdsp_config_info info
;
4783 unsigned long flags
;
4786 err
= hdsp_check_for_iobox(hdsp
);
4790 err
= hdsp_check_for_firmware(hdsp
, 1);
4794 memset(&info
, 0, sizeof(info
));
4795 spin_lock_irqsave(&hdsp
->lock
, flags
);
4796 info
.pref_sync_ref
= (unsigned char)hdsp_pref_sync_ref(hdsp
);
4797 info
.wordclock_sync_check
= (unsigned char)hdsp_wc_sync_check(hdsp
);
4798 if (hdsp
->io_type
!= H9632
)
4799 info
.adatsync_sync_check
= (unsigned char)hdsp_adatsync_sync_check(hdsp
);
4800 info
.spdif_sync_check
= (unsigned char)hdsp_spdif_sync_check(hdsp
);
4801 for (i
= 0; i
< ((hdsp
->io_type
!= Multiface
&& hdsp
->io_type
!= RPM
&& hdsp
->io_type
!= H9632
) ? 3 : 1); ++i
)
4802 info
.adat_sync_check
[i
] = (unsigned char)hdsp_adat_sync_check(hdsp
, i
);
4803 info
.spdif_in
= (unsigned char)hdsp_spdif_in(hdsp
);
4804 info
.spdif_out
= (unsigned char)hdsp_toggle_setting(hdsp
,
4805 HDSP_SPDIFOpticalOut
);
4806 info
.spdif_professional
= (unsigned char)
4807 hdsp_toggle_setting(hdsp
, HDSP_SPDIFProfessional
);
4808 info
.spdif_emphasis
= (unsigned char)
4809 hdsp_toggle_setting(hdsp
, HDSP_SPDIFEmphasis
);
4810 info
.spdif_nonaudio
= (unsigned char)
4811 hdsp_toggle_setting(hdsp
, HDSP_SPDIFNonAudio
);
4812 info
.spdif_sample_rate
= hdsp_spdif_sample_rate(hdsp
);
4813 info
.system_sample_rate
= hdsp
->system_sample_rate
;
4814 info
.autosync_sample_rate
= hdsp_external_sample_rate(hdsp
);
4815 info
.system_clock_mode
= (unsigned char)hdsp_system_clock_mode(hdsp
);
4816 info
.clock_source
= (unsigned char)hdsp_clock_source(hdsp
);
4817 info
.autosync_ref
= (unsigned char)hdsp_autosync_ref(hdsp
);
4818 info
.line_out
= (unsigned char)
4819 hdsp_toggle_setting(hdsp
, HDSP_LineOut
);
4820 if (hdsp
->io_type
== H9632
) {
4821 info
.da_gain
= (unsigned char)hdsp_da_gain(hdsp
);
4822 info
.ad_gain
= (unsigned char)hdsp_ad_gain(hdsp
);
4823 info
.phone_gain
= (unsigned char)hdsp_phone_gain(hdsp
);
4824 info
.xlr_breakout_cable
=
4825 (unsigned char)hdsp_toggle_setting(hdsp
,
4826 HDSP_XLRBreakoutCable
);
4828 } else if (hdsp
->io_type
== RPM
) {
4829 info
.da_gain
= (unsigned char) hdsp_rpm_input12(hdsp
);
4830 info
.ad_gain
= (unsigned char) hdsp_rpm_input34(hdsp
);
4832 if (hdsp
->io_type
== H9632
|| hdsp
->io_type
== H9652
)
4833 info
.analog_extension_board
=
4834 (unsigned char)hdsp_toggle_setting(hdsp
,
4835 HDSP_AnalogExtensionBoard
);
4836 spin_unlock_irqrestore(&hdsp
->lock
, flags
);
4837 if (copy_to_user(argp
, &info
, sizeof(info
)))
4841 case SNDRV_HDSP_IOCTL_GET_9632_AEB
: {
4842 struct hdsp_9632_aeb h9632_aeb
;
4844 if (hdsp
->io_type
!= H9632
) return -EINVAL
;
4845 h9632_aeb
.aebi
= hdsp
->ss_in_channels
- H9632_SS_CHANNELS
;
4846 h9632_aeb
.aebo
= hdsp
->ss_out_channels
- H9632_SS_CHANNELS
;
4847 if (copy_to_user(argp
, &h9632_aeb
, sizeof(h9632_aeb
)))
4851 case SNDRV_HDSP_IOCTL_GET_VERSION
: {
4852 struct hdsp_version hdsp_version
;
4855 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
) return -EINVAL
;
4856 if (hdsp
->io_type
== Undefined
) {
4857 if ((err
= hdsp_get_iobox_version(hdsp
)) < 0)
4860 memset(&hdsp_version
, 0, sizeof(hdsp_version
));
4861 hdsp_version
.io_type
= hdsp
->io_type
;
4862 hdsp_version
.firmware_rev
= hdsp
->firmware_rev
;
4863 if ((err
= copy_to_user(argp
, &hdsp_version
, sizeof(hdsp_version
))))
4867 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE
: {
4868 struct hdsp_firmware firmware
;
4869 u32 __user
*firmware_data
;
4872 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
) return -EINVAL
;
4873 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4874 if (hdsp
->io_type
== Undefined
) return -EINVAL
;
4876 if (hdsp
->state
& (HDSP_FirmwareCached
| HDSP_FirmwareLoaded
))
4879 dev_info(hdsp
->card
->dev
,
4880 "initializing firmware upload\n");
4881 if (copy_from_user(&firmware
, argp
, sizeof(firmware
)))
4883 firmware_data
= (u32 __user
*)firmware
.firmware_data
;
4885 if (hdsp_check_for_iobox (hdsp
))
4888 if (!hdsp
->fw_uploaded
) {
4889 hdsp
->fw_uploaded
= vmalloc(HDSP_FIRMWARE_SIZE
);
4890 if (!hdsp
->fw_uploaded
)
4894 if (copy_from_user(hdsp
->fw_uploaded
, firmware_data
,
4895 HDSP_FIRMWARE_SIZE
)) {
4896 vfree(hdsp
->fw_uploaded
);
4897 hdsp
->fw_uploaded
= NULL
;
4901 hdsp
->state
|= HDSP_FirmwareCached
;
4903 if ((err
= snd_hdsp_load_firmware_from_cache(hdsp
)) < 0)
4906 if (!(hdsp
->state
& HDSP_InitializationComplete
)) {
4907 if ((err
= snd_hdsp_enable_io(hdsp
)) < 0)
4910 snd_hdsp_initialize_channels(hdsp
);
4911 snd_hdsp_initialize_midi_flush(hdsp
);
4913 if ((err
= snd_hdsp_create_alsa_devices(hdsp
->card
, hdsp
)) < 0) {
4914 dev_err(hdsp
->card
->dev
,
4915 "error creating alsa devices\n");
4921 case SNDRV_HDSP_IOCTL_GET_MIXER
: {
4922 struct hdsp_mixer __user
*mixer
= (struct hdsp_mixer __user
*)argp
;
4923 if (copy_to_user(mixer
->matrix
, hdsp
->mixer_matrix
, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE
))
4933 static const struct snd_pcm_ops snd_hdsp_playback_ops
= {
4934 .open
= snd_hdsp_playback_open
,
4935 .close
= snd_hdsp_playback_release
,
4936 .ioctl
= snd_hdsp_ioctl
,
4937 .hw_params
= snd_hdsp_hw_params
,
4938 .prepare
= snd_hdsp_prepare
,
4939 .trigger
= snd_hdsp_trigger
,
4940 .pointer
= snd_hdsp_hw_pointer
,
4941 .copy_user
= snd_hdsp_playback_copy
,
4942 .copy_kernel
= snd_hdsp_playback_copy_kernel
,
4943 .fill_silence
= snd_hdsp_hw_silence
,
4946 static const struct snd_pcm_ops snd_hdsp_capture_ops
= {
4947 .open
= snd_hdsp_capture_open
,
4948 .close
= snd_hdsp_capture_release
,
4949 .ioctl
= snd_hdsp_ioctl
,
4950 .hw_params
= snd_hdsp_hw_params
,
4951 .prepare
= snd_hdsp_prepare
,
4952 .trigger
= snd_hdsp_trigger
,
4953 .pointer
= snd_hdsp_hw_pointer
,
4954 .copy_user
= snd_hdsp_capture_copy
,
4955 .copy_kernel
= snd_hdsp_capture_copy_kernel
,
4958 static int snd_hdsp_create_hwdep(struct snd_card
*card
, struct hdsp
*hdsp
)
4960 struct snd_hwdep
*hw
;
4963 if ((err
= snd_hwdep_new(card
, "HDSP hwdep", 0, &hw
)) < 0)
4967 hw
->private_data
= hdsp
;
4968 strcpy(hw
->name
, "HDSP hwdep interface");
4970 hw
->ops
.ioctl
= snd_hdsp_hwdep_ioctl
;
4971 hw
->ops
.ioctl_compat
= snd_hdsp_hwdep_ioctl
;
4976 static int snd_hdsp_create_pcm(struct snd_card
*card
, struct hdsp
*hdsp
)
4978 struct snd_pcm
*pcm
;
4981 if ((err
= snd_pcm_new(card
, hdsp
->card_name
, 0, 1, 1, &pcm
)) < 0)
4985 pcm
->private_data
= hdsp
;
4986 strcpy(pcm
->name
, hdsp
->card_name
);
4988 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_hdsp_playback_ops
);
4989 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_hdsp_capture_ops
);
4991 pcm
->info_flags
= SNDRV_PCM_INFO_JOINT_DUPLEX
;
4996 static void snd_hdsp_9652_enable_mixer (struct hdsp
*hdsp
)
4998 hdsp
->control2_register
|= HDSP_9652_ENABLE_MIXER
;
4999 hdsp_write (hdsp
, HDSP_control2Reg
, hdsp
->control2_register
);
5002 static int snd_hdsp_enable_io (struct hdsp
*hdsp
)
5006 if (hdsp_fifo_wait (hdsp
, 0, 100)) {
5007 dev_err(hdsp
->card
->dev
,
5008 "enable_io fifo_wait failed\n");
5012 for (i
= 0; i
< hdsp
->max_channels
; ++i
) {
5013 hdsp_write (hdsp
, HDSP_inputEnable
+ (4 * i
), 1);
5014 hdsp_write (hdsp
, HDSP_outputEnable
+ (4 * i
), 1);
5020 static void snd_hdsp_initialize_channels(struct hdsp
*hdsp
)
5022 int status
, aebi_channels
, aebo_channels
, i
;
5024 switch (hdsp
->io_type
) {
5026 hdsp
->card_name
= "RME Hammerfall DSP + Digiface";
5027 hdsp
->ss_in_channels
= hdsp
->ss_out_channels
= DIGIFACE_SS_CHANNELS
;
5028 hdsp
->ds_in_channels
= hdsp
->ds_out_channels
= DIGIFACE_DS_CHANNELS
;
5032 hdsp
->card_name
= "RME Hammerfall HDSP 9652";
5033 hdsp
->ss_in_channels
= hdsp
->ss_out_channels
= H9652_SS_CHANNELS
;
5034 hdsp
->ds_in_channels
= hdsp
->ds_out_channels
= H9652_DS_CHANNELS
;
5038 status
= hdsp_read(hdsp
, HDSP_statusRegister
);
5039 /* HDSP_AEBx bits are low when AEB are connected */
5040 aebi_channels
= (status
& HDSP_AEBI
) ? 0 : 4;
5041 aebo_channels
= (status
& HDSP_AEBO
) ? 0 : 4;
5042 hdsp
->card_name
= "RME Hammerfall HDSP 9632";
5043 hdsp
->ss_in_channels
= H9632_SS_CHANNELS
+aebi_channels
;
5044 hdsp
->ds_in_channels
= H9632_DS_CHANNELS
+aebi_channels
;
5045 hdsp
->qs_in_channels
= H9632_QS_CHANNELS
+aebi_channels
;
5046 hdsp
->ss_out_channels
= H9632_SS_CHANNELS
+aebo_channels
;
5047 hdsp
->ds_out_channels
= H9632_DS_CHANNELS
+aebo_channels
;
5048 hdsp
->qs_out_channels
= H9632_QS_CHANNELS
+aebo_channels
;
5049 /* Disable loopback of output channels, as the set function
5050 * only sets on a change we fake all bits (channels) as enabled.
5052 hdsp
->io_loopback
= 0xffffffff;
5053 for (i
= 0; i
< hdsp
->max_channels
; ++i
)
5054 hdsp_loopback_set(hdsp
, i
, false);
5058 hdsp
->card_name
= "RME Hammerfall DSP + Multiface";
5059 hdsp
->ss_in_channels
= hdsp
->ss_out_channels
= MULTIFACE_SS_CHANNELS
;
5060 hdsp
->ds_in_channels
= hdsp
->ds_out_channels
= MULTIFACE_DS_CHANNELS
;
5064 hdsp
->card_name
= "RME Hammerfall DSP + RPM";
5065 hdsp
->ss_in_channels
= RPM_CHANNELS
-1;
5066 hdsp
->ss_out_channels
= RPM_CHANNELS
;
5067 hdsp
->ds_in_channels
= RPM_CHANNELS
-1;
5068 hdsp
->ds_out_channels
= RPM_CHANNELS
;
5072 /* should never get here */
5077 static void snd_hdsp_initialize_midi_flush (struct hdsp
*hdsp
)
5079 snd_hdsp_flush_midi_input (hdsp
, 0);
5080 snd_hdsp_flush_midi_input (hdsp
, 1);
5083 static int snd_hdsp_create_alsa_devices(struct snd_card
*card
, struct hdsp
*hdsp
)
5087 if ((err
= snd_hdsp_create_pcm(card
, hdsp
)) < 0) {
5089 "Error creating pcm interface\n");
5094 if ((err
= snd_hdsp_create_midi(card
, hdsp
, 0)) < 0) {
5096 "Error creating first midi interface\n");
5100 if (hdsp
->io_type
== Digiface
|| hdsp
->io_type
== H9652
) {
5101 if ((err
= snd_hdsp_create_midi(card
, hdsp
, 1)) < 0) {
5103 "Error creating second midi interface\n");
5108 if ((err
= snd_hdsp_create_controls(card
, hdsp
)) < 0) {
5110 "Error creating ctl interface\n");
5114 snd_hdsp_proc_init(hdsp
);
5116 hdsp
->system_sample_rate
= -1;
5117 hdsp
->playback_pid
= -1;
5118 hdsp
->capture_pid
= -1;
5119 hdsp
->capture_substream
= NULL
;
5120 hdsp
->playback_substream
= NULL
;
5122 if ((err
= snd_hdsp_set_defaults(hdsp
)) < 0) {
5124 "Error setting default values\n");
5128 if (!(hdsp
->state
& HDSP_InitializationComplete
)) {
5129 strcpy(card
->shortname
, "Hammerfall DSP");
5130 sprintf(card
->longname
, "%s at 0x%lx, irq %d", hdsp
->card_name
,
5131 hdsp
->port
, hdsp
->irq
);
5133 if ((err
= snd_card_register(card
)) < 0) {
5135 "error registering card\n");
5138 hdsp
->state
|= HDSP_InitializationComplete
;
5144 /* load firmware via hotplug fw loader */
5145 static int hdsp_request_fw_loader(struct hdsp
*hdsp
)
5148 const struct firmware
*fw
;
5151 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
)
5153 if (hdsp
->io_type
== Undefined
) {
5154 if ((err
= hdsp_get_iobox_version(hdsp
)) < 0)
5156 if (hdsp
->io_type
== H9652
|| hdsp
->io_type
== H9632
)
5160 /* caution: max length of firmware filename is 30! */
5161 switch (hdsp
->io_type
) {
5163 fwfile
= "rpm_firmware.bin";
5166 if (hdsp
->firmware_rev
== 0xa)
5167 fwfile
= "multiface_firmware.bin";
5169 fwfile
= "multiface_firmware_rev11.bin";
5172 if (hdsp
->firmware_rev
== 0xa)
5173 fwfile
= "digiface_firmware.bin";
5175 fwfile
= "digiface_firmware_rev11.bin";
5178 dev_err(hdsp
->card
->dev
,
5179 "invalid io_type %d\n", hdsp
->io_type
);
5183 if (request_firmware(&fw
, fwfile
, &hdsp
->pci
->dev
)) {
5184 dev_err(hdsp
->card
->dev
,
5185 "cannot load firmware %s\n", fwfile
);
5188 if (fw
->size
< HDSP_FIRMWARE_SIZE
) {
5189 dev_err(hdsp
->card
->dev
,
5190 "too short firmware size %d (expected %d)\n",
5191 (int)fw
->size
, HDSP_FIRMWARE_SIZE
);
5192 release_firmware(fw
);
5196 hdsp
->firmware
= fw
;
5198 hdsp
->state
|= HDSP_FirmwareCached
;
5200 if ((err
= snd_hdsp_load_firmware_from_cache(hdsp
)) < 0)
5203 if (!(hdsp
->state
& HDSP_InitializationComplete
)) {
5204 if ((err
= snd_hdsp_enable_io(hdsp
)) < 0)
5207 if ((err
= snd_hdsp_create_hwdep(hdsp
->card
, hdsp
)) < 0) {
5208 dev_err(hdsp
->card
->dev
,
5209 "error creating hwdep device\n");
5212 snd_hdsp_initialize_channels(hdsp
);
5213 snd_hdsp_initialize_midi_flush(hdsp
);
5214 if ((err
= snd_hdsp_create_alsa_devices(hdsp
->card
, hdsp
)) < 0) {
5215 dev_err(hdsp
->card
->dev
,
5216 "error creating alsa devices\n");
5223 static int snd_hdsp_create(struct snd_card
*card
,
5226 struct pci_dev
*pci
= hdsp
->pci
;
5233 hdsp
->midi
[0].rmidi
= NULL
;
5234 hdsp
->midi
[1].rmidi
= NULL
;
5235 hdsp
->midi
[0].input
= NULL
;
5236 hdsp
->midi
[1].input
= NULL
;
5237 hdsp
->midi
[0].output
= NULL
;
5238 hdsp
->midi
[1].output
= NULL
;
5239 hdsp
->midi
[0].pending
= 0;
5240 hdsp
->midi
[1].pending
= 0;
5241 spin_lock_init(&hdsp
->midi
[0].lock
);
5242 spin_lock_init(&hdsp
->midi
[1].lock
);
5243 hdsp
->iobase
= NULL
;
5244 hdsp
->control_register
= 0;
5245 hdsp
->control2_register
= 0;
5246 hdsp
->io_type
= Undefined
;
5247 hdsp
->max_channels
= 26;
5251 spin_lock_init(&hdsp
->lock
);
5253 INIT_WORK(&hdsp
->midi_work
, hdsp_midi_work
);
5255 pci_read_config_word(hdsp
->pci
, PCI_CLASS_REVISION
, &hdsp
->firmware_rev
);
5256 hdsp
->firmware_rev
&= 0xff;
5258 /* From Martin Bjoernsen :
5259 "It is important that the card's latency timer register in
5260 the PCI configuration space is set to a value much larger
5261 than 0 by the computer's BIOS or the driver.
5262 The windows driver always sets this 8 bit register [...]
5263 to its maximum 255 to avoid problems with some computers."
5265 pci_write_config_byte(hdsp
->pci
, PCI_LATENCY_TIMER
, 0xFF);
5267 strcpy(card
->driver
, "H-DSP");
5268 strcpy(card
->mixername
, "Xilinx FPGA");
5270 if (hdsp
->firmware_rev
< 0xa)
5272 else if (hdsp
->firmware_rev
< 0x64)
5273 hdsp
->card_name
= "RME Hammerfall DSP";
5274 else if (hdsp
->firmware_rev
< 0x96) {
5275 hdsp
->card_name
= "RME HDSP 9652";
5278 hdsp
->card_name
= "RME HDSP 9632";
5279 hdsp
->max_channels
= 16;
5283 if ((err
= pci_enable_device(pci
)) < 0)
5286 pci_set_master(hdsp
->pci
);
5288 if ((err
= pci_request_regions(pci
, "hdsp")) < 0)
5290 hdsp
->port
= pci_resource_start(pci
, 0);
5291 if ((hdsp
->iobase
= ioremap(hdsp
->port
, HDSP_IO_EXTENT
)) == NULL
) {
5292 dev_err(hdsp
->card
->dev
, "unable to remap region 0x%lx-0x%lx\n",
5293 hdsp
->port
, hdsp
->port
+ HDSP_IO_EXTENT
- 1);
5297 if (request_irq(pci
->irq
, snd_hdsp_interrupt
, IRQF_SHARED
,
5298 KBUILD_MODNAME
, hdsp
)) {
5299 dev_err(hdsp
->card
->dev
, "unable to use IRQ %d\n", pci
->irq
);
5303 hdsp
->irq
= pci
->irq
;
5304 card
->sync_irq
= hdsp
->irq
;
5305 hdsp
->precise_ptr
= 0;
5306 hdsp
->use_midi_work
= 1;
5307 hdsp
->dds_value
= 0;
5309 if ((err
= snd_hdsp_initialize_memory(hdsp
)) < 0)
5312 if (!is_9652
&& !is_9632
) {
5313 /* we wait a maximum of 10 seconds to let freshly
5314 * inserted cardbus cards do their hardware init */
5315 err
= hdsp_wait_for_iobox(hdsp
, 1000, 10);
5320 if ((hdsp_read (hdsp
, HDSP_statusRegister
) & HDSP_DllError
) != 0) {
5321 if ((err
= hdsp_request_fw_loader(hdsp
)) < 0)
5322 /* we don't fail as this can happen
5323 if userspace is not ready for
5326 dev_err(hdsp
->card
->dev
,
5327 "couldn't get firmware from userspace. try using hdsploader\n");
5329 /* init is complete, we return */
5331 /* we defer initialization */
5332 dev_info(hdsp
->card
->dev
,
5333 "card initialization pending : waiting for firmware\n");
5334 if ((err
= snd_hdsp_create_hwdep(card
, hdsp
)) < 0)
5338 dev_info(hdsp
->card
->dev
,
5339 "Firmware already present, initializing card.\n");
5340 if (hdsp_read(hdsp
, HDSP_status2Register
) & HDSP_version2
)
5341 hdsp
->io_type
= RPM
;
5342 else if (hdsp_read(hdsp
, HDSP_status2Register
) & HDSP_version1
)
5343 hdsp
->io_type
= Multiface
;
5345 hdsp
->io_type
= Digiface
;
5349 if ((err
= snd_hdsp_enable_io(hdsp
)) != 0)
5353 hdsp
->io_type
= H9652
;
5356 hdsp
->io_type
= H9632
;
5358 if ((err
= snd_hdsp_create_hwdep(card
, hdsp
)) < 0)
5361 snd_hdsp_initialize_channels(hdsp
);
5362 snd_hdsp_initialize_midi_flush(hdsp
);
5364 hdsp
->state
|= HDSP_FirmwareLoaded
;
5366 if ((err
= snd_hdsp_create_alsa_devices(card
, hdsp
)) < 0)
5372 static int snd_hdsp_free(struct hdsp
*hdsp
)
5375 /* stop the audio, and cancel all interrupts */
5376 cancel_work_sync(&hdsp
->midi_work
);
5377 hdsp
->control_register
&= ~(HDSP_Start
|HDSP_AudioInterruptEnable
|HDSP_Midi0InterruptEnable
|HDSP_Midi1InterruptEnable
);
5378 hdsp_write (hdsp
, HDSP_controlRegister
, hdsp
->control_register
);
5382 free_irq(hdsp
->irq
, (void *)hdsp
);
5384 snd_hdsp_free_buffers(hdsp
);
5386 release_firmware(hdsp
->firmware
);
5387 vfree(hdsp
->fw_uploaded
);
5388 iounmap(hdsp
->iobase
);
5391 pci_release_regions(hdsp
->pci
);
5393 pci_disable_device(hdsp
->pci
);
5397 static void snd_hdsp_card_free(struct snd_card
*card
)
5399 struct hdsp
*hdsp
= card
->private_data
;
5402 snd_hdsp_free(hdsp
);
5405 static int snd_hdsp_probe(struct pci_dev
*pci
,
5406 const struct pci_device_id
*pci_id
)
5410 struct snd_card
*card
;
5413 if (dev
>= SNDRV_CARDS
)
5420 err
= snd_card_new(&pci
->dev
, index
[dev
], id
[dev
], THIS_MODULE
,
5421 sizeof(struct hdsp
), &card
);
5425 hdsp
= card
->private_data
;
5426 card
->private_free
= snd_hdsp_card_free
;
5429 err
= snd_hdsp_create(card
, hdsp
);
5433 strcpy(card
->shortname
, "Hammerfall DSP");
5434 sprintf(card
->longname
, "%s at 0x%lx, irq %d", hdsp
->card_name
,
5435 hdsp
->port
, hdsp
->irq
);
5436 err
= snd_card_register(card
);
5439 snd_card_free(card
);
5442 pci_set_drvdata(pci
, card
);
5447 static void snd_hdsp_remove(struct pci_dev
*pci
)
5449 snd_card_free(pci_get_drvdata(pci
));
5452 static struct pci_driver hdsp_driver
= {
5453 .name
= KBUILD_MODNAME
,
5454 .id_table
= snd_hdsp_ids
,
5455 .probe
= snd_hdsp_probe
,
5456 .remove
= snd_hdsp_remove
,
5459 module_pci_driver(hdsp_driver
);