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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
4 *
5 * Copyright (c) 2002 Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 */
9
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
18 #include <linux/io.h>
19 #include <linux/nospec.h>
20
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
30
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
33
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
37
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_FIRMWARE("rpm_firmware.bin");
48 MODULE_FIRMWARE("multiface_firmware.bin");
49 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
50 MODULE_FIRMWARE("digiface_firmware.bin");
51 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
52
53 #define HDSP_MAX_CHANNELS 26
54 #define HDSP_MAX_DS_CHANNELS 14
55 #define HDSP_MAX_QS_CHANNELS 8
56 #define DIGIFACE_SS_CHANNELS 26
57 #define DIGIFACE_DS_CHANNELS 14
58 #define MULTIFACE_SS_CHANNELS 18
59 #define MULTIFACE_DS_CHANNELS 14
60 #define H9652_SS_CHANNELS 26
61 #define H9652_DS_CHANNELS 14
62 /* This does not include possible Analog Extension Boards
63 AEBs are detected at card initialization
64 */
65 #define H9632_SS_CHANNELS 12
66 #define H9632_DS_CHANNELS 8
67 #define H9632_QS_CHANNELS 4
68 #define RPM_CHANNELS 6
69
70 /* Write registers. These are defined as byte-offsets from the iobase value.
71 */
72 #define HDSP_resetPointer 0
73 #define HDSP_freqReg 0
74 #define HDSP_outputBufferAddress 32
75 #define HDSP_inputBufferAddress 36
76 #define HDSP_controlRegister 64
77 #define HDSP_interruptConfirmation 96
78 #define HDSP_outputEnable 128
79 #define HDSP_control2Reg 256
80 #define HDSP_midiDataOut0 352
81 #define HDSP_midiDataOut1 356
82 #define HDSP_fifoData 368
83 #define HDSP_inputEnable 384
84
85 /* Read registers. These are defined as byte-offsets from the iobase value
86 */
87
88 #define HDSP_statusRegister 0
89 #define HDSP_timecode 128
90 #define HDSP_status2Register 192
91 #define HDSP_midiDataIn0 360
92 #define HDSP_midiDataIn1 364
93 #define HDSP_midiStatusOut0 384
94 #define HDSP_midiStatusOut1 388
95 #define HDSP_midiStatusIn0 392
96 #define HDSP_midiStatusIn1 396
97 #define HDSP_fifoStatus 400
98
99 /* the meters are regular i/o-mapped registers, but offset
100 considerably from the rest. the peak registers are reset
101 when read; the least-significant 4 bits are full-scale counters;
102 the actual peak value is in the most-significant 24 bits.
103 */
104
105 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
106 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
107 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
108 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
109 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
110
111
112 /* This is for H9652 cards
113 Peak values are read downward from the base
114 Rms values are read upward
115 There are rms values for the outputs too
116 26*3 values are read in ss mode
117 14*3 in ds mode, with no gap between values
118 */
119 #define HDSP_9652_peakBase 7164
120 #define HDSP_9652_rmsBase 4096
121
122 /* c.f. the hdsp_9632_meters_t struct */
123 #define HDSP_9632_metersBase 4096
124
125 #define HDSP_IO_EXTENT 7168
126
127 /* control2 register bits */
128
129 #define HDSP_TMS 0x01
130 #define HDSP_TCK 0x02
131 #define HDSP_TDI 0x04
132 #define HDSP_JTAG 0x08
133 #define HDSP_PWDN 0x10
134 #define HDSP_PROGRAM 0x020
135 #define HDSP_CONFIG_MODE_0 0x040
136 #define HDSP_CONFIG_MODE_1 0x080
137 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
138 #define HDSP_BIGENDIAN_MODE 0x200
139 #define HDSP_RD_MULTIPLE 0x400
140 #define HDSP_9652_ENABLE_MIXER 0x800
141 #define HDSP_S200 0x800
142 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
143 #define HDSP_CYCLIC_MODE 0x1000
144 #define HDSP_TDO 0x10000000
145
146 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
147 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
148
149 /* Control Register bits */
150
151 #define HDSP_Start (1<<0) /* start engine */
152 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
153 #define HDSP_Latency1 (1<<2) /* [ see above ] */
154 #define HDSP_Latency2 (1<<3) /* [ see above ] */
155 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
156 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
157 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
158 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
159 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
160 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
161 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
162 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
163 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
164 #define HDSP_SyncRef2 (1<<13)
165 #define HDSP_SPDIFInputSelect0 (1<<14)
166 #define HDSP_SPDIFInputSelect1 (1<<15)
167 #define HDSP_SyncRef0 (1<<16)
168 #define HDSP_SyncRef1 (1<<17)
169 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
170 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
171 #define HDSP_Midi0InterruptEnable (1<<22)
172 #define HDSP_Midi1InterruptEnable (1<<23)
173 #define HDSP_LineOut (1<<24)
174 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
175 #define HDSP_ADGain1 (1<<26)
176 #define HDSP_DAGain0 (1<<27)
177 #define HDSP_DAGain1 (1<<28)
178 #define HDSP_PhoneGain0 (1<<29)
179 #define HDSP_PhoneGain1 (1<<30)
180 #define HDSP_QuadSpeed (1<<31)
181
182 /* RPM uses some of the registers for special purposes */
183 #define HDSP_RPM_Inp12 0x04A00
184 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
185 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
186 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
187 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
188 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
189
190 #define HDSP_RPM_Inp34 0x32000
191 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
192 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
193 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
194 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
195 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
196
197 #define HDSP_RPM_Bypass 0x01000
198
199 #define HDSP_RPM_Disconnect 0x00001
200
201 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
202 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
203 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
204 #define HDSP_ADGainLowGain 0
205
206 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
207 #define HDSP_DAGainHighGain HDSP_DAGainMask
208 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
209 #define HDSP_DAGainMinus10dBV 0
210
211 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
212 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
213 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
214 #define HDSP_PhoneGainMinus12dB 0
215
216 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
217 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
218
219 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
220 #define HDSP_SPDIFInputADAT1 0
221 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
222 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
224
225 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
226 #define HDSP_SyncRef_ADAT1 0
227 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
228 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
229 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
230 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
231 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
232
233 /* Sample Clock Sources */
234
235 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
236 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
237 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
238 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
239 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
240 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
241 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
242 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
243 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
244 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
245
246 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
247
248 #define HDSP_SYNC_FROM_WORD 0
249 #define HDSP_SYNC_FROM_SPDIF 1
250 #define HDSP_SYNC_FROM_ADAT1 2
251 #define HDSP_SYNC_FROM_ADAT_SYNC 3
252 #define HDSP_SYNC_FROM_ADAT2 4
253 #define HDSP_SYNC_FROM_ADAT3 5
254
255 /* SyncCheck status */
256
257 #define HDSP_SYNC_CHECK_NO_LOCK 0
258 #define HDSP_SYNC_CHECK_LOCK 1
259 #define HDSP_SYNC_CHECK_SYNC 2
260
261 /* AutoSync references - used by "autosync_ref" control switch */
262
263 #define HDSP_AUTOSYNC_FROM_WORD 0
264 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
265 #define HDSP_AUTOSYNC_FROM_SPDIF 2
266 #define HDSP_AUTOSYNC_FROM_NONE 3
267 #define HDSP_AUTOSYNC_FROM_ADAT1 4
268 #define HDSP_AUTOSYNC_FROM_ADAT2 5
269 #define HDSP_AUTOSYNC_FROM_ADAT3 6
270
271 /* Possible sources of S/PDIF input */
272
273 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
274 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
275 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
276 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
277
278 #define HDSP_Frequency32KHz HDSP_Frequency0
279 #define HDSP_Frequency44_1KHz HDSP_Frequency1
280 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
281 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
282 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
283 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
284 /* For H9632 cards */
285 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
286 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
287 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
288 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
289 return 104857600000000 / rate; // 100 MHz
290 return 110100480000000 / rate; // 105 MHz
291 */
292 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
293
294 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
295 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
296
297 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
298 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
299
300 /* Status Register bits */
301
302 #define HDSP_audioIRQPending (1<<0)
303 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
304 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
305 #define HDSP_Lock1 (1<<2)
306 #define HDSP_Lock0 (1<<3)
307 #define HDSP_SPDIFSync (1<<4)
308 #define HDSP_TimecodeLock (1<<5)
309 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
310 #define HDSP_Sync2 (1<<16)
311 #define HDSP_Sync1 (1<<17)
312 #define HDSP_Sync0 (1<<18)
313 #define HDSP_DoubleSpeedStatus (1<<19)
314 #define HDSP_ConfigError (1<<20)
315 #define HDSP_DllError (1<<21)
316 #define HDSP_spdifFrequency0 (1<<22)
317 #define HDSP_spdifFrequency1 (1<<23)
318 #define HDSP_spdifFrequency2 (1<<24)
319 #define HDSP_SPDIFErrorFlag (1<<25)
320 #define HDSP_BufferID (1<<26)
321 #define HDSP_TimecodeSync (1<<27)
322 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
323 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
324 #define HDSP_midi0IRQPending (1<<30)
325 #define HDSP_midi1IRQPending (1<<31)
326
327 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
328 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
329 HDSP_spdifFrequency1|\
330 HDSP_spdifFrequency2|\
331 HDSP_spdifFrequency3)
332
333 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
334 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
335 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
336
337 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
338 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
339 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
340
341 /* This is for H9632 cards */
342 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
343 HDSP_spdifFrequency1|\
344 HDSP_spdifFrequency2)
345 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
346 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
347
348 /* Status2 Register bits */
349
350 #define HDSP_version0 (1<<0)
351 #define HDSP_version1 (1<<1)
352 #define HDSP_version2 (1<<2)
353 #define HDSP_wc_lock (1<<3)
354 #define HDSP_wc_sync (1<<4)
355 #define HDSP_inp_freq0 (1<<5)
356 #define HDSP_inp_freq1 (1<<6)
357 #define HDSP_inp_freq2 (1<<7)
358 #define HDSP_SelSyncRef0 (1<<8)
359 #define HDSP_SelSyncRef1 (1<<9)
360 #define HDSP_SelSyncRef2 (1<<10)
361
362 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
363
364 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
365 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
366 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
367 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
368 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
369 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
370 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
371 /* FIXME : more values for 9632 cards ? */
372
373 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
374 #define HDSP_SelSyncRef_ADAT1 0
375 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
376 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
377 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
378 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
379 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
380
381 /* Card state flags */
382
383 #define HDSP_InitializationComplete (1<<0)
384 #define HDSP_FirmwareLoaded (1<<1)
385 #define HDSP_FirmwareCached (1<<2)
386
387 /* FIFO wait times, defined in terms of 1/10ths of msecs */
388
389 #define HDSP_LONG_WAIT 5000
390 #define HDSP_SHORT_WAIT 30
391
392 #define UNITY_GAIN 32768
393 #define MINUS_INFINITY_GAIN 0
394
395 /* the size of a substream (1 mono data stream) */
396
397 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
398 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
399
400 /* the size of the area we need to allocate for DMA transfers. the
401 size is the same regardless of the number of channels - the
402 Multiface still uses the same memory area.
403
404 Note that we allocate 1 more channel than is apparently needed
405 because the h/w seems to write 1 byte beyond the end of the last
406 page. Sigh.
407 */
408
409 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
410 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
411
412 #define HDSP_FIRMWARE_SIZE (24413 * 4)
413
414 struct hdsp_9632_meters {
415 u32 input_peak[16];
416 u32 playback_peak[16];
417 u32 output_peak[16];
418 u32 xxx_peak[16];
419 u32 padding[64];
420 u32 input_rms_low[16];
421 u32 playback_rms_low[16];
422 u32 output_rms_low[16];
423 u32 xxx_rms_low[16];
424 u32 input_rms_high[16];
425 u32 playback_rms_high[16];
426 u32 output_rms_high[16];
427 u32 xxx_rms_high[16];
428 };
429
430 struct hdsp_midi {
431 struct hdsp *hdsp;
432 int id;
433 struct snd_rawmidi *rmidi;
434 struct snd_rawmidi_substream *input;
435 struct snd_rawmidi_substream *output;
436 char istimer; /* timer in use */
437 struct timer_list timer;
438 spinlock_t lock;
439 int pending;
440 };
441
442 struct hdsp {
443 spinlock_t lock;
444 struct snd_pcm_substream *capture_substream;
445 struct snd_pcm_substream *playback_substream;
446 struct hdsp_midi midi[2];
447 struct work_struct midi_work;
448 int use_midi_work;
449 int precise_ptr;
450 u32 control_register; /* cached value */
451 u32 control2_register; /* cached value */
452 u32 creg_spdif;
453 u32 creg_spdif_stream;
454 int clock_source_locked;
455 char *card_name; /* digiface/multiface/rpm */
456 enum HDSP_IO_Type io_type; /* ditto, but for code use */
457 unsigned short firmware_rev;
458 unsigned short state; /* stores state bits */
459 const struct firmware *firmware;
460 u32 *fw_uploaded;
461 size_t period_bytes; /* guess what this is */
462 unsigned char max_channels;
463 unsigned char qs_in_channels; /* quad speed mode for H9632 */
464 unsigned char ds_in_channels;
465 unsigned char ss_in_channels; /* different for multiface/digiface */
466 unsigned char qs_out_channels;
467 unsigned char ds_out_channels;
468 unsigned char ss_out_channels;
469 u32 io_loopback; /* output loopback channel states*/
470
471 struct snd_dma_buffer capture_dma_buf;
472 struct snd_dma_buffer playback_dma_buf;
473 unsigned char *capture_buffer; /* suitably aligned address */
474 unsigned char *playback_buffer; /* suitably aligned address */
475
476 pid_t capture_pid;
477 pid_t playback_pid;
478 int running;
479 int system_sample_rate;
480 const char *channel_map;
481 int dev;
482 int irq;
483 unsigned long port;
484 void __iomem *iobase;
485 struct snd_card *card;
486 struct snd_pcm *pcm;
487 struct snd_hwdep *hwdep;
488 struct pci_dev *pci;
489 struct snd_kcontrol *spdif_ctl;
490 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
491 unsigned int dds_value; /* last value written to freq register */
492 };
493
494 /* These tables map the ALSA channels 1..N to the channels that we
495 need to use in order to find the relevant channel buffer. RME
496 refer to this kind of mapping as between "the ADAT channel and
497 the DMA channel." We index it using the logical audio channel,
498 and the value is the DMA channel (i.e. channel buffer number)
499 where the data for that channel can be read/written from/to.
500 */
501
502 static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
503 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
504 18, 19, 20, 21, 22, 23, 24, 25
505 };
506
507 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
508 /* Analog */
509 0, 1, 2, 3, 4, 5, 6, 7,
510 /* ADAT 2 */
511 16, 17, 18, 19, 20, 21, 22, 23,
512 /* SPDIF */
513 24, 25,
514 -1, -1, -1, -1, -1, -1, -1, -1
515 };
516
517 static const char channel_map_ds[HDSP_MAX_CHANNELS] = {
518 /* ADAT channels are remapped */
519 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
520 /* channels 12 and 13 are S/PDIF */
521 24, 25,
522 /* others don't exist */
523 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
524 };
525
526 static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
527 /* ADAT channels */
528 0, 1, 2, 3, 4, 5, 6, 7,
529 /* SPDIF */
530 8, 9,
531 /* Analog */
532 10, 11,
533 /* AO4S-192 and AI4S-192 extension boards */
534 12, 13, 14, 15,
535 /* others don't exist */
536 -1, -1, -1, -1, -1, -1, -1, -1,
537 -1, -1
538 };
539
540 static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
541 /* ADAT */
542 1, 3, 5, 7,
543 /* SPDIF */
544 8, 9,
545 /* Analog */
546 10, 11,
547 /* AO4S-192 and AI4S-192 extension boards */
548 12, 13, 14, 15,
549 /* others don't exist */
550 -1, -1, -1, -1, -1, -1, -1, -1,
551 -1, -1, -1, -1, -1, -1
552 };
553
554 static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
555 /* ADAT is disabled in this mode */
556 /* SPDIF */
557 8, 9,
558 /* Analog */
559 10, 11,
560 /* AO4S-192 and AI4S-192 extension boards */
561 12, 13, 14, 15,
562 /* others don't exist */
563 -1, -1, -1, -1, -1, -1, -1, -1,
564 -1, -1, -1, -1, -1, -1, -1, -1,
565 -1, -1
566 };
567
568 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
569 {
570 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
571 }
572
573 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
574 {
575 if (dmab->area)
576 snd_dma_free_pages(dmab);
577 }
578
579
580 static const struct pci_device_id snd_hdsp_ids[] = {
581 {
582 .vendor = PCI_VENDOR_ID_XILINX,
583 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
584 .subvendor = PCI_ANY_ID,
585 .subdevice = PCI_ANY_ID,
586 }, /* RME Hammerfall-DSP */
587 { 0, },
588 };
589
590 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
591
592 /* prototypes */
593 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
594 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
595 static int snd_hdsp_enable_io (struct hdsp *hdsp);
596 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
597 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
598 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
599 static int hdsp_autosync_ref(struct hdsp *hdsp);
600 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
601 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
602
603 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
604 {
605 switch (hdsp->io_type) {
606 case Multiface:
607 case Digiface:
608 case RPM:
609 default:
610 if (hdsp->firmware_rev == 0xa)
611 return (64 * out) + (32 + (in));
612 else
613 return (52 * out) + (26 + (in));
614 case H9632:
615 return (32 * out) + (16 + (in));
616 case H9652:
617 return (52 * out) + (26 + (in));
618 }
619 }
620
621 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
622 {
623 switch (hdsp->io_type) {
624 case Multiface:
625 case Digiface:
626 case RPM:
627 default:
628 if (hdsp->firmware_rev == 0xa)
629 return (64 * out) + in;
630 else
631 return (52 * out) + in;
632 case H9632:
633 return (32 * out) + in;
634 case H9652:
635 return (52 * out) + in;
636 }
637 }
638
639 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
640 {
641 writel(val, hdsp->iobase + reg);
642 }
643
644 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
645 {
646 return readl (hdsp->iobase + reg);
647 }
648
649 static int hdsp_check_for_iobox (struct hdsp *hdsp)
650 {
651 int i;
652
653 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
654 for (i = 0; i < 500; i++) {
655 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
656 HDSP_ConfigError)) {
657 if (i) {
658 dev_dbg(hdsp->card->dev,
659 "IO box found after %d ms\n",
660 (20 * i));
661 }
662 return 0;
663 }
664 msleep(20);
665 }
666 dev_err(hdsp->card->dev, "no IO box connected!\n");
667 hdsp->state &= ~HDSP_FirmwareLoaded;
668 return -EIO;
669 }
670
671 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
672 unsigned int delay)
673 {
674 unsigned int i;
675
676 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
677 return 0;
678
679 for (i = 0; i != loops; ++i) {
680 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
681 msleep(delay);
682 else {
683 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
684 i * delay);
685 return 0;
686 }
687 }
688
689 dev_info(hdsp->card->dev, "no IO box connected!\n");
690 hdsp->state &= ~HDSP_FirmwareLoaded;
691 return -EIO;
692 }
693
694 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
695
696 int i;
697 unsigned long flags;
698 const u32 *cache;
699
700 if (hdsp->fw_uploaded)
701 cache = hdsp->fw_uploaded;
702 else {
703 if (!hdsp->firmware)
704 return -ENODEV;
705 cache = (u32 *)hdsp->firmware->data;
706 if (!cache)
707 return -ENODEV;
708 }
709
710 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
711
712 dev_info(hdsp->card->dev, "loading firmware\n");
713
714 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
715 hdsp_write (hdsp, HDSP_fifoData, 0);
716
717 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
718 dev_info(hdsp->card->dev,
719 "timeout waiting for download preparation\n");
720 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
721 return -EIO;
722 }
723
724 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
725
726 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
727 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
728 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
729 dev_info(hdsp->card->dev,
730 "timeout during firmware loading\n");
731 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
732 return -EIO;
733 }
734 }
735
736 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
737 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
738
739 ssleep(3);
740 #ifdef SNDRV_BIG_ENDIAN
741 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
742 #else
743 hdsp->control2_register = 0;
744 #endif
745 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
746 dev_info(hdsp->card->dev, "finished firmware loading\n");
747
748 }
749 if (hdsp->state & HDSP_InitializationComplete) {
750 dev_info(hdsp->card->dev,
751 "firmware loaded from cache, restoring defaults\n");
752 spin_lock_irqsave(&hdsp->lock, flags);
753 snd_hdsp_set_defaults(hdsp);
754 spin_unlock_irqrestore(&hdsp->lock, flags);
755 }
756
757 hdsp->state |= HDSP_FirmwareLoaded;
758
759 return 0;
760 }
761
762 static int hdsp_get_iobox_version (struct hdsp *hdsp)
763 {
764 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
765
766 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
767 hdsp_write(hdsp, HDSP_fifoData, 0);
768
769 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
770 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
771 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
772 }
773
774 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
775 hdsp_write (hdsp, HDSP_fifoData, 0);
776 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
777 goto set_multi;
778
779 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
780 hdsp_write(hdsp, HDSP_fifoData, 0);
781 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
782 hdsp->io_type = Digiface;
783 dev_info(hdsp->card->dev, "Digiface found\n");
784 return 0;
785 }
786
787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
788 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
789 hdsp_write(hdsp, HDSP_fifoData, 0);
790 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
791 goto set_multi;
792
793 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
794 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
795 hdsp_write(hdsp, HDSP_fifoData, 0);
796 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
797 goto set_multi;
798
799 hdsp->io_type = RPM;
800 dev_info(hdsp->card->dev, "RPM found\n");
801 return 0;
802 } else {
803 /* firmware was already loaded, get iobox type */
804 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
805 hdsp->io_type = RPM;
806 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
807 hdsp->io_type = Multiface;
808 else
809 hdsp->io_type = Digiface;
810 }
811 return 0;
812
813 set_multi:
814 hdsp->io_type = Multiface;
815 dev_info(hdsp->card->dev, "Multiface found\n");
816 return 0;
817 }
818
819
820 static int hdsp_request_fw_loader(struct hdsp *hdsp);
821
822 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
823 {
824 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
825 return 0;
826 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
827 hdsp->state &= ~HDSP_FirmwareLoaded;
828 if (! load_on_demand)
829 return -EIO;
830 dev_err(hdsp->card->dev, "firmware not present.\n");
831 /* try to load firmware */
832 if (! (hdsp->state & HDSP_FirmwareCached)) {
833 if (! hdsp_request_fw_loader(hdsp))
834 return 0;
835 dev_err(hdsp->card->dev,
836 "No firmware loaded nor cached, please upload firmware.\n");
837 return -EIO;
838 }
839 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
840 dev_err(hdsp->card->dev,
841 "Firmware loading from cache failed, please upload manually.\n");
842 return -EIO;
843 }
844 }
845 return 0;
846 }
847
848
849 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
850 {
851 int i;
852
853 /* the fifoStatus registers reports on how many words
854 are available in the command FIFO.
855 */
856
857 for (i = 0; i < timeout; i++) {
858
859 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
860 return 0;
861
862 /* not very friendly, but we only do this during a firmware
863 load and changing the mixer, so we just put up with it.
864 */
865
866 udelay (100);
867 }
868
869 dev_warn(hdsp->card->dev,
870 "wait for FIFO status <= %d failed after %d iterations\n",
871 count, timeout);
872 return -1;
873 }
874
875 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
876 {
877 if (addr >= HDSP_MATRIX_MIXER_SIZE)
878 return 0;
879
880 return hdsp->mixer_matrix[addr];
881 }
882
883 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
884 {
885 unsigned int ad;
886
887 if (addr >= HDSP_MATRIX_MIXER_SIZE)
888 return -1;
889
890 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
891
892 /* from martin bjornsen:
893
894 "You can only write dwords to the
895 mixer memory which contain two
896 mixer values in the low and high
897 word. So if you want to change
898 value 0 you have to read value 1
899 from the cache and write both to
900 the first dword in the mixer
901 memory."
902 */
903
904 if (hdsp->io_type == H9632 && addr >= 512)
905 return 0;
906
907 if (hdsp->io_type == H9652 && addr >= 1352)
908 return 0;
909
910 hdsp->mixer_matrix[addr] = data;
911
912
913 /* `addr' addresses a 16-bit wide address, but
914 the address space accessed via hdsp_write
915 uses byte offsets. put another way, addr
916 varies from 0 to 1351, but to access the
917 corresponding memory location, we need
918 to access 0 to 2703 ...
919 */
920 ad = addr/2;
921
922 hdsp_write (hdsp, 4096 + (ad*4),
923 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
924 hdsp->mixer_matrix[addr&0x7fe]);
925
926 return 0;
927
928 } else {
929
930 ad = (addr << 16) + data;
931
932 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
933 return -1;
934
935 hdsp_write (hdsp, HDSP_fifoData, ad);
936 hdsp->mixer_matrix[addr] = data;
937
938 }
939
940 return 0;
941 }
942
943 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
944 {
945 unsigned long flags;
946 int ret = 1;
947
948 spin_lock_irqsave(&hdsp->lock, flags);
949 if ((hdsp->playback_pid != hdsp->capture_pid) &&
950 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
951 ret = 0;
952 spin_unlock_irqrestore(&hdsp->lock, flags);
953 return ret;
954 }
955
956 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
957 {
958 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
959 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
960
961 /* For the 9632, the mask is different */
962 if (hdsp->io_type == H9632)
963 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
964
965 if (status & HDSP_SPDIFErrorFlag)
966 return 0;
967
968 switch (rate_bits) {
969 case HDSP_spdifFrequency32KHz: return 32000;
970 case HDSP_spdifFrequency44_1KHz: return 44100;
971 case HDSP_spdifFrequency48KHz: return 48000;
972 case HDSP_spdifFrequency64KHz: return 64000;
973 case HDSP_spdifFrequency88_2KHz: return 88200;
974 case HDSP_spdifFrequency96KHz: return 96000;
975 case HDSP_spdifFrequency128KHz:
976 if (hdsp->io_type == H9632) return 128000;
977 break;
978 case HDSP_spdifFrequency176_4KHz:
979 if (hdsp->io_type == H9632) return 176400;
980 break;
981 case HDSP_spdifFrequency192KHz:
982 if (hdsp->io_type == H9632) return 192000;
983 break;
984 default:
985 break;
986 }
987 dev_warn(hdsp->card->dev,
988 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
989 rate_bits, status);
990 return 0;
991 }
992
993 static int hdsp_external_sample_rate(struct hdsp *hdsp)
994 {
995 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
996 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
997
998 /* For the 9632 card, there seems to be no bit for indicating external
999 * sample rate greater than 96kHz. The card reports the corresponding
1000 * single speed. So the best means seems to get spdif rate when
1001 * autosync reference is spdif */
1002 if (hdsp->io_type == H9632 &&
1003 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1004 return hdsp_spdif_sample_rate(hdsp);
1005
1006 switch (rate_bits) {
1007 case HDSP_systemFrequency32: return 32000;
1008 case HDSP_systemFrequency44_1: return 44100;
1009 case HDSP_systemFrequency48: return 48000;
1010 case HDSP_systemFrequency64: return 64000;
1011 case HDSP_systemFrequency88_2: return 88200;
1012 case HDSP_systemFrequency96: return 96000;
1013 default:
1014 return 0;
1015 }
1016 }
1017
1018 static void hdsp_compute_period_size(struct hdsp *hdsp)
1019 {
1020 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1021 }
1022
1023 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1024 {
1025 int position;
1026
1027 position = hdsp_read(hdsp, HDSP_statusRegister);
1028
1029 if (!hdsp->precise_ptr)
1030 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1031
1032 position &= HDSP_BufferPositionMask;
1033 position /= 4;
1034 position &= (hdsp->period_bytes/2) - 1;
1035 return position;
1036 }
1037
1038 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1039 {
1040 hdsp_write (hdsp, HDSP_resetPointer, 0);
1041 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1042 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1043 * requires (?) to write again DDS value after a reset pointer
1044 * (at least, it works like this) */
1045 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1046 }
1047
1048 static void hdsp_start_audio(struct hdsp *s)
1049 {
1050 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1051 hdsp_write(s, HDSP_controlRegister, s->control_register);
1052 }
1053
1054 static void hdsp_stop_audio(struct hdsp *s)
1055 {
1056 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1057 hdsp_write(s, HDSP_controlRegister, s->control_register);
1058 }
1059
1060 static void hdsp_silence_playback(struct hdsp *hdsp)
1061 {
1062 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1063 }
1064
1065 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1066 {
1067 int n;
1068
1069 spin_lock_irq(&s->lock);
1070
1071 frames >>= 7;
1072 n = 0;
1073 while (frames) {
1074 n++;
1075 frames >>= 1;
1076 }
1077
1078 s->control_register &= ~HDSP_LatencyMask;
1079 s->control_register |= hdsp_encode_latency(n);
1080
1081 hdsp_write(s, HDSP_controlRegister, s->control_register);
1082
1083 hdsp_compute_period_size(s);
1084
1085 spin_unlock_irq(&s->lock);
1086
1087 return 0;
1088 }
1089
1090 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1091 {
1092 u64 n;
1093
1094 if (rate >= 112000)
1095 rate /= 4;
1096 else if (rate >= 56000)
1097 rate /= 2;
1098
1099 n = DDS_NUMERATOR;
1100 n = div_u64(n, rate);
1101 /* n should be less than 2^32 for being written to FREQ register */
1102 snd_BUG_ON(n >> 32);
1103 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1104 value to write it after a reset */
1105 hdsp->dds_value = n;
1106 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1107 }
1108
1109 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1110 {
1111 int reject_if_open = 0;
1112 int current_rate;
1113 int rate_bits;
1114
1115 /* ASSUMPTION: hdsp->lock is either held, or
1116 there is no need for it (e.g. during module
1117 initialization).
1118 */
1119
1120 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1121 if (called_internally) {
1122 /* request from ctl or card initialization */
1123 dev_err(hdsp->card->dev,
1124 "device is not running as a clock master: cannot set sample rate.\n");
1125 return -1;
1126 } else {
1127 /* hw_param request while in AutoSync mode */
1128 int external_freq = hdsp_external_sample_rate(hdsp);
1129 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1130
1131 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1132 dev_info(hdsp->card->dev,
1133 "Detected ADAT in double speed mode\n");
1134 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1135 dev_info(hdsp->card->dev,
1136 "Detected ADAT in quad speed mode\n");
1137 else if (rate != external_freq) {
1138 dev_info(hdsp->card->dev,
1139 "No AutoSync source for requested rate\n");
1140 return -1;
1141 }
1142 }
1143 }
1144
1145 current_rate = hdsp->system_sample_rate;
1146
1147 /* Changing from a "single speed" to a "double speed" rate is
1148 not allowed if any substreams are open. This is because
1149 such a change causes a shift in the location of
1150 the DMA buffers and a reduction in the number of available
1151 buffers.
1152
1153 Note that a similar but essentially insoluble problem
1154 exists for externally-driven rate changes. All we can do
1155 is to flag rate changes in the read/write routines. */
1156
1157 if (rate > 96000 && hdsp->io_type != H9632)
1158 return -EINVAL;
1159
1160 switch (rate) {
1161 case 32000:
1162 if (current_rate > 48000)
1163 reject_if_open = 1;
1164 rate_bits = HDSP_Frequency32KHz;
1165 break;
1166 case 44100:
1167 if (current_rate > 48000)
1168 reject_if_open = 1;
1169 rate_bits = HDSP_Frequency44_1KHz;
1170 break;
1171 case 48000:
1172 if (current_rate > 48000)
1173 reject_if_open = 1;
1174 rate_bits = HDSP_Frequency48KHz;
1175 break;
1176 case 64000:
1177 if (current_rate <= 48000 || current_rate > 96000)
1178 reject_if_open = 1;
1179 rate_bits = HDSP_Frequency64KHz;
1180 break;
1181 case 88200:
1182 if (current_rate <= 48000 || current_rate > 96000)
1183 reject_if_open = 1;
1184 rate_bits = HDSP_Frequency88_2KHz;
1185 break;
1186 case 96000:
1187 if (current_rate <= 48000 || current_rate > 96000)
1188 reject_if_open = 1;
1189 rate_bits = HDSP_Frequency96KHz;
1190 break;
1191 case 128000:
1192 if (current_rate < 128000)
1193 reject_if_open = 1;
1194 rate_bits = HDSP_Frequency128KHz;
1195 break;
1196 case 176400:
1197 if (current_rate < 128000)
1198 reject_if_open = 1;
1199 rate_bits = HDSP_Frequency176_4KHz;
1200 break;
1201 case 192000:
1202 if (current_rate < 128000)
1203 reject_if_open = 1;
1204 rate_bits = HDSP_Frequency192KHz;
1205 break;
1206 default:
1207 return -EINVAL;
1208 }
1209
1210 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1211 dev_warn(hdsp->card->dev,
1212 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1213 hdsp->capture_pid,
1214 hdsp->playback_pid);
1215 return -EBUSY;
1216 }
1217
1218 hdsp->control_register &= ~HDSP_FrequencyMask;
1219 hdsp->control_register |= rate_bits;
1220 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1221
1222 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1223 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1224 hdsp_set_dds_value(hdsp, rate);
1225
1226 if (rate >= 128000) {
1227 hdsp->channel_map = channel_map_H9632_qs;
1228 } else if (rate > 48000) {
1229 if (hdsp->io_type == H9632)
1230 hdsp->channel_map = channel_map_H9632_ds;
1231 else
1232 hdsp->channel_map = channel_map_ds;
1233 } else {
1234 switch (hdsp->io_type) {
1235 case RPM:
1236 case Multiface:
1237 hdsp->channel_map = channel_map_mf_ss;
1238 break;
1239 case Digiface:
1240 case H9652:
1241 hdsp->channel_map = channel_map_df_ss;
1242 break;
1243 case H9632:
1244 hdsp->channel_map = channel_map_H9632_ss;
1245 break;
1246 default:
1247 /* should never happen */
1248 break;
1249 }
1250 }
1251
1252 hdsp->system_sample_rate = rate;
1253
1254 return 0;
1255 }
1256
1257 /*----------------------------------------------------------------------------
1258 MIDI
1259 ----------------------------------------------------------------------------*/
1260
1261 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1262 {
1263 /* the hardware already does the relevant bit-mask with 0xff */
1264 if (id)
1265 return hdsp_read(hdsp, HDSP_midiDataIn1);
1266 else
1267 return hdsp_read(hdsp, HDSP_midiDataIn0);
1268 }
1269
1270 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1271 {
1272 /* the hardware already does the relevant bit-mask with 0xff */
1273 if (id)
1274 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1275 else
1276 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1277 }
1278
1279 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1280 {
1281 if (id)
1282 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1283 else
1284 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1285 }
1286
1287 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1288 {
1289 int fifo_bytes_used;
1290
1291 if (id)
1292 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1293 else
1294 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1295
1296 if (fifo_bytes_used < 128)
1297 return 128 - fifo_bytes_used;
1298 else
1299 return 0;
1300 }
1301
1302 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1303 {
1304 while (snd_hdsp_midi_input_available (hdsp, id))
1305 snd_hdsp_midi_read_byte (hdsp, id);
1306 }
1307
1308 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1309 {
1310 unsigned long flags;
1311 int n_pending;
1312 int to_write;
1313 int i;
1314 unsigned char buf[128];
1315
1316 /* Output is not interrupt driven */
1317
1318 spin_lock_irqsave (&hmidi->lock, flags);
1319 if (hmidi->output) {
1320 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1321 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1322 if (n_pending > (int)sizeof (buf))
1323 n_pending = sizeof (buf);
1324
1325 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1326 for (i = 0; i < to_write; ++i)
1327 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1328 }
1329 }
1330 }
1331 }
1332 spin_unlock_irqrestore (&hmidi->lock, flags);
1333 return 0;
1334 }
1335
1336 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1337 {
1338 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1339 unsigned long flags;
1340 int n_pending;
1341 int i;
1342
1343 spin_lock_irqsave (&hmidi->lock, flags);
1344 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1345 if (hmidi->input) {
1346 if (n_pending > (int)sizeof (buf))
1347 n_pending = sizeof (buf);
1348 for (i = 0; i < n_pending; ++i)
1349 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1350 if (n_pending)
1351 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1352 } else {
1353 /* flush the MIDI input FIFO */
1354 while (--n_pending)
1355 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1356 }
1357 }
1358 hmidi->pending = 0;
1359 if (hmidi->id)
1360 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1361 else
1362 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1363 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1364 spin_unlock_irqrestore (&hmidi->lock, flags);
1365 return snd_hdsp_midi_output_write (hmidi);
1366 }
1367
1368 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1369 {
1370 struct hdsp *hdsp;
1371 struct hdsp_midi *hmidi;
1372 unsigned long flags;
1373 u32 ie;
1374
1375 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1376 hdsp = hmidi->hdsp;
1377 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1378 spin_lock_irqsave (&hdsp->lock, flags);
1379 if (up) {
1380 if (!(hdsp->control_register & ie)) {
1381 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1382 hdsp->control_register |= ie;
1383 }
1384 } else {
1385 hdsp->control_register &= ~ie;
1386 }
1387
1388 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1389 spin_unlock_irqrestore (&hdsp->lock, flags);
1390 }
1391
1392 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1393 {
1394 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1395 unsigned long flags;
1396
1397 snd_hdsp_midi_output_write(hmidi);
1398 spin_lock_irqsave (&hmidi->lock, flags);
1399
1400 /* this does not bump hmidi->istimer, because the
1401 kernel automatically removed the timer when it
1402 expired, and we are now adding it back, thus
1403 leaving istimer wherever it was set before.
1404 */
1405
1406 if (hmidi->istimer)
1407 mod_timer(&hmidi->timer, 1 + jiffies);
1408
1409 spin_unlock_irqrestore (&hmidi->lock, flags);
1410 }
1411
1412 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1413 {
1414 struct hdsp_midi *hmidi;
1415 unsigned long flags;
1416
1417 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1418 spin_lock_irqsave (&hmidi->lock, flags);
1419 if (up) {
1420 if (!hmidi->istimer) {
1421 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1422 0);
1423 mod_timer(&hmidi->timer, 1 + jiffies);
1424 hmidi->istimer++;
1425 }
1426 } else {
1427 if (hmidi->istimer && --hmidi->istimer <= 0)
1428 del_timer (&hmidi->timer);
1429 }
1430 spin_unlock_irqrestore (&hmidi->lock, flags);
1431 if (up)
1432 snd_hdsp_midi_output_write(hmidi);
1433 }
1434
1435 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1436 {
1437 struct hdsp_midi *hmidi;
1438
1439 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1440 spin_lock_irq (&hmidi->lock);
1441 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1442 hmidi->input = substream;
1443 spin_unlock_irq (&hmidi->lock);
1444
1445 return 0;
1446 }
1447
1448 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1449 {
1450 struct hdsp_midi *hmidi;
1451
1452 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1453 spin_lock_irq (&hmidi->lock);
1454 hmidi->output = substream;
1455 spin_unlock_irq (&hmidi->lock);
1456
1457 return 0;
1458 }
1459
1460 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1461 {
1462 struct hdsp_midi *hmidi;
1463
1464 snd_hdsp_midi_input_trigger (substream, 0);
1465
1466 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1467 spin_lock_irq (&hmidi->lock);
1468 hmidi->input = NULL;
1469 spin_unlock_irq (&hmidi->lock);
1470
1471 return 0;
1472 }
1473
1474 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1475 {
1476 struct hdsp_midi *hmidi;
1477
1478 snd_hdsp_midi_output_trigger (substream, 0);
1479
1480 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1481 spin_lock_irq (&hmidi->lock);
1482 hmidi->output = NULL;
1483 spin_unlock_irq (&hmidi->lock);
1484
1485 return 0;
1486 }
1487
1488 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1489 {
1490 .open = snd_hdsp_midi_output_open,
1491 .close = snd_hdsp_midi_output_close,
1492 .trigger = snd_hdsp_midi_output_trigger,
1493 };
1494
1495 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1496 {
1497 .open = snd_hdsp_midi_input_open,
1498 .close = snd_hdsp_midi_input_close,
1499 .trigger = snd_hdsp_midi_input_trigger,
1500 };
1501
1502 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1503 {
1504 char buf[40];
1505
1506 hdsp->midi[id].id = id;
1507 hdsp->midi[id].rmidi = NULL;
1508 hdsp->midi[id].input = NULL;
1509 hdsp->midi[id].output = NULL;
1510 hdsp->midi[id].hdsp = hdsp;
1511 hdsp->midi[id].istimer = 0;
1512 hdsp->midi[id].pending = 0;
1513 spin_lock_init (&hdsp->midi[id].lock);
1514
1515 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1516 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1517 return -1;
1518
1519 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1520 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1521
1522 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1523 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1524
1525 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1526 SNDRV_RAWMIDI_INFO_INPUT |
1527 SNDRV_RAWMIDI_INFO_DUPLEX;
1528
1529 return 0;
1530 }
1531
1532 /*-----------------------------------------------------------------------------
1533 Control Interface
1534 ----------------------------------------------------------------------------*/
1535
1536 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1537 {
1538 u32 val = 0;
1539 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1540 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1541 if (val & HDSP_SPDIFProfessional)
1542 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1543 else
1544 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1545 return val;
1546 }
1547
1548 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1549 {
1550 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1551 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1552 if (val & HDSP_SPDIFProfessional)
1553 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1554 else
1555 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1556 }
1557
1558 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1559 {
1560 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1561 uinfo->count = 1;
1562 return 0;
1563 }
1564
1565 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1566 {
1567 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1568
1569 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1570 return 0;
1571 }
1572
1573 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1574 {
1575 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1576 int change;
1577 u32 val;
1578
1579 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1580 spin_lock_irq(&hdsp->lock);
1581 change = val != hdsp->creg_spdif;
1582 hdsp->creg_spdif = val;
1583 spin_unlock_irq(&hdsp->lock);
1584 return change;
1585 }
1586
1587 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1588 {
1589 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1590 uinfo->count = 1;
1591 return 0;
1592 }
1593
1594 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1595 {
1596 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1597
1598 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1599 return 0;
1600 }
1601
1602 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1603 {
1604 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1605 int change;
1606 u32 val;
1607
1608 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1609 spin_lock_irq(&hdsp->lock);
1610 change = val != hdsp->creg_spdif_stream;
1611 hdsp->creg_spdif_stream = val;
1612 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1613 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1614 spin_unlock_irq(&hdsp->lock);
1615 return change;
1616 }
1617
1618 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1619 {
1620 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1621 uinfo->count = 1;
1622 return 0;
1623 }
1624
1625 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1626 {
1627 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1628 return 0;
1629 }
1630
1631 #define HDSP_SPDIF_IN(xname, xindex) \
1632 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1633 .name = xname, \
1634 .index = xindex, \
1635 .info = snd_hdsp_info_spdif_in, \
1636 .get = snd_hdsp_get_spdif_in, \
1637 .put = snd_hdsp_put_spdif_in }
1638
1639 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1640 {
1641 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1642 }
1643
1644 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1645 {
1646 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1647 hdsp->control_register |= hdsp_encode_spdif_in(in);
1648 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1649 return 0;
1650 }
1651
1652 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1653 {
1654 static const char * const texts[4] = {
1655 "Optical", "Coaxial", "Internal", "AES"
1656 };
1657 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1658
1659 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1660 texts);
1661 }
1662
1663 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1664 {
1665 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1666
1667 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1668 return 0;
1669 }
1670
1671 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1672 {
1673 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1674 int change;
1675 unsigned int val;
1676
1677 if (!snd_hdsp_use_is_exclusive(hdsp))
1678 return -EBUSY;
1679 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1680 spin_lock_irq(&hdsp->lock);
1681 change = val != hdsp_spdif_in(hdsp);
1682 if (change)
1683 hdsp_set_spdif_input(hdsp, val);
1684 spin_unlock_irq(&hdsp->lock);
1685 return change;
1686 }
1687
1688 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1689 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1690 .name = xname, \
1691 .private_value = xindex, \
1692 .info = snd_hdsp_info_toggle_setting, \
1693 .get = snd_hdsp_get_toggle_setting, \
1694 .put = snd_hdsp_put_toggle_setting \
1695 }
1696
1697 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1698 {
1699 return (hdsp->control_register & regmask) ? 1 : 0;
1700 }
1701
1702 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1703 {
1704 if (out)
1705 hdsp->control_register |= regmask;
1706 else
1707 hdsp->control_register &= ~regmask;
1708 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1709
1710 return 0;
1711 }
1712
1713 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1714
1715 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1716 struct snd_ctl_elem_value *ucontrol)
1717 {
1718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1719 u32 regmask = kcontrol->private_value;
1720
1721 spin_lock_irq(&hdsp->lock);
1722 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1723 spin_unlock_irq(&hdsp->lock);
1724 return 0;
1725 }
1726
1727 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1728 struct snd_ctl_elem_value *ucontrol)
1729 {
1730 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1731 u32 regmask = kcontrol->private_value;
1732 int change;
1733 unsigned int val;
1734
1735 if (!snd_hdsp_use_is_exclusive(hdsp))
1736 return -EBUSY;
1737 val = ucontrol->value.integer.value[0] & 1;
1738 spin_lock_irq(&hdsp->lock);
1739 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1740 if (change)
1741 hdsp_set_toggle_setting(hdsp, regmask, val);
1742 spin_unlock_irq(&hdsp->lock);
1743 return change;
1744 }
1745
1746 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1747 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1748 .name = xname, \
1749 .index = xindex, \
1750 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1751 .info = snd_hdsp_info_spdif_sample_rate, \
1752 .get = snd_hdsp_get_spdif_sample_rate \
1753 }
1754
1755 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1756 {
1757 static const char * const texts[] = {
1758 "32000", "44100", "48000", "64000", "88200", "96000",
1759 "None", "128000", "176400", "192000"
1760 };
1761 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1762
1763 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1764 texts);
1765 }
1766
1767 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1768 {
1769 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1770
1771 switch (hdsp_spdif_sample_rate(hdsp)) {
1772 case 32000:
1773 ucontrol->value.enumerated.item[0] = 0;
1774 break;
1775 case 44100:
1776 ucontrol->value.enumerated.item[0] = 1;
1777 break;
1778 case 48000:
1779 ucontrol->value.enumerated.item[0] = 2;
1780 break;
1781 case 64000:
1782 ucontrol->value.enumerated.item[0] = 3;
1783 break;
1784 case 88200:
1785 ucontrol->value.enumerated.item[0] = 4;
1786 break;
1787 case 96000:
1788 ucontrol->value.enumerated.item[0] = 5;
1789 break;
1790 case 128000:
1791 ucontrol->value.enumerated.item[0] = 7;
1792 break;
1793 case 176400:
1794 ucontrol->value.enumerated.item[0] = 8;
1795 break;
1796 case 192000:
1797 ucontrol->value.enumerated.item[0] = 9;
1798 break;
1799 default:
1800 ucontrol->value.enumerated.item[0] = 6;
1801 }
1802 return 0;
1803 }
1804
1805 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1806 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1807 .name = xname, \
1808 .index = xindex, \
1809 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1810 .info = snd_hdsp_info_system_sample_rate, \
1811 .get = snd_hdsp_get_system_sample_rate \
1812 }
1813
1814 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1815 {
1816 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1817 uinfo->count = 1;
1818 return 0;
1819 }
1820
1821 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1822 {
1823 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1824
1825 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1826 return 0;
1827 }
1828
1829 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1831 .name = xname, \
1832 .index = xindex, \
1833 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1834 .info = snd_hdsp_info_autosync_sample_rate, \
1835 .get = snd_hdsp_get_autosync_sample_rate \
1836 }
1837
1838 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1839 {
1840 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1841 static const char * const texts[] = {
1842 "32000", "44100", "48000", "64000", "88200", "96000",
1843 "None", "128000", "176400", "192000"
1844 };
1845
1846 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1847 texts);
1848 }
1849
1850 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1851 {
1852 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1853
1854 switch (hdsp_external_sample_rate(hdsp)) {
1855 case 32000:
1856 ucontrol->value.enumerated.item[0] = 0;
1857 break;
1858 case 44100:
1859 ucontrol->value.enumerated.item[0] = 1;
1860 break;
1861 case 48000:
1862 ucontrol->value.enumerated.item[0] = 2;
1863 break;
1864 case 64000:
1865 ucontrol->value.enumerated.item[0] = 3;
1866 break;
1867 case 88200:
1868 ucontrol->value.enumerated.item[0] = 4;
1869 break;
1870 case 96000:
1871 ucontrol->value.enumerated.item[0] = 5;
1872 break;
1873 case 128000:
1874 ucontrol->value.enumerated.item[0] = 7;
1875 break;
1876 case 176400:
1877 ucontrol->value.enumerated.item[0] = 8;
1878 break;
1879 case 192000:
1880 ucontrol->value.enumerated.item[0] = 9;
1881 break;
1882 default:
1883 ucontrol->value.enumerated.item[0] = 6;
1884 }
1885 return 0;
1886 }
1887
1888 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1889 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1890 .name = xname, \
1891 .index = xindex, \
1892 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1893 .info = snd_hdsp_info_system_clock_mode, \
1894 .get = snd_hdsp_get_system_clock_mode \
1895 }
1896
1897 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1898 {
1899 if (hdsp->control_register & HDSP_ClockModeMaster)
1900 return 0;
1901 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1902 return 0;
1903 return 1;
1904 }
1905
1906 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1907 {
1908 static const char * const texts[] = {"Master", "Slave" };
1909
1910 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1911 }
1912
1913 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1914 {
1915 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1916
1917 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1918 return 0;
1919 }
1920
1921 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1922 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1923 .name = xname, \
1924 .index = xindex, \
1925 .info = snd_hdsp_info_clock_source, \
1926 .get = snd_hdsp_get_clock_source, \
1927 .put = snd_hdsp_put_clock_source \
1928 }
1929
1930 static int hdsp_clock_source(struct hdsp *hdsp)
1931 {
1932 if (hdsp->control_register & HDSP_ClockModeMaster) {
1933 switch (hdsp->system_sample_rate) {
1934 case 32000:
1935 return 1;
1936 case 44100:
1937 return 2;
1938 case 48000:
1939 return 3;
1940 case 64000:
1941 return 4;
1942 case 88200:
1943 return 5;
1944 case 96000:
1945 return 6;
1946 case 128000:
1947 return 7;
1948 case 176400:
1949 return 8;
1950 case 192000:
1951 return 9;
1952 default:
1953 return 3;
1954 }
1955 } else {
1956 return 0;
1957 }
1958 }
1959
1960 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1961 {
1962 int rate;
1963 switch (mode) {
1964 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1965 if (hdsp_external_sample_rate(hdsp) != 0) {
1966 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1967 hdsp->control_register &= ~HDSP_ClockModeMaster;
1968 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1969 return 0;
1970 }
1971 }
1972 return -1;
1973 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1974 rate = 32000;
1975 break;
1976 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1977 rate = 44100;
1978 break;
1979 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1980 rate = 48000;
1981 break;
1982 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1983 rate = 64000;
1984 break;
1985 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1986 rate = 88200;
1987 break;
1988 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1989 rate = 96000;
1990 break;
1991 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1992 rate = 128000;
1993 break;
1994 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1995 rate = 176400;
1996 break;
1997 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
1998 rate = 192000;
1999 break;
2000 default:
2001 rate = 48000;
2002 }
2003 hdsp->control_register |= HDSP_ClockModeMaster;
2004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2005 hdsp_set_rate(hdsp, rate, 1);
2006 return 0;
2007 }
2008
2009 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2010 {
2011 static const char * const texts[] = {
2012 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2013 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2014 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2015 "Internal 192.0 KHz"
2016 };
2017 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2018
2019 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2020 texts);
2021 }
2022
2023 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2024 {
2025 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2026
2027 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2028 return 0;
2029 }
2030
2031 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2032 {
2033 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2034 int change;
2035 int val;
2036
2037 if (!snd_hdsp_use_is_exclusive(hdsp))
2038 return -EBUSY;
2039 val = ucontrol->value.enumerated.item[0];
2040 if (val < 0) val = 0;
2041 if (hdsp->io_type == H9632) {
2042 if (val > 9)
2043 val = 9;
2044 } else {
2045 if (val > 6)
2046 val = 6;
2047 }
2048 spin_lock_irq(&hdsp->lock);
2049 if (val != hdsp_clock_source(hdsp))
2050 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2051 else
2052 change = 0;
2053 spin_unlock_irq(&hdsp->lock);
2054 return change;
2055 }
2056
2057 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2058
2059 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2060 {
2061 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2062
2063 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2064 return 0;
2065 }
2066
2067 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2068 {
2069 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2070 int change;
2071
2072 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2073 if (change)
2074 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2075 return change;
2076 }
2077
2078 #define HDSP_DA_GAIN(xname, xindex) \
2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2080 .name = xname, \
2081 .index = xindex, \
2082 .info = snd_hdsp_info_da_gain, \
2083 .get = snd_hdsp_get_da_gain, \
2084 .put = snd_hdsp_put_da_gain \
2085 }
2086
2087 static int hdsp_da_gain(struct hdsp *hdsp)
2088 {
2089 switch (hdsp->control_register & HDSP_DAGainMask) {
2090 case HDSP_DAGainHighGain:
2091 return 0;
2092 case HDSP_DAGainPlus4dBu:
2093 return 1;
2094 case HDSP_DAGainMinus10dBV:
2095 return 2;
2096 default:
2097 return 1;
2098 }
2099 }
2100
2101 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2102 {
2103 hdsp->control_register &= ~HDSP_DAGainMask;
2104 switch (mode) {
2105 case 0:
2106 hdsp->control_register |= HDSP_DAGainHighGain;
2107 break;
2108 case 1:
2109 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2110 break;
2111 case 2:
2112 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2113 break;
2114 default:
2115 return -1;
2116
2117 }
2118 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2119 return 0;
2120 }
2121
2122 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2123 {
2124 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2125
2126 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2127 }
2128
2129 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2130 {
2131 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2132
2133 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2134 return 0;
2135 }
2136
2137 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2138 {
2139 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2140 int change;
2141 int val;
2142
2143 if (!snd_hdsp_use_is_exclusive(hdsp))
2144 return -EBUSY;
2145 val = ucontrol->value.enumerated.item[0];
2146 if (val < 0) val = 0;
2147 if (val > 2) val = 2;
2148 spin_lock_irq(&hdsp->lock);
2149 if (val != hdsp_da_gain(hdsp))
2150 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2151 else
2152 change = 0;
2153 spin_unlock_irq(&hdsp->lock);
2154 return change;
2155 }
2156
2157 #define HDSP_AD_GAIN(xname, xindex) \
2158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2159 .name = xname, \
2160 .index = xindex, \
2161 .info = snd_hdsp_info_ad_gain, \
2162 .get = snd_hdsp_get_ad_gain, \
2163 .put = snd_hdsp_put_ad_gain \
2164 }
2165
2166 static int hdsp_ad_gain(struct hdsp *hdsp)
2167 {
2168 switch (hdsp->control_register & HDSP_ADGainMask) {
2169 case HDSP_ADGainMinus10dBV:
2170 return 0;
2171 case HDSP_ADGainPlus4dBu:
2172 return 1;
2173 case HDSP_ADGainLowGain:
2174 return 2;
2175 default:
2176 return 1;
2177 }
2178 }
2179
2180 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2181 {
2182 hdsp->control_register &= ~HDSP_ADGainMask;
2183 switch (mode) {
2184 case 0:
2185 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2186 break;
2187 case 1:
2188 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2189 break;
2190 case 2:
2191 hdsp->control_register |= HDSP_ADGainLowGain;
2192 break;
2193 default:
2194 return -1;
2195
2196 }
2197 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2198 return 0;
2199 }
2200
2201 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2202 {
2203 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2204
2205 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2206 }
2207
2208 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2209 {
2210 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2211
2212 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2213 return 0;
2214 }
2215
2216 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2217 {
2218 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2219 int change;
2220 int val;
2221
2222 if (!snd_hdsp_use_is_exclusive(hdsp))
2223 return -EBUSY;
2224 val = ucontrol->value.enumerated.item[0];
2225 if (val < 0) val = 0;
2226 if (val > 2) val = 2;
2227 spin_lock_irq(&hdsp->lock);
2228 if (val != hdsp_ad_gain(hdsp))
2229 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2230 else
2231 change = 0;
2232 spin_unlock_irq(&hdsp->lock);
2233 return change;
2234 }
2235
2236 #define HDSP_PHONE_GAIN(xname, xindex) \
2237 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2238 .name = xname, \
2239 .index = xindex, \
2240 .info = snd_hdsp_info_phone_gain, \
2241 .get = snd_hdsp_get_phone_gain, \
2242 .put = snd_hdsp_put_phone_gain \
2243 }
2244
2245 static int hdsp_phone_gain(struct hdsp *hdsp)
2246 {
2247 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2248 case HDSP_PhoneGain0dB:
2249 return 0;
2250 case HDSP_PhoneGainMinus6dB:
2251 return 1;
2252 case HDSP_PhoneGainMinus12dB:
2253 return 2;
2254 default:
2255 return 0;
2256 }
2257 }
2258
2259 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2260 {
2261 hdsp->control_register &= ~HDSP_PhoneGainMask;
2262 switch (mode) {
2263 case 0:
2264 hdsp->control_register |= HDSP_PhoneGain0dB;
2265 break;
2266 case 1:
2267 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2268 break;
2269 case 2:
2270 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2271 break;
2272 default:
2273 return -1;
2274
2275 }
2276 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2277 return 0;
2278 }
2279
2280 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2281 {
2282 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2283
2284 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2285 }
2286
2287 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2288 {
2289 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2290
2291 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2292 return 0;
2293 }
2294
2295 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2296 {
2297 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2298 int change;
2299 int val;
2300
2301 if (!snd_hdsp_use_is_exclusive(hdsp))
2302 return -EBUSY;
2303 val = ucontrol->value.enumerated.item[0];
2304 if (val < 0) val = 0;
2305 if (val > 2) val = 2;
2306 spin_lock_irq(&hdsp->lock);
2307 if (val != hdsp_phone_gain(hdsp))
2308 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2309 else
2310 change = 0;
2311 spin_unlock_irq(&hdsp->lock);
2312 return change;
2313 }
2314
2315 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2316 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2317 .name = xname, \
2318 .index = xindex, \
2319 .info = snd_hdsp_info_pref_sync_ref, \
2320 .get = snd_hdsp_get_pref_sync_ref, \
2321 .put = snd_hdsp_put_pref_sync_ref \
2322 }
2323
2324 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2325 {
2326 /* Notice that this looks at the requested sync source,
2327 not the one actually in use.
2328 */
2329
2330 switch (hdsp->control_register & HDSP_SyncRefMask) {
2331 case HDSP_SyncRef_ADAT1:
2332 return HDSP_SYNC_FROM_ADAT1;
2333 case HDSP_SyncRef_ADAT2:
2334 return HDSP_SYNC_FROM_ADAT2;
2335 case HDSP_SyncRef_ADAT3:
2336 return HDSP_SYNC_FROM_ADAT3;
2337 case HDSP_SyncRef_SPDIF:
2338 return HDSP_SYNC_FROM_SPDIF;
2339 case HDSP_SyncRef_WORD:
2340 return HDSP_SYNC_FROM_WORD;
2341 case HDSP_SyncRef_ADAT_SYNC:
2342 return HDSP_SYNC_FROM_ADAT_SYNC;
2343 default:
2344 return HDSP_SYNC_FROM_WORD;
2345 }
2346 return 0;
2347 }
2348
2349 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2350 {
2351 hdsp->control_register &= ~HDSP_SyncRefMask;
2352 switch (pref) {
2353 case HDSP_SYNC_FROM_ADAT1:
2354 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2355 break;
2356 case HDSP_SYNC_FROM_ADAT2:
2357 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2358 break;
2359 case HDSP_SYNC_FROM_ADAT3:
2360 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2361 break;
2362 case HDSP_SYNC_FROM_SPDIF:
2363 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2364 break;
2365 case HDSP_SYNC_FROM_WORD:
2366 hdsp->control_register |= HDSP_SyncRef_WORD;
2367 break;
2368 case HDSP_SYNC_FROM_ADAT_SYNC:
2369 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2370 break;
2371 default:
2372 return -1;
2373 }
2374 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2375 return 0;
2376 }
2377
2378 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2379 {
2380 static const char * const texts[] = {
2381 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2382 };
2383 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2384 int num_items;
2385
2386 switch (hdsp->io_type) {
2387 case Digiface:
2388 case H9652:
2389 num_items = 6;
2390 break;
2391 case Multiface:
2392 num_items = 4;
2393 break;
2394 case H9632:
2395 num_items = 3;
2396 break;
2397 default:
2398 return -EINVAL;
2399 }
2400
2401 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2402 }
2403
2404 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2405 {
2406 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2407
2408 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2409 return 0;
2410 }
2411
2412 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2413 {
2414 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2415 int change, max;
2416 unsigned int val;
2417
2418 if (!snd_hdsp_use_is_exclusive(hdsp))
2419 return -EBUSY;
2420
2421 switch (hdsp->io_type) {
2422 case Digiface:
2423 case H9652:
2424 max = 6;
2425 break;
2426 case Multiface:
2427 max = 4;
2428 break;
2429 case H9632:
2430 max = 3;
2431 break;
2432 default:
2433 return -EIO;
2434 }
2435
2436 val = ucontrol->value.enumerated.item[0] % max;
2437 spin_lock_irq(&hdsp->lock);
2438 change = (int)val != hdsp_pref_sync_ref(hdsp);
2439 hdsp_set_pref_sync_ref(hdsp, val);
2440 spin_unlock_irq(&hdsp->lock);
2441 return change;
2442 }
2443
2444 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2445 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2446 .name = xname, \
2447 .index = xindex, \
2448 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2449 .info = snd_hdsp_info_autosync_ref, \
2450 .get = snd_hdsp_get_autosync_ref, \
2451 }
2452
2453 static int hdsp_autosync_ref(struct hdsp *hdsp)
2454 {
2455 /* This looks at the autosync selected sync reference */
2456 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2457
2458 switch (status2 & HDSP_SelSyncRefMask) {
2459 case HDSP_SelSyncRef_WORD:
2460 return HDSP_AUTOSYNC_FROM_WORD;
2461 case HDSP_SelSyncRef_ADAT_SYNC:
2462 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2463 case HDSP_SelSyncRef_SPDIF:
2464 return HDSP_AUTOSYNC_FROM_SPDIF;
2465 case HDSP_SelSyncRefMask:
2466 return HDSP_AUTOSYNC_FROM_NONE;
2467 case HDSP_SelSyncRef_ADAT1:
2468 return HDSP_AUTOSYNC_FROM_ADAT1;
2469 case HDSP_SelSyncRef_ADAT2:
2470 return HDSP_AUTOSYNC_FROM_ADAT2;
2471 case HDSP_SelSyncRef_ADAT3:
2472 return HDSP_AUTOSYNC_FROM_ADAT3;
2473 default:
2474 return HDSP_AUTOSYNC_FROM_WORD;
2475 }
2476 return 0;
2477 }
2478
2479 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2480 {
2481 static const char * const texts[] = {
2482 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2483 };
2484
2485 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2486 }
2487
2488 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2489 {
2490 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2491
2492 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2493 return 0;
2494 }
2495
2496 #define HDSP_PRECISE_POINTER(xname, xindex) \
2497 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2498 .name = xname, \
2499 .index = xindex, \
2500 .info = snd_hdsp_info_precise_pointer, \
2501 .get = snd_hdsp_get_precise_pointer, \
2502 .put = snd_hdsp_put_precise_pointer \
2503 }
2504
2505 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2506 {
2507 if (precise)
2508 hdsp->precise_ptr = 1;
2509 else
2510 hdsp->precise_ptr = 0;
2511 return 0;
2512 }
2513
2514 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2515
2516 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2517 {
2518 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2519
2520 spin_lock_irq(&hdsp->lock);
2521 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2522 spin_unlock_irq(&hdsp->lock);
2523 return 0;
2524 }
2525
2526 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2527 {
2528 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2529 int change;
2530 unsigned int val;
2531
2532 if (!snd_hdsp_use_is_exclusive(hdsp))
2533 return -EBUSY;
2534 val = ucontrol->value.integer.value[0] & 1;
2535 spin_lock_irq(&hdsp->lock);
2536 change = (int)val != hdsp->precise_ptr;
2537 hdsp_set_precise_pointer(hdsp, val);
2538 spin_unlock_irq(&hdsp->lock);
2539 return change;
2540 }
2541
2542 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2543 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2544 .name = xname, \
2545 .index = xindex, \
2546 .info = snd_hdsp_info_use_midi_work, \
2547 .get = snd_hdsp_get_use_midi_work, \
2548 .put = snd_hdsp_put_use_midi_work \
2549 }
2550
2551 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2552 {
2553 if (use_work)
2554 hdsp->use_midi_work = 1;
2555 else
2556 hdsp->use_midi_work = 0;
2557 return 0;
2558 }
2559
2560 #define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info
2561
2562 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2563 {
2564 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2565
2566 spin_lock_irq(&hdsp->lock);
2567 ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2568 spin_unlock_irq(&hdsp->lock);
2569 return 0;
2570 }
2571
2572 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2573 {
2574 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2575 int change;
2576 unsigned int val;
2577
2578 if (!snd_hdsp_use_is_exclusive(hdsp))
2579 return -EBUSY;
2580 val = ucontrol->value.integer.value[0] & 1;
2581 spin_lock_irq(&hdsp->lock);
2582 change = (int)val != hdsp->use_midi_work;
2583 hdsp_set_use_midi_work(hdsp, val);
2584 spin_unlock_irq(&hdsp->lock);
2585 return change;
2586 }
2587
2588 #define HDSP_MIXER(xname, xindex) \
2589 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2590 .name = xname, \
2591 .index = xindex, \
2592 .device = 0, \
2593 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2594 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2595 .info = snd_hdsp_info_mixer, \
2596 .get = snd_hdsp_get_mixer, \
2597 .put = snd_hdsp_put_mixer \
2598 }
2599
2600 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2601 {
2602 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2603 uinfo->count = 3;
2604 uinfo->value.integer.min = 0;
2605 uinfo->value.integer.max = 65536;
2606 uinfo->value.integer.step = 1;
2607 return 0;
2608 }
2609
2610 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2611 {
2612 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2613 int source;
2614 int destination;
2615 int addr;
2616
2617 source = ucontrol->value.integer.value[0];
2618 destination = ucontrol->value.integer.value[1];
2619
2620 if (source >= hdsp->max_channels)
2621 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2622 else
2623 addr = hdsp_input_to_output_key(hdsp,source, destination);
2624
2625 spin_lock_irq(&hdsp->lock);
2626 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2627 spin_unlock_irq(&hdsp->lock);
2628 return 0;
2629 }
2630
2631 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2632 {
2633 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2634 int change;
2635 int source;
2636 int destination;
2637 int gain;
2638 int addr;
2639
2640 if (!snd_hdsp_use_is_exclusive(hdsp))
2641 return -EBUSY;
2642
2643 source = ucontrol->value.integer.value[0];
2644 destination = ucontrol->value.integer.value[1];
2645
2646 if (source >= hdsp->max_channels)
2647 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2648 else
2649 addr = hdsp_input_to_output_key(hdsp,source, destination);
2650
2651 gain = ucontrol->value.integer.value[2];
2652
2653 spin_lock_irq(&hdsp->lock);
2654 change = gain != hdsp_read_gain(hdsp, addr);
2655 if (change)
2656 hdsp_write_gain(hdsp, addr, gain);
2657 spin_unlock_irq(&hdsp->lock);
2658 return change;
2659 }
2660
2661 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2662 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2663 .name = xname, \
2664 .index = xindex, \
2665 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2666 .info = snd_hdsp_info_sync_check, \
2667 .get = snd_hdsp_get_wc_sync_check \
2668 }
2669
2670 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2671 {
2672 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2673
2674 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2675 }
2676
2677 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2678 {
2679 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2680 if (status2 & HDSP_wc_lock) {
2681 if (status2 & HDSP_wc_sync)
2682 return 2;
2683 else
2684 return 1;
2685 } else
2686 return 0;
2687 return 0;
2688 }
2689
2690 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2691 {
2692 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2693
2694 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2695 return 0;
2696 }
2697
2698 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2699 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2700 .name = xname, \
2701 .index = xindex, \
2702 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2703 .info = snd_hdsp_info_sync_check, \
2704 .get = snd_hdsp_get_spdif_sync_check \
2705 }
2706
2707 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2708 {
2709 int status = hdsp_read(hdsp, HDSP_statusRegister);
2710 if (status & HDSP_SPDIFErrorFlag)
2711 return 0;
2712 else {
2713 if (status & HDSP_SPDIFSync)
2714 return 2;
2715 else
2716 return 1;
2717 }
2718 return 0;
2719 }
2720
2721 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2722 {
2723 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2724
2725 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2726 return 0;
2727 }
2728
2729 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2730 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2731 .name = xname, \
2732 .index = xindex, \
2733 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2734 .info = snd_hdsp_info_sync_check, \
2735 .get = snd_hdsp_get_adatsync_sync_check \
2736 }
2737
2738 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2739 {
2740 int status = hdsp_read(hdsp, HDSP_statusRegister);
2741 if (status & HDSP_TimecodeLock) {
2742 if (status & HDSP_TimecodeSync)
2743 return 2;
2744 else
2745 return 1;
2746 } else
2747 return 0;
2748 }
2749
2750 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2751 {
2752 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2753
2754 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2755 return 0;
2756 }
2757
2758 #define HDSP_ADAT_SYNC_CHECK \
2759 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2760 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2761 .info = snd_hdsp_info_sync_check, \
2762 .get = snd_hdsp_get_adat_sync_check \
2763 }
2764
2765 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2766 {
2767 int status = hdsp_read(hdsp, HDSP_statusRegister);
2768
2769 if (status & (HDSP_Lock0>>idx)) {
2770 if (status & (HDSP_Sync0>>idx))
2771 return 2;
2772 else
2773 return 1;
2774 } else
2775 return 0;
2776 }
2777
2778 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2779 {
2780 int offset;
2781 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2782
2783 offset = ucontrol->id.index - 1;
2784 if (snd_BUG_ON(offset < 0))
2785 return -EINVAL;
2786
2787 switch (hdsp->io_type) {
2788 case Digiface:
2789 case H9652:
2790 if (offset >= 3)
2791 return -EINVAL;
2792 break;
2793 case Multiface:
2794 case H9632:
2795 if (offset >= 1)
2796 return -EINVAL;
2797 break;
2798 default:
2799 return -EIO;
2800 }
2801
2802 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2803 return 0;
2804 }
2805
2806 #define HDSP_DDS_OFFSET(xname, xindex) \
2807 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2808 .name = xname, \
2809 .index = xindex, \
2810 .info = snd_hdsp_info_dds_offset, \
2811 .get = snd_hdsp_get_dds_offset, \
2812 .put = snd_hdsp_put_dds_offset \
2813 }
2814
2815 static int hdsp_dds_offset(struct hdsp *hdsp)
2816 {
2817 u64 n;
2818 unsigned int dds_value = hdsp->dds_value;
2819 int system_sample_rate = hdsp->system_sample_rate;
2820
2821 if (!dds_value)
2822 return 0;
2823
2824 n = DDS_NUMERATOR;
2825 /*
2826 * dds_value = n / rate
2827 * rate = n / dds_value
2828 */
2829 n = div_u64(n, dds_value);
2830 if (system_sample_rate >= 112000)
2831 n *= 4;
2832 else if (system_sample_rate >= 56000)
2833 n *= 2;
2834 return ((int)n) - system_sample_rate;
2835 }
2836
2837 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2838 {
2839 int rate = hdsp->system_sample_rate + offset_hz;
2840 hdsp_set_dds_value(hdsp, rate);
2841 return 0;
2842 }
2843
2844 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2845 {
2846 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2847 uinfo->count = 1;
2848 uinfo->value.integer.min = -5000;
2849 uinfo->value.integer.max = 5000;
2850 return 0;
2851 }
2852
2853 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2854 {
2855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2856
2857 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2858 return 0;
2859 }
2860
2861 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2862 {
2863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2864 int change;
2865 int val;
2866
2867 if (!snd_hdsp_use_is_exclusive(hdsp))
2868 return -EBUSY;
2869 val = ucontrol->value.integer.value[0];
2870 spin_lock_irq(&hdsp->lock);
2871 if (val != hdsp_dds_offset(hdsp))
2872 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2873 else
2874 change = 0;
2875 spin_unlock_irq(&hdsp->lock);
2876 return change;
2877 }
2878
2879 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2880 HDSP_DA_GAIN("DA Gain", 0),
2881 HDSP_AD_GAIN("AD Gain", 0),
2882 HDSP_PHONE_GAIN("Phones Gain", 0),
2883 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2884 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2885 };
2886
2887 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2888 {
2889 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2890 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2891 .info = snd_hdsp_control_spdif_info,
2892 .get = snd_hdsp_control_spdif_get,
2893 .put = snd_hdsp_control_spdif_put,
2894 },
2895 {
2896 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2897 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2898 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2899 .info = snd_hdsp_control_spdif_stream_info,
2900 .get = snd_hdsp_control_spdif_stream_get,
2901 .put = snd_hdsp_control_spdif_stream_put,
2902 },
2903 {
2904 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2905 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2906 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2907 .info = snd_hdsp_control_spdif_mask_info,
2908 .get = snd_hdsp_control_spdif_mask_get,
2909 .private_value = IEC958_AES0_NONAUDIO |
2910 IEC958_AES0_PROFESSIONAL |
2911 IEC958_AES0_CON_EMPHASIS,
2912 },
2913 {
2914 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2915 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2916 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2917 .info = snd_hdsp_control_spdif_mask_info,
2918 .get = snd_hdsp_control_spdif_mask_get,
2919 .private_value = IEC958_AES0_NONAUDIO |
2920 IEC958_AES0_PROFESSIONAL |
2921 IEC958_AES0_PRO_EMPHASIS,
2922 },
2923 HDSP_MIXER("Mixer", 0),
2924 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2925 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2926 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2927 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2928 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2929 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2930 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2931 {
2932 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2933 .name = "Sample Clock Source Locking",
2934 .info = snd_hdsp_info_clock_source_lock,
2935 .get = snd_hdsp_get_clock_source_lock,
2936 .put = snd_hdsp_put_clock_source_lock,
2937 },
2938 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2939 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2940 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2941 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2942 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2943 /* 'External Rate' complies with the alsa control naming scheme */
2944 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2945 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2946 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2947 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2948 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2949 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2950 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2951 };
2952
2953
2954 static int hdsp_rpm_input12(struct hdsp *hdsp)
2955 {
2956 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2957 case HDSP_RPM_Inp12_Phon_6dB:
2958 return 0;
2959 case HDSP_RPM_Inp12_Phon_n6dB:
2960 return 2;
2961 case HDSP_RPM_Inp12_Line_0dB:
2962 return 3;
2963 case HDSP_RPM_Inp12_Line_n6dB:
2964 return 4;
2965 }
2966 return 1;
2967 }
2968
2969
2970 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2971 {
2972 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2973
2974 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2975 return 0;
2976 }
2977
2978
2979 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2980 {
2981 hdsp->control_register &= ~HDSP_RPM_Inp12;
2982 switch (mode) {
2983 case 0:
2984 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2985 break;
2986 case 1:
2987 break;
2988 case 2:
2989 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2990 break;
2991 case 3:
2992 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2993 break;
2994 case 4:
2995 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2996 break;
2997 default:
2998 return -1;
2999 }
3000
3001 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3002 return 0;
3003 }
3004
3005
3006 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3007 {
3008 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3009 int change;
3010 int val;
3011
3012 if (!snd_hdsp_use_is_exclusive(hdsp))
3013 return -EBUSY;
3014 val = ucontrol->value.enumerated.item[0];
3015 if (val < 0)
3016 val = 0;
3017 if (val > 4)
3018 val = 4;
3019 spin_lock_irq(&hdsp->lock);
3020 if (val != hdsp_rpm_input12(hdsp))
3021 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3022 else
3023 change = 0;
3024 spin_unlock_irq(&hdsp->lock);
3025 return change;
3026 }
3027
3028
3029 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3030 {
3031 static const char * const texts[] = {
3032 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3033 };
3034
3035 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3036 }
3037
3038
3039 static int hdsp_rpm_input34(struct hdsp *hdsp)
3040 {
3041 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3042 case HDSP_RPM_Inp34_Phon_6dB:
3043 return 0;
3044 case HDSP_RPM_Inp34_Phon_n6dB:
3045 return 2;
3046 case HDSP_RPM_Inp34_Line_0dB:
3047 return 3;
3048 case HDSP_RPM_Inp34_Line_n6dB:
3049 return 4;
3050 }
3051 return 1;
3052 }
3053
3054
3055 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3056 {
3057 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3058
3059 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3060 return 0;
3061 }
3062
3063
3064 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3065 {
3066 hdsp->control_register &= ~HDSP_RPM_Inp34;
3067 switch (mode) {
3068 case 0:
3069 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3070 break;
3071 case 1:
3072 break;
3073 case 2:
3074 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3075 break;
3076 case 3:
3077 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3078 break;
3079 case 4:
3080 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3081 break;
3082 default:
3083 return -1;
3084 }
3085
3086 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3087 return 0;
3088 }
3089
3090
3091 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3092 {
3093 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3094 int change;
3095 int val;
3096
3097 if (!snd_hdsp_use_is_exclusive(hdsp))
3098 return -EBUSY;
3099 val = ucontrol->value.enumerated.item[0];
3100 if (val < 0)
3101 val = 0;
3102 if (val > 4)
3103 val = 4;
3104 spin_lock_irq(&hdsp->lock);
3105 if (val != hdsp_rpm_input34(hdsp))
3106 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3107 else
3108 change = 0;
3109 spin_unlock_irq(&hdsp->lock);
3110 return change;
3111 }
3112
3113
3114 /* RPM Bypass switch */
3115 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3116 {
3117 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3118 }
3119
3120
3121 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3122 {
3123 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3124
3125 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3126 return 0;
3127 }
3128
3129
3130 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3131 {
3132 if (on)
3133 hdsp->control_register |= HDSP_RPM_Bypass;
3134 else
3135 hdsp->control_register &= ~HDSP_RPM_Bypass;
3136 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3137 return 0;
3138 }
3139
3140
3141 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3142 {
3143 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3144 int change;
3145 unsigned int val;
3146
3147 if (!snd_hdsp_use_is_exclusive(hdsp))
3148 return -EBUSY;
3149 val = ucontrol->value.integer.value[0] & 1;
3150 spin_lock_irq(&hdsp->lock);
3151 change = (int)val != hdsp_rpm_bypass(hdsp);
3152 hdsp_set_rpm_bypass(hdsp, val);
3153 spin_unlock_irq(&hdsp->lock);
3154 return change;
3155 }
3156
3157
3158 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3159 {
3160 static const char * const texts[] = {"On", "Off"};
3161
3162 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3163 }
3164
3165
3166 /* RPM Disconnect switch */
3167 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3168 {
3169 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3170 }
3171
3172
3173 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3174 {
3175 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3176
3177 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3178 return 0;
3179 }
3180
3181
3182 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3183 {
3184 if (on)
3185 hdsp->control_register |= HDSP_RPM_Disconnect;
3186 else
3187 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3188 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3189 return 0;
3190 }
3191
3192
3193 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3194 {
3195 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3196 int change;
3197 unsigned int val;
3198
3199 if (!snd_hdsp_use_is_exclusive(hdsp))
3200 return -EBUSY;
3201 val = ucontrol->value.integer.value[0] & 1;
3202 spin_lock_irq(&hdsp->lock);
3203 change = (int)val != hdsp_rpm_disconnect(hdsp);
3204 hdsp_set_rpm_disconnect(hdsp, val);
3205 spin_unlock_irq(&hdsp->lock);
3206 return change;
3207 }
3208
3209 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3210 {
3211 static const char * const texts[] = {"On", "Off"};
3212
3213 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3214 }
3215
3216 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3217 {
3218 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3219 .name = "RPM Bypass",
3220 .get = snd_hdsp_get_rpm_bypass,
3221 .put = snd_hdsp_put_rpm_bypass,
3222 .info = snd_hdsp_info_rpm_bypass
3223 },
3224 {
3225 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3226 .name = "RPM Disconnect",
3227 .get = snd_hdsp_get_rpm_disconnect,
3228 .put = snd_hdsp_put_rpm_disconnect,
3229 .info = snd_hdsp_info_rpm_disconnect
3230 },
3231 {
3232 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3233 .name = "Input 1/2",
3234 .get = snd_hdsp_get_rpm_input12,
3235 .put = snd_hdsp_put_rpm_input12,
3236 .info = snd_hdsp_info_rpm_input
3237 },
3238 {
3239 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3240 .name = "Input 3/4",
3241 .get = snd_hdsp_get_rpm_input34,
3242 .put = snd_hdsp_put_rpm_input34,
3243 .info = snd_hdsp_info_rpm_input
3244 },
3245 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3246 HDSP_MIXER("Mixer", 0)
3247 };
3248
3249 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3250 HDSP_TOGGLE_SETTING("Analog Extension Board",
3251 HDSP_AnalogExtensionBoard);
3252 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3253
3254
3255 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3256 {
3257 return hdsp->io_loopback & (1 << channel);
3258 }
3259
3260 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3261 {
3262 if (hdsp_loopback_get(hdsp, channel) == enable)
3263 return 0;
3264
3265 hdsp->io_loopback ^= (1 << channel);
3266
3267 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3268
3269 return 1;
3270 }
3271
3272 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3273 struct snd_ctl_elem_value *const ucontrol)
3274 {
3275 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3276 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3277
3278 if (channel >= hdsp->max_channels)
3279 return -ENOENT;
3280
3281 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3282
3283 return 0;
3284 }
3285
3286 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3287 struct snd_ctl_elem_value *const ucontrol)
3288 {
3289 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3290 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3291 const bool enable = ucontrol->value.integer.value[0] & 1;
3292
3293 if (channel >= hdsp->max_channels)
3294 return -ENOENT;
3295
3296 return hdsp_loopback_set(hdsp, channel, enable);
3297 }
3298
3299 static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3300 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3301 .name = "Output Loopback",
3302 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3303 .info = snd_ctl_boolean_mono_info,
3304 .get = snd_hdsp_loopback_get,
3305 .put = snd_hdsp_loopback_put
3306 };
3307
3308 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3309 {
3310 unsigned int idx;
3311 int err;
3312 struct snd_kcontrol *kctl;
3313
3314 if (hdsp->io_type == RPM) {
3315 /* RPM Bypass, Disconnect and Input switches */
3316 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3317 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3318 if (err < 0)
3319 return err;
3320 }
3321 return 0;
3322 }
3323
3324 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3325 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3326 return err;
3327 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3328 hdsp->spdif_ctl = kctl;
3329 }
3330
3331 /* ADAT SyncCheck status */
3332 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3333 snd_hdsp_adat_sync_check.index = 1;
3334 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3335 return err;
3336 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3337 for (idx = 1; idx < 3; ++idx) {
3338 snd_hdsp_adat_sync_check.index = idx+1;
3339 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3340 return err;
3341 }
3342 }
3343
3344 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3345 if (hdsp->io_type == H9632) {
3346 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3347 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3348 return err;
3349 }
3350 }
3351
3352 /* Output loopback controls for H9632 cards */
3353 if (hdsp->io_type == H9632) {
3354 snd_hdsp_loopback_control.count = hdsp->max_channels;
3355 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3356 if (kctl == NULL)
3357 return -ENOMEM;
3358 err = snd_ctl_add(card, kctl);
3359 if (err < 0)
3360 return err;
3361 }
3362
3363 /* AEB control for H96xx card */
3364 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3365 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3366 return err;
3367 }
3368
3369 return 0;
3370 }
3371
3372 /*------------------------------------------------------------
3373 /proc interface
3374 ------------------------------------------------------------*/
3375
3376 static void
3377 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3378 {
3379 struct hdsp *hdsp = entry->private_data;
3380 unsigned int status;
3381 unsigned int status2;
3382 char *pref_sync_ref;
3383 char *autosync_ref;
3384 char *system_clock_mode;
3385 char *clock_source;
3386 int x;
3387
3388 status = hdsp_read(hdsp, HDSP_statusRegister);
3389 status2 = hdsp_read(hdsp, HDSP_status2Register);
3390
3391 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3392 hdsp->card->number + 1);
3393 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3394 hdsp->capture_buffer, hdsp->playback_buffer);
3395 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3396 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3397 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3398 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3399 hdsp->control2_register);
3400 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3401 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3402
3403 if (hdsp_check_for_iobox(hdsp)) {
3404 snd_iprintf(buffer, "No I/O box connected.\n"
3405 "Please connect one and upload firmware.\n");
3406 return;
3407 }
3408
3409 if (hdsp_check_for_firmware(hdsp, 0)) {
3410 if (hdsp->state & HDSP_FirmwareCached) {
3411 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3412 snd_iprintf(buffer, "Firmware loading from "
3413 "cache failed, "
3414 "please upload manually.\n");
3415 return;
3416 }
3417 } else {
3418 int err;
3419
3420 err = hdsp_request_fw_loader(hdsp);
3421 if (err < 0) {
3422 snd_iprintf(buffer,
3423 "No firmware loaded nor cached, "
3424 "please upload firmware.\n");
3425 return;
3426 }
3427 }
3428 }
3429
3430 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3431 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3432 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3433 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3434 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3435 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3436
3437 snd_iprintf(buffer, "\n");
3438
3439 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3440
3441 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3442 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3443 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3444 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3445
3446 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3447
3448 snd_iprintf(buffer, "\n");
3449
3450 switch (hdsp_clock_source(hdsp)) {
3451 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3452 clock_source = "AutoSync";
3453 break;
3454 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3455 clock_source = "Internal 32 kHz";
3456 break;
3457 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3458 clock_source = "Internal 44.1 kHz";
3459 break;
3460 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3461 clock_source = "Internal 48 kHz";
3462 break;
3463 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3464 clock_source = "Internal 64 kHz";
3465 break;
3466 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3467 clock_source = "Internal 88.2 kHz";
3468 break;
3469 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3470 clock_source = "Internal 96 kHz";
3471 break;
3472 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3473 clock_source = "Internal 128 kHz";
3474 break;
3475 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3476 clock_source = "Internal 176.4 kHz";
3477 break;
3478 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3479 clock_source = "Internal 192 kHz";
3480 break;
3481 default:
3482 clock_source = "Error";
3483 }
3484 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3485
3486 if (hdsp_system_clock_mode(hdsp))
3487 system_clock_mode = "Slave";
3488 else
3489 system_clock_mode = "Master";
3490
3491 switch (hdsp_pref_sync_ref (hdsp)) {
3492 case HDSP_SYNC_FROM_WORD:
3493 pref_sync_ref = "Word Clock";
3494 break;
3495 case HDSP_SYNC_FROM_ADAT_SYNC:
3496 pref_sync_ref = "ADAT Sync";
3497 break;
3498 case HDSP_SYNC_FROM_SPDIF:
3499 pref_sync_ref = "SPDIF";
3500 break;
3501 case HDSP_SYNC_FROM_ADAT1:
3502 pref_sync_ref = "ADAT1";
3503 break;
3504 case HDSP_SYNC_FROM_ADAT2:
3505 pref_sync_ref = "ADAT2";
3506 break;
3507 case HDSP_SYNC_FROM_ADAT3:
3508 pref_sync_ref = "ADAT3";
3509 break;
3510 default:
3511 pref_sync_ref = "Word Clock";
3512 break;
3513 }
3514 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3515
3516 switch (hdsp_autosync_ref (hdsp)) {
3517 case HDSP_AUTOSYNC_FROM_WORD:
3518 autosync_ref = "Word Clock";
3519 break;
3520 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3521 autosync_ref = "ADAT Sync";
3522 break;
3523 case HDSP_AUTOSYNC_FROM_SPDIF:
3524 autosync_ref = "SPDIF";
3525 break;
3526 case HDSP_AUTOSYNC_FROM_NONE:
3527 autosync_ref = "None";
3528 break;
3529 case HDSP_AUTOSYNC_FROM_ADAT1:
3530 autosync_ref = "ADAT1";
3531 break;
3532 case HDSP_AUTOSYNC_FROM_ADAT2:
3533 autosync_ref = "ADAT2";
3534 break;
3535 case HDSP_AUTOSYNC_FROM_ADAT3:
3536 autosync_ref = "ADAT3";
3537 break;
3538 default:
3539 autosync_ref = "---";
3540 break;
3541 }
3542 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3543
3544 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3545
3546 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3547
3548 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3549 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3550
3551 snd_iprintf(buffer, "\n");
3552
3553 if (hdsp->io_type != RPM) {
3554 switch (hdsp_spdif_in(hdsp)) {
3555 case HDSP_SPDIFIN_OPTICAL:
3556 snd_iprintf(buffer, "IEC958 input: Optical\n");
3557 break;
3558 case HDSP_SPDIFIN_COAXIAL:
3559 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3560 break;
3561 case HDSP_SPDIFIN_INTERNAL:
3562 snd_iprintf(buffer, "IEC958 input: Internal\n");
3563 break;
3564 case HDSP_SPDIFIN_AES:
3565 snd_iprintf(buffer, "IEC958 input: AES\n");
3566 break;
3567 default:
3568 snd_iprintf(buffer, "IEC958 input: ???\n");
3569 break;
3570 }
3571 }
3572
3573 if (RPM == hdsp->io_type) {
3574 if (hdsp->control_register & HDSP_RPM_Bypass)
3575 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3576 else
3577 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3578 if (hdsp->control_register & HDSP_RPM_Disconnect)
3579 snd_iprintf(buffer, "RPM disconnected\n");
3580 else
3581 snd_iprintf(buffer, "RPM connected\n");
3582
3583 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3584 case HDSP_RPM_Inp12_Phon_6dB:
3585 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3586 break;
3587 case HDSP_RPM_Inp12_Phon_0dB:
3588 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3589 break;
3590 case HDSP_RPM_Inp12_Phon_n6dB:
3591 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3592 break;
3593 case HDSP_RPM_Inp12_Line_0dB:
3594 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3595 break;
3596 case HDSP_RPM_Inp12_Line_n6dB:
3597 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3598 break;
3599 default:
3600 snd_iprintf(buffer, "Input 1/2: ???\n");
3601 }
3602
3603 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3604 case HDSP_RPM_Inp34_Phon_6dB:
3605 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3606 break;
3607 case HDSP_RPM_Inp34_Phon_0dB:
3608 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3609 break;
3610 case HDSP_RPM_Inp34_Phon_n6dB:
3611 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3612 break;
3613 case HDSP_RPM_Inp34_Line_0dB:
3614 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3615 break;
3616 case HDSP_RPM_Inp34_Line_n6dB:
3617 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3618 break;
3619 default:
3620 snd_iprintf(buffer, "Input 3/4: ???\n");
3621 }
3622
3623 } else {
3624 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3625 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3626 else
3627 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3628
3629 if (hdsp->control_register & HDSP_SPDIFProfessional)
3630 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3631 else
3632 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3633
3634 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3635 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3636 else
3637 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3638
3639 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3640 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3641 else
3642 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3643 x = hdsp_spdif_sample_rate(hdsp);
3644 if (x != 0)
3645 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3646 else
3647 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3648 }
3649 snd_iprintf(buffer, "\n");
3650
3651 /* Sync Check */
3652 x = status & HDSP_Sync0;
3653 if (status & HDSP_Lock0)
3654 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3655 else
3656 snd_iprintf(buffer, "ADAT1: No Lock\n");
3657
3658 switch (hdsp->io_type) {
3659 case Digiface:
3660 case H9652:
3661 x = status & HDSP_Sync1;
3662 if (status & HDSP_Lock1)
3663 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3664 else
3665 snd_iprintf(buffer, "ADAT2: No Lock\n");
3666 x = status & HDSP_Sync2;
3667 if (status & HDSP_Lock2)
3668 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3669 else
3670 snd_iprintf(buffer, "ADAT3: No Lock\n");
3671 break;
3672 default:
3673 /* relax */
3674 break;
3675 }
3676
3677 x = status & HDSP_SPDIFSync;
3678 if (status & HDSP_SPDIFErrorFlag)
3679 snd_iprintf (buffer, "SPDIF: No Lock\n");
3680 else
3681 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3682
3683 x = status2 & HDSP_wc_sync;
3684 if (status2 & HDSP_wc_lock)
3685 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3686 else
3687 snd_iprintf (buffer, "Word Clock: No Lock\n");
3688
3689 x = status & HDSP_TimecodeSync;
3690 if (status & HDSP_TimecodeLock)
3691 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3692 else
3693 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3694
3695 snd_iprintf(buffer, "\n");
3696
3697 /* Informations about H9632 specific controls */
3698 if (hdsp->io_type == H9632) {
3699 char *tmp;
3700
3701 switch (hdsp_ad_gain(hdsp)) {
3702 case 0:
3703 tmp = "-10 dBV";
3704 break;
3705 case 1:
3706 tmp = "+4 dBu";
3707 break;
3708 default:
3709 tmp = "Lo Gain";
3710 break;
3711 }
3712 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3713
3714 switch (hdsp_da_gain(hdsp)) {
3715 case 0:
3716 tmp = "Hi Gain";
3717 break;
3718 case 1:
3719 tmp = "+4 dBu";
3720 break;
3721 default:
3722 tmp = "-10 dBV";
3723 break;
3724 }
3725 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3726
3727 switch (hdsp_phone_gain(hdsp)) {
3728 case 0:
3729 tmp = "0 dB";
3730 break;
3731 case 1:
3732 tmp = "-6 dB";
3733 break;
3734 default:
3735 tmp = "-12 dB";
3736 break;
3737 }
3738 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3739
3740 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3741 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3742 "yes" : "no");
3743
3744 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3745 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3746 else
3747 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3748 snd_iprintf(buffer, "\n");
3749 }
3750
3751 }
3752
3753 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3754 {
3755 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3756 }
3757
3758 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3759 {
3760 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3761 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3762 }
3763
3764 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3765 {
3766 unsigned long pb_bus, cb_bus;
3767
3768 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3769 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3770 if (hdsp->capture_dma_buf.area)
3771 snd_dma_free_pages(&hdsp->capture_dma_buf);
3772 dev_err(hdsp->card->dev,
3773 "%s: no buffers available\n", hdsp->card_name);
3774 return -ENOMEM;
3775 }
3776
3777 /* Align to bus-space 64K boundary */
3778
3779 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3780 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3781
3782 /* Tell the card where it is */
3783
3784 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3785 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3786
3787 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3788 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3789
3790 return 0;
3791 }
3792
3793 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3794 {
3795 unsigned int i;
3796
3797 /* ASSUMPTION: hdsp->lock is either held, or
3798 there is no need to hold it (e.g. during module
3799 initialization).
3800 */
3801
3802 /* set defaults:
3803
3804 SPDIF Input via Coax
3805 Master clock mode
3806 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3807 which implies 2 4096 sample, 32Kbyte periods).
3808 Enable line out.
3809 */
3810
3811 hdsp->control_register = HDSP_ClockModeMaster |
3812 HDSP_SPDIFInputCoaxial |
3813 hdsp_encode_latency(7) |
3814 HDSP_LineOut;
3815
3816
3817 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3818
3819 #ifdef SNDRV_BIG_ENDIAN
3820 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3821 #else
3822 hdsp->control2_register = 0;
3823 #endif
3824 if (hdsp->io_type == H9652)
3825 snd_hdsp_9652_enable_mixer (hdsp);
3826 else
3827 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3828
3829 hdsp_reset_hw_pointer(hdsp);
3830 hdsp_compute_period_size(hdsp);
3831
3832 /* silence everything */
3833
3834 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3835 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3836
3837 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3838 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3839 return -EIO;
3840 }
3841
3842 /* H9632 specific defaults */
3843 if (hdsp->io_type == H9632) {
3844 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3845 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3846 }
3847
3848 /* set a default rate so that the channel map is set up.
3849 */
3850
3851 hdsp_set_rate(hdsp, 48000, 1);
3852
3853 return 0;
3854 }
3855
3856 static void hdsp_midi_work(struct work_struct *work)
3857 {
3858 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3859
3860 if (hdsp->midi[0].pending)
3861 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3862 if (hdsp->midi[1].pending)
3863 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3864 }
3865
3866 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3867 {
3868 struct hdsp *hdsp = (struct hdsp *) dev_id;
3869 unsigned int status;
3870 int audio;
3871 int midi0;
3872 int midi1;
3873 unsigned int midi0status;
3874 unsigned int midi1status;
3875 int schedule = 0;
3876
3877 status = hdsp_read(hdsp, HDSP_statusRegister);
3878
3879 audio = status & HDSP_audioIRQPending;
3880 midi0 = status & HDSP_midi0IRQPending;
3881 midi1 = status & HDSP_midi1IRQPending;
3882
3883 if (!audio && !midi0 && !midi1)
3884 return IRQ_NONE;
3885
3886 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3887
3888 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3889 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3890
3891 if (!(hdsp->state & HDSP_InitializationComplete))
3892 return IRQ_HANDLED;
3893
3894 if (audio) {
3895 if (hdsp->capture_substream)
3896 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3897
3898 if (hdsp->playback_substream)
3899 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3900 }
3901
3902 if (midi0 && midi0status) {
3903 if (hdsp->use_midi_work) {
3904 /* we disable interrupts for this input until processing is done */
3905 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3906 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3907 hdsp->midi[0].pending = 1;
3908 schedule = 1;
3909 } else {
3910 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3911 }
3912 }
3913 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3914 if (hdsp->use_midi_work) {
3915 /* we disable interrupts for this input until processing is done */
3916 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3917 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3918 hdsp->midi[1].pending = 1;
3919 schedule = 1;
3920 } else {
3921 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3922 }
3923 }
3924 if (hdsp->use_midi_work && schedule)
3925 queue_work(system_highpri_wq, &hdsp->midi_work);
3926 return IRQ_HANDLED;
3927 }
3928
3929 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3930 {
3931 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3932 return hdsp_hw_pointer(hdsp);
3933 }
3934
3935 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3936 int stream,
3937 int channel)
3938
3939 {
3940 int mapped_channel;
3941
3942 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3943 return NULL;
3944
3945 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3946 return NULL;
3947
3948 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3949 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3950 else
3951 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3952 }
3953
3954 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3955 int channel, unsigned long pos,
3956 void __user *src, unsigned long count)
3957 {
3958 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3959 char *channel_buf;
3960
3961 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3962 return -EINVAL;
3963
3964 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3965 if (snd_BUG_ON(!channel_buf))
3966 return -EIO;
3967 if (copy_from_user(channel_buf + pos, src, count))
3968 return -EFAULT;
3969 return 0;
3970 }
3971
3972 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3973 int channel, unsigned long pos,
3974 void *src, unsigned long count)
3975 {
3976 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3977 char *channel_buf;
3978
3979 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3980 if (snd_BUG_ON(!channel_buf))
3981 return -EIO;
3982 memcpy(channel_buf + pos, src, count);
3983 return 0;
3984 }
3985
3986 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3987 int channel, unsigned long pos,
3988 void __user *dst, unsigned long count)
3989 {
3990 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3991 char *channel_buf;
3992
3993 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3994 return -EINVAL;
3995
3996 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3997 if (snd_BUG_ON(!channel_buf))
3998 return -EIO;
3999 if (copy_to_user(dst, channel_buf + pos, count))
4000 return -EFAULT;
4001 return 0;
4002 }
4003
4004 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
4005 int channel, unsigned long pos,
4006 void *dst, unsigned long count)
4007 {
4008 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4009 char *channel_buf;
4010
4011 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
4012 if (snd_BUG_ON(!channel_buf))
4013 return -EIO;
4014 memcpy(dst, channel_buf + pos, count);
4015 return 0;
4016 }
4017
4018 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
4019 int channel, unsigned long pos,
4020 unsigned long count)
4021 {
4022 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4023 char *channel_buf;
4024
4025 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4026 if (snd_BUG_ON(!channel_buf))
4027 return -EIO;
4028 memset(channel_buf + pos, 0, count);
4029 return 0;
4030 }
4031
4032 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4033 {
4034 struct snd_pcm_runtime *runtime = substream->runtime;
4035 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4036 struct snd_pcm_substream *other;
4037 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4038 other = hdsp->capture_substream;
4039 else
4040 other = hdsp->playback_substream;
4041 if (hdsp->running)
4042 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4043 else
4044 runtime->status->hw_ptr = 0;
4045 if (other) {
4046 struct snd_pcm_substream *s;
4047 struct snd_pcm_runtime *oruntime = other->runtime;
4048 snd_pcm_group_for_each_entry(s, substream) {
4049 if (s == other) {
4050 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4051 break;
4052 }
4053 }
4054 }
4055 return 0;
4056 }
4057
4058 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4059 struct snd_pcm_hw_params *params)
4060 {
4061 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4062 int err;
4063 pid_t this_pid;
4064 pid_t other_pid;
4065
4066 if (hdsp_check_for_iobox (hdsp))
4067 return -EIO;
4068
4069 if (hdsp_check_for_firmware(hdsp, 1))
4070 return -EIO;
4071
4072 spin_lock_irq(&hdsp->lock);
4073
4074 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4075 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4076 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4077 this_pid = hdsp->playback_pid;
4078 other_pid = hdsp->capture_pid;
4079 } else {
4080 this_pid = hdsp->capture_pid;
4081 other_pid = hdsp->playback_pid;
4082 }
4083
4084 if ((other_pid > 0) && (this_pid != other_pid)) {
4085
4086 /* The other stream is open, and not by the same
4087 task as this one. Make sure that the parameters
4088 that matter are the same.
4089 */
4090
4091 if (params_rate(params) != hdsp->system_sample_rate) {
4092 spin_unlock_irq(&hdsp->lock);
4093 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4094 return -EBUSY;
4095 }
4096
4097 if (params_period_size(params) != hdsp->period_bytes / 4) {
4098 spin_unlock_irq(&hdsp->lock);
4099 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4100 return -EBUSY;
4101 }
4102
4103 /* We're fine. */
4104
4105 spin_unlock_irq(&hdsp->lock);
4106 return 0;
4107
4108 } else {
4109 spin_unlock_irq(&hdsp->lock);
4110 }
4111
4112 /* how to make sure that the rate matches an externally-set one ?
4113 */
4114
4115 spin_lock_irq(&hdsp->lock);
4116 if (! hdsp->clock_source_locked) {
4117 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4118 spin_unlock_irq(&hdsp->lock);
4119 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4120 return err;
4121 }
4122 }
4123 spin_unlock_irq(&hdsp->lock);
4124
4125 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4126 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4127 return err;
4128 }
4129
4130 return 0;
4131 }
4132
4133 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4134 struct snd_pcm_channel_info *info)
4135 {
4136 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4137 unsigned int channel = info->channel;
4138
4139 if (snd_BUG_ON(channel >= hdsp->max_channels))
4140 return -EINVAL;
4141 channel = array_index_nospec(channel, hdsp->max_channels);
4142
4143 if (hdsp->channel_map[channel] < 0)
4144 return -EINVAL;
4145
4146 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4147 info->first = 0;
4148 info->step = 32;
4149 return 0;
4150 }
4151
4152 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4153 unsigned int cmd, void *arg)
4154 {
4155 switch (cmd) {
4156 case SNDRV_PCM_IOCTL1_RESET:
4157 return snd_hdsp_reset(substream);
4158 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4159 return snd_hdsp_channel_info(substream, arg);
4160 default:
4161 break;
4162 }
4163
4164 return snd_pcm_lib_ioctl(substream, cmd, arg);
4165 }
4166
4167 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4168 {
4169 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4170 struct snd_pcm_substream *other;
4171 int running;
4172
4173 if (hdsp_check_for_iobox (hdsp))
4174 return -EIO;
4175
4176 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4177 return -EIO;
4178
4179 spin_lock(&hdsp->lock);
4180 running = hdsp->running;
4181 switch (cmd) {
4182 case SNDRV_PCM_TRIGGER_START:
4183 running |= 1 << substream->stream;
4184 break;
4185 case SNDRV_PCM_TRIGGER_STOP:
4186 running &= ~(1 << substream->stream);
4187 break;
4188 default:
4189 snd_BUG();
4190 spin_unlock(&hdsp->lock);
4191 return -EINVAL;
4192 }
4193 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4194 other = hdsp->capture_substream;
4195 else
4196 other = hdsp->playback_substream;
4197
4198 if (other) {
4199 struct snd_pcm_substream *s;
4200 snd_pcm_group_for_each_entry(s, substream) {
4201 if (s == other) {
4202 snd_pcm_trigger_done(s, substream);
4203 if (cmd == SNDRV_PCM_TRIGGER_START)
4204 running |= 1 << s->stream;
4205 else
4206 running &= ~(1 << s->stream);
4207 goto _ok;
4208 }
4209 }
4210 if (cmd == SNDRV_PCM_TRIGGER_START) {
4211 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4212 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4213 hdsp_silence_playback(hdsp);
4214 } else {
4215 if (running &&
4216 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4217 hdsp_silence_playback(hdsp);
4218 }
4219 } else {
4220 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4221 hdsp_silence_playback(hdsp);
4222 }
4223 _ok:
4224 snd_pcm_trigger_done(substream, substream);
4225 if (!hdsp->running && running)
4226 hdsp_start_audio(hdsp);
4227 else if (hdsp->running && !running)
4228 hdsp_stop_audio(hdsp);
4229 hdsp->running = running;
4230 spin_unlock(&hdsp->lock);
4231
4232 return 0;
4233 }
4234
4235 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4236 {
4237 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4238 int result = 0;
4239
4240 if (hdsp_check_for_iobox (hdsp))
4241 return -EIO;
4242
4243 if (hdsp_check_for_firmware(hdsp, 1))
4244 return -EIO;
4245
4246 spin_lock_irq(&hdsp->lock);
4247 if (!hdsp->running)
4248 hdsp_reset_hw_pointer(hdsp);
4249 spin_unlock_irq(&hdsp->lock);
4250 return result;
4251 }
4252
4253 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4254 {
4255 .info = (SNDRV_PCM_INFO_MMAP |
4256 SNDRV_PCM_INFO_MMAP_VALID |
4257 SNDRV_PCM_INFO_NONINTERLEAVED |
4258 SNDRV_PCM_INFO_SYNC_START |
4259 SNDRV_PCM_INFO_DOUBLE),
4260 #ifdef SNDRV_BIG_ENDIAN
4261 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4262 #else
4263 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4264 #endif
4265 .rates = (SNDRV_PCM_RATE_32000 |
4266 SNDRV_PCM_RATE_44100 |
4267 SNDRV_PCM_RATE_48000 |
4268 SNDRV_PCM_RATE_64000 |
4269 SNDRV_PCM_RATE_88200 |
4270 SNDRV_PCM_RATE_96000),
4271 .rate_min = 32000,
4272 .rate_max = 96000,
4273 .channels_min = 6,
4274 .channels_max = HDSP_MAX_CHANNELS,
4275 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4276 .period_bytes_min = (64 * 4) * 10,
4277 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4278 .periods_min = 2,
4279 .periods_max = 2,
4280 .fifo_size = 0
4281 };
4282
4283 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4284 {
4285 .info = (SNDRV_PCM_INFO_MMAP |
4286 SNDRV_PCM_INFO_MMAP_VALID |
4287 SNDRV_PCM_INFO_NONINTERLEAVED |
4288 SNDRV_PCM_INFO_SYNC_START),
4289 #ifdef SNDRV_BIG_ENDIAN
4290 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4291 #else
4292 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4293 #endif
4294 .rates = (SNDRV_PCM_RATE_32000 |
4295 SNDRV_PCM_RATE_44100 |
4296 SNDRV_PCM_RATE_48000 |
4297 SNDRV_PCM_RATE_64000 |
4298 SNDRV_PCM_RATE_88200 |
4299 SNDRV_PCM_RATE_96000),
4300 .rate_min = 32000,
4301 .rate_max = 96000,
4302 .channels_min = 5,
4303 .channels_max = HDSP_MAX_CHANNELS,
4304 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4305 .period_bytes_min = (64 * 4) * 10,
4306 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4307 .periods_min = 2,
4308 .periods_max = 2,
4309 .fifo_size = 0
4310 };
4311
4312 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4313
4314 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4315 .count = ARRAY_SIZE(hdsp_period_sizes),
4316 .list = hdsp_period_sizes,
4317 .mask = 0
4318 };
4319
4320 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4321
4322 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4323 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4324 .list = hdsp_9632_sample_rates,
4325 .mask = 0
4326 };
4327
4328 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4329 struct snd_pcm_hw_rule *rule)
4330 {
4331 struct hdsp *hdsp = rule->private;
4332 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4333 if (hdsp->io_type == H9632) {
4334 unsigned int list[3];
4335 list[0] = hdsp->qs_in_channels;
4336 list[1] = hdsp->ds_in_channels;
4337 list[2] = hdsp->ss_in_channels;
4338 return snd_interval_list(c, 3, list, 0);
4339 } else {
4340 unsigned int list[2];
4341 list[0] = hdsp->ds_in_channels;
4342 list[1] = hdsp->ss_in_channels;
4343 return snd_interval_list(c, 2, list, 0);
4344 }
4345 }
4346
4347 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4348 struct snd_pcm_hw_rule *rule)
4349 {
4350 unsigned int list[3];
4351 struct hdsp *hdsp = rule->private;
4352 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4353 if (hdsp->io_type == H9632) {
4354 list[0] = hdsp->qs_out_channels;
4355 list[1] = hdsp->ds_out_channels;
4356 list[2] = hdsp->ss_out_channels;
4357 return snd_interval_list(c, 3, list, 0);
4358 } else {
4359 list[0] = hdsp->ds_out_channels;
4360 list[1] = hdsp->ss_out_channels;
4361 }
4362 return snd_interval_list(c, 2, list, 0);
4363 }
4364
4365 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4366 struct snd_pcm_hw_rule *rule)
4367 {
4368 struct hdsp *hdsp = rule->private;
4369 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4370 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4371 if (r->min > 96000 && hdsp->io_type == H9632) {
4372 struct snd_interval t = {
4373 .min = hdsp->qs_in_channels,
4374 .max = hdsp->qs_in_channels,
4375 .integer = 1,
4376 };
4377 return snd_interval_refine(c, &t);
4378 } else if (r->min > 48000 && r->max <= 96000) {
4379 struct snd_interval t = {
4380 .min = hdsp->ds_in_channels,
4381 .max = hdsp->ds_in_channels,
4382 .integer = 1,
4383 };
4384 return snd_interval_refine(c, &t);
4385 } else if (r->max < 64000) {
4386 struct snd_interval t = {
4387 .min = hdsp->ss_in_channels,
4388 .max = hdsp->ss_in_channels,
4389 .integer = 1,
4390 };
4391 return snd_interval_refine(c, &t);
4392 }
4393 return 0;
4394 }
4395
4396 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4397 struct snd_pcm_hw_rule *rule)
4398 {
4399 struct hdsp *hdsp = rule->private;
4400 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4401 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4402 if (r->min > 96000 && hdsp->io_type == H9632) {
4403 struct snd_interval t = {
4404 .min = hdsp->qs_out_channels,
4405 .max = hdsp->qs_out_channels,
4406 .integer = 1,
4407 };
4408 return snd_interval_refine(c, &t);
4409 } else if (r->min > 48000 && r->max <= 96000) {
4410 struct snd_interval t = {
4411 .min = hdsp->ds_out_channels,
4412 .max = hdsp->ds_out_channels,
4413 .integer = 1,
4414 };
4415 return snd_interval_refine(c, &t);
4416 } else if (r->max < 64000) {
4417 struct snd_interval t = {
4418 .min = hdsp->ss_out_channels,
4419 .max = hdsp->ss_out_channels,
4420 .integer = 1,
4421 };
4422 return snd_interval_refine(c, &t);
4423 }
4424 return 0;
4425 }
4426
4427 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4428 struct snd_pcm_hw_rule *rule)
4429 {
4430 struct hdsp *hdsp = rule->private;
4431 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4432 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4433 if (c->min >= hdsp->ss_out_channels) {
4434 struct snd_interval t = {
4435 .min = 32000,
4436 .max = 48000,
4437 .integer = 1,
4438 };
4439 return snd_interval_refine(r, &t);
4440 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4441 struct snd_interval t = {
4442 .min = 128000,
4443 .max = 192000,
4444 .integer = 1,
4445 };
4446 return snd_interval_refine(r, &t);
4447 } else if (c->max <= hdsp->ds_out_channels) {
4448 struct snd_interval t = {
4449 .min = 64000,
4450 .max = 96000,
4451 .integer = 1,
4452 };
4453 return snd_interval_refine(r, &t);
4454 }
4455 return 0;
4456 }
4457
4458 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4459 struct snd_pcm_hw_rule *rule)
4460 {
4461 struct hdsp *hdsp = rule->private;
4462 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4463 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4464 if (c->min >= hdsp->ss_in_channels) {
4465 struct snd_interval t = {
4466 .min = 32000,
4467 .max = 48000,
4468 .integer = 1,
4469 };
4470 return snd_interval_refine(r, &t);
4471 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4472 struct snd_interval t = {
4473 .min = 128000,
4474 .max = 192000,
4475 .integer = 1,
4476 };
4477 return snd_interval_refine(r, &t);
4478 } else if (c->max <= hdsp->ds_in_channels) {
4479 struct snd_interval t = {
4480 .min = 64000,
4481 .max = 96000,
4482 .integer = 1,
4483 };
4484 return snd_interval_refine(r, &t);
4485 }
4486 return 0;
4487 }
4488
4489 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4490 {
4491 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4492 struct snd_pcm_runtime *runtime = substream->runtime;
4493
4494 if (hdsp_check_for_iobox (hdsp))
4495 return -EIO;
4496
4497 if (hdsp_check_for_firmware(hdsp, 1))
4498 return -EIO;
4499
4500 spin_lock_irq(&hdsp->lock);
4501
4502 snd_pcm_set_sync(substream);
4503
4504 runtime->hw = snd_hdsp_playback_subinfo;
4505 runtime->dma_area = hdsp->playback_buffer;
4506 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4507
4508 hdsp->playback_pid = current->pid;
4509 hdsp->playback_substream = substream;
4510
4511 spin_unlock_irq(&hdsp->lock);
4512
4513 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4514 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4515 if (hdsp->clock_source_locked) {
4516 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4517 } else if (hdsp->io_type == H9632) {
4518 runtime->hw.rate_max = 192000;
4519 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4520 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4521 }
4522 if (hdsp->io_type == H9632) {
4523 runtime->hw.channels_min = hdsp->qs_out_channels;
4524 runtime->hw.channels_max = hdsp->ss_out_channels;
4525 }
4526
4527 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4528 snd_hdsp_hw_rule_out_channels, hdsp,
4529 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4530 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4531 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4532 SNDRV_PCM_HW_PARAM_RATE, -1);
4533 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4534 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4535 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4536
4537 if (RPM != hdsp->io_type) {
4538 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4539 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4540 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4541 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4542 }
4543 return 0;
4544 }
4545
4546 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4547 {
4548 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4549
4550 spin_lock_irq(&hdsp->lock);
4551
4552 hdsp->playback_pid = -1;
4553 hdsp->playback_substream = NULL;
4554
4555 spin_unlock_irq(&hdsp->lock);
4556
4557 if (RPM != hdsp->io_type) {
4558 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4559 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4560 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4561 }
4562 return 0;
4563 }
4564
4565
4566 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4567 {
4568 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4569 struct snd_pcm_runtime *runtime = substream->runtime;
4570
4571 if (hdsp_check_for_iobox (hdsp))
4572 return -EIO;
4573
4574 if (hdsp_check_for_firmware(hdsp, 1))
4575 return -EIO;
4576
4577 spin_lock_irq(&hdsp->lock);
4578
4579 snd_pcm_set_sync(substream);
4580
4581 runtime->hw = snd_hdsp_capture_subinfo;
4582 runtime->dma_area = hdsp->capture_buffer;
4583 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4584
4585 hdsp->capture_pid = current->pid;
4586 hdsp->capture_substream = substream;
4587
4588 spin_unlock_irq(&hdsp->lock);
4589
4590 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4591 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4592 if (hdsp->io_type == H9632) {
4593 runtime->hw.channels_min = hdsp->qs_in_channels;
4594 runtime->hw.channels_max = hdsp->ss_in_channels;
4595 runtime->hw.rate_max = 192000;
4596 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4597 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4598 }
4599 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4600 snd_hdsp_hw_rule_in_channels, hdsp,
4601 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4602 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4603 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4604 SNDRV_PCM_HW_PARAM_RATE, -1);
4605 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4606 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4607 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4608 return 0;
4609 }
4610
4611 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4612 {
4613 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4614
4615 spin_lock_irq(&hdsp->lock);
4616
4617 hdsp->capture_pid = -1;
4618 hdsp->capture_substream = NULL;
4619
4620 spin_unlock_irq(&hdsp->lock);
4621 return 0;
4622 }
4623
4624 /* helper functions for copying meter values */
4625 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4626 {
4627 u32 val = readl(src);
4628 return copy_to_user(dest, &val, 4);
4629 }
4630
4631 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4632 {
4633 u32 rms_low, rms_high;
4634 u64 rms;
4635 rms_low = readl(src_low);
4636 rms_high = readl(src_high);
4637 rms = ((u64)rms_high << 32) | rms_low;
4638 return copy_to_user(dest, &rms, 8);
4639 }
4640
4641 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4642 {
4643 u32 rms_low, rms_high;
4644 u64 rms;
4645 rms_low = readl(src_low) & 0xffffff00;
4646 rms_high = readl(src_high) & 0xffffff00;
4647 rms = ((u64)rms_high << 32) | rms_low;
4648 return copy_to_user(dest, &rms, 8);
4649 }
4650
4651 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4652 {
4653 int doublespeed = 0;
4654 int i, j, channels, ofs;
4655
4656 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4657 doublespeed = 1;
4658 channels = doublespeed ? 14 : 26;
4659 for (i = 0, j = 0; i < 26; ++i) {
4660 if (doublespeed && (i & 4))
4661 continue;
4662 ofs = HDSP_9652_peakBase - j * 4;
4663 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4664 return -EFAULT;
4665 ofs -= channels * 4;
4666 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4667 return -EFAULT;
4668 ofs -= channels * 4;
4669 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4670 return -EFAULT;
4671 ofs = HDSP_9652_rmsBase + j * 8;
4672 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4673 hdsp->iobase + ofs + 4))
4674 return -EFAULT;
4675 ofs += channels * 8;
4676 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4677 hdsp->iobase + ofs + 4))
4678 return -EFAULT;
4679 ofs += channels * 8;
4680 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4681 hdsp->iobase + ofs + 4))
4682 return -EFAULT;
4683 j++;
4684 }
4685 return 0;
4686 }
4687
4688 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4689 {
4690 int i, j;
4691 struct hdsp_9632_meters __iomem *m;
4692 int doublespeed = 0;
4693
4694 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4695 doublespeed = 1;
4696 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4697 for (i = 0, j = 0; i < 16; ++i, ++j) {
4698 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4699 return -EFAULT;
4700 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4701 return -EFAULT;
4702 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4703 return -EFAULT;
4704 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4705 &m->input_rms_high[j]))
4706 return -EFAULT;
4707 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4708 &m->playback_rms_high[j]))
4709 return -EFAULT;
4710 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4711 &m->output_rms_high[j]))
4712 return -EFAULT;
4713 if (doublespeed && i == 3) i += 4;
4714 }
4715 return 0;
4716 }
4717
4718 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4719 {
4720 int i;
4721
4722 for (i = 0; i < 26; i++) {
4723 if (copy_u32_le(&peak_rms->playback_peaks[i],
4724 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4725 return -EFAULT;
4726 if (copy_u32_le(&peak_rms->input_peaks[i],
4727 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4728 return -EFAULT;
4729 }
4730 for (i = 0; i < 28; i++) {
4731 if (copy_u32_le(&peak_rms->output_peaks[i],
4732 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4733 return -EFAULT;
4734 }
4735 for (i = 0; i < 26; ++i) {
4736 if (copy_u64_le(&peak_rms->playback_rms[i],
4737 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4738 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4739 return -EFAULT;
4740 if (copy_u64_le(&peak_rms->input_rms[i],
4741 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4742 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4743 return -EFAULT;
4744 }
4745 return 0;
4746 }
4747
4748 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4749 {
4750 struct hdsp *hdsp = hw->private_data;
4751 void __user *argp = (void __user *)arg;
4752 int err;
4753
4754 switch (cmd) {
4755 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4756 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4757
4758 err = hdsp_check_for_iobox(hdsp);
4759 if (err < 0)
4760 return err;
4761
4762 err = hdsp_check_for_firmware(hdsp, 1);
4763 if (err < 0)
4764 return err;
4765
4766 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4767 dev_err(hdsp->card->dev,
4768 "firmware needs to be uploaded to the card.\n");
4769 return -EINVAL;
4770 }
4771
4772 switch (hdsp->io_type) {
4773 case H9652:
4774 return hdsp_9652_get_peak(hdsp, peak_rms);
4775 case H9632:
4776 return hdsp_9632_get_peak(hdsp, peak_rms);
4777 default:
4778 return hdsp_get_peak(hdsp, peak_rms);
4779 }
4780 }
4781 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4782 struct hdsp_config_info info;
4783 unsigned long flags;
4784 int i;
4785
4786 err = hdsp_check_for_iobox(hdsp);
4787 if (err < 0)
4788 return err;
4789
4790 err = hdsp_check_for_firmware(hdsp, 1);
4791 if (err < 0)
4792 return err;
4793
4794 memset(&info, 0, sizeof(info));
4795 spin_lock_irqsave(&hdsp->lock, flags);
4796 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4797 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4798 if (hdsp->io_type != H9632)
4799 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4800 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4801 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4802 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4803 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4804 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4805 HDSP_SPDIFOpticalOut);
4806 info.spdif_professional = (unsigned char)
4807 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4808 info.spdif_emphasis = (unsigned char)
4809 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4810 info.spdif_nonaudio = (unsigned char)
4811 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4812 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4813 info.system_sample_rate = hdsp->system_sample_rate;
4814 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4815 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4816 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4817 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4818 info.line_out = (unsigned char)
4819 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4820 if (hdsp->io_type == H9632) {
4821 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4822 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4823 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4824 info.xlr_breakout_cable =
4825 (unsigned char)hdsp_toggle_setting(hdsp,
4826 HDSP_XLRBreakoutCable);
4827
4828 } else if (hdsp->io_type == RPM) {
4829 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4830 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4831 }
4832 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4833 info.analog_extension_board =
4834 (unsigned char)hdsp_toggle_setting(hdsp,
4835 HDSP_AnalogExtensionBoard);
4836 spin_unlock_irqrestore(&hdsp->lock, flags);
4837 if (copy_to_user(argp, &info, sizeof(info)))
4838 return -EFAULT;
4839 break;
4840 }
4841 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4842 struct hdsp_9632_aeb h9632_aeb;
4843
4844 if (hdsp->io_type != H9632) return -EINVAL;
4845 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4846 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4847 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4848 return -EFAULT;
4849 break;
4850 }
4851 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4852 struct hdsp_version hdsp_version;
4853 int err;
4854
4855 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4856 if (hdsp->io_type == Undefined) {
4857 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4858 return err;
4859 }
4860 memset(&hdsp_version, 0, sizeof(hdsp_version));
4861 hdsp_version.io_type = hdsp->io_type;
4862 hdsp_version.firmware_rev = hdsp->firmware_rev;
4863 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4864 return -EFAULT;
4865 break;
4866 }
4867 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4868 struct hdsp_firmware firmware;
4869 u32 __user *firmware_data;
4870 int err;
4871
4872 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4873 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4874 if (hdsp->io_type == Undefined) return -EINVAL;
4875
4876 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4877 return -EBUSY;
4878
4879 dev_info(hdsp->card->dev,
4880 "initializing firmware upload\n");
4881 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4882 return -EFAULT;
4883 firmware_data = (u32 __user *)firmware.firmware_data;
4884
4885 if (hdsp_check_for_iobox (hdsp))
4886 return -EIO;
4887
4888 if (!hdsp->fw_uploaded) {
4889 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4890 if (!hdsp->fw_uploaded)
4891 return -ENOMEM;
4892 }
4893
4894 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4895 HDSP_FIRMWARE_SIZE)) {
4896 vfree(hdsp->fw_uploaded);
4897 hdsp->fw_uploaded = NULL;
4898 return -EFAULT;
4899 }
4900
4901 hdsp->state |= HDSP_FirmwareCached;
4902
4903 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4904 return err;
4905
4906 if (!(hdsp->state & HDSP_InitializationComplete)) {
4907 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4908 return err;
4909
4910 snd_hdsp_initialize_channels(hdsp);
4911 snd_hdsp_initialize_midi_flush(hdsp);
4912
4913 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4914 dev_err(hdsp->card->dev,
4915 "error creating alsa devices\n");
4916 return err;
4917 }
4918 }
4919 break;
4920 }
4921 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4922 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4923 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4924 return -EFAULT;
4925 break;
4926 }
4927 default:
4928 return -EINVAL;
4929 }
4930 return 0;
4931 }
4932
4933 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4934 .open = snd_hdsp_playback_open,
4935 .close = snd_hdsp_playback_release,
4936 .ioctl = snd_hdsp_ioctl,
4937 .hw_params = snd_hdsp_hw_params,
4938 .prepare = snd_hdsp_prepare,
4939 .trigger = snd_hdsp_trigger,
4940 .pointer = snd_hdsp_hw_pointer,
4941 .copy_user = snd_hdsp_playback_copy,
4942 .copy_kernel = snd_hdsp_playback_copy_kernel,
4943 .fill_silence = snd_hdsp_hw_silence,
4944 };
4945
4946 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4947 .open = snd_hdsp_capture_open,
4948 .close = snd_hdsp_capture_release,
4949 .ioctl = snd_hdsp_ioctl,
4950 .hw_params = snd_hdsp_hw_params,
4951 .prepare = snd_hdsp_prepare,
4952 .trigger = snd_hdsp_trigger,
4953 .pointer = snd_hdsp_hw_pointer,
4954 .copy_user = snd_hdsp_capture_copy,
4955 .copy_kernel = snd_hdsp_capture_copy_kernel,
4956 };
4957
4958 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4959 {
4960 struct snd_hwdep *hw;
4961 int err;
4962
4963 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4964 return err;
4965
4966 hdsp->hwdep = hw;
4967 hw->private_data = hdsp;
4968 strcpy(hw->name, "HDSP hwdep interface");
4969
4970 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4971 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4972
4973 return 0;
4974 }
4975
4976 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4977 {
4978 struct snd_pcm *pcm;
4979 int err;
4980
4981 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4982 return err;
4983
4984 hdsp->pcm = pcm;
4985 pcm->private_data = hdsp;
4986 strcpy(pcm->name, hdsp->card_name);
4987
4988 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4989 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4990
4991 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4992
4993 return 0;
4994 }
4995
4996 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4997 {
4998 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4999 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
5000 }
5001
5002 static int snd_hdsp_enable_io (struct hdsp *hdsp)
5003 {
5004 int i;
5005
5006 if (hdsp_fifo_wait (hdsp, 0, 100)) {
5007 dev_err(hdsp->card->dev,
5008 "enable_io fifo_wait failed\n");
5009 return -EIO;
5010 }
5011
5012 for (i = 0; i < hdsp->max_channels; ++i) {
5013 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5014 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5015 }
5016
5017 return 0;
5018 }
5019
5020 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5021 {
5022 int status, aebi_channels, aebo_channels, i;
5023
5024 switch (hdsp->io_type) {
5025 case Digiface:
5026 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5027 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5028 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5029 break;
5030
5031 case H9652:
5032 hdsp->card_name = "RME Hammerfall HDSP 9652";
5033 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5034 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5035 break;
5036
5037 case H9632:
5038 status = hdsp_read(hdsp, HDSP_statusRegister);
5039 /* HDSP_AEBx bits are low when AEB are connected */
5040 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5041 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5042 hdsp->card_name = "RME Hammerfall HDSP 9632";
5043 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5044 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5045 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5046 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5047 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5048 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5049 /* Disable loopback of output channels, as the set function
5050 * only sets on a change we fake all bits (channels) as enabled.
5051 */
5052 hdsp->io_loopback = 0xffffffff;
5053 for (i = 0; i < hdsp->max_channels; ++i)
5054 hdsp_loopback_set(hdsp, i, false);
5055 break;
5056
5057 case Multiface:
5058 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5059 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5060 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5061 break;
5062
5063 case RPM:
5064 hdsp->card_name = "RME Hammerfall DSP + RPM";
5065 hdsp->ss_in_channels = RPM_CHANNELS-1;
5066 hdsp->ss_out_channels = RPM_CHANNELS;
5067 hdsp->ds_in_channels = RPM_CHANNELS-1;
5068 hdsp->ds_out_channels = RPM_CHANNELS;
5069 break;
5070
5071 default:
5072 /* should never get here */
5073 break;
5074 }
5075 }
5076
5077 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5078 {
5079 snd_hdsp_flush_midi_input (hdsp, 0);
5080 snd_hdsp_flush_midi_input (hdsp, 1);
5081 }
5082
5083 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5084 {
5085 int err;
5086
5087 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5088 dev_err(card->dev,
5089 "Error creating pcm interface\n");
5090 return err;
5091 }
5092
5093
5094 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5095 dev_err(card->dev,
5096 "Error creating first midi interface\n");
5097 return err;
5098 }
5099
5100 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5101 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5102 dev_err(card->dev,
5103 "Error creating second midi interface\n");
5104 return err;
5105 }
5106 }
5107
5108 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5109 dev_err(card->dev,
5110 "Error creating ctl interface\n");
5111 return err;
5112 }
5113
5114 snd_hdsp_proc_init(hdsp);
5115
5116 hdsp->system_sample_rate = -1;
5117 hdsp->playback_pid = -1;
5118 hdsp->capture_pid = -1;
5119 hdsp->capture_substream = NULL;
5120 hdsp->playback_substream = NULL;
5121
5122 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5123 dev_err(card->dev,
5124 "Error setting default values\n");
5125 return err;
5126 }
5127
5128 if (!(hdsp->state & HDSP_InitializationComplete)) {
5129 strcpy(card->shortname, "Hammerfall DSP");
5130 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5131 hdsp->port, hdsp->irq);
5132
5133 if ((err = snd_card_register(card)) < 0) {
5134 dev_err(card->dev,
5135 "error registering card\n");
5136 return err;
5137 }
5138 hdsp->state |= HDSP_InitializationComplete;
5139 }
5140
5141 return 0;
5142 }
5143
5144 /* load firmware via hotplug fw loader */
5145 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5146 {
5147 const char *fwfile;
5148 const struct firmware *fw;
5149 int err;
5150
5151 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5152 return 0;
5153 if (hdsp->io_type == Undefined) {
5154 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5155 return err;
5156 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5157 return 0;
5158 }
5159
5160 /* caution: max length of firmware filename is 30! */
5161 switch (hdsp->io_type) {
5162 case RPM:
5163 fwfile = "rpm_firmware.bin";
5164 break;
5165 case Multiface:
5166 if (hdsp->firmware_rev == 0xa)
5167 fwfile = "multiface_firmware.bin";
5168 else
5169 fwfile = "multiface_firmware_rev11.bin";
5170 break;
5171 case Digiface:
5172 if (hdsp->firmware_rev == 0xa)
5173 fwfile = "digiface_firmware.bin";
5174 else
5175 fwfile = "digiface_firmware_rev11.bin";
5176 break;
5177 default:
5178 dev_err(hdsp->card->dev,
5179 "invalid io_type %d\n", hdsp->io_type);
5180 return -EINVAL;
5181 }
5182
5183 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5184 dev_err(hdsp->card->dev,
5185 "cannot load firmware %s\n", fwfile);
5186 return -ENOENT;
5187 }
5188 if (fw->size < HDSP_FIRMWARE_SIZE) {
5189 dev_err(hdsp->card->dev,
5190 "too short firmware size %d (expected %d)\n",
5191 (int)fw->size, HDSP_FIRMWARE_SIZE);
5192 release_firmware(fw);
5193 return -EINVAL;
5194 }
5195
5196 hdsp->firmware = fw;
5197
5198 hdsp->state |= HDSP_FirmwareCached;
5199
5200 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5201 return err;
5202
5203 if (!(hdsp->state & HDSP_InitializationComplete)) {
5204 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5205 return err;
5206
5207 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5208 dev_err(hdsp->card->dev,
5209 "error creating hwdep device\n");
5210 return err;
5211 }
5212 snd_hdsp_initialize_channels(hdsp);
5213 snd_hdsp_initialize_midi_flush(hdsp);
5214 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5215 dev_err(hdsp->card->dev,
5216 "error creating alsa devices\n");
5217 return err;
5218 }
5219 }
5220 return 0;
5221 }
5222
5223 static int snd_hdsp_create(struct snd_card *card,
5224 struct hdsp *hdsp)
5225 {
5226 struct pci_dev *pci = hdsp->pci;
5227 int err;
5228 int is_9652 = 0;
5229 int is_9632 = 0;
5230
5231 hdsp->irq = -1;
5232 hdsp->state = 0;
5233 hdsp->midi[0].rmidi = NULL;
5234 hdsp->midi[1].rmidi = NULL;
5235 hdsp->midi[0].input = NULL;
5236 hdsp->midi[1].input = NULL;
5237 hdsp->midi[0].output = NULL;
5238 hdsp->midi[1].output = NULL;
5239 hdsp->midi[0].pending = 0;
5240 hdsp->midi[1].pending = 0;
5241 spin_lock_init(&hdsp->midi[0].lock);
5242 spin_lock_init(&hdsp->midi[1].lock);
5243 hdsp->iobase = NULL;
5244 hdsp->control_register = 0;
5245 hdsp->control2_register = 0;
5246 hdsp->io_type = Undefined;
5247 hdsp->max_channels = 26;
5248
5249 hdsp->card = card;
5250
5251 spin_lock_init(&hdsp->lock);
5252
5253 INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5254
5255 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5256 hdsp->firmware_rev &= 0xff;
5257
5258 /* From Martin Bjoernsen :
5259 "It is important that the card's latency timer register in
5260 the PCI configuration space is set to a value much larger
5261 than 0 by the computer's BIOS or the driver.
5262 The windows driver always sets this 8 bit register [...]
5263 to its maximum 255 to avoid problems with some computers."
5264 */
5265 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5266
5267 strcpy(card->driver, "H-DSP");
5268 strcpy(card->mixername, "Xilinx FPGA");
5269
5270 if (hdsp->firmware_rev < 0xa)
5271 return -ENODEV;
5272 else if (hdsp->firmware_rev < 0x64)
5273 hdsp->card_name = "RME Hammerfall DSP";
5274 else if (hdsp->firmware_rev < 0x96) {
5275 hdsp->card_name = "RME HDSP 9652";
5276 is_9652 = 1;
5277 } else {
5278 hdsp->card_name = "RME HDSP 9632";
5279 hdsp->max_channels = 16;
5280 is_9632 = 1;
5281 }
5282
5283 if ((err = pci_enable_device(pci)) < 0)
5284 return err;
5285
5286 pci_set_master(hdsp->pci);
5287
5288 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5289 return err;
5290 hdsp->port = pci_resource_start(pci, 0);
5291 if ((hdsp->iobase = ioremap(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5292 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5293 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5294 return -EBUSY;
5295 }
5296
5297 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5298 KBUILD_MODNAME, hdsp)) {
5299 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5300 return -EBUSY;
5301 }
5302
5303 hdsp->irq = pci->irq;
5304 card->sync_irq = hdsp->irq;
5305 hdsp->precise_ptr = 0;
5306 hdsp->use_midi_work = 1;
5307 hdsp->dds_value = 0;
5308
5309 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5310 return err;
5311
5312 if (!is_9652 && !is_9632) {
5313 /* we wait a maximum of 10 seconds to let freshly
5314 * inserted cardbus cards do their hardware init */
5315 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5316
5317 if (err < 0)
5318 return err;
5319
5320 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5321 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5322 /* we don't fail as this can happen
5323 if userspace is not ready for
5324 firmware upload
5325 */
5326 dev_err(hdsp->card->dev,
5327 "couldn't get firmware from userspace. try using hdsploader\n");
5328 else
5329 /* init is complete, we return */
5330 return 0;
5331 /* we defer initialization */
5332 dev_info(hdsp->card->dev,
5333 "card initialization pending : waiting for firmware\n");
5334 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5335 return err;
5336 return 0;
5337 } else {
5338 dev_info(hdsp->card->dev,
5339 "Firmware already present, initializing card.\n");
5340 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5341 hdsp->io_type = RPM;
5342 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5343 hdsp->io_type = Multiface;
5344 else
5345 hdsp->io_type = Digiface;
5346 }
5347 }
5348
5349 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5350 return err;
5351
5352 if (is_9652)
5353 hdsp->io_type = H9652;
5354
5355 if (is_9632)
5356 hdsp->io_type = H9632;
5357
5358 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5359 return err;
5360
5361 snd_hdsp_initialize_channels(hdsp);
5362 snd_hdsp_initialize_midi_flush(hdsp);
5363
5364 hdsp->state |= HDSP_FirmwareLoaded;
5365
5366 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5367 return err;
5368
5369 return 0;
5370 }
5371
5372 static int snd_hdsp_free(struct hdsp *hdsp)
5373 {
5374 if (hdsp->port) {
5375 /* stop the audio, and cancel all interrupts */
5376 cancel_work_sync(&hdsp->midi_work);
5377 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5378 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5379 }
5380
5381 if (hdsp->irq >= 0)
5382 free_irq(hdsp->irq, (void *)hdsp);
5383
5384 snd_hdsp_free_buffers(hdsp);
5385
5386 release_firmware(hdsp->firmware);
5387 vfree(hdsp->fw_uploaded);
5388 iounmap(hdsp->iobase);
5389
5390 if (hdsp->port)
5391 pci_release_regions(hdsp->pci);
5392
5393 pci_disable_device(hdsp->pci);
5394 return 0;
5395 }
5396
5397 static void snd_hdsp_card_free(struct snd_card *card)
5398 {
5399 struct hdsp *hdsp = card->private_data;
5400
5401 if (hdsp)
5402 snd_hdsp_free(hdsp);
5403 }
5404
5405 static int snd_hdsp_probe(struct pci_dev *pci,
5406 const struct pci_device_id *pci_id)
5407 {
5408 static int dev;
5409 struct hdsp *hdsp;
5410 struct snd_card *card;
5411 int err;
5412
5413 if (dev >= SNDRV_CARDS)
5414 return -ENODEV;
5415 if (!enable[dev]) {
5416 dev++;
5417 return -ENOENT;
5418 }
5419
5420 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5421 sizeof(struct hdsp), &card);
5422 if (err < 0)
5423 return err;
5424
5425 hdsp = card->private_data;
5426 card->private_free = snd_hdsp_card_free;
5427 hdsp->dev = dev;
5428 hdsp->pci = pci;
5429 err = snd_hdsp_create(card, hdsp);
5430 if (err)
5431 goto free_card;
5432
5433 strcpy(card->shortname, "Hammerfall DSP");
5434 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5435 hdsp->port, hdsp->irq);
5436 err = snd_card_register(card);
5437 if (err) {
5438 free_card:
5439 snd_card_free(card);
5440 return err;
5441 }
5442 pci_set_drvdata(pci, card);
5443 dev++;
5444 return 0;
5445 }
5446
5447 static void snd_hdsp_remove(struct pci_dev *pci)
5448 {
5449 snd_card_free(pci_get_drvdata(pci));
5450 }
5451
5452 static struct pci_driver hdsp_driver = {
5453 .name = KBUILD_MODNAME,
5454 .id_table = snd_hdsp_ids,
5455 .probe = snd_hdsp_probe,
5456 .remove = snd_hdsp_remove,
5457 };
5458
5459 module_pci_driver(hdsp_driver);