sound/soc/amd/acp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ACP_HW_H
   3 #define __ACP_HW_H
   4
   5 #include "include/acp_2_2_d.h"
   6 #include "include/acp_2_2_sh_mask.h"
   7
   8 #define ACP_PAGE_SIZE_4K_ENABLE                 0x02
   9
  10 #define ACP_PLAYBACK_PTE_OFFSET                 10
  11 #define ACP_CAPTURE_PTE_OFFSET                  0
  12
  13 #define ACP_GARLIC_CNTL_DEFAULT                 0x00000FB4
  14 #define ACP_ONION_CNTL_DEFAULT                  0x00000FB4
  15
  16 #define ACP_PHYSICAL_BASE                       0x14000
  17
  18 /* Playback SRAM address (as a destination in dma descriptor) */
  19 #define ACP_SHARED_RAM_BANK_1_ADDRESS           0x4002000
  20
  21 /* Capture SRAM address (as a source in dma descriptor) */
  22 #define ACP_SHARED_RAM_BANK_5_ADDRESS           0x400A000
  23 #define ACP_SHARED_RAM_BANK_3_ADDRESS           0x4006000
  24
  25 #define ACP_DMA_RESET_TIME                      10000
  26 #define ACP_CLOCK_EN_TIME_OUT_VALUE             0x000000FF
  27 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE      0x000000FF
  28 #define ACP_DMA_COMPLETE_TIME_OUT_VALUE         0x000000FF
  29
  30 #define ACP_SRAM_BASE_ADDRESS                   0x4000000
  31 #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS          0x4001000
  32 #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET      0x1000
  33 #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS  0x00000000
  34 #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS  0x01800000
  35
  36 #define TO_ACP_I2S_1   0x2
  37 #define TO_ACP_I2S_2   0x4
  38 #define FROM_ACP_I2S_1 0xa
  39 #define FROM_ACP_I2S_2 0xb
  40
  41 #define ACP_TILE_ON_MASK                0x03
  42 #define ACP_TILE_OFF_MASK               0x02
  43 #define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
  44 #define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
  45
  46 #define ACP_TILE_P1_MASK                0x3e
  47 #define ACP_TILE_P2_MASK                0x3d
  48 #define ACP_TILE_DSP0_MASK              0x3b
  49 #define ACP_TILE_DSP1_MASK              0x37
  50
  51 #define ACP_TILE_DSP2_MASK              0x2f
  52 /* Playback DMA channels */
  53 #define SYSRAM_TO_ACP_CH_NUM 12
  54 #define ACP_TO_I2S_DMA_CH_NUM 13
  55
  56 /* Capture DMA channels */
  57 #define ACP_TO_SYSRAM_CH_NUM 14
  58 #define I2S_TO_ACP_DMA_CH_NUM 15
  59
  60 #define NUM_DSCRS_PER_CHANNEL 2
  61
  62 #define PLAYBACK_START_DMA_DESCR_CH12 0
  63 #define PLAYBACK_END_DMA_DESCR_CH12 1
  64 #define PLAYBACK_START_DMA_DESCR_CH13 2
  65 #define PLAYBACK_END_DMA_DESCR_CH13 3
  66
  67 #define CAPTURE_START_DMA_DESCR_CH14 4
  68 #define CAPTURE_END_DMA_DESCR_CH14 5
  69 #define CAPTURE_START_DMA_DESCR_CH15 6
  70 #define CAPTURE_END_DMA_DESCR_CH15 7
  71
  72 #define mmACP_I2S_16BIT_RESOLUTION_EN       0x5209
  73 enum acp_dma_priority_level {
  74         /* 0x0 Specifies the DMA channel is given normal priority */
  75         ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
  76         /* 0x1 Specifies the DMA channel is given high priority */
  77         ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
  78         ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
  79 };
  80
  81 struct audio_substream_data {
  82         struct page *pg;
  83         unsigned int order;
  84         u16 num_of_pages;
  85         u16 direction;
  86         uint64_t size;
  87         u64 renderbytescount;
  88         u64 capturebytescount;
  89         void __iomem *acp_mmio;
  90 };
  91
  92 struct audio_drv_data {
  93         struct snd_pcm_substream *play_stream;
  94         struct snd_pcm_substream *capture_stream;
  95         void __iomem *acp_mmio;
  96         u32 asic_type;
  97 };
  98
  99 union acp_dma_count {
 100         struct {
 101         u32 low;
 102         u32 high;
 103         } bcount;
 104         u64 bytescount;
 105 };
 106
 107 enum {
 108         ACP_TILE_P1 = 0,
 109         ACP_TILE_P2,
 110         ACP_TILE_DSP0,
 111         ACP_TILE_DSP1,
 112         ACP_TILE_DSP2,
 113 };
 114
 115 enum {
 116         ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0,
 117         ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
 118         ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8,
 119         ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
 120         ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF
 121 };
 122
 123 typedef struct acp_dma_dscr_transfer {
 124         /* Specifies the source memory location for the DMA data transfer. */
 125         u32 src;
 126         /* Specifies the destination memory location to where the data will
 127          * be transferred.
 128         */
 129         u32 dest;
 130         /* Specifies the number of bytes need to be transferred
 131         * from source to destination memory.Transfer direction & IOC enable
 132         */
 133         u32 xfer_val;
 134         /* Reserved for future use */
 135         u32 reserved;
 136 } acp_dma_dscr_transfer_t;
 137
 138 #endif /*__ACP_HW_H */