sound/soc/bcm/bcm2835-i2s.c

   1 /*
   2  * ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
   3  *
   4  * Author:      Florian Meier <florian.meier@koalo.de>
   5  *              Copyright 2013
   6  *
   7  * Based on
   8  *      Raspberry Pi PCM I2S ALSA Driver
   9  *      Copyright (c) by Phil Poole 2013
  10  *
  11  *      ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
  12  *      Vladimir Barinov, <vbarinov@embeddedalley.com>
  13  *      Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  14  *
  15  *      OMAP ALSA SoC DAI driver using McBSP port
  16  *      Copyright (C) 2008 Nokia Corporation
  17  *      Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  18  *               Peter Ujfalusi <peter.ujfalusi@ti.com>
  19  *
  20  *      Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  21  *      Author: Timur Tabi <timur@freescale.com>
  22  *      Copyright 2007-2010 Freescale Semiconductor, Inc.
  23  *
  24  * This program is free software; you can redistribute it and/or
  25  * modify it under the terms of the GNU General Public License
  26  * version 2 as published by the Free Software Foundation.
  27  *
  28  * This program is distributed in the hope that it will be useful, but
  29  * WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  31  * General Public License for more details.
  32  */
  33
  34 #include <linux/bitops.h>
  35 #include <linux/clk.h>
  36 #include <linux/delay.h>
  37 #include <linux/device.h>
  38 #include <linux/init.h>
  39 #include <linux/io.h>
  40 #include <linux/module.h>
  41 #include <linux/of_address.h>
  42 #include <linux/slab.h>
  43
  44 #include <sound/core.h>
  45 #include <sound/dmaengine_pcm.h>
  46 #include <sound/initval.h>
  47 #include <sound/pcm.h>
  48 #include <sound/pcm_params.h>
  49 #include <sound/soc.h>
  50
  51 /* I2S registers */
  52 #define BCM2835_I2S_CS_A_REG            0x00
  53 #define BCM2835_I2S_FIFO_A_REG          0x04
  54 #define BCM2835_I2S_MODE_A_REG          0x08
  55 #define BCM2835_I2S_RXC_A_REG           0x0c
  56 #define BCM2835_I2S_TXC_A_REG           0x10
  57 #define BCM2835_I2S_DREQ_A_REG          0x14
  58 #define BCM2835_I2S_INTEN_A_REG 0x18
  59 #define BCM2835_I2S_INTSTC_A_REG        0x1c
  60 #define BCM2835_I2S_GRAY_REG            0x20
  61
  62 /* I2S register settings */
  63 #define BCM2835_I2S_STBY                BIT(25)
  64 #define BCM2835_I2S_SYNC                BIT(24)
  65 #define BCM2835_I2S_RXSEX               BIT(23)
  66 #define BCM2835_I2S_RXF         BIT(22)
  67 #define BCM2835_I2S_TXE         BIT(21)
  68 #define BCM2835_I2S_RXD         BIT(20)
  69 #define BCM2835_I2S_TXD         BIT(19)
  70 #define BCM2835_I2S_RXR         BIT(18)
  71 #define BCM2835_I2S_TXW         BIT(17)
  72 #define BCM2835_I2S_CS_RXERR            BIT(16)
  73 #define BCM2835_I2S_CS_TXERR            BIT(15)
  74 #define BCM2835_I2S_RXSYNC              BIT(14)
  75 #define BCM2835_I2S_TXSYNC              BIT(13)
  76 #define BCM2835_I2S_DMAEN               BIT(9)
  77 #define BCM2835_I2S_RXTHR(v)            ((v) << 7)
  78 #define BCM2835_I2S_TXTHR(v)            ((v) << 5)
  79 #define BCM2835_I2S_RXCLR               BIT(4)
  80 #define BCM2835_I2S_TXCLR               BIT(3)
  81 #define BCM2835_I2S_TXON                BIT(2)
  82 #define BCM2835_I2S_RXON                BIT(1)
  83 #define BCM2835_I2S_EN                  (1)
  84
  85 #define BCM2835_I2S_CLKDIS              BIT(28)
  86 #define BCM2835_I2S_PDMN                BIT(27)
  87 #define BCM2835_I2S_PDME                BIT(26)
  88 #define BCM2835_I2S_FRXP                BIT(25)
  89 #define BCM2835_I2S_FTXP                BIT(24)
  90 #define BCM2835_I2S_CLKM                BIT(23)
  91 #define BCM2835_I2S_CLKI                BIT(22)
  92 #define BCM2835_I2S_FSM         BIT(21)
  93 #define BCM2835_I2S_FSI         BIT(20)
  94 #define BCM2835_I2S_FLEN(v)             ((v) << 10)
  95 #define BCM2835_I2S_FSLEN(v)            (v)
  96
  97 #define BCM2835_I2S_CHWEX               BIT(15)
  98 #define BCM2835_I2S_CHEN                BIT(14)
  99 #define BCM2835_I2S_CHPOS(v)            ((v) << 4)
 100 #define BCM2835_I2S_CHWID(v)            (v)
 101 #define BCM2835_I2S_CH1(v)              ((v) << 16)
 102 #define BCM2835_I2S_CH2(v)              (v)
 103 #define BCM2835_I2S_CH1_POS(v)          BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
 104 #define BCM2835_I2S_CH2_POS(v)          BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
 105
 106 #define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
 107 #define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
 108 #define BCM2835_I2S_TX(v)               ((v) << 8)
 109 #define BCM2835_I2S_RX(v)               (v)
 110
 111 #define BCM2835_I2S_INT_RXERR           BIT(3)
 112 #define BCM2835_I2S_INT_TXERR           BIT(2)
 113 #define BCM2835_I2S_INT_RXR             BIT(1)
 114 #define BCM2835_I2S_INT_TXW             BIT(0)
 115
 116 /* Frame length register is 10 bit, maximum length 1024 */
 117 #define BCM2835_I2S_MAX_FRAME_LENGTH    1024
 118
 119 /* General device struct */
 120 struct bcm2835_i2s_dev {
 121         struct device                           *dev;
 122         struct snd_dmaengine_dai_dma_data       dma_data[2];
 123         unsigned int                            fmt;
 124         unsigned int                            tdm_slots;
 125         unsigned int                            rx_mask;
 126         unsigned int                            tx_mask;
 127         unsigned int                            slot_width;
 128         unsigned int                            frame_length;
 129
 130         struct regmap                           *i2s_regmap;
 131         struct clk                              *clk;
 132         bool                                    clk_prepared;
 133 };
 134
 135 static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
 136 {
 137         unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 138
 139         if (dev->clk_prepared)
 140                 return;
 141
 142         switch (master) {
 143         case SND_SOC_DAIFMT_CBS_CFS:
 144         case SND_SOC_DAIFMT_CBS_CFM:
 145                 clk_prepare_enable(dev->clk);
 146                 dev->clk_prepared = true;
 147                 break;
 148         default:
 149                 break;
 150         }
 151 }
 152
 153 static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
 154 {
 155         if (dev->clk_prepared)
 156                 clk_disable_unprepare(dev->clk);
 157         dev->clk_prepared = false;
 158 }
 159
 160 static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
 161                                     bool tx, bool rx)
 162 {
 163         int timeout = 1000;
 164         uint32_t syncval;
 165         uint32_t csreg;
 166         uint32_t i2s_active_state;
 167         bool clk_was_prepared;
 168         uint32_t off;
 169         uint32_t clr;
 170
 171         off =  tx ? BCM2835_I2S_TXON : 0;
 172         off |= rx ? BCM2835_I2S_RXON : 0;
 173
 174         clr =  tx ? BCM2835_I2S_TXCLR : 0;
 175         clr |= rx ? BCM2835_I2S_RXCLR : 0;
 176
 177         /* Backup the current state */
 178         regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
 179         i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
 180
 181         /* Start clock if not running */
 182         clk_was_prepared = dev->clk_prepared;
 183         if (!clk_was_prepared)
 184                 bcm2835_i2s_start_clock(dev);
 185
 186         /* Stop I2S module */
 187         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
 188
 189         /*
 190          * Clear the FIFOs
 191          * Requires at least 2 PCM clock cycles to take effect
 192          */
 193         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
 194
 195         /* Wait for 2 PCM clock cycles */
 196
 197         /*
 198          * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
 199          * FIXME: This does not seem to work for slave mode!
 200          */
 201         regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
 202         syncval &= BCM2835_I2S_SYNC;
 203
 204         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
 205                         BCM2835_I2S_SYNC, ~syncval);
 206
 207         /* Wait for the SYNC flag changing it's state */
 208         while (--timeout) {
 209                 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
 210                 if ((csreg & BCM2835_I2S_SYNC) != syncval)
 211                         break;
 212         }
 213
 214         if (!timeout)
 215                 dev_err(dev->dev, "I2S SYNC error!\n");
 216
 217         /* Stop clock if it was not running before */
 218         if (!clk_was_prepared)
 219                 bcm2835_i2s_stop_clock(dev);
 220
 221         /* Restore I2S state */
 222         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
 223                         BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
 224 }
 225
 226 static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
 227                                       unsigned int fmt)
 228 {
 229         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 230         dev->fmt = fmt;
 231         return 0;
 232 }
 233
 234 static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
 235                                       unsigned int ratio)
 236 {
 237         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 238
 239         if (!ratio) {
 240                 dev->tdm_slots = 0;
 241                 return 0;
 242         }
 243
 244         if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
 245                 return -EINVAL;
 246
 247         dev->tdm_slots = 2;
 248         dev->rx_mask = 0x03;
 249         dev->tx_mask = 0x03;
 250         dev->slot_width = ratio / 2;
 251         dev->frame_length = ratio;
 252
 253         return 0;
 254 }
 255
 256 static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
 257         unsigned int tx_mask, unsigned int rx_mask,
 258         int slots, int width)
 259 {
 260         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 261
 262         if (slots) {
 263                 if (slots < 0 || width < 0)
 264                         return -EINVAL;
 265
 266                 /* Limit masks to available slots */
 267                 rx_mask &= GENMASK(slots - 1, 0);
 268                 tx_mask &= GENMASK(slots - 1, 0);
 269
 270                 /*
 271                  * The driver is limited to 2-channel setups.
 272                  * Check that exactly 2 bits are set in the masks.
 273                  */
 274                 if (hweight_long((unsigned long) rx_mask) != 2
 275                     || hweight_long((unsigned long) tx_mask) != 2)
 276                         return -EINVAL;
 277
 278                 if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
 279                         return -EINVAL;
 280         }
 281
 282         dev->tdm_slots = slots;
 283
 284         dev->rx_mask = rx_mask;
 285         dev->tx_mask = tx_mask;
 286         dev->slot_width = width;
 287         dev->frame_length = slots * width;
 288
 289         return 0;
 290 }
 291
 292 /*
 293  * Convert logical slot number into physical slot number.
 294  *
 295  * If odd_offset is 0 sequential number is identical to logical number.
 296  * This is used for DSP modes with slot numbering 0 1 2 3 ...
 297  *
 298  * Otherwise odd_offset defines the physical offset for odd numbered
 299  * slots. This is used for I2S and left/right justified modes to
 300  * translate from logical slot numbers 0 1 2 3 ... into physical slot
 301  * numbers 0 2 ... 3 4 ...
 302  */
 303 static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
 304 {
 305         if (!odd_offset)
 306                 return slot;
 307
 308         if (slot & 1)
 309                 return (slot >> 1) + odd_offset;
 310
 311         return slot >> 1;
 312 }
 313
 314 /*
 315  * Calculate channel position from mask and slot width.
 316  *
 317  * Mask must contain exactly 2 set bits.
 318  * Lowest set bit is channel 1 position, highest set bit channel 2.
 319  * The constant offset is added to both channel positions.
 320  *
 321  * If odd_offset is > 0 slot positions are translated to
 322  * I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
 323  * logical slot numbers starting at physical slot odd_offset.
 324  */
 325 static void bcm2835_i2s_calc_channel_pos(
 326         unsigned int *ch1_pos, unsigned int *ch2_pos,
 327         unsigned int mask, unsigned int width,
 328         unsigned int bit_offset, unsigned int odd_offset)
 329 {
 330         *ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
 331                         * width + bit_offset;
 332         *ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
 333                         * width + bit_offset;
 334 }
 335
 336 static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
 337                                  struct snd_pcm_hw_params *params,
 338                                  struct snd_soc_dai *dai)
 339 {
 340         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 341         unsigned int data_length, data_delay, framesync_length;
 342         unsigned int slots, slot_width, odd_slot_offset;
 343         int frame_length, bclk_rate;
 344         unsigned int rx_mask, tx_mask;
 345         unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
 346         unsigned int mode, format;
 347         uint32_t csreg;
 348         int ret = 0;
 349
 350         /*
 351          * If a stream is already enabled,
 352          * the registers are already set properly.
 353          */
 354         regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
 355
 356         if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
 357                 return 0;
 358
 359         data_length = params_width(params);
 360         data_delay = 0;
 361         odd_slot_offset = 0;
 362         mode = 0;
 363
 364         if (dev->tdm_slots) {
 365                 slots = dev->tdm_slots;
 366                 slot_width = dev->slot_width;
 367                 frame_length = dev->frame_length;
 368                 rx_mask = dev->rx_mask;
 369                 tx_mask = dev->tx_mask;
 370                 bclk_rate = dev->frame_length * params_rate(params);
 371         } else {
 372                 slots = 2;
 373                 slot_width = params_width(params);
 374                 rx_mask = 0x03;
 375                 tx_mask = 0x03;
 376
 377                 frame_length = snd_soc_params_to_frame_size(params);
 378                 if (frame_length < 0)
 379                         return frame_length;
 380
 381                 bclk_rate = snd_soc_params_to_bclk(params);
 382                 if (bclk_rate < 0)
 383                         return bclk_rate;
 384         }
 385
 386         /* Check if data fits into slots */
 387         if (data_length > slot_width)
 388                 return -EINVAL;
 389
 390         /* Clock should only be set up here if CPU is clock master */
 391         switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 392         case SND_SOC_DAIFMT_CBS_CFS:
 393         case SND_SOC_DAIFMT_CBS_CFM:
 394                 ret = clk_set_rate(dev->clk, bclk_rate);
 395                 if (ret)
 396                         return ret;
 397                 break;
 398         default:
 399                 break;
 400         }
 401
 402         /* Setup the frame format */
 403         format = BCM2835_I2S_CHEN;
 404
 405         if (data_length >= 24)
 406                 format |= BCM2835_I2S_CHWEX;
 407
 408         format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
 409
 410         /* CH2 format is the same as for CH1 */
 411         format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
 412
 413         switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 414         case SND_SOC_DAIFMT_I2S:
 415                 /* I2S mode needs an even number of slots */
 416                 if (slots & 1)
 417                         return -EINVAL;
 418
 419                 /*
 420                  * Use I2S-style logical slot numbering: even slots
 421                  * are in first half of frame, odd slots in second half.
 422                  */
 423                 odd_slot_offset = slots >> 1;
 424
 425                 /* MSB starts one cycle after frame start */
 426                 data_delay = 1;
 427
 428                 /* Setup frame sync signal for 50% duty cycle */
 429                 framesync_length = frame_length / 2;
 430                 break;
 431         default:
 432                 /*
 433                  * TODO
 434                  * Others are possible but are not implemented at the moment.
 435                  */
 436                 dev_err(dev->dev, "%s:bad format\n", __func__);
 437                 return -EINVAL;
 438         }
 439
 440         bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
 441                 rx_mask, slot_width, data_delay, odd_slot_offset);
 442         bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
 443                 tx_mask, slot_width, data_delay, odd_slot_offset);
 444
 445         /*
 446          * Set format for both streams.
 447          * We cannot set another frame length
 448          * (and therefore word length) anyway,
 449          * so the format will be the same.
 450          */
 451         regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG,
 452                   format
 453                 | BCM2835_I2S_CH1_POS(rx_ch1_pos)
 454                 | BCM2835_I2S_CH2_POS(rx_ch2_pos));
 455         regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG,
 456                   format
 457                 | BCM2835_I2S_CH1_POS(tx_ch1_pos)
 458                 | BCM2835_I2S_CH2_POS(tx_ch2_pos));
 459
 460         /* Setup the I2S mode */
 461
 462         if (data_length <= 16) {
 463                 /*
 464                  * Use frame packed mode (2 channels per 32 bit word)
 465                  * We cannot set another frame length in the second stream
 466                  * (and therefore word length) anyway,
 467                  * so the format will be the same.
 468                  */
 469                 mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
 470         }
 471
 472         mode |= BCM2835_I2S_FLEN(frame_length - 1);
 473         mode |= BCM2835_I2S_FSLEN(framesync_length);
 474
 475         /* Master or slave? */
 476         switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 477         case SND_SOC_DAIFMT_CBS_CFS:
 478                 /* CPU is master */
 479                 break;
 480         case SND_SOC_DAIFMT_CBM_CFS:
 481                 /*
 482                  * CODEC is bit clock master
 483                  * CPU is frame master
 484                  */
 485                 mode |= BCM2835_I2S_CLKM;
 486                 break;
 487         case SND_SOC_DAIFMT_CBS_CFM:
 488                 /*
 489                  * CODEC is frame master
 490                  * CPU is bit clock master
 491                  */
 492                 mode |= BCM2835_I2S_FSM;
 493                 break;
 494         case SND_SOC_DAIFMT_CBM_CFM:
 495                 /* CODEC is master */
 496                 mode |= BCM2835_I2S_CLKM;
 497                 mode |= BCM2835_I2S_FSM;
 498                 break;
 499         default:
 500                 dev_err(dev->dev, "%s:bad master\n", __func__);
 501                 return -EINVAL;
 502         }
 503
 504         /*
 505          * Invert clocks?
 506          *
 507          * The BCM approach seems to be inverted to the classical I2S approach.
 508          */
 509         switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
 510         case SND_SOC_DAIFMT_NB_NF:
 511                 /* None. Therefore, both for BCM */
 512                 mode |= BCM2835_I2S_CLKI;
 513                 mode |= BCM2835_I2S_FSI;
 514                 break;
 515         case SND_SOC_DAIFMT_IB_IF:
 516                 /* Both. Therefore, none for BCM */
 517                 break;
 518         case SND_SOC_DAIFMT_NB_IF:
 519                 /*
 520                  * Invert only frame sync. Therefore,
 521                  * invert only bit clock for BCM
 522                  */
 523                 mode |= BCM2835_I2S_CLKI;
 524                 break;
 525         case SND_SOC_DAIFMT_IB_NF:
 526                 /*
 527                  * Invert only bit clock. Therefore,
 528                  * invert only frame sync for BCM
 529                  */
 530                 mode |= BCM2835_I2S_FSI;
 531                 break;
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);
 537
 538         /* Setup the DMA parameters */
 539         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
 540                         BCM2835_I2S_RXTHR(1)
 541                         | BCM2835_I2S_TXTHR(1)
 542                         | BCM2835_I2S_DMAEN, 0xffffffff);
 543
 544         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
 545                           BCM2835_I2S_TX_PANIC(0x10)
 546                         | BCM2835_I2S_RX_PANIC(0x30)
 547                         | BCM2835_I2S_TX(0x30)
 548                         | BCM2835_I2S_RX(0x20), 0xffffffff);
 549
 550         /* Clear FIFOs */
 551         bcm2835_i2s_clear_fifos(dev, true, true);
 552
 553         dev_dbg(dev->dev,
 554                 "slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
 555                 slots, slot_width, rx_mask, tx_mask);
 556
 557         dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
 558                 frame_length, framesync_length, data_length);
 559
 560         dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
 561                 rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
 562
 563         dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
 564                 params_rate(params), bclk_rate);
 565
 566         return ret;
 567 }
 568
 569 static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
 570                 struct snd_soc_dai *dai)
 571 {
 572         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 573         uint32_t cs_reg;
 574
 575         bcm2835_i2s_start_clock(dev);
 576
 577         /*
 578          * Clear both FIFOs if the one that should be started
 579          * is not empty at the moment. This should only happen
 580          * after overrun. Otherwise, hw_params would have cleared
 581          * the FIFO.
 582          */
 583         regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);
 584
 585         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
 586                         && !(cs_reg & BCM2835_I2S_TXE))
 587                 bcm2835_i2s_clear_fifos(dev, true, false);
 588         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
 589                         && (cs_reg & BCM2835_I2S_RXD))
 590                 bcm2835_i2s_clear_fifos(dev, false, true);
 591
 592         return 0;
 593 }
 594
 595 static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
 596                 struct snd_pcm_substream *substream,
 597                 struct snd_soc_dai *dai)
 598 {
 599         uint32_t mask;
 600
 601         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 602                 mask = BCM2835_I2S_RXON;
 603         else
 604                 mask = BCM2835_I2S_TXON;
 605
 606         regmap_update_bits(dev->i2s_regmap,
 607                         BCM2835_I2S_CS_A_REG, mask, 0);
 608
 609         /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
 610         if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
 611                 bcm2835_i2s_stop_clock(dev);
 612 }
 613
 614 static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 615                                struct snd_soc_dai *dai)
 616 {
 617         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 618         uint32_t mask;
 619
 620         switch (cmd) {
 621         case SNDRV_PCM_TRIGGER_START:
 622         case SNDRV_PCM_TRIGGER_RESUME:
 623         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 624                 bcm2835_i2s_start_clock(dev);
 625
 626                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 627                         mask = BCM2835_I2S_RXON;
 628                 else
 629                         mask = BCM2835_I2S_TXON;
 630
 631                 regmap_update_bits(dev->i2s_regmap,
 632                                 BCM2835_I2S_CS_A_REG, mask, mask);
 633                 break;
 634
 635         case SNDRV_PCM_TRIGGER_STOP:
 636         case SNDRV_PCM_TRIGGER_SUSPEND:
 637         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 638                 bcm2835_i2s_stop(dev, substream, dai);
 639                 break;
 640         default:
 641                 return -EINVAL;
 642         }
 643
 644         return 0;
 645 }
 646
 647 static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
 648                                struct snd_soc_dai *dai)
 649 {
 650         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 651
 652         if (dai->active)
 653                 return 0;
 654
 655         /* Should this still be running stop it */
 656         bcm2835_i2s_stop_clock(dev);
 657
 658         /* Enable PCM block */
 659         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
 660                         BCM2835_I2S_EN, BCM2835_I2S_EN);
 661
 662         /*
 663          * Disable STBY.
 664          * Requires at least 4 PCM clock cycles to take effect.
 665          */
 666         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
 667                         BCM2835_I2S_STBY, BCM2835_I2S_STBY);
 668
 669         return 0;
 670 }
 671
 672 static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
 673                 struct snd_soc_dai *dai)
 674 {
 675         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 676
 677         bcm2835_i2s_stop(dev, substream, dai);
 678
 679         /* If both streams are stopped, disable module and clock */
 680         if (dai->active)
 681                 return;
 682
 683         /* Disable the module */
 684         regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
 685                         BCM2835_I2S_EN, 0);
 686
 687         /*
 688          * Stopping clock is necessary, because stop does
 689          * not stop the clock when SND_SOC_DAIFMT_CONT
 690          */
 691         bcm2835_i2s_stop_clock(dev);
 692 }
 693
 694 static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
 695         .startup        = bcm2835_i2s_startup,
 696         .shutdown       = bcm2835_i2s_shutdown,
 697         .prepare        = bcm2835_i2s_prepare,
 698         .trigger        = bcm2835_i2s_trigger,
 699         .hw_params      = bcm2835_i2s_hw_params,
 700         .set_fmt        = bcm2835_i2s_set_dai_fmt,
 701         .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
 702         .set_tdm_slot   = bcm2835_i2s_set_dai_tdm_slot,
 703 };
 704
 705 static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
 706 {
 707         struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 708
 709         snd_soc_dai_init_dma_data(dai,
 710                         &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
 711                         &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
 712
 713         return 0;
 714 }
 715
 716 static struct snd_soc_dai_driver bcm2835_i2s_dai = {
 717         .name   = "bcm2835-i2s",
 718         .probe  = bcm2835_i2s_dai_probe,
 719         .playback = {
 720                 .channels_min = 2,
 721                 .channels_max = 2,
 722                 .rates =        SNDRV_PCM_RATE_8000_192000,
 723                 .formats =      SNDRV_PCM_FMTBIT_S16_LE
 724                                 | SNDRV_PCM_FMTBIT_S24_LE
 725                                 | SNDRV_PCM_FMTBIT_S32_LE
 726                 },
 727         .capture = {
 728                 .channels_min = 2,
 729                 .channels_max = 2,
 730                 .rates =        SNDRV_PCM_RATE_8000_192000,
 731                 .formats =      SNDRV_PCM_FMTBIT_S16_LE
 732                                 | SNDRV_PCM_FMTBIT_S24_LE
 733                                 | SNDRV_PCM_FMTBIT_S32_LE
 734                 },
 735         .ops = &bcm2835_i2s_dai_ops,
 736         .symmetric_rates = 1
 737 };
 738
 739 static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
 740 {
 741         switch (reg) {
 742         case BCM2835_I2S_CS_A_REG:
 743         case BCM2835_I2S_FIFO_A_REG:
 744         case BCM2835_I2S_INTSTC_A_REG:
 745         case BCM2835_I2S_GRAY_REG:
 746                 return true;
 747         default:
 748                 return false;
 749         };
 750 }
 751
 752 static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
 753 {
 754         switch (reg) {
 755         case BCM2835_I2S_FIFO_A_REG:
 756                 return true;
 757         default:
 758                 return false;
 759         };
 760 }
 761
 762 static const struct regmap_config bcm2835_regmap_config = {
 763         .reg_bits = 32,
 764         .reg_stride = 4,
 765         .val_bits = 32,
 766         .max_register = BCM2835_I2S_GRAY_REG,
 767         .precious_reg = bcm2835_i2s_precious_reg,
 768         .volatile_reg = bcm2835_i2s_volatile_reg,
 769         .cache_type = REGCACHE_RBTREE,
 770 };
 771
 772 static const struct snd_soc_component_driver bcm2835_i2s_component = {
 773         .name           = "bcm2835-i2s-comp",
 774 };
 775
 776 static int bcm2835_i2s_probe(struct platform_device *pdev)
 777 {
 778         struct bcm2835_i2s_dev *dev;
 779         int ret;
 780         struct resource *mem;
 781         void __iomem *base;
 782         const __be32 *addr;
 783         dma_addr_t dma_base;
 784
 785         dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
 786                            GFP_KERNEL);
 787         if (!dev)
 788                 return -ENOMEM;
 789
 790         /* get the clock */
 791         dev->clk_prepared = false;
 792         dev->clk = devm_clk_get(&pdev->dev, NULL);
 793         if (IS_ERR(dev->clk)) {
 794                 dev_err(&pdev->dev, "could not get clk: %ld\n",
 795                         PTR_ERR(dev->clk));
 796                 return PTR_ERR(dev->clk);
 797         }
 798
 799         /* Request ioarea */
 800         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 801         base = devm_ioremap_resource(&pdev->dev, mem);
 802         if (IS_ERR(base))
 803                 return PTR_ERR(base);
 804
 805         dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
 806                                 &bcm2835_regmap_config);
 807         if (IS_ERR(dev->i2s_regmap))
 808                 return PTR_ERR(dev->i2s_regmap);
 809
 810         /* Set the DMA address - we have to parse DT ourselves */
 811         addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
 812         if (!addr) {
 813                 dev_err(&pdev->dev, "could not get DMA-register address\n");
 814                 return -EINVAL;
 815         }
 816         dma_base = be32_to_cpup(addr);
 817
 818         dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
 819                 dma_base + BCM2835_I2S_FIFO_A_REG;
 820
 821         dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
 822                 dma_base + BCM2835_I2S_FIFO_A_REG;
 823
 824         /* Set the bus width */
 825         dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
 826                 DMA_SLAVE_BUSWIDTH_4_BYTES;
 827         dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
 828                 DMA_SLAVE_BUSWIDTH_4_BYTES;
 829
 830         /* Set burst */
 831         dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
 832         dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
 833
 834         /*
 835          * Set the PACK flag to enable S16_LE support (2 S16_LE values
 836          * packed into 32-bit transfers).
 837          */
 838         dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags =
 839                 SND_DMAENGINE_PCM_DAI_FLAG_PACK;
 840         dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
 841                 SND_DMAENGINE_PCM_DAI_FLAG_PACK;
 842
 843         /* Store the pdev */
 844         dev->dev = &pdev->dev;
 845         dev_set_drvdata(&pdev->dev, dev);
 846
 847         ret = devm_snd_soc_register_component(&pdev->dev,
 848                         &bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
 849         if (ret) {
 850                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 851                 return ret;
 852         }
 853
 854         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 855         if (ret) {
 856                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 857                 return ret;
 858         }
 859
 860         return 0;
 861 }
 862
 863 static const struct of_device_id bcm2835_i2s_of_match[] = {
 864         { .compatible = "brcm,bcm2835-i2s", },
 865         {},
 866 };
 867
 868 MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
 869
 870 static struct platform_driver bcm2835_i2s_driver = {
 871         .probe          = bcm2835_i2s_probe,
 872         .driver         = {
 873                 .name   = "bcm2835-i2s",
 874                 .of_match_table = bcm2835_i2s_of_match,
 875         },
 876 };
 877
 878 module_platform_driver(bcm2835_i2s_driver);
 879
 880 MODULE_ALIAS("platform:bcm2835-i2s");
 881 MODULE_DESCRIPTION("BCM2835 I2S interface");
 882 MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
 883 MODULE_LICENSE("GPL v2");