sound/soc/codecs/adau1977.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADAU1977/ADAU1978/ADAU1979 driver
   4  *
   5  * Copyright 2014 Analog Devices Inc.
   6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/i2c.h>
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_data/adau1977.h>
  16 #include <linux/regmap.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/slab.h>
  19
  20 #include <sound/core.h>
  21 #include <sound/initval.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/tlv.h>
  26
  27 #include "adau1977.h"
  28
  29 #define ADAU1977_REG_POWER              0x00
  30 #define ADAU1977_REG_PLL                0x01
  31 #define ADAU1977_REG_BOOST              0x02
  32 #define ADAU1977_REG_MICBIAS            0x03
  33 #define ADAU1977_REG_BLOCK_POWER_SAI    0x04
  34 #define ADAU1977_REG_SAI_CTRL0          0x05
  35 #define ADAU1977_REG_SAI_CTRL1          0x06
  36 #define ADAU1977_REG_CMAP12             0x07
  37 #define ADAU1977_REG_CMAP34             0x08
  38 #define ADAU1977_REG_SAI_OVERTEMP       0x09
  39 #define ADAU1977_REG_POST_ADC_GAIN(x)   (0x0a + (x))
  40 #define ADAU1977_REG_MISC_CONTROL       0x0e
  41 #define ADAU1977_REG_DIAG_CONTROL       0x10
  42 #define ADAU1977_REG_STATUS(x)          (0x11 + (x))
  43 #define ADAU1977_REG_DIAG_IRQ1          0x15
  44 #define ADAU1977_REG_DIAG_IRQ2          0x16
  45 #define ADAU1977_REG_ADJUST1            0x17
  46 #define ADAU1977_REG_ADJUST2            0x18
  47 #define ADAU1977_REG_ADC_CLIP           0x19
  48 #define ADAU1977_REG_DC_HPF_CAL         0x1a
  49
  50 #define ADAU1977_POWER_RESET                    BIT(7)
  51 #define ADAU1977_POWER_PWUP                     BIT(0)
  52
  53 #define ADAU1977_PLL_CLK_S                      BIT(4)
  54 #define ADAU1977_PLL_MCS_MASK                   0x7
  55
  56 #define ADAU1977_MICBIAS_MB_VOLTS_MASK          0xf0
  57 #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET        4
  58
  59 #define ADAU1977_BLOCK_POWER_SAI_LR_POL         BIT(7)
  60 #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE      BIT(6)
  61 #define ADAU1977_BLOCK_POWER_SAI_LDO_EN         BIT(5)
  62
  63 #define ADAU1977_SAI_CTRL0_FMT_MASK             (0x3 << 6)
  64 #define ADAU1977_SAI_CTRL0_FMT_I2S              (0x0 << 6)
  65 #define ADAU1977_SAI_CTRL0_FMT_LJ               (0x1 << 6)
  66 #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT         (0x2 << 6)
  67 #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT         (0x3 << 6)
  68
  69 #define ADAU1977_SAI_CTRL0_SAI_MASK             (0x7 << 3)
  70 #define ADAU1977_SAI_CTRL0_SAI_I2S              (0x0 << 3)
  71 #define ADAU1977_SAI_CTRL0_SAI_TDM_2            (0x1 << 3)
  72 #define ADAU1977_SAI_CTRL0_SAI_TDM_4            (0x2 << 3)
  73 #define ADAU1977_SAI_CTRL0_SAI_TDM_8            (0x3 << 3)
  74 #define ADAU1977_SAI_CTRL0_SAI_TDM_16           (0x4 << 3)
  75
  76 #define ADAU1977_SAI_CTRL0_FS_MASK              (0x7)
  77 #define ADAU1977_SAI_CTRL0_FS_8000_12000        (0x0)
  78 #define ADAU1977_SAI_CTRL0_FS_16000_24000       (0x1)
  79 #define ADAU1977_SAI_CTRL0_FS_32000_48000       (0x2)
  80 #define ADAU1977_SAI_CTRL0_FS_64000_96000       (0x3)
  81 #define ADAU1977_SAI_CTRL0_FS_128000_192000     (0x4)
  82
  83 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK      (0x3 << 5)
  84 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32        (0x0 << 5)
  85 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24        (0x1 << 5)
  86 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16        (0x2 << 5)
  87 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK      (0x1 << 4)
  88 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT     (0x1 << 4)
  89 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT     (0x0 << 4)
  90 #define ADAU1977_SAI_CTRL1_LRCLK_PULSE          BIT(3)
  91 #define ADAU1977_SAI_CTRL1_MSB                  BIT(2)
  92 #define ADAU1977_SAI_CTRL1_BCLKRATE_16          (0x1 << 1)
  93 #define ADAU1977_SAI_CTRL1_BCLKRATE_32          (0x0 << 1)
  94 #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK        (0x1 << 1)
  95 #define ADAU1977_SAI_CTRL1_MASTER               BIT(0)
  96
  97 #define ADAU1977_SAI_OVERTEMP_DRV_C(x)          BIT(4 + (x))
  98 #define ADAU1977_SAI_OVERTEMP_DRV_HIZ           BIT(3)
  99
 100 #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK     (0x3 << 6)
 101 #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH      (0x2 << 6)
 102 #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH      (0x1 << 6)
 103 #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH      (0x0 << 6)
 104 #define ADAU1977_MISC_CONTROL_MMUTE             BIT(4)
 105 #define ADAU1977_MISC_CONTROL_DC_CAL            BIT(0)
 106
 107 #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET    4
 108 #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET     0
 109
 110 struct adau1977 {
 111         struct regmap *regmap;
 112         bool right_j;
 113         unsigned int sysclk;
 114         enum adau1977_sysclk_src sysclk_src;
 115         struct gpio_desc *reset_gpio;
 116         enum adau1977_type type;
 117
 118         struct regulator *avdd_reg;
 119         struct regulator *dvdd_reg;
 120
 121         struct snd_pcm_hw_constraint_list constraints;
 122
 123         struct device *dev;
 124         void (*switch_mode)(struct device *dev);
 125
 126         unsigned int max_master_fs;
 127         unsigned int slot_width;
 128         bool enabled;
 129         bool master;
 130 };
 131
 132 static const struct reg_default adau1977_reg_defaults[] = {
 133         { 0x00, 0x00 },
 134         { 0x01, 0x41 },
 135         { 0x02, 0x4a },
 136         { 0x03, 0x7d },
 137         { 0x04, 0x3d },
 138         { 0x05, 0x02 },
 139         { 0x06, 0x00 },
 140         { 0x07, 0x10 },
 141         { 0x08, 0x32 },
 142         { 0x09, 0xf0 },
 143         { 0x0a, 0xa0 },
 144         { 0x0b, 0xa0 },
 145         { 0x0c, 0xa0 },
 146         { 0x0d, 0xa0 },
 147         { 0x0e, 0x02 },
 148         { 0x10, 0x0f },
 149         { 0x15, 0x20 },
 150         { 0x16, 0x00 },
 151         { 0x17, 0x00 },
 152         { 0x18, 0x00 },
 153         { 0x1a, 0x00 },
 154 };
 155
 156 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
 157
 158 static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
 159         SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
 160                 3, 0, NULL, 0)
 161 };
 162
 163 static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
 164         SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
 165                 4, 0, NULL, 0),
 166
 167         SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
 168         SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
 169         SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
 170         SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
 171
 172         SND_SOC_DAPM_INPUT("AIN1"),
 173         SND_SOC_DAPM_INPUT("AIN2"),
 174         SND_SOC_DAPM_INPUT("AIN3"),
 175         SND_SOC_DAPM_INPUT("AIN4"),
 176
 177         SND_SOC_DAPM_OUTPUT("VREF"),
 178 };
 179
 180 static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
 181         { "ADC1", NULL, "AIN1" },
 182         { "ADC2", NULL, "AIN2" },
 183         { "ADC3", NULL, "AIN3" },
 184         { "ADC4", NULL, "AIN4" },
 185
 186         { "ADC1", NULL, "Vref" },
 187         { "ADC2", NULL, "Vref" },
 188         { "ADC3", NULL, "Vref" },
 189         { "ADC4", NULL, "Vref" },
 190
 191         { "VREF", NULL, "Vref" },
 192 };
 193
 194 #define ADAU1977_VOLUME(x) \
 195         SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
 196                 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
 197                 0, 255, 1, adau1977_adc_gain)
 198
 199 #define ADAU1977_HPF_SWITCH(x) \
 200         SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
 201                 ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
 202
 203 #define ADAU1977_DC_SUB_SWITCH(x) \
 204         SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
 205                 ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
 206
 207 static const struct snd_kcontrol_new adau1977_snd_controls[] = {
 208         ADAU1977_VOLUME(1),
 209         ADAU1977_VOLUME(2),
 210         ADAU1977_VOLUME(3),
 211         ADAU1977_VOLUME(4),
 212
 213         ADAU1977_HPF_SWITCH(1),
 214         ADAU1977_HPF_SWITCH(2),
 215         ADAU1977_HPF_SWITCH(3),
 216         ADAU1977_HPF_SWITCH(4),
 217
 218         ADAU1977_DC_SUB_SWITCH(1),
 219         ADAU1977_DC_SUB_SWITCH(2),
 220         ADAU1977_DC_SUB_SWITCH(3),
 221         ADAU1977_DC_SUB_SWITCH(4),
 222 };
 223
 224 static int adau1977_reset(struct adau1977 *adau1977)
 225 {
 226         int ret;
 227
 228         /*
 229          * The reset bit is obviously volatile, but we need to be able to cache
 230          * the other bits in the register, so we can't just mark the whole
 231          * register as volatile. Since this is the only place where we'll ever
 232          * touch the reset bit just bypass the cache for this operation.
 233          */
 234         regcache_cache_bypass(adau1977->regmap, true);
 235         ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
 236                         ADAU1977_POWER_RESET);
 237         regcache_cache_bypass(adau1977->regmap, false);
 238         if (ret)
 239                 return ret;
 240
 241         return ret;
 242 }
 243
 244 /*
 245  * Returns the appropriate setting for ths FS field in the CTRL0 register
 246  * depending on the rate.
 247  */
 248 static int adau1977_lookup_fs(unsigned int rate)
 249 {
 250         if (rate >= 8000 && rate <= 12000)
 251                 return ADAU1977_SAI_CTRL0_FS_8000_12000;
 252         else if (rate >= 16000 && rate <= 24000)
 253                 return ADAU1977_SAI_CTRL0_FS_16000_24000;
 254         else if (rate >= 32000 && rate <= 48000)
 255                 return ADAU1977_SAI_CTRL0_FS_32000_48000;
 256         else if (rate >= 64000 && rate <= 96000)
 257                 return ADAU1977_SAI_CTRL0_FS_64000_96000;
 258         else if (rate >= 128000 && rate <= 192000)
 259                 return ADAU1977_SAI_CTRL0_FS_128000_192000;
 260         else
 261                 return -EINVAL;
 262 }
 263
 264 static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
 265         unsigned int fs)
 266 {
 267         unsigned int mcs;
 268
 269         /*
 270          * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
 271          * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
 272          * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
 273          */
 274
 275         rate *= 512 >> fs;
 276
 277         if (adau1977->sysclk % rate != 0)
 278                 return -EINVAL;
 279
 280         mcs = adau1977->sysclk / rate;
 281
 282         /* The factors configured by MCS are 1, 2, 3, 4, 6 */
 283         if (mcs < 1 || mcs > 6 || mcs == 5)
 284                 return -EINVAL;
 285
 286         mcs = mcs - 1;
 287         if (mcs == 5)
 288                 mcs = 4;
 289
 290         return mcs;
 291 }
 292
 293 static int adau1977_hw_params(struct snd_pcm_substream *substream,
 294         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 295 {
 296         struct snd_soc_component *component = dai->component;
 297         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
 298         unsigned int rate = params_rate(params);
 299         unsigned int slot_width;
 300         unsigned int ctrl0, ctrl0_mask;
 301         unsigned int ctrl1;
 302         int mcs, fs;
 303         int ret;
 304
 305         fs = adau1977_lookup_fs(rate);
 306         if (fs < 0)
 307                 return fs;
 308
 309         if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
 310                 mcs = adau1977_lookup_mcs(adau1977, rate, fs);
 311                 if (mcs < 0)
 312                         return mcs;
 313         } else {
 314                 mcs = 0;
 315         }
 316
 317         ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
 318         ctrl0 = fs;
 319
 320         if (adau1977->right_j) {
 321                 switch (params_width(params)) {
 322                 case 16:
 323                         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
 324                         break;
 325                 case 24:
 326                         ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
 327                         break;
 328                 default:
 329                         return -EINVAL;
 330                 }
 331                 ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
 332         }
 333
 334         if (adau1977->master) {
 335                 switch (params_width(params)) {
 336                 case 16:
 337                         ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
 338                         slot_width = 16;
 339                         break;
 340                 case 24:
 341                 case 32:
 342                         ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
 343                         slot_width = 32;
 344                         break;
 345                 default:
 346                         return -EINVAL;
 347                 }
 348
 349                 /* In TDM mode there is a fixed slot width */
 350                 if (adau1977->slot_width)
 351                         slot_width = adau1977->slot_width;
 352
 353                 if (slot_width == 16)
 354                         ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
 355                 else
 356                         ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
 357
 358                 ret = regmap_update_bits(adau1977->regmap,
 359                         ADAU1977_REG_SAI_CTRL1,
 360                         ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
 361                         ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
 362                         ctrl1);
 363                 if (ret < 0)
 364                         return ret;
 365         }
 366
 367         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
 368                                 ctrl0_mask, ctrl0);
 369         if (ret < 0)
 370                 return ret;
 371
 372         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
 373                                 ADAU1977_PLL_MCS_MASK, mcs);
 374 }
 375
 376 static int adau1977_power_disable(struct adau1977 *adau1977)
 377 {
 378         int ret = 0;
 379
 380         if (!adau1977->enabled)
 381                 return 0;
 382
 383         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
 384                 ADAU1977_POWER_PWUP, 0);
 385         if (ret)
 386                 return ret;
 387
 388         regcache_mark_dirty(adau1977->regmap);
 389
 390         gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
 391
 392         regcache_cache_only(adau1977->regmap, true);
 393
 394         regulator_disable(adau1977->avdd_reg);
 395         if (adau1977->dvdd_reg)
 396                 regulator_disable(adau1977->dvdd_reg);
 397
 398         adau1977->enabled = false;
 399
 400         return 0;
 401 }
 402
 403 static int adau1977_power_enable(struct adau1977 *adau1977)
 404 {
 405         unsigned int val;
 406         int ret = 0;
 407
 408         if (adau1977->enabled)
 409                 return 0;
 410
 411         ret = regulator_enable(adau1977->avdd_reg);
 412         if (ret)
 413                 return ret;
 414
 415         if (adau1977->dvdd_reg) {
 416                 ret = regulator_enable(adau1977->dvdd_reg);
 417                 if (ret)
 418                         goto err_disable_avdd;
 419         }
 420
 421         gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
 422
 423         regcache_cache_only(adau1977->regmap, false);
 424
 425         if (adau1977->switch_mode)
 426                 adau1977->switch_mode(adau1977->dev);
 427
 428         ret = adau1977_reset(adau1977);
 429         if (ret)
 430                 goto err_disable_dvdd;
 431
 432         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
 433                 ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
 434         if (ret)
 435                 goto err_disable_dvdd;
 436
 437         ret = regcache_sync(adau1977->regmap);
 438         if (ret)
 439                 goto err_disable_dvdd;
 440
 441         /*
 442          * The PLL register is not affected by the software reset. It is
 443          * possible that the value of the register was changed to the
 444          * default value while we were in cache only mode. In this case
 445          * regcache_sync will skip over it and we have to manually sync
 446          * it.
 447          */
 448         ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
 449         if (ret)
 450                 goto err_disable_dvdd;
 451
 452         if (val == 0x41) {
 453                 regcache_cache_bypass(adau1977->regmap, true);
 454                 ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
 455                         0x41);
 456                 if (ret)
 457                         goto err_disable_dvdd;
 458                 regcache_cache_bypass(adau1977->regmap, false);
 459         }
 460
 461         adau1977->enabled = true;
 462
 463         return ret;
 464
 465 err_disable_dvdd:
 466         if (adau1977->dvdd_reg)
 467                 regulator_disable(adau1977->dvdd_reg);
 468 err_disable_avdd:
 469                 regulator_disable(adau1977->avdd_reg);
 470         return ret;
 471 }
 472
 473 static int adau1977_set_bias_level(struct snd_soc_component *component,
 474         enum snd_soc_bias_level level)
 475 {
 476         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
 477         int ret = 0;
 478
 479         switch (level) {
 480         case SND_SOC_BIAS_ON:
 481                 break;
 482         case SND_SOC_BIAS_PREPARE:
 483                 break;
 484         case SND_SOC_BIAS_STANDBY:
 485                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
 486                         ret = adau1977_power_enable(adau1977);
 487                 break;
 488         case SND_SOC_BIAS_OFF:
 489                 ret = adau1977_power_disable(adau1977);
 490                 break;
 491         }
 492
 493         return ret;
 494 }
 495
 496 static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 497         unsigned int rx_mask, int slots, int width)
 498 {
 499         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
 500         unsigned int ctrl0, ctrl1, drv;
 501         unsigned int slot[4];
 502         unsigned int i;
 503         int ret;
 504
 505         if (slots == 0) {
 506                 /* 0 = No fixed slot width */
 507                 adau1977->slot_width = 0;
 508                 adau1977->max_master_fs = 192000;
 509                 return regmap_update_bits(adau1977->regmap,
 510                         ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
 511                         ADAU1977_SAI_CTRL0_SAI_I2S);
 512         }
 513
 514         if (rx_mask == 0 || tx_mask != 0)
 515                 return -EINVAL;
 516
 517         drv = 0;
 518         for (i = 0; i < 4; i++) {
 519                 slot[i] = __ffs(rx_mask);
 520                 drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
 521                 rx_mask &= ~(1 << slot[i]);
 522                 if (slot[i] >= slots)
 523                         return -EINVAL;
 524                 if (rx_mask == 0)
 525                         break;
 526         }
 527
 528         if (rx_mask != 0)
 529                 return -EINVAL;
 530
 531         switch (width) {
 532         case 16:
 533                 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
 534                 break;
 535         case 24:
 536                 /* We can only generate 16 bit or 32 bit wide slots */
 537                 if (adau1977->master)
 538                         return -EINVAL;
 539                 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
 540                 break;
 541         case 32:
 542                 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
 543                 break;
 544         default:
 545                 return -EINVAL;
 546         }
 547
 548         switch (slots) {
 549         case 2:
 550                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
 551                 break;
 552         case 4:
 553                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
 554                 break;
 555         case 8:
 556                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
 557                 break;
 558         case 16:
 559                 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
 560                 break;
 561         default:
 562                 return -EINVAL;
 563         }
 564
 565         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
 566                 ADAU1977_SAI_OVERTEMP_DRV_C(0) |
 567                 ADAU1977_SAI_OVERTEMP_DRV_C(1) |
 568                 ADAU1977_SAI_OVERTEMP_DRV_C(2) |
 569                 ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
 570         if (ret)
 571                 return ret;
 572
 573         ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
 574                 (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
 575                 (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
 576         if (ret)
 577                 return ret;
 578
 579         ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
 580                 (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
 581                 (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
 582         if (ret)
 583                 return ret;
 584
 585         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
 586                 ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
 587         if (ret)
 588                 return ret;
 589
 590         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
 591                 ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
 592         if (ret)
 593                 return ret;
 594
 595         adau1977->slot_width = width;
 596
 597         /* In master mode the maximum bitclock is 24.576 MHz */
 598         adau1977->max_master_fs = min(192000, 24576000 / width / slots);
 599
 600         return 0;
 601 }
 602
 603 static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
 604 {
 605         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
 606         unsigned int val;
 607
 608         if (mute)
 609                 val = ADAU1977_MISC_CONTROL_MMUTE;
 610         else
 611                 val = 0;
 612
 613         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
 614                         ADAU1977_MISC_CONTROL_MMUTE, val);
 615 }
 616
 617 static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 618 {
 619         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
 620         unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
 621         bool invert_lrclk;
 622         int ret;
 623
 624         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 625         case SND_SOC_DAIFMT_CBS_CFS:
 626                 adau1977->master = false;
 627                 break;
 628         case SND_SOC_DAIFMT_CBM_CFM:
 629                 ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
 630                 adau1977->master = true;
 631                 break;
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 637         case SND_SOC_DAIFMT_NB_NF:
 638                 invert_lrclk = false;
 639                 break;
 640         case SND_SOC_DAIFMT_IB_NF:
 641                 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
 642                 invert_lrclk = false;
 643                 break;
 644         case SND_SOC_DAIFMT_NB_IF:
 645                 invert_lrclk = true;
 646                 break;
 647         case SND_SOC_DAIFMT_IB_IF:
 648                 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
 649                 invert_lrclk = true;
 650                 break;
 651         default:
 652                 return -EINVAL;
 653         }
 654
 655         adau1977->right_j = false;
 656         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 657         case SND_SOC_DAIFMT_I2S:
 658                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
 659                 break;
 660         case SND_SOC_DAIFMT_LEFT_J:
 661                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
 662                 invert_lrclk = !invert_lrclk;
 663                 break;
 664         case SND_SOC_DAIFMT_RIGHT_J:
 665                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
 666                 adau1977->right_j = true;
 667                 invert_lrclk = !invert_lrclk;
 668                 break;
 669         case SND_SOC_DAIFMT_DSP_A:
 670                 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
 671                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
 672                 invert_lrclk = false;
 673                 break;
 674         case SND_SOC_DAIFMT_DSP_B:
 675                 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
 676                 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
 677                 invert_lrclk = false;
 678                 break;
 679         default:
 680                 return -EINVAL;
 681         }
 682
 683         if (invert_lrclk)
 684                 block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
 685
 686         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
 687                 ADAU1977_BLOCK_POWER_SAI_LR_POL |
 688                 ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
 689         if (ret)
 690                 return ret;
 691
 692         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
 693                 ADAU1977_SAI_CTRL0_FMT_MASK,
 694                 ctrl0);
 695         if (ret)
 696                 return ret;
 697
 698         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
 699                 ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
 700                 ctrl1);
 701 }
 702
 703 static int adau1977_startup(struct snd_pcm_substream *substream,
 704         struct snd_soc_dai *dai)
 705 {
 706         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
 707         u64 formats = 0;
 708
 709         if (adau1977->slot_width == 16)
 710                 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
 711         else if (adau1977->right_j || adau1977->slot_width == 24)
 712                 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
 713                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
 714
 715         snd_pcm_hw_constraint_list(substream->runtime, 0,
 716                 SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
 717
 718         if (adau1977->master)
 719                 snd_pcm_hw_constraint_minmax(substream->runtime,
 720                         SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
 721
 722         if (formats != 0)
 723                 snd_pcm_hw_constraint_mask64(substream->runtime,
 724                         SNDRV_PCM_HW_PARAM_FORMAT, formats);
 725
 726         return 0;
 727 }
 728
 729 static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
 730 {
 731         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
 732         unsigned int val;
 733
 734         if (tristate)
 735                 val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
 736         else
 737                 val = 0;
 738
 739         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
 740                 ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
 741 }
 742
 743 static const struct snd_soc_dai_ops adau1977_dai_ops = {
 744         .startup        = adau1977_startup,
 745         .hw_params      = adau1977_hw_params,
 746         .mute_stream    = adau1977_mute,
 747         .set_fmt        = adau1977_set_dai_fmt,
 748         .set_tdm_slot   = adau1977_set_tdm_slot,
 749         .set_tristate   = adau1977_set_tristate,
 750 };
 751
 752 static struct snd_soc_dai_driver adau1977_dai = {
 753         .name = "adau1977-hifi",
 754         .capture = {
 755                 .stream_name = "Capture",
 756                 .channels_min = 1,
 757                 .channels_max = 4,
 758                 .rates = SNDRV_PCM_RATE_KNOT,
 759                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 760                     SNDRV_PCM_FMTBIT_S32_LE,
 761                 .sig_bits = 24,
 762         },
 763         .ops = &adau1977_dai_ops,
 764 };
 765
 766 static const unsigned int adau1977_rates[] = {
 767         8000, 16000, 32000, 64000, 128000,
 768         11025, 22050, 44100, 88200, 172400,
 769         12000, 24000, 48000, 96000, 192000,
 770 };
 771
 772 #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
 773 #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
 774 #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
 775 /* All rates >= 32000 */
 776 #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
 777
 778 static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
 779 {
 780         unsigned int mcs;
 781
 782         if (mclk % (base_freq * 128) != 0)
 783                 return false;
 784
 785         mcs = mclk / (128 * base_freq);
 786         if (mcs < 1 || mcs > 6 || mcs == 5)
 787                 return false;
 788
 789         return true;
 790 }
 791
 792 static int adau1977_set_sysclk(struct snd_soc_component *component,
 793         int clk_id, int source, unsigned int freq, int dir)
 794 {
 795         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
 796         unsigned int mask = 0;
 797         unsigned int clk_src;
 798         unsigned int ret;
 799
 800         if (dir != SND_SOC_CLOCK_IN)
 801                 return -EINVAL;
 802
 803         if (clk_id != ADAU1977_SYSCLK)
 804                 return -EINVAL;
 805
 806         switch (source) {
 807         case ADAU1977_SYSCLK_SRC_MCLK:
 808                 clk_src = 0;
 809                 break;
 810         case ADAU1977_SYSCLK_SRC_LRCLK:
 811                 clk_src = ADAU1977_PLL_CLK_S;
 812                 break;
 813         default:
 814                 return -EINVAL;
 815         }
 816
 817         if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
 818                 if (freq < 4000000 || freq > 36864000)
 819                         return -EINVAL;
 820
 821                 if (adau1977_check_sysclk(freq, 32000))
 822                         mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
 823                 if (adau1977_check_sysclk(freq, 44100))
 824                         mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
 825                 if (adau1977_check_sysclk(freq, 48000))
 826                         mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
 827
 828                 if (mask == 0)
 829                         return -EINVAL;
 830         } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
 831                 mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
 832         }
 833
 834         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
 835                 ADAU1977_PLL_CLK_S, clk_src);
 836         if (ret)
 837                 return ret;
 838
 839         adau1977->constraints.mask = mask;
 840         adau1977->sysclk_src = source;
 841         adau1977->sysclk = freq;
 842
 843         return 0;
 844 }
 845
 846 static int adau1977_component_probe(struct snd_soc_component *component)
 847 {
 848         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 849         struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
 850         int ret;
 851
 852         switch (adau1977->type) {
 853         case ADAU1977:
 854                 ret = snd_soc_dapm_new_controls(dapm,
 855                         adau1977_micbias_dapm_widgets,
 856                         ARRAY_SIZE(adau1977_micbias_dapm_widgets));
 857                 if (ret < 0)
 858                         return ret;
 859                 break;
 860         default:
 861                 break;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static const struct snd_soc_component_driver adau1977_component_driver = {
 868         .probe                  = adau1977_component_probe,
 869         .set_bias_level         = adau1977_set_bias_level,
 870         .set_sysclk             = adau1977_set_sysclk,
 871         .controls               = adau1977_snd_controls,
 872         .num_controls           = ARRAY_SIZE(adau1977_snd_controls),
 873         .dapm_widgets           = adau1977_dapm_widgets,
 874         .num_dapm_widgets       = ARRAY_SIZE(adau1977_dapm_widgets),
 875         .dapm_routes            = adau1977_dapm_routes,
 876         .num_dapm_routes        = ARRAY_SIZE(adau1977_dapm_routes),
 877         .use_pmdown_time        = 1,
 878         .endianness             = 1,
 879         .non_legacy_dai_naming  = 1,
 880 };
 881
 882 static int adau1977_setup_micbias(struct adau1977 *adau1977)
 883 {
 884         struct adau1977_platform_data *pdata = adau1977->dev->platform_data;
 885         unsigned int micbias;
 886
 887         if (pdata)
 888                 micbias = pdata->micbias;
 889         else if (device_property_read_u32(adau1977->dev, "adi,micbias",
 890                                           &micbias))
 891                 micbias = ADAU1977_MICBIAS_8V5;
 892
 893         if (micbias > ADAU1977_MICBIAS_9V0) {
 894                 dev_err(adau1977->dev, "Invalid value for 'adi,micbias'\n");
 895                 return -EINVAL;
 896         }
 897
 898         return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
 899                 ADAU1977_MICBIAS_MB_VOLTS_MASK,
 900                 micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
 901 }
 902
 903 int adau1977_probe(struct device *dev, struct regmap *regmap,
 904         enum adau1977_type type, void (*switch_mode)(struct device *dev))
 905 {
 906         unsigned int power_off_mask;
 907         struct adau1977 *adau1977;
 908         int ret;
 909
 910         if (IS_ERR(regmap))
 911                 return PTR_ERR(regmap);
 912
 913         adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
 914         if (adau1977 == NULL)
 915                 return -ENOMEM;
 916
 917         adau1977->dev = dev;
 918         adau1977->type = type;
 919         adau1977->regmap = regmap;
 920         adau1977->switch_mode = switch_mode;
 921         adau1977->max_master_fs = 192000;
 922
 923         adau1977->constraints.list = adau1977_rates;
 924         adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
 925
 926         adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
 927         if (IS_ERR(adau1977->avdd_reg))
 928                 return PTR_ERR(adau1977->avdd_reg);
 929
 930         adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
 931         if (IS_ERR(adau1977->dvdd_reg)) {
 932                 if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
 933                         return PTR_ERR(adau1977->dvdd_reg);
 934                 adau1977->dvdd_reg = NULL;
 935         }
 936
 937         adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
 938                                                        GPIOD_OUT_LOW);
 939         if (IS_ERR(adau1977->reset_gpio))
 940                 return PTR_ERR(adau1977->reset_gpio);
 941
 942         dev_set_drvdata(dev, adau1977);
 943
 944         if (adau1977->reset_gpio)
 945                 ndelay(100);
 946
 947         ret = adau1977_power_enable(adau1977);
 948         if (ret)
 949                 return ret;
 950
 951         if (type == ADAU1977) {
 952                 ret = adau1977_setup_micbias(adau1977);
 953                 if (ret)
 954                         goto err_poweroff;
 955         }
 956
 957         if (adau1977->dvdd_reg)
 958                 power_off_mask = ~0;
 959         else
 960                 power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
 961
 962         ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
 963                                 power_off_mask, 0x00);
 964         if (ret)
 965                 goto err_poweroff;
 966
 967         ret = adau1977_power_disable(adau1977);
 968         if (ret)
 969                 return ret;
 970
 971         return devm_snd_soc_register_component(dev, &adau1977_component_driver,
 972                         &adau1977_dai, 1);
 973
 974 err_poweroff:
 975         adau1977_power_disable(adau1977);
 976         return ret;
 977
 978 }
 979 EXPORT_SYMBOL_GPL(adau1977_probe);
 980
 981 static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
 982 {
 983         switch (reg) {
 984         case ADAU1977_REG_STATUS(0):
 985         case ADAU1977_REG_STATUS(1):
 986         case ADAU1977_REG_STATUS(2):
 987         case ADAU1977_REG_STATUS(3):
 988         case ADAU1977_REG_ADC_CLIP:
 989                 return true;
 990         }
 991
 992         return false;
 993 }
 994
 995 const struct regmap_config adau1977_regmap_config = {
 996         .max_register = ADAU1977_REG_DC_HPF_CAL,
 997         .volatile_reg = adau1977_register_volatile,
 998
 999         .cache_type = REGCACHE_RBTREE,
1000         .reg_defaults = adau1977_reg_defaults,
1001         .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
1002 };
1003 EXPORT_SYMBOL_GPL(adau1977_regmap_config);
1004
1005 MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1006 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1007 MODULE_LICENSE("GPL");