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Merge branch 'for-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / cs42l42.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/version.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/gpio.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/acpi.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/soc-dapm.h>
34 #include <sound/initval.h>
35 #include <sound/tlv.h>
36 #include <dt-bindings/sound/cs42l42.h>
37
38 #include "cs42l42.h"
39 #include "cirrus_legacy.h"
40
41 static const struct reg_default cs42l42_reg_defaults[] = {
42 { CS42L42_FRZ_CTL, 0x00 },
43 { CS42L42_SRC_CTL, 0x10 },
44 { CS42L42_MCLK_STATUS, 0x02 },
45 { CS42L42_MCLK_CTL, 0x02 },
46 { CS42L42_SFTRAMP_RATE, 0xA4 },
47 { CS42L42_I2C_DEBOUNCE, 0x88 },
48 { CS42L42_I2C_STRETCH, 0x03 },
49 { CS42L42_I2C_TIMEOUT, 0xB7 },
50 { CS42L42_PWR_CTL1, 0xFF },
51 { CS42L42_PWR_CTL2, 0x84 },
52 { CS42L42_PWR_CTL3, 0x20 },
53 { CS42L42_RSENSE_CTL1, 0x40 },
54 { CS42L42_RSENSE_CTL2, 0x00 },
55 { CS42L42_OSC_SWITCH, 0x00 },
56 { CS42L42_OSC_SWITCH_STATUS, 0x05 },
57 { CS42L42_RSENSE_CTL3, 0x1B },
58 { CS42L42_TSENSE_CTL, 0x1B },
59 { CS42L42_TSRS_INT_DISABLE, 0x00 },
60 { CS42L42_TRSENSE_STATUS, 0x00 },
61 { CS42L42_HSDET_CTL1, 0x77 },
62 { CS42L42_HSDET_CTL2, 0x00 },
63 { CS42L42_HS_SWITCH_CTL, 0xF3 },
64 { CS42L42_HS_DET_STATUS, 0x00 },
65 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
66 { CS42L42_MCLK_SRC_SEL, 0x00 },
67 { CS42L42_SPDIF_CLK_CFG, 0x00 },
68 { CS42L42_FSYNC_PW_LOWER, 0x00 },
69 { CS42L42_FSYNC_PW_UPPER, 0x00 },
70 { CS42L42_FSYNC_P_LOWER, 0xF9 },
71 { CS42L42_FSYNC_P_UPPER, 0x00 },
72 { CS42L42_ASP_CLK_CFG, 0x00 },
73 { CS42L42_ASP_FRM_CFG, 0x10 },
74 { CS42L42_FS_RATE_EN, 0x00 },
75 { CS42L42_IN_ASRC_CLK, 0x00 },
76 { CS42L42_OUT_ASRC_CLK, 0x00 },
77 { CS42L42_PLL_DIV_CFG1, 0x00 },
78 { CS42L42_ADC_OVFL_STATUS, 0x00 },
79 { CS42L42_MIXER_STATUS, 0x00 },
80 { CS42L42_SRC_STATUS, 0x00 },
81 { CS42L42_ASP_RX_STATUS, 0x00 },
82 { CS42L42_ASP_TX_STATUS, 0x00 },
83 { CS42L42_CODEC_STATUS, 0x00 },
84 { CS42L42_DET_INT_STATUS1, 0x00 },
85 { CS42L42_DET_INT_STATUS2, 0x00 },
86 { CS42L42_SRCPL_INT_STATUS, 0x00 },
87 { CS42L42_VPMON_STATUS, 0x00 },
88 { CS42L42_PLL_LOCK_STATUS, 0x00 },
89 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
90 { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
91 { CS42L42_MIXER_INT_MASK, 0x0F },
92 { CS42L42_SRC_INT_MASK, 0x0F },
93 { CS42L42_ASP_RX_INT_MASK, 0x1F },
94 { CS42L42_ASP_TX_INT_MASK, 0x0F },
95 { CS42L42_CODEC_INT_MASK, 0x03 },
96 { CS42L42_SRCPL_INT_MASK, 0xFF },
97 { CS42L42_VPMON_INT_MASK, 0x01 },
98 { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
99 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
100 { CS42L42_PLL_CTL1, 0x00 },
101 { CS42L42_PLL_DIV_FRAC0, 0x00 },
102 { CS42L42_PLL_DIV_FRAC1, 0x00 },
103 { CS42L42_PLL_DIV_FRAC2, 0x00 },
104 { CS42L42_PLL_DIV_INT, 0x40 },
105 { CS42L42_PLL_CTL3, 0x10 },
106 { CS42L42_PLL_CAL_RATIO, 0x80 },
107 { CS42L42_PLL_CTL4, 0x03 },
108 { CS42L42_LOAD_DET_RCSTAT, 0x00 },
109 { CS42L42_LOAD_DET_DONE, 0x00 },
110 { CS42L42_LOAD_DET_EN, 0x00 },
111 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
112 { CS42L42_WAKE_CTL, 0xC0 },
113 { CS42L42_ADC_DISABLE_MUTE, 0x00 },
114 { CS42L42_TIPSENSE_CTL, 0x02 },
115 { CS42L42_MISC_DET_CTL, 0x03 },
116 { CS42L42_MIC_DET_CTL1, 0x1F },
117 { CS42L42_MIC_DET_CTL2, 0x2F },
118 { CS42L42_DET_STATUS1, 0x00 },
119 { CS42L42_DET_STATUS2, 0x00 },
120 { CS42L42_DET_INT1_MASK, 0xE0 },
121 { CS42L42_DET_INT2_MASK, 0xFF },
122 { CS42L42_HS_BIAS_CTL, 0xC2 },
123 { CS42L42_ADC_CTL, 0x00 },
124 { CS42L42_ADC_VOLUME, 0x00 },
125 { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
126 { CS42L42_DAC_CTL1, 0x00 },
127 { CS42L42_DAC_CTL2, 0x02 },
128 { CS42L42_HP_CTL, 0x0D },
129 { CS42L42_CLASSH_CTL, 0x07 },
130 { CS42L42_MIXER_CHA_VOL, 0x3F },
131 { CS42L42_MIXER_ADC_VOL, 0x3F },
132 { CS42L42_MIXER_CHB_VOL, 0x3F },
133 { CS42L42_EQ_COEF_IN0, 0x22 },
134 { CS42L42_EQ_COEF_IN1, 0x00 },
135 { CS42L42_EQ_COEF_IN2, 0x00 },
136 { CS42L42_EQ_COEF_IN3, 0x00 },
137 { CS42L42_EQ_COEF_RW, 0x00 },
138 { CS42L42_EQ_COEF_OUT0, 0x00 },
139 { CS42L42_EQ_COEF_OUT1, 0x00 },
140 { CS42L42_EQ_COEF_OUT2, 0x00 },
141 { CS42L42_EQ_COEF_OUT3, 0x00 },
142 { CS42L42_EQ_INIT_STAT, 0x00 },
143 { CS42L42_EQ_START_FILT, 0x00 },
144 { CS42L42_EQ_MUTE_CTL, 0x00 },
145 { CS42L42_SP_RX_CH_SEL, 0x04 },
146 { CS42L42_SP_RX_ISOC_CTL, 0x04 },
147 { CS42L42_SP_RX_FS, 0x8C },
148 { CS42l42_SPDIF_CH_SEL, 0x0E },
149 { CS42L42_SP_TX_ISOC_CTL, 0x04 },
150 { CS42L42_SP_TX_FS, 0xCC },
151 { CS42L42_SPDIF_SW_CTL1, 0x3F },
152 { CS42L42_SRC_SDIN_FS, 0x40 },
153 { CS42L42_SRC_SDOUT_FS, 0x40 },
154 { CS42L42_SPDIF_CTL1, 0x01 },
155 { CS42L42_SPDIF_CTL2, 0x00 },
156 { CS42L42_SPDIF_CTL3, 0x00 },
157 { CS42L42_SPDIF_CTL4, 0x42 },
158 { CS42L42_ASP_TX_SZ_EN, 0x00 },
159 { CS42L42_ASP_TX_CH_EN, 0x00 },
160 { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
161 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
162 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
163 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
164 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
165 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
166 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
167 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
168 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
169 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
170 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
171 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
172 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
173 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
174 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
175 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
176 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
177 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
178 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
179 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
180 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
181 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
182 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
183 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
184 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
185 { CS42L42_SUB_REVID, 0x03 },
186 };
187
188 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
189 {
190 switch (reg) {
191 case CS42L42_PAGE_REGISTER:
192 case CS42L42_DEVID_AB:
193 case CS42L42_DEVID_CD:
194 case CS42L42_DEVID_E:
195 case CS42L42_FABID:
196 case CS42L42_REVID:
197 case CS42L42_FRZ_CTL:
198 case CS42L42_SRC_CTL:
199 case CS42L42_MCLK_STATUS:
200 case CS42L42_MCLK_CTL:
201 case CS42L42_SFTRAMP_RATE:
202 case CS42L42_I2C_DEBOUNCE:
203 case CS42L42_I2C_STRETCH:
204 case CS42L42_I2C_TIMEOUT:
205 case CS42L42_PWR_CTL1:
206 case CS42L42_PWR_CTL2:
207 case CS42L42_PWR_CTL3:
208 case CS42L42_RSENSE_CTL1:
209 case CS42L42_RSENSE_CTL2:
210 case CS42L42_OSC_SWITCH:
211 case CS42L42_OSC_SWITCH_STATUS:
212 case CS42L42_RSENSE_CTL3:
213 case CS42L42_TSENSE_CTL:
214 case CS42L42_TSRS_INT_DISABLE:
215 case CS42L42_TRSENSE_STATUS:
216 case CS42L42_HSDET_CTL1:
217 case CS42L42_HSDET_CTL2:
218 case CS42L42_HS_SWITCH_CTL:
219 case CS42L42_HS_DET_STATUS:
220 case CS42L42_HS_CLAMP_DISABLE:
221 case CS42L42_MCLK_SRC_SEL:
222 case CS42L42_SPDIF_CLK_CFG:
223 case CS42L42_FSYNC_PW_LOWER:
224 case CS42L42_FSYNC_PW_UPPER:
225 case CS42L42_FSYNC_P_LOWER:
226 case CS42L42_FSYNC_P_UPPER:
227 case CS42L42_ASP_CLK_CFG:
228 case CS42L42_ASP_FRM_CFG:
229 case CS42L42_FS_RATE_EN:
230 case CS42L42_IN_ASRC_CLK:
231 case CS42L42_OUT_ASRC_CLK:
232 case CS42L42_PLL_DIV_CFG1:
233 case CS42L42_ADC_OVFL_STATUS:
234 case CS42L42_MIXER_STATUS:
235 case CS42L42_SRC_STATUS:
236 case CS42L42_ASP_RX_STATUS:
237 case CS42L42_ASP_TX_STATUS:
238 case CS42L42_CODEC_STATUS:
239 case CS42L42_DET_INT_STATUS1:
240 case CS42L42_DET_INT_STATUS2:
241 case CS42L42_SRCPL_INT_STATUS:
242 case CS42L42_VPMON_STATUS:
243 case CS42L42_PLL_LOCK_STATUS:
244 case CS42L42_TSRS_PLUG_STATUS:
245 case CS42L42_ADC_OVFL_INT_MASK:
246 case CS42L42_MIXER_INT_MASK:
247 case CS42L42_SRC_INT_MASK:
248 case CS42L42_ASP_RX_INT_MASK:
249 case CS42L42_ASP_TX_INT_MASK:
250 case CS42L42_CODEC_INT_MASK:
251 case CS42L42_SRCPL_INT_MASK:
252 case CS42L42_VPMON_INT_MASK:
253 case CS42L42_PLL_LOCK_INT_MASK:
254 case CS42L42_TSRS_PLUG_INT_MASK:
255 case CS42L42_PLL_CTL1:
256 case CS42L42_PLL_DIV_FRAC0:
257 case CS42L42_PLL_DIV_FRAC1:
258 case CS42L42_PLL_DIV_FRAC2:
259 case CS42L42_PLL_DIV_INT:
260 case CS42L42_PLL_CTL3:
261 case CS42L42_PLL_CAL_RATIO:
262 case CS42L42_PLL_CTL4:
263 case CS42L42_LOAD_DET_RCSTAT:
264 case CS42L42_LOAD_DET_DONE:
265 case CS42L42_LOAD_DET_EN:
266 case CS42L42_HSBIAS_SC_AUTOCTL:
267 case CS42L42_WAKE_CTL:
268 case CS42L42_ADC_DISABLE_MUTE:
269 case CS42L42_TIPSENSE_CTL:
270 case CS42L42_MISC_DET_CTL:
271 case CS42L42_MIC_DET_CTL1:
272 case CS42L42_MIC_DET_CTL2:
273 case CS42L42_DET_STATUS1:
274 case CS42L42_DET_STATUS2:
275 case CS42L42_DET_INT1_MASK:
276 case CS42L42_DET_INT2_MASK:
277 case CS42L42_HS_BIAS_CTL:
278 case CS42L42_ADC_CTL:
279 case CS42L42_ADC_VOLUME:
280 case CS42L42_ADC_WNF_HPF_CTL:
281 case CS42L42_DAC_CTL1:
282 case CS42L42_DAC_CTL2:
283 case CS42L42_HP_CTL:
284 case CS42L42_CLASSH_CTL:
285 case CS42L42_MIXER_CHA_VOL:
286 case CS42L42_MIXER_ADC_VOL:
287 case CS42L42_MIXER_CHB_VOL:
288 case CS42L42_EQ_COEF_IN0:
289 case CS42L42_EQ_COEF_IN1:
290 case CS42L42_EQ_COEF_IN2:
291 case CS42L42_EQ_COEF_IN3:
292 case CS42L42_EQ_COEF_RW:
293 case CS42L42_EQ_COEF_OUT0:
294 case CS42L42_EQ_COEF_OUT1:
295 case CS42L42_EQ_COEF_OUT2:
296 case CS42L42_EQ_COEF_OUT3:
297 case CS42L42_EQ_INIT_STAT:
298 case CS42L42_EQ_START_FILT:
299 case CS42L42_EQ_MUTE_CTL:
300 case CS42L42_SP_RX_CH_SEL:
301 case CS42L42_SP_RX_ISOC_CTL:
302 case CS42L42_SP_RX_FS:
303 case CS42l42_SPDIF_CH_SEL:
304 case CS42L42_SP_TX_ISOC_CTL:
305 case CS42L42_SP_TX_FS:
306 case CS42L42_SPDIF_SW_CTL1:
307 case CS42L42_SRC_SDIN_FS:
308 case CS42L42_SRC_SDOUT_FS:
309 case CS42L42_SPDIF_CTL1:
310 case CS42L42_SPDIF_CTL2:
311 case CS42L42_SPDIF_CTL3:
312 case CS42L42_SPDIF_CTL4:
313 case CS42L42_ASP_TX_SZ_EN:
314 case CS42L42_ASP_TX_CH_EN:
315 case CS42L42_ASP_TX_CH_AP_RES:
316 case CS42L42_ASP_TX_CH1_BIT_MSB:
317 case CS42L42_ASP_TX_CH1_BIT_LSB:
318 case CS42L42_ASP_TX_HIZ_DLY_CFG:
319 case CS42L42_ASP_TX_CH2_BIT_MSB:
320 case CS42L42_ASP_TX_CH2_BIT_LSB:
321 case CS42L42_ASP_RX_DAI0_EN:
322 case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
323 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
324 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
325 case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
326 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
327 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
328 case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
329 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
330 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
331 case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
332 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
333 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
334 case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
335 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
336 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
337 case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
338 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
339 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
340 case CS42L42_SUB_REVID:
341 return true;
342 default:
343 return false;
344 }
345 }
346
347 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
348 {
349 switch (reg) {
350 case CS42L42_DEVID_AB:
351 case CS42L42_DEVID_CD:
352 case CS42L42_DEVID_E:
353 case CS42L42_MCLK_STATUS:
354 case CS42L42_TRSENSE_STATUS:
355 case CS42L42_HS_DET_STATUS:
356 case CS42L42_ADC_OVFL_STATUS:
357 case CS42L42_MIXER_STATUS:
358 case CS42L42_SRC_STATUS:
359 case CS42L42_ASP_RX_STATUS:
360 case CS42L42_ASP_TX_STATUS:
361 case CS42L42_CODEC_STATUS:
362 case CS42L42_DET_INT_STATUS1:
363 case CS42L42_DET_INT_STATUS2:
364 case CS42L42_SRCPL_INT_STATUS:
365 case CS42L42_VPMON_STATUS:
366 case CS42L42_PLL_LOCK_STATUS:
367 case CS42L42_TSRS_PLUG_STATUS:
368 case CS42L42_LOAD_DET_RCSTAT:
369 case CS42L42_LOAD_DET_DONE:
370 case CS42L42_DET_STATUS1:
371 case CS42L42_DET_STATUS2:
372 return true;
373 default:
374 return false;
375 }
376 }
377
378 static const struct regmap_range_cfg cs42l42_page_range = {
379 .name = "Pages",
380 .range_min = 0,
381 .range_max = CS42L42_MAX_REGISTER,
382 .selector_reg = CS42L42_PAGE_REGISTER,
383 .selector_mask = 0xff,
384 .selector_shift = 0,
385 .window_start = 0,
386 .window_len = 256,
387 };
388
389 static const struct regmap_config cs42l42_regmap = {
390 .reg_bits = 8,
391 .val_bits = 8,
392
393 .readable_reg = cs42l42_readable_register,
394 .volatile_reg = cs42l42_volatile_register,
395
396 .ranges = &cs42l42_page_range,
397 .num_ranges = 1,
398
399 .max_register = CS42L42_MAX_REGISTER,
400 .reg_defaults = cs42l42_reg_defaults,
401 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
402 .cache_type = REGCACHE_RBTREE,
403
404 .use_single_read = true,
405 .use_single_write = true,
406 };
407
408 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false);
409 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
410
411 static const char * const cs42l42_hpf_freq_text[] = {
412 "1.86Hz", "120Hz", "235Hz", "466Hz"
413 };
414
415 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
416 CS42L42_ADC_HPF_CF_SHIFT,
417 cs42l42_hpf_freq_text);
418
419 static const char * const cs42l42_wnf3_freq_text[] = {
420 "160Hz", "180Hz", "200Hz", "220Hz",
421 "240Hz", "260Hz", "280Hz", "300Hz"
422 };
423
424 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
425 CS42L42_ADC_WNF_CF_SHIFT,
426 cs42l42_wnf3_freq_text);
427
428 static const char * const cs42l42_wnf05_freq_text[] = {
429 "280Hz", "315Hz", "350Hz", "385Hz",
430 "420Hz", "455Hz", "490Hz", "525Hz"
431 };
432
433 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
434 CS42L42_ADC_WNF_CF_SHIFT,
435 cs42l42_wnf05_freq_text);
436
437 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
438 /* ADC Volume and Filter Controls */
439 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
440 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false),
441 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
442 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
443 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
444 CS42L42_ADC_INV_SHIFT, true, false),
445 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
446 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
447 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME,
448 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv),
449 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
450 CS42L42_ADC_WNF_EN_SHIFT, true, false),
451 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
452 CS42L42_ADC_HPF_EN_SHIFT, true, false),
453 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
454 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
455 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum),
456
457 /* DAC Volume and Filter Controls */
458 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
459 CS42L42_DACA_INV_SHIFT, true, false),
460 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
461 CS42L42_DACB_INV_SHIFT, true, false),
462 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
463 CS42L42_DAC_HPF_EN_SHIFT, true, false),
464 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
465 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
466 0x3f, 1, mixer_tlv)
467 };
468
469 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
470 /* Playback Path */
471 SND_SOC_DAPM_OUTPUT("HP"),
472 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1),
473 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
474 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH1_SHIFT, 0),
475 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH2_SHIFT, 0),
476
477 /* Playback Requirements */
478 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
479
480 /* Capture Path */
481 SND_SOC_DAPM_INPUT("HS"),
482 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1),
483 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
484 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
485
486 /* Capture Requirements */
487 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
488 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
489
490 /* Playback/Capture Requirements */
491 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
492 };
493
494 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
495 /* Playback Path */
496 {"HP", NULL, "DAC"},
497 {"DAC", NULL, "MIXER"},
498 {"MIXER", NULL, "SDIN1"},
499 {"MIXER", NULL, "SDIN2"},
500 {"SDIN1", NULL, "Playback"},
501 {"SDIN2", NULL, "Playback"},
502
503 /* Playback Requirements */
504 {"SDIN1", NULL, "ASP DAI0"},
505 {"SDIN2", NULL, "ASP DAI0"},
506 {"SDIN1", NULL, "SCLK"},
507 {"SDIN2", NULL, "SCLK"},
508
509 /* Capture Path */
510 {"ADC", NULL, "HS"},
511 { "SDOUT1", NULL, "ADC" },
512 { "SDOUT2", NULL, "ADC" },
513 { "Capture", NULL, "SDOUT1" },
514 { "Capture", NULL, "SDOUT2" },
515
516 /* Capture Requirements */
517 { "SDOUT1", NULL, "ASP DAO0" },
518 { "SDOUT2", NULL, "ASP DAO0" },
519 { "SDOUT1", NULL, "SCLK" },
520 { "SDOUT2", NULL, "SCLK" },
521 { "SDOUT1", NULL, "ASP TX EN" },
522 { "SDOUT2", NULL, "ASP TX EN" },
523 };
524
525 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
526 {
527 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
528
529 cs42l42->jack = jk;
530
531 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
532 CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK |
533 CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK,
534 (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) |
535 (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT));
536
537 return 0;
538 }
539
540 static int cs42l42_component_probe(struct snd_soc_component *component)
541 {
542 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
543
544 cs42l42->component = component;
545
546 return 0;
547 }
548
549 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
550 .probe = cs42l42_component_probe,
551 .set_jack = cs42l42_set_jack,
552 .dapm_widgets = cs42l42_dapm_widgets,
553 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
554 .dapm_routes = cs42l42_audio_map,
555 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
556 .controls = cs42l42_snd_controls,
557 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
558 .idle_bias_on = 1,
559 .endianness = 1,
560 .non_legacy_dai_naming = 1,
561 };
562
563 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
564 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
565 {
566 .reg = CS42L42_OSC_SWITCH,
567 .def = CS42L42_SCLK_PRESENT_MASK,
568 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
569 },
570 };
571
572 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
573 static const struct reg_sequence cs42l42_to_osc_seq[] = {
574 {
575 .reg = CS42L42_OSC_SWITCH,
576 .def = 0,
577 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
578 },
579 };
580
581 struct cs42l42_pll_params {
582 u32 sclk;
583 u8 mclk_div;
584 u8 mclk_src_sel;
585 u8 sclk_prediv;
586 u8 pll_div_int;
587 u32 pll_div_frac;
588 u8 pll_mode;
589 u8 pll_divout;
590 u32 mclk_int;
591 u8 pll_cal_ratio;
592 };
593
594 /*
595 * Common PLL Settings for given SCLK
596 * Table 4-5 from the Datasheet
597 */
598 static const struct cs42l42_pll_params pll_ratio_table[] = {
599 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
600 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
601 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
602 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
603 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
604 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
605 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
606 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
607 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
608 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
609 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
610 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
611 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
612 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
613 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
614 };
615
616 static int cs42l42_pll_config(struct snd_soc_component *component)
617 {
618 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
619 int i;
620 u32 clk;
621 u32 fsync;
622
623 if (!cs42l42->sclk)
624 clk = cs42l42->bclk;
625 else
626 clk = cs42l42->sclk;
627
628 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
629 if (pll_ratio_table[i].sclk == clk) {
630 /* Configure the internal sample rate */
631 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
632 CS42L42_INTERNAL_FS_MASK,
633 ((pll_ratio_table[i].mclk_int !=
634 12000000) &&
635 (pll_ratio_table[i].mclk_int !=
636 24000000)) <<
637 CS42L42_INTERNAL_FS_SHIFT);
638 /* Set the MCLK src (PLL or SCLK) and the divide
639 * ratio
640 */
641 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
642 CS42L42_MCLK_SRC_SEL_MASK |
643 CS42L42_MCLKDIV_MASK,
644 (pll_ratio_table[i].mclk_src_sel
645 << CS42L42_MCLK_SRC_SEL_SHIFT) |
646 (pll_ratio_table[i].mclk_div <<
647 CS42L42_MCLKDIV_SHIFT));
648 /* Set up the LRCLK */
649 fsync = clk / cs42l42->srate;
650 if (((fsync * cs42l42->srate) != clk)
651 || ((fsync % 2) != 0)) {
652 dev_err(component->dev,
653 "Unsupported sclk %d/sample rate %d\n",
654 clk,
655 cs42l42->srate);
656 return -EINVAL;
657 }
658 /* Set the LRCLK period */
659 snd_soc_component_update_bits(component,
660 CS42L42_FSYNC_P_LOWER,
661 CS42L42_FSYNC_PERIOD_MASK,
662 CS42L42_FRAC0_VAL(fsync - 1) <<
663 CS42L42_FSYNC_PERIOD_SHIFT);
664 snd_soc_component_update_bits(component,
665 CS42L42_FSYNC_P_UPPER,
666 CS42L42_FSYNC_PERIOD_MASK,
667 CS42L42_FRAC1_VAL(fsync - 1) <<
668 CS42L42_FSYNC_PERIOD_SHIFT);
669 /* Set the LRCLK to 50% duty cycle */
670 fsync = fsync / 2;
671 snd_soc_component_update_bits(component,
672 CS42L42_FSYNC_PW_LOWER,
673 CS42L42_FSYNC_PULSE_WIDTH_MASK,
674 CS42L42_FRAC0_VAL(fsync - 1) <<
675 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
676 snd_soc_component_update_bits(component,
677 CS42L42_FSYNC_PW_UPPER,
678 CS42L42_FSYNC_PULSE_WIDTH_MASK,
679 CS42L42_FRAC1_VAL(fsync - 1) <<
680 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
681 snd_soc_component_update_bits(component,
682 CS42L42_ASP_FRM_CFG,
683 CS42L42_ASP_5050_MASK,
684 CS42L42_ASP_5050_MASK);
685 /* Set the frame delay to 1.0 SCLK clocks */
686 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG,
687 CS42L42_ASP_FSD_MASK,
688 CS42L42_ASP_FSD_1_0 <<
689 CS42L42_ASP_FSD_SHIFT);
690 /* Set the sample rates (96k or lower) */
691 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
692 CS42L42_FS_EN_MASK,
693 (CS42L42_FS_EN_IASRC_96K |
694 CS42L42_FS_EN_OASRC_96K) <<
695 CS42L42_FS_EN_SHIFT);
696 /* Set the input/output internal MCLK clock ~12 MHz */
697 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
698 CS42L42_CLK_IASRC_SEL_MASK,
699 CS42L42_CLK_IASRC_SEL_12 <<
700 CS42L42_CLK_IASRC_SEL_SHIFT);
701 snd_soc_component_update_bits(component,
702 CS42L42_OUT_ASRC_CLK,
703 CS42L42_CLK_OASRC_SEL_MASK,
704 CS42L42_CLK_OASRC_SEL_12 <<
705 CS42L42_CLK_OASRC_SEL_SHIFT);
706 if (pll_ratio_table[i].mclk_src_sel == 0) {
707 /* Pass the clock straight through */
708 snd_soc_component_update_bits(component,
709 CS42L42_PLL_CTL1,
710 CS42L42_PLL_START_MASK, 0);
711 } else {
712 /* Configure PLL per table 4-5 */
713 snd_soc_component_update_bits(component,
714 CS42L42_PLL_DIV_CFG1,
715 CS42L42_SCLK_PREDIV_MASK,
716 pll_ratio_table[i].sclk_prediv
717 << CS42L42_SCLK_PREDIV_SHIFT);
718 snd_soc_component_update_bits(component,
719 CS42L42_PLL_DIV_INT,
720 CS42L42_PLL_DIV_INT_MASK,
721 pll_ratio_table[i].pll_div_int
722 << CS42L42_PLL_DIV_INT_SHIFT);
723 snd_soc_component_update_bits(component,
724 CS42L42_PLL_DIV_FRAC0,
725 CS42L42_PLL_DIV_FRAC_MASK,
726 CS42L42_FRAC0_VAL(
727 pll_ratio_table[i].pll_div_frac)
728 << CS42L42_PLL_DIV_FRAC_SHIFT);
729 snd_soc_component_update_bits(component,
730 CS42L42_PLL_DIV_FRAC1,
731 CS42L42_PLL_DIV_FRAC_MASK,
732 CS42L42_FRAC1_VAL(
733 pll_ratio_table[i].pll_div_frac)
734 << CS42L42_PLL_DIV_FRAC_SHIFT);
735 snd_soc_component_update_bits(component,
736 CS42L42_PLL_DIV_FRAC2,
737 CS42L42_PLL_DIV_FRAC_MASK,
738 CS42L42_FRAC2_VAL(
739 pll_ratio_table[i].pll_div_frac)
740 << CS42L42_PLL_DIV_FRAC_SHIFT);
741 snd_soc_component_update_bits(component,
742 CS42L42_PLL_CTL4,
743 CS42L42_PLL_MODE_MASK,
744 pll_ratio_table[i].pll_mode
745 << CS42L42_PLL_MODE_SHIFT);
746 snd_soc_component_update_bits(component,
747 CS42L42_PLL_CTL3,
748 CS42L42_PLL_DIVOUT_MASK,
749 pll_ratio_table[i].pll_divout
750 << CS42L42_PLL_DIVOUT_SHIFT);
751 snd_soc_component_update_bits(component,
752 CS42L42_PLL_CAL_RATIO,
753 CS42L42_PLL_CAL_RATIO_MASK,
754 pll_ratio_table[i].pll_cal_ratio
755 << CS42L42_PLL_CAL_RATIO_SHIFT);
756 }
757 return 0;
758 }
759 }
760
761 return -EINVAL;
762 }
763
764 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
765 {
766 struct snd_soc_component *component = codec_dai->component;
767 u32 asp_cfg_val = 0;
768
769 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
770 case SND_SOC_DAIFMT_CBS_CFM:
771 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
772 CS42L42_ASP_MODE_SHIFT;
773 break;
774 case SND_SOC_DAIFMT_CBS_CFS:
775 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
776 CS42L42_ASP_MODE_SHIFT;
777 break;
778 default:
779 return -EINVAL;
780 }
781
782 /* interface format */
783 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
784 case SND_SOC_DAIFMT_I2S:
785 case SND_SOC_DAIFMT_LEFT_J:
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 /* Bitclock/frame inversion */
792 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
793 case SND_SOC_DAIFMT_NB_NF:
794 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
795 break;
796 case SND_SOC_DAIFMT_NB_IF:
797 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
798 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
799 break;
800 case SND_SOC_DAIFMT_IB_NF:
801 break;
802 case SND_SOC_DAIFMT_IB_IF:
803 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
804 break;
805 }
806
807 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
808 CS42L42_ASP_SCPOL_MASK |
809 CS42L42_ASP_LCPOL_MASK,
810 asp_cfg_val);
811
812 return 0;
813 }
814
815 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
816 struct snd_pcm_hw_params *params,
817 struct snd_soc_dai *dai)
818 {
819 struct snd_soc_component *component = dai->component;
820 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
821 unsigned int channels = params_channels(params);
822 unsigned int width = (params_width(params) / 8) - 1;
823 unsigned int val = 0;
824
825 cs42l42->srate = params_rate(params);
826 cs42l42->bclk = snd_soc_params_to_bclk(params);
827
828 switch(substream->stream) {
829 case SNDRV_PCM_STREAM_CAPTURE:
830 if (channels == 2) {
831 val |= CS42L42_ASP_TX_CH2_AP_MASK;
832 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT;
833 }
834 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT;
835
836 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
837 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
838 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
839 break;
840 case SNDRV_PCM_STREAM_PLAYBACK:
841 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
842 /* channel 1 on low LRCLK */
843 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
844 CS42L42_ASP_RX_CH_AP_MASK |
845 CS42L42_ASP_RX_CH_RES_MASK, val);
846 /* Channel 2 on high LRCLK */
847 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
848 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
849 CS42L42_ASP_RX_CH_AP_MASK |
850 CS42L42_ASP_RX_CH_RES_MASK, val);
851 break;
852 default:
853 break;
854 }
855
856 return cs42l42_pll_config(component);
857 }
858
859 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
860 int clk_id, unsigned int freq, int dir)
861 {
862 struct snd_soc_component *component = dai->component;
863 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
864
865 cs42l42->sclk = freq;
866
867 return 0;
868 }
869
870 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
871 {
872 struct snd_soc_component *component = dai->component;
873 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
874 unsigned int regval;
875 u8 fullScaleVol;
876 int ret;
877
878 if (mute) {
879 /* Mute the headphone */
880 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
881 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
882 CS42L42_HP_ANA_AMUTE_MASK |
883 CS42L42_HP_ANA_BMUTE_MASK,
884 CS42L42_HP_ANA_AMUTE_MASK |
885 CS42L42_HP_ANA_BMUTE_MASK);
886
887 cs42l42->stream_use &= ~(1 << stream);
888 if(!cs42l42->stream_use) {
889 /*
890 * Switch to the internal oscillator.
891 * SCLK must remain running until after this clock switch.
892 * Without a source of clock the I2C bus doesn't work.
893 */
894 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
895 ARRAY_SIZE(cs42l42_to_osc_seq));
896 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
897 CS42L42_PLL_START_MASK, 0);
898 }
899 } else {
900 if (!cs42l42->stream_use) {
901 /* SCLK must be running before codec unmute */
902 if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600)) {
903 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
904 CS42L42_PLL_START_MASK, 1);
905 ret = regmap_read_poll_timeout(cs42l42->regmap,
906 CS42L42_PLL_LOCK_STATUS,
907 regval,
908 (regval & 1),
909 CS42L42_PLL_LOCK_POLL_US,
910 CS42L42_PLL_LOCK_TIMEOUT_US);
911 if (ret < 0)
912 dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
913 }
914
915 /* Mark SCLK as present, turn off internal oscillator */
916 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
917 ARRAY_SIZE(cs42l42_to_sclk_seq));
918 }
919 cs42l42->stream_use |= 1 << stream;
920
921 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
922 /* Read the headphone load */
923 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
924 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) ==
925 CS42L42_RLA_STAT_15_OHM) {
926 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
927 } else {
928 fullScaleVol = 0;
929 }
930
931 /* Un-mute the headphone, set the full scale volume flag */
932 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
933 CS42L42_HP_ANA_AMUTE_MASK |
934 CS42L42_HP_ANA_BMUTE_MASK |
935 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
936 }
937 }
938
939 return 0;
940 }
941
942 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
943 SNDRV_PCM_FMTBIT_S24_LE |\
944 SNDRV_PCM_FMTBIT_S32_LE )
945
946
947 static const struct snd_soc_dai_ops cs42l42_ops = {
948 .hw_params = cs42l42_pcm_hw_params,
949 .set_fmt = cs42l42_set_dai_fmt,
950 .set_sysclk = cs42l42_set_sysclk,
951 .mute_stream = cs42l42_mute_stream,
952 };
953
954 static struct snd_soc_dai_driver cs42l42_dai = {
955 .name = "cs42l42",
956 .playback = {
957 .stream_name = "Playback",
958 .channels_min = 1,
959 .channels_max = 2,
960 .rates = SNDRV_PCM_RATE_8000_192000,
961 .formats = CS42L42_FORMATS,
962 },
963 .capture = {
964 .stream_name = "Capture",
965 .channels_min = 1,
966 .channels_max = 2,
967 .rates = SNDRV_PCM_RATE_8000_192000,
968 .formats = CS42L42_FORMATS,
969 },
970 .symmetric_rate = 1,
971 .symmetric_sample_bits = 1,
972 .ops = &cs42l42_ops,
973 };
974
975 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
976 {
977 unsigned int hs_det_status;
978 unsigned int int_status;
979
980 /* Mask the auto detect interrupt */
981 regmap_update_bits(cs42l42->regmap,
982 CS42L42_CODEC_INT_MASK,
983 CS42L42_PDN_DONE_MASK |
984 CS42L42_HSDET_AUTO_DONE_MASK,
985 (1 << CS42L42_PDN_DONE_SHIFT) |
986 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
987
988 /* Set hs detect to automatic, disabled mode */
989 regmap_update_bits(cs42l42->regmap,
990 CS42L42_HSDET_CTL2,
991 CS42L42_HSDET_CTRL_MASK |
992 CS42L42_HSDET_SET_MASK |
993 CS42L42_HSBIAS_REF_MASK |
994 CS42L42_HSDET_AUTO_TIME_MASK,
995 (2 << CS42L42_HSDET_CTRL_SHIFT) |
996 (2 << CS42L42_HSDET_SET_SHIFT) |
997 (0 << CS42L42_HSBIAS_REF_SHIFT) |
998 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
999
1000 /* Read and save the hs detection result */
1001 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1002
1003 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1004 CS42L42_HSDET_TYPE_SHIFT;
1005
1006 /* Set up button detection */
1007 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1008 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1009 /* Set auto HS bias settings to default */
1010 regmap_update_bits(cs42l42->regmap,
1011 CS42L42_HSBIAS_SC_AUTOCTL,
1012 CS42L42_HSBIAS_SENSE_EN_MASK |
1013 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1014 CS42L42_TIP_SENSE_EN_MASK |
1015 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1016 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1017 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1018 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1019 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1020
1021 /* Set up hs detect level sensitivity */
1022 regmap_update_bits(cs42l42->regmap,
1023 CS42L42_MIC_DET_CTL1,
1024 CS42L42_LATCH_TO_VP_MASK |
1025 CS42L42_EVENT_STAT_SEL_MASK |
1026 CS42L42_HS_DET_LEVEL_MASK,
1027 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1028 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1029 (cs42l42->bias_thresholds[0] <<
1030 CS42L42_HS_DET_LEVEL_SHIFT));
1031
1032 /* Set auto HS bias settings to default */
1033 regmap_update_bits(cs42l42->regmap,
1034 CS42L42_HSBIAS_SC_AUTOCTL,
1035 CS42L42_HSBIAS_SENSE_EN_MASK |
1036 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1037 CS42L42_TIP_SENSE_EN_MASK |
1038 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1039 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1040 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1041 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1042 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1043
1044 /* Turn on level detect circuitry */
1045 regmap_update_bits(cs42l42->regmap,
1046 CS42L42_MISC_DET_CTL,
1047 CS42L42_DETECT_MODE_MASK |
1048 CS42L42_HSBIAS_CTL_MASK |
1049 CS42L42_PDN_MIC_LVL_DET_MASK,
1050 (0 << CS42L42_DETECT_MODE_SHIFT) |
1051 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1052 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1053
1054 msleep(cs42l42->btn_det_init_dbnce);
1055
1056 /* Clear any button interrupts before unmasking them */
1057 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1058 &int_status);
1059
1060 /* Unmask button detect interrupts */
1061 regmap_update_bits(cs42l42->regmap,
1062 CS42L42_DET_INT2_MASK,
1063 CS42L42_M_DETECT_TF_MASK |
1064 CS42L42_M_DETECT_FT_MASK |
1065 CS42L42_M_HSBIAS_HIZ_MASK |
1066 CS42L42_M_SHORT_RLS_MASK |
1067 CS42L42_M_SHORT_DET_MASK,
1068 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1069 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1070 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1071 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1072 (1 << CS42L42_M_SHORT_DET_SHIFT));
1073 } else {
1074 /* Make sure button detect and HS bias circuits are off */
1075 regmap_update_bits(cs42l42->regmap,
1076 CS42L42_MISC_DET_CTL,
1077 CS42L42_DETECT_MODE_MASK |
1078 CS42L42_HSBIAS_CTL_MASK |
1079 CS42L42_PDN_MIC_LVL_DET_MASK,
1080 (0 << CS42L42_DETECT_MODE_SHIFT) |
1081 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1082 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1083 }
1084
1085 regmap_update_bits(cs42l42->regmap,
1086 CS42L42_DAC_CTL2,
1087 CS42L42_HPOUT_PULLDOWN_MASK |
1088 CS42L42_HPOUT_LOAD_MASK |
1089 CS42L42_HPOUT_CLAMP_MASK |
1090 CS42L42_DAC_HPF_EN_MASK |
1091 CS42L42_DAC_MON_EN_MASK,
1092 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1093 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1094 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1095 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1096 (0 << CS42L42_DAC_MON_EN_SHIFT));
1097
1098 /* Unmask tip sense interrupts */
1099 regmap_update_bits(cs42l42->regmap,
1100 CS42L42_TSRS_PLUG_INT_MASK,
1101 CS42L42_RS_PLUG_MASK |
1102 CS42L42_RS_UNPLUG_MASK |
1103 CS42L42_TS_PLUG_MASK |
1104 CS42L42_TS_UNPLUG_MASK,
1105 (1 << CS42L42_RS_PLUG_SHIFT) |
1106 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1107 (0 << CS42L42_TS_PLUG_SHIFT) |
1108 (0 << CS42L42_TS_UNPLUG_SHIFT));
1109 }
1110
1111 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1112 {
1113 /* Mask tip sense interrupts */
1114 regmap_update_bits(cs42l42->regmap,
1115 CS42L42_TSRS_PLUG_INT_MASK,
1116 CS42L42_RS_PLUG_MASK |
1117 CS42L42_RS_UNPLUG_MASK |
1118 CS42L42_TS_PLUG_MASK |
1119 CS42L42_TS_UNPLUG_MASK,
1120 (1 << CS42L42_RS_PLUG_SHIFT) |
1121 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1122 (1 << CS42L42_TS_PLUG_SHIFT) |
1123 (1 << CS42L42_TS_UNPLUG_SHIFT));
1124
1125 /* Make sure button detect and HS bias circuits are off */
1126 regmap_update_bits(cs42l42->regmap,
1127 CS42L42_MISC_DET_CTL,
1128 CS42L42_DETECT_MODE_MASK |
1129 CS42L42_HSBIAS_CTL_MASK |
1130 CS42L42_PDN_MIC_LVL_DET_MASK,
1131 (0 << CS42L42_DETECT_MODE_SHIFT) |
1132 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1133 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1134
1135 /* Set auto HS bias settings to default */
1136 regmap_update_bits(cs42l42->regmap,
1137 CS42L42_HSBIAS_SC_AUTOCTL,
1138 CS42L42_HSBIAS_SENSE_EN_MASK |
1139 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1140 CS42L42_TIP_SENSE_EN_MASK |
1141 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1142 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1143 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1144 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1145 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1146
1147 /* Set hs detect to manual, disabled mode */
1148 regmap_update_bits(cs42l42->regmap,
1149 CS42L42_HSDET_CTL2,
1150 CS42L42_HSDET_CTRL_MASK |
1151 CS42L42_HSDET_SET_MASK |
1152 CS42L42_HSBIAS_REF_MASK |
1153 CS42L42_HSDET_AUTO_TIME_MASK,
1154 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1155 (2 << CS42L42_HSDET_SET_SHIFT) |
1156 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1157 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1158
1159 regmap_update_bits(cs42l42->regmap,
1160 CS42L42_DAC_CTL2,
1161 CS42L42_HPOUT_PULLDOWN_MASK |
1162 CS42L42_HPOUT_LOAD_MASK |
1163 CS42L42_HPOUT_CLAMP_MASK |
1164 CS42L42_DAC_HPF_EN_MASK |
1165 CS42L42_DAC_MON_EN_MASK,
1166 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1167 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1168 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1169 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1170 (1 << CS42L42_DAC_MON_EN_SHIFT));
1171
1172 /* Power up HS bias to 2.7V */
1173 regmap_update_bits(cs42l42->regmap,
1174 CS42L42_MISC_DET_CTL,
1175 CS42L42_DETECT_MODE_MASK |
1176 CS42L42_HSBIAS_CTL_MASK |
1177 CS42L42_PDN_MIC_LVL_DET_MASK,
1178 (0 << CS42L42_DETECT_MODE_SHIFT) |
1179 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1180 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1181
1182 /* Wait for HS bias to ramp up */
1183 msleep(cs42l42->hs_bias_ramp_time);
1184
1185 /* Unmask auto detect interrupt */
1186 regmap_update_bits(cs42l42->regmap,
1187 CS42L42_CODEC_INT_MASK,
1188 CS42L42_PDN_DONE_MASK |
1189 CS42L42_HSDET_AUTO_DONE_MASK,
1190 (1 << CS42L42_PDN_DONE_SHIFT) |
1191 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1192
1193 /* Set hs detect to automatic, enabled mode */
1194 regmap_update_bits(cs42l42->regmap,
1195 CS42L42_HSDET_CTL2,
1196 CS42L42_HSDET_CTRL_MASK |
1197 CS42L42_HSDET_SET_MASK |
1198 CS42L42_HSBIAS_REF_MASK |
1199 CS42L42_HSDET_AUTO_TIME_MASK,
1200 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1201 (2 << CS42L42_HSDET_SET_SHIFT) |
1202 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1203 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1204 }
1205
1206 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1207 {
1208 /* Mask button detect interrupts */
1209 regmap_update_bits(cs42l42->regmap,
1210 CS42L42_DET_INT2_MASK,
1211 CS42L42_M_DETECT_TF_MASK |
1212 CS42L42_M_DETECT_FT_MASK |
1213 CS42L42_M_HSBIAS_HIZ_MASK |
1214 CS42L42_M_SHORT_RLS_MASK |
1215 CS42L42_M_SHORT_DET_MASK,
1216 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1217 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1218 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1219 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1220 (1 << CS42L42_M_SHORT_DET_SHIFT));
1221
1222 /* Ground HS bias */
1223 regmap_update_bits(cs42l42->regmap,
1224 CS42L42_MISC_DET_CTL,
1225 CS42L42_DETECT_MODE_MASK |
1226 CS42L42_HSBIAS_CTL_MASK |
1227 CS42L42_PDN_MIC_LVL_DET_MASK,
1228 (0 << CS42L42_DETECT_MODE_SHIFT) |
1229 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1230 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1231
1232 /* Set auto HS bias settings to default */
1233 regmap_update_bits(cs42l42->regmap,
1234 CS42L42_HSBIAS_SC_AUTOCTL,
1235 CS42L42_HSBIAS_SENSE_EN_MASK |
1236 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1237 CS42L42_TIP_SENSE_EN_MASK |
1238 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1239 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1240 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1241 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1242 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1243
1244 /* Set hs detect to manual, disabled mode */
1245 regmap_update_bits(cs42l42->regmap,
1246 CS42L42_HSDET_CTL2,
1247 CS42L42_HSDET_CTRL_MASK |
1248 CS42L42_HSDET_SET_MASK |
1249 CS42L42_HSBIAS_REF_MASK |
1250 CS42L42_HSDET_AUTO_TIME_MASK,
1251 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1252 (2 << CS42L42_HSDET_SET_SHIFT) |
1253 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1254 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1255 }
1256
1257 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1258 {
1259 int bias_level;
1260 unsigned int detect_status;
1261
1262 /* Mask button detect interrupts */
1263 regmap_update_bits(cs42l42->regmap,
1264 CS42L42_DET_INT2_MASK,
1265 CS42L42_M_DETECT_TF_MASK |
1266 CS42L42_M_DETECT_FT_MASK |
1267 CS42L42_M_HSBIAS_HIZ_MASK |
1268 CS42L42_M_SHORT_RLS_MASK |
1269 CS42L42_M_SHORT_DET_MASK,
1270 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1271 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1272 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1273 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1274 (1 << CS42L42_M_SHORT_DET_SHIFT));
1275
1276 usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1277 cs42l42->btn_det_event_dbnce * 2000);
1278
1279 /* Test all 4 level detect biases */
1280 bias_level = 1;
1281 do {
1282 /* Adjust button detect level sensitivity */
1283 regmap_update_bits(cs42l42->regmap,
1284 CS42L42_MIC_DET_CTL1,
1285 CS42L42_LATCH_TO_VP_MASK |
1286 CS42L42_EVENT_STAT_SEL_MASK |
1287 CS42L42_HS_DET_LEVEL_MASK,
1288 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1289 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1290 (cs42l42->bias_thresholds[bias_level] <<
1291 CS42L42_HS_DET_LEVEL_SHIFT));
1292
1293 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1294 &detect_status);
1295 } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1296 (++bias_level < CS42L42_NUM_BIASES));
1297
1298 switch (bias_level) {
1299 case 1: /* Function C button press */
1300 bias_level = SND_JACK_BTN_2;
1301 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1302 break;
1303 case 2: /* Function B button press */
1304 bias_level = SND_JACK_BTN_1;
1305 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1306 break;
1307 case 3: /* Function D button press */
1308 bias_level = SND_JACK_BTN_3;
1309 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1310 break;
1311 case 4: /* Function A button press */
1312 bias_level = SND_JACK_BTN_0;
1313 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1314 break;
1315 default:
1316 bias_level = 0;
1317 break;
1318 }
1319
1320 /* Set button detect level sensitivity back to default */
1321 regmap_update_bits(cs42l42->regmap,
1322 CS42L42_MIC_DET_CTL1,
1323 CS42L42_LATCH_TO_VP_MASK |
1324 CS42L42_EVENT_STAT_SEL_MASK |
1325 CS42L42_HS_DET_LEVEL_MASK,
1326 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1327 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1328 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1329
1330 /* Clear any button interrupts before unmasking them */
1331 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1332 &detect_status);
1333
1334 /* Unmask button detect interrupts */
1335 regmap_update_bits(cs42l42->regmap,
1336 CS42L42_DET_INT2_MASK,
1337 CS42L42_M_DETECT_TF_MASK |
1338 CS42L42_M_DETECT_FT_MASK |
1339 CS42L42_M_HSBIAS_HIZ_MASK |
1340 CS42L42_M_SHORT_RLS_MASK |
1341 CS42L42_M_SHORT_DET_MASK,
1342 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1343 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1344 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1345 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1346 (1 << CS42L42_M_SHORT_DET_SHIFT));
1347
1348 return bias_level;
1349 }
1350
1351 struct cs42l42_irq_params {
1352 u16 status_addr;
1353 u16 mask_addr;
1354 u8 mask;
1355 };
1356
1357 static const struct cs42l42_irq_params irq_params_table[] = {
1358 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1359 CS42L42_ADC_OVFL_VAL_MASK},
1360 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1361 CS42L42_MIXER_VAL_MASK},
1362 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1363 CS42L42_SRC_VAL_MASK},
1364 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1365 CS42L42_ASP_RX_VAL_MASK},
1366 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1367 CS42L42_ASP_TX_VAL_MASK},
1368 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1369 CS42L42_CODEC_VAL_MASK},
1370 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1371 CS42L42_DET_INT_VAL1_MASK},
1372 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1373 CS42L42_DET_INT_VAL2_MASK},
1374 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1375 CS42L42_SRCPL_VAL_MASK},
1376 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1377 CS42L42_VPMON_VAL_MASK},
1378 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1379 CS42L42_PLL_LOCK_VAL_MASK},
1380 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1381 CS42L42_TSRS_PLUG_VAL_MASK}
1382 };
1383
1384 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1385 {
1386 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1387 struct snd_soc_component *component = cs42l42->component;
1388 unsigned int stickies[12];
1389 unsigned int masks[12];
1390 unsigned int current_plug_status;
1391 unsigned int current_button_status;
1392 unsigned int i;
1393 int report = 0;
1394
1395
1396 /* Read sticky registers to clear interurpt */
1397 for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1398 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1399 &(stickies[i]));
1400 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1401 &(masks[i]));
1402 stickies[i] = stickies[i] & (~masks[i]) &
1403 irq_params_table[i].mask;
1404 }
1405
1406 /* Read tip sense status before handling type detect */
1407 current_plug_status = (stickies[11] &
1408 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1409 CS42L42_TS_PLUG_SHIFT;
1410
1411 /* Read button sense status */
1412 current_button_status = stickies[7] &
1413 (CS42L42_M_DETECT_TF_MASK |
1414 CS42L42_M_DETECT_FT_MASK |
1415 CS42L42_M_HSBIAS_HIZ_MASK);
1416
1417 /* Check auto-detect status */
1418 if ((~masks[5]) & irq_params_table[5].mask) {
1419 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1420 cs42l42_process_hs_type_detect(cs42l42);
1421 switch(cs42l42->hs_type){
1422 case CS42L42_PLUG_CTIA:
1423 case CS42L42_PLUG_OMTP:
1424 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1425 SND_JACK_HEADSET);
1426 break;
1427 case CS42L42_PLUG_HEADPHONE:
1428 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1429 SND_JACK_HEADPHONE);
1430 break;
1431 default:
1432 break;
1433 }
1434 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1435 }
1436 }
1437
1438 /* Check tip sense status */
1439 if ((~masks[11]) & irq_params_table[11].mask) {
1440 switch (current_plug_status) {
1441 case CS42L42_TS_PLUG:
1442 if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1443 cs42l42->plug_state = CS42L42_TS_PLUG;
1444 cs42l42_init_hs_type_detect(cs42l42);
1445 }
1446 break;
1447
1448 case CS42L42_TS_UNPLUG:
1449 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1450 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1451 cs42l42_cancel_hs_type_detect(cs42l42);
1452
1453 switch(cs42l42->hs_type){
1454 case CS42L42_PLUG_CTIA:
1455 case CS42L42_PLUG_OMTP:
1456 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET);
1457 break;
1458 case CS42L42_PLUG_HEADPHONE:
1459 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE);
1460 break;
1461 default:
1462 break;
1463 }
1464 dev_dbg(component->dev, "Unplug event\n");
1465 }
1466 break;
1467
1468 default:
1469 if (cs42l42->plug_state != CS42L42_TS_TRANS)
1470 cs42l42->plug_state = CS42L42_TS_TRANS;
1471 }
1472 }
1473
1474 /* Check button detect status */
1475 if ((~masks[7]) & irq_params_table[7].mask) {
1476 if (!(current_button_status &
1477 CS42L42_M_HSBIAS_HIZ_MASK)) {
1478
1479 if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1480 dev_dbg(component->dev, "Button released\n");
1481 report = 0;
1482 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1483 report = cs42l42_handle_button_press(cs42l42);
1484
1485 }
1486 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1487 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1488 }
1489 }
1490
1491 return IRQ_HANDLED;
1492 }
1493
1494 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1495 {
1496 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1497 CS42L42_ADC_OVFL_MASK,
1498 (1 << CS42L42_ADC_OVFL_SHIFT));
1499
1500 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1501 CS42L42_MIX_CHB_OVFL_MASK |
1502 CS42L42_MIX_CHA_OVFL_MASK |
1503 CS42L42_EQ_OVFL_MASK |
1504 CS42L42_EQ_BIQUAD_OVFL_MASK,
1505 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1506 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1507 (1 << CS42L42_EQ_OVFL_SHIFT) |
1508 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1509
1510 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1511 CS42L42_SRC_ILK_MASK |
1512 CS42L42_SRC_OLK_MASK |
1513 CS42L42_SRC_IUNLK_MASK |
1514 CS42L42_SRC_OUNLK_MASK,
1515 (1 << CS42L42_SRC_ILK_SHIFT) |
1516 (1 << CS42L42_SRC_OLK_SHIFT) |
1517 (1 << CS42L42_SRC_IUNLK_SHIFT) |
1518 (1 << CS42L42_SRC_OUNLK_SHIFT));
1519
1520 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1521 CS42L42_ASPRX_NOLRCK_MASK |
1522 CS42L42_ASPRX_EARLY_MASK |
1523 CS42L42_ASPRX_LATE_MASK |
1524 CS42L42_ASPRX_ERROR_MASK |
1525 CS42L42_ASPRX_OVLD_MASK,
1526 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1527 (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1528 (1 << CS42L42_ASPRX_LATE_SHIFT) |
1529 (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1530 (1 << CS42L42_ASPRX_OVLD_SHIFT));
1531
1532 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1533 CS42L42_ASPTX_NOLRCK_MASK |
1534 CS42L42_ASPTX_EARLY_MASK |
1535 CS42L42_ASPTX_LATE_MASK |
1536 CS42L42_ASPTX_SMERROR_MASK,
1537 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1538 (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1539 (1 << CS42L42_ASPTX_LATE_SHIFT) |
1540 (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1541
1542 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1543 CS42L42_PDN_DONE_MASK |
1544 CS42L42_HSDET_AUTO_DONE_MASK,
1545 (1 << CS42L42_PDN_DONE_SHIFT) |
1546 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1547
1548 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1549 CS42L42_SRCPL_ADC_LK_MASK |
1550 CS42L42_SRCPL_DAC_LK_MASK |
1551 CS42L42_SRCPL_ADC_UNLK_MASK |
1552 CS42L42_SRCPL_DAC_UNLK_MASK,
1553 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1554 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1555 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1556 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1557
1558 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1559 CS42L42_TIP_SENSE_UNPLUG_MASK |
1560 CS42L42_TIP_SENSE_PLUG_MASK |
1561 CS42L42_HSBIAS_SENSE_MASK,
1562 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1563 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1564 (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1565
1566 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1567 CS42L42_M_DETECT_TF_MASK |
1568 CS42L42_M_DETECT_FT_MASK |
1569 CS42L42_M_HSBIAS_HIZ_MASK |
1570 CS42L42_M_SHORT_RLS_MASK |
1571 CS42L42_M_SHORT_DET_MASK,
1572 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1573 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1574 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1575 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1576 (1 << CS42L42_M_SHORT_DET_SHIFT));
1577
1578 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1579 CS42L42_VPMON_MASK,
1580 (1 << CS42L42_VPMON_SHIFT));
1581
1582 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1583 CS42L42_PLL_LOCK_MASK,
1584 (1 << CS42L42_PLL_LOCK_SHIFT));
1585
1586 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1587 CS42L42_RS_PLUG_MASK |
1588 CS42L42_RS_UNPLUG_MASK |
1589 CS42L42_TS_PLUG_MASK |
1590 CS42L42_TS_UNPLUG_MASK,
1591 (1 << CS42L42_RS_PLUG_SHIFT) |
1592 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1593 (1 << CS42L42_TS_PLUG_SHIFT) |
1594 (1 << CS42L42_TS_UNPLUG_SHIFT));
1595 }
1596
1597 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1598 {
1599 unsigned int reg;
1600
1601 cs42l42->hs_type = CS42L42_PLUG_INVALID;
1602
1603 /* Latch analog controls to VP power domain */
1604 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1605 CS42L42_LATCH_TO_VP_MASK |
1606 CS42L42_EVENT_STAT_SEL_MASK |
1607 CS42L42_HS_DET_LEVEL_MASK,
1608 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1609 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1610 (cs42l42->bias_thresholds[0] <<
1611 CS42L42_HS_DET_LEVEL_SHIFT));
1612
1613 /* Remove ground noise-suppression clamps */
1614 regmap_update_bits(cs42l42->regmap,
1615 CS42L42_HS_CLAMP_DISABLE,
1616 CS42L42_HS_CLAMP_DISABLE_MASK,
1617 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1618
1619 /* Enable the tip sense circuit */
1620 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1621 CS42L42_TIP_SENSE_CTRL_MASK |
1622 CS42L42_TIP_SENSE_INV_MASK |
1623 CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1624 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1625 (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1626 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1627
1628 /* Save the initial status of the tip sense */
1629 regmap_read(cs42l42->regmap,
1630 CS42L42_TSRS_PLUG_STATUS,
1631 &reg);
1632 cs42l42->plug_state = (((char) reg) &
1633 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1634 CS42L42_TS_PLUG_SHIFT;
1635 }
1636
1637 static const unsigned int threshold_defaults[] = {
1638 CS42L42_HS_DET_LEVEL_15,
1639 CS42L42_HS_DET_LEVEL_8,
1640 CS42L42_HS_DET_LEVEL_4,
1641 CS42L42_HS_DET_LEVEL_1
1642 };
1643
1644 static int cs42l42_handle_device_data(struct device *dev,
1645 struct cs42l42_private *cs42l42)
1646 {
1647 unsigned int val;
1648 u32 thresholds[CS42L42_NUM_BIASES];
1649 int ret;
1650 int i;
1651
1652 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1653 if (!ret) {
1654 switch (val) {
1655 case CS42L42_TS_INV_EN:
1656 case CS42L42_TS_INV_DIS:
1657 cs42l42->ts_inv = val;
1658 break;
1659 default:
1660 dev_err(dev,
1661 "Wrong cirrus,ts-inv DT value %d\n",
1662 val);
1663 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1664 }
1665 } else {
1666 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1667 }
1668
1669 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1670 CS42L42_TS_INV_MASK,
1671 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1672
1673 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1674 if (!ret) {
1675 switch (val) {
1676 case CS42L42_TS_DBNCE_0:
1677 case CS42L42_TS_DBNCE_125:
1678 case CS42L42_TS_DBNCE_250:
1679 case CS42L42_TS_DBNCE_500:
1680 case CS42L42_TS_DBNCE_750:
1681 case CS42L42_TS_DBNCE_1000:
1682 case CS42L42_TS_DBNCE_1250:
1683 case CS42L42_TS_DBNCE_1500:
1684 cs42l42->ts_dbnc_rise = val;
1685 break;
1686 default:
1687 dev_err(dev,
1688 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1689 val);
1690 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1691 }
1692 } else {
1693 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1694 }
1695
1696 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1697 CS42L42_TS_RISE_DBNCE_TIME_MASK,
1698 (cs42l42->ts_dbnc_rise <<
1699 CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1700
1701 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1702 if (!ret) {
1703 switch (val) {
1704 case CS42L42_TS_DBNCE_0:
1705 case CS42L42_TS_DBNCE_125:
1706 case CS42L42_TS_DBNCE_250:
1707 case CS42L42_TS_DBNCE_500:
1708 case CS42L42_TS_DBNCE_750:
1709 case CS42L42_TS_DBNCE_1000:
1710 case CS42L42_TS_DBNCE_1250:
1711 case CS42L42_TS_DBNCE_1500:
1712 cs42l42->ts_dbnc_fall = val;
1713 break;
1714 default:
1715 dev_err(dev,
1716 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1717 val);
1718 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1719 }
1720 } else {
1721 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1722 }
1723
1724 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1725 CS42L42_TS_FALL_DBNCE_TIME_MASK,
1726 (cs42l42->ts_dbnc_fall <<
1727 CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1728
1729 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1730 if (!ret) {
1731 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1732 cs42l42->btn_det_init_dbnce = val;
1733 else {
1734 dev_err(dev,
1735 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1736 val);
1737 cs42l42->btn_det_init_dbnce =
1738 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1739 }
1740 } else {
1741 cs42l42->btn_det_init_dbnce =
1742 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1743 }
1744
1745 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1746 if (!ret) {
1747 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1748 cs42l42->btn_det_event_dbnce = val;
1749 else {
1750 dev_err(dev,
1751 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1752 cs42l42->btn_det_event_dbnce =
1753 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1754 }
1755 } else {
1756 cs42l42->btn_det_event_dbnce =
1757 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1758 }
1759
1760 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1761 thresholds, ARRAY_SIZE(thresholds));
1762 if (!ret) {
1763 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1764 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1765 cs42l42->bias_thresholds[i] = thresholds[i];
1766 else {
1767 dev_err(dev,
1768 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1769 thresholds[i]);
1770 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1771 }
1772 }
1773 } else {
1774 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1775 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1776 }
1777
1778 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
1779 if (!ret) {
1780 switch (val) {
1781 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1782 cs42l42->hs_bias_ramp_rate = val;
1783 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1784 break;
1785 case CS42L42_HSBIAS_RAMP_FAST:
1786 cs42l42->hs_bias_ramp_rate = val;
1787 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1788 break;
1789 case CS42L42_HSBIAS_RAMP_SLOW:
1790 cs42l42->hs_bias_ramp_rate = val;
1791 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1792 break;
1793 case CS42L42_HSBIAS_RAMP_SLOWEST:
1794 cs42l42->hs_bias_ramp_rate = val;
1795 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1796 break;
1797 default:
1798 dev_err(dev,
1799 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1800 val);
1801 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1802 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1803 }
1804 } else {
1805 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1806 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1807 }
1808
1809 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1810 CS42L42_HSBIAS_RAMP_MASK,
1811 (cs42l42->hs_bias_ramp_rate <<
1812 CS42L42_HSBIAS_RAMP_SHIFT));
1813
1814 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
1815 cs42l42->hs_bias_sense_en = 0;
1816 else
1817 cs42l42->hs_bias_sense_en = 1;
1818
1819 return 0;
1820 }
1821
1822 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1823 const struct i2c_device_id *id)
1824 {
1825 struct cs42l42_private *cs42l42;
1826 int ret, i, devid;
1827 unsigned int reg;
1828
1829 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1830 GFP_KERNEL);
1831 if (!cs42l42)
1832 return -ENOMEM;
1833
1834 i2c_set_clientdata(i2c_client, cs42l42);
1835
1836 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1837 if (IS_ERR(cs42l42->regmap)) {
1838 ret = PTR_ERR(cs42l42->regmap);
1839 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1840 return ret;
1841 }
1842
1843 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1844 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1845
1846 ret = devm_regulator_bulk_get(&i2c_client->dev,
1847 ARRAY_SIZE(cs42l42->supplies),
1848 cs42l42->supplies);
1849 if (ret != 0) {
1850 dev_err(&i2c_client->dev,
1851 "Failed to request supplies: %d\n", ret);
1852 return ret;
1853 }
1854
1855 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1856 cs42l42->supplies);
1857 if (ret != 0) {
1858 dev_err(&i2c_client->dev,
1859 "Failed to enable supplies: %d\n", ret);
1860 return ret;
1861 }
1862
1863 /* Reset the Device */
1864 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1865 "reset", GPIOD_OUT_LOW);
1866 if (IS_ERR(cs42l42->reset_gpio)) {
1867 ret = PTR_ERR(cs42l42->reset_gpio);
1868 goto err_disable;
1869 }
1870
1871 if (cs42l42->reset_gpio) {
1872 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1873 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1874 }
1875 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1876
1877 /* Request IRQ */
1878 ret = devm_request_threaded_irq(&i2c_client->dev,
1879 i2c_client->irq,
1880 NULL, cs42l42_irq_thread,
1881 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1882 "cs42l42", cs42l42);
1883
1884 if (ret != 0)
1885 dev_err(&i2c_client->dev,
1886 "Failed to request IRQ: %d\n", ret);
1887
1888 /* initialize codec */
1889 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
1890 if (devid < 0) {
1891 ret = devid;
1892 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1893 goto err_disable;
1894 }
1895
1896 if (devid != CS42L42_CHIP_ID) {
1897 ret = -ENODEV;
1898 dev_err(&i2c_client->dev,
1899 "CS42L42 Device ID (%X). Expected %X\n",
1900 devid, CS42L42_CHIP_ID);
1901 goto err_disable;
1902 }
1903
1904 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1905 if (ret < 0) {
1906 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1907 goto err_disable;
1908 }
1909
1910 dev_info(&i2c_client->dev,
1911 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1912
1913 /* Power up the codec */
1914 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1915 CS42L42_ASP_DAO_PDN_MASK |
1916 CS42L42_ASP_DAI_PDN_MASK |
1917 CS42L42_MIXER_PDN_MASK |
1918 CS42L42_EQ_PDN_MASK |
1919 CS42L42_HP_PDN_MASK |
1920 CS42L42_ADC_PDN_MASK |
1921 CS42L42_PDN_ALL_MASK,
1922 (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1923 (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1924 (1 << CS42L42_MIXER_PDN_SHIFT) |
1925 (1 << CS42L42_EQ_PDN_SHIFT) |
1926 (1 << CS42L42_HP_PDN_SHIFT) |
1927 (1 << CS42L42_ADC_PDN_SHIFT) |
1928 (0 << CS42L42_PDN_ALL_SHIFT));
1929
1930 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
1931 if (ret != 0)
1932 goto err_disable;
1933
1934 /* Setup headset detection */
1935 cs42l42_setup_hs_type_detect(cs42l42);
1936
1937 /* Mask/Unmask Interrupts */
1938 cs42l42_set_interrupt_masks(cs42l42);
1939
1940 /* Register codec for machine driver */
1941 ret = devm_snd_soc_register_component(&i2c_client->dev,
1942 &soc_component_dev_cs42l42, &cs42l42_dai, 1);
1943 if (ret < 0)
1944 goto err_disable;
1945 return 0;
1946
1947 err_disable:
1948 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1949 cs42l42->supplies);
1950 return ret;
1951 }
1952
1953 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1954 {
1955 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1956
1957 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42);
1958 pm_runtime_suspend(&i2c_client->dev);
1959 pm_runtime_disable(&i2c_client->dev);
1960
1961 return 0;
1962 }
1963
1964 #ifdef CONFIG_PM
1965 static int cs42l42_runtime_suspend(struct device *dev)
1966 {
1967 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1968
1969 regcache_cache_only(cs42l42->regmap, true);
1970 regcache_mark_dirty(cs42l42->regmap);
1971
1972 /* Hold down reset */
1973 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1974
1975 /* remove power */
1976 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1977 cs42l42->supplies);
1978
1979 return 0;
1980 }
1981
1982 static int cs42l42_runtime_resume(struct device *dev)
1983 {
1984 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1985 int ret;
1986
1987 /* Enable power */
1988 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1989 cs42l42->supplies);
1990 if (ret != 0) {
1991 dev_err(dev, "Failed to enable supplies: %d\n",
1992 ret);
1993 return ret;
1994 }
1995
1996 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1997 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1998
1999 regcache_cache_only(cs42l42->regmap, false);
2000 regcache_sync(cs42l42->regmap);
2001
2002 return 0;
2003 }
2004 #endif
2005
2006 static const struct dev_pm_ops cs42l42_runtime_pm = {
2007 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
2008 NULL)
2009 };
2010
2011 #ifdef CONFIG_OF
2012 static const struct of_device_id cs42l42_of_match[] = {
2013 { .compatible = "cirrus,cs42l42", },
2014 {}
2015 };
2016 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2017 #endif
2018
2019 #ifdef CONFIG_ACPI
2020 static const struct acpi_device_id cs42l42_acpi_match[] = {
2021 {"10134242", 0,},
2022 {}
2023 };
2024 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2025 #endif
2026
2027 static const struct i2c_device_id cs42l42_id[] = {
2028 {"cs42l42", 0},
2029 {}
2030 };
2031
2032 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2033
2034 static struct i2c_driver cs42l42_i2c_driver = {
2035 .driver = {
2036 .name = "cs42l42",
2037 .pm = &cs42l42_runtime_pm,
2038 .of_match_table = of_match_ptr(cs42l42_of_match),
2039 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2040 },
2041 .id_table = cs42l42_id,
2042 .probe = cs42l42_i2c_probe,
2043 .remove = cs42l42_i2c_remove,
2044 };
2045
2046 module_i2c_driver(cs42l42_i2c_driver);
2047
2048 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2049 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2050 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2051 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2052 MODULE_LICENSE("GPL");
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