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[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / max98095.c
1 /*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <linux/slab.h>
26 #include <asm/div64.h>
27 #include <sound/max98095.h>
28 #include <sound/jack.h>
29 #include "max98095.h"
30
31 enum max98095_type {
32 MAX98095,
33 };
34
35 struct max98095_cdata {
36 unsigned int rate;
37 unsigned int fmt;
38 int eq_sel;
39 int bq_sel;
40 };
41
42 struct max98095_priv {
43 struct regmap *regmap;
44 enum max98095_type devtype;
45 struct max98095_pdata *pdata;
46 struct clk *mclk;
47 unsigned int sysclk;
48 struct max98095_cdata dai[3];
49 const char **eq_texts;
50 const char **bq_texts;
51 struct soc_enum eq_enum;
52 struct soc_enum bq_enum;
53 int eq_textcnt;
54 int bq_textcnt;
55 u8 lin_state;
56 unsigned int mic1pre;
57 unsigned int mic2pre;
58 struct snd_soc_jack *headphone_jack;
59 struct snd_soc_jack *mic_jack;
60 };
61
62 static const struct reg_default max98095_reg_def[] = {
63 { 0xf, 0x00 }, /* 0F */
64 { 0x10, 0x00 }, /* 10 */
65 { 0x11, 0x00 }, /* 11 */
66 { 0x12, 0x00 }, /* 12 */
67 { 0x13, 0x00 }, /* 13 */
68 { 0x14, 0x00 }, /* 14 */
69 { 0x15, 0x00 }, /* 15 */
70 { 0x16, 0x00 }, /* 16 */
71 { 0x17, 0x00 }, /* 17 */
72 { 0x18, 0x00 }, /* 18 */
73 { 0x19, 0x00 }, /* 19 */
74 { 0x1a, 0x00 }, /* 1A */
75 { 0x1b, 0x00 }, /* 1B */
76 { 0x1c, 0x00 }, /* 1C */
77 { 0x1d, 0x00 }, /* 1D */
78 { 0x1e, 0x00 }, /* 1E */
79 { 0x1f, 0x00 }, /* 1F */
80 { 0x20, 0x00 }, /* 20 */
81 { 0x21, 0x00 }, /* 21 */
82 { 0x22, 0x00 }, /* 22 */
83 { 0x23, 0x00 }, /* 23 */
84 { 0x24, 0x00 }, /* 24 */
85 { 0x25, 0x00 }, /* 25 */
86 { 0x26, 0x00 }, /* 26 */
87 { 0x27, 0x00 }, /* 27 */
88 { 0x28, 0x00 }, /* 28 */
89 { 0x29, 0x00 }, /* 29 */
90 { 0x2a, 0x00 }, /* 2A */
91 { 0x2b, 0x00 }, /* 2B */
92 { 0x2c, 0x00 }, /* 2C */
93 { 0x2d, 0x00 }, /* 2D */
94 { 0x2e, 0x00 }, /* 2E */
95 { 0x2f, 0x00 }, /* 2F */
96 { 0x30, 0x00 }, /* 30 */
97 { 0x31, 0x00 }, /* 31 */
98 { 0x32, 0x00 }, /* 32 */
99 { 0x33, 0x00 }, /* 33 */
100 { 0x34, 0x00 }, /* 34 */
101 { 0x35, 0x00 }, /* 35 */
102 { 0x36, 0x00 }, /* 36 */
103 { 0x37, 0x00 }, /* 37 */
104 { 0x38, 0x00 }, /* 38 */
105 { 0x39, 0x00 }, /* 39 */
106 { 0x3a, 0x00 }, /* 3A */
107 { 0x3b, 0x00 }, /* 3B */
108 { 0x3c, 0x00 }, /* 3C */
109 { 0x3d, 0x00 }, /* 3D */
110 { 0x3e, 0x00 }, /* 3E */
111 { 0x3f, 0x00 }, /* 3F */
112 { 0x40, 0x00 }, /* 40 */
113 { 0x41, 0x00 }, /* 41 */
114 { 0x42, 0x00 }, /* 42 */
115 { 0x43, 0x00 }, /* 43 */
116 { 0x44, 0x00 }, /* 44 */
117 { 0x45, 0x00 }, /* 45 */
118 { 0x46, 0x00 }, /* 46 */
119 { 0x47, 0x00 }, /* 47 */
120 { 0x48, 0x00 }, /* 48 */
121 { 0x49, 0x00 }, /* 49 */
122 { 0x4a, 0x00 }, /* 4A */
123 { 0x4b, 0x00 }, /* 4B */
124 { 0x4c, 0x00 }, /* 4C */
125 { 0x4d, 0x00 }, /* 4D */
126 { 0x4e, 0x00 }, /* 4E */
127 { 0x4f, 0x00 }, /* 4F */
128 { 0x50, 0x00 }, /* 50 */
129 { 0x51, 0x00 }, /* 51 */
130 { 0x52, 0x00 }, /* 52 */
131 { 0x53, 0x00 }, /* 53 */
132 { 0x54, 0x00 }, /* 54 */
133 { 0x55, 0x00 }, /* 55 */
134 { 0x56, 0x00 }, /* 56 */
135 { 0x57, 0x00 }, /* 57 */
136 { 0x58, 0x00 }, /* 58 */
137 { 0x59, 0x00 }, /* 59 */
138 { 0x5a, 0x00 }, /* 5A */
139 { 0x5b, 0x00 }, /* 5B */
140 { 0x5c, 0x00 }, /* 5C */
141 { 0x5d, 0x00 }, /* 5D */
142 { 0x5e, 0x00 }, /* 5E */
143 { 0x5f, 0x00 }, /* 5F */
144 { 0x60, 0x00 }, /* 60 */
145 { 0x61, 0x00 }, /* 61 */
146 { 0x62, 0x00 }, /* 62 */
147 { 0x63, 0x00 }, /* 63 */
148 { 0x64, 0x00 }, /* 64 */
149 { 0x65, 0x00 }, /* 65 */
150 { 0x66, 0x00 }, /* 66 */
151 { 0x67, 0x00 }, /* 67 */
152 { 0x68, 0x00 }, /* 68 */
153 { 0x69, 0x00 }, /* 69 */
154 { 0x6a, 0x00 }, /* 6A */
155 { 0x6b, 0x00 }, /* 6B */
156 { 0x6c, 0x00 }, /* 6C */
157 { 0x6d, 0x00 }, /* 6D */
158 { 0x6e, 0x00 }, /* 6E */
159 { 0x6f, 0x00 }, /* 6F */
160 { 0x70, 0x00 }, /* 70 */
161 { 0x71, 0x00 }, /* 71 */
162 { 0x72, 0x00 }, /* 72 */
163 { 0x73, 0x00 }, /* 73 */
164 { 0x74, 0x00 }, /* 74 */
165 { 0x75, 0x00 }, /* 75 */
166 { 0x76, 0x00 }, /* 76 */
167 { 0x77, 0x00 }, /* 77 */
168 { 0x78, 0x00 }, /* 78 */
169 { 0x79, 0x00 }, /* 79 */
170 { 0x7a, 0x00 }, /* 7A */
171 { 0x7b, 0x00 }, /* 7B */
172 { 0x7c, 0x00 }, /* 7C */
173 { 0x7d, 0x00 }, /* 7D */
174 { 0x7e, 0x00 }, /* 7E */
175 { 0x7f, 0x00 }, /* 7F */
176 { 0x80, 0x00 }, /* 80 */
177 { 0x81, 0x00 }, /* 81 */
178 { 0x82, 0x00 }, /* 82 */
179 { 0x83, 0x00 }, /* 83 */
180 { 0x84, 0x00 }, /* 84 */
181 { 0x85, 0x00 }, /* 85 */
182 { 0x86, 0x00 }, /* 86 */
183 { 0x87, 0x00 }, /* 87 */
184 { 0x88, 0x00 }, /* 88 */
185 { 0x89, 0x00 }, /* 89 */
186 { 0x8a, 0x00 }, /* 8A */
187 { 0x8b, 0x00 }, /* 8B */
188 { 0x8c, 0x00 }, /* 8C */
189 { 0x8d, 0x00 }, /* 8D */
190 { 0x8e, 0x00 }, /* 8E */
191 { 0x8f, 0x00 }, /* 8F */
192 { 0x90, 0x00 }, /* 90 */
193 { 0x91, 0x00 }, /* 91 */
194 { 0x92, 0x30 }, /* 92 */
195 { 0x93, 0xF0 }, /* 93 */
196 { 0x94, 0x00 }, /* 94 */
197 { 0x95, 0x00 }, /* 95 */
198 { 0x96, 0x3F }, /* 96 */
199 { 0x97, 0x00 }, /* 97 */
200 { 0xff, 0x00 }, /* FF */
201 };
202
203 static struct {
204 int readable;
205 int writable;
206 } max98095_access[M98095_REG_CNT] = {
207 { 0x00, 0x00 }, /* 00 */
208 { 0xFF, 0x00 }, /* 01 */
209 { 0xFF, 0x00 }, /* 02 */
210 { 0xFF, 0x00 }, /* 03 */
211 { 0xFF, 0x00 }, /* 04 */
212 { 0xFF, 0x00 }, /* 05 */
213 { 0xFF, 0x00 }, /* 06 */
214 { 0xFF, 0x00 }, /* 07 */
215 { 0xFF, 0x00 }, /* 08 */
216 { 0xFF, 0x00 }, /* 09 */
217 { 0xFF, 0x00 }, /* 0A */
218 { 0xFF, 0x00 }, /* 0B */
219 { 0xFF, 0x00 }, /* 0C */
220 { 0xFF, 0x00 }, /* 0D */
221 { 0xFF, 0x00 }, /* 0E */
222 { 0xFF, 0x9F }, /* 0F */
223 { 0xFF, 0xFF }, /* 10 */
224 { 0xFF, 0xFF }, /* 11 */
225 { 0xFF, 0xFF }, /* 12 */
226 { 0xFF, 0xFF }, /* 13 */
227 { 0xFF, 0xFF }, /* 14 */
228 { 0xFF, 0xFF }, /* 15 */
229 { 0xFF, 0xFF }, /* 16 */
230 { 0xFF, 0xFF }, /* 17 */
231 { 0xFF, 0xFF }, /* 18 */
232 { 0xFF, 0xFF }, /* 19 */
233 { 0xFF, 0xFF }, /* 1A */
234 { 0xFF, 0xFF }, /* 1B */
235 { 0xFF, 0xFF }, /* 1C */
236 { 0xFF, 0xFF }, /* 1D */
237 { 0xFF, 0x77 }, /* 1E */
238 { 0xFF, 0x77 }, /* 1F */
239 { 0xFF, 0x77 }, /* 20 */
240 { 0xFF, 0x77 }, /* 21 */
241 { 0xFF, 0x77 }, /* 22 */
242 { 0xFF, 0x77 }, /* 23 */
243 { 0xFF, 0xFF }, /* 24 */
244 { 0xFF, 0x7F }, /* 25 */
245 { 0xFF, 0x31 }, /* 26 */
246 { 0xFF, 0xFF }, /* 27 */
247 { 0xFF, 0xFF }, /* 28 */
248 { 0xFF, 0xFF }, /* 29 */
249 { 0xFF, 0xF7 }, /* 2A */
250 { 0xFF, 0x2F }, /* 2B */
251 { 0xFF, 0xEF }, /* 2C */
252 { 0xFF, 0xFF }, /* 2D */
253 { 0xFF, 0xFF }, /* 2E */
254 { 0xFF, 0xFF }, /* 2F */
255 { 0xFF, 0xFF }, /* 30 */
256 { 0xFF, 0xFF }, /* 31 */
257 { 0xFF, 0xFF }, /* 32 */
258 { 0xFF, 0xFF }, /* 33 */
259 { 0xFF, 0xF7 }, /* 34 */
260 { 0xFF, 0x2F }, /* 35 */
261 { 0xFF, 0xCF }, /* 36 */
262 { 0xFF, 0xFF }, /* 37 */
263 { 0xFF, 0xFF }, /* 38 */
264 { 0xFF, 0xFF }, /* 39 */
265 { 0xFF, 0xFF }, /* 3A */
266 { 0xFF, 0xFF }, /* 3B */
267 { 0xFF, 0xFF }, /* 3C */
268 { 0xFF, 0xFF }, /* 3D */
269 { 0xFF, 0xF7 }, /* 3E */
270 { 0xFF, 0x2F }, /* 3F */
271 { 0xFF, 0xCF }, /* 40 */
272 { 0xFF, 0xFF }, /* 41 */
273 { 0xFF, 0x77 }, /* 42 */
274 { 0xFF, 0xFF }, /* 43 */
275 { 0xFF, 0xFF }, /* 44 */
276 { 0xFF, 0xFF }, /* 45 */
277 { 0xFF, 0xFF }, /* 46 */
278 { 0xFF, 0xFF }, /* 47 */
279 { 0xFF, 0xFF }, /* 48 */
280 { 0xFF, 0x0F }, /* 49 */
281 { 0xFF, 0xFF }, /* 4A */
282 { 0xFF, 0xFF }, /* 4B */
283 { 0xFF, 0x3F }, /* 4C */
284 { 0xFF, 0x3F }, /* 4D */
285 { 0xFF, 0x3F }, /* 4E */
286 { 0xFF, 0xFF }, /* 4F */
287 { 0xFF, 0x7F }, /* 50 */
288 { 0xFF, 0x7F }, /* 51 */
289 { 0xFF, 0x0F }, /* 52 */
290 { 0xFF, 0x3F }, /* 53 */
291 { 0xFF, 0x3F }, /* 54 */
292 { 0xFF, 0x3F }, /* 55 */
293 { 0xFF, 0xFF }, /* 56 */
294 { 0xFF, 0xFF }, /* 57 */
295 { 0xFF, 0xBF }, /* 58 */
296 { 0xFF, 0x1F }, /* 59 */
297 { 0xFF, 0xBF }, /* 5A */
298 { 0xFF, 0x1F }, /* 5B */
299 { 0xFF, 0xBF }, /* 5C */
300 { 0xFF, 0x3F }, /* 5D */
301 { 0xFF, 0x3F }, /* 5E */
302 { 0xFF, 0x7F }, /* 5F */
303 { 0xFF, 0x7F }, /* 60 */
304 { 0xFF, 0x47 }, /* 61 */
305 { 0xFF, 0x9F }, /* 62 */
306 { 0xFF, 0x9F }, /* 63 */
307 { 0xFF, 0x9F }, /* 64 */
308 { 0xFF, 0x9F }, /* 65 */
309 { 0xFF, 0x9F }, /* 66 */
310 { 0xFF, 0xBF }, /* 67 */
311 { 0xFF, 0xBF }, /* 68 */
312 { 0xFF, 0xFF }, /* 69 */
313 { 0xFF, 0xFF }, /* 6A */
314 { 0xFF, 0x7F }, /* 6B */
315 { 0xFF, 0xF7 }, /* 6C */
316 { 0xFF, 0xFF }, /* 6D */
317 { 0xFF, 0xFF }, /* 6E */
318 { 0xFF, 0x1F }, /* 6F */
319 { 0xFF, 0xF7 }, /* 70 */
320 { 0xFF, 0xFF }, /* 71 */
321 { 0xFF, 0xFF }, /* 72 */
322 { 0xFF, 0x1F }, /* 73 */
323 { 0xFF, 0xF7 }, /* 74 */
324 { 0xFF, 0xFF }, /* 75 */
325 { 0xFF, 0xFF }, /* 76 */
326 { 0xFF, 0x1F }, /* 77 */
327 { 0xFF, 0xF7 }, /* 78 */
328 { 0xFF, 0xFF }, /* 79 */
329 { 0xFF, 0xFF }, /* 7A */
330 { 0xFF, 0x1F }, /* 7B */
331 { 0xFF, 0xF7 }, /* 7C */
332 { 0xFF, 0xFF }, /* 7D */
333 { 0xFF, 0xFF }, /* 7E */
334 { 0xFF, 0x1F }, /* 7F */
335 { 0xFF, 0xF7 }, /* 80 */
336 { 0xFF, 0xFF }, /* 81 */
337 { 0xFF, 0xFF }, /* 82 */
338 { 0xFF, 0x1F }, /* 83 */
339 { 0xFF, 0x7F }, /* 84 */
340 { 0xFF, 0x0F }, /* 85 */
341 { 0xFF, 0xD8 }, /* 86 */
342 { 0xFF, 0xFF }, /* 87 */
343 { 0xFF, 0xEF }, /* 88 */
344 { 0xFF, 0xFE }, /* 89 */
345 { 0xFF, 0xFE }, /* 8A */
346 { 0xFF, 0xFF }, /* 8B */
347 { 0xFF, 0xFF }, /* 8C */
348 { 0xFF, 0x3F }, /* 8D */
349 { 0xFF, 0xFF }, /* 8E */
350 { 0xFF, 0x3F }, /* 8F */
351 { 0xFF, 0x8F }, /* 90 */
352 { 0xFF, 0xFF }, /* 91 */
353 { 0xFF, 0x3F }, /* 92 */
354 { 0xFF, 0xFF }, /* 93 */
355 { 0xFF, 0xFF }, /* 94 */
356 { 0xFF, 0x0F }, /* 95 */
357 { 0xFF, 0x3F }, /* 96 */
358 { 0xFF, 0x8C }, /* 97 */
359 { 0x00, 0x00 }, /* 98 */
360 { 0x00, 0x00 }, /* 99 */
361 { 0x00, 0x00 }, /* 9A */
362 { 0x00, 0x00 }, /* 9B */
363 { 0x00, 0x00 }, /* 9C */
364 { 0x00, 0x00 }, /* 9D */
365 { 0x00, 0x00 }, /* 9E */
366 { 0x00, 0x00 }, /* 9F */
367 { 0x00, 0x00 }, /* A0 */
368 { 0x00, 0x00 }, /* A1 */
369 { 0x00, 0x00 }, /* A2 */
370 { 0x00, 0x00 }, /* A3 */
371 { 0x00, 0x00 }, /* A4 */
372 { 0x00, 0x00 }, /* A5 */
373 { 0x00, 0x00 }, /* A6 */
374 { 0x00, 0x00 }, /* A7 */
375 { 0x00, 0x00 }, /* A8 */
376 { 0x00, 0x00 }, /* A9 */
377 { 0x00, 0x00 }, /* AA */
378 { 0x00, 0x00 }, /* AB */
379 { 0x00, 0x00 }, /* AC */
380 { 0x00, 0x00 }, /* AD */
381 { 0x00, 0x00 }, /* AE */
382 { 0x00, 0x00 }, /* AF */
383 { 0x00, 0x00 }, /* B0 */
384 { 0x00, 0x00 }, /* B1 */
385 { 0x00, 0x00 }, /* B2 */
386 { 0x00, 0x00 }, /* B3 */
387 { 0x00, 0x00 }, /* B4 */
388 { 0x00, 0x00 }, /* B5 */
389 { 0x00, 0x00 }, /* B6 */
390 { 0x00, 0x00 }, /* B7 */
391 { 0x00, 0x00 }, /* B8 */
392 { 0x00, 0x00 }, /* B9 */
393 { 0x00, 0x00 }, /* BA */
394 { 0x00, 0x00 }, /* BB */
395 { 0x00, 0x00 }, /* BC */
396 { 0x00, 0x00 }, /* BD */
397 { 0x00, 0x00 }, /* BE */
398 { 0x00, 0x00 }, /* BF */
399 { 0x00, 0x00 }, /* C0 */
400 { 0x00, 0x00 }, /* C1 */
401 { 0x00, 0x00 }, /* C2 */
402 { 0x00, 0x00 }, /* C3 */
403 { 0x00, 0x00 }, /* C4 */
404 { 0x00, 0x00 }, /* C5 */
405 { 0x00, 0x00 }, /* C6 */
406 { 0x00, 0x00 }, /* C7 */
407 { 0x00, 0x00 }, /* C8 */
408 { 0x00, 0x00 }, /* C9 */
409 { 0x00, 0x00 }, /* CA */
410 { 0x00, 0x00 }, /* CB */
411 { 0x00, 0x00 }, /* CC */
412 { 0x00, 0x00 }, /* CD */
413 { 0x00, 0x00 }, /* CE */
414 { 0x00, 0x00 }, /* CF */
415 { 0x00, 0x00 }, /* D0 */
416 { 0x00, 0x00 }, /* D1 */
417 { 0x00, 0x00 }, /* D2 */
418 { 0x00, 0x00 }, /* D3 */
419 { 0x00, 0x00 }, /* D4 */
420 { 0x00, 0x00 }, /* D5 */
421 { 0x00, 0x00 }, /* D6 */
422 { 0x00, 0x00 }, /* D7 */
423 { 0x00, 0x00 }, /* D8 */
424 { 0x00, 0x00 }, /* D9 */
425 { 0x00, 0x00 }, /* DA */
426 { 0x00, 0x00 }, /* DB */
427 { 0x00, 0x00 }, /* DC */
428 { 0x00, 0x00 }, /* DD */
429 { 0x00, 0x00 }, /* DE */
430 { 0x00, 0x00 }, /* DF */
431 { 0x00, 0x00 }, /* E0 */
432 { 0x00, 0x00 }, /* E1 */
433 { 0x00, 0x00 }, /* E2 */
434 { 0x00, 0x00 }, /* E3 */
435 { 0x00, 0x00 }, /* E4 */
436 { 0x00, 0x00 }, /* E5 */
437 { 0x00, 0x00 }, /* E6 */
438 { 0x00, 0x00 }, /* E7 */
439 { 0x00, 0x00 }, /* E8 */
440 { 0x00, 0x00 }, /* E9 */
441 { 0x00, 0x00 }, /* EA */
442 { 0x00, 0x00 }, /* EB */
443 { 0x00, 0x00 }, /* EC */
444 { 0x00, 0x00 }, /* ED */
445 { 0x00, 0x00 }, /* EE */
446 { 0x00, 0x00 }, /* EF */
447 { 0x00, 0x00 }, /* F0 */
448 { 0x00, 0x00 }, /* F1 */
449 { 0x00, 0x00 }, /* F2 */
450 { 0x00, 0x00 }, /* F3 */
451 { 0x00, 0x00 }, /* F4 */
452 { 0x00, 0x00 }, /* F5 */
453 { 0x00, 0x00 }, /* F6 */
454 { 0x00, 0x00 }, /* F7 */
455 { 0x00, 0x00 }, /* F8 */
456 { 0x00, 0x00 }, /* F9 */
457 { 0x00, 0x00 }, /* FA */
458 { 0x00, 0x00 }, /* FB */
459 { 0x00, 0x00 }, /* FC */
460 { 0x00, 0x00 }, /* FD */
461 { 0x00, 0x00 }, /* FE */
462 { 0xFF, 0x00 }, /* FF */
463 };
464
465 static bool max98095_readable(struct device *dev, unsigned int reg)
466 {
467 if (reg >= M98095_REG_CNT)
468 return 0;
469 return max98095_access[reg].readable != 0;
470 }
471
472 static bool max98095_volatile(struct device *dev, unsigned int reg)
473 {
474 if (reg > M98095_REG_MAX_CACHED)
475 return 1;
476
477 switch (reg) {
478 case M98095_000_HOST_DATA:
479 case M98095_001_HOST_INT_STS:
480 case M98095_002_HOST_RSP_STS:
481 case M98095_003_HOST_CMD_STS:
482 case M98095_004_CODEC_STS:
483 case M98095_005_DAI1_ALC_STS:
484 case M98095_006_DAI2_ALC_STS:
485 case M98095_007_JACK_AUTO_STS:
486 case M98095_008_JACK_MANUAL_STS:
487 case M98095_009_JACK_VBAT_STS:
488 case M98095_00A_ACC_ADC_STS:
489 case M98095_00B_MIC_NG_AGC_STS:
490 case M98095_00C_SPK_L_VOLT_STS:
491 case M98095_00D_SPK_R_VOLT_STS:
492 case M98095_00E_TEMP_SENSOR_STS:
493 return 1;
494 }
495
496 return 0;
497 }
498
499 static const struct regmap_config max98095_regmap = {
500 .reg_bits = 8,
501 .val_bits = 8,
502
503 .reg_defaults = max98095_reg_def,
504 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
505 .max_register = M98095_0FF_REV_ID,
506 .cache_type = REGCACHE_RBTREE,
507
508 .readable_reg = max98095_readable,
509 .volatile_reg = max98095_volatile,
510 };
511
512 /*
513 * Load equalizer DSP coefficient configurations registers
514 */
515 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
516 unsigned int band, u16 *coefs)
517 {
518 unsigned int eq_reg;
519 unsigned int i;
520
521 if (WARN_ON(band > 4) ||
522 WARN_ON(dai > 1))
523 return;
524
525 /* Load the base register address */
526 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
527
528 /* Add the band address offset, note adjustment for word address */
529 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
530
531 /* Step through the registers and coefs */
532 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
533 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
534 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
535 }
536 }
537
538 /*
539 * Load biquad filter coefficient configurations registers
540 */
541 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
542 unsigned int band, u16 *coefs)
543 {
544 unsigned int bq_reg;
545 unsigned int i;
546
547 if (WARN_ON(band > 1) ||
548 WARN_ON(dai > 1))
549 return;
550
551 /* Load the base register address */
552 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
553
554 /* Add the band address offset, note adjustment for word address */
555 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
556
557 /* Step through the registers and coefs */
558 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
559 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
560 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
561 }
562 }
563
564 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
565 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
566 M98095_02E_DAI1_FILTERS, 7,
567 max98095_fltr_mode);
568 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
569 M98095_038_DAI2_FILTERS, 7,
570 max98095_fltr_mode);
571
572 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
573
574 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
575 M98095_087_CFG_MIC, 0,
576 max98095_extmic_text);
577
578 static const struct snd_kcontrol_new max98095_extmic_mux =
579 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
580
581 static const char * const max98095_linein_text[] = { "INA", "INB" };
582
583 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
584 M98095_086_CFG_LINE, 6,
585 max98095_linein_text);
586
587 static const struct snd_kcontrol_new max98095_linein_mux =
588 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
589
590 static const char * const max98095_line_mode_text[] = {
591 "Stereo", "Differential"};
592
593 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
594 M98095_086_CFG_LINE, 7,
595 max98095_line_mode_text);
596
597 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
598 M98095_086_CFG_LINE, 4,
599 max98095_line_mode_text);
600
601 static const char * const max98095_dai_fltr[] = {
602 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
603 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
604 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
605 M98095_02E_DAI1_FILTERS, 0,
606 max98095_dai_fltr);
607 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
608 M98095_038_DAI2_FILTERS, 0,
609 max98095_dai_fltr);
610 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
611 M98095_042_DAI3_FILTERS, 0,
612 max98095_dai_fltr);
613
614 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
615 struct snd_ctl_elem_value *ucontrol)
616 {
617 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
618 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
619 unsigned int sel = ucontrol->value.integer.value[0];
620
621 max98095->mic1pre = sel;
622 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
623 (1+sel)<<M98095_MICPRE_SHIFT);
624
625 return 0;
626 }
627
628 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
629 struct snd_ctl_elem_value *ucontrol)
630 {
631 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
632 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
633
634 ucontrol->value.integer.value[0] = max98095->mic1pre;
635 return 0;
636 }
637
638 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
639 struct snd_ctl_elem_value *ucontrol)
640 {
641 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
642 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
643 unsigned int sel = ucontrol->value.integer.value[0];
644
645 max98095->mic2pre = sel;
646 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
647 (1+sel)<<M98095_MICPRE_SHIFT);
648
649 return 0;
650 }
651
652 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
653 struct snd_ctl_elem_value *ucontrol)
654 {
655 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
656 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
657
658 ucontrol->value.integer.value[0] = max98095->mic2pre;
659 return 0;
660 }
661
662 static const unsigned int max98095_micboost_tlv[] = {
663 TLV_DB_RANGE_HEAD(2),
664 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
665 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
666 };
667
668 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
669 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
670 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
671
672 static const unsigned int max98095_hp_tlv[] = {
673 TLV_DB_RANGE_HEAD(5),
674 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
675 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
676 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
677 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
678 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
679 };
680
681 static const unsigned int max98095_spk_tlv[] = {
682 TLV_DB_RANGE_HEAD(4),
683 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
684 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
685 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
686 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
687 };
688
689 static const unsigned int max98095_rcv_lout_tlv[] = {
690 TLV_DB_RANGE_HEAD(5),
691 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
692 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
693 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
694 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
695 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
696 };
697
698 static const unsigned int max98095_lin_tlv[] = {
699 TLV_DB_RANGE_HEAD(3),
700 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
701 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
702 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
703 };
704
705 static const struct snd_kcontrol_new max98095_snd_controls[] = {
706
707 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
708 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
709
710 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
711 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
712
713 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
714 0, 31, 0, max98095_rcv_lout_tlv),
715
716 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
717 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
718
719 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
720 M98095_065_LVL_HP_R, 7, 1, 1),
721
722 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
723 M98095_068_LVL_SPK_R, 7, 1, 1),
724
725 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
726
727 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
728 M98095_063_LVL_LINEOUT2, 7, 1, 1),
729
730 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
731 max98095_mic_tlv),
732
733 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
734 max98095_mic_tlv),
735
736 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
737 M98095_05F_LVL_MIC1, 5, 2, 0,
738 max98095_mic1pre_get, max98095_mic1pre_set,
739 max98095_micboost_tlv),
740 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
741 M98095_060_LVL_MIC2, 5, 2, 0,
742 max98095_mic2pre_get, max98095_mic2pre_set,
743 max98095_micboost_tlv),
744
745 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
746 max98095_lin_tlv),
747
748 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
749 max98095_adc_tlv),
750 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
751 max98095_adc_tlv),
752
753 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
754 max98095_adcboost_tlv),
755 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
756 max98095_adcboost_tlv),
757
758 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
759 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
760
761 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
762 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
763
764 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
765 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
766 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
767 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
768 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
769
770 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
771 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
772 };
773
774 /* Left speaker mixer switch */
775 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
776 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
777 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
778 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
779 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
780 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
781 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
782 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
783 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
784 };
785
786 /* Right speaker mixer switch */
787 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
788 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
789 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
790 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
791 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
792 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
793 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
794 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
795 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
796 };
797
798 /* Left headphone mixer switch */
799 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
800 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
801 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
802 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
803 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
804 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
805 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
806 };
807
808 /* Right headphone mixer switch */
809 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
810 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
811 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
812 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
813 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
814 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
815 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
816 };
817
818 /* Receiver earpiece mixer switch */
819 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
820 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
821 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
822 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
823 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
824 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
825 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
826 };
827
828 /* Left lineout mixer switch */
829 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
830 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
831 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
832 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
833 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
834 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
835 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
836 };
837
838 /* Right lineout mixer switch */
839 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
840 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
841 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
842 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
843 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
844 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
845 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
846 };
847
848 /* Left ADC mixer switch */
849 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
850 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
851 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
852 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
853 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
854 };
855
856 /* Right ADC mixer switch */
857 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
858 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
859 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
860 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
861 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
862 };
863
864 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
865 struct snd_kcontrol *kcontrol, int event)
866 {
867 struct snd_soc_codec *codec = w->codec;
868 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
869
870 switch (event) {
871 case SND_SOC_DAPM_POST_PMU:
872 if (w->reg == M98095_05F_LVL_MIC1) {
873 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
874 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
875 } else {
876 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
877 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
878 }
879 break;
880 case SND_SOC_DAPM_POST_PMD:
881 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
882 break;
883 default:
884 return -EINVAL;
885 }
886
887 return 0;
888 }
889
890 /*
891 * The line inputs are stereo inputs with the left and right
892 * channels sharing a common PGA power control signal.
893 */
894 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
895 int event, u8 channel)
896 {
897 struct snd_soc_codec *codec = w->codec;
898 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
899 u8 *state;
900
901 if (WARN_ON(!(channel == 1 || channel == 2)))
902 return -EINVAL;
903
904 state = &max98095->lin_state;
905
906 switch (event) {
907 case SND_SOC_DAPM_POST_PMU:
908 *state |= channel;
909 snd_soc_update_bits(codec, w->reg,
910 (1 << w->shift), (1 << w->shift));
911 break;
912 case SND_SOC_DAPM_POST_PMD:
913 *state &= ~channel;
914 if (*state == 0) {
915 snd_soc_update_bits(codec, w->reg,
916 (1 << w->shift), 0);
917 }
918 break;
919 default:
920 return -EINVAL;
921 }
922
923 return 0;
924 }
925
926 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
927 struct snd_kcontrol *k, int event)
928 {
929 return max98095_line_pga(w, event, 1);
930 }
931
932 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *k, int event)
934 {
935 return max98095_line_pga(w, event, 2);
936 }
937
938 /*
939 * The stereo line out mixer outputs to two stereo line outs.
940 * The 2nd pair has a separate set of enables.
941 */
942 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
943 struct snd_kcontrol *kcontrol, int event)
944 {
945 struct snd_soc_codec *codec = w->codec;
946
947 switch (event) {
948 case SND_SOC_DAPM_POST_PMU:
949 snd_soc_update_bits(codec, w->reg,
950 (1 << (w->shift+2)), (1 << (w->shift+2)));
951 break;
952 case SND_SOC_DAPM_POST_PMD:
953 snd_soc_update_bits(codec, w->reg,
954 (1 << (w->shift+2)), 0);
955 break;
956 default:
957 return -EINVAL;
958 }
959
960 return 0;
961 }
962
963 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
964
965 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
966 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
967
968 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
969 M98095_091_PWR_EN_OUT, 0, 0),
970 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
971 M98095_091_PWR_EN_OUT, 1, 0),
972 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
973 M98095_091_PWR_EN_OUT, 2, 0),
974 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
975 M98095_091_PWR_EN_OUT, 2, 0),
976
977 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
978 6, 0, NULL, 0),
979 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
980 7, 0, NULL, 0),
981
982 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
983 4, 0, NULL, 0),
984 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
985 5, 0, NULL, 0),
986
987 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
988 3, 0, NULL, 0),
989
990 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
991 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
992 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
993 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
994
995 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
996 &max98095_extmic_mux),
997
998 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
999 &max98095_linein_mux),
1000
1001 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1002 &max98095_left_hp_mixer_controls[0],
1003 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
1004
1005 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1006 &max98095_right_hp_mixer_controls[0],
1007 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
1008
1009 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1010 &max98095_left_speaker_mixer_controls[0],
1011 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
1012
1013 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1014 &max98095_right_speaker_mixer_controls[0],
1015 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
1016
1017 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
1018 &max98095_mono_rcv_mixer_controls[0],
1019 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
1020
1021 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
1022 &max98095_left_lineout_mixer_controls[0],
1023 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
1024
1025 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
1026 &max98095_right_lineout_mixer_controls[0],
1027 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
1028
1029 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1030 &max98095_left_ADC_mixer_controls[0],
1031 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
1032
1033 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1034 &max98095_right_ADC_mixer_controls[0],
1035 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
1036
1037 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
1038 5, 0, NULL, 0, max98095_mic_event,
1039 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1040
1041 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
1042 5, 0, NULL, 0, max98095_mic_event,
1043 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1044
1045 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
1046 7, 0, NULL, 0, max98095_pga_in1_event,
1047 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1048
1049 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
1050 7, 0, NULL, 0, max98095_pga_in2_event,
1051 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1052
1053 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
1054 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
1055
1056 SND_SOC_DAPM_OUTPUT("HPL"),
1057 SND_SOC_DAPM_OUTPUT("HPR"),
1058 SND_SOC_DAPM_OUTPUT("SPKL"),
1059 SND_SOC_DAPM_OUTPUT("SPKR"),
1060 SND_SOC_DAPM_OUTPUT("RCV"),
1061 SND_SOC_DAPM_OUTPUT("OUT1"),
1062 SND_SOC_DAPM_OUTPUT("OUT2"),
1063 SND_SOC_DAPM_OUTPUT("OUT3"),
1064 SND_SOC_DAPM_OUTPUT("OUT4"),
1065
1066 SND_SOC_DAPM_INPUT("MIC1"),
1067 SND_SOC_DAPM_INPUT("MIC2"),
1068 SND_SOC_DAPM_INPUT("INA1"),
1069 SND_SOC_DAPM_INPUT("INA2"),
1070 SND_SOC_DAPM_INPUT("INB1"),
1071 SND_SOC_DAPM_INPUT("INB2"),
1072 };
1073
1074 static const struct snd_soc_dapm_route max98095_audio_map[] = {
1075 /* Left headphone output mixer */
1076 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1077 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1078 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1079 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1080 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
1081 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
1082
1083 /* Right headphone output mixer */
1084 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1085 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1086 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1087 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1088 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
1089 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
1090
1091 /* Left speaker output mixer */
1092 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1093 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1094 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1095 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1096 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1097 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1098 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
1099 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
1100
1101 /* Right speaker output mixer */
1102 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1103 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1104 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1105 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1106 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1107 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1108 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
1109 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
1110
1111 /* Earpiece/Receiver output mixer */
1112 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
1113 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
1114 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1115 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1116 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
1117 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
1118
1119 /* Left Lineout output mixer */
1120 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1121 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1122 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1123 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1124 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
1125 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
1126
1127 /* Right lineout output mixer */
1128 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1129 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1130 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1131 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1132 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
1133 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
1134
1135 {"HP Left Out", NULL, "Left Headphone Mixer"},
1136 {"HP Right Out", NULL, "Right Headphone Mixer"},
1137 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1138 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1139 {"RCV Mono Out", NULL, "Receiver Mixer"},
1140 {"LINE Left Out", NULL, "Left Lineout Mixer"},
1141 {"LINE Right Out", NULL, "Right Lineout Mixer"},
1142
1143 {"HPL", NULL, "HP Left Out"},
1144 {"HPR", NULL, "HP Right Out"},
1145 {"SPKL", NULL, "SPK Left Out"},
1146 {"SPKR", NULL, "SPK Right Out"},
1147 {"RCV", NULL, "RCV Mono Out"},
1148 {"OUT1", NULL, "LINE Left Out"},
1149 {"OUT2", NULL, "LINE Right Out"},
1150 {"OUT3", NULL, "LINE Left Out"},
1151 {"OUT4", NULL, "LINE Right Out"},
1152
1153 /* Left ADC input mixer */
1154 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1155 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1156 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
1157 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
1158
1159 /* Right ADC input mixer */
1160 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1161 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1162 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
1163 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
1164
1165 /* Inputs */
1166 {"ADCL", NULL, "Left ADC Mixer"},
1167 {"ADCR", NULL, "Right ADC Mixer"},
1168
1169 {"IN1 Input", NULL, "INA1"},
1170 {"IN2 Input", NULL, "INA2"},
1171
1172 {"MIC1 Input", NULL, "MIC1"},
1173 {"MIC2 Input", NULL, "MIC2"},
1174 };
1175
1176 /* codec mclk clock divider coefficients */
1177 static const struct {
1178 u32 rate;
1179 u8 sr;
1180 } rate_table[] = {
1181 {8000, 0x01},
1182 {11025, 0x02},
1183 {16000, 0x03},
1184 {22050, 0x04},
1185 {24000, 0x05},
1186 {32000, 0x06},
1187 {44100, 0x07},
1188 {48000, 0x08},
1189 {88200, 0x09},
1190 {96000, 0x0A},
1191 };
1192
1193 static int rate_value(int rate, u8 *value)
1194 {
1195 int i;
1196
1197 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1198 if (rate_table[i].rate >= rate) {
1199 *value = rate_table[i].sr;
1200 return 0;
1201 }
1202 }
1203 *value = rate_table[0].sr;
1204 return -EINVAL;
1205 }
1206
1207 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
1208 struct snd_pcm_hw_params *params,
1209 struct snd_soc_dai *dai)
1210 {
1211 struct snd_soc_codec *codec = dai->codec;
1212 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1213 struct max98095_cdata *cdata;
1214 unsigned long long ni;
1215 unsigned int rate;
1216 u8 regval;
1217
1218 cdata = &max98095->dai[0];
1219
1220 rate = params_rate(params);
1221
1222 switch (params_width(params)) {
1223 case 16:
1224 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1225 M98095_DAI_WS, 0);
1226 break;
1227 case 24:
1228 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1229 M98095_DAI_WS, M98095_DAI_WS);
1230 break;
1231 default:
1232 return -EINVAL;
1233 }
1234
1235 if (rate_value(rate, &regval))
1236 return -EINVAL;
1237
1238 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
1239 M98095_CLKMODE_MASK, regval);
1240 cdata->rate = rate;
1241
1242 /* Configure NI when operating as master */
1243 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
1244 if (max98095->sysclk == 0) {
1245 dev_err(codec->dev, "Invalid system clock frequency\n");
1246 return -EINVAL;
1247 }
1248 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1249 * (unsigned long long int)rate;
1250 do_div(ni, (unsigned long long int)max98095->sysclk);
1251 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1252 (ni >> 8) & 0x7F);
1253 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1254 ni & 0xFF);
1255 }
1256
1257 /* Update sample rate mode */
1258 if (rate < 50000)
1259 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1260 M98095_DAI_DHF, 0);
1261 else
1262 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1263 M98095_DAI_DHF, M98095_DAI_DHF);
1264
1265 return 0;
1266 }
1267
1268 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1269 struct snd_pcm_hw_params *params,
1270 struct snd_soc_dai *dai)
1271 {
1272 struct snd_soc_codec *codec = dai->codec;
1273 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1274 struct max98095_cdata *cdata;
1275 unsigned long long ni;
1276 unsigned int rate;
1277 u8 regval;
1278
1279 cdata = &max98095->dai[1];
1280
1281 rate = params_rate(params);
1282
1283 switch (params_format(params)) {
1284 case SNDRV_PCM_FORMAT_S16_LE:
1285 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1286 M98095_DAI_WS, 0);
1287 break;
1288 case SNDRV_PCM_FORMAT_S24_LE:
1289 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1290 M98095_DAI_WS, M98095_DAI_WS);
1291 break;
1292 default:
1293 return -EINVAL;
1294 }
1295
1296 if (rate_value(rate, &regval))
1297 return -EINVAL;
1298
1299 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1300 M98095_CLKMODE_MASK, regval);
1301 cdata->rate = rate;
1302
1303 /* Configure NI when operating as master */
1304 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1305 if (max98095->sysclk == 0) {
1306 dev_err(codec->dev, "Invalid system clock frequency\n");
1307 return -EINVAL;
1308 }
1309 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1310 * (unsigned long long int)rate;
1311 do_div(ni, (unsigned long long int)max98095->sysclk);
1312 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1313 (ni >> 8) & 0x7F);
1314 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1315 ni & 0xFF);
1316 }
1317
1318 /* Update sample rate mode */
1319 if (rate < 50000)
1320 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1321 M98095_DAI_DHF, 0);
1322 else
1323 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1324 M98095_DAI_DHF, M98095_DAI_DHF);
1325
1326 return 0;
1327 }
1328
1329 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1330 struct snd_pcm_hw_params *params,
1331 struct snd_soc_dai *dai)
1332 {
1333 struct snd_soc_codec *codec = dai->codec;
1334 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1335 struct max98095_cdata *cdata;
1336 unsigned long long ni;
1337 unsigned int rate;
1338 u8 regval;
1339
1340 cdata = &max98095->dai[2];
1341
1342 rate = params_rate(params);
1343
1344 switch (params_format(params)) {
1345 case SNDRV_PCM_FORMAT_S16_LE:
1346 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1347 M98095_DAI_WS, 0);
1348 break;
1349 case SNDRV_PCM_FORMAT_S24_LE:
1350 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1351 M98095_DAI_WS, M98095_DAI_WS);
1352 break;
1353 default:
1354 return -EINVAL;
1355 }
1356
1357 if (rate_value(rate, &regval))
1358 return -EINVAL;
1359
1360 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1361 M98095_CLKMODE_MASK, regval);
1362 cdata->rate = rate;
1363
1364 /* Configure NI when operating as master */
1365 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1366 if (max98095->sysclk == 0) {
1367 dev_err(codec->dev, "Invalid system clock frequency\n");
1368 return -EINVAL;
1369 }
1370 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1371 * (unsigned long long int)rate;
1372 do_div(ni, (unsigned long long int)max98095->sysclk);
1373 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1374 (ni >> 8) & 0x7F);
1375 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1376 ni & 0xFF);
1377 }
1378
1379 /* Update sample rate mode */
1380 if (rate < 50000)
1381 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1382 M98095_DAI_DHF, 0);
1383 else
1384 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1385 M98095_DAI_DHF, M98095_DAI_DHF);
1386
1387 return 0;
1388 }
1389
1390 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1391 int clk_id, unsigned int freq, int dir)
1392 {
1393 struct snd_soc_codec *codec = dai->codec;
1394 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1395
1396 /* Requested clock frequency is already setup */
1397 if (freq == max98095->sysclk)
1398 return 0;
1399
1400 if (!IS_ERR(max98095->mclk)) {
1401 freq = clk_round_rate(max98095->mclk, freq);
1402 clk_set_rate(max98095->mclk, freq);
1403 }
1404
1405 /* Setup clocks for slave mode, and using the PLL
1406 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1407 * 0x02 (when master clk is 20MHz to 40MHz)..
1408 * 0x03 (when master clk is 40MHz to 60MHz)..
1409 */
1410 if ((freq >= 10000000) && (freq < 20000000)) {
1411 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1412 } else if ((freq >= 20000000) && (freq < 40000000)) {
1413 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1414 } else if ((freq >= 40000000) && (freq < 60000000)) {
1415 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1416 } else {
1417 dev_err(codec->dev, "Invalid master clock frequency\n");
1418 return -EINVAL;
1419 }
1420
1421 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1422
1423 max98095->sysclk = freq;
1424 return 0;
1425 }
1426
1427 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1428 unsigned int fmt)
1429 {
1430 struct snd_soc_codec *codec = codec_dai->codec;
1431 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1432 struct max98095_cdata *cdata;
1433 u8 regval = 0;
1434
1435 cdata = &max98095->dai[0];
1436
1437 if (fmt != cdata->fmt) {
1438 cdata->fmt = fmt;
1439
1440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1441 case SND_SOC_DAIFMT_CBS_CFS:
1442 /* Slave mode PLL */
1443 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1444 0x80);
1445 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1446 0x00);
1447 break;
1448 case SND_SOC_DAIFMT_CBM_CFM:
1449 /* Set to master mode */
1450 regval |= M98095_DAI_MAS;
1451 break;
1452 case SND_SOC_DAIFMT_CBS_CFM:
1453 case SND_SOC_DAIFMT_CBM_CFS:
1454 default:
1455 dev_err(codec->dev, "Clock mode unsupported");
1456 return -EINVAL;
1457 }
1458
1459 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1460 case SND_SOC_DAIFMT_I2S:
1461 regval |= M98095_DAI_DLY;
1462 break;
1463 case SND_SOC_DAIFMT_LEFT_J:
1464 break;
1465 default:
1466 return -EINVAL;
1467 }
1468
1469 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1470 case SND_SOC_DAIFMT_NB_NF:
1471 break;
1472 case SND_SOC_DAIFMT_NB_IF:
1473 regval |= M98095_DAI_WCI;
1474 break;
1475 case SND_SOC_DAIFMT_IB_NF:
1476 regval |= M98095_DAI_BCI;
1477 break;
1478 case SND_SOC_DAIFMT_IB_IF:
1479 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1480 break;
1481 default:
1482 return -EINVAL;
1483 }
1484
1485 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1486 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1487 M98095_DAI_WCI, regval);
1488
1489 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1490 }
1491
1492 return 0;
1493 }
1494
1495 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1496 unsigned int fmt)
1497 {
1498 struct snd_soc_codec *codec = codec_dai->codec;
1499 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1500 struct max98095_cdata *cdata;
1501 u8 regval = 0;
1502
1503 cdata = &max98095->dai[1];
1504
1505 if (fmt != cdata->fmt) {
1506 cdata->fmt = fmt;
1507
1508 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1509 case SND_SOC_DAIFMT_CBS_CFS:
1510 /* Slave mode PLL */
1511 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1512 0x80);
1513 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1514 0x00);
1515 break;
1516 case SND_SOC_DAIFMT_CBM_CFM:
1517 /* Set to master mode */
1518 regval |= M98095_DAI_MAS;
1519 break;
1520 case SND_SOC_DAIFMT_CBS_CFM:
1521 case SND_SOC_DAIFMT_CBM_CFS:
1522 default:
1523 dev_err(codec->dev, "Clock mode unsupported");
1524 return -EINVAL;
1525 }
1526
1527 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1528 case SND_SOC_DAIFMT_I2S:
1529 regval |= M98095_DAI_DLY;
1530 break;
1531 case SND_SOC_DAIFMT_LEFT_J:
1532 break;
1533 default:
1534 return -EINVAL;
1535 }
1536
1537 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1538 case SND_SOC_DAIFMT_NB_NF:
1539 break;
1540 case SND_SOC_DAIFMT_NB_IF:
1541 regval |= M98095_DAI_WCI;
1542 break;
1543 case SND_SOC_DAIFMT_IB_NF:
1544 regval |= M98095_DAI_BCI;
1545 break;
1546 case SND_SOC_DAIFMT_IB_IF:
1547 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1548 break;
1549 default:
1550 return -EINVAL;
1551 }
1552
1553 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1554 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1555 M98095_DAI_WCI, regval);
1556
1557 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1558 M98095_DAI_BSEL64);
1559 }
1560
1561 return 0;
1562 }
1563
1564 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1565 unsigned int fmt)
1566 {
1567 struct snd_soc_codec *codec = codec_dai->codec;
1568 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1569 struct max98095_cdata *cdata;
1570 u8 regval = 0;
1571
1572 cdata = &max98095->dai[2];
1573
1574 if (fmt != cdata->fmt) {
1575 cdata->fmt = fmt;
1576
1577 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1578 case SND_SOC_DAIFMT_CBS_CFS:
1579 /* Slave mode PLL */
1580 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1581 0x80);
1582 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1583 0x00);
1584 break;
1585 case SND_SOC_DAIFMT_CBM_CFM:
1586 /* Set to master mode */
1587 regval |= M98095_DAI_MAS;
1588 break;
1589 case SND_SOC_DAIFMT_CBS_CFM:
1590 case SND_SOC_DAIFMT_CBM_CFS:
1591 default:
1592 dev_err(codec->dev, "Clock mode unsupported");
1593 return -EINVAL;
1594 }
1595
1596 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1597 case SND_SOC_DAIFMT_I2S:
1598 regval |= M98095_DAI_DLY;
1599 break;
1600 case SND_SOC_DAIFMT_LEFT_J:
1601 break;
1602 default:
1603 return -EINVAL;
1604 }
1605
1606 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1607 case SND_SOC_DAIFMT_NB_NF:
1608 break;
1609 case SND_SOC_DAIFMT_NB_IF:
1610 regval |= M98095_DAI_WCI;
1611 break;
1612 case SND_SOC_DAIFMT_IB_NF:
1613 regval |= M98095_DAI_BCI;
1614 break;
1615 case SND_SOC_DAIFMT_IB_IF:
1616 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1617 break;
1618 default:
1619 return -EINVAL;
1620 }
1621
1622 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1623 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1624 M98095_DAI_WCI, regval);
1625
1626 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1627 M98095_DAI_BSEL64);
1628 }
1629
1630 return 0;
1631 }
1632
1633 static int max98095_set_bias_level(struct snd_soc_codec *codec,
1634 enum snd_soc_bias_level level)
1635 {
1636 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1637 int ret;
1638
1639 switch (level) {
1640 case SND_SOC_BIAS_ON:
1641 break;
1642
1643 case SND_SOC_BIAS_PREPARE:
1644 /*
1645 * SND_SOC_BIAS_PREPARE is called while preparing for a
1646 * transition to ON or away from ON. If current bias_level
1647 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1648 * away from ON. Disable the clock in that case, otherwise
1649 * enable it.
1650 */
1651 if (!IS_ERR(max98095->mclk)) {
1652 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
1653 clk_disable_unprepare(max98095->mclk);
1654 else
1655 clk_prepare_enable(max98095->mclk);
1656 }
1657 break;
1658
1659 case SND_SOC_BIAS_STANDBY:
1660 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1661 ret = regcache_sync(max98095->regmap);
1662
1663 if (ret != 0) {
1664 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1665 return ret;
1666 }
1667 }
1668
1669 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1670 M98095_MBEN, M98095_MBEN);
1671 break;
1672
1673 case SND_SOC_BIAS_OFF:
1674 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1675 M98095_MBEN, 0);
1676 regcache_mark_dirty(max98095->regmap);
1677 break;
1678 }
1679 codec->dapm.bias_level = level;
1680 return 0;
1681 }
1682
1683 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1684 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1685
1686 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1687 .set_sysclk = max98095_dai_set_sysclk,
1688 .set_fmt = max98095_dai1_set_fmt,
1689 .hw_params = max98095_dai1_hw_params,
1690 };
1691
1692 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1693 .set_sysclk = max98095_dai_set_sysclk,
1694 .set_fmt = max98095_dai2_set_fmt,
1695 .hw_params = max98095_dai2_hw_params,
1696 };
1697
1698 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1699 .set_sysclk = max98095_dai_set_sysclk,
1700 .set_fmt = max98095_dai3_set_fmt,
1701 .hw_params = max98095_dai3_hw_params,
1702 };
1703
1704 static struct snd_soc_dai_driver max98095_dai[] = {
1705 {
1706 .name = "HiFi",
1707 .playback = {
1708 .stream_name = "HiFi Playback",
1709 .channels_min = 1,
1710 .channels_max = 2,
1711 .rates = MAX98095_RATES,
1712 .formats = MAX98095_FORMATS,
1713 },
1714 .capture = {
1715 .stream_name = "HiFi Capture",
1716 .channels_min = 1,
1717 .channels_max = 2,
1718 .rates = MAX98095_RATES,
1719 .formats = MAX98095_FORMATS,
1720 },
1721 .ops = &max98095_dai1_ops,
1722 },
1723 {
1724 .name = "Aux",
1725 .playback = {
1726 .stream_name = "Aux Playback",
1727 .channels_min = 1,
1728 .channels_max = 1,
1729 .rates = MAX98095_RATES,
1730 .formats = MAX98095_FORMATS,
1731 },
1732 .ops = &max98095_dai2_ops,
1733 },
1734 {
1735 .name = "Voice",
1736 .playback = {
1737 .stream_name = "Voice Playback",
1738 .channels_min = 1,
1739 .channels_max = 1,
1740 .rates = MAX98095_RATES,
1741 .formats = MAX98095_FORMATS,
1742 },
1743 .ops = &max98095_dai3_ops,
1744 }
1745
1746 };
1747
1748 static int max98095_get_eq_channel(const char *name)
1749 {
1750 if (strcmp(name, "EQ1 Mode") == 0)
1751 return 0;
1752 if (strcmp(name, "EQ2 Mode") == 0)
1753 return 1;
1754 return -EINVAL;
1755 }
1756
1757 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1758 struct snd_ctl_elem_value *ucontrol)
1759 {
1760 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1761 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1762 struct max98095_pdata *pdata = max98095->pdata;
1763 int channel = max98095_get_eq_channel(kcontrol->id.name);
1764 struct max98095_cdata *cdata;
1765 unsigned int sel = ucontrol->value.integer.value[0];
1766 struct max98095_eq_cfg *coef_set;
1767 int fs, best, best_val, i;
1768 int regmask, regsave;
1769
1770 if (WARN_ON(channel > 1))
1771 return -EINVAL;
1772
1773 if (!pdata || !max98095->eq_textcnt)
1774 return 0;
1775
1776 if (sel >= pdata->eq_cfgcnt)
1777 return -EINVAL;
1778
1779 cdata = &max98095->dai[channel];
1780 cdata->eq_sel = sel;
1781 fs = cdata->rate;
1782
1783 /* Find the selected configuration with nearest sample rate */
1784 best = 0;
1785 best_val = INT_MAX;
1786 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1787 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1788 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1789 best = i;
1790 best_val = abs(pdata->eq_cfg[i].rate - fs);
1791 }
1792 }
1793
1794 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1795 pdata->eq_cfg[best].name,
1796 pdata->eq_cfg[best].rate, fs);
1797
1798 coef_set = &pdata->eq_cfg[best];
1799
1800 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1801
1802 /* Disable filter while configuring, and save current on/off state */
1803 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1804 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1805
1806 mutex_lock(&codec->mutex);
1807 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1808 m98095_eq_band(codec, channel, 0, coef_set->band1);
1809 m98095_eq_band(codec, channel, 1, coef_set->band2);
1810 m98095_eq_band(codec, channel, 2, coef_set->band3);
1811 m98095_eq_band(codec, channel, 3, coef_set->band4);
1812 m98095_eq_band(codec, channel, 4, coef_set->band5);
1813 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1814 mutex_unlock(&codec->mutex);
1815
1816 /* Restore the original on/off state */
1817 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1818 return 0;
1819 }
1820
1821 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1822 struct snd_ctl_elem_value *ucontrol)
1823 {
1824 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1825 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1826 int channel = max98095_get_eq_channel(kcontrol->id.name);
1827 struct max98095_cdata *cdata;
1828
1829 cdata = &max98095->dai[channel];
1830 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1831
1832 return 0;
1833 }
1834
1835 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
1836 {
1837 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1838 struct max98095_pdata *pdata = max98095->pdata;
1839 struct max98095_eq_cfg *cfg;
1840 unsigned int cfgcnt;
1841 int i, j;
1842 const char **t;
1843 int ret;
1844
1845 struct snd_kcontrol_new controls[] = {
1846 SOC_ENUM_EXT("EQ1 Mode",
1847 max98095->eq_enum,
1848 max98095_get_eq_enum,
1849 max98095_put_eq_enum),
1850 SOC_ENUM_EXT("EQ2 Mode",
1851 max98095->eq_enum,
1852 max98095_get_eq_enum,
1853 max98095_put_eq_enum),
1854 };
1855
1856 cfg = pdata->eq_cfg;
1857 cfgcnt = pdata->eq_cfgcnt;
1858
1859 /* Setup an array of texts for the equalizer enum.
1860 * This is based on Mark Brown's equalizer driver code.
1861 */
1862 max98095->eq_textcnt = 0;
1863 max98095->eq_texts = NULL;
1864 for (i = 0; i < cfgcnt; i++) {
1865 for (j = 0; j < max98095->eq_textcnt; j++) {
1866 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1867 break;
1868 }
1869
1870 if (j != max98095->eq_textcnt)
1871 continue;
1872
1873 /* Expand the array */
1874 t = krealloc(max98095->eq_texts,
1875 sizeof(char *) * (max98095->eq_textcnt + 1),
1876 GFP_KERNEL);
1877 if (t == NULL)
1878 continue;
1879
1880 /* Store the new entry */
1881 t[max98095->eq_textcnt] = cfg[i].name;
1882 max98095->eq_textcnt++;
1883 max98095->eq_texts = t;
1884 }
1885
1886 /* Now point the soc_enum to .texts array items */
1887 max98095->eq_enum.texts = max98095->eq_texts;
1888 max98095->eq_enum.items = max98095->eq_textcnt;
1889
1890 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
1891 if (ret != 0)
1892 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1893 }
1894
1895 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1896
1897 static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1898 const char *name)
1899 {
1900 int i;
1901
1902 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++)
1903 if (strcmp(name, bq_mode_name[i]) == 0)
1904 return i;
1905
1906 /* Shouldn't happen */
1907 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name);
1908 return -EINVAL;
1909 }
1910
1911 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1912 struct snd_ctl_elem_value *ucontrol)
1913 {
1914 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1915 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1916 struct max98095_pdata *pdata = max98095->pdata;
1917 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
1918 struct max98095_cdata *cdata;
1919 unsigned int sel = ucontrol->value.integer.value[0];
1920 struct max98095_biquad_cfg *coef_set;
1921 int fs, best, best_val, i;
1922 int regmask, regsave;
1923
1924 if (channel < 0)
1925 return channel;
1926
1927 if (!pdata || !max98095->bq_textcnt)
1928 return 0;
1929
1930 if (sel >= pdata->bq_cfgcnt)
1931 return -EINVAL;
1932
1933 cdata = &max98095->dai[channel];
1934 cdata->bq_sel = sel;
1935 fs = cdata->rate;
1936
1937 /* Find the selected configuration with nearest sample rate */
1938 best = 0;
1939 best_val = INT_MAX;
1940 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1941 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1942 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1943 best = i;
1944 best_val = abs(pdata->bq_cfg[i].rate - fs);
1945 }
1946 }
1947
1948 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1949 pdata->bq_cfg[best].name,
1950 pdata->bq_cfg[best].rate, fs);
1951
1952 coef_set = &pdata->bq_cfg[best];
1953
1954 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1955
1956 /* Disable filter while configuring, and save current on/off state */
1957 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1958 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1959
1960 mutex_lock(&codec->mutex);
1961 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1962 m98095_biquad_band(codec, channel, 0, coef_set->band1);
1963 m98095_biquad_band(codec, channel, 1, coef_set->band2);
1964 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1965 mutex_unlock(&codec->mutex);
1966
1967 /* Restore the original on/off state */
1968 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1969 return 0;
1970 }
1971
1972 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1973 struct snd_ctl_elem_value *ucontrol)
1974 {
1975 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1976 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1977 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
1978 struct max98095_cdata *cdata;
1979
1980 if (channel < 0)
1981 return channel;
1982
1983 cdata = &max98095->dai[channel];
1984 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1985
1986 return 0;
1987 }
1988
1989 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
1990 {
1991 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1992 struct max98095_pdata *pdata = max98095->pdata;
1993 struct max98095_biquad_cfg *cfg;
1994 unsigned int cfgcnt;
1995 int i, j;
1996 const char **t;
1997 int ret;
1998
1999 struct snd_kcontrol_new controls[] = {
2000 SOC_ENUM_EXT((char *)bq_mode_name[0],
2001 max98095->bq_enum,
2002 max98095_get_bq_enum,
2003 max98095_put_bq_enum),
2004 SOC_ENUM_EXT((char *)bq_mode_name[1],
2005 max98095->bq_enum,
2006 max98095_get_bq_enum,
2007 max98095_put_bq_enum),
2008 };
2009 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
2010
2011 cfg = pdata->bq_cfg;
2012 cfgcnt = pdata->bq_cfgcnt;
2013
2014 /* Setup an array of texts for the biquad enum.
2015 * This is based on Mark Brown's equalizer driver code.
2016 */
2017 max98095->bq_textcnt = 0;
2018 max98095->bq_texts = NULL;
2019 for (i = 0; i < cfgcnt; i++) {
2020 for (j = 0; j < max98095->bq_textcnt; j++) {
2021 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
2022 break;
2023 }
2024
2025 if (j != max98095->bq_textcnt)
2026 continue;
2027
2028 /* Expand the array */
2029 t = krealloc(max98095->bq_texts,
2030 sizeof(char *) * (max98095->bq_textcnt + 1),
2031 GFP_KERNEL);
2032 if (t == NULL)
2033 continue;
2034
2035 /* Store the new entry */
2036 t[max98095->bq_textcnt] = cfg[i].name;
2037 max98095->bq_textcnt++;
2038 max98095->bq_texts = t;
2039 }
2040
2041 /* Now point the soc_enum to .texts array items */
2042 max98095->bq_enum.texts = max98095->bq_texts;
2043 max98095->bq_enum.items = max98095->bq_textcnt;
2044
2045 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2046 if (ret != 0)
2047 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
2048 }
2049
2050 static void max98095_handle_pdata(struct snd_soc_codec *codec)
2051 {
2052 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2053 struct max98095_pdata *pdata = max98095->pdata;
2054 u8 regval = 0;
2055
2056 if (!pdata) {
2057 dev_dbg(codec->dev, "No platform data\n");
2058 return;
2059 }
2060
2061 /* Configure mic for analog/digital mic mode */
2062 if (pdata->digmic_left_mode)
2063 regval |= M98095_DIGMIC_L;
2064
2065 if (pdata->digmic_right_mode)
2066 regval |= M98095_DIGMIC_R;
2067
2068 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
2069
2070 /* Configure equalizers */
2071 if (pdata->eq_cfgcnt)
2072 max98095_handle_eq_pdata(codec);
2073
2074 /* Configure bi-quad filters */
2075 if (pdata->bq_cfgcnt)
2076 max98095_handle_bq_pdata(codec);
2077 }
2078
2079 static irqreturn_t max98095_report_jack(int irq, void *data)
2080 {
2081 struct snd_soc_codec *codec = data;
2082 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2083 unsigned int value;
2084 int hp_report = 0;
2085 int mic_report = 0;
2086
2087 /* Read the Jack Status Register */
2088 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
2089
2090 /* If ddone is not set, then detection isn't finished yet */
2091 if ((value & M98095_DDONE) == 0)
2092 return IRQ_NONE;
2093
2094 /* if hp, check its bit, and if set, clear it */
2095 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
2096 max98095->headphone_jack)
2097 hp_report |= SND_JACK_HEADPHONE;
2098
2099 /* if mic, check its bit, and if set, clear it */
2100 if ((value & M98095_MIC_IN) && max98095->mic_jack)
2101 mic_report |= SND_JACK_MICROPHONE;
2102
2103 if (max98095->headphone_jack == max98095->mic_jack) {
2104 snd_soc_jack_report(max98095->headphone_jack,
2105 hp_report | mic_report,
2106 SND_JACK_HEADSET);
2107 } else {
2108 if (max98095->headphone_jack)
2109 snd_soc_jack_report(max98095->headphone_jack,
2110 hp_report, SND_JACK_HEADPHONE);
2111 if (max98095->mic_jack)
2112 snd_soc_jack_report(max98095->mic_jack,
2113 mic_report, SND_JACK_MICROPHONE);
2114 }
2115
2116 return IRQ_HANDLED;
2117 }
2118
2119 static int max98095_jack_detect_enable(struct snd_soc_codec *codec)
2120 {
2121 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2122 int ret = 0;
2123 int detect_enable = M98095_JDEN;
2124 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
2125
2126 if (max98095->pdata->jack_detect_pin5en)
2127 detect_enable |= M98095_PIN5EN;
2128
2129 if (max98095->pdata->jack_detect_delay)
2130 slew = max98095->pdata->jack_detect_delay;
2131
2132 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
2133 if (ret < 0) {
2134 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2135 return ret;
2136 }
2137
2138 /* configure auto detection to be enabled */
2139 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
2140 if (ret < 0) {
2141 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2142 return ret;
2143 }
2144
2145 return ret;
2146 }
2147
2148 static int max98095_jack_detect_disable(struct snd_soc_codec *codec)
2149 {
2150 int ret = 0;
2151
2152 /* configure auto detection to be disabled */
2153 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
2154 if (ret < 0) {
2155 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2156 return ret;
2157 }
2158
2159 return ret;
2160 }
2161
2162 int max98095_jack_detect(struct snd_soc_codec *codec,
2163 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
2164 {
2165 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2166 struct i2c_client *client = to_i2c_client(codec->dev);
2167 int ret = 0;
2168
2169 max98095->headphone_jack = hp_jack;
2170 max98095->mic_jack = mic_jack;
2171
2172 /* only progress if we have at least 1 jack pointer */
2173 if (!hp_jack && !mic_jack)
2174 return -EINVAL;
2175
2176 max98095_jack_detect_enable(codec);
2177
2178 /* enable interrupts for headphone jack detection */
2179 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
2180 M98095_IDDONE, M98095_IDDONE);
2181 if (ret < 0) {
2182 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
2183 return ret;
2184 }
2185
2186 max98095_report_jack(client->irq, codec);
2187 return 0;
2188 }
2189 EXPORT_SYMBOL_GPL(max98095_jack_detect);
2190
2191 #ifdef CONFIG_PM
2192 static int max98095_suspend(struct snd_soc_codec *codec)
2193 {
2194 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2195
2196 if (max98095->headphone_jack || max98095->mic_jack)
2197 max98095_jack_detect_disable(codec);
2198
2199 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2200
2201 return 0;
2202 }
2203
2204 static int max98095_resume(struct snd_soc_codec *codec)
2205 {
2206 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2207 struct i2c_client *client = to_i2c_client(codec->dev);
2208
2209 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2210
2211 if (max98095->headphone_jack || max98095->mic_jack) {
2212 max98095_jack_detect_enable(codec);
2213 max98095_report_jack(client->irq, codec);
2214 }
2215
2216 return 0;
2217 }
2218 #else
2219 #define max98095_suspend NULL
2220 #define max98095_resume NULL
2221 #endif
2222
2223 static int max98095_reset(struct snd_soc_codec *codec)
2224 {
2225 int i, ret;
2226
2227 /* Gracefully reset the DSP core and the codec hardware
2228 * in a proper sequence */
2229 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
2230 if (ret < 0) {
2231 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
2232 return ret;
2233 }
2234
2235 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
2236 if (ret < 0) {
2237 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
2238 return ret;
2239 }
2240
2241 /* Reset to hardware default for registers, as there is not
2242 * a soft reset hardware control register */
2243 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
2244 ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
2245 if (ret < 0) {
2246 dev_err(codec->dev, "Failed to reset: %d\n", ret);
2247 return ret;
2248 }
2249 }
2250
2251 return ret;
2252 }
2253
2254 static int max98095_probe(struct snd_soc_codec *codec)
2255 {
2256 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2257 struct max98095_cdata *cdata;
2258 struct i2c_client *client;
2259 int ret = 0;
2260
2261 max98095->mclk = devm_clk_get(codec->dev, "mclk");
2262 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
2263 return -EPROBE_DEFER;
2264
2265 /* reset the codec, the DSP core, and disable all interrupts */
2266 max98095_reset(codec);
2267
2268 client = to_i2c_client(codec->dev);
2269
2270 /* initialize private data */
2271
2272 max98095->sysclk = (unsigned)-1;
2273 max98095->eq_textcnt = 0;
2274 max98095->bq_textcnt = 0;
2275
2276 cdata = &max98095->dai[0];
2277 cdata->rate = (unsigned)-1;
2278 cdata->fmt = (unsigned)-1;
2279 cdata->eq_sel = 0;
2280 cdata->bq_sel = 0;
2281
2282 cdata = &max98095->dai[1];
2283 cdata->rate = (unsigned)-1;
2284 cdata->fmt = (unsigned)-1;
2285 cdata->eq_sel = 0;
2286 cdata->bq_sel = 0;
2287
2288 cdata = &max98095->dai[2];
2289 cdata->rate = (unsigned)-1;
2290 cdata->fmt = (unsigned)-1;
2291 cdata->eq_sel = 0;
2292 cdata->bq_sel = 0;
2293
2294 max98095->lin_state = 0;
2295 max98095->mic1pre = 0;
2296 max98095->mic2pre = 0;
2297
2298 if (client->irq) {
2299 /* register an audio interrupt */
2300 ret = request_threaded_irq(client->irq, NULL,
2301 max98095_report_jack,
2302 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2303 "max98095", codec);
2304 if (ret) {
2305 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2306 goto err_access;
2307 }
2308 }
2309
2310 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2311 if (ret < 0) {
2312 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
2313 ret);
2314 goto err_irq;
2315 }
2316 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2317
2318 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
2319
2320 /* initialize registers cache to hardware default */
2321 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2322
2323 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
2324 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2325
2326 snd_soc_write(codec, M98095_049_MIX_DAC_M,
2327 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2328
2329 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2330 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2331 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
2332
2333 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
2334 M98095_S1NORMAL|M98095_SDATA);
2335
2336 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
2337 M98095_S2NORMAL|M98095_SDATA);
2338
2339 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
2340 M98095_S3NORMAL|M98095_SDATA);
2341
2342 max98095_handle_pdata(codec);
2343
2344 /* take the codec out of the shut down */
2345 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2346 M98095_SHDNRUN);
2347
2348 return 0;
2349
2350 err_irq:
2351 if (client->irq)
2352 free_irq(client->irq, codec);
2353 err_access:
2354 return ret;
2355 }
2356
2357 static int max98095_remove(struct snd_soc_codec *codec)
2358 {
2359 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2360 struct i2c_client *client = to_i2c_client(codec->dev);
2361
2362 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2363
2364 if (max98095->headphone_jack || max98095->mic_jack)
2365 max98095_jack_detect_disable(codec);
2366
2367 if (client->irq)
2368 free_irq(client->irq, codec);
2369
2370 return 0;
2371 }
2372
2373 static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2374 .probe = max98095_probe,
2375 .remove = max98095_remove,
2376 .suspend = max98095_suspend,
2377 .resume = max98095_resume,
2378 .set_bias_level = max98095_set_bias_level,
2379 .controls = max98095_snd_controls,
2380 .num_controls = ARRAY_SIZE(max98095_snd_controls),
2381 .dapm_widgets = max98095_dapm_widgets,
2382 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2383 .dapm_routes = max98095_audio_map,
2384 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2385 };
2386
2387 static int max98095_i2c_probe(struct i2c_client *i2c,
2388 const struct i2c_device_id *id)
2389 {
2390 struct max98095_priv *max98095;
2391 int ret;
2392
2393 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2394 GFP_KERNEL);
2395 if (max98095 == NULL)
2396 return -ENOMEM;
2397
2398 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2399 if (IS_ERR(max98095->regmap)) {
2400 ret = PTR_ERR(max98095->regmap);
2401 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2402 return ret;
2403 }
2404
2405 max98095->devtype = id->driver_data;
2406 i2c_set_clientdata(i2c, max98095);
2407 max98095->pdata = i2c->dev.platform_data;
2408
2409 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095,
2410 max98095_dai, ARRAY_SIZE(max98095_dai));
2411 return ret;
2412 }
2413
2414 static int max98095_i2c_remove(struct i2c_client *client)
2415 {
2416 snd_soc_unregister_codec(&client->dev);
2417 return 0;
2418 }
2419
2420 static const struct i2c_device_id max98095_i2c_id[] = {
2421 { "max98095", MAX98095 },
2422 { }
2423 };
2424 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2425
2426 static const struct of_device_id max98095_of_match[] = {
2427 { .compatible = "maxim,max98095", },
2428 { }
2429 };
2430 MODULE_DEVICE_TABLE(of, max98095_of_match);
2431
2432 static struct i2c_driver max98095_i2c_driver = {
2433 .driver = {
2434 .name = "max98095",
2435 .owner = THIS_MODULE,
2436 .of_match_table = of_match_ptr(max98095_of_match),
2437 },
2438 .probe = max98095_i2c_probe,
2439 .remove = max98095_i2c_remove,
2440 .id_table = max98095_i2c_id,
2441 };
2442
2443 module_i2c_driver(max98095_i2c_driver);
2444
2445 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2446 MODULE_AUTHOR("Peter Hsiang");
2447 MODULE_LICENSE("GPL");
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