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[mirror_ubuntu-zesty-kernel.git] / sound / soc / codecs / nau8825.c
1 /*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21 #include <linux/semaphore.h>
22
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30
31
32 #include "nau8825.h"
33
34
35 #define NUVOTON_CODEC_DAI "nau8825-hifi"
36
37 #define NAU_FREF_MAX 13500000
38 #define NAU_FVCO_MAX 124000000
39 #define NAU_FVCO_MIN 90000000
40
41 /* cross talk suppression detection */
42 #define LOG10_MAGIC 646456993
43 #define GAIN_AUGMENT 22500
44 #define SIDETONE_BASE 207000
45
46
47 static int nau8825_configure_sysclk(struct nau8825 *nau8825,
48 int clk_id, unsigned int freq);
49
50 struct nau8825_fll {
51 int mclk_src;
52 int ratio;
53 int fll_frac;
54 int fll_int;
55 int clk_ref_div;
56 };
57
58 struct nau8825_fll_attr {
59 unsigned int param;
60 unsigned int val;
61 };
62
63 /* scaling for mclk from sysclk_src output */
64 static const struct nau8825_fll_attr mclk_src_scaling[] = {
65 { 1, 0x0 },
66 { 2, 0x2 },
67 { 4, 0x3 },
68 { 8, 0x4 },
69 { 16, 0x5 },
70 { 32, 0x6 },
71 { 3, 0x7 },
72 { 6, 0xa },
73 { 12, 0xb },
74 { 24, 0xc },
75 { 48, 0xd },
76 { 96, 0xe },
77 { 5, 0xf },
78 };
79
80 /* ratio for input clk freq */
81 static const struct nau8825_fll_attr fll_ratio[] = {
82 { 512000, 0x01 },
83 { 256000, 0x02 },
84 { 128000, 0x04 },
85 { 64000, 0x08 },
86 { 32000, 0x10 },
87 { 8000, 0x20 },
88 { 4000, 0x40 },
89 };
90
91 static const struct nau8825_fll_attr fll_pre_scalar[] = {
92 { 1, 0x0 },
93 { 2, 0x1 },
94 { 4, 0x2 },
95 { 8, 0x3 },
96 };
97
98 static const struct reg_default nau8825_reg_defaults[] = {
99 { NAU8825_REG_ENA_CTRL, 0x00ff },
100 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
101 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
102 { NAU8825_REG_FLL1, 0x0 },
103 { NAU8825_REG_FLL2, 0x3126 },
104 { NAU8825_REG_FLL3, 0x0008 },
105 { NAU8825_REG_FLL4, 0x0010 },
106 { NAU8825_REG_FLL5, 0x0 },
107 { NAU8825_REG_FLL6, 0x6000 },
108 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
109 { NAU8825_REG_HSD_CTRL, 0x000c },
110 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
111 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
112 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
113 { NAU8825_REG_SAR_CTRL, 0x0015 },
114 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
115 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
116 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
117 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
118 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
119 { NAU8825_REG_GPIO34_CTRL, 0x0 },
120 { NAU8825_REG_GPIO12_CTRL, 0x0 },
121 { NAU8825_REG_TDM_CTRL, 0x0 },
122 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
123 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
124 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
125 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
126 { NAU8825_REG_BIQ_CTRL, 0x0 },
127 { NAU8825_REG_BIQ_COF1, 0x0 },
128 { NAU8825_REG_BIQ_COF2, 0x0 },
129 { NAU8825_REG_BIQ_COF3, 0x0 },
130 { NAU8825_REG_BIQ_COF4, 0x0 },
131 { NAU8825_REG_BIQ_COF5, 0x0 },
132 { NAU8825_REG_BIQ_COF6, 0x0 },
133 { NAU8825_REG_BIQ_COF7, 0x0 },
134 { NAU8825_REG_BIQ_COF8, 0x0 },
135 { NAU8825_REG_BIQ_COF9, 0x0 },
136 { NAU8825_REG_BIQ_COF10, 0x0 },
137 { NAU8825_REG_ADC_RATE, 0x0010 },
138 { NAU8825_REG_DAC_CTRL1, 0x0001 },
139 { NAU8825_REG_DAC_CTRL2, 0x0 },
140 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
141 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
142 { NAU8825_REG_MUTE_CTRL, 0x0 },
143 { NAU8825_REG_HSVOL_CTRL, 0x0 },
144 { NAU8825_REG_DACL_CTRL, 0x02cf },
145 { NAU8825_REG_DACR_CTRL, 0x00cf },
146 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
147 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
148 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
149 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
150 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
151 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
152 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
153 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
154 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
155 { NAU8825_REG_CLASSG_CTRL, 0x0 },
156 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
157 { NAU8825_REG_MISC_CTRL, 0x0 },
158 { NAU8825_REG_BIAS_ADJ, 0x0 },
159 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
160 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
161 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
162 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
163 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
164 { NAU8825_REG_RDAC, 0x0008 },
165 { NAU8825_REG_MIC_BIAS, 0x0006 },
166 { NAU8825_REG_BOOST, 0x0 },
167 { NAU8825_REG_FEPGA, 0x0 },
168 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
169 { NAU8825_REG_CHARGE_PUMP, 0x0 },
170 };
171
172 /* register backup table when cross talk detection */
173 static struct reg_default nau8825_xtalk_baktab[] = {
174 { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
175 { NAU8825_REG_HSVOL_CTRL, 0 },
176 { NAU8825_REG_DACL_CTRL, 0 },
177 { NAU8825_REG_DACR_CTRL, 0 },
178 };
179
180 static const unsigned short logtable[256] = {
181 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
182 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
183 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
184 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
185 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
186 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
187 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
188 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
189 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
190 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
191 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
192 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
193 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
194 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
195 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
196 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
197 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
198 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
199 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
200 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
201 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
202 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
203 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
204 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
205 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
206 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
207 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
208 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
209 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
210 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
211 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
212 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
213 };
214
215 /**
216 * nau8825_sema_acquire - acquire the semaphore of nau88l25
217 * @nau8825: component to register the codec private data with
218 * @timeout: how long in jiffies to wait before failure or zero to wait
219 * until release
220 *
221 * Attempts to acquire the semaphore with number of jiffies. If no more
222 * tasks are allowed to acquire the semaphore, calling this function will
223 * put the task to sleep. If the semaphore is not released within the
224 * specified number of jiffies, this function returns.
225 * Acquires the semaphore without jiffies. If no more tasks are allowed
226 * to acquire the semaphore, calling this function will put the task to
227 * sleep until the semaphore is released.
228 * If the semaphore is not released within the specified number of jiffies,
229 * this function returns -ETIME.
230 * If the sleep is interrupted by a signal, this function will return -EINTR.
231 * It returns 0 if the semaphore was acquired successfully.
232 */
233 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
234 {
235 int ret;
236
237 if (timeout) {
238 ret = down_timeout(&nau8825->xtalk_sem, timeout);
239 if (ret < 0)
240 dev_warn(nau8825->dev, "Acquire semaphone timeout\n");
241 } else {
242 ret = down_interruptible(&nau8825->xtalk_sem);
243 if (ret < 0)
244 dev_warn(nau8825->dev, "Acquire semaphone fail\n");
245 }
246
247 return ret;
248 }
249
250 /**
251 * nau8825_sema_release - release the semaphore of nau88l25
252 * @nau8825: component to register the codec private data with
253 *
254 * Release the semaphore which may be called from any context and
255 * even by tasks which have never called down().
256 */
257 static inline void nau8825_sema_release(struct nau8825 *nau8825)
258 {
259 up(&nau8825->xtalk_sem);
260 }
261
262 /**
263 * nau8825_sema_reset - reset the semaphore for nau88l25
264 * @nau8825: component to register the codec private data with
265 *
266 * Reset the counter of the semaphore. Call this function to restart
267 * a new round task management.
268 */
269 static inline void nau8825_sema_reset(struct nau8825 *nau8825)
270 {
271 nau8825->xtalk_sem.count = 1;
272 }
273
274 /**
275 * Ramp up the headphone volume change gradually to target level.
276 *
277 * @nau8825: component to register the codec private data with
278 * @vol_from: the volume to start up
279 * @vol_to: the target volume
280 * @step: the volume span to move on
281 *
282 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
283 * If the volume changes sharp, there is a pop noise heard in headphone. We
284 * provide the function to ramp up the volume up or down by delaying 10ms
285 * per step.
286 */
287 static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
288 unsigned int vol_from, unsigned int vol_to, unsigned int step)
289 {
290 unsigned int value, volume, ramp_up, from, to;
291
292 if (vol_from == vol_to || step == 0) {
293 return;
294 } else if (vol_from < vol_to) {
295 ramp_up = true;
296 from = vol_from;
297 to = vol_to;
298 } else {
299 ramp_up = false;
300 from = vol_to;
301 to = vol_from;
302 }
303 /* only handle volume from 0dB to minimum -54dB */
304 if (to > NAU8825_HP_VOL_MIN)
305 to = NAU8825_HP_VOL_MIN;
306
307 for (volume = from; volume < to; volume += step) {
308 if (ramp_up)
309 value = volume;
310 else
311 value = to - volume + from;
312 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
313 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
314 (value << NAU8825_HPL_VOL_SFT) | value);
315 usleep_range(10000, 10500);
316 }
317 if (ramp_up)
318 value = to;
319 else
320 value = from;
321 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
322 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
323 (value << NAU8825_HPL_VOL_SFT) | value);
324 }
325
326 /**
327 * Computes log10 of a value; the result is round off to 3 decimal. This func-
328 * tion takes reference to dvb-math. The source code locates as the following.
329 * Linux/drivers/media/dvb-core/dvb_math.c
330 *
331 * return log10(value) * 1000
332 */
333 static u32 nau8825_intlog10_dec3(u32 value)
334 {
335 u32 msb, logentry, significand, interpolation, log10val;
336 u64 log2val;
337
338 /* first detect the msb (count begins at 0) */
339 msb = fls(value) - 1;
340 /**
341 * now we use a logtable after the following method:
342 *
343 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
344 * where x = msb and therefore 1 <= y < 2
345 * first y is determined by shifting the value left
346 * so that msb is bit 31
347 * 0x00231f56 -> 0x8C7D5800
348 * the result is y * 2^31 -> "significand"
349 * then the highest 9 bits are used for a table lookup
350 * the highest bit is discarded because it's always set
351 * the highest nine bits in our example are 100011000
352 * so we would use the entry 0x18
353 */
354 significand = value << (31 - msb);
355 logentry = (significand >> 23) & 0xff;
356 /**
357 * last step we do is interpolation because of the
358 * limitations of the log table the error is that part of
359 * the significand which isn't used for lookup then we
360 * compute the ratio between the error and the next table entry
361 * and interpolate it between the log table entry used and the
362 * next one the biggest error possible is 0x7fffff
363 * (in our example it's 0x7D5800)
364 * needed value for next table entry is 0x800000
365 * so the interpolation is
366 * (error / 0x800000) * (logtable_next - logtable_current)
367 * in the implementation the division is moved to the end for
368 * better accuracy there is also an overflow correction if
369 * logtable_next is 256
370 */
371 interpolation = ((significand & 0x7fffff) *
372 ((logtable[(logentry + 1) & 0xff] -
373 logtable[logentry]) & 0xffff)) >> 15;
374
375 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
376 /**
377 * log10(x) = log2(x) * log10(2)
378 */
379 log10val = (log2val * LOG10_MAGIC) >> 31;
380 /**
381 * the result is round off to 3 decimal
382 */
383 return log10val / ((1 << 24) / 1000);
384 }
385
386 /**
387 * computes cross talk suppression sidetone gain.
388 *
389 * @sig_org: orignal signal level
390 * @sig_cros: cross talk signal level
391 *
392 * The orignal and cross talk signal vlues need to be characterized.
393 * Once these values have been characterized, this sidetone value
394 * can be converted to decibel with the equation below.
395 * sidetone = 20 * log (original signal level / crosstalk signal level)
396 *
397 * return cross talk sidetone gain
398 */
399 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
400 {
401 u32 gain, sidetone;
402
403 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
404 WARN_ON(1);
405 return 0;
406 }
407
408 sig_org = nau8825_intlog10_dec3(sig_org);
409 sig_cros = nau8825_intlog10_dec3(sig_cros);
410 if (sig_org >= sig_cros)
411 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
412 else
413 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
414 sidetone = SIDETONE_BASE - gain * 2;
415 sidetone /= 1000;
416
417 return sidetone;
418 }
419
420 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
421 {
422 int index;
423
424 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
425 if (nau8825_xtalk_baktab[index].reg == reg)
426 return index;
427 return -EINVAL;
428 }
429
430 static void nau8825_xtalk_backup(struct nau8825 *nau8825)
431 {
432 int i;
433
434 /* Backup some register values to backup table */
435 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
436 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
437 &nau8825_xtalk_baktab[i].def);
438 }
439
440 static void nau8825_xtalk_restore(struct nau8825 *nau8825)
441 {
442 int i, volume;
443
444 /* Restore register values from backup table; When the driver restores
445 * the headphone volumem, it needs recover to original level gradually
446 * with 3dB per step for less pop noise.
447 */
448 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
449 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
450 /* Ramping up the volume change to reduce pop noise */
451 volume = nau8825_xtalk_baktab[i].def &
452 NAU8825_HPR_VOL_MASK;
453 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
454 continue;
455 }
456 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
457 nau8825_xtalk_baktab[i].def);
458 }
459 }
460
461 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
462 {
463 /* Enable power of DAC path */
464 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
465 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
466 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
467 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
468 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
469 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
470 /* Prevent startup click by letting charge pump to ramp up and
471 * change bump enable
472 */
473 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
474 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
475 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
476 /* Enable clock sync of DAC and DAC clock */
477 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
478 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
479 NAU8825_RDAC_FS_BCLK_ENB,
480 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
481 /* Power up output driver with 2 stage */
482 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
483 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
484 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
485 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
486 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
487 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
488 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
489 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
490 /* HP outputs not shouted to ground */
491 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
492 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
493 /* Enable HP boost driver */
494 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
495 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
496 /* Enable class G compare path to supply 1.8V or 0.9V. */
497 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
498 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
499 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
500 }
501
502 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
503 {
504 /* Power up left ADC and raise 5dB than Vmid for Vref */
505 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
506 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
507 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
508 }
509
510 static void nau8825_xtalk_clock(struct nau8825 *nau8825)
511 {
512 /* Recover FLL default value */
513 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
514 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
515 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
516 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
517 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
518 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
519 /* Enable internal VCO clock for detection signal generated */
520 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
521 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
522 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
523 NAU8825_DCO_EN);
524 /* Given specific clock frequency of internal clock to
525 * generate signal.
526 */
527 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
528 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
529 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
530 NAU8825_FLL_RATIO_MASK, 0x10);
531 }
532
533 static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
534 {
535 int volume, index;
536
537 /* Backup those registers changed by cross talk detection */
538 nau8825_xtalk_backup(nau8825);
539 /* Config IIS as master to output signal by codec */
540 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
541 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
542 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
543 (0x2 << NAU8825_I2S_DRV_SFT) | 0x1);
544 /* Ramp up headphone volume to 0dB to get better performance and
545 * avoid pop noise in headphone.
546 */
547 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
548 if (index != -EINVAL) {
549 volume = nau8825_xtalk_baktab[index].def &
550 NAU8825_HPR_VOL_MASK;
551 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
552 }
553 nau8825_xtalk_clock(nau8825);
554 nau8825_xtalk_prepare_dac(nau8825);
555 nau8825_xtalk_prepare_adc(nau8825);
556 /* Config channel path and digital gain */
557 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
558 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
559 NAU8825_DACL_CH_SEL_L | 0xab);
560 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
561 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
562 NAU8825_DACR_CH_SEL_R | 0xab);
563 /* Config cross talk parameters and generate the 23Hz sine wave with
564 * 1/16 full scale of signal level for impedance measurement.
565 */
566 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
567 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
568 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
569 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
570 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
571 /* RMS intrruption enable */
572 regmap_update_bits(nau8825->regmap,
573 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
574 /* Power up left and right DAC */
575 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
576 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
577 }
578
579 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
580 {
581 /* Disable HP boost driver */
582 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
583 NAU8825_HP_BOOST_DIS, 0);
584 /* HP outputs shouted to ground */
585 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
586 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
587 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
588 /* Power down left and right DAC */
589 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
590 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
591 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
592 /* Enable the TESTDAC and disable L/R HP impedance */
593 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
594 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
595 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
596 /* Power down output driver with 2 stage */
597 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
598 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
599 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
600 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
601 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
602 /* Disable clock sync of DAC and DAC clock */
603 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
604 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
605 /* Disable charge pump ramp up function and change bump */
606 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
607 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
608 /* Disable power of DAC path */
609 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
610 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
611 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
612 if (!nau8825->irq)
613 regmap_update_bits(nau8825->regmap,
614 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
615 }
616
617 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
618 {
619 /* Power down left ADC and restore voltage to Vmid */
620 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
621 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
622 }
623
624 static void nau8825_xtalk_clean(struct nau8825 *nau8825)
625 {
626 /* Enable internal VCO needed for interruptions */
627 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
628 nau8825_xtalk_clean_dac(nau8825);
629 nau8825_xtalk_clean_adc(nau8825);
630 /* Clear cross talk parameters and disable */
631 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
632 /* RMS intrruption disable */
633 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
634 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
635 /* Recover default value for IIS */
636 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
637 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
638 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
639 /* Restore value of specific register for cross talk */
640 nau8825_xtalk_restore(nau8825);
641 }
642
643 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
644 {
645 /* Apply ADC volume for better cross talk performance */
646 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
647 NAU8825_ADC_DIG_VOL_MASK, vol);
648 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
649 * Do it before sending signal in order to erase pop noise.
650 */
651 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
652 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
653 NAU8825_BIAS_TESTDACL_EN);
654 switch (nau8825->xtalk_state) {
655 case NAU8825_XTALK_HPR_R2L:
656 /* Enable right headphone impedance */
657 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
658 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
659 NAU8825_BIAS_HPR_IMP);
660 break;
661 case NAU8825_XTALK_HPL_R2L:
662 /* Enable left headphone impedance */
663 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
664 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
665 NAU8825_BIAS_HPL_IMP);
666 break;
667 default:
668 break;
669 }
670 msleep(100);
671 /* Impedance measurement mode enable */
672 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
673 NAU8825_IMM_EN, NAU8825_IMM_EN);
674 }
675
676 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
677 {
678 /* Impedance measurement mode disable */
679 regmap_update_bits(nau8825->regmap,
680 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
681 }
682
683 /* The cross talk measurement function can reduce cross talk across the
684 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
685 * level to determine what cross talk reduction gain is. This system works by
686 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
687 * the PGA. The output of the PGA is then connected to an internal current
688 * sense which measures the attenuated 23Hz signal and passing the output to
689 * an ADC which converts the measurement to a binary code. With two separated
690 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
691 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
692 * Thus, the measurement function has four states to complete whole sequence.
693 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
694 * IMM stat to make JKR1(HPR) impedance measure.
695 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
696 * to HPL IMM state to make JKTIP(HPL) impedance measure.
697 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
698 * transfer to IMM state to determine suppression sidetone gain.
699 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
700 * and cross talk signal level. Apply this gain and then restore codec
701 * configuration. Then transfer to Done state for ending.
702 */
703 static void nau8825_xtalk_measure(struct nau8825 *nau8825)
704 {
705 u32 sidetone;
706
707 switch (nau8825->xtalk_state) {
708 case NAU8825_XTALK_PREPARE:
709 /* In prepare state, set up clock, intrruption, DAC path, ADC
710 * path and cross talk detection parameters for preparation.
711 */
712 nau8825_xtalk_prepare(nau8825);
713 msleep(280);
714 /* Trigger right headphone impedance detection */
715 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
716 nau8825_xtalk_imm_start(nau8825, 0x00d2);
717 break;
718 case NAU8825_XTALK_HPR_R2L:
719 /* In right headphone IMM state, read out right headphone
720 * impedance measure result, and then start up left side.
721 */
722 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
723 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
724 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
725 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
726 /* Disable then re-enable IMM mode to update */
727 nau8825_xtalk_imm_stop(nau8825);
728 /* Trigger left headphone impedance detection */
729 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
730 nau8825_xtalk_imm_start(nau8825, 0x00ff);
731 break;
732 case NAU8825_XTALK_HPL_R2L:
733 /* In left headphone IMM state, read out left headphone
734 * impedance measure result, and delay some time to wait
735 * detection sine wave output finish. Then, we can calculate
736 * the cross talk suppresstion side tone according to the L/R
737 * headphone imedance.
738 */
739 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
740 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
741 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
742 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
743 nau8825_xtalk_imm_stop(nau8825);
744 msleep(150);
745 nau8825->xtalk_state = NAU8825_XTALK_IMM;
746 break;
747 case NAU8825_XTALK_IMM:
748 /* In impedance measure state, the orignal and cross talk
749 * signal level vlues are ready. The side tone gain is deter-
750 * mined with these signal level. After all, restore codec
751 * configuration.
752 */
753 sidetone = nau8825_xtalk_sidetone(
754 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
755 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
756 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
757 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
758 (sidetone << 8) | sidetone);
759 nau8825_xtalk_clean(nau8825);
760 nau8825->xtalk_state = NAU8825_XTALK_DONE;
761 break;
762 default:
763 break;
764 }
765 }
766
767 static void nau8825_xtalk_work(struct work_struct *work)
768 {
769 struct nau8825 *nau8825 = container_of(
770 work, struct nau8825, xtalk_work);
771
772 nau8825_xtalk_measure(nau8825);
773 /* To determine the cross talk side tone gain when reach
774 * the impedance measure state.
775 */
776 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
777 nau8825_xtalk_measure(nau8825);
778
779 /* Delay jack report until cross talk detection process
780 * completed. It can avoid application to do playback
781 * preparation before cross talk detection is still working.
782 * Meanwhile, the protection of the cross talk detection
783 * is released.
784 */
785 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
786 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
787 nau8825->xtalk_event_mask);
788 nau8825_sema_release(nau8825);
789 nau8825->xtalk_protect = false;
790 }
791 }
792
793 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
794 {
795 /* If the xtalk_protect is true, that means the process is still
796 * on going. The driver forces to cancel the cross talk task and
797 * restores the configuration to original status.
798 */
799 if (nau8825->xtalk_protect) {
800 cancel_work_sync(&nau8825->xtalk_work);
801 nau8825_xtalk_clean(nau8825);
802 }
803 /* Reset parameters for cross talk suppression function */
804 nau8825_sema_reset(nau8825);
805 nau8825->xtalk_state = NAU8825_XTALK_DONE;
806 nau8825->xtalk_protect = false;
807 }
808
809 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
810 {
811 switch (reg) {
812 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
813 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
814 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
815 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
816 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
817 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
818 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
819 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
820 case NAU8825_REG_MISC_CTRL:
821 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
822 case NAU8825_REG_BIAS_ADJ:
823 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
824 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
825 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
826 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
827 return true;
828 default:
829 return false;
830 }
831
832 }
833
834 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
835 {
836 switch (reg) {
837 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
838 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
839 case NAU8825_REG_INTERRUPT_MASK:
840 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
841 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
842 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
843 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
844 case NAU8825_REG_IMM_MODE_CTRL:
845 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
846 case NAU8825_REG_MISC_CTRL:
847 case NAU8825_REG_BIAS_ADJ:
848 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
849 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
850 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
851 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
852 return true;
853 default:
854 return false;
855 }
856 }
857
858 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
859 {
860 switch (reg) {
861 case NAU8825_REG_RESET:
862 case NAU8825_REG_IRQ_STATUS:
863 case NAU8825_REG_INT_CLR_KEY_STATUS:
864 case NAU8825_REG_IMM_RMS_L:
865 case NAU8825_REG_IMM_RMS_R:
866 case NAU8825_REG_I2C_DEVICE_ID:
867 case NAU8825_REG_SARDOUT_RAM_STATUS:
868 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
869 case NAU8825_REG_GENERAL_STATUS:
870 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
871 return true;
872 default:
873 return false;
874 }
875 }
876
877 static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
878 struct snd_kcontrol *kcontrol, int event)
879 {
880 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
881 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
882
883 switch (event) {
884 case SND_SOC_DAPM_POST_PMU:
885 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
886 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
887 break;
888 case SND_SOC_DAPM_POST_PMD:
889 if (!nau8825->irq)
890 regmap_update_bits(nau8825->regmap,
891 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
892 break;
893 default:
894 return -EINVAL;
895 }
896
897 return 0;
898 }
899
900 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
901 struct snd_kcontrol *kcontrol, int event)
902 {
903 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
904 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
905
906 switch (event) {
907 case SND_SOC_DAPM_POST_PMU:
908 /* Prevent startup click by letting charge pump to ramp up */
909 msleep(10);
910 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
911 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
912 break;
913 case SND_SOC_DAPM_PRE_PMD:
914 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
915 NAU8825_JAMNODCLOW, 0);
916 break;
917 default:
918 return -EINVAL;
919 }
920
921 return 0;
922 }
923
924 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
925 struct snd_kcontrol *kcontrol, int event)
926 {
927 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
928 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
929
930 switch (event) {
931 case SND_SOC_DAPM_PRE_PMU:
932 /* Disables the TESTDAC to let DAC signal pass through. */
933 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
934 NAU8825_BIAS_TESTDAC_EN, 0);
935 break;
936 case SND_SOC_DAPM_POST_PMD:
937 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
938 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
939 break;
940 default:
941 return -EINVAL;
942 }
943
944 return 0;
945 }
946
947 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
948 struct snd_ctl_elem_value *ucontrol)
949 {
950 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
951 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
952
953 if (!component->regmap)
954 return -EINVAL;
955
956 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
957 ucontrol->value.bytes.data, params->max);
958 return 0;
959 }
960
961 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
962 struct snd_ctl_elem_value *ucontrol)
963 {
964 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
965 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
966 void *data;
967
968 if (!component->regmap)
969 return -EINVAL;
970
971 data = kmemdup(ucontrol->value.bytes.data,
972 params->max, GFP_KERNEL | GFP_DMA);
973 if (!data)
974 return -ENOMEM;
975
976 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
977 NAU8825_BIQ_WRT_EN, 0);
978 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
979 data, params->max);
980 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
981 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
982
983 kfree(data);
984 return 0;
985 }
986
987 static const char * const nau8825_biq_path[] = {
988 "ADC", "DAC"
989 };
990
991 static const struct soc_enum nau8825_biq_path_enum =
992 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
993 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
994
995 static const char * const nau8825_adc_decimation[] = {
996 "32", "64", "128", "256"
997 };
998
999 static const struct soc_enum nau8825_adc_decimation_enum =
1000 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1001 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1002
1003 static const char * const nau8825_dac_oversampl[] = {
1004 "64", "256", "128", "", "32"
1005 };
1006
1007 static const struct soc_enum nau8825_dac_oversampl_enum =
1008 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1009 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1010
1011 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1012 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1013 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1014 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1015 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1016
1017 static const struct snd_kcontrol_new nau8825_controls[] = {
1018 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1019 0, 0xff, 0, adc_vol_tlv),
1020 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1021 12, 8, 0x0f, 0, sidetone_vol_tlv),
1022 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1023 6, 0, 0x3f, 1, dac_vol_tlv),
1024 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1025 8, 37, 0, fepga_gain_tlv),
1026 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1027 0, 8, 0xff, 0, crosstalk_vol_tlv),
1028
1029 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1030 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1031 /* programmable biquad filter */
1032 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1033 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1034 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1035 };
1036
1037 /* DAC Mux 0x33[9] and 0x34[9] */
1038 static const char * const nau8825_dac_src[] = {
1039 "DACL", "DACR",
1040 };
1041
1042 static SOC_ENUM_SINGLE_DECL(
1043 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1044 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1045
1046 static SOC_ENUM_SINGLE_DECL(
1047 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1048 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1049
1050 static const struct snd_kcontrol_new nau8825_dacl_mux =
1051 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1052
1053 static const struct snd_kcontrol_new nau8825_dacr_mux =
1054 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1055
1056
1057 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1058 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1059 15, 1),
1060
1061 SND_SOC_DAPM_INPUT("MIC"),
1062 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1063
1064 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1065 NULL, 0),
1066
1067 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1068 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1069 SND_SOC_DAPM_POST_PMD),
1070 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1071 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1072 0),
1073
1074 /* ADC for button press detection. A dapm supply widget is used to
1075 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1076 * during suspend.
1077 */
1078 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1079 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1080
1081 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1082 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1083 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1084 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1085
1086 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1087 NAU8825_ENABLE_DACR_SFT, 0),
1088 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1089 NAU8825_ENABLE_DACL_SFT, 0),
1090 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1091
1092 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1093 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1094
1095 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1096 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1097 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1098 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1099
1100 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1101 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1102 SND_SOC_DAPM_PRE_PMD),
1103
1104 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1105 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1106 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1107 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1108 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1109 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1110 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1111 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1112 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1113 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1114 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1115 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1116
1117 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1118 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1119 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1120 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1121 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1122 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1123
1124 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1125 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1126 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1127 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1128 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1129
1130 /* High current HPOL/R boost driver */
1131 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1132 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1133
1134 /* Class G operation control*/
1135 SND_SOC_DAPM_PGA_S("Class G", 10,
1136 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1137
1138 SND_SOC_DAPM_OUTPUT("HPOL"),
1139 SND_SOC_DAPM_OUTPUT("HPOR"),
1140 };
1141
1142 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1143 {"Frontend PGA", NULL, "MIC"},
1144 {"ADC", NULL, "Frontend PGA"},
1145 {"ADC", NULL, "ADC Clock"},
1146 {"ADC", NULL, "ADC Power"},
1147 {"AIFTX", NULL, "ADC"},
1148
1149 {"DDACL", NULL, "Playback"},
1150 {"DDACR", NULL, "Playback"},
1151 {"DDACL", NULL, "DDAC Clock"},
1152 {"DDACR", NULL, "DDAC Clock"},
1153 {"DACL Mux", "DACL", "DDACL"},
1154 {"DACL Mux", "DACR", "DDACR"},
1155 {"DACR Mux", "DACL", "DDACL"},
1156 {"DACR Mux", "DACR", "DDACR"},
1157 {"HP amp L", NULL, "DACL Mux"},
1158 {"HP amp R", NULL, "DACR Mux"},
1159 {"Charge Pump", NULL, "HP amp L"},
1160 {"Charge Pump", NULL, "HP amp R"},
1161 {"ADACL", NULL, "Charge Pump"},
1162 {"ADACR", NULL, "Charge Pump"},
1163 {"ADACL Clock", NULL, "ADACL"},
1164 {"ADACR Clock", NULL, "ADACR"},
1165 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1166 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1167 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1168 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1169 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1170 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1171 {"Output DACL", NULL, "Output Driver L Stage 3"},
1172 {"Output DACR", NULL, "Output Driver R Stage 3"},
1173 {"HPOL Pulldown", NULL, "Output DACL"},
1174 {"HPOR Pulldown", NULL, "Output DACR"},
1175 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1176 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1177 {"Class G", NULL, "HP Boost Driver"},
1178 {"HPOL", NULL, "Class G"},
1179 {"HPOR", NULL, "Class G"},
1180 };
1181
1182 static int nau8825_hw_params(struct snd_pcm_substream *substream,
1183 struct snd_pcm_hw_params *params,
1184 struct snd_soc_dai *dai)
1185 {
1186 struct snd_soc_codec *codec = dai->codec;
1187 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1188 unsigned int val_len = 0;
1189
1190 nau8825_sema_acquire(nau8825, 2 * HZ);
1191
1192 switch (params_width(params)) {
1193 case 16:
1194 val_len |= NAU8825_I2S_DL_16;
1195 break;
1196 case 20:
1197 val_len |= NAU8825_I2S_DL_20;
1198 break;
1199 case 24:
1200 val_len |= NAU8825_I2S_DL_24;
1201 break;
1202 case 32:
1203 val_len |= NAU8825_I2S_DL_32;
1204 break;
1205 default:
1206 return -EINVAL;
1207 }
1208
1209 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1210 NAU8825_I2S_DL_MASK, val_len);
1211
1212 /* Release the semaphone. */
1213 nau8825_sema_release(nau8825);
1214
1215 return 0;
1216 }
1217
1218 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1219 {
1220 struct snd_soc_codec *codec = codec_dai->codec;
1221 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1222 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1223
1224 nau8825_sema_acquire(nau8825, 2 * HZ);
1225
1226 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1227 case SND_SOC_DAIFMT_CBM_CFM:
1228 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1229 break;
1230 case SND_SOC_DAIFMT_CBS_CFS:
1231 break;
1232 default:
1233 return -EINVAL;
1234 }
1235
1236 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1237 case SND_SOC_DAIFMT_NB_NF:
1238 break;
1239 case SND_SOC_DAIFMT_IB_NF:
1240 ctrl1_val |= NAU8825_I2S_BP_INV;
1241 break;
1242 default:
1243 return -EINVAL;
1244 }
1245
1246 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1247 case SND_SOC_DAIFMT_I2S:
1248 ctrl1_val |= NAU8825_I2S_DF_I2S;
1249 break;
1250 case SND_SOC_DAIFMT_LEFT_J:
1251 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1252 break;
1253 case SND_SOC_DAIFMT_RIGHT_J:
1254 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1255 break;
1256 case SND_SOC_DAIFMT_DSP_A:
1257 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1258 break;
1259 case SND_SOC_DAIFMT_DSP_B:
1260 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1261 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1262 break;
1263 default:
1264 return -EINVAL;
1265 }
1266
1267 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1268 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1269 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1270 ctrl1_val);
1271 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1272 NAU8825_I2S_MS_MASK, ctrl2_val);
1273
1274 /* Release the semaphone. */
1275 nau8825_sema_release(nau8825);
1276
1277 return 0;
1278 }
1279
1280 static const struct snd_soc_dai_ops nau8825_dai_ops = {
1281 .hw_params = nau8825_hw_params,
1282 .set_fmt = nau8825_set_dai_fmt,
1283 };
1284
1285 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1286 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1287 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1288
1289 static struct snd_soc_dai_driver nau8825_dai = {
1290 .name = "nau8825-hifi",
1291 .playback = {
1292 .stream_name = "Playback",
1293 .channels_min = 1,
1294 .channels_max = 2,
1295 .rates = NAU8825_RATES,
1296 .formats = NAU8825_FORMATS,
1297 },
1298 .capture = {
1299 .stream_name = "Capture",
1300 .channels_min = 1,
1301 .channels_max = 1,
1302 .rates = NAU8825_RATES,
1303 .formats = NAU8825_FORMATS,
1304 },
1305 .ops = &nau8825_dai_ops,
1306 };
1307
1308 /**
1309 * nau8825_enable_jack_detect - Specify a jack for event reporting
1310 *
1311 * @component: component to register the jack with
1312 * @jack: jack to use to report headset and button events on
1313 *
1314 * After this function has been called the headset insert/remove and button
1315 * events will be routed to the given jack. Jack can be null to stop
1316 * reporting.
1317 */
1318 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1319 struct snd_soc_jack *jack)
1320 {
1321 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1322 struct regmap *regmap = nau8825->regmap;
1323
1324 nau8825->jack = jack;
1325
1326 /* Ground HP Outputs[1:0], needed for headset auto detection
1327 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1328 */
1329 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1330 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1331 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1332
1333 return 0;
1334 }
1335 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1336
1337
1338 static bool nau8825_is_jack_inserted(struct regmap *regmap)
1339 {
1340 bool active_high, is_high;
1341 int status, jkdet;
1342
1343 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1344 active_high = jkdet & NAU8825_JACK_POLARITY;
1345 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1346 is_high = status & NAU8825_GPIO2JD1;
1347 /* return jack connection status according to jack insertion logic
1348 * active high or active low.
1349 */
1350 return active_high == is_high;
1351 }
1352
1353 static void nau8825_restart_jack_detection(struct regmap *regmap)
1354 {
1355 /* this will restart the entire jack detection process including MIC/GND
1356 * switching and create interrupts. We have to go from 0 to 1 and back
1357 * to 0 to restart.
1358 */
1359 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1360 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1361 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1362 NAU8825_JACK_DET_RESTART, 0);
1363 }
1364
1365 static void nau8825_int_status_clear_all(struct regmap *regmap)
1366 {
1367 int active_irq, clear_irq, i;
1368
1369 /* Reset the intrruption status from rightmost bit if the corres-
1370 * ponding irq event occurs.
1371 */
1372 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1373 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1374 clear_irq = (0x1 << i);
1375 if (active_irq & clear_irq)
1376 regmap_write(regmap,
1377 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1378 }
1379 }
1380
1381 static void nau8825_eject_jack(struct nau8825 *nau8825)
1382 {
1383 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1384 struct regmap *regmap = nau8825->regmap;
1385
1386 /* Force to cancel the cross talk detection process */
1387 nau8825_xtalk_cancel(nau8825);
1388
1389 snd_soc_dapm_disable_pin(dapm, "SAR");
1390 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1391 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1392 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1393 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1394 /* ground HPL/HPR, MICGRND1/2 */
1395 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1396
1397 snd_soc_dapm_sync(dapm);
1398
1399 /* Clear all interruption status */
1400 nau8825_int_status_clear_all(regmap);
1401
1402 /* Enable the insertion interruption, disable the ejection inter-
1403 * ruption, and then bypass de-bounce circuit.
1404 */
1405 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1406 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1407 NAU8825_IRQ_EJECT_DIS);
1408 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1409 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1410 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1411 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1412 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1413 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1414 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1415
1416 /* Disable ADC needed for interruptions at audo mode */
1417 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1418 NAU8825_ENABLE_ADC, 0);
1419
1420 /* Close clock for jack type detection at manual mode */
1421 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1422 }
1423
1424 /* Enable audo mode interruptions with internal clock. */
1425 static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1426 {
1427 struct regmap *regmap = nau8825->regmap;
1428
1429 /* Enable headset jack type detection complete interruption and
1430 * jack ejection interruption.
1431 */
1432 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1433 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1434
1435 /* Enable internal VCO needed for interruptions */
1436 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1437
1438 /* Enable ADC needed for interruptions */
1439 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1440 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1441
1442 /* Chip needs one FSCLK cycle in order to generate interruptions,
1443 * as we cannot guarantee one will be provided by the system. Turning
1444 * master mode on then off enables us to generate that FSCLK cycle
1445 * with a minimum of contention on the clock bus.
1446 */
1447 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1448 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1449 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1450 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1451
1452 /* Not bypass de-bounce circuit */
1453 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1454 NAU8825_JACK_DET_DB_BYPASS, 0);
1455
1456 /* Unmask all interruptions */
1457 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1458
1459 /* Restart the jack detection process at auto mode */
1460 nau8825_restart_jack_detection(regmap);
1461 }
1462
1463 static int nau8825_button_decode(int value)
1464 {
1465 int buttons = 0;
1466
1467 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1468 if (value & BIT(0))
1469 buttons |= SND_JACK_BTN_0;
1470 if (value & BIT(1))
1471 buttons |= SND_JACK_BTN_1;
1472 if (value & BIT(2))
1473 buttons |= SND_JACK_BTN_2;
1474 if (value & BIT(3))
1475 buttons |= SND_JACK_BTN_3;
1476 if (value & BIT(4))
1477 buttons |= SND_JACK_BTN_4;
1478 if (value & BIT(5))
1479 buttons |= SND_JACK_BTN_5;
1480
1481 return buttons;
1482 }
1483
1484 static int nau8825_jack_insert(struct nau8825 *nau8825)
1485 {
1486 struct regmap *regmap = nau8825->regmap;
1487 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1488 int jack_status_reg, mic_detected;
1489 int type = 0;
1490
1491 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1492 mic_detected = (jack_status_reg >> 10) & 3;
1493 /* The JKSLV and JKR2 all detected in high impedance headset */
1494 if (mic_detected == 0x3)
1495 nau8825->high_imped = true;
1496 else
1497 nau8825->high_imped = false;
1498
1499 switch (mic_detected) {
1500 case 0:
1501 /* no mic */
1502 type = SND_JACK_HEADPHONE;
1503 break;
1504 case 1:
1505 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1506 type = SND_JACK_HEADSET;
1507
1508 /* Unground MICGND1 */
1509 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1510 1 << 2);
1511 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1512 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1513 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1514 NAU8825_MICBIAS_JKR2);
1515 /* Attach SARADC to MICGND1 */
1516 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1517 NAU8825_SAR_INPUT_MASK,
1518 NAU8825_SAR_INPUT_JKR2);
1519
1520 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1521 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1522 snd_soc_dapm_sync(dapm);
1523 break;
1524 case 2:
1525 case 3:
1526 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1527 type = SND_JACK_HEADSET;
1528
1529 /* Unground MICGND2 */
1530 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1531 2 << 2);
1532 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1533 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1534 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1535 NAU8825_MICBIAS_JKSLV);
1536 /* Attach SARADC to MICGND2 */
1537 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1538 NAU8825_SAR_INPUT_MASK,
1539 NAU8825_SAR_INPUT_JKSLV);
1540
1541 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1542 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1543 snd_soc_dapm_sync(dapm);
1544 break;
1545 }
1546
1547 /* Leaving HPOL/R grounded after jack insert by default. They will be
1548 * ungrounded as part of the widget power up sequence at the beginning
1549 * of playback to reduce pop.
1550 */
1551 return type;
1552 }
1553
1554 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1555 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1556
1557 static irqreturn_t nau8825_interrupt(int irq, void *data)
1558 {
1559 struct nau8825 *nau8825 = (struct nau8825 *)data;
1560 struct regmap *regmap = nau8825->regmap;
1561 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1562
1563 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1564 dev_err(nau8825->dev, "failed to read irq status\n");
1565 return IRQ_NONE;
1566 }
1567
1568 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1569 NAU8825_JACK_EJECTION_DETECTED) {
1570
1571 nau8825_eject_jack(nau8825);
1572 event_mask |= SND_JACK_HEADSET;
1573 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1574 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1575 int key_status;
1576
1577 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1578 &key_status);
1579
1580 /* upper 8 bits of the register are for short pressed keys,
1581 * lower 8 bits - for long pressed buttons
1582 */
1583 nau8825->button_pressed = nau8825_button_decode(
1584 key_status >> 8);
1585
1586 event |= nau8825->button_pressed;
1587 event_mask |= NAU8825_BUTTONS;
1588 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1589 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1590 event_mask = NAU8825_BUTTONS;
1591 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1592 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1593 if (nau8825_is_jack_inserted(regmap)) {
1594 event |= nau8825_jack_insert(nau8825);
1595 if (!nau8825->high_imped) {
1596 /* Apply the cross talk suppression in the
1597 * headset without high impedance.
1598 */
1599 if (!nau8825->xtalk_protect) {
1600 /* Raise protection for cross talk de-
1601 * tection if no protection before.
1602 * The driver has to cancel the pro-
1603 * cess and restore changes if process
1604 * is ongoing when ejection.
1605 */
1606 int ret;
1607 nau8825->xtalk_protect = true;
1608 ret = nau8825_sema_acquire(nau8825, 0);
1609 if (ret < 0)
1610 nau8825->xtalk_protect = false;
1611 }
1612 /* Startup cross talk detection process */
1613 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1614 schedule_work(&nau8825->xtalk_work);
1615 } else {
1616 /* The cross talk suppression shouldn't apply
1617 * in the headset with high impedance. Thus,
1618 * relieve the protection raised before.
1619 */
1620 if (nau8825->xtalk_protect) {
1621 nau8825_sema_release(nau8825);
1622 nau8825->xtalk_protect = false;
1623 }
1624 }
1625 } else {
1626 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1627 nau8825_eject_jack(nau8825);
1628 }
1629
1630 event_mask |= SND_JACK_HEADSET;
1631 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1632 /* Record the interruption report event for driver to report
1633 * the event later. The jack report will delay until cross
1634 * talk detection process is done.
1635 */
1636 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1637 nau8825->xtalk_event = event;
1638 nau8825->xtalk_event_mask = event_mask;
1639 }
1640 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1641 schedule_work(&nau8825->xtalk_work);
1642 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1643 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1644 NAU8825_JACK_INSERTION_DETECTED) {
1645 /* One more step to check GPIO status directly. Thus, the
1646 * driver can confirm the real insertion interruption because
1647 * the intrruption at manual mode has bypassed debounce
1648 * circuit which can get rid of unstable status.
1649 */
1650 if (nau8825_is_jack_inserted(regmap)) {
1651 /* Turn off insertion interruption at manual mode */
1652 regmap_update_bits(regmap,
1653 NAU8825_REG_INTERRUPT_DIS_CTRL,
1654 NAU8825_IRQ_INSERT_DIS,
1655 NAU8825_IRQ_INSERT_DIS);
1656 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1657 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1658 /* Enable interruption for jack type detection at audo
1659 * mode which can detect microphone and jack type.
1660 */
1661 nau8825_setup_auto_irq(nau8825);
1662 }
1663 }
1664
1665 if (!clear_irq)
1666 clear_irq = active_irq;
1667 /* clears the rightmost interruption */
1668 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1669
1670 /* Delay jack report until cross talk detection is done. It can avoid
1671 * application to do playback preparation when cross talk detection
1672 * process is still working. Otherwise, the resource like clock and
1673 * power will be issued by them at the same time and conflict happens.
1674 */
1675 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1676 snd_soc_jack_report(nau8825->jack, event, event_mask);
1677
1678 return IRQ_HANDLED;
1679 }
1680
1681 static void nau8825_setup_buttons(struct nau8825 *nau8825)
1682 {
1683 struct regmap *regmap = nau8825->regmap;
1684
1685 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1686 NAU8825_SAR_TRACKING_GAIN_MASK,
1687 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1688 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1689 NAU8825_SAR_COMPARE_TIME_MASK,
1690 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1691 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1692 NAU8825_SAR_SAMPLING_TIME_MASK,
1693 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1694
1695 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1696 NAU8825_KEYDET_LEVELS_NR_MASK,
1697 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1698 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1699 NAU8825_KEYDET_HYSTERESIS_MASK,
1700 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1701 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1702 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1703 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1704
1705 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1706 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1707 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1708 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1709 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1710 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1711 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1712 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1713
1714 /* Enable short press and release interruptions */
1715 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1716 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1717 0);
1718 }
1719
1720 static void nau8825_init_regs(struct nau8825 *nau8825)
1721 {
1722 struct regmap *regmap = nau8825->regmap;
1723
1724 /* Latch IIC LSB value */
1725 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1726 /* Enable Bias/Vmid */
1727 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1728 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1729 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1730 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1731
1732 /* VMID Tieoff */
1733 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1734 NAU8825_BIAS_VMID_SEL_MASK,
1735 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1736 /* Disable Boost Driver, Automatic Short circuit protection enable */
1737 regmap_update_bits(regmap, NAU8825_REG_BOOST,
1738 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1739 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1740 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1741 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1742
1743 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1744 NAU8825_JKDET_OUTPUT_EN,
1745 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1746 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1747 NAU8825_JKDET_PULL_EN,
1748 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1749 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1750 NAU8825_JKDET_PULL_UP,
1751 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1752 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1753 NAU8825_JACK_POLARITY,
1754 /* jkdet_polarity - 1 is for active-low */
1755 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1756
1757 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1758 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1759 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1760 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1761 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1762 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1763
1764 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1765 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1766
1767 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1768 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1769
1770 if (nau8825->sar_threshold_num)
1771 nau8825_setup_buttons(nau8825);
1772
1773 /* Default oversampling/decimations settings are unusable
1774 * (audible hiss). Set it to something better.
1775 */
1776 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1777 NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
1778 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1779 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
1780 /* Disable DACR/L power */
1781 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1782 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1783 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1784 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1785 * signal to avoid any glitches due to power up transients in both
1786 * the analog and digital DAC circuit.
1787 */
1788 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1789 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1790 /* CICCLP off */
1791 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1792 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1793
1794 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1795 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1796 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1797 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1798 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1799 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1800 /* Class G timer 64ms */
1801 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1802 NAU8825_CLASSG_TIMER_MASK,
1803 0x20 << NAU8825_CLASSG_TIMER_SFT);
1804 /* DAC clock delay 2ns, VREF */
1805 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1806 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1807 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1808 (0x3 << NAU8825_RDAC_VREF_SFT));
1809 /* Config L/R channel */
1810 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1811 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1812 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1813 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1814 }
1815
1816 static const struct regmap_config nau8825_regmap_config = {
1817 .val_bits = NAU8825_REG_DATA_LEN,
1818 .reg_bits = NAU8825_REG_ADDR_LEN,
1819
1820 .max_register = NAU8825_REG_MAX,
1821 .readable_reg = nau8825_readable_reg,
1822 .writeable_reg = nau8825_writeable_reg,
1823 .volatile_reg = nau8825_volatile_reg,
1824
1825 .cache_type = REGCACHE_RBTREE,
1826 .reg_defaults = nau8825_reg_defaults,
1827 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1828 };
1829
1830 static int nau8825_codec_probe(struct snd_soc_codec *codec)
1831 {
1832 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1833 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1834
1835 nau8825->dapm = dapm;
1836
1837 return 0;
1838 }
1839
1840 static int nau8825_codec_remove(struct snd_soc_codec *codec)
1841 {
1842 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1843
1844 /* Cancel and reset cross tak suppresstion detection funciton */
1845 nau8825_xtalk_cancel(nau8825);
1846
1847 return 0;
1848 }
1849
1850 /**
1851 * nau8825_calc_fll_param - Calculate FLL parameters.
1852 * @fll_in: external clock provided to codec.
1853 * @fs: sampling rate.
1854 * @fll_param: Pointer to structure of FLL parameters.
1855 *
1856 * Calculate FLL parameters to configure codec.
1857 *
1858 * Returns 0 for success or negative error code.
1859 */
1860 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1861 struct nau8825_fll *fll_param)
1862 {
1863 u64 fvco, fvco_max;
1864 unsigned int fref, i, fvco_sel;
1865
1866 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1867 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1868 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1869 */
1870 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1871 fref = fll_in / fll_pre_scalar[i].param;
1872 if (fref <= NAU_FREF_MAX)
1873 break;
1874 }
1875 if (i == ARRAY_SIZE(fll_pre_scalar))
1876 return -EINVAL;
1877 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1878
1879 /* Choose the FLL ratio based on FREF */
1880 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1881 if (fref >= fll_ratio[i].param)
1882 break;
1883 }
1884 if (i == ARRAY_SIZE(fll_ratio))
1885 return -EINVAL;
1886 fll_param->ratio = fll_ratio[i].val;
1887
1888 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1889 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1890 * guaranteed across the full range of operation.
1891 * FDCO = freq_out * 2 * mclk_src_scaling
1892 */
1893 fvco_max = 0;
1894 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1895 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1896 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1897 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1898 fvco_max < fvco) {
1899 fvco_max = fvco;
1900 fvco_sel = i;
1901 }
1902 }
1903 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1904 return -EINVAL;
1905 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1906
1907 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1908 * input based on FDCO, FREF and FLL ratio.
1909 */
1910 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1911 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1912 fll_param->fll_frac = fvco & 0xFFFF;
1913 return 0;
1914 }
1915
1916 static void nau8825_fll_apply(struct nau8825 *nau8825,
1917 struct nau8825_fll *fll_param)
1918 {
1919 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1920 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
1921 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
1922 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
1923 NAU8825_FLL_RATIO_MASK, fll_param->ratio);
1924 /* FLL 16-bit fractional input */
1925 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
1926 /* FLL 10-bit integer input */
1927 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
1928 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
1929 /* FLL pre-scaler */
1930 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
1931 NAU8825_FLL_REF_DIV_MASK, fll_param->clk_ref_div);
1932 /* select divided VCO input */
1933 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1934 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
1935 /* Disable free-running mode */
1936 regmap_update_bits(nau8825->regmap,
1937 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
1938 if (fll_param->fll_frac) {
1939 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1940 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1941 NAU8825_FLL_FTR_SW_MASK,
1942 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1943 NAU8825_FLL_FTR_SW_FILTER);
1944 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
1945 NAU8825_SDM_EN, NAU8825_SDM_EN);
1946 } else {
1947 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1948 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1949 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
1950 regmap_update_bits(nau8825->regmap,
1951 NAU8825_REG_FLL6, NAU8825_SDM_EN, 0);
1952 }
1953 }
1954
1955 /* freq_out must be 256*Fs in order to achieve the best performance */
1956 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
1957 unsigned int freq_in, unsigned int freq_out)
1958 {
1959 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1960 struct nau8825_fll fll_param;
1961 int ret, fs;
1962
1963 fs = freq_out / 256;
1964 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
1965 if (ret < 0) {
1966 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
1967 return ret;
1968 }
1969 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1970 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1971 fll_param.fll_int, fll_param.clk_ref_div);
1972
1973 nau8825_fll_apply(nau8825, &fll_param);
1974 mdelay(2);
1975 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1976 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1977 return 0;
1978 }
1979
1980 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
1981 {
1982 int ret = 0;
1983
1984 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
1985 if (IS_ERR(nau8825->mclk)) {
1986 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
1987 return 0;
1988 }
1989
1990 if (!nau8825->mclk_freq) {
1991 ret = clk_prepare_enable(nau8825->mclk);
1992 if (ret) {
1993 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1994 return ret;
1995 }
1996 }
1997
1998 if (nau8825->mclk_freq != freq) {
1999 freq = clk_round_rate(nau8825->mclk, freq);
2000 ret = clk_set_rate(nau8825->mclk, freq);
2001 if (ret) {
2002 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2003 return ret;
2004 }
2005 nau8825->mclk_freq = freq;
2006 }
2007
2008 return 0;
2009 }
2010
2011 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2012 {
2013 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2014 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2015 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2016 NAU8825_DCO_EN, 0);
2017 }
2018
2019 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2020 unsigned int freq)
2021 {
2022 struct regmap *regmap = nau8825->regmap;
2023 int ret;
2024
2025 switch (clk_id) {
2026 case NAU8825_CLK_DIS:
2027 /* Clock provided externally and disable internal VCO clock */
2028 nau8825_configure_mclk_as_sysclk(regmap);
2029 if (nau8825->mclk_freq) {
2030 clk_disable_unprepare(nau8825->mclk);
2031 nau8825->mclk_freq = 0;
2032 }
2033
2034 break;
2035 case NAU8825_CLK_MCLK:
2036 /* Acquire the semaphone to synchronize the playback and
2037 * interrupt handler. In order to avoid the playback inter-
2038 * fered by cross talk process, the driver make the playback
2039 * preparation halted until cross talk process finish.
2040 */
2041 nau8825_sema_acquire(nau8825, 2 * HZ);
2042 nau8825_configure_mclk_as_sysclk(regmap);
2043 /* MCLK not changed by clock tree */
2044 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2045 NAU8825_CLK_MCLK_SRC_MASK, 0);
2046 /* Release the semaphone. */
2047 nau8825_sema_release(nau8825);
2048
2049 ret = nau8825_mclk_prepare(nau8825, freq);
2050 if (ret)
2051 return ret;
2052
2053 break;
2054 case NAU8825_CLK_INTERNAL:
2055 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2056 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2057 NAU8825_DCO_EN, NAU8825_DCO_EN);
2058 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2059 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2060 /* Decrease the VCO frequency for power saving */
2061 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2062 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2063 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2064 NAU8825_FLL_RATIO_MASK, 0x10);
2065 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2066 NAU8825_SDM_EN, NAU8825_SDM_EN);
2067 } else {
2068 /* The clock turns off intentionally for power saving
2069 * when no headset connected.
2070 */
2071 nau8825_configure_mclk_as_sysclk(regmap);
2072 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2073 }
2074 if (nau8825->mclk_freq) {
2075 clk_disable_unprepare(nau8825->mclk);
2076 nau8825->mclk_freq = 0;
2077 }
2078
2079 break;
2080 case NAU8825_CLK_FLL_MCLK:
2081 /* Acquire the semaphone to synchronize the playback and
2082 * interrupt handler. In order to avoid the playback inter-
2083 * fered by cross talk process, the driver make the playback
2084 * preparation halted until cross talk process finish.
2085 */
2086 nau8825_sema_acquire(nau8825, 2 * HZ);
2087 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2088 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
2089 /* Release the semaphone. */
2090 nau8825_sema_release(nau8825);
2091
2092 ret = nau8825_mclk_prepare(nau8825, freq);
2093 if (ret)
2094 return ret;
2095
2096 break;
2097 case NAU8825_CLK_FLL_BLK:
2098 /* Acquire the semaphone to synchronize the playback and
2099 * interrupt handler. In order to avoid the playback inter-
2100 * fered by cross talk process, the driver make the playback
2101 * preparation halted until cross talk process finish.
2102 */
2103 nau8825_sema_acquire(nau8825, 2 * HZ);
2104 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2105 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
2106 /* Release the semaphone. */
2107 nau8825_sema_release(nau8825);
2108
2109 if (nau8825->mclk_freq) {
2110 clk_disable_unprepare(nau8825->mclk);
2111 nau8825->mclk_freq = 0;
2112 }
2113
2114 break;
2115 case NAU8825_CLK_FLL_FS:
2116 /* Acquire the semaphone to synchronize the playback and
2117 * interrupt handler. In order to avoid the playback inter-
2118 * fered by cross talk process, the driver make the playback
2119 * preparation halted until cross talk process finish.
2120 */
2121 nau8825_sema_acquire(nau8825, 2 * HZ);
2122 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2123 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
2124 /* Release the semaphone. */
2125 nau8825_sema_release(nau8825);
2126
2127 if (nau8825->mclk_freq) {
2128 clk_disable_unprepare(nau8825->mclk);
2129 nau8825->mclk_freq = 0;
2130 }
2131
2132 break;
2133 default:
2134 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2135 return -EINVAL;
2136 }
2137
2138 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2139 clk_id);
2140 return 0;
2141 }
2142
2143 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2144 int source, unsigned int freq, int dir)
2145 {
2146 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2147
2148 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2149 }
2150
2151 static int nau8825_resume_setup(struct nau8825 *nau8825)
2152 {
2153 struct regmap *regmap = nau8825->regmap;
2154
2155 /* Close clock when jack type detection at manual mode */
2156 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2157
2158 /* Clear all interruption status */
2159 nau8825_int_status_clear_all(regmap);
2160
2161 /* Enable both insertion and ejection interruptions, and then
2162 * bypass de-bounce circuit.
2163 */
2164 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2165 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2166 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2167 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2168 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2169 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2170 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2171 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2172
2173 return 0;
2174 }
2175
2176 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2177 enum snd_soc_bias_level level)
2178 {
2179 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2180 int ret;
2181
2182 switch (level) {
2183 case SND_SOC_BIAS_ON:
2184 break;
2185
2186 case SND_SOC_BIAS_PREPARE:
2187 break;
2188
2189 case SND_SOC_BIAS_STANDBY:
2190 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2191 if (nau8825->mclk_freq) {
2192 ret = clk_prepare_enable(nau8825->mclk);
2193 if (ret) {
2194 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2195 return ret;
2196 }
2197 }
2198 /* Setup codec configuration after resume */
2199 nau8825_resume_setup(nau8825);
2200 }
2201 break;
2202
2203 case SND_SOC_BIAS_OFF:
2204 /* Cancel and reset cross talk detection funciton */
2205 nau8825_xtalk_cancel(nau8825);
2206 /* Turn off all interruptions before system shutdown. Keep the
2207 * interruption quiet before resume setup completes.
2208 */
2209 regmap_write(nau8825->regmap,
2210 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2211 /* Disable ADC needed for interruptions at audo mode */
2212 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2213 NAU8825_ENABLE_ADC, 0);
2214 if (nau8825->mclk_freq)
2215 clk_disable_unprepare(nau8825->mclk);
2216 break;
2217 }
2218 return 0;
2219 }
2220
2221 static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
2222 {
2223 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2224
2225 disable_irq(nau8825->irq);
2226 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2227 regcache_cache_only(nau8825->regmap, true);
2228 regcache_mark_dirty(nau8825->regmap);
2229
2230 return 0;
2231 }
2232
2233 static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
2234 {
2235 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2236 int ret;
2237
2238 regcache_cache_only(nau8825->regmap, false);
2239 regcache_sync(nau8825->regmap);
2240 nau8825->xtalk_protect = true;
2241 ret = nau8825_sema_acquire(nau8825, 0);
2242 if (ret < 0)
2243 nau8825->xtalk_protect = false;
2244 enable_irq(nau8825->irq);
2245
2246 return 0;
2247 }
2248
2249 static struct snd_soc_codec_driver nau8825_codec_driver = {
2250 .probe = nau8825_codec_probe,
2251 .remove = nau8825_codec_remove,
2252 .set_sysclk = nau8825_set_sysclk,
2253 .set_pll = nau8825_set_pll,
2254 .set_bias_level = nau8825_set_bias_level,
2255 .suspend_bias_off = true,
2256 .suspend = nau8825_suspend,
2257 .resume = nau8825_resume,
2258
2259 .component_driver = {
2260 .controls = nau8825_controls,
2261 .num_controls = ARRAY_SIZE(nau8825_controls),
2262 .dapm_widgets = nau8825_dapm_widgets,
2263 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2264 .dapm_routes = nau8825_dapm_routes,
2265 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2266 },
2267 };
2268
2269 static void nau8825_reset_chip(struct regmap *regmap)
2270 {
2271 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2272 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2273 }
2274
2275 static void nau8825_print_device_properties(struct nau8825 *nau8825)
2276 {
2277 int i;
2278 struct device *dev = nau8825->dev;
2279
2280 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2281 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2282 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2283 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2284 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2285 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2286
2287 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2288 for (i = 0; i < nau8825->sar_threshold_num; i++)
2289 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2290 nau8825->sar_threshold[i]);
2291
2292 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2293 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2294 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2295 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2296 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2297 dev_dbg(dev, "jack-insert-debounce: %d\n",
2298 nau8825->jack_insert_debounce);
2299 dev_dbg(dev, "jack-eject-debounce: %d\n",
2300 nau8825->jack_eject_debounce);
2301 }
2302
2303 static int nau8825_read_device_properties(struct device *dev,
2304 struct nau8825 *nau8825) {
2305
2306 nau8825->jkdet_enable = device_property_read_bool(dev,
2307 "nuvoton,jkdet-enable");
2308 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2309 "nuvoton,jkdet-pull-enable");
2310 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2311 "nuvoton,jkdet-pull-up");
2312 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2313 &nau8825->jkdet_polarity);
2314 device_property_read_u32(dev, "nuvoton,micbias-voltage",
2315 &nau8825->micbias_voltage);
2316 device_property_read_u32(dev, "nuvoton,vref-impedance",
2317 &nau8825->vref_impedance);
2318 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2319 &nau8825->sar_threshold_num);
2320 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2321 nau8825->sar_threshold, nau8825->sar_threshold_num);
2322 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2323 &nau8825->sar_hysteresis);
2324 device_property_read_u32(dev, "nuvoton,sar-voltage",
2325 &nau8825->sar_voltage);
2326 device_property_read_u32(dev, "nuvoton,sar-compare-time",
2327 &nau8825->sar_compare_time);
2328 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2329 &nau8825->sar_sampling_time);
2330 device_property_read_u32(dev, "nuvoton,short-key-debounce",
2331 &nau8825->key_debounce);
2332 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2333 &nau8825->jack_insert_debounce);
2334 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2335 &nau8825->jack_eject_debounce);
2336
2337 nau8825->mclk = devm_clk_get(dev, "mclk");
2338 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2339 return -EPROBE_DEFER;
2340 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2341 /* The MCLK is managed externally or not used at all */
2342 nau8825->mclk = NULL;
2343 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2344 } else if (IS_ERR(nau8825->mclk)) {
2345 return -EINVAL;
2346 }
2347
2348 return 0;
2349 }
2350
2351 static int nau8825_setup_irq(struct nau8825 *nau8825)
2352 {
2353 int ret;
2354
2355 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2356 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2357 "nau8825", nau8825);
2358
2359 if (ret) {
2360 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2361 nau8825->irq, ret);
2362 return ret;
2363 }
2364
2365 return 0;
2366 }
2367
2368 static int nau8825_i2c_probe(struct i2c_client *i2c,
2369 const struct i2c_device_id *id)
2370 {
2371 struct device *dev = &i2c->dev;
2372 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2373 int ret, value;
2374
2375 if (!nau8825) {
2376 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2377 if (!nau8825)
2378 return -ENOMEM;
2379 ret = nau8825_read_device_properties(dev, nau8825);
2380 if (ret)
2381 return ret;
2382 }
2383
2384 i2c_set_clientdata(i2c, nau8825);
2385
2386 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2387 if (IS_ERR(nau8825->regmap))
2388 return PTR_ERR(nau8825->regmap);
2389 nau8825->dev = dev;
2390 nau8825->irq = i2c->irq;
2391 /* Initiate parameters, semaphone and work queue which are needed in
2392 * cross talk suppression measurment function.
2393 */
2394 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2395 nau8825->xtalk_protect = false;
2396 sema_init(&nau8825->xtalk_sem, 1);
2397 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2398
2399 nau8825_print_device_properties(nau8825);
2400
2401 nau8825_reset_chip(nau8825->regmap);
2402 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2403 if (ret < 0) {
2404 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2405 ret);
2406 return ret;
2407 }
2408 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2409 NAU8825_SOFTWARE_ID_NAU8825) {
2410 dev_err(dev, "Not a NAU8825 chip\n");
2411 return -ENODEV;
2412 }
2413
2414 nau8825_init_regs(nau8825);
2415
2416 if (i2c->irq)
2417 nau8825_setup_irq(nau8825);
2418
2419 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2420 &nau8825_dai, 1);
2421 }
2422
2423 static int nau8825_i2c_remove(struct i2c_client *client)
2424 {
2425 snd_soc_unregister_codec(&client->dev);
2426 return 0;
2427 }
2428
2429 static const struct i2c_device_id nau8825_i2c_ids[] = {
2430 { "nau8825", 0 },
2431 { }
2432 };
2433 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2434
2435 #ifdef CONFIG_OF
2436 static const struct of_device_id nau8825_of_ids[] = {
2437 { .compatible = "nuvoton,nau8825", },
2438 {}
2439 };
2440 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2441 #endif
2442
2443 #ifdef CONFIG_ACPI
2444 static const struct acpi_device_id nau8825_acpi_match[] = {
2445 { "10508825", 0 },
2446 {},
2447 };
2448 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2449 #endif
2450
2451 static struct i2c_driver nau8825_driver = {
2452 .driver = {
2453 .name = "nau8825",
2454 .of_match_table = of_match_ptr(nau8825_of_ids),
2455 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2456 },
2457 .probe = nau8825_i2c_probe,
2458 .remove = nau8825_i2c_remove,
2459 .id_table = nau8825_i2c_ids,
2460 };
2461 module_i2c_driver(nau8825_driver);
2462
2463 MODULE_DESCRIPTION("ASoC nau8825 driver");
2464 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2465 MODULE_LICENSE("GPL");
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