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ASoC: rt5645: Lock mutex in rt5645_enable_push_button_irq
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / rt5645.c
1 /*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/acpi.h>
23 #include <linux/dmi.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/jack.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "rl6231.h"
34 #include "rt5645.h"
35
36 #define RT5645_DEVICE_ID 0x6308
37 #define RT5650_DEVICE_ID 0x6419
38
39 #define RT5645_PR_RANGE_BASE (0xff + 1)
40 #define RT5645_PR_SPACING 0x100
41
42 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
43
44 static const struct regmap_range_cfg rt5645_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5645_PR_BASE,
48 .range_max = RT5645_PR_BASE + 0xf8,
49 .selector_reg = RT5645_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5645_PRIV_DATA,
53 .window_len = 0x1,
54 },
55 };
56
57 static const struct reg_default init_list[] = {
58 {RT5645_PR_BASE + 0x3d, 0x3600},
59 {RT5645_PR_BASE + 0x1c, 0xfd20},
60 {RT5645_PR_BASE + 0x20, 0x611f},
61 {RT5645_PR_BASE + 0x21, 0x4040},
62 {RT5645_PR_BASE + 0x23, 0x0004},
63 };
64 #define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
65
66 static const struct reg_default rt5650_init_list[] = {
67 {0xf6, 0x0100},
68 };
69
70 static const struct reg_default rt5645_reg[] = {
71 { 0x00, 0x0000 },
72 { 0x01, 0xc8c8 },
73 { 0x02, 0xc8c8 },
74 { 0x03, 0xc8c8 },
75 { 0x0a, 0x0002 },
76 { 0x0b, 0x2827 },
77 { 0x0c, 0xe000 },
78 { 0x0d, 0x0000 },
79 { 0x0e, 0x0000 },
80 { 0x0f, 0x0808 },
81 { 0x14, 0x3333 },
82 { 0x16, 0x4b00 },
83 { 0x18, 0x018b },
84 { 0x19, 0xafaf },
85 { 0x1a, 0xafaf },
86 { 0x1b, 0x0001 },
87 { 0x1c, 0x2f2f },
88 { 0x1d, 0x2f2f },
89 { 0x1e, 0x0000 },
90 { 0x20, 0x0000 },
91 { 0x27, 0x7060 },
92 { 0x28, 0x7070 },
93 { 0x29, 0x8080 },
94 { 0x2a, 0x5656 },
95 { 0x2b, 0x5454 },
96 { 0x2c, 0xaaa0 },
97 { 0x2d, 0x0000 },
98 { 0x2f, 0x1002 },
99 { 0x31, 0x5000 },
100 { 0x32, 0x0000 },
101 { 0x33, 0x0000 },
102 { 0x34, 0x0000 },
103 { 0x35, 0x0000 },
104 { 0x3b, 0x0000 },
105 { 0x3c, 0x007f },
106 { 0x3d, 0x0000 },
107 { 0x3e, 0x007f },
108 { 0x3f, 0x0000 },
109 { 0x40, 0x001f },
110 { 0x41, 0x0000 },
111 { 0x42, 0x001f },
112 { 0x45, 0x6000 },
113 { 0x46, 0x003e },
114 { 0x47, 0x003e },
115 { 0x48, 0xf807 },
116 { 0x4a, 0x0004 },
117 { 0x4d, 0x0000 },
118 { 0x4e, 0x0000 },
119 { 0x4f, 0x01ff },
120 { 0x50, 0x0000 },
121 { 0x51, 0x0000 },
122 { 0x52, 0x01ff },
123 { 0x53, 0xf000 },
124 { 0x56, 0x0111 },
125 { 0x57, 0x0064 },
126 { 0x58, 0xef0e },
127 { 0x59, 0xf0f0 },
128 { 0x5a, 0xef0e },
129 { 0x5b, 0xf0f0 },
130 { 0x5c, 0xef0e },
131 { 0x5d, 0xf0f0 },
132 { 0x5e, 0xf000 },
133 { 0x5f, 0x0000 },
134 { 0x61, 0x0300 },
135 { 0x62, 0x0000 },
136 { 0x63, 0x00c2 },
137 { 0x64, 0x0000 },
138 { 0x65, 0x0000 },
139 { 0x66, 0x0000 },
140 { 0x6a, 0x0000 },
141 { 0x6c, 0x0aaa },
142 { 0x70, 0x8000 },
143 { 0x71, 0x8000 },
144 { 0x72, 0x8000 },
145 { 0x73, 0x7770 },
146 { 0x74, 0x3e00 },
147 { 0x75, 0x2409 },
148 { 0x76, 0x000a },
149 { 0x77, 0x0c00 },
150 { 0x78, 0x0000 },
151 { 0x79, 0x0123 },
152 { 0x80, 0x0000 },
153 { 0x81, 0x0000 },
154 { 0x82, 0x0000 },
155 { 0x83, 0x0000 },
156 { 0x84, 0x0000 },
157 { 0x85, 0x0000 },
158 { 0x8a, 0x0000 },
159 { 0x8e, 0x0004 },
160 { 0x8f, 0x1100 },
161 { 0x90, 0x0646 },
162 { 0x91, 0x0c06 },
163 { 0x93, 0x0000 },
164 { 0x94, 0x0200 },
165 { 0x95, 0x0000 },
166 { 0x9a, 0x2184 },
167 { 0x9b, 0x010a },
168 { 0x9c, 0x0aea },
169 { 0x9d, 0x000c },
170 { 0x9e, 0x0400 },
171 { 0xa0, 0xa0a8 },
172 { 0xa1, 0x0059 },
173 { 0xa2, 0x0001 },
174 { 0xae, 0x6000 },
175 { 0xaf, 0x0000 },
176 { 0xb0, 0x6000 },
177 { 0xb1, 0x0000 },
178 { 0xb2, 0x0000 },
179 { 0xb3, 0x001f },
180 { 0xb4, 0x020c },
181 { 0xb5, 0x1f00 },
182 { 0xb6, 0x0000 },
183 { 0xbb, 0x0000 },
184 { 0xbc, 0x0000 },
185 { 0xbd, 0x0000 },
186 { 0xbe, 0x0000 },
187 { 0xbf, 0x3100 },
188 { 0xc0, 0x0000 },
189 { 0xc1, 0x0000 },
190 { 0xc2, 0x0000 },
191 { 0xc3, 0x2000 },
192 { 0xcd, 0x0000 },
193 { 0xce, 0x0000 },
194 { 0xcf, 0x1813 },
195 { 0xd0, 0x0690 },
196 { 0xd1, 0x1c17 },
197 { 0xd3, 0xb320 },
198 { 0xd4, 0x0000 },
199 { 0xd6, 0x0400 },
200 { 0xd9, 0x0809 },
201 { 0xda, 0x0000 },
202 { 0xdb, 0x0003 },
203 { 0xdc, 0x0049 },
204 { 0xdd, 0x001b },
205 { 0xdf, 0x0008 },
206 { 0xe0, 0x4000 },
207 { 0xe6, 0x8000 },
208 { 0xe7, 0x0200 },
209 { 0xec, 0xb300 },
210 { 0xed, 0x0000 },
211 { 0xf0, 0x001f },
212 { 0xf1, 0x020c },
213 { 0xf2, 0x1f00 },
214 { 0xf3, 0x0000 },
215 { 0xf4, 0x4000 },
216 { 0xf8, 0x0000 },
217 { 0xf9, 0x0000 },
218 { 0xfa, 0x2060 },
219 { 0xfb, 0x4040 },
220 { 0xfc, 0x0000 },
221 { 0xfd, 0x0002 },
222 { 0xfe, 0x10ec },
223 { 0xff, 0x6308 },
224 };
225
226 static int rt5645_reset(struct snd_soc_codec *codec)
227 {
228 return snd_soc_write(codec, RT5645_RESET, 0);
229 }
230
231 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
232 {
233 int i;
234
235 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
236 if (reg >= rt5645_ranges[i].range_min &&
237 reg <= rt5645_ranges[i].range_max) {
238 return true;
239 }
240 }
241
242 switch (reg) {
243 case RT5645_RESET:
244 case RT5645_PRIV_DATA:
245 case RT5645_IN1_CTRL1:
246 case RT5645_IN1_CTRL2:
247 case RT5645_IN1_CTRL3:
248 case RT5645_A_JD_CTRL1:
249 case RT5645_ADC_EQ_CTRL1:
250 case RT5645_EQ_CTRL1:
251 case RT5645_ALC_CTRL_1:
252 case RT5645_IRQ_CTRL2:
253 case RT5645_IRQ_CTRL3:
254 case RT5645_INT_IRQ_ST:
255 case RT5645_IL_CMD:
256 case RT5650_4BTN_IL_CMD1:
257 case RT5645_VENDOR_ID:
258 case RT5645_VENDOR_ID1:
259 case RT5645_VENDOR_ID2:
260 return true;
261 default:
262 return false;
263 }
264 }
265
266 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
267 {
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
271 if (reg >= rt5645_ranges[i].range_min &&
272 reg <= rt5645_ranges[i].range_max) {
273 return true;
274 }
275 }
276
277 switch (reg) {
278 case RT5645_RESET:
279 case RT5645_SPK_VOL:
280 case RT5645_HP_VOL:
281 case RT5645_LOUT1:
282 case RT5645_IN1_CTRL1:
283 case RT5645_IN1_CTRL2:
284 case RT5645_IN1_CTRL3:
285 case RT5645_IN2_CTRL:
286 case RT5645_INL1_INR1_VOL:
287 case RT5645_SPK_FUNC_LIM:
288 case RT5645_ADJ_HPF_CTRL:
289 case RT5645_DAC1_DIG_VOL:
290 case RT5645_DAC2_DIG_VOL:
291 case RT5645_DAC_CTRL:
292 case RT5645_STO1_ADC_DIG_VOL:
293 case RT5645_MONO_ADC_DIG_VOL:
294 case RT5645_ADC_BST_VOL1:
295 case RT5645_ADC_BST_VOL2:
296 case RT5645_STO1_ADC_MIXER:
297 case RT5645_MONO_ADC_MIXER:
298 case RT5645_AD_DA_MIXER:
299 case RT5645_STO_DAC_MIXER:
300 case RT5645_MONO_DAC_MIXER:
301 case RT5645_DIG_MIXER:
302 case RT5650_A_DAC_SOUR:
303 case RT5645_DIG_INF1_DATA:
304 case RT5645_PDM_OUT_CTRL:
305 case RT5645_REC_L1_MIXER:
306 case RT5645_REC_L2_MIXER:
307 case RT5645_REC_R1_MIXER:
308 case RT5645_REC_R2_MIXER:
309 case RT5645_HPMIXL_CTRL:
310 case RT5645_HPOMIXL_CTRL:
311 case RT5645_HPMIXR_CTRL:
312 case RT5645_HPOMIXR_CTRL:
313 case RT5645_HPO_MIXER:
314 case RT5645_SPK_L_MIXER:
315 case RT5645_SPK_R_MIXER:
316 case RT5645_SPO_MIXER:
317 case RT5645_SPO_CLSD_RATIO:
318 case RT5645_OUT_L1_MIXER:
319 case RT5645_OUT_R1_MIXER:
320 case RT5645_OUT_L_GAIN1:
321 case RT5645_OUT_L_GAIN2:
322 case RT5645_OUT_R_GAIN1:
323 case RT5645_OUT_R_GAIN2:
324 case RT5645_LOUT_MIXER:
325 case RT5645_HAPTIC_CTRL1:
326 case RT5645_HAPTIC_CTRL2:
327 case RT5645_HAPTIC_CTRL3:
328 case RT5645_HAPTIC_CTRL4:
329 case RT5645_HAPTIC_CTRL5:
330 case RT5645_HAPTIC_CTRL6:
331 case RT5645_HAPTIC_CTRL7:
332 case RT5645_HAPTIC_CTRL8:
333 case RT5645_HAPTIC_CTRL9:
334 case RT5645_HAPTIC_CTRL10:
335 case RT5645_PWR_DIG1:
336 case RT5645_PWR_DIG2:
337 case RT5645_PWR_ANLG1:
338 case RT5645_PWR_ANLG2:
339 case RT5645_PWR_MIXER:
340 case RT5645_PWR_VOL:
341 case RT5645_PRIV_INDEX:
342 case RT5645_PRIV_DATA:
343 case RT5645_I2S1_SDP:
344 case RT5645_I2S2_SDP:
345 case RT5645_ADDA_CLK1:
346 case RT5645_ADDA_CLK2:
347 case RT5645_DMIC_CTRL1:
348 case RT5645_DMIC_CTRL2:
349 case RT5645_TDM_CTRL_1:
350 case RT5645_TDM_CTRL_2:
351 case RT5645_TDM_CTRL_3:
352 case RT5645_GLB_CLK:
353 case RT5645_PLL_CTRL1:
354 case RT5645_PLL_CTRL2:
355 case RT5645_ASRC_1:
356 case RT5645_ASRC_2:
357 case RT5645_ASRC_3:
358 case RT5645_ASRC_4:
359 case RT5645_DEPOP_M1:
360 case RT5645_DEPOP_M2:
361 case RT5645_DEPOP_M3:
362 case RT5645_MICBIAS:
363 case RT5645_A_JD_CTRL1:
364 case RT5645_VAD_CTRL4:
365 case RT5645_CLSD_OUT_CTRL:
366 case RT5645_ADC_EQ_CTRL1:
367 case RT5645_ADC_EQ_CTRL2:
368 case RT5645_EQ_CTRL1:
369 case RT5645_EQ_CTRL2:
370 case RT5645_ALC_CTRL_1:
371 case RT5645_ALC_CTRL_2:
372 case RT5645_ALC_CTRL_3:
373 case RT5645_ALC_CTRL_4:
374 case RT5645_ALC_CTRL_5:
375 case RT5645_JD_CTRL:
376 case RT5645_IRQ_CTRL1:
377 case RT5645_IRQ_CTRL2:
378 case RT5645_IRQ_CTRL3:
379 case RT5645_INT_IRQ_ST:
380 case RT5645_GPIO_CTRL1:
381 case RT5645_GPIO_CTRL2:
382 case RT5645_GPIO_CTRL3:
383 case RT5645_BASS_BACK:
384 case RT5645_MP3_PLUS1:
385 case RT5645_MP3_PLUS2:
386 case RT5645_ADJ_HPF1:
387 case RT5645_ADJ_HPF2:
388 case RT5645_HP_CALIB_AMP_DET:
389 case RT5645_SV_ZCD1:
390 case RT5645_SV_ZCD2:
391 case RT5645_IL_CMD:
392 case RT5645_IL_CMD2:
393 case RT5645_IL_CMD3:
394 case RT5650_4BTN_IL_CMD1:
395 case RT5650_4BTN_IL_CMD2:
396 case RT5645_DRC1_HL_CTRL1:
397 case RT5645_DRC2_HL_CTRL1:
398 case RT5645_ADC_MONO_HP_CTRL1:
399 case RT5645_ADC_MONO_HP_CTRL2:
400 case RT5645_DRC2_CTRL1:
401 case RT5645_DRC2_CTRL2:
402 case RT5645_DRC2_CTRL3:
403 case RT5645_DRC2_CTRL4:
404 case RT5645_DRC2_CTRL5:
405 case RT5645_JD_CTRL3:
406 case RT5645_JD_CTRL4:
407 case RT5645_GEN_CTRL1:
408 case RT5645_GEN_CTRL2:
409 case RT5645_GEN_CTRL3:
410 case RT5645_VENDOR_ID:
411 case RT5645_VENDOR_ID1:
412 case RT5645_VENDOR_ID2:
413 return true;
414 default:
415 return false;
416 }
417 }
418
419 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
420 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
421 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
422 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
423 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
424
425 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
426 static unsigned int bst_tlv[] = {
427 TLV_DB_RANGE_HEAD(7),
428 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
429 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
430 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
431 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
432 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
433 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
434 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
435 };
436
437 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
438 /* Speaker Output Volume */
439 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
440 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
441 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
442 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
443
444 /* Headphone Output Volume */
445 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
446 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
447 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
448 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
449
450 /* OUTPUT Control */
451 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
452 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
453 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
454 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
455 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
456 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
457
458 /* DAC Digital Volume */
459 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
460 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
461 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
462 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
463 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
464 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
465
466 /* IN1/IN2 Control */
467 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
468 RT5645_BST_SFT1, 8, 0, bst_tlv),
469 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
470 RT5645_BST_SFT2, 8, 0, bst_tlv),
471
472 /* INL/INR Volume Control */
473 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
474 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
475
476 /* ADC Digital Volume Control */
477 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
478 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
479 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
480 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
481 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
482 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
483 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
484 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
485
486 /* ADC Boost Volume Control */
487 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
488 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
489 adc_bst_tlv),
490 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
491 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
492 adc_bst_tlv),
493
494 /* I2S2 function select */
495 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
496 1, 1),
497 };
498
499 /**
500 * set_dmic_clk - Set parameter of dmic.
501 *
502 * @w: DAPM widget.
503 * @kcontrol: The kcontrol of this widget.
504 * @event: Event id.
505 *
506 */
507 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
508 struct snd_kcontrol *kcontrol, int event)
509 {
510 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
511 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
512 int idx = -EINVAL;
513
514 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
515
516 if (idx < 0)
517 dev_err(codec->dev, "Failed to set DMIC clock\n");
518 else
519 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
520 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
521 return idx;
522 }
523
524 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
525 struct snd_soc_dapm_widget *sink)
526 {
527 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
528 unsigned int val;
529
530 val = snd_soc_read(codec, RT5645_GLB_CLK);
531 val &= RT5645_SCLK_SRC_MASK;
532 if (val == RT5645_SCLK_SRC_PLL1)
533 return 1;
534 else
535 return 0;
536 }
537
538 static int is_using_asrc(struct snd_soc_dapm_widget *source,
539 struct snd_soc_dapm_widget *sink)
540 {
541 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
542 unsigned int reg, shift, val;
543
544 switch (source->shift) {
545 case 0:
546 reg = RT5645_ASRC_3;
547 shift = 0;
548 break;
549 case 1:
550 reg = RT5645_ASRC_3;
551 shift = 4;
552 break;
553 case 3:
554 reg = RT5645_ASRC_2;
555 shift = 0;
556 break;
557 case 8:
558 reg = RT5645_ASRC_2;
559 shift = 4;
560 break;
561 case 9:
562 reg = RT5645_ASRC_2;
563 shift = 8;
564 break;
565 case 10:
566 reg = RT5645_ASRC_2;
567 shift = 12;
568 break;
569 default:
570 return 0;
571 }
572
573 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
574 switch (val) {
575 case 1:
576 case 2:
577 case 3:
578 case 4:
579 return 1;
580 default:
581 return 0;
582 }
583
584 }
585
586 /**
587 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
588 * @codec: SoC audio codec device.
589 * @filter_mask: mask of filters.
590 * @clk_src: clock source
591 *
592 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
593 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
594 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
595 * ASRC function will track i2s clock and generate a corresponding system clock
596 * for codec. This function provides an API to select the clock source for a
597 * set of filters specified by the mask. And the codec driver will turn on ASRC
598 * for these filters if ASRC is selected as their clock source.
599 */
600 int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
601 unsigned int filter_mask, unsigned int clk_src)
602 {
603 unsigned int asrc2_mask = 0;
604 unsigned int asrc2_value = 0;
605 unsigned int asrc3_mask = 0;
606 unsigned int asrc3_value = 0;
607
608 switch (clk_src) {
609 case RT5645_CLK_SEL_SYS:
610 case RT5645_CLK_SEL_I2S1_ASRC:
611 case RT5645_CLK_SEL_I2S2_ASRC:
612 case RT5645_CLK_SEL_SYS2:
613 break;
614
615 default:
616 return -EINVAL;
617 }
618
619 if (filter_mask & RT5645_DA_STEREO_FILTER) {
620 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
621 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
622 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
623 }
624
625 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
626 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
627 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
628 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
629 }
630
631 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
632 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
633 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
634 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
635 }
636
637 if (filter_mask & RT5645_AD_STEREO_FILTER) {
638 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
639 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
640 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
641 }
642
643 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
644 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
645 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
646 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
647 }
648
649 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
650 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
651 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
652 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
653 }
654
655 if (asrc2_mask)
656 snd_soc_update_bits(codec, RT5645_ASRC_2,
657 asrc2_mask, asrc2_value);
658
659 if (asrc3_mask)
660 snd_soc_update_bits(codec, RT5645_ASRC_3,
661 asrc3_mask, asrc3_value);
662
663 return 0;
664 }
665 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
666
667 /* Digital Mixer */
668 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
669 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
670 RT5645_M_ADC_L1_SFT, 1, 1),
671 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
672 RT5645_M_ADC_L2_SFT, 1, 1),
673 };
674
675 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
676 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
677 RT5645_M_ADC_R1_SFT, 1, 1),
678 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
679 RT5645_M_ADC_R2_SFT, 1, 1),
680 };
681
682 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
683 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
684 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
685 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
686 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
687 };
688
689 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
690 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
691 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
692 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
693 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
694 };
695
696 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
697 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
698 RT5645_M_ADCMIX_L_SFT, 1, 1),
699 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
700 RT5645_M_DAC1_L_SFT, 1, 1),
701 };
702
703 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
704 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
705 RT5645_M_ADCMIX_R_SFT, 1, 1),
706 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
707 RT5645_M_DAC1_R_SFT, 1, 1),
708 };
709
710 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
711 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
712 RT5645_M_DAC_L1_SFT, 1, 1),
713 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
714 RT5645_M_DAC_L2_SFT, 1, 1),
715 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
716 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
717 };
718
719 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
720 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
721 RT5645_M_DAC_R1_SFT, 1, 1),
722 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
723 RT5645_M_DAC_R2_SFT, 1, 1),
724 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
725 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
726 };
727
728 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
729 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
730 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
731 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
732 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
733 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
734 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
735 };
736
737 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
738 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
739 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
740 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
741 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
742 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
743 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
744 };
745
746 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
747 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
748 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
749 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
750 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
751 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
752 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
753 };
754
755 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
756 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
757 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
758 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
759 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
760 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
761 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
762 };
763
764 /* Analog Input Mixer */
765 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
766 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
767 RT5645_M_HP_L_RM_L_SFT, 1, 1),
768 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
769 RT5645_M_IN_L_RM_L_SFT, 1, 1),
770 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
771 RT5645_M_BST2_RM_L_SFT, 1, 1),
772 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
773 RT5645_M_BST1_RM_L_SFT, 1, 1),
774 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
775 RT5645_M_OM_L_RM_L_SFT, 1, 1),
776 };
777
778 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
779 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
780 RT5645_M_HP_R_RM_R_SFT, 1, 1),
781 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
782 RT5645_M_IN_R_RM_R_SFT, 1, 1),
783 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
784 RT5645_M_BST2_RM_R_SFT, 1, 1),
785 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
786 RT5645_M_BST1_RM_R_SFT, 1, 1),
787 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
788 RT5645_M_OM_R_RM_R_SFT, 1, 1),
789 };
790
791 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
792 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
793 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
794 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
795 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
796 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
797 RT5645_M_IN_L_SM_L_SFT, 1, 1),
798 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
799 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
800 };
801
802 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
803 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
804 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
805 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
806 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
807 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
808 RT5645_M_IN_R_SM_R_SFT, 1, 1),
809 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
810 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
811 };
812
813 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
814 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
815 RT5645_M_BST1_OM_L_SFT, 1, 1),
816 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
817 RT5645_M_IN_L_OM_L_SFT, 1, 1),
818 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
819 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
820 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
821 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
822 };
823
824 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
825 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
826 RT5645_M_BST2_OM_R_SFT, 1, 1),
827 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
828 RT5645_M_IN_R_OM_R_SFT, 1, 1),
829 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
830 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
831 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
832 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
833 };
834
835 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
836 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
837 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
838 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
839 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
840 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
841 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
842 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
843 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
844 };
845
846 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
847 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
848 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
849 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
850 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
851 };
852
853 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
854 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
855 RT5645_M_DAC1_HM_SFT, 1, 1),
856 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
857 RT5645_M_HPVOL_HM_SFT, 1, 1),
858 };
859
860 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
861 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
862 RT5645_M_DAC1_HV_SFT, 1, 1),
863 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
864 RT5645_M_DAC2_HV_SFT, 1, 1),
865 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
866 RT5645_M_IN_HV_SFT, 1, 1),
867 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
868 RT5645_M_BST1_HV_SFT, 1, 1),
869 };
870
871 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
872 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
873 RT5645_M_DAC1_HV_SFT, 1, 1),
874 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
875 RT5645_M_DAC2_HV_SFT, 1, 1),
876 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
877 RT5645_M_IN_HV_SFT, 1, 1),
878 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
879 RT5645_M_BST2_HV_SFT, 1, 1),
880 };
881
882 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
883 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
884 RT5645_M_DAC_L1_LM_SFT, 1, 1),
885 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
886 RT5645_M_DAC_R1_LM_SFT, 1, 1),
887 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
888 RT5645_M_OV_L_LM_SFT, 1, 1),
889 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
890 RT5645_M_OV_R_LM_SFT, 1, 1),
891 };
892
893 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
894 static const char * const rt5645_dac1_src[] = {
895 "IF1 DAC", "IF2 DAC", "IF3 DAC"
896 };
897
898 static SOC_ENUM_SINGLE_DECL(
899 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
900 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
901
902 static const struct snd_kcontrol_new rt5645_dac1l_mux =
903 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
904
905 static SOC_ENUM_SINGLE_DECL(
906 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
907 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
908
909 static const struct snd_kcontrol_new rt5645_dac1r_mux =
910 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
911
912 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
913 static const char * const rt5645_dac12_src[] = {
914 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
915 };
916
917 static SOC_ENUM_SINGLE_DECL(
918 rt5645_dac2l_enum, RT5645_DAC_CTRL,
919 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
920
921 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
922 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
923
924 static const char * const rt5645_dacr2_src[] = {
925 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
926 };
927
928 static SOC_ENUM_SINGLE_DECL(
929 rt5645_dac2r_enum, RT5645_DAC_CTRL,
930 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
931
932 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
933 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
934
935
936 /* INL/R source */
937 static const char * const rt5645_inl_src[] = {
938 "IN2P", "MonoP"
939 };
940
941 static SOC_ENUM_SINGLE_DECL(
942 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
943 RT5645_INL_SEL_SFT, rt5645_inl_src);
944
945 static const struct snd_kcontrol_new rt5645_inl_mux =
946 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
947
948 static const char * const rt5645_inr_src[] = {
949 "IN2N", "MonoN"
950 };
951
952 static SOC_ENUM_SINGLE_DECL(
953 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
954 RT5645_INR_SEL_SFT, rt5645_inr_src);
955
956 static const struct snd_kcontrol_new rt5645_inr_mux =
957 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
958
959 /* Stereo1 ADC source */
960 /* MX-27 [12] */
961 static const char * const rt5645_stereo_adc1_src[] = {
962 "DAC MIX", "ADC"
963 };
964
965 static SOC_ENUM_SINGLE_DECL(
966 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
967 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
968
969 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
970 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
971
972 /* MX-27 [11] */
973 static const char * const rt5645_stereo_adc2_src[] = {
974 "DAC MIX", "DMIC"
975 };
976
977 static SOC_ENUM_SINGLE_DECL(
978 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
979 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
980
981 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
982 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
983
984 /* MX-27 [8] */
985 static const char * const rt5645_stereo_dmic_src[] = {
986 "DMIC1", "DMIC2"
987 };
988
989 static SOC_ENUM_SINGLE_DECL(
990 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
991 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
992
993 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
994 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
995
996 /* Mono ADC source */
997 /* MX-28 [12] */
998 static const char * const rt5645_mono_adc_l1_src[] = {
999 "Mono DAC MIXL", "ADC"
1000 };
1001
1002 static SOC_ENUM_SINGLE_DECL(
1003 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1004 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1005
1006 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1007 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1008 /* MX-28 [11] */
1009 static const char * const rt5645_mono_adc_l2_src[] = {
1010 "Mono DAC MIXL", "DMIC"
1011 };
1012
1013 static SOC_ENUM_SINGLE_DECL(
1014 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1015 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1016
1017 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1018 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1019
1020 /* MX-28 [8] */
1021 static const char * const rt5645_mono_dmic_src[] = {
1022 "DMIC1", "DMIC2"
1023 };
1024
1025 static SOC_ENUM_SINGLE_DECL(
1026 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1027 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1028
1029 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1030 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1031 /* MX-28 [1:0] */
1032 static SOC_ENUM_SINGLE_DECL(
1033 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1034 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1035
1036 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1037 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1038 /* MX-28 [4] */
1039 static const char * const rt5645_mono_adc_r1_src[] = {
1040 "Mono DAC MIXR", "ADC"
1041 };
1042
1043 static SOC_ENUM_SINGLE_DECL(
1044 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1045 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1046
1047 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1048 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1049 /* MX-28 [3] */
1050 static const char * const rt5645_mono_adc_r2_src[] = {
1051 "Mono DAC MIXR", "DMIC"
1052 };
1053
1054 static SOC_ENUM_SINGLE_DECL(
1055 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1056 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1057
1058 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1059 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1060
1061 /* MX-77 [9:8] */
1062 static const char * const rt5645_if1_adc_in_src[] = {
1063 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1064 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1065 };
1066
1067 static SOC_ENUM_SINGLE_DECL(
1068 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1069 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1070
1071 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1072 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1073
1074 /* MX-78 [4:0] */
1075 static const char * const rt5650_if1_adc_in_src[] = {
1076 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1077 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1078 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1079 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1080 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1081 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1082
1083 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1084 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1085 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1086 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1087 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1088 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1089
1090 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1091 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1092 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1093 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1094 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1095 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1096
1097 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1098 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1099 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1100 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1101 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1102 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1103 };
1104
1105 static SOC_ENUM_SINGLE_DECL(
1106 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1107 0, rt5650_if1_adc_in_src);
1108
1109 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1110 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1111
1112 /* MX-78 [15:14][13:12][11:10] */
1113 static const char * const rt5645_tdm_adc_swap_select[] = {
1114 "L/R", "R/L", "L/L", "R/R"
1115 };
1116
1117 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1118 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1119
1120 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1121 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1122
1123 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1124 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1125
1126 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1127 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1128
1129 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1130 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1131
1132 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1133 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1134
1135 /* MX-77 [7:6][5:4][3:2] */
1136 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1137 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1138
1139 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1140 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1141
1142 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1143 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1144
1145 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1146 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1147
1148 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1149 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1150
1151 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1152 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1153
1154 /* MX-79 [14:12][10:8][6:4][2:0] */
1155 static const char * const rt5645_tdm_dac_swap_select[] = {
1156 "Slot0", "Slot1", "Slot2", "Slot3"
1157 };
1158
1159 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1160 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1161
1162 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1163 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1164
1165 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1166 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1167
1168 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1169 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1170
1171 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1172 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1173
1174 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1175 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1176
1177 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1178 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1179
1180 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1181 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1182
1183 /* MX-7a [14:12][10:8][6:4][2:0] */
1184 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1185 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1186
1187 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1188 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1189
1190 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1191 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1192
1193 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1194 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1195
1196 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1197 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1198
1199 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1200 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1201
1202 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1203 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1204
1205 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1206 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1207
1208 /* MX-2d [3] [2] */
1209 static const char * const rt5650_a_dac1_src[] = {
1210 "DAC1", "Stereo DAC Mixer"
1211 };
1212
1213 static SOC_ENUM_SINGLE_DECL(
1214 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1215 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1216
1217 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1218 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1219
1220 static SOC_ENUM_SINGLE_DECL(
1221 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1222 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1223
1224 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1225 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1226
1227 /* MX-2d [1] [0] */
1228 static const char * const rt5650_a_dac2_src[] = {
1229 "Stereo DAC Mixer", "Mono DAC Mixer"
1230 };
1231
1232 static SOC_ENUM_SINGLE_DECL(
1233 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1234 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1235
1236 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1237 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1238
1239 static SOC_ENUM_SINGLE_DECL(
1240 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1241 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1242
1243 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1244 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1245
1246 /* MX-2F [13:12] */
1247 static const char * const rt5645_if2_adc_in_src[] = {
1248 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1249 };
1250
1251 static SOC_ENUM_SINGLE_DECL(
1252 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1253 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1254
1255 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1256 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1257
1258 /* MX-2F [1:0] */
1259 static const char * const rt5645_if3_adc_in_src[] = {
1260 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1261 };
1262
1263 static SOC_ENUM_SINGLE_DECL(
1264 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1265 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1266
1267 static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1268 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1269
1270 /* MX-31 [15] [13] [11] [9] */
1271 static const char * const rt5645_pdm_src[] = {
1272 "Mono DAC", "Stereo DAC"
1273 };
1274
1275 static SOC_ENUM_SINGLE_DECL(
1276 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1277 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1278
1279 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1280 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1281
1282 static SOC_ENUM_SINGLE_DECL(
1283 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1284 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1285
1286 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1287 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1288
1289 /* MX-9D [9:8] */
1290 static const char * const rt5645_vad_adc_src[] = {
1291 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1292 };
1293
1294 static SOC_ENUM_SINGLE_DECL(
1295 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1296 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1297
1298 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1299 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1300
1301 static const struct snd_kcontrol_new spk_l_vol_control =
1302 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1303 RT5645_L_MUTE_SFT, 1, 1);
1304
1305 static const struct snd_kcontrol_new spk_r_vol_control =
1306 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1307 RT5645_R_MUTE_SFT, 1, 1);
1308
1309 static const struct snd_kcontrol_new hp_l_vol_control =
1310 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1311 RT5645_L_MUTE_SFT, 1, 1);
1312
1313 static const struct snd_kcontrol_new hp_r_vol_control =
1314 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1315 RT5645_R_MUTE_SFT, 1, 1);
1316
1317 static const struct snd_kcontrol_new pdm1_l_vol_control =
1318 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1319 RT5645_M_PDM1_L, 1, 1);
1320
1321 static const struct snd_kcontrol_new pdm1_r_vol_control =
1322 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1323 RT5645_M_PDM1_R, 1, 1);
1324
1325 static void hp_amp_power(struct snd_soc_codec *codec, int on)
1326 {
1327 static int hp_amp_power_count;
1328 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1329
1330 if (on) {
1331 if (hp_amp_power_count <= 0) {
1332 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1333 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1334 0x0e06);
1335 snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d);
1336 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1337 0x3e, 0x7400);
1338 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1339 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1340 RT5645_MAMP_INT_REG2, 0xfc00);
1341 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1342 } else {
1343 /* depop parameters */
1344 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1345 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1346 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1347 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1348 RT5645_HP_DCC_INT1, 0x9f01);
1349 mdelay(150);
1350 /* headphone amp power on */
1351 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1352 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1353 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1354 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1355 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1356 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1357 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1358 RT5645_PWR_HA,
1359 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1360 RT5645_PWR_HA);
1361 mdelay(5);
1362 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1363 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1364 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1365
1366 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1367 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1368 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1369 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1370 0x14, 0x1aaa);
1371 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1372 0x24, 0x0430);
1373 }
1374 }
1375 hp_amp_power_count++;
1376 } else {
1377 hp_amp_power_count--;
1378 if (hp_amp_power_count <= 0) {
1379 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1380 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1381 0x3e, 0x7400);
1382 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1383 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1384 RT5645_MAMP_INT_REG2, 0xfc00);
1385 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1386 msleep(100);
1387 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1388
1389 } else {
1390 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1391 RT5645_HP_SG_MASK |
1392 RT5645_HP_L_SMT_MASK |
1393 RT5645_HP_R_SMT_MASK,
1394 RT5645_HP_SG_DIS |
1395 RT5645_HP_L_SMT_DIS |
1396 RT5645_HP_R_SMT_DIS);
1397 /* headphone amp power down */
1398 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1399 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1400 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1401 RT5645_PWR_HA, 0);
1402 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1403 RT5645_DEPOP_MASK, 0);
1404 }
1405 }
1406 }
1407 }
1408
1409 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1410 struct snd_kcontrol *kcontrol, int event)
1411 {
1412 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1413 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1414
1415 switch (event) {
1416 case SND_SOC_DAPM_POST_PMU:
1417 hp_amp_power(codec, 1);
1418 /* headphone unmute sequence */
1419 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1420 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1421 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1422 RT5645_CP_FQ3_MASK,
1423 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1424 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1425 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1426 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1427 RT5645_MAMP_INT_REG2, 0xfc00);
1428 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1429 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1430 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1431 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1432 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1433 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1434 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1435 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1436 msleep(40);
1437 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1438 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1439 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1440 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1441 }
1442 break;
1443
1444 case SND_SOC_DAPM_PRE_PMD:
1445 /* headphone mute sequence */
1446 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1447 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1448 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1449 RT5645_CP_FQ3_MASK,
1450 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1451 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1452 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1453 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1454 RT5645_MAMP_INT_REG2, 0xfc00);
1455 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1456 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1457 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1458 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1459 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1460 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1461 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1462 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1463 msleep(30);
1464 }
1465 hp_amp_power(codec, 0);
1466 break;
1467
1468 default:
1469 return 0;
1470 }
1471
1472 return 0;
1473 }
1474
1475 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1476 struct snd_kcontrol *kcontrol, int event)
1477 {
1478 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1479
1480 switch (event) {
1481 case SND_SOC_DAPM_POST_PMU:
1482 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1483 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1484 RT5645_PWR_CLS_D_L,
1485 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1486 RT5645_PWR_CLS_D_L);
1487 break;
1488
1489 case SND_SOC_DAPM_PRE_PMD:
1490 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1491 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1492 RT5645_PWR_CLS_D_L, 0);
1493 break;
1494
1495 default:
1496 return 0;
1497 }
1498
1499 return 0;
1500 }
1501
1502 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1503 struct snd_kcontrol *kcontrol, int event)
1504 {
1505 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1506
1507 switch (event) {
1508 case SND_SOC_DAPM_POST_PMU:
1509 hp_amp_power(codec, 1);
1510 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1511 RT5645_PWR_LM, RT5645_PWR_LM);
1512 snd_soc_update_bits(codec, RT5645_LOUT1,
1513 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1514 break;
1515
1516 case SND_SOC_DAPM_PRE_PMD:
1517 snd_soc_update_bits(codec, RT5645_LOUT1,
1518 RT5645_L_MUTE | RT5645_R_MUTE,
1519 RT5645_L_MUTE | RT5645_R_MUTE);
1520 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1521 RT5645_PWR_LM, 0);
1522 hp_amp_power(codec, 0);
1523 break;
1524
1525 default:
1526 return 0;
1527 }
1528
1529 return 0;
1530 }
1531
1532 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1533 struct snd_kcontrol *kcontrol, int event)
1534 {
1535 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1536
1537 switch (event) {
1538 case SND_SOC_DAPM_POST_PMU:
1539 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1540 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1541 break;
1542
1543 case SND_SOC_DAPM_PRE_PMD:
1544 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1545 RT5645_PWR_BST2_P, 0);
1546 break;
1547
1548 default:
1549 return 0;
1550 }
1551
1552 return 0;
1553 }
1554
1555 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1556 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1557 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1558 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1559 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1560
1561 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1562 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1563 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1564 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1565
1566 /* ASRC */
1567 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1568 11, 0, NULL, 0),
1569 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1570 12, 0, NULL, 0),
1571 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1572 10, 0, NULL, 0),
1573 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1574 9, 0, NULL, 0),
1575 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1576 8, 0, NULL, 0),
1577 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1578 7, 0, NULL, 0),
1579 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1580 5, 0, NULL, 0),
1581 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1582 4, 0, NULL, 0),
1583 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1584 3, 0, NULL, 0),
1585 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1586 1, 0, NULL, 0),
1587 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1588 0, 0, NULL, 0),
1589
1590 /* Input Side */
1591 /* micbias */
1592 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1593 RT5645_PWR_MB1_BIT, 0),
1594 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1595 RT5645_PWR_MB2_BIT, 0),
1596 /* Input Lines */
1597 SND_SOC_DAPM_INPUT("DMIC L1"),
1598 SND_SOC_DAPM_INPUT("DMIC R1"),
1599 SND_SOC_DAPM_INPUT("DMIC L2"),
1600 SND_SOC_DAPM_INPUT("DMIC R2"),
1601
1602 SND_SOC_DAPM_INPUT("IN1P"),
1603 SND_SOC_DAPM_INPUT("IN1N"),
1604 SND_SOC_DAPM_INPUT("IN2P"),
1605 SND_SOC_DAPM_INPUT("IN2N"),
1606
1607 SND_SOC_DAPM_INPUT("Haptic Generator"),
1608
1609 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1610 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1611 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1612 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1613 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1614 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1615 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1616 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1617 /* Boost */
1618 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1619 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1620 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1621 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1622 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1623 /* Input Volume */
1624 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1625 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1626 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1627 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1628 /* REC Mixer */
1629 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1630 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1631 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1632 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1633 /* ADCs */
1634 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1635 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1636
1637 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1638 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1639 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1640 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1641
1642 /* ADC Mux */
1643 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1644 &rt5645_sto1_dmic_mux),
1645 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1646 &rt5645_sto_adc2_mux),
1647 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1648 &rt5645_sto_adc2_mux),
1649 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1650 &rt5645_sto_adc1_mux),
1651 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1652 &rt5645_sto_adc1_mux),
1653 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1654 &rt5645_mono_dmic_l_mux),
1655 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1656 &rt5645_mono_dmic_r_mux),
1657 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1658 &rt5645_mono_adc_l2_mux),
1659 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1660 &rt5645_mono_adc_l1_mux),
1661 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1662 &rt5645_mono_adc_r1_mux),
1663 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1664 &rt5645_mono_adc_r2_mux),
1665 /* ADC Mixer */
1666
1667 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1668 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1669 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1670 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1671 NULL, 0),
1672 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1673 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1674 NULL, 0),
1675 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1676 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1677 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1678 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1679 NULL, 0),
1680 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1681 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1682 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1683 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1684 NULL, 0),
1685
1686 /* ADC PGA */
1687 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1688 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1689 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1690 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1691 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1692 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1693 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1694 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1695 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1696 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1697
1698 /* IF1 2 Mux */
1699 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1700 0, 0, &rt5645_if1_adc1_in_mux),
1701 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1702 0, 0, &rt5645_if1_adc2_in_mux),
1703 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1704 0, 0, &rt5645_if1_adc3_in_mux),
1705 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
1706 0, 0, &rt5645_if1_adc_in_mux),
1707
1708 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1709 0, 0, &rt5650_if1_adc1_in_mux),
1710 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1711 0, 0, &rt5650_if1_adc2_in_mux),
1712 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1713 0, 0, &rt5650_if1_adc3_in_mux),
1714 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
1715 0, 0, &rt5650_if1_adc_in_mux),
1716
1717 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1718 0, 0, &rt5645_if2_adc_in_mux),
1719
1720 /* Digital Interface */
1721 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1722 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1723 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1724 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1725 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1726 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1727 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1728 &rt5645_if1_dac0_tdm_sel_mux),
1729 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1730 &rt5645_if1_dac1_tdm_sel_mux),
1731 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1732 &rt5645_if1_dac2_tdm_sel_mux),
1733 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1734 &rt5645_if1_dac3_tdm_sel_mux),
1735 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1736 &rt5650_if1_dac0_tdm_sel_mux),
1737 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1738 &rt5650_if1_dac1_tdm_sel_mux),
1739 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1740 &rt5650_if1_dac2_tdm_sel_mux),
1741 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1742 &rt5650_if1_dac3_tdm_sel_mux),
1743 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1744 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1745 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1746 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1747 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1748 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1749 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1750 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1751 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1752
1753 /* Digital Interface Select */
1754 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1755 0, 0, &rt5645_vad_adc_mux),
1756
1757 /* Audio Interface */
1758 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1759 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1760 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1761 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1762
1763 /* Output Side */
1764 /* DAC mixer before sound effect */
1765 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1766 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1767 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1768 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1769
1770 /* DAC2 channel Mux */
1771 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1772 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1773 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1774 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1775 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1776 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1777
1778 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1779 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1780
1781 /* DAC Mixer */
1782 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1783 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1784 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1785 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1786 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1787 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1788 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1789 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1790 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1791 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1792 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1793 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1794 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1795 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1796 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1797 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1798 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1799 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1800
1801 /* DACs */
1802 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1803 0),
1804 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1805 0),
1806 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1807 0),
1808 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1809 0),
1810 /* OUT Mixer */
1811 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1812 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1813 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1814 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1815 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1816 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1817 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1818 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1819 /* Ouput Volume */
1820 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1821 &spk_l_vol_control),
1822 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1823 &spk_r_vol_control),
1824 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1825 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1826 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1827 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1828 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1829 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1830 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1831 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1836 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1837
1838 /* HPO/LOUT/Mono Mixer */
1839 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1840 ARRAY_SIZE(rt5645_spo_l_mix)),
1841 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1842 ARRAY_SIZE(rt5645_spo_r_mix)),
1843 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1844 ARRAY_SIZE(rt5645_hpo_mix)),
1845 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1846 ARRAY_SIZE(rt5645_lout_mix)),
1847
1848 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1849 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1850 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1851 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1852 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1853 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1854
1855 /* PDM */
1856 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1857 0, NULL, 0),
1858 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1859 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1860
1861 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1862 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1863
1864 /* Output Lines */
1865 SND_SOC_DAPM_OUTPUT("HPOL"),
1866 SND_SOC_DAPM_OUTPUT("HPOR"),
1867 SND_SOC_DAPM_OUTPUT("LOUTL"),
1868 SND_SOC_DAPM_OUTPUT("LOUTR"),
1869 SND_SOC_DAPM_OUTPUT("PDM1L"),
1870 SND_SOC_DAPM_OUTPUT("PDM1R"),
1871 SND_SOC_DAPM_OUTPUT("SPOL"),
1872 SND_SOC_DAPM_OUTPUT("SPOR"),
1873 };
1874
1875 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1876 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1877 0, 0, &rt5650_a_dac1_l_mux),
1878 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1879 0, 0, &rt5650_a_dac1_r_mux),
1880 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1881 0, 0, &rt5650_a_dac2_l_mux),
1882 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1883 0, 0, &rt5650_a_dac2_r_mux),
1884 };
1885
1886 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1887 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1888 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1889 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1890 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1891 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1892 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1893
1894 { "I2S1", NULL, "I2S1 ASRC" },
1895 { "I2S2", NULL, "I2S2 ASRC" },
1896
1897 { "IN1P", NULL, "LDO2" },
1898 { "IN2P", NULL, "LDO2" },
1899
1900 { "DMIC1", NULL, "DMIC L1" },
1901 { "DMIC1", NULL, "DMIC R1" },
1902 { "DMIC2", NULL, "DMIC L2" },
1903 { "DMIC2", NULL, "DMIC R2" },
1904
1905 { "BST1", NULL, "IN1P" },
1906 { "BST1", NULL, "IN1N" },
1907 { "BST1", NULL, "JD Power" },
1908 { "BST1", NULL, "Mic Det Power" },
1909 { "BST2", NULL, "IN2P" },
1910 { "BST2", NULL, "IN2N" },
1911
1912 { "INL VOL", NULL, "IN2P" },
1913 { "INR VOL", NULL, "IN2N" },
1914
1915 { "RECMIXL", "HPOL Switch", "HPOL" },
1916 { "RECMIXL", "INL Switch", "INL VOL" },
1917 { "RECMIXL", "BST2 Switch", "BST2" },
1918 { "RECMIXL", "BST1 Switch", "BST1" },
1919 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1920
1921 { "RECMIXR", "HPOR Switch", "HPOR" },
1922 { "RECMIXR", "INR Switch", "INR VOL" },
1923 { "RECMIXR", "BST2 Switch", "BST2" },
1924 { "RECMIXR", "BST1 Switch", "BST1" },
1925 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1926
1927 { "ADC L", NULL, "RECMIXL" },
1928 { "ADC L", NULL, "ADC L power" },
1929 { "ADC R", NULL, "RECMIXR" },
1930 { "ADC R", NULL, "ADC R power" },
1931
1932 {"DMIC L1", NULL, "DMIC CLK"},
1933 {"DMIC L1", NULL, "DMIC1 Power"},
1934 {"DMIC R1", NULL, "DMIC CLK"},
1935 {"DMIC R1", NULL, "DMIC1 Power"},
1936 {"DMIC L2", NULL, "DMIC CLK"},
1937 {"DMIC L2", NULL, "DMIC2 Power"},
1938 {"DMIC R2", NULL, "DMIC CLK"},
1939 {"DMIC R2", NULL, "DMIC2 Power"},
1940
1941 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1942 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1943 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1944
1945 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1946 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1947 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1948
1949 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1950 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1951 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1952
1953 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1954 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1955 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1956 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1957
1958 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1959 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1960 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1961 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1962
1963 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1964 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1965 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1966 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1967
1968 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1969 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1970 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1971 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1972
1973 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1974 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1975 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1976 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1977
1978 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1979 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1980 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1981
1982 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1983 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1984 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1985
1986 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1987 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1988 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1989 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1990
1991 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1992 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1993 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1994 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1995
1996 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1997 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1998 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1999
2000 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2001 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2002 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2003 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2004 { "VAD_ADC", NULL, "VAD ADC Mux" },
2005
2006 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2007 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2008 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2009
2010 { "IF1 ADC", NULL, "I2S1" },
2011 { "IF2 ADC", NULL, "I2S2" },
2012 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2013
2014 { "AIF2TX", NULL, "IF2 ADC" },
2015
2016 { "IF1 DAC0", NULL, "AIF1RX" },
2017 { "IF1 DAC1", NULL, "AIF1RX" },
2018 { "IF1 DAC2", NULL, "AIF1RX" },
2019 { "IF1 DAC3", NULL, "AIF1RX" },
2020 { "IF2 DAC", NULL, "AIF2RX" },
2021
2022 { "IF1 DAC0", NULL, "I2S1" },
2023 { "IF1 DAC1", NULL, "I2S1" },
2024 { "IF1 DAC2", NULL, "I2S1" },
2025 { "IF1 DAC3", NULL, "I2S1" },
2026 { "IF2 DAC", NULL, "I2S2" },
2027
2028 { "IF2 DAC L", NULL, "IF2 DAC" },
2029 { "IF2 DAC R", NULL, "IF2 DAC" },
2030
2031 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2032 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2033
2034 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2035 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2036 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2037 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2038 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2039 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2040
2041 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2042 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2043 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2044 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2045 { "DAC L2 Volume", NULL, "dac mono left filter" },
2046
2047 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2048 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2049 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2050 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2051 { "DAC R2 Volume", NULL, "dac mono right filter" },
2052
2053 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2054 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2055 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2056 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2057 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2058 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2059 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2060 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2061
2062 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2063 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2064 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2065 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2066 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2067 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2068 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2069 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2070
2071 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2072 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2073 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2074 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2075 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2076 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2077
2078 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2079 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2080 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2081 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2082
2083 { "SPK MIXL", "BST1 Switch", "BST1" },
2084 { "SPK MIXL", "INL Switch", "INL VOL" },
2085 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2086 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2087 { "SPK MIXR", "BST2 Switch", "BST2" },
2088 { "SPK MIXR", "INR Switch", "INR VOL" },
2089 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2090 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2091
2092 { "OUT MIXL", "BST1 Switch", "BST1" },
2093 { "OUT MIXL", "INL Switch", "INL VOL" },
2094 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2095 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2096
2097 { "OUT MIXR", "BST2 Switch", "BST2" },
2098 { "OUT MIXR", "INR Switch", "INR VOL" },
2099 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2100 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2101
2102 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2103 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2104 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2105 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2106 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2107 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2108 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2109 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2110 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2111 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2112
2113 { "DAC 2", NULL, "DAC L2" },
2114 { "DAC 2", NULL, "DAC R2" },
2115 { "DAC 1", NULL, "DAC L1" },
2116 { "DAC 1", NULL, "DAC R1" },
2117 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2118 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2119 { "HPOVOL", NULL, "HPOVOL L" },
2120 { "HPOVOL", NULL, "HPOVOL R" },
2121 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2122 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2123
2124 { "SPKVOL L", "Switch", "SPK MIXL" },
2125 { "SPKVOL R", "Switch", "SPK MIXR" },
2126
2127 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2128 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2129 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2130 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2131 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2132 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2133
2134 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2135 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2136 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2137 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2138
2139 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2140 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2141 { "PDM1 L Mux", NULL, "PDM1 Power" },
2142 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2143 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2144 { "PDM1 R Mux", NULL, "PDM1 Power" },
2145
2146 { "HP amp", NULL, "HPO MIX" },
2147 { "HP amp", NULL, "JD Power" },
2148 { "HP amp", NULL, "Mic Det Power" },
2149 { "HP amp", NULL, "LDO2" },
2150 { "HPOL", NULL, "HP amp" },
2151 { "HPOR", NULL, "HP amp" },
2152
2153 { "LOUT amp", NULL, "LOUT MIX" },
2154 { "LOUTL", NULL, "LOUT amp" },
2155 { "LOUTR", NULL, "LOUT amp" },
2156
2157 { "PDM1 L", "Switch", "PDM1 L Mux" },
2158 { "PDM1 R", "Switch", "PDM1 R Mux" },
2159
2160 { "PDM1L", NULL, "PDM1 L" },
2161 { "PDM1R", NULL, "PDM1 R" },
2162
2163 { "SPK amp", NULL, "SPOL MIX" },
2164 { "SPK amp", NULL, "SPOR MIX" },
2165 { "SPOL", NULL, "SPK amp" },
2166 { "SPOR", NULL, "SPK amp" },
2167 };
2168
2169 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2170 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2171 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2172 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2173 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2174
2175 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2176 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2177 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2178 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2179
2180 { "DAC L1", NULL, "A DAC1 L Mux" },
2181 { "DAC R1", NULL, "A DAC1 R Mux" },
2182 { "DAC L2", NULL, "A DAC2 L Mux" },
2183 { "DAC R2", NULL, "A DAC2 R Mux" },
2184
2185 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2186 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2187 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2188 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2189
2190 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2191 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2192 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2193 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2194
2195 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2196 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2197 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2198 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2199
2200 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2201 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2202 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2203
2204 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2205 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2206 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2207 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2208 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2209 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2210
2211 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2212 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2213 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2214 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2215 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2216 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2217
2218 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2219 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2220 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2221 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2222 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2223 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2224
2225 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2226 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2227 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2228 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2229 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2230 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2231 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2232
2233 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2234 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2235 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2236 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2237
2238 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2239 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2240 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2241 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2242
2243 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2244 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2245 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2246 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2247
2248 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2249 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2250 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2251 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2252
2253 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2254 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2255
2256 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2257 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2258 };
2259
2260 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2261 { "DAC L1", NULL, "Stereo DAC MIXL" },
2262 { "DAC R1", NULL, "Stereo DAC MIXR" },
2263 { "DAC L2", NULL, "Mono DAC MIXL" },
2264 { "DAC R2", NULL, "Mono DAC MIXR" },
2265
2266 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2267 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2268 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2269 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2270
2271 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2272 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2273 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2274 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2275
2276 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2277 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2278 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2279 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2280
2281 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2282 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2283 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2284
2285 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2286 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2287 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2288 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2289 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2290
2291 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2292 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2293 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2294 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2295
2296 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2297 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2298 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2299 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2300
2301 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2302 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2303 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2304 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2305
2306 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2307 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2308 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2309 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2310
2311 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2312 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2313
2314 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2315 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2316 };
2317
2318 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2319 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2320 {
2321 struct snd_soc_codec *codec = dai->codec;
2322 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2323 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2324 int pre_div, bclk_ms, frame_size;
2325
2326 rt5645->lrck[dai->id] = params_rate(params);
2327 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2328 if (pre_div < 0) {
2329 dev_err(codec->dev, "Unsupported clock setting\n");
2330 return -EINVAL;
2331 }
2332 frame_size = snd_soc_params_to_frame_size(params);
2333 if (frame_size < 0) {
2334 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2335 return -EINVAL;
2336 }
2337
2338 switch (rt5645->codec_type) {
2339 case CODEC_TYPE_RT5650:
2340 dl_sft = 4;
2341 break;
2342 default:
2343 dl_sft = 2;
2344 break;
2345 }
2346
2347 bclk_ms = frame_size > 32;
2348 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2349
2350 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2351 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2352 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2353 bclk_ms, pre_div, dai->id);
2354
2355 switch (params_width(params)) {
2356 case 16:
2357 break;
2358 case 20:
2359 val_len = 0x1;
2360 break;
2361 case 24:
2362 val_len = 0x2;
2363 break;
2364 case 8:
2365 val_len = 0x3;
2366 break;
2367 default:
2368 return -EINVAL;
2369 }
2370
2371 switch (dai->id) {
2372 case RT5645_AIF1:
2373 mask_clk = RT5645_I2S_PD1_MASK;
2374 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2375 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2376 (0x3 << dl_sft), (val_len << dl_sft));
2377 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2378 break;
2379 case RT5645_AIF2:
2380 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2381 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2382 pre_div << RT5645_I2S_PD2_SFT;
2383 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2384 (0x3 << dl_sft), (val_len << dl_sft));
2385 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2386 break;
2387 default:
2388 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2389 return -EINVAL;
2390 }
2391
2392 return 0;
2393 }
2394
2395 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2396 {
2397 struct snd_soc_codec *codec = dai->codec;
2398 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2399 unsigned int reg_val = 0, pol_sft;
2400
2401 switch (rt5645->codec_type) {
2402 case CODEC_TYPE_RT5650:
2403 pol_sft = 8;
2404 break;
2405 default:
2406 pol_sft = 7;
2407 break;
2408 }
2409
2410 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2411 case SND_SOC_DAIFMT_CBM_CFM:
2412 rt5645->master[dai->id] = 1;
2413 break;
2414 case SND_SOC_DAIFMT_CBS_CFS:
2415 reg_val |= RT5645_I2S_MS_S;
2416 rt5645->master[dai->id] = 0;
2417 break;
2418 default:
2419 return -EINVAL;
2420 }
2421
2422 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2423 case SND_SOC_DAIFMT_NB_NF:
2424 break;
2425 case SND_SOC_DAIFMT_IB_NF:
2426 reg_val |= (1 << pol_sft);
2427 break;
2428 default:
2429 return -EINVAL;
2430 }
2431
2432 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2433 case SND_SOC_DAIFMT_I2S:
2434 break;
2435 case SND_SOC_DAIFMT_LEFT_J:
2436 reg_val |= RT5645_I2S_DF_LEFT;
2437 break;
2438 case SND_SOC_DAIFMT_DSP_A:
2439 reg_val |= RT5645_I2S_DF_PCM_A;
2440 break;
2441 case SND_SOC_DAIFMT_DSP_B:
2442 reg_val |= RT5645_I2S_DF_PCM_B;
2443 break;
2444 default:
2445 return -EINVAL;
2446 }
2447 switch (dai->id) {
2448 case RT5645_AIF1:
2449 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2450 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2451 RT5645_I2S_DF_MASK, reg_val);
2452 break;
2453 case RT5645_AIF2:
2454 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2455 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2456 RT5645_I2S_DF_MASK, reg_val);
2457 break;
2458 default:
2459 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2460 return -EINVAL;
2461 }
2462 return 0;
2463 }
2464
2465 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2466 int clk_id, unsigned int freq, int dir)
2467 {
2468 struct snd_soc_codec *codec = dai->codec;
2469 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2470 unsigned int reg_val = 0;
2471
2472 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2473 return 0;
2474
2475 switch (clk_id) {
2476 case RT5645_SCLK_S_MCLK:
2477 reg_val |= RT5645_SCLK_SRC_MCLK;
2478 break;
2479 case RT5645_SCLK_S_PLL1:
2480 reg_val |= RT5645_SCLK_SRC_PLL1;
2481 break;
2482 case RT5645_SCLK_S_RCCLK:
2483 reg_val |= RT5645_SCLK_SRC_RCCLK;
2484 break;
2485 default:
2486 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2487 return -EINVAL;
2488 }
2489 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2490 RT5645_SCLK_SRC_MASK, reg_val);
2491 rt5645->sysclk = freq;
2492 rt5645->sysclk_src = clk_id;
2493
2494 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2495
2496 return 0;
2497 }
2498
2499 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2500 unsigned int freq_in, unsigned int freq_out)
2501 {
2502 struct snd_soc_codec *codec = dai->codec;
2503 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2504 struct rl6231_pll_code pll_code;
2505 int ret;
2506
2507 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2508 freq_out == rt5645->pll_out)
2509 return 0;
2510
2511 if (!freq_in || !freq_out) {
2512 dev_dbg(codec->dev, "PLL disabled\n");
2513
2514 rt5645->pll_in = 0;
2515 rt5645->pll_out = 0;
2516 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2517 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2518 return 0;
2519 }
2520
2521 switch (source) {
2522 case RT5645_PLL1_S_MCLK:
2523 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2524 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2525 break;
2526 case RT5645_PLL1_S_BCLK1:
2527 case RT5645_PLL1_S_BCLK2:
2528 switch (dai->id) {
2529 case RT5645_AIF1:
2530 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2531 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2532 break;
2533 case RT5645_AIF2:
2534 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2535 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2536 break;
2537 default:
2538 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2539 return -EINVAL;
2540 }
2541 break;
2542 default:
2543 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2544 return -EINVAL;
2545 }
2546
2547 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2548 if (ret < 0) {
2549 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2550 return ret;
2551 }
2552
2553 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2554 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2555 pll_code.n_code, pll_code.k_code);
2556
2557 snd_soc_write(codec, RT5645_PLL_CTRL1,
2558 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2559 snd_soc_write(codec, RT5645_PLL_CTRL2,
2560 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2561 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2562
2563 rt5645->pll_in = freq_in;
2564 rt5645->pll_out = freq_out;
2565 rt5645->pll_src = source;
2566
2567 return 0;
2568 }
2569
2570 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2571 unsigned int rx_mask, int slots, int slot_width)
2572 {
2573 struct snd_soc_codec *codec = dai->codec;
2574 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2575 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2576 unsigned int mask, val = 0;
2577
2578 switch (rt5645->codec_type) {
2579 case CODEC_TYPE_RT5650:
2580 en_sft = 15;
2581 i_slot_sft = 10;
2582 o_slot_sft = 8;
2583 i_width_sht = 6;
2584 o_width_sht = 4;
2585 mask = 0x8ff0;
2586 break;
2587 default:
2588 en_sft = 14;
2589 i_slot_sft = o_slot_sft = 12;
2590 i_width_sht = o_width_sht = 10;
2591 mask = 0x7c00;
2592 break;
2593 }
2594 if (rx_mask || tx_mask) {
2595 val |= (1 << en_sft);
2596 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2597 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2598 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
2599 }
2600
2601 switch (slots) {
2602 case 4:
2603 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
2604 break;
2605 case 6:
2606 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
2607 break;
2608 case 8:
2609 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
2610 break;
2611 case 2:
2612 default:
2613 break;
2614 }
2615
2616 switch (slot_width) {
2617 case 20:
2618 val |= (1 << i_width_sht) | (1 << o_width_sht);
2619 break;
2620 case 24:
2621 val |= (2 << i_width_sht) | (2 << o_width_sht);
2622 break;
2623 case 32:
2624 val |= (3 << i_width_sht) | (3 << o_width_sht);
2625 break;
2626 case 16:
2627 default:
2628 break;
2629 }
2630
2631 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
2632
2633 return 0;
2634 }
2635
2636 static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2637 enum snd_soc_bias_level level)
2638 {
2639 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2640
2641 switch (level) {
2642 case SND_SOC_BIAS_PREPARE:
2643 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
2644 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2645 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2646 RT5645_PWR_BG | RT5645_PWR_VREF2,
2647 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2648 RT5645_PWR_BG | RT5645_PWR_VREF2);
2649 mdelay(10);
2650 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2651 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2652 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2653 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2654 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2655 }
2656 break;
2657
2658 case SND_SOC_BIAS_STANDBY:
2659 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2660 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2661 RT5645_PWR_BG | RT5645_PWR_VREF2,
2662 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2663 RT5645_PWR_BG | RT5645_PWR_VREF2);
2664 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2665 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2666 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2667 break;
2668
2669 case SND_SOC_BIAS_OFF:
2670 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2671 if (!rt5645->en_button_func)
2672 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2673 RT5645_DIG_GATE_CTRL, 0);
2674 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2675 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2676 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2677 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
2678 break;
2679
2680 default:
2681 break;
2682 }
2683 codec->dapm.bias_level = level;
2684
2685 return 0;
2686 }
2687
2688 static int rt5650_calibration(struct rt5645_priv *rt5645)
2689 {
2690 int val, i;
2691 int ret = -1;
2692
2693 regcache_cache_bypass(rt5645->regmap, true);
2694 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2695 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0800);
2696 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_CHOP_DAC_ADC,
2697 0x3600);
2698 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x25, 0x7000);
2699 regmap_write(rt5645->regmap, RT5645_I2S1_SDP, 0x8008);
2700 /* headset type */
2701 regmap_write(rt5645->regmap, RT5645_GEN_CTRL1, 0x2061);
2702 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2703 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0x2012);
2704 regmap_write(rt5645->regmap, RT5645_PWR_MIXER, 0x0002);
2705 regmap_write(rt5645->regmap, RT5645_PWR_VOL, 0x0020);
2706 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2707 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2708 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x1827);
2709 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x0827);
2710 msleep(400);
2711 /* Inline command */
2712 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0001);
2713 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2714 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2715 /* Calbration */
2716 regmap_write(rt5645->regmap, RT5645_GLB_CLK, 0x8000);
2717 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2718 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2719 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2720 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x8800);
2721 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0xe8fa);
2722 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x8c04);
2723 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x3100);
2724 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
2725 regmap_write(rt5645->regmap, RT5645_BASS_BACK, 0x8a13);
2726 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0820);
2727 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x000d);
2728 /* Power on and Calbration */
2729 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_HP_DCC_INT1,
2730 0x9f01);
2731 msleep(200);
2732 for (i = 0; i < 5; i++) {
2733 regmap_read(rt5645->regmap, RT5645_PR_BASE + 0x7a, &val);
2734 if (val != 0 && val != 0x3f3f) {
2735 ret = 0;
2736 break;
2737 }
2738 msleep(50);
2739 }
2740 pr_debug("%s: PR-7A = 0x%x\n", __func__, val);
2741
2742 /* mute */
2743 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x3e, 0x7400);
2744 regmap_write(rt5645->regmap, RT5645_DEPOP_M3, 0x0737);
2745 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_MAMP_INT_REG2,
2746 0xfc00);
2747 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x1140);
2748 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2749 regmap_write(rt5645->regmap, RT5645_GEN_CTRL2, 0x4020);
2750 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x0006);
2751 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x0000);
2752 msleep(350);
2753
2754 regcache_cache_bypass(rt5645->regmap, false);
2755
2756 return ret;
2757 }
2758
2759 static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2760 bool enable)
2761 {
2762 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2763
2764 if (enable) {
2765 snd_soc_dapm_mutex_lock(&codec->dapm);
2766 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2767 "ADC L power");
2768 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2769 "ADC R power");
2770 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2771 "LDO2");
2772 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2773 "Mic Det Power");
2774 snd_soc_dapm_sync_unlocked(&codec->dapm);
2775 snd_soc_dapm_mutex_unlock(&codec->dapm);
2776
2777 snd_soc_update_bits(codec,
2778 RT5645_INT_IRQ_ST, 0x8, 0x8);
2779 snd_soc_update_bits(codec,
2780 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2781 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2782 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2783 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2784 } else {
2785 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2786 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
2787
2788 snd_soc_dapm_mutex_lock(&codec->dapm);
2789 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2790 "ADC L power");
2791 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2792 "ADC R power");
2793 if (rt5645->pdata.jd_mode == 0)
2794 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2795 "LDO2");
2796 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2797 "Mic Det Power");
2798 snd_soc_dapm_sync_unlocked(&codec->dapm);
2799 snd_soc_dapm_mutex_unlock(&codec->dapm);
2800 }
2801 }
2802
2803 static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2804 {
2805 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2806 unsigned int val;
2807
2808 if (jack_insert) {
2809 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2810
2811 if (codec->component.card->instantiated) {
2812 /* for jack type detect */
2813 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2814 snd_soc_dapm_force_enable_pin(&codec->dapm,
2815 "Mic Det Power");
2816 snd_soc_dapm_sync(&codec->dapm);
2817 } else {
2818 /* Power up necessary bits for JD if dapm is
2819 not ready yet */
2820 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2821 RT5645_PWR_MB | RT5645_PWR_VREF2,
2822 RT5645_PWR_MB | RT5645_PWR_VREF2);
2823 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
2824 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
2825 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
2826 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2827 }
2828
2829 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2830 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2831 regmap_update_bits(rt5645->regmap,
2832 RT5645_IN1_CTRL2, 0x1000, 0x1000);
2833 msleep(100);
2834 regmap_update_bits(rt5645->regmap,
2835 RT5645_IN1_CTRL2, 0x1000, 0x0000);
2836
2837 msleep(450);
2838 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2839 val &= 0x7;
2840 dev_dbg(codec->dev, "val = %d\n", val);
2841
2842 if (val == 1 || val == 2) {
2843 rt5645->jack_type = SND_JACK_HEADSET;
2844 if (rt5645->en_button_func) {
2845 rt5645_enable_push_button_irq(codec, true);
2846 }
2847 } else {
2848 if (codec->component.card->instantiated) {
2849 snd_soc_dapm_disable_pin(&codec->dapm,
2850 "Mic Det Power");
2851 snd_soc_dapm_sync(&codec->dapm);
2852 } else
2853 regmap_update_bits(rt5645->regmap,
2854 RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0);
2855 rt5645->jack_type = SND_JACK_HEADPHONE;
2856 }
2857
2858 } else { /* jack out */
2859 rt5645->jack_type = 0;
2860 if (rt5645->en_button_func)
2861 rt5645_enable_push_button_irq(codec, false);
2862 else {
2863 if (codec->component.card->instantiated) {
2864 if (rt5645->pdata.jd_mode == 0)
2865 snd_soc_dapm_disable_pin(&codec->dapm,
2866 "LDO2");
2867 snd_soc_dapm_disable_pin(&codec->dapm,
2868 "Mic Det Power");
2869 snd_soc_dapm_sync(&codec->dapm);
2870 } else {
2871 if (rt5645->pdata.jd_mode == 0)
2872 regmap_update_bits(rt5645->regmap,
2873 RT5645_PWR_MIXER,
2874 RT5645_PWR_LDO2, 0);
2875 regmap_update_bits(rt5645->regmap,
2876 RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0);
2877 }
2878 }
2879 }
2880
2881 return rt5645->jack_type;
2882 }
2883
2884 static int rt5645_irq_detection(struct rt5645_priv *rt5645);
2885 static irqreturn_t rt5645_irq(int irq, void *data);
2886
2887 int rt5645_set_jack_detect(struct snd_soc_codec *codec,
2888 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2889 struct snd_soc_jack *btn_jack)
2890 {
2891 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2892
2893 rt5645->hp_jack = hp_jack;
2894 rt5645->mic_jack = mic_jack;
2895 rt5645->btn_jack = btn_jack;
2896 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
2897 rt5645->en_button_func = true;
2898 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2899 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2900 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
2901 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
2902 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
2903 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2904 }
2905 rt5645_irq(0, rt5645);
2906
2907 return 0;
2908 }
2909 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2910
2911 static void rt5645_jack_detect_work(struct work_struct *work)
2912 {
2913 struct rt5645_priv *rt5645 =
2914 container_of(work, struct rt5645_priv, jack_detect_work.work);
2915
2916 rt5645_irq_detection(rt5645);
2917 }
2918
2919 static irqreturn_t rt5645_irq(int irq, void *data)
2920 {
2921 struct rt5645_priv *rt5645 = data;
2922
2923 queue_delayed_work(system_power_efficient_wq,
2924 &rt5645->jack_detect_work, msecs_to_jiffies(250));
2925
2926 return IRQ_HANDLED;
2927 }
2928
2929 static int rt5645_button_detect(struct snd_soc_codec *codec)
2930 {
2931 int btn_type, val;
2932
2933 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2934 pr_debug("val=0x%x\n", val);
2935 btn_type = val & 0xfff0;
2936 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
2937
2938 return btn_type;
2939 }
2940
2941 static int rt5645_irq_detection(struct rt5645_priv *rt5645)
2942 {
2943 int val, btn_type, gpio_state = 0, report = 0;
2944
2945 switch (rt5645->pdata.jd_mode) {
2946 case 0: /* Not using rt5645 JD */
2947 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2948 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2949 dev_dbg(rt5645->codec->dev, "gpio = %d(%d)\n",
2950 rt5645->pdata.hp_det_gpio, gpio_state);
2951 }
2952 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2953 (!rt5645->pdata.gpio_hp_det_active_high &&
2954 !gpio_state)) {
2955 report = rt5645_jack_detect(rt5645->codec, 1);
2956 } else {
2957 report = rt5645_jack_detect(rt5645->codec, 0);
2958 }
2959 snd_soc_jack_report(rt5645->hp_jack,
2960 report, SND_JACK_HEADPHONE);
2961 snd_soc_jack_report(rt5645->mic_jack,
2962 report, SND_JACK_MICROPHONE);
2963 return report;
2964 case 1: /* 2 port */
2965 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
2966 break;
2967 default: /* 1 port */
2968 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
2969 break;
2970
2971 }
2972
2973 switch (val) {
2974 /* jack in */
2975 case 0x30: /* 2 port */
2976 case 0x0: /* 1 port or 2 port */
2977 if (rt5645->jack_type == 0) {
2978 report = rt5645_jack_detect(rt5645->codec, 1);
2979 /* for push button and jack out */
2980 break;
2981 }
2982 btn_type = 0;
2983 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
2984 /* button pressed */
2985 report = SND_JACK_HEADSET;
2986 btn_type = rt5645_button_detect(rt5645->codec);
2987 /* rt5650 can report three kinds of button behavior,
2988 one click, double click and hold. However,
2989 currently we will report button pressed/released
2990 event. So all the three button behaviors are
2991 treated as button pressed. */
2992 switch (btn_type) {
2993 case 0x8000:
2994 case 0x4000:
2995 case 0x2000:
2996 report |= SND_JACK_BTN_0;
2997 break;
2998 case 0x1000:
2999 case 0x0800:
3000 case 0x0400:
3001 report |= SND_JACK_BTN_1;
3002 break;
3003 case 0x0200:
3004 case 0x0100:
3005 case 0x0080:
3006 report |= SND_JACK_BTN_2;
3007 break;
3008 case 0x0040:
3009 case 0x0020:
3010 case 0x0010:
3011 report |= SND_JACK_BTN_3;
3012 break;
3013 case 0x0000: /* unpressed */
3014 break;
3015 default:
3016 dev_err(rt5645->codec->dev,
3017 "Unexpected button code 0x%04x\n",
3018 btn_type);
3019 break;
3020 }
3021 }
3022 if (btn_type == 0)/* button release */
3023 report = rt5645->jack_type;
3024
3025 break;
3026 /* jack out */
3027 case 0x70: /* 2 port */
3028 case 0x10: /* 2 port */
3029 case 0x20: /* 1 port */
3030 report = 0;
3031 snd_soc_update_bits(rt5645->codec,
3032 RT5645_INT_IRQ_ST, 0x1, 0x0);
3033 rt5645_jack_detect(rt5645->codec, 0);
3034 break;
3035 default:
3036 break;
3037 }
3038
3039 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3040 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3041 if (rt5645->en_button_func)
3042 snd_soc_jack_report(rt5645->btn_jack,
3043 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3044 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3045
3046 return report;
3047 }
3048
3049 static int rt5645_probe(struct snd_soc_codec *codec)
3050 {
3051 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3052
3053 rt5645->codec = codec;
3054
3055 switch (rt5645->codec_type) {
3056 case CODEC_TYPE_RT5645:
3057 snd_soc_dapm_add_routes(&codec->dapm,
3058 rt5645_specific_dapm_routes,
3059 ARRAY_SIZE(rt5645_specific_dapm_routes));
3060 break;
3061 case CODEC_TYPE_RT5650:
3062 snd_soc_dapm_new_controls(&codec->dapm,
3063 rt5650_specific_dapm_widgets,
3064 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3065 snd_soc_dapm_add_routes(&codec->dapm,
3066 rt5650_specific_dapm_routes,
3067 ARRAY_SIZE(rt5650_specific_dapm_routes));
3068 break;
3069 }
3070
3071 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
3072
3073 /* for JD function */
3074 if (rt5645->pdata.jd_mode) {
3075 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
3076 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
3077 snd_soc_dapm_sync(&codec->dapm);
3078 }
3079
3080 return 0;
3081 }
3082
3083 static int rt5645_remove(struct snd_soc_codec *codec)
3084 {
3085 rt5645_reset(codec);
3086 return 0;
3087 }
3088
3089 #ifdef CONFIG_PM
3090 static int rt5645_suspend(struct snd_soc_codec *codec)
3091 {
3092 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3093
3094 regcache_cache_only(rt5645->regmap, true);
3095 regcache_mark_dirty(rt5645->regmap);
3096
3097 return 0;
3098 }
3099
3100 static int rt5645_resume(struct snd_soc_codec *codec)
3101 {
3102 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3103
3104 regcache_cache_only(rt5645->regmap, false);
3105 regcache_sync(rt5645->regmap);
3106
3107 return 0;
3108 }
3109 #else
3110 #define rt5645_suspend NULL
3111 #define rt5645_resume NULL
3112 #endif
3113
3114 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3115 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3116 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3117
3118 static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3119 .hw_params = rt5645_hw_params,
3120 .set_fmt = rt5645_set_dai_fmt,
3121 .set_sysclk = rt5645_set_dai_sysclk,
3122 .set_tdm_slot = rt5645_set_tdm_slot,
3123 .set_pll = rt5645_set_dai_pll,
3124 };
3125
3126 static struct snd_soc_dai_driver rt5645_dai[] = {
3127 {
3128 .name = "rt5645-aif1",
3129 .id = RT5645_AIF1,
3130 .playback = {
3131 .stream_name = "AIF1 Playback",
3132 .channels_min = 1,
3133 .channels_max = 2,
3134 .rates = RT5645_STEREO_RATES,
3135 .formats = RT5645_FORMATS,
3136 },
3137 .capture = {
3138 .stream_name = "AIF1 Capture",
3139 .channels_min = 1,
3140 .channels_max = 2,
3141 .rates = RT5645_STEREO_RATES,
3142 .formats = RT5645_FORMATS,
3143 },
3144 .ops = &rt5645_aif_dai_ops,
3145 },
3146 {
3147 .name = "rt5645-aif2",
3148 .id = RT5645_AIF2,
3149 .playback = {
3150 .stream_name = "AIF2 Playback",
3151 .channels_min = 1,
3152 .channels_max = 2,
3153 .rates = RT5645_STEREO_RATES,
3154 .formats = RT5645_FORMATS,
3155 },
3156 .capture = {
3157 .stream_name = "AIF2 Capture",
3158 .channels_min = 1,
3159 .channels_max = 2,
3160 .rates = RT5645_STEREO_RATES,
3161 .formats = RT5645_FORMATS,
3162 },
3163 .ops = &rt5645_aif_dai_ops,
3164 },
3165 };
3166
3167 static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3168 .probe = rt5645_probe,
3169 .remove = rt5645_remove,
3170 .suspend = rt5645_suspend,
3171 .resume = rt5645_resume,
3172 .set_bias_level = rt5645_set_bias_level,
3173 .idle_bias_off = true,
3174 .controls = rt5645_snd_controls,
3175 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3176 .dapm_widgets = rt5645_dapm_widgets,
3177 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3178 .dapm_routes = rt5645_dapm_routes,
3179 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3180 };
3181
3182 static const struct regmap_config rt5645_regmap = {
3183 .reg_bits = 8,
3184 .val_bits = 16,
3185 .use_single_rw = true,
3186 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3187 RT5645_PR_SPACING),
3188 .volatile_reg = rt5645_volatile_register,
3189 .readable_reg = rt5645_readable_register,
3190
3191 .cache_type = REGCACHE_RBTREE,
3192 .reg_defaults = rt5645_reg,
3193 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3194 .ranges = rt5645_ranges,
3195 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3196 };
3197
3198 static const struct i2c_device_id rt5645_i2c_id[] = {
3199 { "rt5645", 0 },
3200 { "rt5650", 0 },
3201 { }
3202 };
3203 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3204
3205 #ifdef CONFIG_ACPI
3206 static struct acpi_device_id rt5645_acpi_match[] = {
3207 { "10EC5645", 0 },
3208 { "10EC5650", 0 },
3209 {},
3210 };
3211 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3212 #endif
3213
3214 static struct rt5645_platform_data *rt5645_pdata;
3215
3216 static struct rt5645_platform_data strago_platform_data = {
3217 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3218 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3219 .jd_mode = 3,
3220 };
3221
3222 static int strago_quirk_cb(const struct dmi_system_id *id)
3223 {
3224 rt5645_pdata = &strago_platform_data;
3225
3226 return 1;
3227 }
3228
3229 static struct dmi_system_id dmi_platform_intel_braswell[] = {
3230 {
3231 .ident = "Intel Strago",
3232 .callback = strago_quirk_cb,
3233 .matches = {
3234 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3235 },
3236 },
3237 { }
3238 };
3239
3240 static int rt5645_i2c_probe(struct i2c_client *i2c,
3241 const struct i2c_device_id *id)
3242 {
3243 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3244 struct rt5645_priv *rt5645;
3245 int ret;
3246 unsigned int val;
3247 struct gpio_desc *gpiod;
3248
3249 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3250 GFP_KERNEL);
3251 if (rt5645 == NULL)
3252 return -ENOMEM;
3253
3254 rt5645->i2c = i2c;
3255 i2c_set_clientdata(i2c, rt5645);
3256
3257 if (pdata) {
3258 rt5645->pdata = *pdata;
3259 } else {
3260 if (dmi_check_system(dmi_platform_intel_braswell)) {
3261 rt5645->pdata = *rt5645_pdata;
3262 gpiod = devm_gpiod_get_index(&i2c->dev, "rt5645", 0);
3263
3264 if (IS_ERR(gpiod) || gpiod_direction_input(gpiod)) {
3265 rt5645->pdata.hp_det_gpio = -1;
3266 dev_err(&i2c->dev, "failed to initialize gpiod\n");
3267 } else {
3268 rt5645->pdata.hp_det_gpio = desc_to_gpio(gpiod);
3269 rt5645->pdata.gpio_hp_det_active_high
3270 = !gpiod_is_active_low(gpiod);
3271 }
3272 }
3273 }
3274
3275 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3276 if (IS_ERR(rt5645->regmap)) {
3277 ret = PTR_ERR(rt5645->regmap);
3278 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3279 ret);
3280 return ret;
3281 }
3282
3283 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
3284
3285 switch (val) {
3286 case RT5645_DEVICE_ID:
3287 rt5645->codec_type = CODEC_TYPE_RT5645;
3288 break;
3289 case RT5650_DEVICE_ID:
3290 rt5645->codec_type = CODEC_TYPE_RT5650;
3291 break;
3292 default:
3293 dev_err(&i2c->dev,
3294 "Device with ID register %x is not rt5645 or rt5650\n",
3295 val);
3296 return -ENODEV;
3297 }
3298
3299 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3300 ret = rt5650_calibration(rt5645);
3301
3302 if (ret < 0)
3303 pr_err("calibration failed!\n");
3304 }
3305
3306 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3307
3308 ret = regmap_register_patch(rt5645->regmap, init_list,
3309 ARRAY_SIZE(init_list));
3310 if (ret != 0)
3311 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3312
3313 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3314 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3315 ARRAY_SIZE(rt5650_init_list));
3316 if (ret != 0)
3317 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3318 ret);
3319 }
3320
3321 if (rt5645->pdata.in2_diff)
3322 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3323 RT5645_IN_DF2, RT5645_IN_DF2);
3324
3325 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
3326 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3327 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3328 }
3329 switch (rt5645->pdata.dmic1_data_pin) {
3330 case RT5645_DMIC_DATA_IN2N:
3331 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3332 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3333 break;
3334
3335 case RT5645_DMIC_DATA_GPIO5:
3336 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3337 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3338 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3339 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3340 break;
3341
3342 case RT5645_DMIC_DATA_GPIO11:
3343 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3344 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3345 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3346 RT5645_GP11_PIN_MASK,
3347 RT5645_GP11_PIN_DMIC1_SDA);
3348 break;
3349
3350 default:
3351 break;
3352 }
3353
3354 switch (rt5645->pdata.dmic2_data_pin) {
3355 case RT5645_DMIC_DATA_IN2P:
3356 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3357 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3358 break;
3359
3360 case RT5645_DMIC_DATA_GPIO6:
3361 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3362 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3363 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3364 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3365 break;
3366
3367 case RT5645_DMIC_DATA_GPIO10:
3368 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3369 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3370 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3371 RT5645_GP10_PIN_MASK,
3372 RT5645_GP10_PIN_DMIC2_SDA);
3373 break;
3374
3375 case RT5645_DMIC_DATA_GPIO12:
3376 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3377 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3378 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3379 RT5645_GP12_PIN_MASK,
3380 RT5645_GP12_PIN_DMIC2_SDA);
3381 break;
3382
3383 default:
3384 break;
3385 }
3386
3387 if (rt5645->pdata.jd_mode) {
3388 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3389 RT5645_IRQ_CLK_GATE_CTRL,
3390 RT5645_IRQ_CLK_GATE_CTRL);
3391 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3392 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3393 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3394 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
3395 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3396 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3397 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3398 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3399 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3400 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3401 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3402 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3403 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3404 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3405 switch (rt5645->pdata.jd_mode) {
3406 case 1:
3407 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3408 RT5645_JD1_MODE_MASK,
3409 RT5645_JD1_MODE_0);
3410 break;
3411 case 2:
3412 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3413 RT5645_JD1_MODE_MASK,
3414 RT5645_JD1_MODE_1);
3415 break;
3416 case 3:
3417 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3418 RT5645_JD1_MODE_MASK,
3419 RT5645_JD1_MODE_2);
3420 break;
3421 default:
3422 break;
3423 }
3424 }
3425
3426 if (rt5645->i2c->irq) {
3427 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3428 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3429 | IRQF_ONESHOT, "rt5645", rt5645);
3430 if (ret)
3431 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3432 }
3433
3434 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
3435 ret = gpio_request(rt5645->pdata.hp_det_gpio, "rt5645");
3436 if (ret)
3437 dev_err(&i2c->dev, "Fail gpio_request hp_det_gpio\n");
3438
3439 ret = gpio_direction_input(rt5645->pdata.hp_det_gpio);
3440 if (ret)
3441 dev_err(&i2c->dev, "Fail gpio_direction hp_det_gpio\n");
3442 }
3443
3444 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
3445
3446 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3447 rt5645_dai, ARRAY_SIZE(rt5645_dai));
3448 }
3449
3450 static int rt5645_i2c_remove(struct i2c_client *i2c)
3451 {
3452 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3453
3454 if (i2c->irq)
3455 free_irq(i2c->irq, rt5645);
3456
3457 cancel_delayed_work_sync(&rt5645->jack_detect_work);
3458
3459 if (gpio_is_valid(rt5645->pdata.hp_det_gpio))
3460 gpio_free(rt5645->pdata.hp_det_gpio);
3461
3462 snd_soc_unregister_codec(&i2c->dev);
3463
3464 return 0;
3465 }
3466
3467 static struct i2c_driver rt5645_i2c_driver = {
3468 .driver = {
3469 .name = "rt5645",
3470 .owner = THIS_MODULE,
3471 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
3472 },
3473 .probe = rt5645_i2c_probe,
3474 .remove = rt5645_i2c_remove,
3475 .id_table = rt5645_i2c_id,
3476 };
3477 module_i2c_driver(rt5645_i2c_driver);
3478
3479 MODULE_DESCRIPTION("ASoC RT5645 driver");
3480 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3481 MODULE_LICENSE("GPL v2");
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