]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - sound/soc/codecs/rt5677.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


4b6f7d57c1bba271c2b4efe0924a01a2cb110b56
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / rt5677.c
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "rl6231.h"
34 #include "rt5677.h"
35 #include "rt5677-spi.h"
36
37 #define RT5677_DEVICE_ID 0x6327
38
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
41
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44 static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55 };
56
57 static const struct reg_default init_list[] = {
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
64 };
65 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
66
67 static const struct reg_default rt5677_reg[] = {
68 {RT5677_RESET , 0x0000},
69 {RT5677_LOUT1 , 0xa800},
70 {RT5677_IN1 , 0x0000},
71 {RT5677_MICBIAS , 0x0000},
72 {RT5677_SLIMBUS_PARAM , 0x0000},
73 {RT5677_SLIMBUS_RX , 0x0000},
74 {RT5677_SLIMBUS_CTRL , 0x0000},
75 {RT5677_SIDETONE_CTRL , 0x000b},
76 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
77 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
78 {RT5677_DAC4_DIG_VOL , 0xafaf},
79 {RT5677_DAC3_DIG_VOL , 0xafaf},
80 {RT5677_DAC1_DIG_VOL , 0xafaf},
81 {RT5677_DAC2_DIG_VOL , 0xafaf},
82 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
83 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
84 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_STO1_2_ADC_BST , 0x0000},
86 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_ADC_BST_CTRL2 , 0x0000},
88 {RT5677_STO3_4_ADC_BST , 0x0000},
89 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_MIXER , 0xd4c0},
92 {RT5677_STO3_ADC_MIXER , 0xd4c0},
93 {RT5677_STO2_ADC_MIXER , 0xd4c0},
94 {RT5677_STO1_ADC_MIXER , 0xd4c0},
95 {RT5677_MONO_ADC_MIXER , 0xd4d1},
96 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
97 {RT5677_STO1_DAC_MIXER , 0xaaaa},
98 {RT5677_MONO_DAC_MIXER , 0xaaaa},
99 {RT5677_DD1_MIXER , 0xaaaa},
100 {RT5677_DD2_MIXER , 0xaaaa},
101 {RT5677_IF3_DATA , 0x0000},
102 {RT5677_IF4_DATA , 0x0000},
103 {RT5677_PDM_OUT_CTRL , 0x8888},
104 {RT5677_PDM_DATA_CTRL1 , 0x0000},
105 {RT5677_PDM_DATA_CTRL2 , 0x0000},
106 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
109 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
112 {RT5677_TDM1_CTRL1 , 0x0300},
113 {RT5677_TDM1_CTRL2 , 0x0000},
114 {RT5677_TDM1_CTRL3 , 0x4000},
115 {RT5677_TDM1_CTRL4 , 0x0123},
116 {RT5677_TDM1_CTRL5 , 0x4567},
117 {RT5677_TDM2_CTRL1 , 0x0300},
118 {RT5677_TDM2_CTRL2 , 0x0000},
119 {RT5677_TDM2_CTRL3 , 0x4000},
120 {RT5677_TDM2_CTRL4 , 0x0123},
121 {RT5677_TDM2_CTRL5 , 0x4567},
122 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
123 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
130 {RT5677_DMIC_CTRL1 , 0x1505},
131 {RT5677_DMIC_CTRL2 , 0x0055},
132 {RT5677_HAP_GENE_CTRL1 , 0x0111},
133 {RT5677_HAP_GENE_CTRL2 , 0x0064},
134 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
135 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
136 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
137 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
138 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
139 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
140 {RT5677_HAP_GENE_CTRL9 , 0xf000},
141 {RT5677_HAP_GENE_CTRL10 , 0x0000},
142 {RT5677_PWR_DIG1 , 0x0000},
143 {RT5677_PWR_DIG2 , 0x0000},
144 {RT5677_PWR_ANLG1 , 0x0055},
145 {RT5677_PWR_ANLG2 , 0x0000},
146 {RT5677_PWR_DSP1 , 0x0001},
147 {RT5677_PWR_DSP_ST , 0x0000},
148 {RT5677_PWR_DSP2 , 0x0000},
149 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
150 {RT5677_PRIV_INDEX , 0x0000},
151 {RT5677_PRIV_DATA , 0x0000},
152 {RT5677_I2S4_SDP , 0x8000},
153 {RT5677_I2S1_SDP , 0x8000},
154 {RT5677_I2S2_SDP , 0x8000},
155 {RT5677_I2S3_SDP , 0x8000},
156 {RT5677_CLK_TREE_CTRL1 , 0x1111},
157 {RT5677_CLK_TREE_CTRL2 , 0x1111},
158 {RT5677_CLK_TREE_CTRL3 , 0x0000},
159 {RT5677_PLL1_CTRL1 , 0x0000},
160 {RT5677_PLL1_CTRL2 , 0x0000},
161 {RT5677_PLL2_CTRL1 , 0x0c60},
162 {RT5677_PLL2_CTRL2 , 0x2000},
163 {RT5677_GLB_CLK1 , 0x0000},
164 {RT5677_GLB_CLK2 , 0x0000},
165 {RT5677_ASRC_1 , 0x0000},
166 {RT5677_ASRC_2 , 0x0000},
167 {RT5677_ASRC_3 , 0x0000},
168 {RT5677_ASRC_4 , 0x0000},
169 {RT5677_ASRC_5 , 0x0000},
170 {RT5677_ASRC_6 , 0x0000},
171 {RT5677_ASRC_7 , 0x0000},
172 {RT5677_ASRC_8 , 0x0000},
173 {RT5677_ASRC_9 , 0x0000},
174 {RT5677_ASRC_10 , 0x0000},
175 {RT5677_ASRC_11 , 0x0000},
176 {RT5677_ASRC_12 , 0x0008},
177 {RT5677_ASRC_13 , 0x0000},
178 {RT5677_ASRC_14 , 0x0000},
179 {RT5677_ASRC_15 , 0x0000},
180 {RT5677_ASRC_16 , 0x0000},
181 {RT5677_ASRC_17 , 0x0000},
182 {RT5677_ASRC_18 , 0x0000},
183 {RT5677_ASRC_19 , 0x0000},
184 {RT5677_ASRC_20 , 0x0000},
185 {RT5677_ASRC_21 , 0x000c},
186 {RT5677_ASRC_22 , 0x0000},
187 {RT5677_ASRC_23 , 0x0000},
188 {RT5677_VAD_CTRL1 , 0x2184},
189 {RT5677_VAD_CTRL2 , 0x010a},
190 {RT5677_VAD_CTRL3 , 0x0aea},
191 {RT5677_VAD_CTRL4 , 0x000c},
192 {RT5677_VAD_CTRL5 , 0x0000},
193 {RT5677_DSP_INB_CTRL1 , 0x0000},
194 {RT5677_DSP_INB_CTRL2 , 0x0000},
195 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
196 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
197 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
200 {RT5677_ADC_EQ_CTRL1 , 0x6000},
201 {RT5677_ADC_EQ_CTRL2 , 0x0000},
202 {RT5677_EQ_CTRL1 , 0xc000},
203 {RT5677_EQ_CTRL2 , 0x0000},
204 {RT5677_EQ_CTRL3 , 0x0000},
205 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
206 {RT5677_JD_CTRL1 , 0x0000},
207 {RT5677_JD_CTRL2 , 0x0000},
208 {RT5677_JD_CTRL3 , 0x0000},
209 {RT5677_IRQ_CTRL1 , 0x0000},
210 {RT5677_IRQ_CTRL2 , 0x0000},
211 {RT5677_GPIO_ST , 0x0000},
212 {RT5677_GPIO_CTRL1 , 0x0000},
213 {RT5677_GPIO_CTRL2 , 0x0000},
214 {RT5677_GPIO_CTRL3 , 0x0000},
215 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
216 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
217 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
218 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_MB_DRC_CTRL1 , 0x0f20},
226 {RT5677_DRC1_CTRL1 , 0x001f},
227 {RT5677_DRC1_CTRL2 , 0x020c},
228 {RT5677_DRC1_CTRL3 , 0x1f00},
229 {RT5677_DRC1_CTRL4 , 0x0000},
230 {RT5677_DRC1_CTRL5 , 0x0000},
231 {RT5677_DRC1_CTRL6 , 0x0029},
232 {RT5677_DRC2_CTRL1 , 0x001f},
233 {RT5677_DRC2_CTRL2 , 0x020c},
234 {RT5677_DRC2_CTRL3 , 0x1f00},
235 {RT5677_DRC2_CTRL4 , 0x0000},
236 {RT5677_DRC2_CTRL5 , 0x0000},
237 {RT5677_DRC2_CTRL6 , 0x0029},
238 {RT5677_DRC1_HL_CTRL1 , 0x8000},
239 {RT5677_DRC1_HL_CTRL2 , 0x0200},
240 {RT5677_DRC2_HL_CTRL1 , 0x8000},
241 {RT5677_DRC2_HL_CTRL2 , 0x0200},
242 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
243 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
244 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
246 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
247 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
248 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
250 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
251 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
252 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
254 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
255 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
256 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
258 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
259 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
260 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
262 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
263 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
264 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
265 {RT5677_DIG_MISC , 0x0000},
266 {RT5677_GEN_CTRL1 , 0x0000},
267 {RT5677_GEN_CTRL2 , 0x0000},
268 {RT5677_VENDOR_ID , 0x0000},
269 {RT5677_VENDOR_ID1 , 0x10ec},
270 {RT5677_VENDOR_ID2 , 0x6327},
271 };
272
273 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
274 {
275 int i;
276
277 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
278 if (reg >= rt5677_ranges[i].range_min &&
279 reg <= rt5677_ranges[i].range_max) {
280 return true;
281 }
282 }
283
284 switch (reg) {
285 case RT5677_RESET:
286 case RT5677_SLIMBUS_PARAM:
287 case RT5677_PDM_DATA_CTRL1:
288 case RT5677_PDM_DATA_CTRL2:
289 case RT5677_PDM1_DATA_CTRL4:
290 case RT5677_PDM2_DATA_CTRL4:
291 case RT5677_I2C_MASTER_CTRL1:
292 case RT5677_I2C_MASTER_CTRL7:
293 case RT5677_I2C_MASTER_CTRL8:
294 case RT5677_HAP_GENE_CTRL2:
295 case RT5677_PWR_DSP_ST:
296 case RT5677_PRIV_DATA:
297 case RT5677_PLL1_CTRL2:
298 case RT5677_PLL2_CTRL2:
299 case RT5677_ASRC_22:
300 case RT5677_ASRC_23:
301 case RT5677_VAD_CTRL5:
302 case RT5677_ADC_EQ_CTRL1:
303 case RT5677_EQ_CTRL1:
304 case RT5677_IRQ_CTRL1:
305 case RT5677_IRQ_CTRL2:
306 case RT5677_GPIO_ST:
307 case RT5677_DSP_INB1_SRC_CTRL4:
308 case RT5677_DSP_INB2_SRC_CTRL4:
309 case RT5677_DSP_INB3_SRC_CTRL4:
310 case RT5677_DSP_OUTB1_SRC_CTRL4:
311 case RT5677_DSP_OUTB2_SRC_CTRL4:
312 case RT5677_VENDOR_ID:
313 case RT5677_VENDOR_ID1:
314 case RT5677_VENDOR_ID2:
315 return true;
316 default:
317 return false;
318 }
319 }
320
321 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
322 {
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
326 if (reg >= rt5677_ranges[i].range_min &&
327 reg <= rt5677_ranges[i].range_max) {
328 return true;
329 }
330 }
331
332 switch (reg) {
333 case RT5677_RESET:
334 case RT5677_LOUT1:
335 case RT5677_IN1:
336 case RT5677_MICBIAS:
337 case RT5677_SLIMBUS_PARAM:
338 case RT5677_SLIMBUS_RX:
339 case RT5677_SLIMBUS_CTRL:
340 case RT5677_SIDETONE_CTRL:
341 case RT5677_ANA_DAC1_2_3_SRC:
342 case RT5677_IF_DSP_DAC3_4_MIXER:
343 case RT5677_DAC4_DIG_VOL:
344 case RT5677_DAC3_DIG_VOL:
345 case RT5677_DAC1_DIG_VOL:
346 case RT5677_DAC2_DIG_VOL:
347 case RT5677_IF_DSP_DAC2_MIXER:
348 case RT5677_STO1_ADC_DIG_VOL:
349 case RT5677_MONO_ADC_DIG_VOL:
350 case RT5677_STO1_2_ADC_BST:
351 case RT5677_STO2_ADC_DIG_VOL:
352 case RT5677_ADC_BST_CTRL2:
353 case RT5677_STO3_4_ADC_BST:
354 case RT5677_STO3_ADC_DIG_VOL:
355 case RT5677_STO4_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_MIXER:
357 case RT5677_STO3_ADC_MIXER:
358 case RT5677_STO2_ADC_MIXER:
359 case RT5677_STO1_ADC_MIXER:
360 case RT5677_MONO_ADC_MIXER:
361 case RT5677_ADC_IF_DSP_DAC1_MIXER:
362 case RT5677_STO1_DAC_MIXER:
363 case RT5677_MONO_DAC_MIXER:
364 case RT5677_DD1_MIXER:
365 case RT5677_DD2_MIXER:
366 case RT5677_IF3_DATA:
367 case RT5677_IF4_DATA:
368 case RT5677_PDM_OUT_CTRL:
369 case RT5677_PDM_DATA_CTRL1:
370 case RT5677_PDM_DATA_CTRL2:
371 case RT5677_PDM1_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL3:
373 case RT5677_PDM1_DATA_CTRL4:
374 case RT5677_PDM2_DATA_CTRL2:
375 case RT5677_PDM2_DATA_CTRL3:
376 case RT5677_PDM2_DATA_CTRL4:
377 case RT5677_TDM1_CTRL1:
378 case RT5677_TDM1_CTRL2:
379 case RT5677_TDM1_CTRL3:
380 case RT5677_TDM1_CTRL4:
381 case RT5677_TDM1_CTRL5:
382 case RT5677_TDM2_CTRL1:
383 case RT5677_TDM2_CTRL2:
384 case RT5677_TDM2_CTRL3:
385 case RT5677_TDM2_CTRL4:
386 case RT5677_TDM2_CTRL5:
387 case RT5677_I2C_MASTER_CTRL1:
388 case RT5677_I2C_MASTER_CTRL2:
389 case RT5677_I2C_MASTER_CTRL3:
390 case RT5677_I2C_MASTER_CTRL4:
391 case RT5677_I2C_MASTER_CTRL5:
392 case RT5677_I2C_MASTER_CTRL6:
393 case RT5677_I2C_MASTER_CTRL7:
394 case RT5677_I2C_MASTER_CTRL8:
395 case RT5677_DMIC_CTRL1:
396 case RT5677_DMIC_CTRL2:
397 case RT5677_HAP_GENE_CTRL1:
398 case RT5677_HAP_GENE_CTRL2:
399 case RT5677_HAP_GENE_CTRL3:
400 case RT5677_HAP_GENE_CTRL4:
401 case RT5677_HAP_GENE_CTRL5:
402 case RT5677_HAP_GENE_CTRL6:
403 case RT5677_HAP_GENE_CTRL7:
404 case RT5677_HAP_GENE_CTRL8:
405 case RT5677_HAP_GENE_CTRL9:
406 case RT5677_HAP_GENE_CTRL10:
407 case RT5677_PWR_DIG1:
408 case RT5677_PWR_DIG2:
409 case RT5677_PWR_ANLG1:
410 case RT5677_PWR_ANLG2:
411 case RT5677_PWR_DSP1:
412 case RT5677_PWR_DSP_ST:
413 case RT5677_PWR_DSP2:
414 case RT5677_ADC_DAC_HPF_CTRL1:
415 case RT5677_PRIV_INDEX:
416 case RT5677_PRIV_DATA:
417 case RT5677_I2S4_SDP:
418 case RT5677_I2S1_SDP:
419 case RT5677_I2S2_SDP:
420 case RT5677_I2S3_SDP:
421 case RT5677_CLK_TREE_CTRL1:
422 case RT5677_CLK_TREE_CTRL2:
423 case RT5677_CLK_TREE_CTRL3:
424 case RT5677_PLL1_CTRL1:
425 case RT5677_PLL1_CTRL2:
426 case RT5677_PLL2_CTRL1:
427 case RT5677_PLL2_CTRL2:
428 case RT5677_GLB_CLK1:
429 case RT5677_GLB_CLK2:
430 case RT5677_ASRC_1:
431 case RT5677_ASRC_2:
432 case RT5677_ASRC_3:
433 case RT5677_ASRC_4:
434 case RT5677_ASRC_5:
435 case RT5677_ASRC_6:
436 case RT5677_ASRC_7:
437 case RT5677_ASRC_8:
438 case RT5677_ASRC_9:
439 case RT5677_ASRC_10:
440 case RT5677_ASRC_11:
441 case RT5677_ASRC_12:
442 case RT5677_ASRC_13:
443 case RT5677_ASRC_14:
444 case RT5677_ASRC_15:
445 case RT5677_ASRC_16:
446 case RT5677_ASRC_17:
447 case RT5677_ASRC_18:
448 case RT5677_ASRC_19:
449 case RT5677_ASRC_20:
450 case RT5677_ASRC_21:
451 case RT5677_ASRC_22:
452 case RT5677_ASRC_23:
453 case RT5677_VAD_CTRL1:
454 case RT5677_VAD_CTRL2:
455 case RT5677_VAD_CTRL3:
456 case RT5677_VAD_CTRL4:
457 case RT5677_VAD_CTRL5:
458 case RT5677_DSP_INB_CTRL1:
459 case RT5677_DSP_INB_CTRL2:
460 case RT5677_DSP_IN_OUTB_CTRL:
461 case RT5677_DSP_OUTB0_1_DIG_VOL:
462 case RT5677_DSP_OUTB2_3_DIG_VOL:
463 case RT5677_DSP_OUTB4_5_DIG_VOL:
464 case RT5677_DSP_OUTB6_7_DIG_VOL:
465 case RT5677_ADC_EQ_CTRL1:
466 case RT5677_ADC_EQ_CTRL2:
467 case RT5677_EQ_CTRL1:
468 case RT5677_EQ_CTRL2:
469 case RT5677_EQ_CTRL3:
470 case RT5677_SOFT_VOL_ZERO_CROSS1:
471 case RT5677_JD_CTRL1:
472 case RT5677_JD_CTRL2:
473 case RT5677_JD_CTRL3:
474 case RT5677_IRQ_CTRL1:
475 case RT5677_IRQ_CTRL2:
476 case RT5677_GPIO_ST:
477 case RT5677_GPIO_CTRL1:
478 case RT5677_GPIO_CTRL2:
479 case RT5677_GPIO_CTRL3:
480 case RT5677_STO1_ADC_HI_FILTER1:
481 case RT5677_STO1_ADC_HI_FILTER2:
482 case RT5677_MONO_ADC_HI_FILTER1:
483 case RT5677_MONO_ADC_HI_FILTER2:
484 case RT5677_STO2_ADC_HI_FILTER1:
485 case RT5677_STO2_ADC_HI_FILTER2:
486 case RT5677_STO3_ADC_HI_FILTER1:
487 case RT5677_STO3_ADC_HI_FILTER2:
488 case RT5677_STO4_ADC_HI_FILTER1:
489 case RT5677_STO4_ADC_HI_FILTER2:
490 case RT5677_MB_DRC_CTRL1:
491 case RT5677_DRC1_CTRL1:
492 case RT5677_DRC1_CTRL2:
493 case RT5677_DRC1_CTRL3:
494 case RT5677_DRC1_CTRL4:
495 case RT5677_DRC1_CTRL5:
496 case RT5677_DRC1_CTRL6:
497 case RT5677_DRC2_CTRL1:
498 case RT5677_DRC2_CTRL2:
499 case RT5677_DRC2_CTRL3:
500 case RT5677_DRC2_CTRL4:
501 case RT5677_DRC2_CTRL5:
502 case RT5677_DRC2_CTRL6:
503 case RT5677_DRC1_HL_CTRL1:
504 case RT5677_DRC1_HL_CTRL2:
505 case RT5677_DRC2_HL_CTRL1:
506 case RT5677_DRC2_HL_CTRL2:
507 case RT5677_DSP_INB1_SRC_CTRL1:
508 case RT5677_DSP_INB1_SRC_CTRL2:
509 case RT5677_DSP_INB1_SRC_CTRL3:
510 case RT5677_DSP_INB1_SRC_CTRL4:
511 case RT5677_DSP_INB2_SRC_CTRL1:
512 case RT5677_DSP_INB2_SRC_CTRL2:
513 case RT5677_DSP_INB2_SRC_CTRL3:
514 case RT5677_DSP_INB2_SRC_CTRL4:
515 case RT5677_DSP_INB3_SRC_CTRL1:
516 case RT5677_DSP_INB3_SRC_CTRL2:
517 case RT5677_DSP_INB3_SRC_CTRL3:
518 case RT5677_DSP_INB3_SRC_CTRL4:
519 case RT5677_DSP_OUTB1_SRC_CTRL1:
520 case RT5677_DSP_OUTB1_SRC_CTRL2:
521 case RT5677_DSP_OUTB1_SRC_CTRL3:
522 case RT5677_DSP_OUTB1_SRC_CTRL4:
523 case RT5677_DSP_OUTB2_SRC_CTRL1:
524 case RT5677_DSP_OUTB2_SRC_CTRL2:
525 case RT5677_DSP_OUTB2_SRC_CTRL3:
526 case RT5677_DSP_OUTB2_SRC_CTRL4:
527 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
528 case RT5677_DSP_OUTB_45_MIXER_CTRL:
529 case RT5677_DSP_OUTB_67_MIXER_CTRL:
530 case RT5677_DIG_MISC:
531 case RT5677_GEN_CTRL1:
532 case RT5677_GEN_CTRL2:
533 case RT5677_VENDOR_ID:
534 case RT5677_VENDOR_ID1:
535 case RT5677_VENDOR_ID2:
536 return true;
537 default:
538 return false;
539 }
540 }
541
542 /**
543 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
544 * @rt5677: Private Data.
545 * @addr: Address index.
546 * @value: Address data.
547 *
548 *
549 * Returns 0 for success or negative error code.
550 */
551 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
552 unsigned int addr, unsigned int value, unsigned int opcode)
553 {
554 struct snd_soc_codec *codec = rt5677->codec;
555 int ret;
556
557 mutex_lock(&rt5677->dsp_cmd_lock);
558
559 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
560 addr >> 16);
561 if (ret < 0) {
562 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
563 goto err;
564 }
565
566 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
567 addr & 0xffff);
568 if (ret < 0) {
569 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
570 goto err;
571 }
572
573 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
574 value >> 16);
575 if (ret < 0) {
576 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
577 goto err;
578 }
579
580 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
581 value & 0xffff);
582 if (ret < 0) {
583 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
584 goto err;
585 }
586
587 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
588 opcode);
589 if (ret < 0) {
590 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
591 goto err;
592 }
593
594 err:
595 mutex_unlock(&rt5677->dsp_cmd_lock);
596
597 return ret;
598 }
599
600 /**
601 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
602 * rt5677: Private Data.
603 * @addr: Address index.
604 * @value: Address data.
605 *
606 *
607 * Returns 0 for success or negative error code.
608 */
609 static int rt5677_dsp_mode_i2c_read_addr(
610 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
611 {
612 struct snd_soc_codec *codec = rt5677->codec;
613 int ret;
614 unsigned int msb, lsb;
615
616 mutex_lock(&rt5677->dsp_cmd_lock);
617
618 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
619 addr >> 16);
620 if (ret < 0) {
621 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
622 goto err;
623 }
624
625 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
626 addr & 0xffff);
627 if (ret < 0) {
628 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
629 goto err;
630 }
631
632 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
633 0x0002);
634 if (ret < 0) {
635 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
636 goto err;
637 }
638
639 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
641 *value = (msb << 16) | lsb;
642
643 err:
644 mutex_unlock(&rt5677->dsp_cmd_lock);
645
646 return ret;
647 }
648
649 /**
650 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
651 * rt5677: Private Data.
652 * @reg: Register index.
653 * @value: Register data.
654 *
655 *
656 * Returns 0 for success or negative error code.
657 */
658 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
659 unsigned int reg, unsigned int value)
660 {
661 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
662 value, 0x0001);
663 }
664
665 /**
666 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
667 * @codec: SoC audio codec device.
668 * @reg: Register index.
669 * @value: Register data.
670 *
671 *
672 * Returns 0 for success or negative error code.
673 */
674 static int rt5677_dsp_mode_i2c_read(
675 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
676 {
677 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
678 value);
679
680 *value &= 0xffff;
681
682 return ret;
683 }
684
685 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
686 {
687 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
688
689 if (on) {
690 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
691 rt5677->is_dsp_mode = true;
692 } else {
693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
694 rt5677->is_dsp_mode = false;
695 }
696 }
697
698 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
699 {
700 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
701 static bool activity;
702 int ret;
703
704 if (on && !activity) {
705 activity = true;
706
707 regcache_cache_only(rt5677->regmap, false);
708 regcache_cache_bypass(rt5677->regmap, true);
709
710 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
711 regmap_update_bits(rt5677->regmap,
712 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
713 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
714 RT5677_LDO1_SEL_MASK, 0x0);
715 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
716 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
717 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
718 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
719 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
720 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
721 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
722 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
723 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
724 rt5677_set_dsp_mode(codec, true);
725
726 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
727 codec->dev);
728 if (ret == 0) {
729 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
730 release_firmware(rt5677->fw1);
731 }
732
733 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
734 codec->dev);
735 if (ret == 0) {
736 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
737 release_firmware(rt5677->fw2);
738 }
739
740 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
741
742 regcache_cache_bypass(rt5677->regmap, false);
743 regcache_cache_only(rt5677->regmap, true);
744 } else if (!on && activity) {
745 activity = false;
746
747 regcache_cache_only(rt5677->regmap, false);
748 regcache_cache_bypass(rt5677->regmap, true);
749
750 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
751 rt5677_set_dsp_mode(codec, false);
752 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
753
754 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
755
756 regcache_cache_bypass(rt5677->regmap, false);
757 regcache_mark_dirty(rt5677->regmap);
758 regcache_sync(rt5677->regmap);
759 }
760
761 return 0;
762 }
763
764 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
765 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
766 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
767 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
768 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
769 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
770
771 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
772 static unsigned int bst_tlv[] = {
773 TLV_DB_RANGE_HEAD(7),
774 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
775 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
776 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
777 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
778 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
779 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
780 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
781 };
782
783 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
785 {
786 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
787 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
788
789 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
790
791 return 0;
792 }
793
794 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
795 struct snd_ctl_elem_value *ucontrol)
796 {
797 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
798 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
799
800 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
801
802 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
803 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
804
805 return 0;
806 }
807
808 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
809 /* OUTPUT Control */
810 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
811 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
812 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
813 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
814 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
815 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
816
817 /* DAC Digital Volume */
818 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
819 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
820 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
821 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
822 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
823 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
824 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
825 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
826
827 /* IN1/IN2 Control */
828 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
829 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
830
831 /* ADC Digital Volume Control */
832 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
833 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
834 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
835 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
836 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
837 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
838 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
839 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
840 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
841 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
842
843 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
844 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
845 adc_vol_tlv),
846 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
847 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
848 adc_vol_tlv),
849 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
850 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
851 adc_vol_tlv),
852 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
853 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
854 adc_vol_tlv),
855 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
856 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
857 adc_vol_tlv),
858
859 /* Sidetone Control */
860 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
861 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
862
863 /* ADC Boost Volume Control */
864 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
865 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
866 adc_bst_tlv),
867 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
868 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
869 adc_bst_tlv),
870 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
871 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
872 adc_bst_tlv),
873 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
874 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
875 adc_bst_tlv),
876 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
877 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
878 adc_bst_tlv),
879
880 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
881 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
882 };
883
884 /**
885 * set_dmic_clk - Set parameter of dmic.
886 *
887 * @w: DAPM widget.
888 * @kcontrol: The kcontrol of this widget.
889 * @event: Event id.
890 *
891 * Choose dmic clock between 1MHz and 3MHz.
892 * It is better for clock to approximate 3MHz.
893 */
894 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
895 struct snd_kcontrol *kcontrol, int event)
896 {
897 struct snd_soc_codec *codec = w->codec;
898 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
899 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
900
901 if (idx < 0)
902 dev_err(codec->dev, "Failed to set DMIC clock\n");
903 else
904 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
905 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
906 return idx;
907 }
908
909 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
910 struct snd_soc_dapm_widget *sink)
911 {
912 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
913 unsigned int val;
914
915 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
916 val &= RT5677_SCLK_SRC_MASK;
917 if (val == RT5677_SCLK_SRC_PLL1)
918 return 1;
919 else
920 return 0;
921 }
922
923 /* Digital Mixer */
924 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
925 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
926 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
927 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
928 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
929 };
930
931 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
932 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
933 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
934 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
935 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
936 };
937
938 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
939 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
940 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
941 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
942 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
943 };
944
945 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
946 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
947 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
948 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
949 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
950 };
951
952 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
953 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
954 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
955 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
956 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
957 };
958
959 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
960 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
961 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
962 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
963 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
964 };
965
966 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
967 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
968 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
969 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
970 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
971 };
972
973 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
974 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
975 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
976 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
977 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
978 };
979
980 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
981 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
982 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
983 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
984 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
985 };
986
987 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
988 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
989 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
990 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
991 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
992 };
993
994 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
995 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
996 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
997 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
998 RT5677_M_DAC1_L_SFT, 1, 1),
999 };
1000
1001 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1002 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1003 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1004 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1005 RT5677_M_DAC1_R_SFT, 1, 1),
1006 };
1007
1008 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1009 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1010 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1011 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1012 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1013 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1014 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1015 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1016 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1017 };
1018
1019 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1020 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1021 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1022 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1023 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1024 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1025 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1026 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1027 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1028 };
1029
1030 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1031 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1032 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1033 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1034 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1035 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1036 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1037 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1038 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1039 };
1040
1041 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1042 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1043 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1044 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1045 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1046 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1047 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1049 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1050 };
1051
1052 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1053 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1054 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1055 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1056 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1057 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1058 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1059 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1060 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1061 };
1062
1063 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1064 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1065 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1066 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1067 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1068 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1069 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1071 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1072 };
1073
1074 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1075 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1076 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1077 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1078 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1079 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1080 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1081 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1082 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1083 };
1084
1085 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1086 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1087 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1088 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1089 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1090 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1091 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1092 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1093 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1094 };
1095
1096 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1097 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1098 RT5677_DSP_IB_01_H_SFT, 1, 1),
1099 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1100 RT5677_DSP_IB_23_H_SFT, 1, 1),
1101 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1102 RT5677_DSP_IB_45_H_SFT, 1, 1),
1103 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1104 RT5677_DSP_IB_6_H_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1106 RT5677_DSP_IB_7_H_SFT, 1, 1),
1107 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1108 RT5677_DSP_IB_8_H_SFT, 1, 1),
1109 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1110 RT5677_DSP_IB_9_H_SFT, 1, 1),
1111 };
1112
1113 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1114 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1115 RT5677_DSP_IB_01_L_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1117 RT5677_DSP_IB_23_L_SFT, 1, 1),
1118 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1119 RT5677_DSP_IB_45_L_SFT, 1, 1),
1120 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1121 RT5677_DSP_IB_6_L_SFT, 1, 1),
1122 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1123 RT5677_DSP_IB_7_L_SFT, 1, 1),
1124 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1125 RT5677_DSP_IB_8_L_SFT, 1, 1),
1126 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1127 RT5677_DSP_IB_9_L_SFT, 1, 1),
1128 };
1129
1130 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1131 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1132 RT5677_DSP_IB_01_H_SFT, 1, 1),
1133 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1134 RT5677_DSP_IB_23_H_SFT, 1, 1),
1135 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1136 RT5677_DSP_IB_45_H_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1138 RT5677_DSP_IB_6_H_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1140 RT5677_DSP_IB_7_H_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1142 RT5677_DSP_IB_8_H_SFT, 1, 1),
1143 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1144 RT5677_DSP_IB_9_H_SFT, 1, 1),
1145 };
1146
1147 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1148 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1149 RT5677_DSP_IB_01_L_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1151 RT5677_DSP_IB_23_L_SFT, 1, 1),
1152 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1153 RT5677_DSP_IB_45_L_SFT, 1, 1),
1154 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1155 RT5677_DSP_IB_6_L_SFT, 1, 1),
1156 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1157 RT5677_DSP_IB_7_L_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1159 RT5677_DSP_IB_8_L_SFT, 1, 1),
1160 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1161 RT5677_DSP_IB_9_L_SFT, 1, 1),
1162 };
1163
1164 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1165 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1166 RT5677_DSP_IB_01_H_SFT, 1, 1),
1167 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1168 RT5677_DSP_IB_23_H_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1170 RT5677_DSP_IB_45_H_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1172 RT5677_DSP_IB_6_H_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1174 RT5677_DSP_IB_7_H_SFT, 1, 1),
1175 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1176 RT5677_DSP_IB_8_H_SFT, 1, 1),
1177 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1178 RT5677_DSP_IB_9_H_SFT, 1, 1),
1179 };
1180
1181 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1182 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1183 RT5677_DSP_IB_01_L_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1185 RT5677_DSP_IB_23_L_SFT, 1, 1),
1186 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1187 RT5677_DSP_IB_45_L_SFT, 1, 1),
1188 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1189 RT5677_DSP_IB_6_L_SFT, 1, 1),
1190 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1191 RT5677_DSP_IB_7_L_SFT, 1, 1),
1192 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1193 RT5677_DSP_IB_8_L_SFT, 1, 1),
1194 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1195 RT5677_DSP_IB_9_L_SFT, 1, 1),
1196 };
1197
1198
1199 /* Mux */
1200 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1201 static const char * const rt5677_dac1_src[] = {
1202 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1203 "OB 01"
1204 };
1205
1206 static SOC_ENUM_SINGLE_DECL(
1207 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1208 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1209
1210 static const struct snd_kcontrol_new rt5677_dac1_mux =
1211 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1212
1213 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1214 static const char * const rt5677_adda1_src[] = {
1215 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1216 };
1217
1218 static SOC_ENUM_SINGLE_DECL(
1219 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1220 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1221
1222 static const struct snd_kcontrol_new rt5677_adda1_mux =
1223 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1224
1225
1226 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1227 static const char * const rt5677_dac2l_src[] = {
1228 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1229 "OB 2",
1230 };
1231
1232 static SOC_ENUM_SINGLE_DECL(
1233 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1234 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1235
1236 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1237 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1238
1239 static const char * const rt5677_dac2r_src[] = {
1240 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1241 "OB 3", "Haptic Generator", "VAD ADC"
1242 };
1243
1244 static SOC_ENUM_SINGLE_DECL(
1245 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1246 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1247
1248 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1249 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1250
1251 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1252 static const char * const rt5677_dac3l_src[] = {
1253 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1254 "SLB DAC 4", "OB 4"
1255 };
1256
1257 static SOC_ENUM_SINGLE_DECL(
1258 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1259 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1260
1261 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1262 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1263
1264 static const char * const rt5677_dac3r_src[] = {
1265 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1266 "SLB DAC 5", "OB 5"
1267 };
1268
1269 static SOC_ENUM_SINGLE_DECL(
1270 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1271 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1272
1273 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1274 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1275
1276 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1277 static const char * const rt5677_dac4l_src[] = {
1278 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1279 "SLB DAC 6", "OB 6"
1280 };
1281
1282 static SOC_ENUM_SINGLE_DECL(
1283 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1284 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1285
1286 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1287 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1288
1289 static const char * const rt5677_dac4r_src[] = {
1290 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1291 "SLB DAC 7", "OB 7"
1292 };
1293
1294 static SOC_ENUM_SINGLE_DECL(
1295 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1296 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1297
1298 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1299 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1300
1301 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1302 static const char * const rt5677_iob_bypass_src[] = {
1303 "Bypass", "Pass SRC"
1304 };
1305
1306 static SOC_ENUM_SINGLE_DECL(
1307 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1308 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1309
1310 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1311 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1312
1313 static SOC_ENUM_SINGLE_DECL(
1314 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1315 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1316
1317 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1318 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1319
1320 static SOC_ENUM_SINGLE_DECL(
1321 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1322 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1323
1324 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1325 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1326
1327 static SOC_ENUM_SINGLE_DECL(
1328 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1329 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1330
1331 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1332 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1333
1334 static SOC_ENUM_SINGLE_DECL(
1335 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1336 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1337
1338 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1339 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1340
1341 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1342 static const char * const rt5677_stereo_adc2_src[] = {
1343 "DD MIX1", "DMIC", "Stereo DAC MIX"
1344 };
1345
1346 static SOC_ENUM_SINGLE_DECL(
1347 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1348 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1349
1350 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1351 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1352
1353 static SOC_ENUM_SINGLE_DECL(
1354 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1355 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1356
1357 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1358 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1359
1360 static SOC_ENUM_SINGLE_DECL(
1361 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1362 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1363
1364 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1365 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1366
1367 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1368 static const char * const rt5677_dmic_src[] = {
1369 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1370 };
1371
1372 static SOC_ENUM_SINGLE_DECL(
1373 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1374 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1375
1376 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1377 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1378
1379 static SOC_ENUM_SINGLE_DECL(
1380 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1381 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1382
1383 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1384 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1385
1386 static SOC_ENUM_SINGLE_DECL(
1387 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1388 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1389
1390 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1391 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1392
1393 static SOC_ENUM_SINGLE_DECL(
1394 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1395 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1396
1397 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1398 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1399
1400 static SOC_ENUM_SINGLE_DECL(
1401 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1402 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1403
1404 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1405 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1406
1407 static SOC_ENUM_SINGLE_DECL(
1408 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1409 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1410
1411 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1412 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1413
1414 /* Stereo2 ADC Source */ /* MX-26 [0] */
1415 static const char * const rt5677_stereo2_adc_lr_src[] = {
1416 "L", "LR"
1417 };
1418
1419 static SOC_ENUM_SINGLE_DECL(
1420 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1421 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1422
1423 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1424 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1425
1426 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1427 static const char * const rt5677_stereo_adc1_src[] = {
1428 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1429 };
1430
1431 static SOC_ENUM_SINGLE_DECL(
1432 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1433 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1434
1435 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1436 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1437
1438 static SOC_ENUM_SINGLE_DECL(
1439 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1440 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1441
1442 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1443 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1444
1445 static SOC_ENUM_SINGLE_DECL(
1446 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1447 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1448
1449 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1450 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1451
1452 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1453 static const char * const rt5677_mono_adc2_l_src[] = {
1454 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1455 };
1456
1457 static SOC_ENUM_SINGLE_DECL(
1458 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1459 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1460
1461 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1462 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1463
1464 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1465 static const char * const rt5677_mono_adc1_l_src[] = {
1466 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1467 };
1468
1469 static SOC_ENUM_SINGLE_DECL(
1470 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1471 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1472
1473 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1474 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1475
1476 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1477 static const char * const rt5677_mono_adc2_r_src[] = {
1478 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1479 };
1480
1481 static SOC_ENUM_SINGLE_DECL(
1482 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1483 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1484
1485 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1486 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1487
1488 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1489 static const char * const rt5677_mono_adc1_r_src[] = {
1490 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1491 };
1492
1493 static SOC_ENUM_SINGLE_DECL(
1494 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1495 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1496
1497 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1498 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1499
1500 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1501 static const char * const rt5677_stereo4_adc2_src[] = {
1502 "DD MIX1", "DMIC", "DD MIX2"
1503 };
1504
1505 static SOC_ENUM_SINGLE_DECL(
1506 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1507 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1508
1509 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1510 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1511
1512
1513 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1514 static const char * const rt5677_stereo4_adc1_src[] = {
1515 "DD MIX1", "ADC1/2", "DD MIX2"
1516 };
1517
1518 static SOC_ENUM_SINGLE_DECL(
1519 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1520 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1521
1522 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1523 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1524
1525 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1526 static const char * const rt5677_inbound01_src[] = {
1527 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1528 "VAD ADC/DAC1 FS"
1529 };
1530
1531 static SOC_ENUM_SINGLE_DECL(
1532 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1533 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1534
1535 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1536 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1537
1538 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1539 static const char * const rt5677_inbound23_src[] = {
1540 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1541 "DAC1 FS", "IF4 DAC"
1542 };
1543
1544 static SOC_ENUM_SINGLE_DECL(
1545 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1546 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1547
1548 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1549 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1550
1551 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1552 static const char * const rt5677_inbound45_src[] = {
1553 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1554 "IF3 DAC"
1555 };
1556
1557 static SOC_ENUM_SINGLE_DECL(
1558 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1559 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1560
1561 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1562 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1563
1564 /* InBound6 Source */ /* MX-A3 [2:0] */
1565 static const char * const rt5677_inbound6_src[] = {
1566 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1567 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1568 };
1569
1570 static SOC_ENUM_SINGLE_DECL(
1571 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1572 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1573
1574 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1575 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1576
1577 /* InBound7 Source */ /* MX-A4 [14:12] */
1578 static const char * const rt5677_inbound7_src[] = {
1579 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1580 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1581 };
1582
1583 static SOC_ENUM_SINGLE_DECL(
1584 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1585 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1586
1587 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1588 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1589
1590 /* InBound8 Source */ /* MX-A4 [10:8] */
1591 static const char * const rt5677_inbound8_src[] = {
1592 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1593 "MONO ADC MIX L", "DACL1 FS"
1594 };
1595
1596 static SOC_ENUM_SINGLE_DECL(
1597 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1598 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1599
1600 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1601 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1602
1603 /* InBound9 Source */ /* MX-A4 [6:4] */
1604 static const char * const rt5677_inbound9_src[] = {
1605 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1606 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1607 };
1608
1609 static SOC_ENUM_SINGLE_DECL(
1610 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1611 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1612
1613 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1614 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1615
1616 /* VAD Source */ /* MX-9F [6:4] */
1617 static const char * const rt5677_vad_src[] = {
1618 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1619 "STO3 ADC MIX L"
1620 };
1621
1622 static SOC_ENUM_SINGLE_DECL(
1623 rt5677_vad_enum, RT5677_VAD_CTRL4,
1624 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1625
1626 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1627 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1628
1629 /* Sidetone Source */ /* MX-13 [11:9] */
1630 static const char * const rt5677_sidetone_src[] = {
1631 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1632 };
1633
1634 static SOC_ENUM_SINGLE_DECL(
1635 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1636 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1637
1638 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1639 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1640
1641 /* DAC1/2 Source */ /* MX-15 [1:0] */
1642 static const char * const rt5677_dac12_src[] = {
1643 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1644 };
1645
1646 static SOC_ENUM_SINGLE_DECL(
1647 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1648 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1649
1650 static const struct snd_kcontrol_new rt5677_dac12_mux =
1651 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1652
1653 /* DAC3 Source */ /* MX-15 [5:4] */
1654 static const char * const rt5677_dac3_src[] = {
1655 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1656 };
1657
1658 static SOC_ENUM_SINGLE_DECL(
1659 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1660 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1661
1662 static const struct snd_kcontrol_new rt5677_dac3_mux =
1663 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1664
1665 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1666 static const char * const rt5677_pdm_src[] = {
1667 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1668 };
1669
1670 static SOC_ENUM_SINGLE_DECL(
1671 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1672 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1673
1674 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1675 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1676
1677 static SOC_ENUM_SINGLE_DECL(
1678 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1679 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1680
1681 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1682 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1683
1684 static SOC_ENUM_SINGLE_DECL(
1685 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1686 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1687
1688 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1689 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1690
1691 static SOC_ENUM_SINGLE_DECL(
1692 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1693 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1694
1695 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1696 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1697
1698 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1699 static const char * const rt5677_if12_adc1_src[] = {
1700 "STO1 ADC MIX", "OB01", "VAD ADC"
1701 };
1702
1703 static SOC_ENUM_SINGLE_DECL(
1704 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1705 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1706
1707 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1708 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1709
1710 static SOC_ENUM_SINGLE_DECL(
1711 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1712 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1713
1714 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1715 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1716
1717 static SOC_ENUM_SINGLE_DECL(
1718 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1719 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1720
1721 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1722 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1723
1724 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1725 static const char * const rt5677_if12_adc2_src[] = {
1726 "STO2 ADC MIX", "OB23"
1727 };
1728
1729 static SOC_ENUM_SINGLE_DECL(
1730 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1731 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1732
1733 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1734 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1735
1736 static SOC_ENUM_SINGLE_DECL(
1737 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1738 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1739
1740 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1741 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1742
1743 static SOC_ENUM_SINGLE_DECL(
1744 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1745 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1746
1747 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1748 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1749
1750 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1751 static const char * const rt5677_if12_adc3_src[] = {
1752 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1753 };
1754
1755 static SOC_ENUM_SINGLE_DECL(
1756 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1757 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1758
1759 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1760 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1761
1762 static SOC_ENUM_SINGLE_DECL(
1763 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1764 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1765
1766 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1767 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1768
1769 static SOC_ENUM_SINGLE_DECL(
1770 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1771 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1772
1773 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1774 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1775
1776 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1777 static const char * const rt5677_if12_adc4_src[] = {
1778 "STO4 ADC MIX", "OB67", "OB01"
1779 };
1780
1781 static SOC_ENUM_SINGLE_DECL(
1782 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1783 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1784
1785 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1786 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1787
1788 static SOC_ENUM_SINGLE_DECL(
1789 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1790 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1791
1792 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1793 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1794
1795 static SOC_ENUM_SINGLE_DECL(
1796 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1797 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1798
1799 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1800 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1801
1802 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
1803 static const char * const rt5677_if34_adc_src[] = {
1804 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1805 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1806 };
1807
1808 static SOC_ENUM_SINGLE_DECL(
1809 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1810 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1811
1812 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1813 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1814
1815 static SOC_ENUM_SINGLE_DECL(
1816 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1817 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1818
1819 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1820 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1821
1822 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1823 static const char * const rt5677_if12_adc_swap_src[] = {
1824 "L/R", "R/L", "L/L", "R/R"
1825 };
1826
1827 static SOC_ENUM_SINGLE_DECL(
1828 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1829 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1830
1831 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1832 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1833
1834 static SOC_ENUM_SINGLE_DECL(
1835 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1836 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1837
1838 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1839 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1840
1841 static SOC_ENUM_SINGLE_DECL(
1842 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1843 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1844
1845 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1846 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1847
1848 static SOC_ENUM_SINGLE_DECL(
1849 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1850 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1851
1852 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1853 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1854
1855 static SOC_ENUM_SINGLE_DECL(
1856 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1857 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1858
1859 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1860 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1861
1862 static SOC_ENUM_SINGLE_DECL(
1863 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1864 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1865
1866 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1867 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1868
1869 static SOC_ENUM_SINGLE_DECL(
1870 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1871 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1872
1873 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1874 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1875
1876 static SOC_ENUM_SINGLE_DECL(
1877 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1878 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1879
1880 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1881 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1882
1883 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
1884 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1885 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1886 "3/1/2/4", "3/4/1/2"
1887 };
1888
1889 static SOC_ENUM_SINGLE_DECL(
1890 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1891 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1892
1893 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1894 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1895
1896 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1897 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1898 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1899 "2/3/1/4", "3/4/1/2"
1900 };
1901
1902 static SOC_ENUM_SINGLE_DECL(
1903 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
1904 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
1905
1906 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
1907 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
1908
1909 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1910 struct snd_kcontrol *kcontrol, int event)
1911 {
1912 struct snd_soc_codec *codec = w->codec;
1913 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1914
1915 switch (event) {
1916 case SND_SOC_DAPM_POST_PMU:
1917 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1918 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1919 break;
1920
1921 case SND_SOC_DAPM_PRE_PMD:
1922 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1923 RT5677_PWR_BST1_P, 0);
1924 break;
1925
1926 default:
1927 return 0;
1928 }
1929
1930 return 0;
1931 }
1932
1933 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1934 struct snd_kcontrol *kcontrol, int event)
1935 {
1936 struct snd_soc_codec *codec = w->codec;
1937 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1938
1939 switch (event) {
1940 case SND_SOC_DAPM_POST_PMU:
1941 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1942 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1943 break;
1944
1945 case SND_SOC_DAPM_PRE_PMD:
1946 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1947 RT5677_PWR_BST2_P, 0);
1948 break;
1949
1950 default:
1951 return 0;
1952 }
1953
1954 return 0;
1955 }
1956
1957 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1958 struct snd_kcontrol *kcontrol, int event)
1959 {
1960 struct snd_soc_codec *codec = w->codec;
1961 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1962
1963 switch (event) {
1964 case SND_SOC_DAPM_POST_PMU:
1965 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1966 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1967 break;
1968 default:
1969 return 0;
1970 }
1971
1972 return 0;
1973 }
1974
1975 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1976 struct snd_kcontrol *kcontrol, int event)
1977 {
1978 struct snd_soc_codec *codec = w->codec;
1979 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1980
1981 switch (event) {
1982 case SND_SOC_DAPM_POST_PMU:
1983 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1984 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1985 break;
1986 default:
1987 return 0;
1988 }
1989
1990 return 0;
1991 }
1992
1993 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1994 struct snd_kcontrol *kcontrol, int event)
1995 {
1996 struct snd_soc_codec *codec = w->codec;
1997 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1998
1999 switch (event) {
2000 case SND_SOC_DAPM_POST_PMU:
2001 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2002 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2003 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2004 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2005 break;
2006
2007 case SND_SOC_DAPM_PRE_PMD:
2008 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2009 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2010 RT5677_PWR_CLK_MB, 0);
2011 break;
2012
2013 default:
2014 return 0;
2015 }
2016
2017 return 0;
2018 }
2019
2020 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2021 struct snd_kcontrol *kcontrol, int event)
2022 {
2023 struct snd_soc_codec *codec = w->codec;
2024 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2025 unsigned int value;
2026
2027 switch (event) {
2028 case SND_SOC_DAPM_PRE_PMU:
2029 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2030 if (value & RT5677_IF1_ADC_CTRL_MASK)
2031 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2032 RT5677_IF1_ADC_MODE_MASK,
2033 RT5677_IF1_ADC_MODE_TDM);
2034 break;
2035
2036 default:
2037 return 0;
2038 }
2039
2040 return 0;
2041 }
2042
2043 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2044 struct snd_kcontrol *kcontrol, int event)
2045 {
2046 struct snd_soc_codec *codec = w->codec;
2047 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2048 unsigned int value;
2049
2050 switch (event) {
2051 case SND_SOC_DAPM_PRE_PMU:
2052 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2053 if (value & RT5677_IF2_ADC_CTRL_MASK)
2054 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2055 RT5677_IF2_ADC_MODE_MASK,
2056 RT5677_IF2_ADC_MODE_TDM);
2057 break;
2058
2059 default:
2060 return 0;
2061 }
2062
2063 return 0;
2064 }
2065
2066 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2067 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2068 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
2069 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2070 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
2071
2072 /* Input Side */
2073 /* micbias */
2074 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2075 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2076 SND_SOC_DAPM_POST_PMU),
2077
2078 /* Input Lines */
2079 SND_SOC_DAPM_INPUT("DMIC L1"),
2080 SND_SOC_DAPM_INPUT("DMIC R1"),
2081 SND_SOC_DAPM_INPUT("DMIC L2"),
2082 SND_SOC_DAPM_INPUT("DMIC R2"),
2083 SND_SOC_DAPM_INPUT("DMIC L3"),
2084 SND_SOC_DAPM_INPUT("DMIC R3"),
2085 SND_SOC_DAPM_INPUT("DMIC L4"),
2086 SND_SOC_DAPM_INPUT("DMIC R4"),
2087
2088 SND_SOC_DAPM_INPUT("IN1P"),
2089 SND_SOC_DAPM_INPUT("IN1N"),
2090 SND_SOC_DAPM_INPUT("IN2P"),
2091 SND_SOC_DAPM_INPUT("IN2N"),
2092
2093 SND_SOC_DAPM_INPUT("Haptic Generator"),
2094
2095 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2096 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2097 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2098 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2099
2100 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2101 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2102 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2103 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2104 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2105 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2106 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2107 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2108
2109 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2110 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2111
2112 /* Boost */
2113 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2114 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2115 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2116 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2117 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2118 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2119
2120 /* ADCs */
2121 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2122 0, 0),
2123 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2124 0, 0),
2125 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2126
2127 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2128 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2129 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2130 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2131 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2132 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2133 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2134 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2135
2136 /* ADC Mux */
2137 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2138 &rt5677_sto1_dmic_mux),
2139 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2140 &rt5677_sto1_adc1_mux),
2141 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2142 &rt5677_sto1_adc2_mux),
2143 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2144 &rt5677_sto2_dmic_mux),
2145 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2146 &rt5677_sto2_adc1_mux),
2147 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2148 &rt5677_sto2_adc2_mux),
2149 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2150 &rt5677_sto2_adc_lr_mux),
2151 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2152 &rt5677_sto3_dmic_mux),
2153 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2154 &rt5677_sto3_adc1_mux),
2155 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2156 &rt5677_sto3_adc2_mux),
2157 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2158 &rt5677_sto4_dmic_mux),
2159 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2160 &rt5677_sto4_adc1_mux),
2161 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2162 &rt5677_sto4_adc2_mux),
2163 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2164 &rt5677_mono_dmic_l_mux),
2165 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2166 &rt5677_mono_dmic_r_mux),
2167 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2168 &rt5677_mono_adc2_l_mux),
2169 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2170 &rt5677_mono_adc1_l_mux),
2171 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2172 &rt5677_mono_adc1_r_mux),
2173 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2174 &rt5677_mono_adc2_r_mux),
2175
2176 /* ADC Mixer */
2177 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2178 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2179 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2180 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2181 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2182 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2183 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2184 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2185 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2186 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2187 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2188 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2189 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2190 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2191 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2192 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2193 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2194 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2195 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2196 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2197 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2198 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2199 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2200 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2201 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2202 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2203 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2204 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2205 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2206 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2207 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2208 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2209
2210 /* ADC PGA */
2211 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2212 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2213 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2214 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2215 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2216 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2217 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2218 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2219 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2220 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2221 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2222 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2223 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2224 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2225 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2226 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2227
2228 /* DSP */
2229 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2230 &rt5677_ib9_src_mux),
2231 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2232 &rt5677_ib8_src_mux),
2233 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2234 &rt5677_ib7_src_mux),
2235 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2236 &rt5677_ib6_src_mux),
2237 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2238 &rt5677_ib45_src_mux),
2239 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2240 &rt5677_ib23_src_mux),
2241 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2242 &rt5677_ib01_src_mux),
2243 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2244 &rt5677_ib45_bypass_src_mux),
2245 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2246 &rt5677_ib23_bypass_src_mux),
2247 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2248 &rt5677_ib01_bypass_src_mux),
2249 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2250 &rt5677_ob23_bypass_src_mux),
2251 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2252 &rt5677_ob01_bypass_src_mux),
2253
2254 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2255 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2256
2257 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2258 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2259 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2260 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2261 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2262 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2263
2264 /* Digital Interface */
2265 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2266 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2267 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2268 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2269 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2270 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2271 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2272 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2273 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2274 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2275 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2276 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2277 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2278 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2279 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2280 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2281 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2282 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2283
2284 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2285 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2286 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2287 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2288 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2289 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2290 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2291 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2292 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2293 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2294 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2295 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2296 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2297 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2298 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2299 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2300 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2301 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2302
2303 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2304 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2305 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2306 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2307 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2308 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2309 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2310 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2311
2312 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2313 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2314 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2315 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2316 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2317 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2318 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2319 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2320
2321 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2322 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2323 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2324 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2325 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2326 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2327 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2328 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2329 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2330 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2331 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2332 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2333 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2334 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2335 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2336 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2337 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2338 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2339
2340 /* Digital Interface Select */
2341 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2342 &rt5677_if1_adc1_mux),
2343 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2344 &rt5677_if1_adc2_mux),
2345 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2346 &rt5677_if1_adc3_mux),
2347 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2348 &rt5677_if1_adc4_mux),
2349 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2350 &rt5677_if1_adc1_swap_mux),
2351 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2352 &rt5677_if1_adc2_swap_mux),
2353 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2354 &rt5677_if1_adc3_swap_mux),
2355 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2356 &rt5677_if1_adc4_swap_mux),
2357 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2358 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2359 SND_SOC_DAPM_PRE_PMU),
2360 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2361 &rt5677_if2_adc1_mux),
2362 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2363 &rt5677_if2_adc2_mux),
2364 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2365 &rt5677_if2_adc3_mux),
2366 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2367 &rt5677_if2_adc4_mux),
2368 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2369 &rt5677_if2_adc1_swap_mux),
2370 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2371 &rt5677_if2_adc2_swap_mux),
2372 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2373 &rt5677_if2_adc3_swap_mux),
2374 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2375 &rt5677_if2_adc4_swap_mux),
2376 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2377 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2378 SND_SOC_DAPM_PRE_PMU),
2379 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2380 &rt5677_if3_adc_mux),
2381 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2382 &rt5677_if4_adc_mux),
2383 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2384 &rt5677_slb_adc1_mux),
2385 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2386 &rt5677_slb_adc2_mux),
2387 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2388 &rt5677_slb_adc3_mux),
2389 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2390 &rt5677_slb_adc4_mux),
2391
2392 /* Audio Interface */
2393 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2394 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2395 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2396 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2397 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2398 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2399 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2400 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2401 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2402 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2403
2404 /* Sidetone Mux */
2405 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2406 &rt5677_sidetone_mux),
2407 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2408 RT5677_ST_EN_SFT, 0, NULL, 0),
2409
2410 /* VAD Mux*/
2411 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2412 &rt5677_vad_src_mux),
2413
2414 /* Tensilica DSP */
2415 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2416 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2417 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2418 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2419 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2420 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2421 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2422 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2423 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2424 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2425 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2426 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2427 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2428
2429 /* Output Side */
2430 /* DAC mixer before sound effect */
2431 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2432 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2433 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2434 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2435 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2436
2437 /* DAC Mux */
2438 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2439 &rt5677_dac1_mux),
2440 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2441 &rt5677_adda1_mux),
2442 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2443 &rt5677_dac12_mux),
2444 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2445 &rt5677_dac3_mux),
2446
2447 /* DAC2 channel Mux */
2448 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2449 &rt5677_dac2_l_mux),
2450 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2451 &rt5677_dac2_r_mux),
2452
2453 /* DAC3 channel Mux */
2454 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2455 &rt5677_dac3_l_mux),
2456 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2457 &rt5677_dac3_r_mux),
2458
2459 /* DAC4 channel Mux */
2460 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2461 &rt5677_dac4_l_mux),
2462 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2463 &rt5677_dac4_r_mux),
2464
2465 /* DAC Mixer */
2466 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2467 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2468 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2469 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2470 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2471 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2472
2473 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2474 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2475 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2476 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2477 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2478 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2479 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2480 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2481 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2482 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2483 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2484 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2485 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2486 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2487 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2488 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2489 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2490 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2491 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2492 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2493
2494 /* DACs */
2495 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2496 RT5677_PWR_DAC1_BIT, 0),
2497 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2498 RT5677_PWR_DAC2_BIT, 0),
2499 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2500 RT5677_PWR_DAC3_BIT, 0),
2501
2502 /* PDM */
2503 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2504 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2505 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2506 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2507
2508 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2509 1, &rt5677_pdm1_l_mux),
2510 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2511 1, &rt5677_pdm1_r_mux),
2512 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2513 1, &rt5677_pdm2_l_mux),
2514 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2515 1, &rt5677_pdm2_r_mux),
2516
2517 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2518 0, NULL, 0),
2519 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2520 0, NULL, 0),
2521 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2522 0, NULL, 0),
2523
2524 /* Output Lines */
2525 SND_SOC_DAPM_OUTPUT("LOUT1"),
2526 SND_SOC_DAPM_OUTPUT("LOUT2"),
2527 SND_SOC_DAPM_OUTPUT("LOUT3"),
2528 SND_SOC_DAPM_OUTPUT("PDM1L"),
2529 SND_SOC_DAPM_OUTPUT("PDM1R"),
2530 SND_SOC_DAPM_OUTPUT("PDM2L"),
2531 SND_SOC_DAPM_OUTPUT("PDM2R"),
2532 };
2533
2534 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2535 { "DMIC1", NULL, "DMIC L1" },
2536 { "DMIC1", NULL, "DMIC R1" },
2537 { "DMIC2", NULL, "DMIC L2" },
2538 { "DMIC2", NULL, "DMIC R2" },
2539 { "DMIC3", NULL, "DMIC L3" },
2540 { "DMIC3", NULL, "DMIC R3" },
2541 { "DMIC4", NULL, "DMIC L4" },
2542 { "DMIC4", NULL, "DMIC R4" },
2543
2544 { "DMIC L1", NULL, "DMIC CLK" },
2545 { "DMIC R1", NULL, "DMIC CLK" },
2546 { "DMIC L2", NULL, "DMIC CLK" },
2547 { "DMIC R2", NULL, "DMIC CLK" },
2548 { "DMIC L3", NULL, "DMIC CLK" },
2549 { "DMIC R3", NULL, "DMIC CLK" },
2550 { "DMIC L4", NULL, "DMIC CLK" },
2551 { "DMIC R4", NULL, "DMIC CLK" },
2552
2553 { "DMIC L1", NULL, "DMIC1 power" },
2554 { "DMIC R1", NULL, "DMIC1 power" },
2555 { "DMIC L3", NULL, "DMIC3 power" },
2556 { "DMIC R3", NULL, "DMIC3 power" },
2557 { "DMIC L4", NULL, "DMIC4 power" },
2558 { "DMIC R4", NULL, "DMIC4 power" },
2559
2560 { "BST1", NULL, "IN1P" },
2561 { "BST1", NULL, "IN1N" },
2562 { "BST2", NULL, "IN2P" },
2563 { "BST2", NULL, "IN2N" },
2564
2565 { "IN1P", NULL, "MICBIAS1" },
2566 { "IN1N", NULL, "MICBIAS1" },
2567 { "IN2P", NULL, "MICBIAS1" },
2568 { "IN2N", NULL, "MICBIAS1" },
2569
2570 { "ADC 1", NULL, "BST1" },
2571 { "ADC 1", NULL, "ADC 1 power" },
2572 { "ADC 1", NULL, "ADC1 clock" },
2573 { "ADC 2", NULL, "BST2" },
2574 { "ADC 2", NULL, "ADC 2 power" },
2575 { "ADC 2", NULL, "ADC2 clock" },
2576
2577 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2578 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2579 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2580 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2581
2582 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2583 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2584 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2585 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2586
2587 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2588 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2589 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2590 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2591
2592 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2593 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2594 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2595 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2596
2597 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2598 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2599 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2600 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2601
2602 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2603 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2604 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2605 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2606
2607 { "ADC 1_2", NULL, "ADC 1" },
2608 { "ADC 1_2", NULL, "ADC 2" },
2609
2610 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2611 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2612 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2613
2614 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2615 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2616 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2617
2618 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2619 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2620 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2621
2622 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2623 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2624 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2625
2626 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2627 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2628 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2629
2630 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2631 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2632 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2633
2634 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2635 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2636 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2637
2638 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2639 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2640 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2641
2642 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2643 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2644 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2645
2646 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2647 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2648 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2649
2650 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2651 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2652 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2653
2654 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2655 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2656 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2657
2658 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2659 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2660 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2661 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2662
2663 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2664 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2665 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2666
2667 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2668 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2669 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2670
2671 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2672 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2673
2674 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2675 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2676 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2677 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2678
2679 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2680 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2681
2682 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2683 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2684
2685 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2686 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2687 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2688
2689 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2690 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2691 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2692
2693 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2694 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2695
2696 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2697 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2698 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2699 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2700
2701 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2702 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2703 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2704
2705 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2706 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2707 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2708
2709 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2710 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2711
2712 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2713 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2714 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2715 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2716
2717 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2718 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2719 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2720
2721 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2722 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2723 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2724
2725 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2726 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2727
2728 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2729 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2730 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2731 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2732
2733 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2734 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2735 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2736 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2737
2738 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2739 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2740
2741 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2742 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2743 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2744 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2745 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2746
2747 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2748 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2749 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2750
2751 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2752 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2753
2754 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2755 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2756 { "IF1 ADC3 Mux", "OB45", "OB45" },
2757
2758 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2759 { "IF1 ADC4 Mux", "OB67", "OB67" },
2760 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2761
2762 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
2763 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
2764 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
2765 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
2766
2767 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
2768 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
2769 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
2770 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
2771
2772 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
2773 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
2774 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
2775 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
2776
2777 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
2778 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
2779 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
2780 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
2781
2782 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
2783 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
2784 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
2785 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
2786
2787 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
2788 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
2789 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
2790 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
2791 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
2792 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
2793 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
2794 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
2795
2796 { "AIF1TX", NULL, "I2S1" },
2797 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
2798
2799 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2800 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2801 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2802
2803 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2804 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2805
2806 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2807 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2808 { "IF2 ADC3 Mux", "OB45", "OB45" },
2809
2810 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2811 { "IF2 ADC4 Mux", "OB67", "OB67" },
2812 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2813
2814 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
2815 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
2816 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
2817 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
2818
2819 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
2820 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
2821 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
2822 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
2823
2824 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
2825 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
2826 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
2827 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
2828
2829 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
2830 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
2831 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
2832 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
2833
2834 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
2835 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
2836 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
2837 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
2838
2839 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
2840 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
2841 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
2842 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
2843 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
2844 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
2845 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
2846 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
2847
2848 { "AIF2TX", NULL, "I2S2" },
2849 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
2850
2851 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2852 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2853 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2854 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2855 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2856 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2857 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2858 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2859
2860 { "AIF3TX", NULL, "I2S3" },
2861 { "AIF3TX", NULL, "IF3 ADC Mux" },
2862
2863 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2864 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2865 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2866 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2867 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2868 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2869 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2870 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2871
2872 { "AIF4TX", NULL, "I2S4" },
2873 { "AIF4TX", NULL, "IF4 ADC Mux" },
2874
2875 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2876 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2877 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2878
2879 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2880 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2881
2882 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2883 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2884 { "SLB ADC3 Mux", "OB45", "OB45" },
2885
2886 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2887 { "SLB ADC4 Mux", "OB67", "OB67" },
2888 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2889
2890 { "SLBTX", NULL, "SLB" },
2891 { "SLBTX", NULL, "SLB ADC1 Mux" },
2892 { "SLBTX", NULL, "SLB ADC2 Mux" },
2893 { "SLBTX", NULL, "SLB ADC3 Mux" },
2894 { "SLBTX", NULL, "SLB ADC4 Mux" },
2895
2896 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2897 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2898 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2899 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2900 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2901
2902 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2903 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2904
2905 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2906 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2907 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2908 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2909 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2910 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2911
2912 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2913 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2914
2915 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2916 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2917 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2918 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2919 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2920
2921 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2922 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2923
2924 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2925 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2926 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2927 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2928 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2929 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2930 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2931 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2932
2933 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2934 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2935 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2936 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2937 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2938 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2939 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2940 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2941
2942 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2943 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2944 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2945 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2946 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2947 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2948
2949 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2950 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2951 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2952 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2953 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2954 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2955 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2956
2957 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2958 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2959 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2960 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2961 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2962 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2963 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2964
2965 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2966 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2967 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2968 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2969 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2970 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2971 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2972
2973 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2974 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2975 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2976 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2977 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2978 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2979 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2980
2981 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2982 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2983 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2984 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2985 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2986 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2987 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2988
2989 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2990 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2991 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2992 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2993 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2994 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2995 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2996
2997 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2998 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2999 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3000 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3001 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3002 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3003 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3004
3005 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3006 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3007 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3008 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3009
3010 { "OutBound2", NULL, "OB23 Bypass Mux" },
3011 { "OutBound3", NULL, "OB23 Bypass Mux" },
3012 { "OutBound4", NULL, "OB4 MIX" },
3013 { "OutBound5", NULL, "OB5 MIX" },
3014 { "OutBound6", NULL, "OB6 MIX" },
3015 { "OutBound7", NULL, "OB7 MIX" },
3016
3017 { "OB45", NULL, "OutBound4" },
3018 { "OB45", NULL, "OutBound5" },
3019 { "OB67", NULL, "OutBound6" },
3020 { "OB67", NULL, "OutBound7" },
3021
3022 { "IF1 DAC0", NULL, "AIF1RX" },
3023 { "IF1 DAC1", NULL, "AIF1RX" },
3024 { "IF1 DAC2", NULL, "AIF1RX" },
3025 { "IF1 DAC3", NULL, "AIF1RX" },
3026 { "IF1 DAC4", NULL, "AIF1RX" },
3027 { "IF1 DAC5", NULL, "AIF1RX" },
3028 { "IF1 DAC6", NULL, "AIF1RX" },
3029 { "IF1 DAC7", NULL, "AIF1RX" },
3030 { "IF1 DAC0", NULL, "I2S1" },
3031 { "IF1 DAC1", NULL, "I2S1" },
3032 { "IF1 DAC2", NULL, "I2S1" },
3033 { "IF1 DAC3", NULL, "I2S1" },
3034 { "IF1 DAC4", NULL, "I2S1" },
3035 { "IF1 DAC5", NULL, "I2S1" },
3036 { "IF1 DAC6", NULL, "I2S1" },
3037 { "IF1 DAC7", NULL, "I2S1" },
3038
3039 { "IF1 DAC01", NULL, "IF1 DAC0" },
3040 { "IF1 DAC01", NULL, "IF1 DAC1" },
3041 { "IF1 DAC23", NULL, "IF1 DAC2" },
3042 { "IF1 DAC23", NULL, "IF1 DAC3" },
3043 { "IF1 DAC45", NULL, "IF1 DAC4" },
3044 { "IF1 DAC45", NULL, "IF1 DAC5" },
3045 { "IF1 DAC67", NULL, "IF1 DAC6" },
3046 { "IF1 DAC67", NULL, "IF1 DAC7" },
3047
3048 { "IF2 DAC0", NULL, "AIF2RX" },
3049 { "IF2 DAC1", NULL, "AIF2RX" },
3050 { "IF2 DAC2", NULL, "AIF2RX" },
3051 { "IF2 DAC3", NULL, "AIF2RX" },
3052 { "IF2 DAC4", NULL, "AIF2RX" },
3053 { "IF2 DAC5", NULL, "AIF2RX" },
3054 { "IF2 DAC6", NULL, "AIF2RX" },
3055 { "IF2 DAC7", NULL, "AIF2RX" },
3056 { "IF2 DAC0", NULL, "I2S2" },
3057 { "IF2 DAC1", NULL, "I2S2" },
3058 { "IF2 DAC2", NULL, "I2S2" },
3059 { "IF2 DAC3", NULL, "I2S2" },
3060 { "IF2 DAC4", NULL, "I2S2" },
3061 { "IF2 DAC5", NULL, "I2S2" },
3062 { "IF2 DAC6", NULL, "I2S2" },
3063 { "IF2 DAC7", NULL, "I2S2" },
3064
3065 { "IF2 DAC01", NULL, "IF2 DAC0" },
3066 { "IF2 DAC01", NULL, "IF2 DAC1" },
3067 { "IF2 DAC23", NULL, "IF2 DAC2" },
3068 { "IF2 DAC23", NULL, "IF2 DAC3" },
3069 { "IF2 DAC45", NULL, "IF2 DAC4" },
3070 { "IF2 DAC45", NULL, "IF2 DAC5" },
3071 { "IF2 DAC67", NULL, "IF2 DAC6" },
3072 { "IF2 DAC67", NULL, "IF2 DAC7" },
3073
3074 { "IF3 DAC", NULL, "AIF3RX" },
3075 { "IF3 DAC", NULL, "I2S3" },
3076
3077 { "IF4 DAC", NULL, "AIF4RX" },
3078 { "IF4 DAC", NULL, "I2S4" },
3079
3080 { "IF3 DAC L", NULL, "IF3 DAC" },
3081 { "IF3 DAC R", NULL, "IF3 DAC" },
3082
3083 { "IF4 DAC L", NULL, "IF4 DAC" },
3084 { "IF4 DAC R", NULL, "IF4 DAC" },
3085
3086 { "SLB DAC0", NULL, "SLBRX" },
3087 { "SLB DAC1", NULL, "SLBRX" },
3088 { "SLB DAC2", NULL, "SLBRX" },
3089 { "SLB DAC3", NULL, "SLBRX" },
3090 { "SLB DAC4", NULL, "SLBRX" },
3091 { "SLB DAC5", NULL, "SLBRX" },
3092 { "SLB DAC6", NULL, "SLBRX" },
3093 { "SLB DAC7", NULL, "SLBRX" },
3094 { "SLB DAC0", NULL, "SLB" },
3095 { "SLB DAC1", NULL, "SLB" },
3096 { "SLB DAC2", NULL, "SLB" },
3097 { "SLB DAC3", NULL, "SLB" },
3098 { "SLB DAC4", NULL, "SLB" },
3099 { "SLB DAC5", NULL, "SLB" },
3100 { "SLB DAC6", NULL, "SLB" },
3101 { "SLB DAC7", NULL, "SLB" },
3102
3103 { "SLB DAC01", NULL, "SLB DAC0" },
3104 { "SLB DAC01", NULL, "SLB DAC1" },
3105 { "SLB DAC23", NULL, "SLB DAC2" },
3106 { "SLB DAC23", NULL, "SLB DAC3" },
3107 { "SLB DAC45", NULL, "SLB DAC4" },
3108 { "SLB DAC45", NULL, "SLB DAC5" },
3109 { "SLB DAC67", NULL, "SLB DAC6" },
3110 { "SLB DAC67", NULL, "SLB DAC7" },
3111
3112 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3113 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3114 { "ADDA1 Mux", "OB 67", "OB67" },
3115
3116 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3117 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3118 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3119 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3120 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3121 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3122
3123 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3124 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3125 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
3126 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3127 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3128 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
3129
3130 { "DAC1 FS", NULL, "DAC1 MIXL" },
3131 { "DAC1 FS", NULL, "DAC1 MIXR" },
3132
3133 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3134 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3135 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3136 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3137 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3138 { "DAC2 L Mux", "OB 2", "OutBound2" },
3139
3140 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3141 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3142 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3143 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3144 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3145 { "DAC2 R Mux", "OB 3", "OutBound3" },
3146 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3147 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3148
3149 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3150 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3151 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3152 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3153 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3154 { "DAC3 L Mux", "OB 4", "OutBound4" },
3155
3156 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3157 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3158 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3159 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3160 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3161 { "DAC3 R Mux", "OB 5", "OutBound5" },
3162
3163 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3164 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3165 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3166 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3167 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3168 { "DAC4 L Mux", "OB 6", "OutBound6" },
3169
3170 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3171 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3172 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3173 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3174 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3175 { "DAC4 R Mux", "OB 7", "OutBound7" },
3176
3177 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3178 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3179 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3180 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3181 { "Sidetone Mux", "ADC1", "ADC 1" },
3182 { "Sidetone Mux", "ADC2", "ADC 2" },
3183 { "Sidetone Mux", NULL, "Sidetone Power" },
3184
3185 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3186 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3187 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3188 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3189 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3190 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3191 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3192 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3193 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3194 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3195
3196 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3197 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3198 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3199 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3200 { "Mono DAC MIXL", NULL, "dac mono left filter" },
3201 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3202 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3203 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3204 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3205 { "Mono DAC MIXR", NULL, "dac mono right filter" },
3206
3207 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3208 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3209 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3210 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3211 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3212 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3213 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3214 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3215
3216 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3217 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3218 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3219 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3220 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3221 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3222 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3223 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3224
3225 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3226 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3227 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3228 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3229 { "DD1 MIX", NULL, "DD1 MIXL" },
3230 { "DD1 MIX", NULL, "DD1 MIXR" },
3231 { "DD2 MIX", NULL, "DD2 MIXL" },
3232 { "DD2 MIX", NULL, "DD2 MIXR" },
3233
3234 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3235 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3236 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3237 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3238
3239 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3240 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3241 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3242 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3243
3244 { "DAC 1", NULL, "DAC12 SRC Mux" },
3245 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
3246 { "DAC 2", NULL, "DAC12 SRC Mux" },
3247 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
3248 { "DAC 3", NULL, "DAC3 SRC Mux" },
3249 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
3250
3251 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3252 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3253 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3254 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3255 { "PDM1 L Mux", NULL, "PDM1 Power" },
3256 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3257 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3258 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3259 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3260 { "PDM1 R Mux", NULL, "PDM1 Power" },
3261 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3262 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3263 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3264 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3265 { "PDM2 L Mux", NULL, "PDM2 Power" },
3266 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3267 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3268 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3269 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3270 { "PDM2 R Mux", NULL, "PDM2 Power" },
3271
3272 { "LOUT1 amp", NULL, "DAC 1" },
3273 { "LOUT2 amp", NULL, "DAC 2" },
3274 { "LOUT3 amp", NULL, "DAC 3" },
3275
3276 { "LOUT1", NULL, "LOUT1 amp" },
3277 { "LOUT2", NULL, "LOUT2 amp" },
3278 { "LOUT3", NULL, "LOUT3 amp" },
3279
3280 { "PDM1L", NULL, "PDM1 L Mux" },
3281 { "PDM1R", NULL, "PDM1 R Mux" },
3282 { "PDM2L", NULL, "PDM2 L Mux" },
3283 { "PDM2R", NULL, "PDM2 R Mux" },
3284 };
3285
3286 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3287 { "DMIC L2", NULL, "DMIC1 power" },
3288 { "DMIC R2", NULL, "DMIC1 power" },
3289 };
3290
3291 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3292 { "DMIC L2", NULL, "DMIC2 power" },
3293 { "DMIC R2", NULL, "DMIC2 power" },
3294 };
3295
3296 static int rt5677_hw_params(struct snd_pcm_substream *substream,
3297 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3298 {
3299 struct snd_soc_codec *codec = dai->codec;
3300 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3301 unsigned int val_len = 0, val_clk, mask_clk;
3302 int pre_div, bclk_ms, frame_size;
3303
3304 rt5677->lrck[dai->id] = params_rate(params);
3305 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
3306 if (pre_div < 0) {
3307 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3308 rt5677->sysclk, rt5677->lrck[dai->id]);
3309 return -EINVAL;
3310 }
3311 frame_size = snd_soc_params_to_frame_size(params);
3312 if (frame_size < 0) {
3313 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3314 return -EINVAL;
3315 }
3316 bclk_ms = frame_size > 32;
3317 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3318
3319 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3320 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3321 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3322 bclk_ms, pre_div, dai->id);
3323
3324 switch (params_width(params)) {
3325 case 16:
3326 break;
3327 case 20:
3328 val_len |= RT5677_I2S_DL_20;
3329 break;
3330 case 24:
3331 val_len |= RT5677_I2S_DL_24;
3332 break;
3333 case 8:
3334 val_len |= RT5677_I2S_DL_8;
3335 break;
3336 default:
3337 return -EINVAL;
3338 }
3339
3340 switch (dai->id) {
3341 case RT5677_AIF1:
3342 mask_clk = RT5677_I2S_PD1_MASK;
3343 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3344 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3345 RT5677_I2S_DL_MASK, val_len);
3346 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3347 mask_clk, val_clk);
3348 break;
3349 case RT5677_AIF2:
3350 mask_clk = RT5677_I2S_PD2_MASK;
3351 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3352 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3353 RT5677_I2S_DL_MASK, val_len);
3354 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3355 mask_clk, val_clk);
3356 break;
3357 case RT5677_AIF3:
3358 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3359 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3360 pre_div << RT5677_I2S_PD3_SFT;
3361 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3362 RT5677_I2S_DL_MASK, val_len);
3363 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3364 mask_clk, val_clk);
3365 break;
3366 case RT5677_AIF4:
3367 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3368 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3369 pre_div << RT5677_I2S_PD4_SFT;
3370 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3371 RT5677_I2S_DL_MASK, val_len);
3372 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3373 mask_clk, val_clk);
3374 break;
3375 default:
3376 break;
3377 }
3378
3379 return 0;
3380 }
3381
3382 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3383 {
3384 struct snd_soc_codec *codec = dai->codec;
3385 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3386 unsigned int reg_val = 0;
3387
3388 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3389 case SND_SOC_DAIFMT_CBM_CFM:
3390 rt5677->master[dai->id] = 1;
3391 break;
3392 case SND_SOC_DAIFMT_CBS_CFS:
3393 reg_val |= RT5677_I2S_MS_S;
3394 rt5677->master[dai->id] = 0;
3395 break;
3396 default:
3397 return -EINVAL;
3398 }
3399
3400 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3401 case SND_SOC_DAIFMT_NB_NF:
3402 break;
3403 case SND_SOC_DAIFMT_IB_NF:
3404 reg_val |= RT5677_I2S_BP_INV;
3405 break;
3406 default:
3407 return -EINVAL;
3408 }
3409
3410 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3411 case SND_SOC_DAIFMT_I2S:
3412 break;
3413 case SND_SOC_DAIFMT_LEFT_J:
3414 reg_val |= RT5677_I2S_DF_LEFT;
3415 break;
3416 case SND_SOC_DAIFMT_DSP_A:
3417 reg_val |= RT5677_I2S_DF_PCM_A;
3418 break;
3419 case SND_SOC_DAIFMT_DSP_B:
3420 reg_val |= RT5677_I2S_DF_PCM_B;
3421 break;
3422 default:
3423 return -EINVAL;
3424 }
3425
3426 switch (dai->id) {
3427 case RT5677_AIF1:
3428 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3429 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3430 RT5677_I2S_DF_MASK, reg_val);
3431 break;
3432 case RT5677_AIF2:
3433 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3434 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3435 RT5677_I2S_DF_MASK, reg_val);
3436 break;
3437 case RT5677_AIF3:
3438 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3439 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3440 RT5677_I2S_DF_MASK, reg_val);
3441 break;
3442 case RT5677_AIF4:
3443 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3444 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3445 RT5677_I2S_DF_MASK, reg_val);
3446 break;
3447 default:
3448 break;
3449 }
3450
3451
3452 return 0;
3453 }
3454
3455 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3456 int clk_id, unsigned int freq, int dir)
3457 {
3458 struct snd_soc_codec *codec = dai->codec;
3459 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3460 unsigned int reg_val = 0;
3461
3462 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3463 return 0;
3464
3465 switch (clk_id) {
3466 case RT5677_SCLK_S_MCLK:
3467 reg_val |= RT5677_SCLK_SRC_MCLK;
3468 break;
3469 case RT5677_SCLK_S_PLL1:
3470 reg_val |= RT5677_SCLK_SRC_PLL1;
3471 break;
3472 case RT5677_SCLK_S_RCCLK:
3473 reg_val |= RT5677_SCLK_SRC_RCCLK;
3474 break;
3475 default:
3476 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3477 return -EINVAL;
3478 }
3479 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3480 RT5677_SCLK_SRC_MASK, reg_val);
3481 rt5677->sysclk = freq;
3482 rt5677->sysclk_src = clk_id;
3483
3484 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3485
3486 return 0;
3487 }
3488
3489 /**
3490 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3491 * @freq_in: external clock provided to codec.
3492 * @freq_out: target clock which codec works on.
3493 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3494 *
3495 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3496 *
3497 * Returns 0 for success or negative error code.
3498 */
3499 static int rt5677_pll_calc(const unsigned int freq_in,
3500 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
3501 {
3502 if (RT5677_PLL_INP_MIN > freq_in)
3503 return -EINVAL;
3504
3505 return rl6231_pll_calc(freq_in, freq_out, pll_code);
3506 }
3507
3508 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3509 unsigned int freq_in, unsigned int freq_out)
3510 {
3511 struct snd_soc_codec *codec = dai->codec;
3512 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3513 struct rl6231_pll_code pll_code;
3514 int ret;
3515
3516 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3517 freq_out == rt5677->pll_out)
3518 return 0;
3519
3520 if (!freq_in || !freq_out) {
3521 dev_dbg(codec->dev, "PLL disabled\n");
3522
3523 rt5677->pll_in = 0;
3524 rt5677->pll_out = 0;
3525 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3526 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3527 return 0;
3528 }
3529
3530 switch (source) {
3531 case RT5677_PLL1_S_MCLK:
3532 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3533 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3534 break;
3535 case RT5677_PLL1_S_BCLK1:
3536 case RT5677_PLL1_S_BCLK2:
3537 case RT5677_PLL1_S_BCLK3:
3538 case RT5677_PLL1_S_BCLK4:
3539 switch (dai->id) {
3540 case RT5677_AIF1:
3541 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3542 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3543 break;
3544 case RT5677_AIF2:
3545 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3546 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3547 break;
3548 case RT5677_AIF3:
3549 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3550 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3551 break;
3552 case RT5677_AIF4:
3553 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3554 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3555 break;
3556 default:
3557 break;
3558 }
3559 break;
3560 default:
3561 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3562 return -EINVAL;
3563 }
3564
3565 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3566 if (ret < 0) {
3567 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3568 return ret;
3569 }
3570
3571 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3572 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3573 pll_code.n_code, pll_code.k_code);
3574
3575 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
3576 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
3577 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3578 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3579 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3580
3581 rt5677->pll_in = freq_in;
3582 rt5677->pll_out = freq_out;
3583 rt5677->pll_src = source;
3584
3585 return 0;
3586 }
3587
3588 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3589 unsigned int rx_mask, int slots, int slot_width)
3590 {
3591 struct snd_soc_codec *codec = dai->codec;
3592 unsigned int val = 0;
3593
3594 if (rx_mask || tx_mask)
3595 val |= (1 << 12);
3596
3597 switch (slots) {
3598 case 4:
3599 val |= (1 << 10);
3600 break;
3601 case 6:
3602 val |= (2 << 10);
3603 break;
3604 case 8:
3605 val |= (3 << 10);
3606 break;
3607 case 2:
3608 default:
3609 break;
3610 }
3611
3612 switch (slot_width) {
3613 case 20:
3614 val |= (1 << 8);
3615 break;
3616 case 24:
3617 val |= (2 << 8);
3618 break;
3619 case 32:
3620 val |= (3 << 8);
3621 break;
3622 case 16:
3623 default:
3624 break;
3625 }
3626
3627 switch (dai->id) {
3628 case RT5677_AIF1:
3629 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
3630 break;
3631 case RT5677_AIF2:
3632 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
3633 break;
3634 default:
3635 break;
3636 }
3637
3638 return 0;
3639 }
3640
3641 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3642 enum snd_soc_bias_level level)
3643 {
3644 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3645
3646 switch (level) {
3647 case SND_SOC_BIAS_ON:
3648 break;
3649
3650 case SND_SOC_BIAS_PREPARE:
3651 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3652 rt5677_set_dsp_vad(codec, false);
3653
3654 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3655 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3656 0x0055);
3657 regmap_update_bits(rt5677->regmap,
3658 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3659 0x0f00, 0x0f00);
3660 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3661 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3662 RT5677_PWR_BG | RT5677_PWR_VREF2,
3663 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3664 RT5677_PWR_BG | RT5677_PWR_VREF2);
3665 mdelay(20);
3666 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3667 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3668 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3669 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3670 RT5677_PWR_CORE, RT5677_PWR_CORE);
3671 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3672 0x1, 0x1);
3673 }
3674 break;
3675
3676 case SND_SOC_BIAS_STANDBY:
3677 break;
3678
3679 case SND_SOC_BIAS_OFF:
3680 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3681 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3682 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
3683 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
3684 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3685 regmap_update_bits(rt5677->regmap,
3686 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3687
3688 if (rt5677->dsp_vad_en)
3689 rt5677_set_dsp_vad(codec, true);
3690 break;
3691
3692 default:
3693 break;
3694 }
3695 codec->dapm.bias_level = level;
3696
3697 return 0;
3698 }
3699
3700 #ifdef CONFIG_GPIOLIB
3701 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
3702 {
3703 return container_of(chip, struct rt5677_priv, gpio_chip);
3704 }
3705
3706 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3707 {
3708 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3709
3710 switch (offset) {
3711 case RT5677_GPIO1 ... RT5677_GPIO5:
3712 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3713 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
3714 break;
3715
3716 case RT5677_GPIO6:
3717 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3718 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
3719 break;
3720
3721 default:
3722 break;
3723 }
3724 }
3725
3726 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
3727 unsigned offset, int value)
3728 {
3729 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3730
3731 switch (offset) {
3732 case RT5677_GPIO1 ... RT5677_GPIO5:
3733 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3734 0x3 << (offset * 3 + 1),
3735 (0x2 | !!value) << (offset * 3 + 1));
3736 break;
3737
3738 case RT5677_GPIO6:
3739 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3740 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
3741 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
3742 break;
3743
3744 default:
3745 break;
3746 }
3747
3748 return 0;
3749 }
3750
3751 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
3752 {
3753 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3754 int value, ret;
3755
3756 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
3757 if (ret < 0)
3758 return ret;
3759
3760 return (value & (0x1 << offset)) >> offset;
3761 }
3762
3763 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3764 {
3765 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3766
3767 switch (offset) {
3768 case RT5677_GPIO1 ... RT5677_GPIO5:
3769 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3770 0x1 << (offset * 3 + 2), 0x0);
3771 break;
3772
3773 case RT5677_GPIO6:
3774 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3775 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
3776 break;
3777
3778 default:
3779 break;
3780 }
3781
3782 return 0;
3783 }
3784
3785 /** Configures the gpio as
3786 * 0 - floating
3787 * 1 - pull down
3788 * 2 - pull up
3789 */
3790 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
3791 int value)
3792 {
3793 int shift;
3794
3795 switch (offset) {
3796 case RT5677_GPIO1 ... RT5677_GPIO2:
3797 shift = 2 * (1 - offset);
3798 regmap_update_bits(rt5677->regmap,
3799 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
3800 0x3 << shift,
3801 (value & 0x3) << shift);
3802 break;
3803
3804 case RT5677_GPIO3 ... RT5677_GPIO6:
3805 shift = 2 * (9 - offset);
3806 regmap_update_bits(rt5677->regmap,
3807 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
3808 0x3 << shift,
3809 (value & 0x3) << shift);
3810 break;
3811
3812 default:
3813 break;
3814 }
3815 }
3816
3817 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
3818 {
3819 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3820 struct regmap_irq_chip_data *data = rt5677->irq_data;
3821 int irq;
3822
3823 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
3824 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
3825 (rt5677->pdata.jd1_gpio == 2 &&
3826 offset == RT5677_GPIO2) ||
3827 (rt5677->pdata.jd1_gpio == 3 &&
3828 offset == RT5677_GPIO3)) {
3829 irq = RT5677_IRQ_JD1;
3830 } else {
3831 return -ENXIO;
3832 }
3833 }
3834
3835 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
3836 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
3837 (rt5677->pdata.jd2_gpio == 2 &&
3838 offset == RT5677_GPIO5) ||
3839 (rt5677->pdata.jd2_gpio == 3 &&
3840 offset == RT5677_GPIO6)) {
3841 irq = RT5677_IRQ_JD2;
3842 } else if ((rt5677->pdata.jd3_gpio == 1 &&
3843 offset == RT5677_GPIO4) ||
3844 (rt5677->pdata.jd3_gpio == 2 &&
3845 offset == RT5677_GPIO5) ||
3846 (rt5677->pdata.jd3_gpio == 3 &&
3847 offset == RT5677_GPIO6)) {
3848 irq = RT5677_IRQ_JD3;
3849 } else {
3850 return -ENXIO;
3851 }
3852 }
3853
3854 return regmap_irq_get_virq(data, irq);
3855 }
3856
3857 static struct gpio_chip rt5677_template_chip = {
3858 .label = "rt5677",
3859 .owner = THIS_MODULE,
3860 .direction_output = rt5677_gpio_direction_out,
3861 .set = rt5677_gpio_set,
3862 .direction_input = rt5677_gpio_direction_in,
3863 .get = rt5677_gpio_get,
3864 .to_irq = rt5677_to_irq,
3865 .can_sleep = 1,
3866 };
3867
3868 static void rt5677_init_gpio(struct i2c_client *i2c)
3869 {
3870 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3871 int ret;
3872
3873 rt5677->gpio_chip = rt5677_template_chip;
3874 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
3875 rt5677->gpio_chip.dev = &i2c->dev;
3876 rt5677->gpio_chip.base = -1;
3877
3878 ret = gpiochip_add(&rt5677->gpio_chip);
3879 if (ret != 0)
3880 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
3881 }
3882
3883 static void rt5677_free_gpio(struct i2c_client *i2c)
3884 {
3885 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3886
3887 gpiochip_remove(&rt5677->gpio_chip);
3888 }
3889 #else
3890 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
3891 int value)
3892 {
3893 }
3894
3895 static void rt5677_init_gpio(struct i2c_client *i2c)
3896 {
3897 }
3898
3899 static void rt5677_free_gpio(struct i2c_client *i2c)
3900 {
3901 }
3902 #endif
3903
3904 static int rt5677_probe(struct snd_soc_codec *codec)
3905 {
3906 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3907 int i;
3908
3909 rt5677->codec = codec;
3910
3911 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3912 snd_soc_dapm_add_routes(&codec->dapm,
3913 rt5677_dmic2_clk_2,
3914 ARRAY_SIZE(rt5677_dmic2_clk_2));
3915 } else { /*use dmic1 clock by default*/
3916 snd_soc_dapm_add_routes(&codec->dapm,
3917 rt5677_dmic2_clk_1,
3918 ARRAY_SIZE(rt5677_dmic2_clk_1));
3919 }
3920
3921 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3922
3923 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3924 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3925
3926 for (i = 0; i < RT5677_GPIO_NUM; i++)
3927 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
3928
3929 if (rt5677->irq_data) {
3930 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
3931 0x8000);
3932 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
3933 0x0008);
3934
3935 if (rt5677->pdata.jd1_gpio)
3936 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
3937 RT5677_SEL_GPIO_JD1_MASK,
3938 rt5677->pdata.jd1_gpio <<
3939 RT5677_SEL_GPIO_JD1_SFT);
3940
3941 if (rt5677->pdata.jd2_gpio)
3942 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
3943 RT5677_SEL_GPIO_JD2_MASK,
3944 rt5677->pdata.jd2_gpio <<
3945 RT5677_SEL_GPIO_JD2_SFT);
3946
3947 if (rt5677->pdata.jd3_gpio)
3948 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
3949 RT5677_SEL_GPIO_JD3_MASK,
3950 rt5677->pdata.jd3_gpio <<
3951 RT5677_SEL_GPIO_JD3_SFT);
3952 }
3953
3954 mutex_init(&rt5677->dsp_cmd_lock);
3955
3956 return 0;
3957 }
3958
3959 static int rt5677_remove(struct snd_soc_codec *codec)
3960 {
3961 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3962
3963 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3964 if (gpio_is_valid(rt5677->pow_ldo2))
3965 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
3966
3967 return 0;
3968 }
3969
3970 #ifdef CONFIG_PM
3971 static int rt5677_suspend(struct snd_soc_codec *codec)
3972 {
3973 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3974
3975 if (!rt5677->dsp_vad_en) {
3976 regcache_cache_only(rt5677->regmap, true);
3977 regcache_mark_dirty(rt5677->regmap);
3978 }
3979
3980 if (gpio_is_valid(rt5677->pow_ldo2))
3981 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
3982
3983 return 0;
3984 }
3985
3986 static int rt5677_resume(struct snd_soc_codec *codec)
3987 {
3988 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3989
3990 if (gpio_is_valid(rt5677->pow_ldo2)) {
3991 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
3992 msleep(10);
3993 }
3994
3995 if (!rt5677->dsp_vad_en) {
3996 regcache_cache_only(rt5677->regmap, false);
3997 regcache_sync(rt5677->regmap);
3998 }
3999
4000 return 0;
4001 }
4002 #else
4003 #define rt5677_suspend NULL
4004 #define rt5677_resume NULL
4005 #endif
4006
4007 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4008 {
4009 struct i2c_client *client = context;
4010 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4011
4012 if (rt5677->is_dsp_mode)
4013 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4014 else
4015 regmap_read(rt5677->regmap_physical, reg, val);
4016
4017 return 0;
4018 }
4019
4020 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4021 {
4022 struct i2c_client *client = context;
4023 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4024
4025 if (rt5677->is_dsp_mode)
4026 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4027 else
4028 regmap_write(rt5677->regmap_physical, reg, val);
4029
4030 return 0;
4031 }
4032
4033 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4034 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4035 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4036
4037 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4038 .hw_params = rt5677_hw_params,
4039 .set_fmt = rt5677_set_dai_fmt,
4040 .set_sysclk = rt5677_set_dai_sysclk,
4041 .set_pll = rt5677_set_dai_pll,
4042 .set_tdm_slot = rt5677_set_tdm_slot,
4043 };
4044
4045 static struct snd_soc_dai_driver rt5677_dai[] = {
4046 {
4047 .name = "rt5677-aif1",
4048 .id = RT5677_AIF1,
4049 .playback = {
4050 .stream_name = "AIF1 Playback",
4051 .channels_min = 1,
4052 .channels_max = 2,
4053 .rates = RT5677_STEREO_RATES,
4054 .formats = RT5677_FORMATS,
4055 },
4056 .capture = {
4057 .stream_name = "AIF1 Capture",
4058 .channels_min = 1,
4059 .channels_max = 2,
4060 .rates = RT5677_STEREO_RATES,
4061 .formats = RT5677_FORMATS,
4062 },
4063 .ops = &rt5677_aif_dai_ops,
4064 },
4065 {
4066 .name = "rt5677-aif2",
4067 .id = RT5677_AIF2,
4068 .playback = {
4069 .stream_name = "AIF2 Playback",
4070 .channels_min = 1,
4071 .channels_max = 2,
4072 .rates = RT5677_STEREO_RATES,
4073 .formats = RT5677_FORMATS,
4074 },
4075 .capture = {
4076 .stream_name = "AIF2 Capture",
4077 .channels_min = 1,
4078 .channels_max = 2,
4079 .rates = RT5677_STEREO_RATES,
4080 .formats = RT5677_FORMATS,
4081 },
4082 .ops = &rt5677_aif_dai_ops,
4083 },
4084 {
4085 .name = "rt5677-aif3",
4086 .id = RT5677_AIF3,
4087 .playback = {
4088 .stream_name = "AIF3 Playback",
4089 .channels_min = 1,
4090 .channels_max = 2,
4091 .rates = RT5677_STEREO_RATES,
4092 .formats = RT5677_FORMATS,
4093 },
4094 .capture = {
4095 .stream_name = "AIF3 Capture",
4096 .channels_min = 1,
4097 .channels_max = 2,
4098 .rates = RT5677_STEREO_RATES,
4099 .formats = RT5677_FORMATS,
4100 },
4101 .ops = &rt5677_aif_dai_ops,
4102 },
4103 {
4104 .name = "rt5677-aif4",
4105 .id = RT5677_AIF4,
4106 .playback = {
4107 .stream_name = "AIF4 Playback",
4108 .channels_min = 1,
4109 .channels_max = 2,
4110 .rates = RT5677_STEREO_RATES,
4111 .formats = RT5677_FORMATS,
4112 },
4113 .capture = {
4114 .stream_name = "AIF4 Capture",
4115 .channels_min = 1,
4116 .channels_max = 2,
4117 .rates = RT5677_STEREO_RATES,
4118 .formats = RT5677_FORMATS,
4119 },
4120 .ops = &rt5677_aif_dai_ops,
4121 },
4122 {
4123 .name = "rt5677-slimbus",
4124 .id = RT5677_AIF5,
4125 .playback = {
4126 .stream_name = "SLIMBus Playback",
4127 .channels_min = 1,
4128 .channels_max = 2,
4129 .rates = RT5677_STEREO_RATES,
4130 .formats = RT5677_FORMATS,
4131 },
4132 .capture = {
4133 .stream_name = "SLIMBus Capture",
4134 .channels_min = 1,
4135 .channels_max = 2,
4136 .rates = RT5677_STEREO_RATES,
4137 .formats = RT5677_FORMATS,
4138 },
4139 .ops = &rt5677_aif_dai_ops,
4140 },
4141 };
4142
4143 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4144 .probe = rt5677_probe,
4145 .remove = rt5677_remove,
4146 .suspend = rt5677_suspend,
4147 .resume = rt5677_resume,
4148 .set_bias_level = rt5677_set_bias_level,
4149 .idle_bias_off = true,
4150 .controls = rt5677_snd_controls,
4151 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4152 .dapm_widgets = rt5677_dapm_widgets,
4153 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4154 .dapm_routes = rt5677_dapm_routes,
4155 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4156 };
4157
4158 static const struct regmap_config rt5677_regmap_physical = {
4159 .name = "physical",
4160 .reg_bits = 8,
4161 .val_bits = 16,
4162
4163 .max_register = RT5677_VENDOR_ID2 + 1,
4164 .readable_reg = rt5677_readable_register,
4165
4166 .cache_type = REGCACHE_NONE,
4167 };
4168
4169 static const struct regmap_config rt5677_regmap = {
4170 .reg_bits = 8,
4171 .val_bits = 16,
4172
4173 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4174 RT5677_PR_SPACING),
4175
4176 .volatile_reg = rt5677_volatile_register,
4177 .readable_reg = rt5677_readable_register,
4178 .reg_read = rt5677_read,
4179 .reg_write = rt5677_write,
4180
4181 .cache_type = REGCACHE_RBTREE,
4182 .reg_defaults = rt5677_reg,
4183 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4184 .ranges = rt5677_ranges,
4185 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4186 };
4187
4188 static const struct i2c_device_id rt5677_i2c_id[] = {
4189 { "rt5677", 0 },
4190 { }
4191 };
4192 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4193
4194 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4195 {
4196 rt5677->pdata.in1_diff = of_property_read_bool(np,
4197 "realtek,in1-differential");
4198 rt5677->pdata.in2_diff = of_property_read_bool(np,
4199 "realtek,in2-differential");
4200 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4201 "realtek,lout1-differential");
4202 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4203 "realtek,lout2-differential");
4204 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4205 "realtek,lout3-differential");
4206
4207 rt5677->pow_ldo2 = of_get_named_gpio(np,
4208 "realtek,pow-ldo2-gpio", 0);
4209
4210 /*
4211 * POW_LDO2 is optional (it may be statically tied on the board).
4212 * -ENOENT means that the property doesn't exist, i.e. there is no
4213 * GPIO, so is not an error. Any other error code means the property
4214 * exists, but could not be parsed.
4215 */
4216 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4217 (rt5677->pow_ldo2 != -ENOENT))
4218 return rt5677->pow_ldo2;
4219
4220 of_property_read_u8_array(np, "realtek,gpio-config",
4221 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4222
4223 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4224 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4225 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4226
4227 return 0;
4228 }
4229
4230 static struct regmap_irq rt5677_irqs[] = {
4231 [RT5677_IRQ_JD1] = {
4232 .reg_offset = 0,
4233 .mask = RT5677_EN_IRQ_GPIO_JD1,
4234 },
4235 [RT5677_IRQ_JD2] = {
4236 .reg_offset = 0,
4237 .mask = RT5677_EN_IRQ_GPIO_JD2,
4238 },
4239 [RT5677_IRQ_JD3] = {
4240 .reg_offset = 0,
4241 .mask = RT5677_EN_IRQ_GPIO_JD3,
4242 },
4243 };
4244
4245 static struct regmap_irq_chip rt5677_irq_chip = {
4246 .name = "rt5677",
4247 .irqs = rt5677_irqs,
4248 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4249
4250 .num_regs = 1,
4251 .status_base = RT5677_IRQ_CTRL1,
4252 .mask_base = RT5677_IRQ_CTRL1,
4253 .mask_invert = 1,
4254 };
4255
4256 static int rt5677_irq_init(struct i2c_client *i2c)
4257 {
4258 int ret;
4259 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4260
4261 if (!rt5677->pdata.jd1_gpio &&
4262 !rt5677->pdata.jd2_gpio &&
4263 !rt5677->pdata.jd3_gpio)
4264 return 0;
4265
4266 if (!i2c->irq) {
4267 dev_err(&i2c->dev, "No interrupt specified\n");
4268 return -EINVAL;
4269 }
4270
4271 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4272 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4273 &rt5677_irq_chip, &rt5677->irq_data);
4274
4275 if (ret != 0) {
4276 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4277 return ret;
4278 }
4279
4280 return 0;
4281 }
4282
4283 static void rt5677_irq_exit(struct i2c_client *i2c)
4284 {
4285 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4286
4287 if (rt5677->irq_data)
4288 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4289 }
4290
4291 static int rt5677_i2c_probe(struct i2c_client *i2c,
4292 const struct i2c_device_id *id)
4293 {
4294 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4295 struct rt5677_priv *rt5677;
4296 int ret;
4297 unsigned int val;
4298
4299 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4300 GFP_KERNEL);
4301 if (rt5677 == NULL)
4302 return -ENOMEM;
4303
4304 i2c_set_clientdata(i2c, rt5677);
4305
4306 if (pdata)
4307 rt5677->pdata = *pdata;
4308
4309 if (i2c->dev.of_node) {
4310 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4311 if (ret) {
4312 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4313 ret);
4314 return ret;
4315 }
4316 } else {
4317 rt5677->pow_ldo2 = -EINVAL;
4318 }
4319
4320 if (gpio_is_valid(rt5677->pow_ldo2)) {
4321 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4322 GPIOF_OUT_INIT_HIGH,
4323 "RT5677 POW_LDO2");
4324 if (ret < 0) {
4325 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4326 rt5677->pow_ldo2, ret);
4327 return ret;
4328 }
4329 /* Wait a while until I2C bus becomes available. The datasheet
4330 * does not specify the exact we should wait but startup
4331 * sequence mentiones at least a few milliseconds.
4332 */
4333 msleep(10);
4334 }
4335
4336 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4337 &rt5677_regmap_physical);
4338 if (IS_ERR(rt5677->regmap_physical)) {
4339 ret = PTR_ERR(rt5677->regmap_physical);
4340 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4341 ret);
4342 return ret;
4343 }
4344
4345 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
4346 if (IS_ERR(rt5677->regmap)) {
4347 ret = PTR_ERR(rt5677->regmap);
4348 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4349 ret);
4350 return ret;
4351 }
4352
4353 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4354 if (val != RT5677_DEVICE_ID) {
4355 dev_err(&i2c->dev,
4356 "Device with ID register %x is not rt5677\n", val);
4357 return -ENODEV;
4358 }
4359
4360 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4361
4362 ret = regmap_register_patch(rt5677->regmap, init_list,
4363 ARRAY_SIZE(init_list));
4364 if (ret != 0)
4365 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4366
4367 if (rt5677->pdata.in1_diff)
4368 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4369 RT5677_IN_DF1, RT5677_IN_DF1);
4370
4371 if (rt5677->pdata.in2_diff)
4372 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4373 RT5677_IN_DF2, RT5677_IN_DF2);
4374
4375 if (rt5677->pdata.lout1_diff)
4376 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4377 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4378
4379 if (rt5677->pdata.lout2_diff)
4380 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4381 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4382
4383 if (rt5677->pdata.lout3_diff)
4384 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4385 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4386
4387 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4388 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4389 RT5677_GPIO5_FUNC_MASK,
4390 RT5677_GPIO5_FUNC_DMIC);
4391 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4392 RT5677_GPIO5_DIR_MASK,
4393 RT5677_GPIO5_DIR_OUT);
4394 }
4395
4396 rt5677_init_gpio(i2c);
4397 rt5677_irq_init(i2c);
4398
4399 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4400 rt5677_dai, ARRAY_SIZE(rt5677_dai));
4401 }
4402
4403 static int rt5677_i2c_remove(struct i2c_client *i2c)
4404 {
4405 rt5677_irq_exit(i2c);
4406
4407 snd_soc_unregister_codec(&i2c->dev);
4408 rt5677_free_gpio(i2c);
4409
4410 return 0;
4411 }
4412
4413 static struct i2c_driver rt5677_i2c_driver = {
4414 .driver = {
4415 .name = "rt5677",
4416 .owner = THIS_MODULE,
4417 },
4418 .probe = rt5677_i2c_probe,
4419 .remove = rt5677_i2c_remove,
4420 .id_table = rt5677_i2c_id,
4421 };
4422 module_i2c_driver(rt5677_i2c_driver);
4423
4424 MODULE_DESCRIPTION("ASoC RT5677 driver");
4425 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4426 MODULE_LICENSE("GPL v2");
ubuntu-bionic-kernel mirror