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ASoC: simple card: Add mclk-fs property in dai-link
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / rt5677.c
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "rl6231.h"
34 #include "rt5677.h"
35 #include "rt5677-spi.h"
36
37 #define RT5677_DEVICE_ID 0x6327
38
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
41
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44 static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55 };
56
57 static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
65 };
66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
67
68 static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
177 {RT5677_ASRC_12 , 0x0018},
178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
272 };
273
274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
275 {
276 int i;
277
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
281 return true;
282 }
283 }
284
285 switch (reg) {
286 case RT5677_RESET:
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320 }
321
322 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323 {
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541 }
542
543 /**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
554 {
555 struct snd_soc_codec *codec = rt5677->codec;
556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595 err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599 }
600
601 /**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
606 *
607 *
608 * Returns 0 for success or negative error code.
609 */
610 static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
612 {
613 struct snd_soc_codec *codec = rt5677->codec;
614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
643
644 err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648 }
649
650 /**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
661 {
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
663 value, 0x0001);
664 }
665
666 /**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
671 *
672 *
673 * Returns 0 for success or negative error code.
674 */
675 static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
677 {
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
680
681 *value &= 0xffff;
682
683 return ret;
684 }
685
686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
687 {
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
689
690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
696 }
697 }
698
699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700 {
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
706 return -ENXIO;
707
708 if (on && !activity) {
709 activity = true;
710
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
713
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
721 switch (rt5677->type) {
722 case RT5677:
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
724 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
726 RT5677_PLL2_PR_SRC_MASK |
727 RT5677_DSP_CLK_SRC_MASK,
728 RT5677_PLL2_PR_SRC_MCLK2 |
729 RT5677_DSP_CLK_SRC_BYPASS);
730 break;
731 case RT5676:
732 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
733 RT5677_DSP_CLK_SRC_MASK,
734 RT5677_DSP_CLK_SRC_BYPASS);
735 break;
736 default:
737 break;
738 }
739 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
740 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
741 rt5677_set_dsp_mode(codec, true);
742
743 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
744 codec->dev);
745 if (ret == 0) {
746 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
747 release_firmware(rt5677->fw1);
748 }
749
750 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
751 codec->dev);
752 if (ret == 0) {
753 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
754 release_firmware(rt5677->fw2);
755 }
756
757 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
758
759 regcache_cache_bypass(rt5677->regmap, false);
760 regcache_cache_only(rt5677->regmap, true);
761 } else if (!on && activity) {
762 activity = false;
763
764 regcache_cache_only(rt5677->regmap, false);
765 regcache_cache_bypass(rt5677->regmap, true);
766
767 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
768 rt5677_set_dsp_mode(codec, false);
769 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
770
771 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
772
773 regcache_cache_bypass(rt5677->regmap, false);
774 regcache_mark_dirty(rt5677->regmap);
775 regcache_sync(rt5677->regmap);
776 }
777
778 return 0;
779 }
780
781 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
782 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
783 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
784 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
786 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
787
788 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
789 static unsigned int bst_tlv[] = {
790 TLV_DB_RANGE_HEAD(7),
791 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
792 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
793 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
794 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
795 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
796 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
797 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
798 };
799
800 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_value *ucontrol)
802 {
803 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
804 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
805
806 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
807
808 return 0;
809 }
810
811 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
812 struct snd_ctl_elem_value *ucontrol)
813 {
814 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
815 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
816 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
817
818 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
819
820 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
821 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
822
823 return 0;
824 }
825
826 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
827 /* OUTPUT Control */
828 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
829 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
830 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
834
835 /* DAC Digital Volume */
836 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
837 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
838 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
840 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
842 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
844
845 /* IN1/IN2 Control */
846 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
847 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
848
849 /* ADC Digital Volume Control */
850 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
851 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
852 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860
861 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
862 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
863 adc_vol_tlv),
864 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
866 adc_vol_tlv),
867 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
869 adc_vol_tlv),
870 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
871 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
872 adc_vol_tlv),
873 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
874 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
875 adc_vol_tlv),
876
877 /* Sidetone Control */
878 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
879 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
880
881 /* ADC Boost Volume Control */
882 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
883 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
884 adc_bst_tlv),
885 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
886 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
887 adc_bst_tlv),
888 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
889 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
890 adc_bst_tlv),
891 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
892 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
893 adc_bst_tlv),
894 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
895 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
896 adc_bst_tlv),
897
898 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
899 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
900 };
901
902 /**
903 * set_dmic_clk - Set parameter of dmic.
904 *
905 * @w: DAPM widget.
906 * @kcontrol: The kcontrol of this widget.
907 * @event: Event id.
908 *
909 * Choose dmic clock between 1MHz and 3MHz.
910 * It is better for clock to approximate 3MHz.
911 */
912 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
913 struct snd_kcontrol *kcontrol, int event)
914 {
915 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
916 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
917 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
918
919 if (idx < 0)
920 dev_err(codec->dev, "Failed to set DMIC clock\n");
921 else
922 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
923 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
924 return idx;
925 }
926
927 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
928 struct snd_soc_dapm_widget *sink)
929 {
930 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
931 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
932 unsigned int val;
933
934 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
935 val &= RT5677_SCLK_SRC_MASK;
936 if (val == RT5677_SCLK_SRC_PLL1)
937 return 1;
938 else
939 return 0;
940 }
941
942 static int is_using_asrc(struct snd_soc_dapm_widget *source,
943 struct snd_soc_dapm_widget *sink)
944 {
945 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
946 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
947 unsigned int reg, shift, val;
948
949 if (source->reg == RT5677_ASRC_1) {
950 switch (source->shift) {
951 case 12:
952 reg = RT5677_ASRC_4;
953 shift = 0;
954 break;
955 case 13:
956 reg = RT5677_ASRC_4;
957 shift = 4;
958 break;
959 case 14:
960 reg = RT5677_ASRC_4;
961 shift = 8;
962 break;
963 case 15:
964 reg = RT5677_ASRC_4;
965 shift = 12;
966 break;
967 default:
968 return 0;
969 }
970 } else {
971 switch (source->shift) {
972 case 0:
973 reg = RT5677_ASRC_6;
974 shift = 8;
975 break;
976 case 1:
977 reg = RT5677_ASRC_6;
978 shift = 12;
979 break;
980 case 2:
981 reg = RT5677_ASRC_5;
982 shift = 0;
983 break;
984 case 3:
985 reg = RT5677_ASRC_5;
986 shift = 4;
987 break;
988 case 4:
989 reg = RT5677_ASRC_5;
990 shift = 8;
991 break;
992 case 5:
993 reg = RT5677_ASRC_5;
994 shift = 12;
995 break;
996 case 12:
997 reg = RT5677_ASRC_3;
998 shift = 0;
999 break;
1000 case 13:
1001 reg = RT5677_ASRC_3;
1002 shift = 4;
1003 break;
1004 case 14:
1005 reg = RT5677_ASRC_3;
1006 shift = 12;
1007 break;
1008 default:
1009 return 0;
1010 }
1011 }
1012
1013 regmap_read(rt5677->regmap, reg, &val);
1014 val = (val >> shift) & 0xf;
1015
1016 switch (val) {
1017 case 1 ... 6:
1018 return 1;
1019 default:
1020 return 0;
1021 }
1022
1023 }
1024
1025 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1026 struct snd_soc_dapm_widget *sink)
1027 {
1028 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1029 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1030
1031 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1032 return 1;
1033
1034 return 0;
1035 }
1036
1037 /**
1038 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1039 * @codec: SoC audio codec device.
1040 * @filter_mask: mask of filters.
1041 * @clk_src: clock source
1042 *
1043 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1044 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1045 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1046 * ASRC function will track i2s clock and generate a corresponding system clock
1047 * for codec. This function provides an API to select the clock source for a
1048 * set of filters specified by the mask. And the codec driver will turn on ASRC
1049 * for these filters if ASRC is selected as their clock source.
1050 */
1051 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1052 unsigned int filter_mask, unsigned int clk_src)
1053 {
1054 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1055 unsigned int asrc3_mask = 0, asrc3_value = 0;
1056 unsigned int asrc4_mask = 0, asrc4_value = 0;
1057 unsigned int asrc5_mask = 0, asrc5_value = 0;
1058 unsigned int asrc6_mask = 0, asrc6_value = 0;
1059 unsigned int asrc7_mask = 0, asrc7_value = 0;
1060
1061 switch (clk_src) {
1062 case RT5677_CLK_SEL_SYS:
1063 case RT5677_CLK_SEL_I2S1_ASRC:
1064 case RT5677_CLK_SEL_I2S2_ASRC:
1065 case RT5677_CLK_SEL_I2S3_ASRC:
1066 case RT5677_CLK_SEL_I2S4_ASRC:
1067 case RT5677_CLK_SEL_I2S5_ASRC:
1068 case RT5677_CLK_SEL_I2S6_ASRC:
1069 case RT5677_CLK_SEL_SYS2:
1070 case RT5677_CLK_SEL_SYS3:
1071 case RT5677_CLK_SEL_SYS4:
1072 case RT5677_CLK_SEL_SYS5:
1073 case RT5677_CLK_SEL_SYS6:
1074 case RT5677_CLK_SEL_SYS7:
1075 break;
1076
1077 default:
1078 return -EINVAL;
1079 }
1080
1081 /* ASRC 3 */
1082 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1083 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1084 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1085 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1086 }
1087
1088 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1089 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1090 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1091 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1092 }
1093
1094 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1095 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1096 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1097 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1098 }
1099
1100 if (asrc3_mask)
1101 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1102 asrc3_value);
1103
1104 /* ASRC 4 */
1105 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1106 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1107 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1108 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1109 }
1110
1111 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1112 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1113 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1114 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1115 }
1116
1117 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1118 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1119 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1120 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1121 }
1122
1123 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1124 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1125 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1126 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1127 }
1128
1129 if (asrc4_mask)
1130 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1131 asrc4_value);
1132
1133 /* ASRC 5 */
1134 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1135 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1136 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1137 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1138 }
1139
1140 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1141 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1142 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1143 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1144 }
1145
1146 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1147 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1148 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1149 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1150 }
1151
1152 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1153 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1154 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1155 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1156 }
1157
1158 if (asrc5_mask)
1159 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1160 asrc5_value);
1161
1162 /* ASRC 6 */
1163 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1164 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1165 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1166 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1167 }
1168
1169 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1170 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1171 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1172 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1173 }
1174
1175 if (asrc6_mask)
1176 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1177 asrc6_value);
1178
1179 /* ASRC 7 */
1180 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1181 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1182 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1183 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1184 }
1185
1186 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1187 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1188 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1189 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1190 }
1191
1192 if (asrc7_mask)
1193 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1194 asrc7_value);
1195
1196 return 0;
1197 }
1198 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1199
1200 /* Digital Mixer */
1201 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1202 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1203 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1204 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1205 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1206 };
1207
1208 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1209 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1210 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1211 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1212 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1213 };
1214
1215 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1216 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1217 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1218 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1219 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1220 };
1221
1222 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1223 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1224 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1225 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1226 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1227 };
1228
1229 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1230 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1231 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1232 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1233 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1234 };
1235
1236 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1237 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1238 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1239 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1240 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1241 };
1242
1243 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1244 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1245 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1246 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1247 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1248 };
1249
1250 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1251 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1252 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1254 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1255 };
1256
1257 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1258 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1259 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1260 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1261 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1262 };
1263
1264 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1265 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1266 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1267 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1268 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1269 };
1270
1271 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1272 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1273 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1274 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1275 RT5677_M_DAC1_L_SFT, 1, 1),
1276 };
1277
1278 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1279 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1280 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1281 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1282 RT5677_M_DAC1_R_SFT, 1, 1),
1283 };
1284
1285 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1286 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1287 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1288 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1289 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1290 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1291 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1292 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1293 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1294 };
1295
1296 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1297 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1298 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1299 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1300 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1301 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1302 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1303 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1304 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1305 };
1306
1307 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1308 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1309 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1310 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1311 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1312 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1313 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1314 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1315 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1316 };
1317
1318 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1319 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1320 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1321 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1322 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1323 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1324 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1325 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1326 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1327 };
1328
1329 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1330 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1331 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1332 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1333 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1334 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1335 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1336 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1337 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1338 };
1339
1340 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1341 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1342 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1343 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1344 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1345 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1346 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1347 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1348 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1349 };
1350
1351 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1352 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1353 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1354 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1355 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1356 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1357 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1358 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1359 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1360 };
1361
1362 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1363 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1364 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1365 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1366 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1367 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1368 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1369 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1370 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1371 };
1372
1373 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1374 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1375 RT5677_DSP_IB_01_H_SFT, 1, 1),
1376 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1377 RT5677_DSP_IB_23_H_SFT, 1, 1),
1378 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1379 RT5677_DSP_IB_45_H_SFT, 1, 1),
1380 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1381 RT5677_DSP_IB_6_H_SFT, 1, 1),
1382 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1383 RT5677_DSP_IB_7_H_SFT, 1, 1),
1384 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1385 RT5677_DSP_IB_8_H_SFT, 1, 1),
1386 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1387 RT5677_DSP_IB_9_H_SFT, 1, 1),
1388 };
1389
1390 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1391 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1392 RT5677_DSP_IB_01_L_SFT, 1, 1),
1393 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1394 RT5677_DSP_IB_23_L_SFT, 1, 1),
1395 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1396 RT5677_DSP_IB_45_L_SFT, 1, 1),
1397 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1398 RT5677_DSP_IB_6_L_SFT, 1, 1),
1399 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1400 RT5677_DSP_IB_7_L_SFT, 1, 1),
1401 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1402 RT5677_DSP_IB_8_L_SFT, 1, 1),
1403 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1404 RT5677_DSP_IB_9_L_SFT, 1, 1),
1405 };
1406
1407 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1408 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1409 RT5677_DSP_IB_01_H_SFT, 1, 1),
1410 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1411 RT5677_DSP_IB_23_H_SFT, 1, 1),
1412 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1413 RT5677_DSP_IB_45_H_SFT, 1, 1),
1414 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1415 RT5677_DSP_IB_6_H_SFT, 1, 1),
1416 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1417 RT5677_DSP_IB_7_H_SFT, 1, 1),
1418 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1419 RT5677_DSP_IB_8_H_SFT, 1, 1),
1420 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1421 RT5677_DSP_IB_9_H_SFT, 1, 1),
1422 };
1423
1424 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1425 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1426 RT5677_DSP_IB_01_L_SFT, 1, 1),
1427 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1428 RT5677_DSP_IB_23_L_SFT, 1, 1),
1429 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1430 RT5677_DSP_IB_45_L_SFT, 1, 1),
1431 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1432 RT5677_DSP_IB_6_L_SFT, 1, 1),
1433 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1434 RT5677_DSP_IB_7_L_SFT, 1, 1),
1435 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1436 RT5677_DSP_IB_8_L_SFT, 1, 1),
1437 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1438 RT5677_DSP_IB_9_L_SFT, 1, 1),
1439 };
1440
1441 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1442 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1443 RT5677_DSP_IB_01_H_SFT, 1, 1),
1444 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1445 RT5677_DSP_IB_23_H_SFT, 1, 1),
1446 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1447 RT5677_DSP_IB_45_H_SFT, 1, 1),
1448 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1449 RT5677_DSP_IB_6_H_SFT, 1, 1),
1450 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1451 RT5677_DSP_IB_7_H_SFT, 1, 1),
1452 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1453 RT5677_DSP_IB_8_H_SFT, 1, 1),
1454 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1455 RT5677_DSP_IB_9_H_SFT, 1, 1),
1456 };
1457
1458 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1459 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1460 RT5677_DSP_IB_01_L_SFT, 1, 1),
1461 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1462 RT5677_DSP_IB_23_L_SFT, 1, 1),
1463 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1464 RT5677_DSP_IB_45_L_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1466 RT5677_DSP_IB_6_L_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1468 RT5677_DSP_IB_7_L_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1470 RT5677_DSP_IB_8_L_SFT, 1, 1),
1471 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1472 RT5677_DSP_IB_9_L_SFT, 1, 1),
1473 };
1474
1475
1476 /* Mux */
1477 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1478 static const char * const rt5677_dac1_src[] = {
1479 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1480 "OB 01"
1481 };
1482
1483 static SOC_ENUM_SINGLE_DECL(
1484 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1485 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1486
1487 static const struct snd_kcontrol_new rt5677_dac1_mux =
1488 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1489
1490 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1491 static const char * const rt5677_adda1_src[] = {
1492 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1493 };
1494
1495 static SOC_ENUM_SINGLE_DECL(
1496 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1497 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1498
1499 static const struct snd_kcontrol_new rt5677_adda1_mux =
1500 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1501
1502
1503 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1504 static const char * const rt5677_dac2l_src[] = {
1505 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1506 "OB 2",
1507 };
1508
1509 static SOC_ENUM_SINGLE_DECL(
1510 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1511 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1512
1513 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1514 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1515
1516 static const char * const rt5677_dac2r_src[] = {
1517 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1518 "OB 3", "Haptic Generator", "VAD ADC"
1519 };
1520
1521 static SOC_ENUM_SINGLE_DECL(
1522 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1523 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1524
1525 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1526 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1527
1528 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1529 static const char * const rt5677_dac3l_src[] = {
1530 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1531 "SLB DAC 4", "OB 4"
1532 };
1533
1534 static SOC_ENUM_SINGLE_DECL(
1535 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1536 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1537
1538 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1539 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1540
1541 static const char * const rt5677_dac3r_src[] = {
1542 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1543 "SLB DAC 5", "OB 5"
1544 };
1545
1546 static SOC_ENUM_SINGLE_DECL(
1547 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1548 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1549
1550 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1551 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1552
1553 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1554 static const char * const rt5677_dac4l_src[] = {
1555 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1556 "SLB DAC 6", "OB 6"
1557 };
1558
1559 static SOC_ENUM_SINGLE_DECL(
1560 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1561 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1562
1563 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1564 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1565
1566 static const char * const rt5677_dac4r_src[] = {
1567 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1568 "SLB DAC 7", "OB 7"
1569 };
1570
1571 static SOC_ENUM_SINGLE_DECL(
1572 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1573 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1574
1575 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1576 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1577
1578 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1579 static const char * const rt5677_iob_bypass_src[] = {
1580 "Bypass", "Pass SRC"
1581 };
1582
1583 static SOC_ENUM_SINGLE_DECL(
1584 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1585 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1586
1587 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1588 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1589
1590 static SOC_ENUM_SINGLE_DECL(
1591 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1592 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1593
1594 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1595 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1596
1597 static SOC_ENUM_SINGLE_DECL(
1598 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1599 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1600
1601 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1602 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1603
1604 static SOC_ENUM_SINGLE_DECL(
1605 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1606 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1607
1608 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1609 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1610
1611 static SOC_ENUM_SINGLE_DECL(
1612 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1613 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1614
1615 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1616 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1617
1618 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1619 static const char * const rt5677_stereo_adc2_src[] = {
1620 "DD MIX1", "DMIC", "Stereo DAC MIX"
1621 };
1622
1623 static SOC_ENUM_SINGLE_DECL(
1624 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1625 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1626
1627 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1628 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1629
1630 static SOC_ENUM_SINGLE_DECL(
1631 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1632 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1633
1634 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1635 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1636
1637 static SOC_ENUM_SINGLE_DECL(
1638 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1639 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1640
1641 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1642 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1643
1644 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1645 static const char * const rt5677_dmic_src[] = {
1646 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1647 };
1648
1649 static SOC_ENUM_SINGLE_DECL(
1650 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1651 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1652
1653 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1654 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1655
1656 static SOC_ENUM_SINGLE_DECL(
1657 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1658 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1659
1660 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1661 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1662
1663 static SOC_ENUM_SINGLE_DECL(
1664 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1665 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1666
1667 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1668 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1669
1670 static SOC_ENUM_SINGLE_DECL(
1671 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1672 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1673
1674 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1675 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1676
1677 static SOC_ENUM_SINGLE_DECL(
1678 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1679 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1680
1681 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1682 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1683
1684 static SOC_ENUM_SINGLE_DECL(
1685 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1686 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1687
1688 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1689 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1690
1691 /* Stereo2 ADC Source */ /* MX-26 [0] */
1692 static const char * const rt5677_stereo2_adc_lr_src[] = {
1693 "L", "LR"
1694 };
1695
1696 static SOC_ENUM_SINGLE_DECL(
1697 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1698 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1699
1700 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1701 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1702
1703 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1704 static const char * const rt5677_stereo_adc1_src[] = {
1705 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1706 };
1707
1708 static SOC_ENUM_SINGLE_DECL(
1709 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1710 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1711
1712 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1713 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1714
1715 static SOC_ENUM_SINGLE_DECL(
1716 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1717 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1718
1719 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1720 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1721
1722 static SOC_ENUM_SINGLE_DECL(
1723 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1724 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1725
1726 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1727 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1728
1729 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1730 static const char * const rt5677_mono_adc2_l_src[] = {
1731 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1732 };
1733
1734 static SOC_ENUM_SINGLE_DECL(
1735 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1736 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1737
1738 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1739 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1740
1741 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1742 static const char * const rt5677_mono_adc1_l_src[] = {
1743 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1744 };
1745
1746 static SOC_ENUM_SINGLE_DECL(
1747 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1748 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1749
1750 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1751 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1752
1753 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1754 static const char * const rt5677_mono_adc2_r_src[] = {
1755 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1756 };
1757
1758 static SOC_ENUM_SINGLE_DECL(
1759 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1760 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1761
1762 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1763 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1764
1765 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1766 static const char * const rt5677_mono_adc1_r_src[] = {
1767 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1768 };
1769
1770 static SOC_ENUM_SINGLE_DECL(
1771 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1772 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1773
1774 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1775 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1776
1777 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1778 static const char * const rt5677_stereo4_adc2_src[] = {
1779 "DD MIX1", "DMIC", "DD MIX2"
1780 };
1781
1782 static SOC_ENUM_SINGLE_DECL(
1783 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1784 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1785
1786 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1787 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1788
1789
1790 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1791 static const char * const rt5677_stereo4_adc1_src[] = {
1792 "DD MIX1", "ADC1/2", "DD MIX2"
1793 };
1794
1795 static SOC_ENUM_SINGLE_DECL(
1796 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1797 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1798
1799 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1800 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1801
1802 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1803 static const char * const rt5677_inbound01_src[] = {
1804 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1805 "VAD ADC/DAC1 FS"
1806 };
1807
1808 static SOC_ENUM_SINGLE_DECL(
1809 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1810 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1811
1812 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1813 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1814
1815 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1816 static const char * const rt5677_inbound23_src[] = {
1817 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1818 "DAC1 FS", "IF4 DAC"
1819 };
1820
1821 static SOC_ENUM_SINGLE_DECL(
1822 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1823 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1824
1825 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1826 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1827
1828 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1829 static const char * const rt5677_inbound45_src[] = {
1830 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1831 "IF3 DAC"
1832 };
1833
1834 static SOC_ENUM_SINGLE_DECL(
1835 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1836 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1837
1838 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1839 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1840
1841 /* InBound6 Source */ /* MX-A3 [2:0] */
1842 static const char * const rt5677_inbound6_src[] = {
1843 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1844 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1845 };
1846
1847 static SOC_ENUM_SINGLE_DECL(
1848 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1849 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1850
1851 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1852 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1853
1854 /* InBound7 Source */ /* MX-A4 [14:12] */
1855 static const char * const rt5677_inbound7_src[] = {
1856 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1857 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1858 };
1859
1860 static SOC_ENUM_SINGLE_DECL(
1861 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1862 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1863
1864 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1865 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1866
1867 /* InBound8 Source */ /* MX-A4 [10:8] */
1868 static const char * const rt5677_inbound8_src[] = {
1869 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1870 "MONO ADC MIX L", "DACL1 FS"
1871 };
1872
1873 static SOC_ENUM_SINGLE_DECL(
1874 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1875 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1876
1877 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1878 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1879
1880 /* InBound9 Source */ /* MX-A4 [6:4] */
1881 static const char * const rt5677_inbound9_src[] = {
1882 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1883 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1884 };
1885
1886 static SOC_ENUM_SINGLE_DECL(
1887 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1888 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1889
1890 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1891 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1892
1893 /* VAD Source */ /* MX-9F [6:4] */
1894 static const char * const rt5677_vad_src[] = {
1895 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1896 "STO3 ADC MIX L"
1897 };
1898
1899 static SOC_ENUM_SINGLE_DECL(
1900 rt5677_vad_enum, RT5677_VAD_CTRL4,
1901 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1902
1903 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1904 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1905
1906 /* Sidetone Source */ /* MX-13 [11:9] */
1907 static const char * const rt5677_sidetone_src[] = {
1908 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1909 };
1910
1911 static SOC_ENUM_SINGLE_DECL(
1912 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1913 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1914
1915 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1916 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1917
1918 /* DAC1/2 Source */ /* MX-15 [1:0] */
1919 static const char * const rt5677_dac12_src[] = {
1920 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1921 };
1922
1923 static SOC_ENUM_SINGLE_DECL(
1924 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1925 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1926
1927 static const struct snd_kcontrol_new rt5677_dac12_mux =
1928 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1929
1930 /* DAC3 Source */ /* MX-15 [5:4] */
1931 static const char * const rt5677_dac3_src[] = {
1932 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1933 };
1934
1935 static SOC_ENUM_SINGLE_DECL(
1936 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1937 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1938
1939 static const struct snd_kcontrol_new rt5677_dac3_mux =
1940 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1941
1942 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1943 static const char * const rt5677_pdm_src[] = {
1944 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1945 };
1946
1947 static SOC_ENUM_SINGLE_DECL(
1948 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1949 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1950
1951 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1952 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1953
1954 static SOC_ENUM_SINGLE_DECL(
1955 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1956 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1957
1958 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1959 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1960
1961 static SOC_ENUM_SINGLE_DECL(
1962 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1963 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1964
1965 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1966 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1967
1968 static SOC_ENUM_SINGLE_DECL(
1969 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1970 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1971
1972 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1973 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1974
1975 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1976 static const char * const rt5677_if12_adc1_src[] = {
1977 "STO1 ADC MIX", "OB01", "VAD ADC"
1978 };
1979
1980 static SOC_ENUM_SINGLE_DECL(
1981 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1982 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1983
1984 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1985 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1986
1987 static SOC_ENUM_SINGLE_DECL(
1988 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1989 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1990
1991 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1992 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1993
1994 static SOC_ENUM_SINGLE_DECL(
1995 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1996 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1997
1998 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1999 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2000
2001 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2002 static const char * const rt5677_if12_adc2_src[] = {
2003 "STO2 ADC MIX", "OB23"
2004 };
2005
2006 static SOC_ENUM_SINGLE_DECL(
2007 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2008 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2009
2010 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2011 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2012
2013 static SOC_ENUM_SINGLE_DECL(
2014 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2015 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2016
2017 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2018 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2019
2020 static SOC_ENUM_SINGLE_DECL(
2021 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2022 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2023
2024 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2025 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2026
2027 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2028 static const char * const rt5677_if12_adc3_src[] = {
2029 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2030 };
2031
2032 static SOC_ENUM_SINGLE_DECL(
2033 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2034 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2035
2036 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2037 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2038
2039 static SOC_ENUM_SINGLE_DECL(
2040 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2041 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2042
2043 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2044 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2045
2046 static SOC_ENUM_SINGLE_DECL(
2047 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2048 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2049
2050 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2051 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2052
2053 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2054 static const char * const rt5677_if12_adc4_src[] = {
2055 "STO4 ADC MIX", "OB67", "OB01"
2056 };
2057
2058 static SOC_ENUM_SINGLE_DECL(
2059 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2060 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2061
2062 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2063 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2064
2065 static SOC_ENUM_SINGLE_DECL(
2066 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2067 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2068
2069 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2070 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2071
2072 static SOC_ENUM_SINGLE_DECL(
2073 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2074 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2075
2076 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2077 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2078
2079 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2080 static const char * const rt5677_if34_adc_src[] = {
2081 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2082 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2083 };
2084
2085 static SOC_ENUM_SINGLE_DECL(
2086 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2087 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2088
2089 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2090 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2091
2092 static SOC_ENUM_SINGLE_DECL(
2093 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2094 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2095
2096 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2097 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2098
2099 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2100 static const char * const rt5677_if12_adc_swap_src[] = {
2101 "L/R", "R/L", "L/L", "R/R"
2102 };
2103
2104 static SOC_ENUM_SINGLE_DECL(
2105 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2106 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2107
2108 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2109 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2110
2111 static SOC_ENUM_SINGLE_DECL(
2112 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2113 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2114
2115 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2116 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2117
2118 static SOC_ENUM_SINGLE_DECL(
2119 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2120 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2121
2122 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2123 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2124
2125 static SOC_ENUM_SINGLE_DECL(
2126 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2127 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2128
2129 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2130 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2131
2132 static SOC_ENUM_SINGLE_DECL(
2133 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2134 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2135
2136 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2137 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2138
2139 static SOC_ENUM_SINGLE_DECL(
2140 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2141 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2142
2143 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2144 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2145
2146 static SOC_ENUM_SINGLE_DECL(
2147 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2148 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2149
2150 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2151 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2152
2153 static SOC_ENUM_SINGLE_DECL(
2154 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2155 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2156
2157 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2158 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2159
2160 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2161 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2162 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2163 "3/1/2/4", "3/4/1/2"
2164 };
2165
2166 static SOC_ENUM_SINGLE_DECL(
2167 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2168 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2169
2170 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2171 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2172
2173 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2174 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2175 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2176 "2/3/1/4", "3/4/1/2"
2177 };
2178
2179 static SOC_ENUM_SINGLE_DECL(
2180 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2181 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2182
2183 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2184 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2185
2186 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2187 MX-3F[14:12][10:8][6:4][2:0]
2188 MX-43[14:12][10:8][6:4][2:0]
2189 MX-44[14:12][10:8][6:4][2:0] */
2190 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2191 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2192 };
2193
2194 static SOC_ENUM_SINGLE_DECL(
2195 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2196 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2197
2198 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2199 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2200
2201 static SOC_ENUM_SINGLE_DECL(
2202 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2203 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2204
2205 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2206 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2207
2208 static SOC_ENUM_SINGLE_DECL(
2209 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2210 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2211
2212 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2213 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2214
2215 static SOC_ENUM_SINGLE_DECL(
2216 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2217 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2218
2219 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2220 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2221
2222 static SOC_ENUM_SINGLE_DECL(
2223 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2224 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2225
2226 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2227 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2228
2229 static SOC_ENUM_SINGLE_DECL(
2230 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2231 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2232
2233 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2234 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2235
2236 static SOC_ENUM_SINGLE_DECL(
2237 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2238 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2239
2240 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2241 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2242
2243 static SOC_ENUM_SINGLE_DECL(
2244 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2245 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2246
2247 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2248 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2249
2250 static SOC_ENUM_SINGLE_DECL(
2251 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2252 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2253
2254 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2255 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2256
2257 static SOC_ENUM_SINGLE_DECL(
2258 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2259 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2260
2261 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2262 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2263
2264 static SOC_ENUM_SINGLE_DECL(
2265 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2266 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2267
2268 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2269 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2270
2271 static SOC_ENUM_SINGLE_DECL(
2272 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2273 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2274
2275 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2276 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2277
2278 static SOC_ENUM_SINGLE_DECL(
2279 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2280 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2281
2282 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2283 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2284
2285 static SOC_ENUM_SINGLE_DECL(
2286 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2287 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2288
2289 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2290 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2291
2292 static SOC_ENUM_SINGLE_DECL(
2293 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2294 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2295
2296 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2297 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2298
2299 static SOC_ENUM_SINGLE_DECL(
2300 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2301 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2302
2303 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2304 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2305
2306 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2307 struct snd_kcontrol *kcontrol, int event)
2308 {
2309 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2310 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2311
2312 switch (event) {
2313 case SND_SOC_DAPM_POST_PMU:
2314 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2315 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2316 break;
2317
2318 case SND_SOC_DAPM_PRE_PMD:
2319 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2320 RT5677_PWR_BST1_P, 0);
2321 break;
2322
2323 default:
2324 return 0;
2325 }
2326
2327 return 0;
2328 }
2329
2330 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2331 struct snd_kcontrol *kcontrol, int event)
2332 {
2333 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2334 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2335
2336 switch (event) {
2337 case SND_SOC_DAPM_POST_PMU:
2338 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2339 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2340 break;
2341
2342 case SND_SOC_DAPM_PRE_PMD:
2343 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2344 RT5677_PWR_BST2_P, 0);
2345 break;
2346
2347 default:
2348 return 0;
2349 }
2350
2351 return 0;
2352 }
2353
2354 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2355 struct snd_kcontrol *kcontrol, int event)
2356 {
2357 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2358 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2359
2360 switch (event) {
2361 case SND_SOC_DAPM_PRE_PMU:
2362 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2363 break;
2364
2365 case SND_SOC_DAPM_POST_PMU:
2366 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2367 break;
2368
2369 default:
2370 return 0;
2371 }
2372
2373 return 0;
2374 }
2375
2376 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2377 struct snd_kcontrol *kcontrol, int event)
2378 {
2379 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2380 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2381
2382 switch (event) {
2383 case SND_SOC_DAPM_PRE_PMU:
2384 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2385 break;
2386
2387 case SND_SOC_DAPM_POST_PMU:
2388 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2389 break;
2390
2391 default:
2392 return 0;
2393 }
2394
2395 return 0;
2396 }
2397
2398 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2399 struct snd_kcontrol *kcontrol, int event)
2400 {
2401 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2402 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2403
2404 switch (event) {
2405 case SND_SOC_DAPM_POST_PMU:
2406 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2407 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2408 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2409 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2410 break;
2411
2412 case SND_SOC_DAPM_PRE_PMD:
2413 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2414 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2415 RT5677_PWR_CLK_MB, 0);
2416 break;
2417
2418 default:
2419 return 0;
2420 }
2421
2422 return 0;
2423 }
2424
2425 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2426 struct snd_kcontrol *kcontrol, int event)
2427 {
2428 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2429 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2430 unsigned int value;
2431
2432 switch (event) {
2433 case SND_SOC_DAPM_PRE_PMU:
2434 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2435 if (value & RT5677_IF1_ADC_CTRL_MASK)
2436 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2437 RT5677_IF1_ADC_MODE_MASK,
2438 RT5677_IF1_ADC_MODE_TDM);
2439 break;
2440
2441 default:
2442 return 0;
2443 }
2444
2445 return 0;
2446 }
2447
2448 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2449 struct snd_kcontrol *kcontrol, int event)
2450 {
2451 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2452 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2453 unsigned int value;
2454
2455 switch (event) {
2456 case SND_SOC_DAPM_PRE_PMU:
2457 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2458 if (value & RT5677_IF2_ADC_CTRL_MASK)
2459 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2460 RT5677_IF2_ADC_MODE_MASK,
2461 RT5677_IF2_ADC_MODE_TDM);
2462 break;
2463
2464 default:
2465 return 0;
2466 }
2467
2468 return 0;
2469 }
2470
2471 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2472 struct snd_kcontrol *kcontrol, int event)
2473 {
2474 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2475 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2476
2477 switch (event) {
2478 case SND_SOC_DAPM_POST_PMU:
2479 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2480 !rt5677->is_vref_slow) {
2481 mdelay(20);
2482 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2483 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2484 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2485 rt5677->is_vref_slow = true;
2486 }
2487 break;
2488
2489 default:
2490 return 0;
2491 }
2492
2493 return 0;
2494 }
2495
2496 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2497 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2498 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2499 SND_SOC_DAPM_POST_PMU),
2500 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2501 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2502 SND_SOC_DAPM_POST_PMU),
2503
2504 /* ASRC */
2505 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2506 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2507 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2508 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2509 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2510 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2511 0),
2512 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2513 0),
2514 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2515 0),
2516 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2517 0),
2518 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2519 0),
2520 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2521 0),
2522 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2523 0),
2524 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2525 0),
2526 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2527 0),
2528 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2529 0),
2530 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2531 0),
2532 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2533 0),
2534 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2535 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2536 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2537 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2538 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2539 0),
2540 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2541 0),
2542
2543 /* Input Side */
2544 /* micbias */
2545 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2546 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2547 SND_SOC_DAPM_POST_PMU),
2548
2549 /* Input Lines */
2550 SND_SOC_DAPM_INPUT("DMIC L1"),
2551 SND_SOC_DAPM_INPUT("DMIC R1"),
2552 SND_SOC_DAPM_INPUT("DMIC L2"),
2553 SND_SOC_DAPM_INPUT("DMIC R2"),
2554 SND_SOC_DAPM_INPUT("DMIC L3"),
2555 SND_SOC_DAPM_INPUT("DMIC R3"),
2556 SND_SOC_DAPM_INPUT("DMIC L4"),
2557 SND_SOC_DAPM_INPUT("DMIC R4"),
2558
2559 SND_SOC_DAPM_INPUT("IN1P"),
2560 SND_SOC_DAPM_INPUT("IN1N"),
2561 SND_SOC_DAPM_INPUT("IN2P"),
2562 SND_SOC_DAPM_INPUT("IN2N"),
2563
2564 SND_SOC_DAPM_INPUT("Haptic Generator"),
2565
2566 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2568 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2570
2571 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2572 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2573 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2574 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2575 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2576 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2577 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2578 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2579
2580 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2581 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2582
2583 /* Boost */
2584 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2585 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2586 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2587 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2588 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2589 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2590
2591 /* ADCs */
2592 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2593 0, 0),
2594 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2595 0, 0),
2596 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2597
2598 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2599 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2600 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2601 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2602 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2603 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2604 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2605 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2606
2607 /* ADC Mux */
2608 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2609 &rt5677_sto1_dmic_mux),
2610 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2611 &rt5677_sto1_adc1_mux),
2612 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2613 &rt5677_sto1_adc2_mux),
2614 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2615 &rt5677_sto2_dmic_mux),
2616 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2617 &rt5677_sto2_adc1_mux),
2618 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2619 &rt5677_sto2_adc2_mux),
2620 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2621 &rt5677_sto2_adc_lr_mux),
2622 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2623 &rt5677_sto3_dmic_mux),
2624 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2625 &rt5677_sto3_adc1_mux),
2626 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2627 &rt5677_sto3_adc2_mux),
2628 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2629 &rt5677_sto4_dmic_mux),
2630 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2631 &rt5677_sto4_adc1_mux),
2632 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2633 &rt5677_sto4_adc2_mux),
2634 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2635 &rt5677_mono_dmic_l_mux),
2636 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2637 &rt5677_mono_dmic_r_mux),
2638 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2639 &rt5677_mono_adc2_l_mux),
2640 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2641 &rt5677_mono_adc1_l_mux),
2642 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2643 &rt5677_mono_adc1_r_mux),
2644 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2645 &rt5677_mono_adc2_r_mux),
2646
2647 /* ADC Mixer */
2648 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2649 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2650 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2651 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2652 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2653 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2654 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2655 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2656 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2657 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2658 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2659 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2660 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2661 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2662 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2663 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2664 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2665 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2666 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2667 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2668 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2669 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2670 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2671 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2672 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2673 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2674 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2675 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2676 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2677 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2678 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2679 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2680
2681 /* ADC PGA */
2682 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2683 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2684 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2685 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2686 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2687 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2688 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2689 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2690 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2691 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2692 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2693 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2694 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2695 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2696 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2697 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2698
2699 /* DSP */
2700 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2701 &rt5677_ib9_src_mux),
2702 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2703 &rt5677_ib8_src_mux),
2704 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2705 &rt5677_ib7_src_mux),
2706 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2707 &rt5677_ib6_src_mux),
2708 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2709 &rt5677_ib45_src_mux),
2710 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2711 &rt5677_ib23_src_mux),
2712 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_ib01_src_mux),
2714 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_ib45_bypass_src_mux),
2716 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_ib23_bypass_src_mux),
2718 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_ib01_bypass_src_mux),
2720 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2721 &rt5677_ob23_bypass_src_mux),
2722 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_ob01_bypass_src_mux),
2724
2725 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2726 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2727
2728 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2729 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2730 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2731 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2732 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2733 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2734
2735 /* Digital Interface */
2736 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2737 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2738 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2739 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2740 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2741 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2742 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2743 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2744 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2745 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2746 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2747 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2748 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2749 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2750 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2751 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2752 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2753 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2754
2755 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2756 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2757 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2758 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2759 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2760 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2761 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2762 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2763 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2764 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2765 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2766 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2767 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2768 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2769 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2770 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2771 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2772 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2773
2774 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2775 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2776 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2777 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2778 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2779 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2780 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2781 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2782
2783 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2784 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2785 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2786 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2791
2792 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2793 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2803 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2804 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2805 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2806 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2807 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2808 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2810
2811 /* Digital Interface Select */
2812 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5677_if1_adc1_mux),
2814 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5677_if1_adc2_mux),
2816 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_if1_adc3_mux),
2818 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_if1_adc4_mux),
2820 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_if1_adc1_swap_mux),
2822 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_if1_adc2_swap_mux),
2824 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_if1_adc3_swap_mux),
2826 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5677_if1_adc4_swap_mux),
2828 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2830 SND_SOC_DAPM_PRE_PMU),
2831 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2832 &rt5677_if2_adc1_mux),
2833 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2834 &rt5677_if2_adc2_mux),
2835 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2836 &rt5677_if2_adc3_mux),
2837 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2838 &rt5677_if2_adc4_mux),
2839 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2840 &rt5677_if2_adc1_swap_mux),
2841 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2842 &rt5677_if2_adc2_swap_mux),
2843 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2844 &rt5677_if2_adc3_swap_mux),
2845 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2846 &rt5677_if2_adc4_swap_mux),
2847 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2848 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2849 SND_SOC_DAPM_PRE_PMU),
2850 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2851 &rt5677_if3_adc_mux),
2852 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2853 &rt5677_if4_adc_mux),
2854 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2855 &rt5677_slb_adc1_mux),
2856 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2857 &rt5677_slb_adc2_mux),
2858 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2859 &rt5677_slb_adc3_mux),
2860 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2861 &rt5677_slb_adc4_mux),
2862
2863 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2864 &rt5677_if1_dac0_tdm_sel_mux),
2865 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2866 &rt5677_if1_dac1_tdm_sel_mux),
2867 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2868 &rt5677_if1_dac2_tdm_sel_mux),
2869 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2870 &rt5677_if1_dac3_tdm_sel_mux),
2871 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2872 &rt5677_if1_dac4_tdm_sel_mux),
2873 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2874 &rt5677_if1_dac5_tdm_sel_mux),
2875 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2876 &rt5677_if1_dac6_tdm_sel_mux),
2877 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2878 &rt5677_if1_dac7_tdm_sel_mux),
2879
2880 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2881 &rt5677_if2_dac0_tdm_sel_mux),
2882 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2883 &rt5677_if2_dac1_tdm_sel_mux),
2884 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2885 &rt5677_if2_dac2_tdm_sel_mux),
2886 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2887 &rt5677_if2_dac3_tdm_sel_mux),
2888 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2889 &rt5677_if2_dac4_tdm_sel_mux),
2890 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2891 &rt5677_if2_dac5_tdm_sel_mux),
2892 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2893 &rt5677_if2_dac6_tdm_sel_mux),
2894 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2895 &rt5677_if2_dac7_tdm_sel_mux),
2896
2897 /* Audio Interface */
2898 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2899 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2900 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2901 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2902 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2903 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2904 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2905 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2906 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2907 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2908
2909 /* Sidetone Mux */
2910 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5677_sidetone_mux),
2912 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2913 RT5677_ST_EN_SFT, 0, NULL, 0),
2914
2915 /* VAD Mux*/
2916 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5677_vad_src_mux),
2918
2919 /* Tensilica DSP */
2920 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2922 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2923 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2924 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2925 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2926 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2927 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2928 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2929 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2930 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2931 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2932 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2933
2934 /* Output Side */
2935 /* DAC mixer before sound effect */
2936 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2937 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2938 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2939 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2940 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2941
2942 /* DAC Mux */
2943 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5677_dac1_mux),
2945 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5677_adda1_mux),
2947 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5677_dac12_mux),
2949 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_dac3_mux),
2951
2952 /* DAC2 channel Mux */
2953 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5677_dac2_l_mux),
2955 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5677_dac2_r_mux),
2957
2958 /* DAC3 channel Mux */
2959 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5677_dac3_l_mux),
2961 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_dac3_r_mux),
2963
2964 /* DAC4 channel Mux */
2965 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_dac4_l_mux),
2967 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5677_dac4_r_mux),
2969
2970 /* DAC Mixer */
2971 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2972 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2973 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
2974 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2975 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
2976 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2977 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2978 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2979 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2980 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2981 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2982 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2983 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2984 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
2985
2986 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2987 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2988 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2989 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2990 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2991 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2992 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2993 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2994 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2995 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2996 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2997 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2998 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2999 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3000 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3001 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3002 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3003 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3004 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3005 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3006
3007 /* DACs */
3008 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3009 RT5677_PWR_DAC1_BIT, 0),
3010 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3011 RT5677_PWR_DAC2_BIT, 0),
3012 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3013 RT5677_PWR_DAC3_BIT, 0),
3014
3015 /* PDM */
3016 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3017 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3018 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3019 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3020
3021 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3022 1, &rt5677_pdm1_l_mux),
3023 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3024 1, &rt5677_pdm1_r_mux),
3025 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3026 1, &rt5677_pdm2_l_mux),
3027 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3028 1, &rt5677_pdm2_r_mux),
3029
3030 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3031 0, NULL, 0),
3032 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3033 0, NULL, 0),
3034 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3035 0, NULL, 0),
3036
3037 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3038 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3039 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3040 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3041 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3042 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3043
3044 /* Output Lines */
3045 SND_SOC_DAPM_OUTPUT("LOUT1"),
3046 SND_SOC_DAPM_OUTPUT("LOUT2"),
3047 SND_SOC_DAPM_OUTPUT("LOUT3"),
3048 SND_SOC_DAPM_OUTPUT("PDM1L"),
3049 SND_SOC_DAPM_OUTPUT("PDM1R"),
3050 SND_SOC_DAPM_OUTPUT("PDM2L"),
3051 SND_SOC_DAPM_OUTPUT("PDM2R"),
3052
3053 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3054 };
3055
3056 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3057 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
3058 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
3059 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
3060 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
3061 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
3062 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
3063 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3064 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3065 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3066 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3067
3068 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3069 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3070 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3071 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3072 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3073 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3074 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3075 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3076 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3077 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3078 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3079 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3080 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3081
3082 { "DMIC1", NULL, "DMIC L1" },
3083 { "DMIC1", NULL, "DMIC R1" },
3084 { "DMIC2", NULL, "DMIC L2" },
3085 { "DMIC2", NULL, "DMIC R2" },
3086 { "DMIC3", NULL, "DMIC L3" },
3087 { "DMIC3", NULL, "DMIC R3" },
3088 { "DMIC4", NULL, "DMIC L4" },
3089 { "DMIC4", NULL, "DMIC R4" },
3090
3091 { "DMIC L1", NULL, "DMIC CLK" },
3092 { "DMIC R1", NULL, "DMIC CLK" },
3093 { "DMIC L2", NULL, "DMIC CLK" },
3094 { "DMIC R2", NULL, "DMIC CLK" },
3095 { "DMIC L3", NULL, "DMIC CLK" },
3096 { "DMIC R3", NULL, "DMIC CLK" },
3097 { "DMIC L4", NULL, "DMIC CLK" },
3098 { "DMIC R4", NULL, "DMIC CLK" },
3099
3100 { "DMIC L1", NULL, "DMIC1 power" },
3101 { "DMIC R1", NULL, "DMIC1 power" },
3102 { "DMIC L3", NULL, "DMIC3 power" },
3103 { "DMIC R3", NULL, "DMIC3 power" },
3104 { "DMIC L4", NULL, "DMIC4 power" },
3105 { "DMIC R4", NULL, "DMIC4 power" },
3106
3107 { "BST1", NULL, "IN1P" },
3108 { "BST1", NULL, "IN1N" },
3109 { "BST2", NULL, "IN2P" },
3110 { "BST2", NULL, "IN2N" },
3111
3112 { "IN1P", NULL, "MICBIAS1" },
3113 { "IN1N", NULL, "MICBIAS1" },
3114 { "IN2P", NULL, "MICBIAS1" },
3115 { "IN2N", NULL, "MICBIAS1" },
3116
3117 { "ADC 1", NULL, "BST1" },
3118 { "ADC 1", NULL, "ADC 1 power" },
3119 { "ADC 1", NULL, "ADC1 clock" },
3120 { "ADC 2", NULL, "BST2" },
3121 { "ADC 2", NULL, "ADC 2 power" },
3122 { "ADC 2", NULL, "ADC2 clock" },
3123
3124 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3125 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3126 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3127 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3128
3129 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3130 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3131 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3132 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3133
3134 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3135 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3136 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3137 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3138
3139 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3140 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3141 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3142 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3143
3144 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3145 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3146 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3147 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3148
3149 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3150 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3151 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3152 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3153
3154 { "ADC 1_2", NULL, "ADC 1" },
3155 { "ADC 1_2", NULL, "ADC 2" },
3156
3157 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3158 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3159 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3160
3161 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3162 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3163 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3164
3165 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3166 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3167 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3168
3169 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3170 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3171 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3172
3173 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3174 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3175 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3176
3177 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3178 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3179 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3180
3181 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3182 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3183 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3184
3185 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3186 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3187 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3188
3189 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3190 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3191 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3192
3193 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3194 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3195 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3196
3197 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3198 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3199 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3200
3201 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3202 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3203 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3204
3205 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3206 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3207 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3208 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3209
3210 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3211 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3212 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3213 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3214 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3215
3216 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3217 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3218
3219 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3220 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3221 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3222 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3223
3224 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3225 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3226
3227 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3228 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3229
3230 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3231 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3232 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3233 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3234 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3235
3236 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3237 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3238
3239 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3240 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3241 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3242 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3243
3244 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3245 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3246 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3247 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3248 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3249
3250 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3251 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3252
3253 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3254 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3255 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3256 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3257
3258 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3259 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3260 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3261 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3262 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3263
3264 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3265 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3266
3267 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3268 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3269 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3270 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3271
3272 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3273 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3274 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3275 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3276
3277 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3278 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3279
3280 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3281 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3282 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3283 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3284 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3285
3286 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3287 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3288 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3289
3290 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3291 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3292
3293 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3294 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3295 { "IF1 ADC3 Mux", "OB45", "OB45" },
3296
3297 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3298 { "IF1 ADC4 Mux", "OB67", "OB67" },
3299 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3300
3301 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3302 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3303 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3304 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3305
3306 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3307 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3308 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3309 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3310
3311 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3312 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3313 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3314 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3315
3316 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3317 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3318 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3319 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3320
3321 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3322 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3323 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3324 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3325
3326 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3327 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3328 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3329 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3330 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3331 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3332 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3333 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3334
3335 { "AIF1TX", NULL, "I2S1" },
3336 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3337
3338 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3339 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3340 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3341
3342 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3343 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3344
3345 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3346 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3347 { "IF2 ADC3 Mux", "OB45", "OB45" },
3348
3349 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3350 { "IF2 ADC4 Mux", "OB67", "OB67" },
3351 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3352
3353 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3354 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3355 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3356 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3357
3358 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3359 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3360 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3361 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3362
3363 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3364 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3365 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3366 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3367
3368 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3369 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3370 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3371 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3372
3373 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3374 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3375 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3376 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3377
3378 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3379 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3380 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3381 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3382 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3383 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3384 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3385 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3386
3387 { "AIF2TX", NULL, "I2S2" },
3388 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3389
3390 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3391 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3392 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3393 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3394 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3395 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3396 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3397 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3398
3399 { "AIF3TX", NULL, "I2S3" },
3400 { "AIF3TX", NULL, "IF3 ADC Mux" },
3401
3402 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3403 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3404 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3405 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3406 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3407 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3408 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3409 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3410
3411 { "AIF4TX", NULL, "I2S4" },
3412 { "AIF4TX", NULL, "IF4 ADC Mux" },
3413
3414 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3415 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3416 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3417
3418 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3419 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3420
3421 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3422 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3423 { "SLB ADC3 Mux", "OB45", "OB45" },
3424
3425 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3426 { "SLB ADC4 Mux", "OB67", "OB67" },
3427 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3428
3429 { "SLBTX", NULL, "SLB" },
3430 { "SLBTX", NULL, "SLB ADC1 Mux" },
3431 { "SLBTX", NULL, "SLB ADC2 Mux" },
3432 { "SLBTX", NULL, "SLB ADC3 Mux" },
3433 { "SLBTX", NULL, "SLB ADC4 Mux" },
3434
3435 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3436 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3437 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3438 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3439 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3440
3441 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3442 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3443
3444 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3445 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3446 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3447 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3448 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3449 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3450
3451 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3452 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3453
3454 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3455 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3456 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3457 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3458 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3459
3460 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3461 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3462
3463 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3464 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3465 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3466 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3467 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3468 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3469 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3470 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3471
3472 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3473 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3474 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3475 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3476 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3477 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3478 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3479 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3480
3481 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3482 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3483 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3484 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3485 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3486 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3487
3488 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3489 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3490 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3491 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3492 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3493 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3494 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3495
3496 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3497 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3498 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3499 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3500 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3501 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3502 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3503
3504 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3505 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3506 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3507 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3508 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3509 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3510 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3511
3512 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3513 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3514 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3515 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3516 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3517 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3518 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3519
3520 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3521 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3522 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3523 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3524 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3525 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3526 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3527
3528 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3529 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3530 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3531 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3532 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3533 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3534 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3535
3536 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3537 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3538 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3539 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3540 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3541 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3542 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3543
3544 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3545 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3546 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3547 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3548
3549 { "OutBound2", NULL, "OB23 Bypass Mux" },
3550 { "OutBound3", NULL, "OB23 Bypass Mux" },
3551 { "OutBound4", NULL, "OB4 MIX" },
3552 { "OutBound5", NULL, "OB5 MIX" },
3553 { "OutBound6", NULL, "OB6 MIX" },
3554 { "OutBound7", NULL, "OB7 MIX" },
3555
3556 { "OB45", NULL, "OutBound4" },
3557 { "OB45", NULL, "OutBound5" },
3558 { "OB67", NULL, "OutBound6" },
3559 { "OB67", NULL, "OutBound7" },
3560
3561 { "IF1 DAC0", NULL, "AIF1RX" },
3562 { "IF1 DAC1", NULL, "AIF1RX" },
3563 { "IF1 DAC2", NULL, "AIF1RX" },
3564 { "IF1 DAC3", NULL, "AIF1RX" },
3565 { "IF1 DAC4", NULL, "AIF1RX" },
3566 { "IF1 DAC5", NULL, "AIF1RX" },
3567 { "IF1 DAC6", NULL, "AIF1RX" },
3568 { "IF1 DAC7", NULL, "AIF1RX" },
3569 { "IF1 DAC0", NULL, "I2S1" },
3570 { "IF1 DAC1", NULL, "I2S1" },
3571 { "IF1 DAC2", NULL, "I2S1" },
3572 { "IF1 DAC3", NULL, "I2S1" },
3573 { "IF1 DAC4", NULL, "I2S1" },
3574 { "IF1 DAC5", NULL, "I2S1" },
3575 { "IF1 DAC6", NULL, "I2S1" },
3576 { "IF1 DAC7", NULL, "I2S1" },
3577
3578 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3579 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3580 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3581 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3582 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3583 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3584 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3585 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3586
3587 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3588 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3589 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3590 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3591 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3592 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3593 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3594 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3595
3596 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3597 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3598 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3599 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3600 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3601 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3602 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3603 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3604
3605 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3606 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3607 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3608 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3609 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3610 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3611 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3612 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3613
3614 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3615 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3616 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3617 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3618 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3619 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3620 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3621 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3622
3623 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3624 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3625 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3626 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3627 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3628 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3629 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3630 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3631
3632 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3633 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3634 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3635 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3636 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3637 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3638 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3639 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3640
3641 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3642 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3643 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3644 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3645 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3646 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3647 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3648 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3649
3650 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3651 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3652 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3653 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3654 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3655 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3656 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3657 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3658
3659 { "IF2 DAC0", NULL, "AIF2RX" },
3660 { "IF2 DAC1", NULL, "AIF2RX" },
3661 { "IF2 DAC2", NULL, "AIF2RX" },
3662 { "IF2 DAC3", NULL, "AIF2RX" },
3663 { "IF2 DAC4", NULL, "AIF2RX" },
3664 { "IF2 DAC5", NULL, "AIF2RX" },
3665 { "IF2 DAC6", NULL, "AIF2RX" },
3666 { "IF2 DAC7", NULL, "AIF2RX" },
3667 { "IF2 DAC0", NULL, "I2S2" },
3668 { "IF2 DAC1", NULL, "I2S2" },
3669 { "IF2 DAC2", NULL, "I2S2" },
3670 { "IF2 DAC3", NULL, "I2S2" },
3671 { "IF2 DAC4", NULL, "I2S2" },
3672 { "IF2 DAC5", NULL, "I2S2" },
3673 { "IF2 DAC6", NULL, "I2S2" },
3674 { "IF2 DAC7", NULL, "I2S2" },
3675
3676 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3677 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3678 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3679 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3680 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3681 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3682 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3683 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3684
3685 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3686 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3687 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3688 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3689 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3690 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3691 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3692 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3693
3694 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3695 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3696 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3697 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3698 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3699 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3700 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3701 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3702
3703 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3704 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3705 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3706 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3707 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3708 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3709 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3710 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3711
3712 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3713 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3714 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3715 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3716 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3717 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3718 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3719 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3720
3721 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3722 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3723 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3724 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3725 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3726 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3727 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3728 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3729
3730 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3731 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3732 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3733 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3734 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3735 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3736 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3737 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3738
3739 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3740 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3741 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3742 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3743 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3744 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3745 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3746 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3747
3748 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3749 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3750 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3751 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3752 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3753 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3754 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3755 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3756
3757 { "IF3 DAC", NULL, "AIF3RX" },
3758 { "IF3 DAC", NULL, "I2S3" },
3759
3760 { "IF4 DAC", NULL, "AIF4RX" },
3761 { "IF4 DAC", NULL, "I2S4" },
3762
3763 { "IF3 DAC L", NULL, "IF3 DAC" },
3764 { "IF3 DAC R", NULL, "IF3 DAC" },
3765
3766 { "IF4 DAC L", NULL, "IF4 DAC" },
3767 { "IF4 DAC R", NULL, "IF4 DAC" },
3768
3769 { "SLB DAC0", NULL, "SLBRX" },
3770 { "SLB DAC1", NULL, "SLBRX" },
3771 { "SLB DAC2", NULL, "SLBRX" },
3772 { "SLB DAC3", NULL, "SLBRX" },
3773 { "SLB DAC4", NULL, "SLBRX" },
3774 { "SLB DAC5", NULL, "SLBRX" },
3775 { "SLB DAC6", NULL, "SLBRX" },
3776 { "SLB DAC7", NULL, "SLBRX" },
3777 { "SLB DAC0", NULL, "SLB" },
3778 { "SLB DAC1", NULL, "SLB" },
3779 { "SLB DAC2", NULL, "SLB" },
3780 { "SLB DAC3", NULL, "SLB" },
3781 { "SLB DAC4", NULL, "SLB" },
3782 { "SLB DAC5", NULL, "SLB" },
3783 { "SLB DAC6", NULL, "SLB" },
3784 { "SLB DAC7", NULL, "SLB" },
3785
3786 { "SLB DAC01", NULL, "SLB DAC0" },
3787 { "SLB DAC01", NULL, "SLB DAC1" },
3788 { "SLB DAC23", NULL, "SLB DAC2" },
3789 { "SLB DAC23", NULL, "SLB DAC3" },
3790 { "SLB DAC45", NULL, "SLB DAC4" },
3791 { "SLB DAC45", NULL, "SLB DAC5" },
3792 { "SLB DAC67", NULL, "SLB DAC6" },
3793 { "SLB DAC67", NULL, "SLB DAC7" },
3794
3795 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3796 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3797 { "ADDA1 Mux", "OB 67", "OB67" },
3798
3799 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3800 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3801 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3802 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3803 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3804 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3805
3806 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3807 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3808 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3809 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3810
3811 { "DAC1 FS", NULL, "DAC1 MIXL" },
3812 { "DAC1 FS", NULL, "DAC1 MIXR" },
3813
3814 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3815 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3816 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3817 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3818 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3819 { "DAC2 L Mux", "OB 2", "OutBound2" },
3820
3821 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3822 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3823 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3824 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3825 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3826 { "DAC2 R Mux", "OB 3", "OutBound3" },
3827 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3828 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3829
3830 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3831 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3832 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3833 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3834 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3835 { "DAC3 L Mux", "OB 4", "OutBound4" },
3836
3837 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3838 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3839 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3840 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3841 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3842 { "DAC3 R Mux", "OB 5", "OutBound5" },
3843
3844 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3845 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3846 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3847 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3848 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3849 { "DAC4 L Mux", "OB 6", "OutBound6" },
3850
3851 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3852 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3853 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3854 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3855 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3856 { "DAC4 R Mux", "OB 7", "OutBound7" },
3857
3858 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3859 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3860 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3861 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3862 { "Sidetone Mux", "ADC1", "ADC 1" },
3863 { "Sidetone Mux", "ADC2", "ADC 2" },
3864 { "Sidetone Mux", NULL, "Sidetone Power" },
3865
3866 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3867 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3868 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3869 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3870 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3871 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3872 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3873 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3874 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3875 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3876 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3877
3878 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3879 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3880 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3881 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3882 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3883 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3884 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3885 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3886 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3887 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3888 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3889 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3890
3891 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3892 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3893 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3894 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3895 { "DD1 MIXL", NULL, "dac mono3 left filter" },
3896 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3897 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3898 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3899 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3900 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3901 { "DD1 MIXR", NULL, "dac mono3 right filter" },
3902 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3903
3904 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3905 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3906 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3907 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3908 { "DD2 MIXL", NULL, "dac mono4 left filter" },
3909 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3910 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3911 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3912 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3913 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3914 { "DD2 MIXR", NULL, "dac mono4 right filter" },
3915 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3916
3917 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3918 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3919 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3920 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3921 { "DD1 MIX", NULL, "DD1 MIXL" },
3922 { "DD1 MIX", NULL, "DD1 MIXR" },
3923 { "DD2 MIX", NULL, "DD2 MIXL" },
3924 { "DD2 MIX", NULL, "DD2 MIXR" },
3925
3926 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3927 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3928 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3929 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3930
3931 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3932 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3933 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3934 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3935
3936 { "DAC 1", NULL, "DAC12 SRC Mux" },
3937 { "DAC 2", NULL, "DAC12 SRC Mux" },
3938 { "DAC 3", NULL, "DAC3 SRC Mux" },
3939
3940 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3941 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3942 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3943 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3944 { "PDM1 L Mux", NULL, "PDM1 Power" },
3945 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3946 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3947 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3948 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3949 { "PDM1 R Mux", NULL, "PDM1 Power" },
3950 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3951 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3952 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3953 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3954 { "PDM2 L Mux", NULL, "PDM2 Power" },
3955 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3956 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3957 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3958 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3959 { "PDM2 R Mux", NULL, "PDM2 Power" },
3960
3961 { "LOUT1 amp", NULL, "DAC 1" },
3962 { "LOUT2 amp", NULL, "DAC 2" },
3963 { "LOUT3 amp", NULL, "DAC 3" },
3964
3965 { "LOUT1 vref", NULL, "LOUT1 amp" },
3966 { "LOUT2 vref", NULL, "LOUT2 amp" },
3967 { "LOUT3 vref", NULL, "LOUT3 amp" },
3968
3969 { "LOUT1", NULL, "LOUT1 vref" },
3970 { "LOUT2", NULL, "LOUT2 vref" },
3971 { "LOUT3", NULL, "LOUT3 vref" },
3972
3973 { "PDM1L", NULL, "PDM1 L Mux" },
3974 { "PDM1R", NULL, "PDM1 R Mux" },
3975 { "PDM2L", NULL, "PDM2 L Mux" },
3976 { "PDM2R", NULL, "PDM2 R Mux" },
3977 };
3978
3979 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3980 { "DMIC L2", NULL, "DMIC1 power" },
3981 { "DMIC R2", NULL, "DMIC1 power" },
3982 };
3983
3984 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3985 { "DMIC L2", NULL, "DMIC2 power" },
3986 { "DMIC R2", NULL, "DMIC2 power" },
3987 };
3988
3989 static int rt5677_hw_params(struct snd_pcm_substream *substream,
3990 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3991 {
3992 struct snd_soc_codec *codec = dai->codec;
3993 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3994 unsigned int val_len = 0, val_clk, mask_clk;
3995 int pre_div, bclk_ms, frame_size;
3996
3997 rt5677->lrck[dai->id] = params_rate(params);
3998 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
3999 if (pre_div < 0) {
4000 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4001 rt5677->sysclk, rt5677->lrck[dai->id]);
4002 return -EINVAL;
4003 }
4004 frame_size = snd_soc_params_to_frame_size(params);
4005 if (frame_size < 0) {
4006 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4007 return -EINVAL;
4008 }
4009 bclk_ms = frame_size > 32;
4010 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4011
4012 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4013 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4014 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4015 bclk_ms, pre_div, dai->id);
4016
4017 switch (params_width(params)) {
4018 case 16:
4019 break;
4020 case 20:
4021 val_len |= RT5677_I2S_DL_20;
4022 break;
4023 case 24:
4024 val_len |= RT5677_I2S_DL_24;
4025 break;
4026 case 8:
4027 val_len |= RT5677_I2S_DL_8;
4028 break;
4029 default:
4030 return -EINVAL;
4031 }
4032
4033 switch (dai->id) {
4034 case RT5677_AIF1:
4035 mask_clk = RT5677_I2S_PD1_MASK;
4036 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4037 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4038 RT5677_I2S_DL_MASK, val_len);
4039 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4040 mask_clk, val_clk);
4041 break;
4042 case RT5677_AIF2:
4043 mask_clk = RT5677_I2S_PD2_MASK;
4044 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4045 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4046 RT5677_I2S_DL_MASK, val_len);
4047 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4048 mask_clk, val_clk);
4049 break;
4050 case RT5677_AIF3:
4051 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4052 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4053 pre_div << RT5677_I2S_PD3_SFT;
4054 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4055 RT5677_I2S_DL_MASK, val_len);
4056 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4057 mask_clk, val_clk);
4058 break;
4059 case RT5677_AIF4:
4060 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4061 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4062 pre_div << RT5677_I2S_PD4_SFT;
4063 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4064 RT5677_I2S_DL_MASK, val_len);
4065 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4066 mask_clk, val_clk);
4067 break;
4068 default:
4069 break;
4070 }
4071
4072 return 0;
4073 }
4074
4075 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4076 {
4077 struct snd_soc_codec *codec = dai->codec;
4078 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4079 unsigned int reg_val = 0;
4080
4081 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4082 case SND_SOC_DAIFMT_CBM_CFM:
4083 rt5677->master[dai->id] = 1;
4084 break;
4085 case SND_SOC_DAIFMT_CBS_CFS:
4086 reg_val |= RT5677_I2S_MS_S;
4087 rt5677->master[dai->id] = 0;
4088 break;
4089 default:
4090 return -EINVAL;
4091 }
4092
4093 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4094 case SND_SOC_DAIFMT_NB_NF:
4095 break;
4096 case SND_SOC_DAIFMT_IB_NF:
4097 reg_val |= RT5677_I2S_BP_INV;
4098 break;
4099 default:
4100 return -EINVAL;
4101 }
4102
4103 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4104 case SND_SOC_DAIFMT_I2S:
4105 break;
4106 case SND_SOC_DAIFMT_LEFT_J:
4107 reg_val |= RT5677_I2S_DF_LEFT;
4108 break;
4109 case SND_SOC_DAIFMT_DSP_A:
4110 reg_val |= RT5677_I2S_DF_PCM_A;
4111 break;
4112 case SND_SOC_DAIFMT_DSP_B:
4113 reg_val |= RT5677_I2S_DF_PCM_B;
4114 break;
4115 default:
4116 return -EINVAL;
4117 }
4118
4119 switch (dai->id) {
4120 case RT5677_AIF1:
4121 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4122 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4123 RT5677_I2S_DF_MASK, reg_val);
4124 break;
4125 case RT5677_AIF2:
4126 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4127 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4128 RT5677_I2S_DF_MASK, reg_val);
4129 break;
4130 case RT5677_AIF3:
4131 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4132 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4133 RT5677_I2S_DF_MASK, reg_val);
4134 break;
4135 case RT5677_AIF4:
4136 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4137 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4138 RT5677_I2S_DF_MASK, reg_val);
4139 break;
4140 default:
4141 break;
4142 }
4143
4144
4145 return 0;
4146 }
4147
4148 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4149 int clk_id, unsigned int freq, int dir)
4150 {
4151 struct snd_soc_codec *codec = dai->codec;
4152 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4153 unsigned int reg_val = 0;
4154
4155 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4156 return 0;
4157
4158 switch (clk_id) {
4159 case RT5677_SCLK_S_MCLK:
4160 reg_val |= RT5677_SCLK_SRC_MCLK;
4161 break;
4162 case RT5677_SCLK_S_PLL1:
4163 reg_val |= RT5677_SCLK_SRC_PLL1;
4164 break;
4165 case RT5677_SCLK_S_RCCLK:
4166 reg_val |= RT5677_SCLK_SRC_RCCLK;
4167 break;
4168 default:
4169 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4170 return -EINVAL;
4171 }
4172 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4173 RT5677_SCLK_SRC_MASK, reg_val);
4174 rt5677->sysclk = freq;
4175 rt5677->sysclk_src = clk_id;
4176
4177 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4178
4179 return 0;
4180 }
4181
4182 /**
4183 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4184 * @freq_in: external clock provided to codec.
4185 * @freq_out: target clock which codec works on.
4186 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4187 *
4188 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4189 *
4190 * Returns 0 for success or negative error code.
4191 */
4192 static int rt5677_pll_calc(const unsigned int freq_in,
4193 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4194 {
4195 if (RT5677_PLL_INP_MIN > freq_in)
4196 return -EINVAL;
4197
4198 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4199 }
4200
4201 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4202 unsigned int freq_in, unsigned int freq_out)
4203 {
4204 struct snd_soc_codec *codec = dai->codec;
4205 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4206 struct rl6231_pll_code pll_code;
4207 int ret;
4208
4209 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4210 freq_out == rt5677->pll_out)
4211 return 0;
4212
4213 if (!freq_in || !freq_out) {
4214 dev_dbg(codec->dev, "PLL disabled\n");
4215
4216 rt5677->pll_in = 0;
4217 rt5677->pll_out = 0;
4218 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4219 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4220 return 0;
4221 }
4222
4223 switch (source) {
4224 case RT5677_PLL1_S_MCLK:
4225 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4226 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4227 break;
4228 case RT5677_PLL1_S_BCLK1:
4229 case RT5677_PLL1_S_BCLK2:
4230 case RT5677_PLL1_S_BCLK3:
4231 case RT5677_PLL1_S_BCLK4:
4232 switch (dai->id) {
4233 case RT5677_AIF1:
4234 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4235 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4236 break;
4237 case RT5677_AIF2:
4238 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4239 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4240 break;
4241 case RT5677_AIF3:
4242 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4243 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4244 break;
4245 case RT5677_AIF4:
4246 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4247 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4248 break;
4249 default:
4250 break;
4251 }
4252 break;
4253 default:
4254 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4255 return -EINVAL;
4256 }
4257
4258 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4259 if (ret < 0) {
4260 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4261 return ret;
4262 }
4263
4264 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4265 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4266 pll_code.n_code, pll_code.k_code);
4267
4268 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4269 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4270 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4271 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4272 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4273
4274 rt5677->pll_in = freq_in;
4275 rt5677->pll_out = freq_out;
4276 rt5677->pll_src = source;
4277
4278 return 0;
4279 }
4280
4281 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4282 unsigned int rx_mask, int slots, int slot_width)
4283 {
4284 struct snd_soc_codec *codec = dai->codec;
4285 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4286 unsigned int val = 0, slot_width_25 = 0;
4287
4288 if (rx_mask || tx_mask)
4289 val |= (1 << 12);
4290
4291 switch (slots) {
4292 case 4:
4293 val |= (1 << 10);
4294 break;
4295 case 6:
4296 val |= (2 << 10);
4297 break;
4298 case 8:
4299 val |= (3 << 10);
4300 break;
4301 case 2:
4302 default:
4303 break;
4304 }
4305
4306 switch (slot_width) {
4307 case 20:
4308 val |= (1 << 8);
4309 break;
4310 case 25:
4311 slot_width_25 = 0x8080;
4312 case 24:
4313 val |= (2 << 8);
4314 break;
4315 case 32:
4316 val |= (3 << 8);
4317 break;
4318 case 16:
4319 default:
4320 break;
4321 }
4322
4323 switch (dai->id) {
4324 case RT5677_AIF1:
4325 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4326 val);
4327 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4328 slot_width_25);
4329 break;
4330 case RT5677_AIF2:
4331 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4332 val);
4333 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4334 slot_width_25);
4335 break;
4336 default:
4337 break;
4338 }
4339
4340 return 0;
4341 }
4342
4343 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4344 enum snd_soc_bias_level level)
4345 {
4346 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4347
4348 switch (level) {
4349 case SND_SOC_BIAS_ON:
4350 break;
4351
4352 case SND_SOC_BIAS_PREPARE:
4353 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
4354 rt5677_set_dsp_vad(codec, false);
4355
4356 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4357 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4358 0x0055);
4359 regmap_update_bits(rt5677->regmap,
4360 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4361 0x0f00, 0x0f00);
4362 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4363 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4364 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4365 RT5677_PWR_BG | RT5677_PWR_VREF2,
4366 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4367 RT5677_PWR_BG | RT5677_PWR_VREF2);
4368 rt5677->is_vref_slow = false;
4369 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4370 RT5677_PWR_CORE, RT5677_PWR_CORE);
4371 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4372 0x1, 0x1);
4373 }
4374 break;
4375
4376 case SND_SOC_BIAS_STANDBY:
4377 break;
4378
4379 case SND_SOC_BIAS_OFF:
4380 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4381 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4382 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4383 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4384 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4385 regmap_update_bits(rt5677->regmap,
4386 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4387
4388 if (rt5677->dsp_vad_en)
4389 rt5677_set_dsp_vad(codec, true);
4390 break;
4391
4392 default:
4393 break;
4394 }
4395 codec->dapm.bias_level = level;
4396
4397 return 0;
4398 }
4399
4400 #ifdef CONFIG_GPIOLIB
4401 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4402 {
4403 return container_of(chip, struct rt5677_priv, gpio_chip);
4404 }
4405
4406 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4407 {
4408 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4409
4410 switch (offset) {
4411 case RT5677_GPIO1 ... RT5677_GPIO5:
4412 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4413 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4414 break;
4415
4416 case RT5677_GPIO6:
4417 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4418 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4419 break;
4420
4421 default:
4422 break;
4423 }
4424 }
4425
4426 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4427 unsigned offset, int value)
4428 {
4429 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4430
4431 switch (offset) {
4432 case RT5677_GPIO1 ... RT5677_GPIO5:
4433 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4434 0x3 << (offset * 3 + 1),
4435 (0x2 | !!value) << (offset * 3 + 1));
4436 break;
4437
4438 case RT5677_GPIO6:
4439 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4440 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4441 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4442 break;
4443
4444 default:
4445 break;
4446 }
4447
4448 return 0;
4449 }
4450
4451 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4452 {
4453 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4454 int value, ret;
4455
4456 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4457 if (ret < 0)
4458 return ret;
4459
4460 return (value & (0x1 << offset)) >> offset;
4461 }
4462
4463 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4464 {
4465 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4466
4467 switch (offset) {
4468 case RT5677_GPIO1 ... RT5677_GPIO5:
4469 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4470 0x1 << (offset * 3 + 2), 0x0);
4471 break;
4472
4473 case RT5677_GPIO6:
4474 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4475 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4476 break;
4477
4478 default:
4479 break;
4480 }
4481
4482 return 0;
4483 }
4484
4485 /** Configures the gpio as
4486 * 0 - floating
4487 * 1 - pull down
4488 * 2 - pull up
4489 */
4490 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4491 int value)
4492 {
4493 int shift;
4494
4495 switch (offset) {
4496 case RT5677_GPIO1 ... RT5677_GPIO2:
4497 shift = 2 * (1 - offset);
4498 regmap_update_bits(rt5677->regmap,
4499 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4500 0x3 << shift,
4501 (value & 0x3) << shift);
4502 break;
4503
4504 case RT5677_GPIO3 ... RT5677_GPIO6:
4505 shift = 2 * (9 - offset);
4506 regmap_update_bits(rt5677->regmap,
4507 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4508 0x3 << shift,
4509 (value & 0x3) << shift);
4510 break;
4511
4512 default:
4513 break;
4514 }
4515 }
4516
4517 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4518 {
4519 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4520 struct regmap_irq_chip_data *data = rt5677->irq_data;
4521 int irq;
4522
4523 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4524 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4525 (rt5677->pdata.jd1_gpio == 2 &&
4526 offset == RT5677_GPIO2) ||
4527 (rt5677->pdata.jd1_gpio == 3 &&
4528 offset == RT5677_GPIO3)) {
4529 irq = RT5677_IRQ_JD1;
4530 } else {
4531 return -ENXIO;
4532 }
4533 }
4534
4535 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4536 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4537 (rt5677->pdata.jd2_gpio == 2 &&
4538 offset == RT5677_GPIO5) ||
4539 (rt5677->pdata.jd2_gpio == 3 &&
4540 offset == RT5677_GPIO6)) {
4541 irq = RT5677_IRQ_JD2;
4542 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4543 offset == RT5677_GPIO4) ||
4544 (rt5677->pdata.jd3_gpio == 2 &&
4545 offset == RT5677_GPIO5) ||
4546 (rt5677->pdata.jd3_gpio == 3 &&
4547 offset == RT5677_GPIO6)) {
4548 irq = RT5677_IRQ_JD3;
4549 } else {
4550 return -ENXIO;
4551 }
4552 }
4553
4554 return regmap_irq_get_virq(data, irq);
4555 }
4556
4557 static struct gpio_chip rt5677_template_chip = {
4558 .label = "rt5677",
4559 .owner = THIS_MODULE,
4560 .direction_output = rt5677_gpio_direction_out,
4561 .set = rt5677_gpio_set,
4562 .direction_input = rt5677_gpio_direction_in,
4563 .get = rt5677_gpio_get,
4564 .to_irq = rt5677_to_irq,
4565 .can_sleep = 1,
4566 };
4567
4568 static void rt5677_init_gpio(struct i2c_client *i2c)
4569 {
4570 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4571 int ret;
4572
4573 rt5677->gpio_chip = rt5677_template_chip;
4574 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4575 rt5677->gpio_chip.dev = &i2c->dev;
4576 rt5677->gpio_chip.base = -1;
4577
4578 ret = gpiochip_add(&rt5677->gpio_chip);
4579 if (ret != 0)
4580 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4581 }
4582
4583 static void rt5677_free_gpio(struct i2c_client *i2c)
4584 {
4585 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4586
4587 gpiochip_remove(&rt5677->gpio_chip);
4588 }
4589 #else
4590 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4591 int value)
4592 {
4593 }
4594
4595 static void rt5677_init_gpio(struct i2c_client *i2c)
4596 {
4597 }
4598
4599 static void rt5677_free_gpio(struct i2c_client *i2c)
4600 {
4601 }
4602 #endif
4603
4604 static int rt5677_probe(struct snd_soc_codec *codec)
4605 {
4606 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4607 int i;
4608
4609 rt5677->codec = codec;
4610
4611 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4612 snd_soc_dapm_add_routes(&codec->dapm,
4613 rt5677_dmic2_clk_2,
4614 ARRAY_SIZE(rt5677_dmic2_clk_2));
4615 } else { /*use dmic1 clock by default*/
4616 snd_soc_dapm_add_routes(&codec->dapm,
4617 rt5677_dmic2_clk_1,
4618 ARRAY_SIZE(rt5677_dmic2_clk_1));
4619 }
4620
4621 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4622
4623 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4624 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4625
4626 for (i = 0; i < RT5677_GPIO_NUM; i++)
4627 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4628
4629 if (rt5677->irq_data) {
4630 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4631 0x8000);
4632 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4633 0x0008);
4634
4635 if (rt5677->pdata.jd1_gpio)
4636 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4637 RT5677_SEL_GPIO_JD1_MASK,
4638 rt5677->pdata.jd1_gpio <<
4639 RT5677_SEL_GPIO_JD1_SFT);
4640
4641 if (rt5677->pdata.jd2_gpio)
4642 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4643 RT5677_SEL_GPIO_JD2_MASK,
4644 rt5677->pdata.jd2_gpio <<
4645 RT5677_SEL_GPIO_JD2_SFT);
4646
4647 if (rt5677->pdata.jd3_gpio)
4648 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4649 RT5677_SEL_GPIO_JD3_MASK,
4650 rt5677->pdata.jd3_gpio <<
4651 RT5677_SEL_GPIO_JD3_SFT);
4652 }
4653
4654 mutex_init(&rt5677->dsp_cmd_lock);
4655 mutex_init(&rt5677->dsp_pri_lock);
4656
4657 return 0;
4658 }
4659
4660 static int rt5677_remove(struct snd_soc_codec *codec)
4661 {
4662 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4663
4664 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4665 if (gpio_is_valid(rt5677->pow_ldo2))
4666 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4667
4668 return 0;
4669 }
4670
4671 #ifdef CONFIG_PM
4672 static int rt5677_suspend(struct snd_soc_codec *codec)
4673 {
4674 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4675
4676 if (!rt5677->dsp_vad_en) {
4677 regcache_cache_only(rt5677->regmap, true);
4678 regcache_mark_dirty(rt5677->regmap);
4679
4680 if (gpio_is_valid(rt5677->pow_ldo2))
4681 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4682 }
4683
4684 return 0;
4685 }
4686
4687 static int rt5677_resume(struct snd_soc_codec *codec)
4688 {
4689 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4690
4691 if (!rt5677->dsp_vad_en) {
4692 if (gpio_is_valid(rt5677->pow_ldo2)) {
4693 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4694 msleep(10);
4695 }
4696
4697 regcache_cache_only(rt5677->regmap, false);
4698 regcache_sync(rt5677->regmap);
4699 }
4700
4701 return 0;
4702 }
4703 #else
4704 #define rt5677_suspend NULL
4705 #define rt5677_resume NULL
4706 #endif
4707
4708 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4709 {
4710 struct i2c_client *client = context;
4711 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4712
4713 if (rt5677->is_dsp_mode) {
4714 if (reg > 0xff) {
4715 mutex_lock(&rt5677->dsp_pri_lock);
4716 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4717 reg & 0xff);
4718 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4719 mutex_unlock(&rt5677->dsp_pri_lock);
4720 } else {
4721 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4722 }
4723 } else {
4724 regmap_read(rt5677->regmap_physical, reg, val);
4725 }
4726
4727 return 0;
4728 }
4729
4730 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4731 {
4732 struct i2c_client *client = context;
4733 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4734
4735 if (rt5677->is_dsp_mode) {
4736 if (reg > 0xff) {
4737 mutex_lock(&rt5677->dsp_pri_lock);
4738 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4739 reg & 0xff);
4740 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4741 val);
4742 mutex_unlock(&rt5677->dsp_pri_lock);
4743 } else {
4744 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4745 }
4746 } else {
4747 regmap_write(rt5677->regmap_physical, reg, val);
4748 }
4749
4750 return 0;
4751 }
4752
4753 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4754 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4755 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4756
4757 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4758 .hw_params = rt5677_hw_params,
4759 .set_fmt = rt5677_set_dai_fmt,
4760 .set_sysclk = rt5677_set_dai_sysclk,
4761 .set_pll = rt5677_set_dai_pll,
4762 .set_tdm_slot = rt5677_set_tdm_slot,
4763 };
4764
4765 static struct snd_soc_dai_driver rt5677_dai[] = {
4766 {
4767 .name = "rt5677-aif1",
4768 .id = RT5677_AIF1,
4769 .playback = {
4770 .stream_name = "AIF1 Playback",
4771 .channels_min = 1,
4772 .channels_max = 2,
4773 .rates = RT5677_STEREO_RATES,
4774 .formats = RT5677_FORMATS,
4775 },
4776 .capture = {
4777 .stream_name = "AIF1 Capture",
4778 .channels_min = 1,
4779 .channels_max = 2,
4780 .rates = RT5677_STEREO_RATES,
4781 .formats = RT5677_FORMATS,
4782 },
4783 .ops = &rt5677_aif_dai_ops,
4784 },
4785 {
4786 .name = "rt5677-aif2",
4787 .id = RT5677_AIF2,
4788 .playback = {
4789 .stream_name = "AIF2 Playback",
4790 .channels_min = 1,
4791 .channels_max = 2,
4792 .rates = RT5677_STEREO_RATES,
4793 .formats = RT5677_FORMATS,
4794 },
4795 .capture = {
4796 .stream_name = "AIF2 Capture",
4797 .channels_min = 1,
4798 .channels_max = 2,
4799 .rates = RT5677_STEREO_RATES,
4800 .formats = RT5677_FORMATS,
4801 },
4802 .ops = &rt5677_aif_dai_ops,
4803 },
4804 {
4805 .name = "rt5677-aif3",
4806 .id = RT5677_AIF3,
4807 .playback = {
4808 .stream_name = "AIF3 Playback",
4809 .channels_min = 1,
4810 .channels_max = 2,
4811 .rates = RT5677_STEREO_RATES,
4812 .formats = RT5677_FORMATS,
4813 },
4814 .capture = {
4815 .stream_name = "AIF3 Capture",
4816 .channels_min = 1,
4817 .channels_max = 2,
4818 .rates = RT5677_STEREO_RATES,
4819 .formats = RT5677_FORMATS,
4820 },
4821 .ops = &rt5677_aif_dai_ops,
4822 },
4823 {
4824 .name = "rt5677-aif4",
4825 .id = RT5677_AIF4,
4826 .playback = {
4827 .stream_name = "AIF4 Playback",
4828 .channels_min = 1,
4829 .channels_max = 2,
4830 .rates = RT5677_STEREO_RATES,
4831 .formats = RT5677_FORMATS,
4832 },
4833 .capture = {
4834 .stream_name = "AIF4 Capture",
4835 .channels_min = 1,
4836 .channels_max = 2,
4837 .rates = RT5677_STEREO_RATES,
4838 .formats = RT5677_FORMATS,
4839 },
4840 .ops = &rt5677_aif_dai_ops,
4841 },
4842 {
4843 .name = "rt5677-slimbus",
4844 .id = RT5677_AIF5,
4845 .playback = {
4846 .stream_name = "SLIMBus Playback",
4847 .channels_min = 1,
4848 .channels_max = 2,
4849 .rates = RT5677_STEREO_RATES,
4850 .formats = RT5677_FORMATS,
4851 },
4852 .capture = {
4853 .stream_name = "SLIMBus Capture",
4854 .channels_min = 1,
4855 .channels_max = 2,
4856 .rates = RT5677_STEREO_RATES,
4857 .formats = RT5677_FORMATS,
4858 },
4859 .ops = &rt5677_aif_dai_ops,
4860 },
4861 };
4862
4863 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4864 .probe = rt5677_probe,
4865 .remove = rt5677_remove,
4866 .suspend = rt5677_suspend,
4867 .resume = rt5677_resume,
4868 .set_bias_level = rt5677_set_bias_level,
4869 .idle_bias_off = true,
4870 .controls = rt5677_snd_controls,
4871 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4872 .dapm_widgets = rt5677_dapm_widgets,
4873 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4874 .dapm_routes = rt5677_dapm_routes,
4875 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4876 };
4877
4878 static const struct regmap_config rt5677_regmap_physical = {
4879 .name = "physical",
4880 .reg_bits = 8,
4881 .val_bits = 16,
4882
4883 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4884 RT5677_PR_SPACING),
4885 .readable_reg = rt5677_readable_register,
4886
4887 .cache_type = REGCACHE_NONE,
4888 .ranges = rt5677_ranges,
4889 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4890 };
4891
4892 static const struct regmap_config rt5677_regmap = {
4893 .reg_bits = 8,
4894 .val_bits = 16,
4895
4896 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4897 RT5677_PR_SPACING),
4898
4899 .volatile_reg = rt5677_volatile_register,
4900 .readable_reg = rt5677_readable_register,
4901 .reg_read = rt5677_read,
4902 .reg_write = rt5677_write,
4903
4904 .cache_type = REGCACHE_RBTREE,
4905 .reg_defaults = rt5677_reg,
4906 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4907 .ranges = rt5677_ranges,
4908 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4909 };
4910
4911 static const struct i2c_device_id rt5677_i2c_id[] = {
4912 { "rt5677", RT5677 },
4913 { "rt5676", RT5676 },
4914 { }
4915 };
4916 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4917
4918 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4919 {
4920 rt5677->pdata.in1_diff = of_property_read_bool(np,
4921 "realtek,in1-differential");
4922 rt5677->pdata.in2_diff = of_property_read_bool(np,
4923 "realtek,in2-differential");
4924 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4925 "realtek,lout1-differential");
4926 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4927 "realtek,lout2-differential");
4928 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4929 "realtek,lout3-differential");
4930
4931 rt5677->pow_ldo2 = of_get_named_gpio(np,
4932 "realtek,pow-ldo2-gpio", 0);
4933
4934 /*
4935 * POW_LDO2 is optional (it may be statically tied on the board).
4936 * -ENOENT means that the property doesn't exist, i.e. there is no
4937 * GPIO, so is not an error. Any other error code means the property
4938 * exists, but could not be parsed.
4939 */
4940 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4941 (rt5677->pow_ldo2 != -ENOENT))
4942 return rt5677->pow_ldo2;
4943
4944 of_property_read_u8_array(np, "realtek,gpio-config",
4945 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4946
4947 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4948 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4949 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4950
4951 return 0;
4952 }
4953
4954 static struct regmap_irq rt5677_irqs[] = {
4955 [RT5677_IRQ_JD1] = {
4956 .reg_offset = 0,
4957 .mask = RT5677_EN_IRQ_GPIO_JD1,
4958 },
4959 [RT5677_IRQ_JD2] = {
4960 .reg_offset = 0,
4961 .mask = RT5677_EN_IRQ_GPIO_JD2,
4962 },
4963 [RT5677_IRQ_JD3] = {
4964 .reg_offset = 0,
4965 .mask = RT5677_EN_IRQ_GPIO_JD3,
4966 },
4967 };
4968
4969 static struct regmap_irq_chip rt5677_irq_chip = {
4970 .name = "rt5677",
4971 .irqs = rt5677_irqs,
4972 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4973
4974 .num_regs = 1,
4975 .status_base = RT5677_IRQ_CTRL1,
4976 .mask_base = RT5677_IRQ_CTRL1,
4977 .mask_invert = 1,
4978 };
4979
4980 static int rt5677_init_irq(struct i2c_client *i2c)
4981 {
4982 int ret;
4983 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4984
4985 if (!rt5677->pdata.jd1_gpio &&
4986 !rt5677->pdata.jd2_gpio &&
4987 !rt5677->pdata.jd3_gpio)
4988 return 0;
4989
4990 if (!i2c->irq) {
4991 dev_err(&i2c->dev, "No interrupt specified\n");
4992 return -EINVAL;
4993 }
4994
4995 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4996 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4997 &rt5677_irq_chip, &rt5677->irq_data);
4998
4999 if (ret != 0) {
5000 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5001 return ret;
5002 }
5003
5004 return 0;
5005 }
5006
5007 static void rt5677_free_irq(struct i2c_client *i2c)
5008 {
5009 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5010
5011 if (rt5677->irq_data)
5012 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5013 }
5014
5015 static int rt5677_i2c_probe(struct i2c_client *i2c,
5016 const struct i2c_device_id *id)
5017 {
5018 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5019 struct rt5677_priv *rt5677;
5020 int ret;
5021 unsigned int val;
5022
5023 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5024 GFP_KERNEL);
5025 if (rt5677 == NULL)
5026 return -ENOMEM;
5027
5028 i2c_set_clientdata(i2c, rt5677);
5029
5030 rt5677->type = id->driver_data;
5031
5032 if (pdata)
5033 rt5677->pdata = *pdata;
5034
5035 if (i2c->dev.of_node) {
5036 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
5037 if (ret) {
5038 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
5039 ret);
5040 return ret;
5041 }
5042 } else {
5043 rt5677->pow_ldo2 = -EINVAL;
5044 }
5045
5046 if (gpio_is_valid(rt5677->pow_ldo2)) {
5047 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
5048 GPIOF_OUT_INIT_HIGH,
5049 "RT5677 POW_LDO2");
5050 if (ret < 0) {
5051 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
5052 rt5677->pow_ldo2, ret);
5053 return ret;
5054 }
5055 /* Wait a while until I2C bus becomes available. The datasheet
5056 * does not specify the exact we should wait but startup
5057 * sequence mentiones at least a few milliseconds.
5058 */
5059 msleep(10);
5060 }
5061
5062 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5063 &rt5677_regmap_physical);
5064 if (IS_ERR(rt5677->regmap_physical)) {
5065 ret = PTR_ERR(rt5677->regmap_physical);
5066 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5067 ret);
5068 return ret;
5069 }
5070
5071 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5072 if (IS_ERR(rt5677->regmap)) {
5073 ret = PTR_ERR(rt5677->regmap);
5074 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5075 ret);
5076 return ret;
5077 }
5078
5079 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5080 if (val != RT5677_DEVICE_ID) {
5081 dev_err(&i2c->dev,
5082 "Device with ID register %x is not rt5677\n", val);
5083 return -ENODEV;
5084 }
5085
5086 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5087
5088 ret = regmap_register_patch(rt5677->regmap, init_list,
5089 ARRAY_SIZE(init_list));
5090 if (ret != 0)
5091 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5092
5093 if (rt5677->pdata.in1_diff)
5094 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5095 RT5677_IN_DF1, RT5677_IN_DF1);
5096
5097 if (rt5677->pdata.in2_diff)
5098 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5099 RT5677_IN_DF2, RT5677_IN_DF2);
5100
5101 if (rt5677->pdata.lout1_diff)
5102 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5103 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5104
5105 if (rt5677->pdata.lout2_diff)
5106 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5107 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5108
5109 if (rt5677->pdata.lout3_diff)
5110 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5111 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5112
5113 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5114 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5115 RT5677_GPIO5_FUNC_MASK,
5116 RT5677_GPIO5_FUNC_DMIC);
5117 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5118 RT5677_GPIO5_DIR_MASK,
5119 RT5677_GPIO5_DIR_OUT);
5120 }
5121
5122 if (rt5677->pdata.micbias1_vdd_3v3)
5123 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5124 RT5677_MICBIAS1_CTRL_VDD_MASK,
5125 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5126
5127 rt5677_init_gpio(i2c);
5128 rt5677_init_irq(i2c);
5129
5130 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5131 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5132 }
5133
5134 static int rt5677_i2c_remove(struct i2c_client *i2c)
5135 {
5136 snd_soc_unregister_codec(&i2c->dev);
5137 rt5677_free_irq(i2c);
5138 rt5677_free_gpio(i2c);
5139
5140 return 0;
5141 }
5142
5143 static struct i2c_driver rt5677_i2c_driver = {
5144 .driver = {
5145 .name = "rt5677",
5146 .owner = THIS_MODULE,
5147 },
5148 .probe = rt5677_i2c_probe,
5149 .remove = rt5677_i2c_remove,
5150 .id_table = rt5677_i2c_id,
5151 };
5152 module_i2c_driver(rt5677_i2c_driver);
5153
5154 MODULE_DESCRIPTION("ASoC RT5677 driver");
5155 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5156 MODULE_LICENSE("GPL v2");
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