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ASoC: codecs: add const to snd_soc_codec_driver structures
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / rt5677.c
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/acpi.h>
13 #include <linux/fs.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/property.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "rl6231.h"
34 #include "rt5677.h"
35 #include "rt5677-spi.h"
36
37 #define RT5677_DEVICE_ID 0x6327
38
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
41
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44 static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55 };
56
57 static const struct reg_sequence init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
65 {RT5677_PR_BASE + 0x15, 0x0490},
66 {RT5677_PR_BASE + 0x38, 0x0f71},
67 {RT5677_PR_BASE + 0x39, 0x0f71},
68 };
69 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
70
71 static const struct reg_default rt5677_reg[] = {
72 {RT5677_RESET , 0x0000},
73 {RT5677_LOUT1 , 0xa800},
74 {RT5677_IN1 , 0x0000},
75 {RT5677_MICBIAS , 0x0000},
76 {RT5677_SLIMBUS_PARAM , 0x0000},
77 {RT5677_SLIMBUS_RX , 0x0000},
78 {RT5677_SLIMBUS_CTRL , 0x0000},
79 {RT5677_SIDETONE_CTRL , 0x000b},
80 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
81 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
82 {RT5677_DAC4_DIG_VOL , 0xafaf},
83 {RT5677_DAC3_DIG_VOL , 0xafaf},
84 {RT5677_DAC1_DIG_VOL , 0xafaf},
85 {RT5677_DAC2_DIG_VOL , 0xafaf},
86 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
87 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
89 {RT5677_STO1_2_ADC_BST , 0x0000},
90 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_ADC_BST_CTRL2 , 0x0000},
92 {RT5677_STO3_4_ADC_BST , 0x0000},
93 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
95 {RT5677_STO4_ADC_MIXER , 0xd4c0},
96 {RT5677_STO3_ADC_MIXER , 0xd4c0},
97 {RT5677_STO2_ADC_MIXER , 0xd4c0},
98 {RT5677_STO1_ADC_MIXER , 0xd4c0},
99 {RT5677_MONO_ADC_MIXER , 0xd4d1},
100 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
101 {RT5677_STO1_DAC_MIXER , 0xaaaa},
102 {RT5677_MONO_DAC_MIXER , 0xaaaa},
103 {RT5677_DD1_MIXER , 0xaaaa},
104 {RT5677_DD2_MIXER , 0xaaaa},
105 {RT5677_IF3_DATA , 0x0000},
106 {RT5677_IF4_DATA , 0x0000},
107 {RT5677_PDM_OUT_CTRL , 0x8888},
108 {RT5677_PDM_DATA_CTRL1 , 0x0000},
109 {RT5677_PDM_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
115 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
116 {RT5677_TDM1_CTRL1 , 0x0300},
117 {RT5677_TDM1_CTRL2 , 0x0000},
118 {RT5677_TDM1_CTRL3 , 0x4000},
119 {RT5677_TDM1_CTRL4 , 0x0123},
120 {RT5677_TDM1_CTRL5 , 0x4567},
121 {RT5677_TDM2_CTRL1 , 0x0300},
122 {RT5677_TDM2_CTRL2 , 0x0000},
123 {RT5677_TDM2_CTRL3 , 0x4000},
124 {RT5677_TDM2_CTRL4 , 0x0123},
125 {RT5677_TDM2_CTRL5 , 0x4567},
126 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
127 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
133 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
134 {RT5677_DMIC_CTRL1 , 0x1505},
135 {RT5677_DMIC_CTRL2 , 0x0055},
136 {RT5677_HAP_GENE_CTRL1 , 0x0111},
137 {RT5677_HAP_GENE_CTRL2 , 0x0064},
138 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
139 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
140 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
141 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
142 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
143 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
144 {RT5677_HAP_GENE_CTRL9 , 0xf000},
145 {RT5677_HAP_GENE_CTRL10 , 0x0000},
146 {RT5677_PWR_DIG1 , 0x0000},
147 {RT5677_PWR_DIG2 , 0x0000},
148 {RT5677_PWR_ANLG1 , 0x0055},
149 {RT5677_PWR_ANLG2 , 0x0000},
150 {RT5677_PWR_DSP1 , 0x0001},
151 {RT5677_PWR_DSP_ST , 0x0000},
152 {RT5677_PWR_DSP2 , 0x0000},
153 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
154 {RT5677_PRIV_INDEX , 0x0000},
155 {RT5677_PRIV_DATA , 0x0000},
156 {RT5677_I2S4_SDP , 0x8000},
157 {RT5677_I2S1_SDP , 0x8000},
158 {RT5677_I2S2_SDP , 0x8000},
159 {RT5677_I2S3_SDP , 0x8000},
160 {RT5677_CLK_TREE_CTRL1 , 0x1111},
161 {RT5677_CLK_TREE_CTRL2 , 0x1111},
162 {RT5677_CLK_TREE_CTRL3 , 0x0000},
163 {RT5677_PLL1_CTRL1 , 0x0000},
164 {RT5677_PLL1_CTRL2 , 0x0000},
165 {RT5677_PLL2_CTRL1 , 0x0c60},
166 {RT5677_PLL2_CTRL2 , 0x2000},
167 {RT5677_GLB_CLK1 , 0x0000},
168 {RT5677_GLB_CLK2 , 0x0000},
169 {RT5677_ASRC_1 , 0x0000},
170 {RT5677_ASRC_2 , 0x0000},
171 {RT5677_ASRC_3 , 0x0000},
172 {RT5677_ASRC_4 , 0x0000},
173 {RT5677_ASRC_5 , 0x0000},
174 {RT5677_ASRC_6 , 0x0000},
175 {RT5677_ASRC_7 , 0x0000},
176 {RT5677_ASRC_8 , 0x0000},
177 {RT5677_ASRC_9 , 0x0000},
178 {RT5677_ASRC_10 , 0x0000},
179 {RT5677_ASRC_11 , 0x0000},
180 {RT5677_ASRC_12 , 0x0018},
181 {RT5677_ASRC_13 , 0x0000},
182 {RT5677_ASRC_14 , 0x0000},
183 {RT5677_ASRC_15 , 0x0000},
184 {RT5677_ASRC_16 , 0x0000},
185 {RT5677_ASRC_17 , 0x0000},
186 {RT5677_ASRC_18 , 0x0000},
187 {RT5677_ASRC_19 , 0x0000},
188 {RT5677_ASRC_20 , 0x0000},
189 {RT5677_ASRC_21 , 0x000c},
190 {RT5677_ASRC_22 , 0x0000},
191 {RT5677_ASRC_23 , 0x0000},
192 {RT5677_VAD_CTRL1 , 0x2184},
193 {RT5677_VAD_CTRL2 , 0x010a},
194 {RT5677_VAD_CTRL3 , 0x0aea},
195 {RT5677_VAD_CTRL4 , 0x000c},
196 {RT5677_VAD_CTRL5 , 0x0000},
197 {RT5677_DSP_INB_CTRL1 , 0x0000},
198 {RT5677_DSP_INB_CTRL2 , 0x0000},
199 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
200 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
203 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
204 {RT5677_ADC_EQ_CTRL1 , 0x6000},
205 {RT5677_ADC_EQ_CTRL2 , 0x0000},
206 {RT5677_EQ_CTRL1 , 0xc000},
207 {RT5677_EQ_CTRL2 , 0x0000},
208 {RT5677_EQ_CTRL3 , 0x0000},
209 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
210 {RT5677_JD_CTRL1 , 0x0000},
211 {RT5677_JD_CTRL2 , 0x0000},
212 {RT5677_JD_CTRL3 , 0x0000},
213 {RT5677_IRQ_CTRL1 , 0x0000},
214 {RT5677_IRQ_CTRL2 , 0x0000},
215 {RT5677_GPIO_ST , 0x0000},
216 {RT5677_GPIO_CTRL1 , 0x0000},
217 {RT5677_GPIO_CTRL2 , 0x0000},
218 {RT5677_GPIO_CTRL3 , 0x0000},
219 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
220 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
226 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
227 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
228 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
229 {RT5677_MB_DRC_CTRL1 , 0x0f20},
230 {RT5677_DRC1_CTRL1 , 0x001f},
231 {RT5677_DRC1_CTRL2 , 0x020c},
232 {RT5677_DRC1_CTRL3 , 0x1f00},
233 {RT5677_DRC1_CTRL4 , 0x0000},
234 {RT5677_DRC1_CTRL5 , 0x0000},
235 {RT5677_DRC1_CTRL6 , 0x0029},
236 {RT5677_DRC2_CTRL1 , 0x001f},
237 {RT5677_DRC2_CTRL2 , 0x020c},
238 {RT5677_DRC2_CTRL3 , 0x1f00},
239 {RT5677_DRC2_CTRL4 , 0x0000},
240 {RT5677_DRC2_CTRL5 , 0x0000},
241 {RT5677_DRC2_CTRL6 , 0x0029},
242 {RT5677_DRC1_HL_CTRL1 , 0x8000},
243 {RT5677_DRC1_HL_CTRL2 , 0x0200},
244 {RT5677_DRC2_HL_CTRL1 , 0x8000},
245 {RT5677_DRC2_HL_CTRL2 , 0x0200},
246 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
247 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
249 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
250 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
251 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
253 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
254 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
255 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
257 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
258 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
259 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
261 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
262 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
263 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
265 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
266 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
267 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
268 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
269 {RT5677_DIG_MISC , 0x0000},
270 {RT5677_GEN_CTRL1 , 0x0000},
271 {RT5677_GEN_CTRL2 , 0x0000},
272 {RT5677_VENDOR_ID , 0x0000},
273 {RT5677_VENDOR_ID1 , 0x10ec},
274 {RT5677_VENDOR_ID2 , 0x6327},
275 };
276
277 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
278 {
279 int i;
280
281 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
282 if (reg >= rt5677_ranges[i].range_min &&
283 reg <= rt5677_ranges[i].range_max) {
284 return true;
285 }
286 }
287
288 switch (reg) {
289 case RT5677_RESET:
290 case RT5677_SLIMBUS_PARAM:
291 case RT5677_PDM_DATA_CTRL1:
292 case RT5677_PDM_DATA_CTRL2:
293 case RT5677_PDM1_DATA_CTRL4:
294 case RT5677_PDM2_DATA_CTRL4:
295 case RT5677_I2C_MASTER_CTRL1:
296 case RT5677_I2C_MASTER_CTRL7:
297 case RT5677_I2C_MASTER_CTRL8:
298 case RT5677_HAP_GENE_CTRL2:
299 case RT5677_PWR_DSP_ST:
300 case RT5677_PRIV_DATA:
301 case RT5677_ASRC_22:
302 case RT5677_ASRC_23:
303 case RT5677_VAD_CTRL5:
304 case RT5677_ADC_EQ_CTRL1:
305 case RT5677_EQ_CTRL1:
306 case RT5677_IRQ_CTRL1:
307 case RT5677_IRQ_CTRL2:
308 case RT5677_GPIO_ST:
309 case RT5677_DSP_INB1_SRC_CTRL4:
310 case RT5677_DSP_INB2_SRC_CTRL4:
311 case RT5677_DSP_INB3_SRC_CTRL4:
312 case RT5677_DSP_OUTB1_SRC_CTRL4:
313 case RT5677_DSP_OUTB2_SRC_CTRL4:
314 case RT5677_VENDOR_ID:
315 case RT5677_VENDOR_ID1:
316 case RT5677_VENDOR_ID2:
317 return true;
318 default:
319 return false;
320 }
321 }
322
323 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
324 {
325 int i;
326
327 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
328 if (reg >= rt5677_ranges[i].range_min &&
329 reg <= rt5677_ranges[i].range_max) {
330 return true;
331 }
332 }
333
334 switch (reg) {
335 case RT5677_RESET:
336 case RT5677_LOUT1:
337 case RT5677_IN1:
338 case RT5677_MICBIAS:
339 case RT5677_SLIMBUS_PARAM:
340 case RT5677_SLIMBUS_RX:
341 case RT5677_SLIMBUS_CTRL:
342 case RT5677_SIDETONE_CTRL:
343 case RT5677_ANA_DAC1_2_3_SRC:
344 case RT5677_IF_DSP_DAC3_4_MIXER:
345 case RT5677_DAC4_DIG_VOL:
346 case RT5677_DAC3_DIG_VOL:
347 case RT5677_DAC1_DIG_VOL:
348 case RT5677_DAC2_DIG_VOL:
349 case RT5677_IF_DSP_DAC2_MIXER:
350 case RT5677_STO1_ADC_DIG_VOL:
351 case RT5677_MONO_ADC_DIG_VOL:
352 case RT5677_STO1_2_ADC_BST:
353 case RT5677_STO2_ADC_DIG_VOL:
354 case RT5677_ADC_BST_CTRL2:
355 case RT5677_STO3_4_ADC_BST:
356 case RT5677_STO3_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_DIG_VOL:
358 case RT5677_STO4_ADC_MIXER:
359 case RT5677_STO3_ADC_MIXER:
360 case RT5677_STO2_ADC_MIXER:
361 case RT5677_STO1_ADC_MIXER:
362 case RT5677_MONO_ADC_MIXER:
363 case RT5677_ADC_IF_DSP_DAC1_MIXER:
364 case RT5677_STO1_DAC_MIXER:
365 case RT5677_MONO_DAC_MIXER:
366 case RT5677_DD1_MIXER:
367 case RT5677_DD2_MIXER:
368 case RT5677_IF3_DATA:
369 case RT5677_IF4_DATA:
370 case RT5677_PDM_OUT_CTRL:
371 case RT5677_PDM_DATA_CTRL1:
372 case RT5677_PDM_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL2:
374 case RT5677_PDM1_DATA_CTRL3:
375 case RT5677_PDM1_DATA_CTRL4:
376 case RT5677_PDM2_DATA_CTRL2:
377 case RT5677_PDM2_DATA_CTRL3:
378 case RT5677_PDM2_DATA_CTRL4:
379 case RT5677_TDM1_CTRL1:
380 case RT5677_TDM1_CTRL2:
381 case RT5677_TDM1_CTRL3:
382 case RT5677_TDM1_CTRL4:
383 case RT5677_TDM1_CTRL5:
384 case RT5677_TDM2_CTRL1:
385 case RT5677_TDM2_CTRL2:
386 case RT5677_TDM2_CTRL3:
387 case RT5677_TDM2_CTRL4:
388 case RT5677_TDM2_CTRL5:
389 case RT5677_I2C_MASTER_CTRL1:
390 case RT5677_I2C_MASTER_CTRL2:
391 case RT5677_I2C_MASTER_CTRL3:
392 case RT5677_I2C_MASTER_CTRL4:
393 case RT5677_I2C_MASTER_CTRL5:
394 case RT5677_I2C_MASTER_CTRL6:
395 case RT5677_I2C_MASTER_CTRL7:
396 case RT5677_I2C_MASTER_CTRL8:
397 case RT5677_DMIC_CTRL1:
398 case RT5677_DMIC_CTRL2:
399 case RT5677_HAP_GENE_CTRL1:
400 case RT5677_HAP_GENE_CTRL2:
401 case RT5677_HAP_GENE_CTRL3:
402 case RT5677_HAP_GENE_CTRL4:
403 case RT5677_HAP_GENE_CTRL5:
404 case RT5677_HAP_GENE_CTRL6:
405 case RT5677_HAP_GENE_CTRL7:
406 case RT5677_HAP_GENE_CTRL8:
407 case RT5677_HAP_GENE_CTRL9:
408 case RT5677_HAP_GENE_CTRL10:
409 case RT5677_PWR_DIG1:
410 case RT5677_PWR_DIG2:
411 case RT5677_PWR_ANLG1:
412 case RT5677_PWR_ANLG2:
413 case RT5677_PWR_DSP1:
414 case RT5677_PWR_DSP_ST:
415 case RT5677_PWR_DSP2:
416 case RT5677_ADC_DAC_HPF_CTRL1:
417 case RT5677_PRIV_INDEX:
418 case RT5677_PRIV_DATA:
419 case RT5677_I2S4_SDP:
420 case RT5677_I2S1_SDP:
421 case RT5677_I2S2_SDP:
422 case RT5677_I2S3_SDP:
423 case RT5677_CLK_TREE_CTRL1:
424 case RT5677_CLK_TREE_CTRL2:
425 case RT5677_CLK_TREE_CTRL3:
426 case RT5677_PLL1_CTRL1:
427 case RT5677_PLL1_CTRL2:
428 case RT5677_PLL2_CTRL1:
429 case RT5677_PLL2_CTRL2:
430 case RT5677_GLB_CLK1:
431 case RT5677_GLB_CLK2:
432 case RT5677_ASRC_1:
433 case RT5677_ASRC_2:
434 case RT5677_ASRC_3:
435 case RT5677_ASRC_4:
436 case RT5677_ASRC_5:
437 case RT5677_ASRC_6:
438 case RT5677_ASRC_7:
439 case RT5677_ASRC_8:
440 case RT5677_ASRC_9:
441 case RT5677_ASRC_10:
442 case RT5677_ASRC_11:
443 case RT5677_ASRC_12:
444 case RT5677_ASRC_13:
445 case RT5677_ASRC_14:
446 case RT5677_ASRC_15:
447 case RT5677_ASRC_16:
448 case RT5677_ASRC_17:
449 case RT5677_ASRC_18:
450 case RT5677_ASRC_19:
451 case RT5677_ASRC_20:
452 case RT5677_ASRC_21:
453 case RT5677_ASRC_22:
454 case RT5677_ASRC_23:
455 case RT5677_VAD_CTRL1:
456 case RT5677_VAD_CTRL2:
457 case RT5677_VAD_CTRL3:
458 case RT5677_VAD_CTRL4:
459 case RT5677_VAD_CTRL5:
460 case RT5677_DSP_INB_CTRL1:
461 case RT5677_DSP_INB_CTRL2:
462 case RT5677_DSP_IN_OUTB_CTRL:
463 case RT5677_DSP_OUTB0_1_DIG_VOL:
464 case RT5677_DSP_OUTB2_3_DIG_VOL:
465 case RT5677_DSP_OUTB4_5_DIG_VOL:
466 case RT5677_DSP_OUTB6_7_DIG_VOL:
467 case RT5677_ADC_EQ_CTRL1:
468 case RT5677_ADC_EQ_CTRL2:
469 case RT5677_EQ_CTRL1:
470 case RT5677_EQ_CTRL2:
471 case RT5677_EQ_CTRL3:
472 case RT5677_SOFT_VOL_ZERO_CROSS1:
473 case RT5677_JD_CTRL1:
474 case RT5677_JD_CTRL2:
475 case RT5677_JD_CTRL3:
476 case RT5677_IRQ_CTRL1:
477 case RT5677_IRQ_CTRL2:
478 case RT5677_GPIO_ST:
479 case RT5677_GPIO_CTRL1:
480 case RT5677_GPIO_CTRL2:
481 case RT5677_GPIO_CTRL3:
482 case RT5677_STO1_ADC_HI_FILTER1:
483 case RT5677_STO1_ADC_HI_FILTER2:
484 case RT5677_MONO_ADC_HI_FILTER1:
485 case RT5677_MONO_ADC_HI_FILTER2:
486 case RT5677_STO2_ADC_HI_FILTER1:
487 case RT5677_STO2_ADC_HI_FILTER2:
488 case RT5677_STO3_ADC_HI_FILTER1:
489 case RT5677_STO3_ADC_HI_FILTER2:
490 case RT5677_STO4_ADC_HI_FILTER1:
491 case RT5677_STO4_ADC_HI_FILTER2:
492 case RT5677_MB_DRC_CTRL1:
493 case RT5677_DRC1_CTRL1:
494 case RT5677_DRC1_CTRL2:
495 case RT5677_DRC1_CTRL3:
496 case RT5677_DRC1_CTRL4:
497 case RT5677_DRC1_CTRL5:
498 case RT5677_DRC1_CTRL6:
499 case RT5677_DRC2_CTRL1:
500 case RT5677_DRC2_CTRL2:
501 case RT5677_DRC2_CTRL3:
502 case RT5677_DRC2_CTRL4:
503 case RT5677_DRC2_CTRL5:
504 case RT5677_DRC2_CTRL6:
505 case RT5677_DRC1_HL_CTRL1:
506 case RT5677_DRC1_HL_CTRL2:
507 case RT5677_DRC2_HL_CTRL1:
508 case RT5677_DRC2_HL_CTRL2:
509 case RT5677_DSP_INB1_SRC_CTRL1:
510 case RT5677_DSP_INB1_SRC_CTRL2:
511 case RT5677_DSP_INB1_SRC_CTRL3:
512 case RT5677_DSP_INB1_SRC_CTRL4:
513 case RT5677_DSP_INB2_SRC_CTRL1:
514 case RT5677_DSP_INB2_SRC_CTRL2:
515 case RT5677_DSP_INB2_SRC_CTRL3:
516 case RT5677_DSP_INB2_SRC_CTRL4:
517 case RT5677_DSP_INB3_SRC_CTRL1:
518 case RT5677_DSP_INB3_SRC_CTRL2:
519 case RT5677_DSP_INB3_SRC_CTRL3:
520 case RT5677_DSP_INB3_SRC_CTRL4:
521 case RT5677_DSP_OUTB1_SRC_CTRL1:
522 case RT5677_DSP_OUTB1_SRC_CTRL2:
523 case RT5677_DSP_OUTB1_SRC_CTRL3:
524 case RT5677_DSP_OUTB1_SRC_CTRL4:
525 case RT5677_DSP_OUTB2_SRC_CTRL1:
526 case RT5677_DSP_OUTB2_SRC_CTRL2:
527 case RT5677_DSP_OUTB2_SRC_CTRL3:
528 case RT5677_DSP_OUTB2_SRC_CTRL4:
529 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
530 case RT5677_DSP_OUTB_45_MIXER_CTRL:
531 case RT5677_DSP_OUTB_67_MIXER_CTRL:
532 case RT5677_DIG_MISC:
533 case RT5677_GEN_CTRL1:
534 case RT5677_GEN_CTRL2:
535 case RT5677_VENDOR_ID:
536 case RT5677_VENDOR_ID1:
537 case RT5677_VENDOR_ID2:
538 return true;
539 default:
540 return false;
541 }
542 }
543
544 /**
545 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
546 * @rt5677: Private Data.
547 * @addr: Address index.
548 * @value: Address data.
549 *
550 *
551 * Returns 0 for success or negative error code.
552 */
553 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
554 unsigned int addr, unsigned int value, unsigned int opcode)
555 {
556 struct snd_soc_codec *codec = rt5677->codec;
557 int ret;
558
559 mutex_lock(&rt5677->dsp_cmd_lock);
560
561 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
562 addr >> 16);
563 if (ret < 0) {
564 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
565 goto err;
566 }
567
568 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
569 addr & 0xffff);
570 if (ret < 0) {
571 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
572 goto err;
573 }
574
575 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
576 value >> 16);
577 if (ret < 0) {
578 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
579 goto err;
580 }
581
582 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
583 value & 0xffff);
584 if (ret < 0) {
585 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
586 goto err;
587 }
588
589 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
590 opcode);
591 if (ret < 0) {
592 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
593 goto err;
594 }
595
596 err:
597 mutex_unlock(&rt5677->dsp_cmd_lock);
598
599 return ret;
600 }
601
602 /**
603 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
604 * rt5677: Private Data.
605 * @addr: Address index.
606 * @value: Address data.
607 *
608 *
609 * Returns 0 for success or negative error code.
610 */
611 static int rt5677_dsp_mode_i2c_read_addr(
612 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
613 {
614 struct snd_soc_codec *codec = rt5677->codec;
615 int ret;
616 unsigned int msb, lsb;
617
618 mutex_lock(&rt5677->dsp_cmd_lock);
619
620 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
621 addr >> 16);
622 if (ret < 0) {
623 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
624 goto err;
625 }
626
627 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
628 addr & 0xffff);
629 if (ret < 0) {
630 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
631 goto err;
632 }
633
634 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
635 0x0002);
636 if (ret < 0) {
637 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
638 goto err;
639 }
640
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
642 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
643 *value = (msb << 16) | lsb;
644
645 err:
646 mutex_unlock(&rt5677->dsp_cmd_lock);
647
648 return ret;
649 }
650
651 /**
652 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
653 * rt5677: Private Data.
654 * @reg: Register index.
655 * @value: Register data.
656 *
657 *
658 * Returns 0 for success or negative error code.
659 */
660 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
661 unsigned int reg, unsigned int value)
662 {
663 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
664 value, 0x0001);
665 }
666
667 /**
668 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
669 * @codec: SoC audio codec device.
670 * @reg: Register index.
671 * @value: Register data.
672 *
673 *
674 * Returns 0 for success or negative error code.
675 */
676 static int rt5677_dsp_mode_i2c_read(
677 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
678 {
679 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
680 value);
681
682 *value &= 0xffff;
683
684 return ret;
685 }
686
687 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
688 {
689 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
690
691 if (on) {
692 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
693 rt5677->is_dsp_mode = true;
694 } else {
695 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
696 rt5677->is_dsp_mode = false;
697 }
698 }
699
700 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
701 {
702 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
703 static bool activity;
704 int ret;
705
706 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
707 return -ENXIO;
708
709 if (on && !activity) {
710 activity = true;
711
712 regcache_cache_only(rt5677->regmap, false);
713 regcache_cache_bypass(rt5677->regmap, true);
714
715 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
716 regmap_update_bits(rt5677->regmap,
717 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
718 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
719 RT5677_LDO1_SEL_MASK, 0x0);
720 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
721 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
722 switch (rt5677->type) {
723 case RT5677:
724 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
725 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
726 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
727 RT5677_PLL2_PR_SRC_MASK |
728 RT5677_DSP_CLK_SRC_MASK,
729 RT5677_PLL2_PR_SRC_MCLK2 |
730 RT5677_DSP_CLK_SRC_BYPASS);
731 break;
732 case RT5676:
733 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
734 RT5677_DSP_CLK_SRC_MASK,
735 RT5677_DSP_CLK_SRC_BYPASS);
736 break;
737 default:
738 break;
739 }
740 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
741 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
742 rt5677_set_dsp_mode(codec, true);
743
744 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
745 codec->dev);
746 if (ret == 0) {
747 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
748 release_firmware(rt5677->fw1);
749 }
750
751 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
752 codec->dev);
753 if (ret == 0) {
754 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
755 release_firmware(rt5677->fw2);
756 }
757
758 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
759
760 regcache_cache_bypass(rt5677->regmap, false);
761 regcache_cache_only(rt5677->regmap, true);
762 } else if (!on && activity) {
763 activity = false;
764
765 regcache_cache_only(rt5677->regmap, false);
766 regcache_cache_bypass(rt5677->regmap, true);
767
768 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
769 rt5677_set_dsp_mode(codec, false);
770 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
771
772 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
773
774 regcache_cache_bypass(rt5677->regmap, false);
775 regcache_mark_dirty(rt5677->regmap);
776 regcache_sync(rt5677->regmap);
777 }
778
779 return 0;
780 }
781
782 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
783 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
784 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
785 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
786 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
787 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
788
789 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
790 static const DECLARE_TLV_DB_RANGE(bst_tlv,
791 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
792 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
793 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
794 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
795 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
796 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
797 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
798 );
799
800 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_value *ucontrol)
802 {
803 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
804 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
805
806 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
807
808 return 0;
809 }
810
811 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
812 struct snd_ctl_elem_value *ucontrol)
813 {
814 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
815 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
816 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
817
818 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
819
820 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
821 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
822
823 return 0;
824 }
825
826 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
827 /* OUTPUT Control */
828 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
829 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
830 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
834
835 /* DAC Digital Volume */
836 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
837 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
838 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
840 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
842 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
844
845 /* IN1/IN2 Control */
846 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
847 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
848
849 /* ADC Digital Volume Control */
850 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
851 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
852 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860
861 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
862 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
863 adc_vol_tlv),
864 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
866 adc_vol_tlv),
867 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
869 adc_vol_tlv),
870 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
871 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
872 adc_vol_tlv),
873 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
874 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
875 adc_vol_tlv),
876
877 /* Sidetone Control */
878 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
879 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
880
881 /* ADC Boost Volume Control */
882 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
883 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
884 adc_bst_tlv),
885 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
886 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
887 adc_bst_tlv),
888 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
889 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
890 adc_bst_tlv),
891 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
892 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
893 adc_bst_tlv),
894 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
895 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
896 adc_bst_tlv),
897
898 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
899 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
900 };
901
902 /**
903 * set_dmic_clk - Set parameter of dmic.
904 *
905 * @w: DAPM widget.
906 * @kcontrol: The kcontrol of this widget.
907 * @event: Event id.
908 *
909 * Choose dmic clock between 1MHz and 3MHz.
910 * It is better for clock to approximate 3MHz.
911 */
912 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
913 struct snd_kcontrol *kcontrol, int event)
914 {
915 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
916 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
917 int idx, rate;
918
919 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
920 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
921 idx = rl6231_calc_dmic_clk(rate);
922 if (idx < 0)
923 dev_err(codec->dev, "Failed to set DMIC clock\n");
924 else
925 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
926 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
927 return idx;
928 }
929
930 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
931 struct snd_soc_dapm_widget *sink)
932 {
933 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
934 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
935 unsigned int val;
936
937 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
938 val &= RT5677_SCLK_SRC_MASK;
939 if (val == RT5677_SCLK_SRC_PLL1)
940 return 1;
941 else
942 return 0;
943 }
944
945 static int is_using_asrc(struct snd_soc_dapm_widget *source,
946 struct snd_soc_dapm_widget *sink)
947 {
948 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
949 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
950 unsigned int reg, shift, val;
951
952 if (source->reg == RT5677_ASRC_1) {
953 switch (source->shift) {
954 case 12:
955 reg = RT5677_ASRC_4;
956 shift = 0;
957 break;
958 case 13:
959 reg = RT5677_ASRC_4;
960 shift = 4;
961 break;
962 case 14:
963 reg = RT5677_ASRC_4;
964 shift = 8;
965 break;
966 case 15:
967 reg = RT5677_ASRC_4;
968 shift = 12;
969 break;
970 default:
971 return 0;
972 }
973 } else {
974 switch (source->shift) {
975 case 0:
976 reg = RT5677_ASRC_6;
977 shift = 8;
978 break;
979 case 1:
980 reg = RT5677_ASRC_6;
981 shift = 12;
982 break;
983 case 2:
984 reg = RT5677_ASRC_5;
985 shift = 0;
986 break;
987 case 3:
988 reg = RT5677_ASRC_5;
989 shift = 4;
990 break;
991 case 4:
992 reg = RT5677_ASRC_5;
993 shift = 8;
994 break;
995 case 5:
996 reg = RT5677_ASRC_5;
997 shift = 12;
998 break;
999 case 12:
1000 reg = RT5677_ASRC_3;
1001 shift = 0;
1002 break;
1003 case 13:
1004 reg = RT5677_ASRC_3;
1005 shift = 4;
1006 break;
1007 case 14:
1008 reg = RT5677_ASRC_3;
1009 shift = 12;
1010 break;
1011 default:
1012 return 0;
1013 }
1014 }
1015
1016 regmap_read(rt5677->regmap, reg, &val);
1017 val = (val >> shift) & 0xf;
1018
1019 switch (val) {
1020 case 1 ... 6:
1021 return 1;
1022 default:
1023 return 0;
1024 }
1025
1026 }
1027
1028 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1029 struct snd_soc_dapm_widget *sink)
1030 {
1031 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1032 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1033
1034 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1035 return 1;
1036
1037 return 0;
1038 }
1039
1040 /**
1041 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1042 * @codec: SoC audio codec device.
1043 * @filter_mask: mask of filters.
1044 * @clk_src: clock source
1045 *
1046 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1047 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1048 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1049 * ASRC function will track i2s clock and generate a corresponding system clock
1050 * for codec. This function provides an API to select the clock source for a
1051 * set of filters specified by the mask. And the codec driver will turn on ASRC
1052 * for these filters if ASRC is selected as their clock source.
1053 */
1054 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1055 unsigned int filter_mask, unsigned int clk_src)
1056 {
1057 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1058 unsigned int asrc3_mask = 0, asrc3_value = 0;
1059 unsigned int asrc4_mask = 0, asrc4_value = 0;
1060 unsigned int asrc5_mask = 0, asrc5_value = 0;
1061 unsigned int asrc6_mask = 0, asrc6_value = 0;
1062 unsigned int asrc7_mask = 0, asrc7_value = 0;
1063 unsigned int asrc8_mask = 0, asrc8_value = 0;
1064
1065 switch (clk_src) {
1066 case RT5677_CLK_SEL_SYS:
1067 case RT5677_CLK_SEL_I2S1_ASRC:
1068 case RT5677_CLK_SEL_I2S2_ASRC:
1069 case RT5677_CLK_SEL_I2S3_ASRC:
1070 case RT5677_CLK_SEL_I2S4_ASRC:
1071 case RT5677_CLK_SEL_I2S5_ASRC:
1072 case RT5677_CLK_SEL_I2S6_ASRC:
1073 case RT5677_CLK_SEL_SYS2:
1074 case RT5677_CLK_SEL_SYS3:
1075 case RT5677_CLK_SEL_SYS4:
1076 case RT5677_CLK_SEL_SYS5:
1077 case RT5677_CLK_SEL_SYS6:
1078 case RT5677_CLK_SEL_SYS7:
1079 break;
1080
1081 default:
1082 return -EINVAL;
1083 }
1084
1085 /* ASRC 3 */
1086 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1087 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1088 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1089 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1090 }
1091
1092 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1093 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1094 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1095 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1096 }
1097
1098 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1099 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1100 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1101 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1102 }
1103
1104 if (asrc3_mask)
1105 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1106 asrc3_value);
1107
1108 /* ASRC 4 */
1109 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1110 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1111 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1112 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1113 }
1114
1115 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1116 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1117 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1118 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1119 }
1120
1121 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1122 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1123 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1124 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1125 }
1126
1127 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1128 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1129 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1130 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1131 }
1132
1133 if (asrc4_mask)
1134 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1135 asrc4_value);
1136
1137 /* ASRC 5 */
1138 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1139 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1140 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1141 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1142 }
1143
1144 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1145 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1146 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1147 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1148 }
1149
1150 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1151 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1152 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1153 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1154 }
1155
1156 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1157 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1158 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1159 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1160 }
1161
1162 if (asrc5_mask)
1163 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1164 asrc5_value);
1165
1166 /* ASRC 6 */
1167 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1168 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1169 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1170 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1171 }
1172
1173 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1174 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1175 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1176 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1177 }
1178
1179 if (asrc6_mask)
1180 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1181 asrc6_value);
1182
1183 /* ASRC 7 */
1184 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1185 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1186 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1187 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1188 }
1189
1190 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1191 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1192 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1193 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1194 }
1195
1196 if (asrc7_mask)
1197 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1198 asrc7_value);
1199
1200 /* ASRC 8 */
1201 if (filter_mask & RT5677_I2S1_SOURCE) {
1202 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1203 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1204 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1205 }
1206
1207 if (filter_mask & RT5677_I2S2_SOURCE) {
1208 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1209 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1210 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1211 }
1212
1213 if (filter_mask & RT5677_I2S3_SOURCE) {
1214 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1215 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1216 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1217 }
1218
1219 if (filter_mask & RT5677_I2S4_SOURCE) {
1220 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1221 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1222 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1223 }
1224
1225 if (asrc8_mask)
1226 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1227 asrc8_value);
1228
1229 return 0;
1230 }
1231 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1232
1233 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1234 struct snd_soc_dapm_widget *sink)
1235 {
1236 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1237 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1238 unsigned int asrc_setting;
1239
1240 switch (source->shift) {
1241 case 11:
1242 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1243 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1244 RT5677_AD_STO1_CLK_SEL_SFT;
1245 break;
1246
1247 case 10:
1248 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1249 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1250 RT5677_AD_STO2_CLK_SEL_SFT;
1251 break;
1252
1253 case 9:
1254 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1255 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1256 RT5677_AD_STO3_CLK_SEL_SFT;
1257 break;
1258
1259 case 8:
1260 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1261 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1262 RT5677_AD_STO4_CLK_SEL_SFT;
1263 break;
1264
1265 case 7:
1266 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1267 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1268 RT5677_AD_MONOL_CLK_SEL_SFT;
1269 break;
1270
1271 case 6:
1272 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1273 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1274 RT5677_AD_MONOR_CLK_SEL_SFT;
1275 break;
1276
1277 default:
1278 return 0;
1279 }
1280
1281 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1282 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1283 return 1;
1284
1285 return 0;
1286 }
1287
1288 /* Digital Mixer */
1289 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1290 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1291 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1292 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1293 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1294 };
1295
1296 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1297 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1298 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1299 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1300 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1301 };
1302
1303 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1304 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1305 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1306 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1307 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1308 };
1309
1310 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1311 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1312 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1313 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1314 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1315 };
1316
1317 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1318 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1319 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1320 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1321 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1322 };
1323
1324 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1325 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1326 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1327 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1328 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1329 };
1330
1331 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1332 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1333 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1334 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1335 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1336 };
1337
1338 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1339 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1340 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1341 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1342 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1343 };
1344
1345 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1346 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1347 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1348 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1349 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1350 };
1351
1352 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1353 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1354 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1355 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1356 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1357 };
1358
1359 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1360 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1361 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1362 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1363 RT5677_M_DAC1_L_SFT, 1, 1),
1364 };
1365
1366 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1367 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1368 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1369 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1370 RT5677_M_DAC1_R_SFT, 1, 1),
1371 };
1372
1373 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1374 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1375 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1376 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1377 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1378 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1379 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1380 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1381 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1382 };
1383
1384 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1385 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1386 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1387 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1388 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1389 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1390 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1391 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1392 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1393 };
1394
1395 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1396 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1397 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1398 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1399 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1400 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1401 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1402 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1403 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1404 };
1405
1406 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1407 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1408 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1409 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1410 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1411 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1412 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1413 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1414 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1415 };
1416
1417 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1418 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1419 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1420 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1421 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1422 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1423 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1424 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1425 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1426 };
1427
1428 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1429 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1430 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1431 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1432 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1433 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1434 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1435 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1436 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1437 };
1438
1439 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1440 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1441 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1442 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1443 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1444 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1445 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1446 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1447 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1448 };
1449
1450 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1451 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1452 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1453 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1454 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1455 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1456 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1457 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1458 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1459 };
1460
1461 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1462 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1463 RT5677_DSP_IB_01_H_SFT, 1, 1),
1464 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1465 RT5677_DSP_IB_23_H_SFT, 1, 1),
1466 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1467 RT5677_DSP_IB_45_H_SFT, 1, 1),
1468 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1469 RT5677_DSP_IB_6_H_SFT, 1, 1),
1470 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1471 RT5677_DSP_IB_7_H_SFT, 1, 1),
1472 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1473 RT5677_DSP_IB_8_H_SFT, 1, 1),
1474 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1475 RT5677_DSP_IB_9_H_SFT, 1, 1),
1476 };
1477
1478 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1479 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1480 RT5677_DSP_IB_01_L_SFT, 1, 1),
1481 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482 RT5677_DSP_IB_23_L_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484 RT5677_DSP_IB_45_L_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486 RT5677_DSP_IB_6_L_SFT, 1, 1),
1487 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488 RT5677_DSP_IB_7_L_SFT, 1, 1),
1489 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1490 RT5677_DSP_IB_8_L_SFT, 1, 1),
1491 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1492 RT5677_DSP_IB_9_L_SFT, 1, 1),
1493 };
1494
1495 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1496 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1497 RT5677_DSP_IB_01_H_SFT, 1, 1),
1498 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1499 RT5677_DSP_IB_23_H_SFT, 1, 1),
1500 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1501 RT5677_DSP_IB_45_H_SFT, 1, 1),
1502 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1503 RT5677_DSP_IB_6_H_SFT, 1, 1),
1504 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1505 RT5677_DSP_IB_7_H_SFT, 1, 1),
1506 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1507 RT5677_DSP_IB_8_H_SFT, 1, 1),
1508 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1509 RT5677_DSP_IB_9_H_SFT, 1, 1),
1510 };
1511
1512 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1513 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1514 RT5677_DSP_IB_01_L_SFT, 1, 1),
1515 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516 RT5677_DSP_IB_23_L_SFT, 1, 1),
1517 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518 RT5677_DSP_IB_45_L_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520 RT5677_DSP_IB_6_L_SFT, 1, 1),
1521 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522 RT5677_DSP_IB_7_L_SFT, 1, 1),
1523 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1524 RT5677_DSP_IB_8_L_SFT, 1, 1),
1525 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1526 RT5677_DSP_IB_9_L_SFT, 1, 1),
1527 };
1528
1529 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1530 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1531 RT5677_DSP_IB_01_H_SFT, 1, 1),
1532 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1533 RT5677_DSP_IB_23_H_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1535 RT5677_DSP_IB_45_H_SFT, 1, 1),
1536 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1537 RT5677_DSP_IB_6_H_SFT, 1, 1),
1538 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1539 RT5677_DSP_IB_7_H_SFT, 1, 1),
1540 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1541 RT5677_DSP_IB_8_H_SFT, 1, 1),
1542 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1543 RT5677_DSP_IB_9_H_SFT, 1, 1),
1544 };
1545
1546 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1547 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1548 RT5677_DSP_IB_01_L_SFT, 1, 1),
1549 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550 RT5677_DSP_IB_23_L_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552 RT5677_DSP_IB_45_L_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554 RT5677_DSP_IB_6_L_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556 RT5677_DSP_IB_7_L_SFT, 1, 1),
1557 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1558 RT5677_DSP_IB_8_L_SFT, 1, 1),
1559 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1560 RT5677_DSP_IB_9_L_SFT, 1, 1),
1561 };
1562
1563
1564 /* Mux */
1565 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1566 static const char * const rt5677_dac1_src[] = {
1567 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1568 "OB 01"
1569 };
1570
1571 static SOC_ENUM_SINGLE_DECL(
1572 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1573 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1574
1575 static const struct snd_kcontrol_new rt5677_dac1_mux =
1576 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1577
1578 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1579 static const char * const rt5677_adda1_src[] = {
1580 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1581 };
1582
1583 static SOC_ENUM_SINGLE_DECL(
1584 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1585 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1586
1587 static const struct snd_kcontrol_new rt5677_adda1_mux =
1588 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1589
1590
1591 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1592 static const char * const rt5677_dac2l_src[] = {
1593 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1594 "OB 2",
1595 };
1596
1597 static SOC_ENUM_SINGLE_DECL(
1598 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1599 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1600
1601 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1602 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1603
1604 static const char * const rt5677_dac2r_src[] = {
1605 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1606 "OB 3", "Haptic Generator", "VAD ADC"
1607 };
1608
1609 static SOC_ENUM_SINGLE_DECL(
1610 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1611 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1612
1613 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1614 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1615
1616 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1617 static const char * const rt5677_dac3l_src[] = {
1618 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1619 "SLB DAC 4", "OB 4"
1620 };
1621
1622 static SOC_ENUM_SINGLE_DECL(
1623 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1624 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1625
1626 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1627 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1628
1629 static const char * const rt5677_dac3r_src[] = {
1630 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1631 "SLB DAC 5", "OB 5"
1632 };
1633
1634 static SOC_ENUM_SINGLE_DECL(
1635 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1636 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1637
1638 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1639 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1640
1641 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1642 static const char * const rt5677_dac4l_src[] = {
1643 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1644 "SLB DAC 6", "OB 6"
1645 };
1646
1647 static SOC_ENUM_SINGLE_DECL(
1648 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1649 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1650
1651 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1652 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1653
1654 static const char * const rt5677_dac4r_src[] = {
1655 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1656 "SLB DAC 7", "OB 7"
1657 };
1658
1659 static SOC_ENUM_SINGLE_DECL(
1660 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1661 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1662
1663 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1664 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1665
1666 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1667 static const char * const rt5677_iob_bypass_src[] = {
1668 "Bypass", "Pass SRC"
1669 };
1670
1671 static SOC_ENUM_SINGLE_DECL(
1672 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1673 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1674
1675 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1676 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1677
1678 static SOC_ENUM_SINGLE_DECL(
1679 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1680 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1681
1682 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1683 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1684
1685 static SOC_ENUM_SINGLE_DECL(
1686 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1687 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1688
1689 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1690 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1691
1692 static SOC_ENUM_SINGLE_DECL(
1693 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1694 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1695
1696 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1697 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1698
1699 static SOC_ENUM_SINGLE_DECL(
1700 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1701 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1702
1703 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1704 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1705
1706 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1707 static const char * const rt5677_stereo_adc2_src[] = {
1708 "DD MIX1", "DMIC", "Stereo DAC MIX"
1709 };
1710
1711 static SOC_ENUM_SINGLE_DECL(
1712 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1713 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1714
1715 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1716 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1717
1718 static SOC_ENUM_SINGLE_DECL(
1719 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1720 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1721
1722 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1723 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1724
1725 static SOC_ENUM_SINGLE_DECL(
1726 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1727 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1728
1729 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1730 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1731
1732 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1733 static const char * const rt5677_dmic_src[] = {
1734 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1735 };
1736
1737 static SOC_ENUM_SINGLE_DECL(
1738 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1739 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1740
1741 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1742 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1743
1744 static SOC_ENUM_SINGLE_DECL(
1745 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1746 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1747
1748 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1749 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1750
1751 static SOC_ENUM_SINGLE_DECL(
1752 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1753 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1754
1755 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1756 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1757
1758 static SOC_ENUM_SINGLE_DECL(
1759 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1760 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1761
1762 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1763 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1764
1765 static SOC_ENUM_SINGLE_DECL(
1766 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1767 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1768
1769 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1770 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1771
1772 static SOC_ENUM_SINGLE_DECL(
1773 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1774 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1775
1776 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1777 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1778
1779 /* Stereo2 ADC Source */ /* MX-26 [0] */
1780 static const char * const rt5677_stereo2_adc_lr_src[] = {
1781 "L", "LR"
1782 };
1783
1784 static SOC_ENUM_SINGLE_DECL(
1785 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1786 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1787
1788 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1789 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1790
1791 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1792 static const char * const rt5677_stereo_adc1_src[] = {
1793 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1794 };
1795
1796 static SOC_ENUM_SINGLE_DECL(
1797 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1798 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1799
1800 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1801 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1802
1803 static SOC_ENUM_SINGLE_DECL(
1804 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1805 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1806
1807 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1808 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1809
1810 static SOC_ENUM_SINGLE_DECL(
1811 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1812 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1813
1814 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1815 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1816
1817 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1818 static const char * const rt5677_mono_adc2_l_src[] = {
1819 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1820 };
1821
1822 static SOC_ENUM_SINGLE_DECL(
1823 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1824 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1825
1826 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1827 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1828
1829 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1830 static const char * const rt5677_mono_adc1_l_src[] = {
1831 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1832 };
1833
1834 static SOC_ENUM_SINGLE_DECL(
1835 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1836 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1837
1838 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1839 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1840
1841 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1842 static const char * const rt5677_mono_adc2_r_src[] = {
1843 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1844 };
1845
1846 static SOC_ENUM_SINGLE_DECL(
1847 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1848 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1849
1850 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1851 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1852
1853 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1854 static const char * const rt5677_mono_adc1_r_src[] = {
1855 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1856 };
1857
1858 static SOC_ENUM_SINGLE_DECL(
1859 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1860 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1861
1862 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1863 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1864
1865 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1866 static const char * const rt5677_stereo4_adc2_src[] = {
1867 "DD MIX1", "DMIC", "DD MIX2"
1868 };
1869
1870 static SOC_ENUM_SINGLE_DECL(
1871 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1872 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1873
1874 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1875 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1876
1877
1878 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1879 static const char * const rt5677_stereo4_adc1_src[] = {
1880 "DD MIX1", "ADC1/2", "DD MIX2"
1881 };
1882
1883 static SOC_ENUM_SINGLE_DECL(
1884 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1885 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1886
1887 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1888 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1889
1890 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1891 static const char * const rt5677_inbound01_src[] = {
1892 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1893 "VAD ADC/DAC1 FS"
1894 };
1895
1896 static SOC_ENUM_SINGLE_DECL(
1897 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1898 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1899
1900 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1901 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1902
1903 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1904 static const char * const rt5677_inbound23_src[] = {
1905 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1906 "DAC1 FS", "IF4 DAC"
1907 };
1908
1909 static SOC_ENUM_SINGLE_DECL(
1910 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1911 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1912
1913 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1914 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1915
1916 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1917 static const char * const rt5677_inbound45_src[] = {
1918 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1919 "IF3 DAC"
1920 };
1921
1922 static SOC_ENUM_SINGLE_DECL(
1923 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1924 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1925
1926 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1927 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1928
1929 /* InBound6 Source */ /* MX-A3 [2:0] */
1930 static const char * const rt5677_inbound6_src[] = {
1931 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1932 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1933 };
1934
1935 static SOC_ENUM_SINGLE_DECL(
1936 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1937 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1938
1939 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1940 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1941
1942 /* InBound7 Source */ /* MX-A4 [14:12] */
1943 static const char * const rt5677_inbound7_src[] = {
1944 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1945 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1946 };
1947
1948 static SOC_ENUM_SINGLE_DECL(
1949 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1950 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1951
1952 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1953 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1954
1955 /* InBound8 Source */ /* MX-A4 [10:8] */
1956 static const char * const rt5677_inbound8_src[] = {
1957 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1958 "MONO ADC MIX L", "DACL1 FS"
1959 };
1960
1961 static SOC_ENUM_SINGLE_DECL(
1962 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1963 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1964
1965 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1966 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1967
1968 /* InBound9 Source */ /* MX-A4 [6:4] */
1969 static const char * const rt5677_inbound9_src[] = {
1970 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1971 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1972 };
1973
1974 static SOC_ENUM_SINGLE_DECL(
1975 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1976 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1977
1978 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1979 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1980
1981 /* VAD Source */ /* MX-9F [6:4] */
1982 static const char * const rt5677_vad_src[] = {
1983 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1984 "STO3 ADC MIX L"
1985 };
1986
1987 static SOC_ENUM_SINGLE_DECL(
1988 rt5677_vad_enum, RT5677_VAD_CTRL4,
1989 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1990
1991 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1992 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1993
1994 /* Sidetone Source */ /* MX-13 [11:9] */
1995 static const char * const rt5677_sidetone_src[] = {
1996 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1997 };
1998
1999 static SOC_ENUM_SINGLE_DECL(
2000 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2001 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2002
2003 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2004 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2005
2006 /* DAC1/2 Source */ /* MX-15 [1:0] */
2007 static const char * const rt5677_dac12_src[] = {
2008 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2009 };
2010
2011 static SOC_ENUM_SINGLE_DECL(
2012 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2013 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2014
2015 static const struct snd_kcontrol_new rt5677_dac12_mux =
2016 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2017
2018 /* DAC3 Source */ /* MX-15 [5:4] */
2019 static const char * const rt5677_dac3_src[] = {
2020 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2021 };
2022
2023 static SOC_ENUM_SINGLE_DECL(
2024 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2025 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2026
2027 static const struct snd_kcontrol_new rt5677_dac3_mux =
2028 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2029
2030 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2031 static const char * const rt5677_pdm_src[] = {
2032 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2033 };
2034
2035 static SOC_ENUM_SINGLE_DECL(
2036 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2037 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2038
2039 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2040 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2041
2042 static SOC_ENUM_SINGLE_DECL(
2043 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2044 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2045
2046 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2047 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2048
2049 static SOC_ENUM_SINGLE_DECL(
2050 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2051 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2052
2053 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2054 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2055
2056 static SOC_ENUM_SINGLE_DECL(
2057 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2058 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2059
2060 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2061 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2062
2063 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2064 static const char * const rt5677_if12_adc1_src[] = {
2065 "STO1 ADC MIX", "OB01", "VAD ADC"
2066 };
2067
2068 static SOC_ENUM_SINGLE_DECL(
2069 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2070 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2071
2072 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2073 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2074
2075 static SOC_ENUM_SINGLE_DECL(
2076 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2077 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2078
2079 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2080 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2081
2082 static SOC_ENUM_SINGLE_DECL(
2083 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2084 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2085
2086 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2087 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2088
2089 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2090 static const char * const rt5677_if12_adc2_src[] = {
2091 "STO2 ADC MIX", "OB23"
2092 };
2093
2094 static SOC_ENUM_SINGLE_DECL(
2095 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2096 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2097
2098 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2099 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2100
2101 static SOC_ENUM_SINGLE_DECL(
2102 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2103 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2104
2105 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2106 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2107
2108 static SOC_ENUM_SINGLE_DECL(
2109 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2110 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2111
2112 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2113 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2114
2115 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2116 static const char * const rt5677_if12_adc3_src[] = {
2117 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2118 };
2119
2120 static SOC_ENUM_SINGLE_DECL(
2121 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2122 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2123
2124 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2125 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2126
2127 static SOC_ENUM_SINGLE_DECL(
2128 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2129 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2130
2131 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2132 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2133
2134 static SOC_ENUM_SINGLE_DECL(
2135 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2136 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2137
2138 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2139 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2140
2141 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2142 static const char * const rt5677_if12_adc4_src[] = {
2143 "STO4 ADC MIX", "OB67", "OB01"
2144 };
2145
2146 static SOC_ENUM_SINGLE_DECL(
2147 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2148 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2149
2150 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2151 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2152
2153 static SOC_ENUM_SINGLE_DECL(
2154 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2155 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2156
2157 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2158 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2159
2160 static SOC_ENUM_SINGLE_DECL(
2161 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2162 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2163
2164 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2165 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2166
2167 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2168 static const char * const rt5677_if34_adc_src[] = {
2169 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2170 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2171 };
2172
2173 static SOC_ENUM_SINGLE_DECL(
2174 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2175 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2176
2177 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2178 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2179
2180 static SOC_ENUM_SINGLE_DECL(
2181 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2182 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2183
2184 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2185 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2186
2187 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2188 static const char * const rt5677_if12_adc_swap_src[] = {
2189 "L/R", "R/L", "L/L", "R/R"
2190 };
2191
2192 static SOC_ENUM_SINGLE_DECL(
2193 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2194 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2195
2196 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2197 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2198
2199 static SOC_ENUM_SINGLE_DECL(
2200 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2201 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2202
2203 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2204 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2205
2206 static SOC_ENUM_SINGLE_DECL(
2207 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2208 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2209
2210 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2211 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2212
2213 static SOC_ENUM_SINGLE_DECL(
2214 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2215 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2216
2217 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2218 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2219
2220 static SOC_ENUM_SINGLE_DECL(
2221 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2222 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2223
2224 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2225 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2226
2227 static SOC_ENUM_SINGLE_DECL(
2228 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2229 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2230
2231 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2232 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2233
2234 static SOC_ENUM_SINGLE_DECL(
2235 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2236 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2237
2238 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2239 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2240
2241 static SOC_ENUM_SINGLE_DECL(
2242 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2243 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2244
2245 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2246 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2247
2248 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2249 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2250 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2251 "3/1/2/4", "3/4/1/2"
2252 };
2253
2254 static SOC_ENUM_SINGLE_DECL(
2255 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2256 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2257
2258 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2259 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2260
2261 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2262 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2263 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2264 "2/3/1/4", "3/4/1/2"
2265 };
2266
2267 static SOC_ENUM_SINGLE_DECL(
2268 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2269 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2270
2271 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2272 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2273
2274 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2275 MX-3F[14:12][10:8][6:4][2:0]
2276 MX-43[14:12][10:8][6:4][2:0]
2277 MX-44[14:12][10:8][6:4][2:0] */
2278 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2279 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2280 };
2281
2282 static SOC_ENUM_SINGLE_DECL(
2283 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2284 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2285
2286 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2287 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2288
2289 static SOC_ENUM_SINGLE_DECL(
2290 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2291 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2292
2293 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2294 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2295
2296 static SOC_ENUM_SINGLE_DECL(
2297 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2298 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2299
2300 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2301 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2302
2303 static SOC_ENUM_SINGLE_DECL(
2304 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2305 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2306
2307 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2308 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2309
2310 static SOC_ENUM_SINGLE_DECL(
2311 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2312 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2313
2314 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2315 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2316
2317 static SOC_ENUM_SINGLE_DECL(
2318 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2319 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2320
2321 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2322 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2323
2324 static SOC_ENUM_SINGLE_DECL(
2325 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2326 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2327
2328 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2329 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2330
2331 static SOC_ENUM_SINGLE_DECL(
2332 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2333 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2334
2335 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2336 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2337
2338 static SOC_ENUM_SINGLE_DECL(
2339 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2340 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2341
2342 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2343 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2344
2345 static SOC_ENUM_SINGLE_DECL(
2346 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2347 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2348
2349 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2350 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2351
2352 static SOC_ENUM_SINGLE_DECL(
2353 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2354 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2355
2356 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2357 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2358
2359 static SOC_ENUM_SINGLE_DECL(
2360 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2361 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2362
2363 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2364 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2365
2366 static SOC_ENUM_SINGLE_DECL(
2367 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2368 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2369
2370 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2371 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2372
2373 static SOC_ENUM_SINGLE_DECL(
2374 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2375 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2376
2377 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2378 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2379
2380 static SOC_ENUM_SINGLE_DECL(
2381 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2382 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2383
2384 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2385 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2386
2387 static SOC_ENUM_SINGLE_DECL(
2388 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2389 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2390
2391 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2392 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2393
2394 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2395 struct snd_kcontrol *kcontrol, int event)
2396 {
2397 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2398 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2399
2400 switch (event) {
2401 case SND_SOC_DAPM_POST_PMU:
2402 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2403 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2404 break;
2405
2406 case SND_SOC_DAPM_PRE_PMD:
2407 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2408 RT5677_PWR_BST1_P, 0);
2409 break;
2410
2411 default:
2412 return 0;
2413 }
2414
2415 return 0;
2416 }
2417
2418 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2419 struct snd_kcontrol *kcontrol, int event)
2420 {
2421 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2422 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2423
2424 switch (event) {
2425 case SND_SOC_DAPM_POST_PMU:
2426 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2427 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2428 break;
2429
2430 case SND_SOC_DAPM_PRE_PMD:
2431 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2432 RT5677_PWR_BST2_P, 0);
2433 break;
2434
2435 default:
2436 return 0;
2437 }
2438
2439 return 0;
2440 }
2441
2442 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2443 struct snd_kcontrol *kcontrol, int event)
2444 {
2445 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2446 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2447
2448 switch (event) {
2449 case SND_SOC_DAPM_PRE_PMU:
2450 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2451 break;
2452
2453 case SND_SOC_DAPM_POST_PMU:
2454 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2455 break;
2456
2457 default:
2458 return 0;
2459 }
2460
2461 return 0;
2462 }
2463
2464 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2465 struct snd_kcontrol *kcontrol, int event)
2466 {
2467 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2468 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2469
2470 switch (event) {
2471 case SND_SOC_DAPM_PRE_PMU:
2472 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2473 break;
2474
2475 case SND_SOC_DAPM_POST_PMU:
2476 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2477 break;
2478
2479 default:
2480 return 0;
2481 }
2482
2483 return 0;
2484 }
2485
2486 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2487 struct snd_kcontrol *kcontrol, int event)
2488 {
2489 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2490 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2491
2492 switch (event) {
2493 case SND_SOC_DAPM_POST_PMU:
2494 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2495 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2496 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2497 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2498 break;
2499
2500 case SND_SOC_DAPM_PRE_PMD:
2501 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2502 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2503 RT5677_PWR_CLK_MB, 0);
2504 break;
2505
2506 default:
2507 return 0;
2508 }
2509
2510 return 0;
2511 }
2512
2513 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2514 struct snd_kcontrol *kcontrol, int event)
2515 {
2516 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2517 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2518 unsigned int value;
2519
2520 switch (event) {
2521 case SND_SOC_DAPM_PRE_PMU:
2522 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2523 if (value & RT5677_IF1_ADC_CTRL_MASK)
2524 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2525 RT5677_IF1_ADC_MODE_MASK,
2526 RT5677_IF1_ADC_MODE_TDM);
2527 break;
2528
2529 default:
2530 return 0;
2531 }
2532
2533 return 0;
2534 }
2535
2536 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2537 struct snd_kcontrol *kcontrol, int event)
2538 {
2539 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2540 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2541 unsigned int value;
2542
2543 switch (event) {
2544 case SND_SOC_DAPM_PRE_PMU:
2545 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2546 if (value & RT5677_IF2_ADC_CTRL_MASK)
2547 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2548 RT5677_IF2_ADC_MODE_MASK,
2549 RT5677_IF2_ADC_MODE_TDM);
2550 break;
2551
2552 default:
2553 return 0;
2554 }
2555
2556 return 0;
2557 }
2558
2559 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2560 struct snd_kcontrol *kcontrol, int event)
2561 {
2562 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2563 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2564
2565 switch (event) {
2566 case SND_SOC_DAPM_POST_PMU:
2567 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2568 !rt5677->is_vref_slow) {
2569 mdelay(20);
2570 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2571 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2572 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2573 rt5677->is_vref_slow = true;
2574 }
2575 break;
2576
2577 default:
2578 return 0;
2579 }
2580
2581 return 0;
2582 }
2583
2584 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2585 struct snd_kcontrol *kcontrol, int event)
2586 {
2587 switch (event) {
2588 case SND_SOC_DAPM_POST_PMU:
2589 msleep(50);
2590 break;
2591
2592 default:
2593 return 0;
2594 }
2595
2596 return 0;
2597 }
2598
2599 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2600 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2601 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2602 SND_SOC_DAPM_POST_PMU),
2603 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2604 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2605 SND_SOC_DAPM_POST_PMU),
2606
2607 /* ASRC */
2608 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2609 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2613 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2614 0),
2615 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2616 0),
2617 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2618 0),
2619 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2620 0),
2621 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2622 0),
2623 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2624 0),
2625 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2626 0),
2627 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2628 0),
2629 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2630 0),
2631 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2632 0),
2633 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2634 0),
2635 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2636 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2638 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2640 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2642 0),
2643 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2644 0),
2645
2646 /* Input Side */
2647 /* micbias */
2648 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2649 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2650 SND_SOC_DAPM_POST_PMU),
2651
2652 /* Input Lines */
2653 SND_SOC_DAPM_INPUT("DMIC L1"),
2654 SND_SOC_DAPM_INPUT("DMIC R1"),
2655 SND_SOC_DAPM_INPUT("DMIC L2"),
2656 SND_SOC_DAPM_INPUT("DMIC R2"),
2657 SND_SOC_DAPM_INPUT("DMIC L3"),
2658 SND_SOC_DAPM_INPUT("DMIC R3"),
2659 SND_SOC_DAPM_INPUT("DMIC L4"),
2660 SND_SOC_DAPM_INPUT("DMIC R4"),
2661
2662 SND_SOC_DAPM_INPUT("IN1P"),
2663 SND_SOC_DAPM_INPUT("IN1N"),
2664 SND_SOC_DAPM_INPUT("IN2P"),
2665 SND_SOC_DAPM_INPUT("IN2N"),
2666
2667 SND_SOC_DAPM_INPUT("Haptic Generator"),
2668
2669 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2670 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2671 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2672 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2673
2674 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2675 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2676 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2677 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2678 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2679 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2680 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2681 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2682
2683 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2684 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2685
2686 /* Boost */
2687 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2688 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2689 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2690 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2691 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2692 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2693
2694 /* ADCs */
2695 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2696 0, 0),
2697 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2698 0, 0),
2699 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2700
2701 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2702 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2703 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2704 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2706 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2707 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2708 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2709
2710 /* ADC Mux */
2711 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2712 &rt5677_sto1_dmic_mux),
2713 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2714 &rt5677_sto1_adc1_mux),
2715 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2716 &rt5677_sto1_adc2_mux),
2717 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2718 &rt5677_sto2_dmic_mux),
2719 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2720 &rt5677_sto2_adc1_mux),
2721 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2722 &rt5677_sto2_adc2_mux),
2723 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2724 &rt5677_sto2_adc_lr_mux),
2725 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2726 &rt5677_sto3_dmic_mux),
2727 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2728 &rt5677_sto3_adc1_mux),
2729 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2730 &rt5677_sto3_adc2_mux),
2731 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2732 &rt5677_sto4_dmic_mux),
2733 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2734 &rt5677_sto4_adc1_mux),
2735 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2736 &rt5677_sto4_adc2_mux),
2737 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2738 &rt5677_mono_dmic_l_mux),
2739 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2740 &rt5677_mono_dmic_r_mux),
2741 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2742 &rt5677_mono_adc2_l_mux),
2743 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2744 &rt5677_mono_adc1_l_mux),
2745 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2746 &rt5677_mono_adc1_r_mux),
2747 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2748 &rt5677_mono_adc2_r_mux),
2749
2750 /* ADC Mixer */
2751 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2752 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2753 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2754 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2755 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2756 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2757 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2758 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2759 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2760 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2761 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2762 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2763 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2764 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2765 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2766 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2767 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2768 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2769 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2770 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2771 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2772 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2773 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2774 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2775 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2776 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2777 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2778 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2779 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2780 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2781 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2782 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2783
2784 /* ADC PGA */
2785 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2786 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2801
2802 /* DSP */
2803 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2804 &rt5677_ib9_src_mux),
2805 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2806 &rt5677_ib8_src_mux),
2807 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2808 &rt5677_ib7_src_mux),
2809 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2810 &rt5677_ib6_src_mux),
2811 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2812 &rt5677_ib45_src_mux),
2813 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2814 &rt5677_ib23_src_mux),
2815 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2816 &rt5677_ib01_src_mux),
2817 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2818 &rt5677_ib45_bypass_src_mux),
2819 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2820 &rt5677_ib23_bypass_src_mux),
2821 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2822 &rt5677_ib01_bypass_src_mux),
2823 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2824 &rt5677_ob23_bypass_src_mux),
2825 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2826 &rt5677_ob01_bypass_src_mux),
2827
2828 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2829 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2830
2831 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2833 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2836 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2837
2838 /* Digital Interface */
2839 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2840 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2857
2858 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2859 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2876
2877 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2878 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2885
2886 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2887 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2894
2895 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2896 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2913
2914 /* Digital Interface Select */
2915 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2916 &rt5677_if1_adc1_mux),
2917 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2918 &rt5677_if1_adc2_mux),
2919 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2920 &rt5677_if1_adc3_mux),
2921 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2922 &rt5677_if1_adc4_mux),
2923 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2924 &rt5677_if1_adc1_swap_mux),
2925 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2926 &rt5677_if1_adc2_swap_mux),
2927 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2928 &rt5677_if1_adc3_swap_mux),
2929 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2930 &rt5677_if1_adc4_swap_mux),
2931 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2932 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2933 SND_SOC_DAPM_PRE_PMU),
2934 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5677_if2_adc1_mux),
2936 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5677_if2_adc2_mux),
2938 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5677_if2_adc3_mux),
2940 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5677_if2_adc4_mux),
2942 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5677_if2_adc1_swap_mux),
2944 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5677_if2_adc2_swap_mux),
2946 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5677_if2_adc3_swap_mux),
2948 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5677_if2_adc4_swap_mux),
2950 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2952 SND_SOC_DAPM_PRE_PMU),
2953 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5677_if3_adc_mux),
2955 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5677_if4_adc_mux),
2957 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5677_slb_adc1_mux),
2959 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5677_slb_adc2_mux),
2961 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_slb_adc3_mux),
2963 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5677_slb_adc4_mux),
2965
2966 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2967 &rt5677_if1_dac0_tdm_sel_mux),
2968 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5677_if1_dac1_tdm_sel_mux),
2970 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5677_if1_dac2_tdm_sel_mux),
2972 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5677_if1_dac3_tdm_sel_mux),
2974 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5677_if1_dac4_tdm_sel_mux),
2976 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5677_if1_dac5_tdm_sel_mux),
2978 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5677_if1_dac6_tdm_sel_mux),
2980 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5677_if1_dac7_tdm_sel_mux),
2982
2983 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5677_if2_dac0_tdm_sel_mux),
2985 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5677_if2_dac1_tdm_sel_mux),
2987 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5677_if2_dac2_tdm_sel_mux),
2989 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5677_if2_dac3_tdm_sel_mux),
2991 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5677_if2_dac4_tdm_sel_mux),
2993 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5677_if2_dac5_tdm_sel_mux),
2995 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5677_if2_dac6_tdm_sel_mux),
2997 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5677_if2_dac7_tdm_sel_mux),
2999
3000 /* Audio Interface */
3001 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3011
3012 /* Sidetone Mux */
3013 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3014 &rt5677_sidetone_mux),
3015 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3016 RT5677_ST_EN_SFT, 0, NULL, 0),
3017
3018 /* VAD Mux*/
3019 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3020 &rt5677_vad_src_mux),
3021
3022 /* Tensilica DSP */
3023 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3024 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3025 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3026 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3027 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3028 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3029 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3030 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3031 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3032 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3033 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3034 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3035 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3036
3037 /* Output Side */
3038 /* DAC mixer before sound effect */
3039 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3040 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3041 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3042 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3043 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3044
3045 /* DAC Mux */
3046 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3047 &rt5677_dac1_mux),
3048 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3049 &rt5677_adda1_mux),
3050 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3051 &rt5677_dac12_mux),
3052 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3053 &rt5677_dac3_mux),
3054
3055 /* DAC2 channel Mux */
3056 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3057 &rt5677_dac2_l_mux),
3058 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3059 &rt5677_dac2_r_mux),
3060
3061 /* DAC3 channel Mux */
3062 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3063 &rt5677_dac3_l_mux),
3064 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3065 &rt5677_dac3_r_mux),
3066
3067 /* DAC4 channel Mux */
3068 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3069 &rt5677_dac4_l_mux),
3070 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3071 &rt5677_dac4_r_mux),
3072
3073 /* DAC Mixer */
3074 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3075 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3076 SND_SOC_DAPM_POST_PMU),
3077 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3078 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3079 SND_SOC_DAPM_POST_PMU),
3080 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3081 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3082 SND_SOC_DAPM_POST_PMU),
3083 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3084 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3085 SND_SOC_DAPM_POST_PMU),
3086 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3087 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3088 SND_SOC_DAPM_POST_PMU),
3089 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3090 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3091 SND_SOC_DAPM_POST_PMU),
3092 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3093 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3094 SND_SOC_DAPM_POST_PMU),
3095
3096 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3097 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3098 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3099 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3100 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3101 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3102 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3103 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3104 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3105 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3106 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3107 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3108 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3109 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3110 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3111 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3112 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3113 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3114 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3115 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3116
3117 /* DACs */
3118 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3119 RT5677_PWR_DAC1_BIT, 0),
3120 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3121 RT5677_PWR_DAC2_BIT, 0),
3122 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3123 RT5677_PWR_DAC3_BIT, 0),
3124
3125 /* PDM */
3126 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3127 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3128 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3129 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3130
3131 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3132 1, &rt5677_pdm1_l_mux),
3133 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3134 1, &rt5677_pdm1_r_mux),
3135 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3136 1, &rt5677_pdm2_l_mux),
3137 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3138 1, &rt5677_pdm2_r_mux),
3139
3140 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3141 0, NULL, 0),
3142 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3143 0, NULL, 0),
3144 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3145 0, NULL, 0),
3146
3147 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3148 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3149 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3150 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3151 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3152 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3153
3154 /* Output Lines */
3155 SND_SOC_DAPM_OUTPUT("LOUT1"),
3156 SND_SOC_DAPM_OUTPUT("LOUT2"),
3157 SND_SOC_DAPM_OUTPUT("LOUT3"),
3158 SND_SOC_DAPM_OUTPUT("PDM1L"),
3159 SND_SOC_DAPM_OUTPUT("PDM1R"),
3160 SND_SOC_DAPM_OUTPUT("PDM2L"),
3161 SND_SOC_DAPM_OUTPUT("PDM2R"),
3162
3163 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3164 };
3165
3166 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3167 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3168 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3169 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3170 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3171 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3172 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3173 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3174 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3175 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3176 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3177
3178 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3179 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3180 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3181 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3182 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3183 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3184 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3185 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3186 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3187 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3188 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3189 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3190 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3191
3192 { "DMIC1", NULL, "DMIC L1" },
3193 { "DMIC1", NULL, "DMIC R1" },
3194 { "DMIC2", NULL, "DMIC L2" },
3195 { "DMIC2", NULL, "DMIC R2" },
3196 { "DMIC3", NULL, "DMIC L3" },
3197 { "DMIC3", NULL, "DMIC R3" },
3198 { "DMIC4", NULL, "DMIC L4" },
3199 { "DMIC4", NULL, "DMIC R4" },
3200
3201 { "DMIC L1", NULL, "DMIC CLK" },
3202 { "DMIC R1", NULL, "DMIC CLK" },
3203 { "DMIC L2", NULL, "DMIC CLK" },
3204 { "DMIC R2", NULL, "DMIC CLK" },
3205 { "DMIC L3", NULL, "DMIC CLK" },
3206 { "DMIC R3", NULL, "DMIC CLK" },
3207 { "DMIC L4", NULL, "DMIC CLK" },
3208 { "DMIC R4", NULL, "DMIC CLK" },
3209
3210 { "DMIC L1", NULL, "DMIC1 power" },
3211 { "DMIC R1", NULL, "DMIC1 power" },
3212 { "DMIC L3", NULL, "DMIC3 power" },
3213 { "DMIC R3", NULL, "DMIC3 power" },
3214 { "DMIC L4", NULL, "DMIC4 power" },
3215 { "DMIC R4", NULL, "DMIC4 power" },
3216
3217 { "BST1", NULL, "IN1P" },
3218 { "BST1", NULL, "IN1N" },
3219 { "BST2", NULL, "IN2P" },
3220 { "BST2", NULL, "IN2N" },
3221
3222 { "IN1P", NULL, "MICBIAS1" },
3223 { "IN1N", NULL, "MICBIAS1" },
3224 { "IN2P", NULL, "MICBIAS1" },
3225 { "IN2N", NULL, "MICBIAS1" },
3226
3227 { "ADC 1", NULL, "BST1" },
3228 { "ADC 1", NULL, "ADC 1 power" },
3229 { "ADC 1", NULL, "ADC1 clock" },
3230 { "ADC 2", NULL, "BST2" },
3231 { "ADC 2", NULL, "ADC 2 power" },
3232 { "ADC 2", NULL, "ADC2 clock" },
3233
3234 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3235 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3236 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3237 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3238
3239 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3240 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3241 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3242 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3243
3244 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3245 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3246 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3247 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3248
3249 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3250 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3251 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3252 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3253
3254 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3255 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3256 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3257 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3258
3259 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3260 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3261 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3262 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3263
3264 { "ADC 1_2", NULL, "ADC 1" },
3265 { "ADC 1_2", NULL, "ADC 2" },
3266
3267 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3268 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3269 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3270
3271 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3272 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3273 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3274
3275 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3276 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3277 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3278
3279 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3280 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3281 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3282
3283 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3284 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3285 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3286
3287 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3288 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3289 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3290
3291 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3292 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3293 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3294
3295 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3296 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3297 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3298
3299 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3300 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3301 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3302
3303 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3304 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3305 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3306
3307 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3308 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3309 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3310
3311 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3312 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3313 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3314
3315 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3316 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3317 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3318 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3319
3320 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3321 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3322 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3323 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3324 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3325
3326 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3327 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3328
3329 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3330 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3331 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3332 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3333
3334 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3335 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3336
3337 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3338 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3339
3340 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3341 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3342 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3343 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3344 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3345
3346 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3347 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3348
3349 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3350 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3351 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3352 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3353
3354 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3355 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3356 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3357 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3358 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3359
3360 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3361 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3362
3363 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3364 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3365 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3366 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3367
3368 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3369 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3370 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3371 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3372 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3373
3374 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3375 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3376
3377 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3378 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3379 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3380 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3381
3382 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3383 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3384 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3385 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3386
3387 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3388 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3389
3390 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3391 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3392 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3393 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3394 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3395
3396 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3397 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3398 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3399
3400 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3401 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3402
3403 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3404 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3405 { "IF1 ADC3 Mux", "OB45", "OB45" },
3406
3407 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3408 { "IF1 ADC4 Mux", "OB67", "OB67" },
3409 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3410
3411 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3412 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3413 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3414 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3415
3416 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3417 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3418 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3419 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3420
3421 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3422 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3423 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3424 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3425
3426 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3427 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3428 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3429 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3430
3431 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3432 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3433 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3434 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3435
3436 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3437 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3438 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3439 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3440 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3441 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3442 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3443 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3444
3445 { "AIF1TX", NULL, "I2S1" },
3446 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3447
3448 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3449 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3450 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3451
3452 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3453 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3454
3455 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3456 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3457 { "IF2 ADC3 Mux", "OB45", "OB45" },
3458
3459 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3460 { "IF2 ADC4 Mux", "OB67", "OB67" },
3461 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3462
3463 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3464 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3465 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3466 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3467
3468 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3469 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3470 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3471 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3472
3473 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3474 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3475 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3476 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3477
3478 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3479 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3480 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3481 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3482
3483 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3484 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3485 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3486 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3487
3488 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3489 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3490 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3491 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3492 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3493 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3494 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3495 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3496
3497 { "AIF2TX", NULL, "I2S2" },
3498 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3499
3500 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3501 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3502 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3503 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3504 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3505 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3506 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3507 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3508
3509 { "AIF3TX", NULL, "I2S3" },
3510 { "AIF3TX", NULL, "IF3 ADC Mux" },
3511
3512 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3513 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3514 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3515 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3516 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3517 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3518 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3519 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3520
3521 { "AIF4TX", NULL, "I2S4" },
3522 { "AIF4TX", NULL, "IF4 ADC Mux" },
3523
3524 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3525 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3526 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3527
3528 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3529 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3530
3531 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3532 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3533 { "SLB ADC3 Mux", "OB45", "OB45" },
3534
3535 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3536 { "SLB ADC4 Mux", "OB67", "OB67" },
3537 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3538
3539 { "SLBTX", NULL, "SLB" },
3540 { "SLBTX", NULL, "SLB ADC1 Mux" },
3541 { "SLBTX", NULL, "SLB ADC2 Mux" },
3542 { "SLBTX", NULL, "SLB ADC3 Mux" },
3543 { "SLBTX", NULL, "SLB ADC4 Mux" },
3544
3545 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3546 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3547 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3548 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3549 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3550
3551 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3552 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3553
3554 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3555 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3556 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3557 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3558 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3559 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3560
3561 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3562 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3563
3564 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3565 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3566 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3567 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3568 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3569
3570 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3571 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3572
3573 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3574 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3575 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3576 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3577 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3578 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3579 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3580 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3581
3582 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3583 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3584 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3585 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3586 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3587 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3588 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3589 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3590
3591 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3592 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3593 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3594 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3595 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3596 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3597
3598 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3599 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3600 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3601 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3602 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3603 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3604 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3605
3606 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3607 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3608 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3609 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3610 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3611 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3612 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3613
3614 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3615 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3616 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3617 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3618 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3619 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3620 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3621
3622 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3623 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3624 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3625 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3626 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3627 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3628 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3629
3630 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3631 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3632 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3633 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3634 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3635 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3636 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3637
3638 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3639 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3640 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3641 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3642 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3643 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3644 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3645
3646 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3647 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3648 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3649 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3650 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3651 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3652 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3653
3654 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3655 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3656 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3657 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3658
3659 { "OutBound2", NULL, "OB23 Bypass Mux" },
3660 { "OutBound3", NULL, "OB23 Bypass Mux" },
3661 { "OutBound4", NULL, "OB4 MIX" },
3662 { "OutBound5", NULL, "OB5 MIX" },
3663 { "OutBound6", NULL, "OB6 MIX" },
3664 { "OutBound7", NULL, "OB7 MIX" },
3665
3666 { "OB45", NULL, "OutBound4" },
3667 { "OB45", NULL, "OutBound5" },
3668 { "OB67", NULL, "OutBound6" },
3669 { "OB67", NULL, "OutBound7" },
3670
3671 { "IF1 DAC0", NULL, "AIF1RX" },
3672 { "IF1 DAC1", NULL, "AIF1RX" },
3673 { "IF1 DAC2", NULL, "AIF1RX" },
3674 { "IF1 DAC3", NULL, "AIF1RX" },
3675 { "IF1 DAC4", NULL, "AIF1RX" },
3676 { "IF1 DAC5", NULL, "AIF1RX" },
3677 { "IF1 DAC6", NULL, "AIF1RX" },
3678 { "IF1 DAC7", NULL, "AIF1RX" },
3679 { "IF1 DAC0", NULL, "I2S1" },
3680 { "IF1 DAC1", NULL, "I2S1" },
3681 { "IF1 DAC2", NULL, "I2S1" },
3682 { "IF1 DAC3", NULL, "I2S1" },
3683 { "IF1 DAC4", NULL, "I2S1" },
3684 { "IF1 DAC5", NULL, "I2S1" },
3685 { "IF1 DAC6", NULL, "I2S1" },
3686 { "IF1 DAC7", NULL, "I2S1" },
3687
3688 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3689 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3690 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3691 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3692 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3693 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3694 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3695 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3696
3697 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3698 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3699 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3700 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3701 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3702 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3703 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3704 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3705
3706 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3707 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3708 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3709 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3710 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3711 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3712 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3713 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3714
3715 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3716 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3717 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3718 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3719 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3720 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3721 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3722 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3723
3724 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3725 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3726 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3727 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3728 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3729 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3730 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3731 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3732
3733 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3734 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3735 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3736 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3737 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3738 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3739 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3740 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3741
3742 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3743 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3744 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3745 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3746 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3747 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3748 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3749 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3750
3751 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3752 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3753 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3754 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3755 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3756 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3757 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3758 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3759
3760 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3761 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3762 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3763 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3764 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3765 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3766 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3767 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3768
3769 { "IF2 DAC0", NULL, "AIF2RX" },
3770 { "IF2 DAC1", NULL, "AIF2RX" },
3771 { "IF2 DAC2", NULL, "AIF2RX" },
3772 { "IF2 DAC3", NULL, "AIF2RX" },
3773 { "IF2 DAC4", NULL, "AIF2RX" },
3774 { "IF2 DAC5", NULL, "AIF2RX" },
3775 { "IF2 DAC6", NULL, "AIF2RX" },
3776 { "IF2 DAC7", NULL, "AIF2RX" },
3777 { "IF2 DAC0", NULL, "I2S2" },
3778 { "IF2 DAC1", NULL, "I2S2" },
3779 { "IF2 DAC2", NULL, "I2S2" },
3780 { "IF2 DAC3", NULL, "I2S2" },
3781 { "IF2 DAC4", NULL, "I2S2" },
3782 { "IF2 DAC5", NULL, "I2S2" },
3783 { "IF2 DAC6", NULL, "I2S2" },
3784 { "IF2 DAC7", NULL, "I2S2" },
3785
3786 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3787 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3788 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3789 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3790 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3791 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3792 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3793 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3794
3795 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3796 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3797 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3798 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3799 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3800 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3801 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3802 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3803
3804 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3805 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3806 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3807 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3808 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3809 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3810 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3811 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3812
3813 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3814 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3815 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3816 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3817 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3818 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3819 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3820 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3821
3822 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3823 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3824 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3825 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3826 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3827 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3828 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3829 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3830
3831 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3832 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3833 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3834 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3835 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3836 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3837 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3838 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3839
3840 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3841 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3842 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3843 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3844 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3845 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3846 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3847 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3848
3849 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3850 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3851 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3852 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3853 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3854 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3855 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3856 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3857
3858 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3859 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3860 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3861 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3862 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3863 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3864 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3865 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3866
3867 { "IF3 DAC", NULL, "AIF3RX" },
3868 { "IF3 DAC", NULL, "I2S3" },
3869
3870 { "IF4 DAC", NULL, "AIF4RX" },
3871 { "IF4 DAC", NULL, "I2S4" },
3872
3873 { "IF3 DAC L", NULL, "IF3 DAC" },
3874 { "IF3 DAC R", NULL, "IF3 DAC" },
3875
3876 { "IF4 DAC L", NULL, "IF4 DAC" },
3877 { "IF4 DAC R", NULL, "IF4 DAC" },
3878
3879 { "SLB DAC0", NULL, "SLBRX" },
3880 { "SLB DAC1", NULL, "SLBRX" },
3881 { "SLB DAC2", NULL, "SLBRX" },
3882 { "SLB DAC3", NULL, "SLBRX" },
3883 { "SLB DAC4", NULL, "SLBRX" },
3884 { "SLB DAC5", NULL, "SLBRX" },
3885 { "SLB DAC6", NULL, "SLBRX" },
3886 { "SLB DAC7", NULL, "SLBRX" },
3887 { "SLB DAC0", NULL, "SLB" },
3888 { "SLB DAC1", NULL, "SLB" },
3889 { "SLB DAC2", NULL, "SLB" },
3890 { "SLB DAC3", NULL, "SLB" },
3891 { "SLB DAC4", NULL, "SLB" },
3892 { "SLB DAC5", NULL, "SLB" },
3893 { "SLB DAC6", NULL, "SLB" },
3894 { "SLB DAC7", NULL, "SLB" },
3895
3896 { "SLB DAC01", NULL, "SLB DAC0" },
3897 { "SLB DAC01", NULL, "SLB DAC1" },
3898 { "SLB DAC23", NULL, "SLB DAC2" },
3899 { "SLB DAC23", NULL, "SLB DAC3" },
3900 { "SLB DAC45", NULL, "SLB DAC4" },
3901 { "SLB DAC45", NULL, "SLB DAC5" },
3902 { "SLB DAC67", NULL, "SLB DAC6" },
3903 { "SLB DAC67", NULL, "SLB DAC7" },
3904
3905 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3906 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3907 { "ADDA1 Mux", "OB 67", "OB67" },
3908
3909 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3910 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3911 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3912 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3913 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3914 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3915
3916 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3917 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3918 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3919 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3920
3921 { "DAC1 FS", NULL, "DAC1 MIXL" },
3922 { "DAC1 FS", NULL, "DAC1 MIXR" },
3923
3924 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3925 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3926 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3927 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3928 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3929 { "DAC2 L Mux", "OB 2", "OutBound2" },
3930
3931 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3932 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3933 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3934 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3935 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3936 { "DAC2 R Mux", "OB 3", "OutBound3" },
3937 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3938 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3939
3940 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3941 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3942 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3943 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3944 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3945 { "DAC3 L Mux", "OB 4", "OutBound4" },
3946
3947 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3948 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3949 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3950 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3951 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3952 { "DAC3 R Mux", "OB 5", "OutBound5" },
3953
3954 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3955 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3956 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3957 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3958 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3959 { "DAC4 L Mux", "OB 6", "OutBound6" },
3960
3961 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3962 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3963 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3964 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3965 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3966 { "DAC4 R Mux", "OB 7", "OutBound7" },
3967
3968 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3969 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3970 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3971 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3972 { "Sidetone Mux", "ADC1", "ADC 1" },
3973 { "Sidetone Mux", "ADC2", "ADC 2" },
3974 { "Sidetone Mux", NULL, "Sidetone Power" },
3975
3976 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3977 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3978 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3979 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3980 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3981 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3982 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3983 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3984 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3985 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3986 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3987
3988 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3989 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3990 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3991 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3992 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3993 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3994 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3995 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3996 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3997 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3998 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3999 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4000
4001 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4002 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4003 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4004 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4005 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4006 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4007 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4008 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4009 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4010 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4011 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4012 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4013
4014 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4015 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4016 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4017 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4018 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4019 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4020 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4021 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4022 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4023 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4024 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4025 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4026
4027 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4028 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4029 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4030 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4031 { "DD1 MIX", NULL, "DD1 MIXL" },
4032 { "DD1 MIX", NULL, "DD1 MIXR" },
4033 { "DD2 MIX", NULL, "DD2 MIXL" },
4034 { "DD2 MIX", NULL, "DD2 MIXR" },
4035
4036 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4037 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4038 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4039 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4040
4041 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4042 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4043 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4044 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4045
4046 { "DAC 1", NULL, "DAC12 SRC Mux" },
4047 { "DAC 2", NULL, "DAC12 SRC Mux" },
4048 { "DAC 3", NULL, "DAC3 SRC Mux" },
4049
4050 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4051 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4052 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4053 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4054 { "PDM1 L Mux", NULL, "PDM1 Power" },
4055 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4056 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4057 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4058 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4059 { "PDM1 R Mux", NULL, "PDM1 Power" },
4060 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4061 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4062 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4063 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4064 { "PDM2 L Mux", NULL, "PDM2 Power" },
4065 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4066 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4067 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4068 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4069 { "PDM2 R Mux", NULL, "PDM2 Power" },
4070
4071 { "LOUT1 amp", NULL, "DAC 1" },
4072 { "LOUT2 amp", NULL, "DAC 2" },
4073 { "LOUT3 amp", NULL, "DAC 3" },
4074
4075 { "LOUT1 vref", NULL, "LOUT1 amp" },
4076 { "LOUT2 vref", NULL, "LOUT2 amp" },
4077 { "LOUT3 vref", NULL, "LOUT3 amp" },
4078
4079 { "LOUT1", NULL, "LOUT1 vref" },
4080 { "LOUT2", NULL, "LOUT2 vref" },
4081 { "LOUT3", NULL, "LOUT3 vref" },
4082
4083 { "PDM1L", NULL, "PDM1 L Mux" },
4084 { "PDM1R", NULL, "PDM1 R Mux" },
4085 { "PDM2L", NULL, "PDM2 L Mux" },
4086 { "PDM2R", NULL, "PDM2 R Mux" },
4087 };
4088
4089 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4090 { "DMIC L2", NULL, "DMIC1 power" },
4091 { "DMIC R2", NULL, "DMIC1 power" },
4092 };
4093
4094 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4095 { "DMIC L2", NULL, "DMIC2 power" },
4096 { "DMIC R2", NULL, "DMIC2 power" },
4097 };
4098
4099 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4100 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4101 {
4102 struct snd_soc_codec *codec = dai->codec;
4103 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4104 unsigned int val_len = 0, val_clk, mask_clk;
4105 int pre_div, bclk_ms, frame_size;
4106
4107 rt5677->lrck[dai->id] = params_rate(params);
4108 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4109 if (pre_div < 0) {
4110 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4111 rt5677->sysclk, rt5677->lrck[dai->id]);
4112 return -EINVAL;
4113 }
4114 frame_size = snd_soc_params_to_frame_size(params);
4115 if (frame_size < 0) {
4116 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4117 return -EINVAL;
4118 }
4119 bclk_ms = frame_size > 32;
4120 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4121
4122 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4123 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4124 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4125 bclk_ms, pre_div, dai->id);
4126
4127 switch (params_width(params)) {
4128 case 16:
4129 break;
4130 case 20:
4131 val_len |= RT5677_I2S_DL_20;
4132 break;
4133 case 24:
4134 val_len |= RT5677_I2S_DL_24;
4135 break;
4136 case 8:
4137 val_len |= RT5677_I2S_DL_8;
4138 break;
4139 default:
4140 return -EINVAL;
4141 }
4142
4143 switch (dai->id) {
4144 case RT5677_AIF1:
4145 mask_clk = RT5677_I2S_PD1_MASK;
4146 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4147 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4148 RT5677_I2S_DL_MASK, val_len);
4149 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4150 mask_clk, val_clk);
4151 break;
4152 case RT5677_AIF2:
4153 mask_clk = RT5677_I2S_PD2_MASK;
4154 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4155 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4156 RT5677_I2S_DL_MASK, val_len);
4157 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4158 mask_clk, val_clk);
4159 break;
4160 case RT5677_AIF3:
4161 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4162 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4163 pre_div << RT5677_I2S_PD3_SFT;
4164 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4165 RT5677_I2S_DL_MASK, val_len);
4166 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4167 mask_clk, val_clk);
4168 break;
4169 case RT5677_AIF4:
4170 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4171 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4172 pre_div << RT5677_I2S_PD4_SFT;
4173 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4174 RT5677_I2S_DL_MASK, val_len);
4175 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4176 mask_clk, val_clk);
4177 break;
4178 default:
4179 break;
4180 }
4181
4182 return 0;
4183 }
4184
4185 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4186 {
4187 struct snd_soc_codec *codec = dai->codec;
4188 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4189 unsigned int reg_val = 0;
4190
4191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4192 case SND_SOC_DAIFMT_CBM_CFM:
4193 rt5677->master[dai->id] = 1;
4194 break;
4195 case SND_SOC_DAIFMT_CBS_CFS:
4196 reg_val |= RT5677_I2S_MS_S;
4197 rt5677->master[dai->id] = 0;
4198 break;
4199 default:
4200 return -EINVAL;
4201 }
4202
4203 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4204 case SND_SOC_DAIFMT_NB_NF:
4205 break;
4206 case SND_SOC_DAIFMT_IB_NF:
4207 reg_val |= RT5677_I2S_BP_INV;
4208 break;
4209 default:
4210 return -EINVAL;
4211 }
4212
4213 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4214 case SND_SOC_DAIFMT_I2S:
4215 break;
4216 case SND_SOC_DAIFMT_LEFT_J:
4217 reg_val |= RT5677_I2S_DF_LEFT;
4218 break;
4219 case SND_SOC_DAIFMT_DSP_A:
4220 reg_val |= RT5677_I2S_DF_PCM_A;
4221 break;
4222 case SND_SOC_DAIFMT_DSP_B:
4223 reg_val |= RT5677_I2S_DF_PCM_B;
4224 break;
4225 default:
4226 return -EINVAL;
4227 }
4228
4229 switch (dai->id) {
4230 case RT5677_AIF1:
4231 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4232 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4233 RT5677_I2S_DF_MASK, reg_val);
4234 break;
4235 case RT5677_AIF2:
4236 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4237 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4238 RT5677_I2S_DF_MASK, reg_val);
4239 break;
4240 case RT5677_AIF3:
4241 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4242 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4243 RT5677_I2S_DF_MASK, reg_val);
4244 break;
4245 case RT5677_AIF4:
4246 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4247 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4248 RT5677_I2S_DF_MASK, reg_val);
4249 break;
4250 default:
4251 break;
4252 }
4253
4254
4255 return 0;
4256 }
4257
4258 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4259 int clk_id, unsigned int freq, int dir)
4260 {
4261 struct snd_soc_codec *codec = dai->codec;
4262 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4263 unsigned int reg_val = 0;
4264
4265 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4266 return 0;
4267
4268 switch (clk_id) {
4269 case RT5677_SCLK_S_MCLK:
4270 reg_val |= RT5677_SCLK_SRC_MCLK;
4271 break;
4272 case RT5677_SCLK_S_PLL1:
4273 reg_val |= RT5677_SCLK_SRC_PLL1;
4274 break;
4275 case RT5677_SCLK_S_RCCLK:
4276 reg_val |= RT5677_SCLK_SRC_RCCLK;
4277 break;
4278 default:
4279 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4280 return -EINVAL;
4281 }
4282 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4283 RT5677_SCLK_SRC_MASK, reg_val);
4284 rt5677->sysclk = freq;
4285 rt5677->sysclk_src = clk_id;
4286
4287 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4288
4289 return 0;
4290 }
4291
4292 /**
4293 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4294 * @freq_in: external clock provided to codec.
4295 * @freq_out: target clock which codec works on.
4296 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4297 *
4298 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4299 *
4300 * Returns 0 for success or negative error code.
4301 */
4302 static int rt5677_pll_calc(const unsigned int freq_in,
4303 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4304 {
4305 if (RT5677_PLL_INP_MIN > freq_in)
4306 return -EINVAL;
4307
4308 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4309 }
4310
4311 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4312 unsigned int freq_in, unsigned int freq_out)
4313 {
4314 struct snd_soc_codec *codec = dai->codec;
4315 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4316 struct rl6231_pll_code pll_code;
4317 int ret;
4318
4319 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4320 freq_out == rt5677->pll_out)
4321 return 0;
4322
4323 if (!freq_in || !freq_out) {
4324 dev_dbg(codec->dev, "PLL disabled\n");
4325
4326 rt5677->pll_in = 0;
4327 rt5677->pll_out = 0;
4328 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4329 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4330 return 0;
4331 }
4332
4333 switch (source) {
4334 case RT5677_PLL1_S_MCLK:
4335 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4336 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4337 break;
4338 case RT5677_PLL1_S_BCLK1:
4339 case RT5677_PLL1_S_BCLK2:
4340 case RT5677_PLL1_S_BCLK3:
4341 case RT5677_PLL1_S_BCLK4:
4342 switch (dai->id) {
4343 case RT5677_AIF1:
4344 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4345 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4346 break;
4347 case RT5677_AIF2:
4348 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4349 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4350 break;
4351 case RT5677_AIF3:
4352 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4353 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4354 break;
4355 case RT5677_AIF4:
4356 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4357 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4358 break;
4359 default:
4360 break;
4361 }
4362 break;
4363 default:
4364 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4365 return -EINVAL;
4366 }
4367
4368 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4369 if (ret < 0) {
4370 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4371 return ret;
4372 }
4373
4374 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4375 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4376 pll_code.n_code, pll_code.k_code);
4377
4378 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4379 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4380 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4381 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4382 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4383
4384 rt5677->pll_in = freq_in;
4385 rt5677->pll_out = freq_out;
4386 rt5677->pll_src = source;
4387
4388 return 0;
4389 }
4390
4391 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4392 unsigned int rx_mask, int slots, int slot_width)
4393 {
4394 struct snd_soc_codec *codec = dai->codec;
4395 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4396 unsigned int val = 0, slot_width_25 = 0;
4397
4398 if (rx_mask || tx_mask)
4399 val |= (1 << 12);
4400
4401 switch (slots) {
4402 case 4:
4403 val |= (1 << 10);
4404 break;
4405 case 6:
4406 val |= (2 << 10);
4407 break;
4408 case 8:
4409 val |= (3 << 10);
4410 break;
4411 case 2:
4412 default:
4413 break;
4414 }
4415
4416 switch (slot_width) {
4417 case 20:
4418 val |= (1 << 8);
4419 break;
4420 case 25:
4421 slot_width_25 = 0x8080;
4422 case 24:
4423 val |= (2 << 8);
4424 break;
4425 case 32:
4426 val |= (3 << 8);
4427 break;
4428 case 16:
4429 default:
4430 break;
4431 }
4432
4433 switch (dai->id) {
4434 case RT5677_AIF1:
4435 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4436 val);
4437 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4438 slot_width_25);
4439 break;
4440 case RT5677_AIF2:
4441 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4442 val);
4443 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4444 slot_width_25);
4445 break;
4446 default:
4447 break;
4448 }
4449
4450 return 0;
4451 }
4452
4453 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4454 enum snd_soc_bias_level level)
4455 {
4456 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4457
4458 switch (level) {
4459 case SND_SOC_BIAS_ON:
4460 break;
4461
4462 case SND_SOC_BIAS_PREPARE:
4463 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4464 rt5677_set_dsp_vad(codec, false);
4465
4466 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4467 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4468 0x0055);
4469 regmap_update_bits(rt5677->regmap,
4470 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4471 0x0f00, 0x0f00);
4472 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4473 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4474 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4475 RT5677_PWR_BG | RT5677_PWR_VREF2,
4476 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4477 RT5677_PWR_BG | RT5677_PWR_VREF2);
4478 rt5677->is_vref_slow = false;
4479 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4480 RT5677_PWR_CORE, RT5677_PWR_CORE);
4481 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4482 0x1, 0x1);
4483 }
4484 break;
4485
4486 case SND_SOC_BIAS_STANDBY:
4487 break;
4488
4489 case SND_SOC_BIAS_OFF:
4490 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4491 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4492 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4493 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4494 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4495 regmap_update_bits(rt5677->regmap,
4496 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4497
4498 if (rt5677->dsp_vad_en)
4499 rt5677_set_dsp_vad(codec, true);
4500 break;
4501
4502 default:
4503 break;
4504 }
4505
4506 return 0;
4507 }
4508
4509 #ifdef CONFIG_GPIOLIB
4510 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4511 {
4512 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4513
4514 switch (offset) {
4515 case RT5677_GPIO1 ... RT5677_GPIO5:
4516 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4517 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4518 break;
4519
4520 case RT5677_GPIO6:
4521 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4522 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4523 break;
4524
4525 default:
4526 break;
4527 }
4528 }
4529
4530 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4531 unsigned offset, int value)
4532 {
4533 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4534
4535 switch (offset) {
4536 case RT5677_GPIO1 ... RT5677_GPIO5:
4537 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4538 0x3 << (offset * 3 + 1),
4539 (0x2 | !!value) << (offset * 3 + 1));
4540 break;
4541
4542 case RT5677_GPIO6:
4543 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4544 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4545 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4546 break;
4547
4548 default:
4549 break;
4550 }
4551
4552 return 0;
4553 }
4554
4555 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4556 {
4557 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4558 int value, ret;
4559
4560 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4561 if (ret < 0)
4562 return ret;
4563
4564 return (value & (0x1 << offset)) >> offset;
4565 }
4566
4567 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4568 {
4569 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4570
4571 switch (offset) {
4572 case RT5677_GPIO1 ... RT5677_GPIO5:
4573 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4574 0x1 << (offset * 3 + 2), 0x0);
4575 break;
4576
4577 case RT5677_GPIO6:
4578 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4579 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4580 break;
4581
4582 default:
4583 break;
4584 }
4585
4586 return 0;
4587 }
4588
4589 /** Configures the gpio as
4590 * 0 - floating
4591 * 1 - pull down
4592 * 2 - pull up
4593 */
4594 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4595 int value)
4596 {
4597 int shift;
4598
4599 switch (offset) {
4600 case RT5677_GPIO1 ... RT5677_GPIO2:
4601 shift = 2 * (1 - offset);
4602 regmap_update_bits(rt5677->regmap,
4603 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4604 0x3 << shift,
4605 (value & 0x3) << shift);
4606 break;
4607
4608 case RT5677_GPIO3 ... RT5677_GPIO6:
4609 shift = 2 * (9 - offset);
4610 regmap_update_bits(rt5677->regmap,
4611 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4612 0x3 << shift,
4613 (value & 0x3) << shift);
4614 break;
4615
4616 default:
4617 break;
4618 }
4619 }
4620
4621 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4622 {
4623 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4624 struct regmap_irq_chip_data *data = rt5677->irq_data;
4625 int irq;
4626
4627 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4628 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4629 (rt5677->pdata.jd1_gpio == 2 &&
4630 offset == RT5677_GPIO2) ||
4631 (rt5677->pdata.jd1_gpio == 3 &&
4632 offset == RT5677_GPIO3)) {
4633 irq = RT5677_IRQ_JD1;
4634 } else {
4635 return -ENXIO;
4636 }
4637 }
4638
4639 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4640 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4641 (rt5677->pdata.jd2_gpio == 2 &&
4642 offset == RT5677_GPIO5) ||
4643 (rt5677->pdata.jd2_gpio == 3 &&
4644 offset == RT5677_GPIO6)) {
4645 irq = RT5677_IRQ_JD2;
4646 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4647 offset == RT5677_GPIO4) ||
4648 (rt5677->pdata.jd3_gpio == 2 &&
4649 offset == RT5677_GPIO5) ||
4650 (rt5677->pdata.jd3_gpio == 3 &&
4651 offset == RT5677_GPIO6)) {
4652 irq = RT5677_IRQ_JD3;
4653 } else {
4654 return -ENXIO;
4655 }
4656 }
4657
4658 return regmap_irq_get_virq(data, irq);
4659 }
4660
4661 static const struct gpio_chip rt5677_template_chip = {
4662 .label = "rt5677",
4663 .owner = THIS_MODULE,
4664 .direction_output = rt5677_gpio_direction_out,
4665 .set = rt5677_gpio_set,
4666 .direction_input = rt5677_gpio_direction_in,
4667 .get = rt5677_gpio_get,
4668 .to_irq = rt5677_to_irq,
4669 .can_sleep = 1,
4670 };
4671
4672 static void rt5677_init_gpio(struct i2c_client *i2c)
4673 {
4674 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4675 int ret;
4676
4677 rt5677->gpio_chip = rt5677_template_chip;
4678 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4679 rt5677->gpio_chip.parent = &i2c->dev;
4680 rt5677->gpio_chip.base = -1;
4681
4682 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4683 if (ret != 0)
4684 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4685 }
4686
4687 static void rt5677_free_gpio(struct i2c_client *i2c)
4688 {
4689 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4690
4691 gpiochip_remove(&rt5677->gpio_chip);
4692 }
4693 #else
4694 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4695 int value)
4696 {
4697 }
4698
4699 static void rt5677_init_gpio(struct i2c_client *i2c)
4700 {
4701 }
4702
4703 static void rt5677_free_gpio(struct i2c_client *i2c)
4704 {
4705 }
4706 #endif
4707
4708 static int rt5677_probe(struct snd_soc_codec *codec)
4709 {
4710 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4711 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4712 int i;
4713
4714 rt5677->codec = codec;
4715
4716 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4717 snd_soc_dapm_add_routes(dapm,
4718 rt5677_dmic2_clk_2,
4719 ARRAY_SIZE(rt5677_dmic2_clk_2));
4720 } else { /*use dmic1 clock by default*/
4721 snd_soc_dapm_add_routes(dapm,
4722 rt5677_dmic2_clk_1,
4723 ARRAY_SIZE(rt5677_dmic2_clk_1));
4724 }
4725
4726 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4727
4728 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4729 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4730
4731 for (i = 0; i < RT5677_GPIO_NUM; i++)
4732 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4733
4734 if (rt5677->irq_data) {
4735 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4736 0x8000);
4737 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4738 0x0008);
4739
4740 if (rt5677->pdata.jd1_gpio)
4741 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4742 RT5677_SEL_GPIO_JD1_MASK,
4743 rt5677->pdata.jd1_gpio <<
4744 RT5677_SEL_GPIO_JD1_SFT);
4745
4746 if (rt5677->pdata.jd2_gpio)
4747 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4748 RT5677_SEL_GPIO_JD2_MASK,
4749 rt5677->pdata.jd2_gpio <<
4750 RT5677_SEL_GPIO_JD2_SFT);
4751
4752 if (rt5677->pdata.jd3_gpio)
4753 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4754 RT5677_SEL_GPIO_JD3_MASK,
4755 rt5677->pdata.jd3_gpio <<
4756 RT5677_SEL_GPIO_JD3_SFT);
4757 }
4758
4759 mutex_init(&rt5677->dsp_cmd_lock);
4760 mutex_init(&rt5677->dsp_pri_lock);
4761
4762 return 0;
4763 }
4764
4765 static int rt5677_remove(struct snd_soc_codec *codec)
4766 {
4767 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4768
4769 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4770 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4771 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4772
4773 return 0;
4774 }
4775
4776 #ifdef CONFIG_PM
4777 static int rt5677_suspend(struct snd_soc_codec *codec)
4778 {
4779 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4780
4781 if (!rt5677->dsp_vad_en) {
4782 regcache_cache_only(rt5677->regmap, true);
4783 regcache_mark_dirty(rt5677->regmap);
4784
4785 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4786 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4787 }
4788
4789 return 0;
4790 }
4791
4792 static int rt5677_resume(struct snd_soc_codec *codec)
4793 {
4794 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4795
4796 if (!rt5677->dsp_vad_en) {
4797 rt5677->pll_src = 0;
4798 rt5677->pll_in = 0;
4799 rt5677->pll_out = 0;
4800 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4801 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4802 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4803 msleep(10);
4804
4805 regcache_cache_only(rt5677->regmap, false);
4806 regcache_sync(rt5677->regmap);
4807 }
4808
4809 return 0;
4810 }
4811 #else
4812 #define rt5677_suspend NULL
4813 #define rt5677_resume NULL
4814 #endif
4815
4816 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4817 {
4818 struct i2c_client *client = context;
4819 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4820
4821 if (rt5677->is_dsp_mode) {
4822 if (reg > 0xff) {
4823 mutex_lock(&rt5677->dsp_pri_lock);
4824 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4825 reg & 0xff);
4826 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4827 mutex_unlock(&rt5677->dsp_pri_lock);
4828 } else {
4829 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4830 }
4831 } else {
4832 regmap_read(rt5677->regmap_physical, reg, val);
4833 }
4834
4835 return 0;
4836 }
4837
4838 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4839 {
4840 struct i2c_client *client = context;
4841 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4842
4843 if (rt5677->is_dsp_mode) {
4844 if (reg > 0xff) {
4845 mutex_lock(&rt5677->dsp_pri_lock);
4846 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4847 reg & 0xff);
4848 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4849 val);
4850 mutex_unlock(&rt5677->dsp_pri_lock);
4851 } else {
4852 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4853 }
4854 } else {
4855 regmap_write(rt5677->regmap_physical, reg, val);
4856 }
4857
4858 return 0;
4859 }
4860
4861 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4862 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4863 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4864
4865 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4866 .hw_params = rt5677_hw_params,
4867 .set_fmt = rt5677_set_dai_fmt,
4868 .set_sysclk = rt5677_set_dai_sysclk,
4869 .set_pll = rt5677_set_dai_pll,
4870 .set_tdm_slot = rt5677_set_tdm_slot,
4871 };
4872
4873 static struct snd_soc_dai_driver rt5677_dai[] = {
4874 {
4875 .name = "rt5677-aif1",
4876 .id = RT5677_AIF1,
4877 .playback = {
4878 .stream_name = "AIF1 Playback",
4879 .channels_min = 1,
4880 .channels_max = 2,
4881 .rates = RT5677_STEREO_RATES,
4882 .formats = RT5677_FORMATS,
4883 },
4884 .capture = {
4885 .stream_name = "AIF1 Capture",
4886 .channels_min = 1,
4887 .channels_max = 2,
4888 .rates = RT5677_STEREO_RATES,
4889 .formats = RT5677_FORMATS,
4890 },
4891 .ops = &rt5677_aif_dai_ops,
4892 },
4893 {
4894 .name = "rt5677-aif2",
4895 .id = RT5677_AIF2,
4896 .playback = {
4897 .stream_name = "AIF2 Playback",
4898 .channels_min = 1,
4899 .channels_max = 2,
4900 .rates = RT5677_STEREO_RATES,
4901 .formats = RT5677_FORMATS,
4902 },
4903 .capture = {
4904 .stream_name = "AIF2 Capture",
4905 .channels_min = 1,
4906 .channels_max = 2,
4907 .rates = RT5677_STEREO_RATES,
4908 .formats = RT5677_FORMATS,
4909 },
4910 .ops = &rt5677_aif_dai_ops,
4911 },
4912 {
4913 .name = "rt5677-aif3",
4914 .id = RT5677_AIF3,
4915 .playback = {
4916 .stream_name = "AIF3 Playback",
4917 .channels_min = 1,
4918 .channels_max = 2,
4919 .rates = RT5677_STEREO_RATES,
4920 .formats = RT5677_FORMATS,
4921 },
4922 .capture = {
4923 .stream_name = "AIF3 Capture",
4924 .channels_min = 1,
4925 .channels_max = 2,
4926 .rates = RT5677_STEREO_RATES,
4927 .formats = RT5677_FORMATS,
4928 },
4929 .ops = &rt5677_aif_dai_ops,
4930 },
4931 {
4932 .name = "rt5677-aif4",
4933 .id = RT5677_AIF4,
4934 .playback = {
4935 .stream_name = "AIF4 Playback",
4936 .channels_min = 1,
4937 .channels_max = 2,
4938 .rates = RT5677_STEREO_RATES,
4939 .formats = RT5677_FORMATS,
4940 },
4941 .capture = {
4942 .stream_name = "AIF4 Capture",
4943 .channels_min = 1,
4944 .channels_max = 2,
4945 .rates = RT5677_STEREO_RATES,
4946 .formats = RT5677_FORMATS,
4947 },
4948 .ops = &rt5677_aif_dai_ops,
4949 },
4950 {
4951 .name = "rt5677-slimbus",
4952 .id = RT5677_AIF5,
4953 .playback = {
4954 .stream_name = "SLIMBus Playback",
4955 .channels_min = 1,
4956 .channels_max = 2,
4957 .rates = RT5677_STEREO_RATES,
4958 .formats = RT5677_FORMATS,
4959 },
4960 .capture = {
4961 .stream_name = "SLIMBus Capture",
4962 .channels_min = 1,
4963 .channels_max = 2,
4964 .rates = RT5677_STEREO_RATES,
4965 .formats = RT5677_FORMATS,
4966 },
4967 .ops = &rt5677_aif_dai_ops,
4968 },
4969 };
4970
4971 static const struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4972 .probe = rt5677_probe,
4973 .remove = rt5677_remove,
4974 .suspend = rt5677_suspend,
4975 .resume = rt5677_resume,
4976 .set_bias_level = rt5677_set_bias_level,
4977 .idle_bias_off = true,
4978 .component_driver = {
4979 .controls = rt5677_snd_controls,
4980 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4981 .dapm_widgets = rt5677_dapm_widgets,
4982 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4983 .dapm_routes = rt5677_dapm_routes,
4984 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4985 },
4986 };
4987
4988 static const struct regmap_config rt5677_regmap_physical = {
4989 .name = "physical",
4990 .reg_bits = 8,
4991 .val_bits = 16,
4992
4993 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4994 RT5677_PR_SPACING),
4995 .readable_reg = rt5677_readable_register,
4996
4997 .cache_type = REGCACHE_NONE,
4998 .ranges = rt5677_ranges,
4999 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5000 };
5001
5002 static const struct regmap_config rt5677_regmap = {
5003 .reg_bits = 8,
5004 .val_bits = 16,
5005
5006 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5007 RT5677_PR_SPACING),
5008
5009 .volatile_reg = rt5677_volatile_register,
5010 .readable_reg = rt5677_readable_register,
5011 .reg_read = rt5677_read,
5012 .reg_write = rt5677_write,
5013
5014 .cache_type = REGCACHE_RBTREE,
5015 .reg_defaults = rt5677_reg,
5016 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5017 .ranges = rt5677_ranges,
5018 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5019 };
5020
5021 static const struct i2c_device_id rt5677_i2c_id[] = {
5022 { "rt5677", RT5677 },
5023 { "rt5676", RT5676 },
5024 { }
5025 };
5026 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5027
5028 static const struct of_device_id rt5677_of_match[] = {
5029 { .compatible = "realtek,rt5677", },
5030 { }
5031 };
5032 MODULE_DEVICE_TABLE(of, rt5677_of_match);
5033
5034 #ifdef CONFIG_ACPI
5035 static const struct acpi_device_id rt5677_acpi_match[] = {
5036 { "RT5677CE", RT5677 },
5037 { }
5038 };
5039 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
5040 #endif
5041
5042 static void rt5677_read_acpi_properties(struct rt5677_priv *rt5677,
5043 struct device *dev)
5044 {
5045 u32 val;
5046
5047 if (!device_property_read_u32(dev, "DCLK", &val))
5048 rt5677->pdata.dmic2_clk_pin = val;
5049
5050 rt5677->pdata.in1_diff = device_property_read_bool(dev, "IN1");
5051 rt5677->pdata.in2_diff = device_property_read_bool(dev, "IN2");
5052 rt5677->pdata.lout1_diff = device_property_read_bool(dev, "OUT1");
5053 rt5677->pdata.lout2_diff = device_property_read_bool(dev, "OUT2");
5054 rt5677->pdata.lout3_diff = device_property_read_bool(dev, "OUT3");
5055
5056 device_property_read_u32(dev, "JD1", &rt5677->pdata.jd1_gpio);
5057 device_property_read_u32(dev, "JD2", &rt5677->pdata.jd2_gpio);
5058 device_property_read_u32(dev, "JD3", &rt5677->pdata.jd3_gpio);
5059 }
5060
5061 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5062 struct device *dev)
5063 {
5064 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5065 "realtek,in1-differential");
5066 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5067 "realtek,in2-differential");
5068 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5069 "realtek,lout1-differential");
5070 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5071 "realtek,lout2-differential");
5072 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5073 "realtek,lout3-differential");
5074
5075 device_property_read_u8_array(dev, "realtek,gpio-config",
5076 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5077
5078 device_property_read_u32(dev, "realtek,jd1-gpio",
5079 &rt5677->pdata.jd1_gpio);
5080 device_property_read_u32(dev, "realtek,jd2-gpio",
5081 &rt5677->pdata.jd2_gpio);
5082 device_property_read_u32(dev, "realtek,jd3-gpio",
5083 &rt5677->pdata.jd3_gpio);
5084 }
5085
5086 static struct regmap_irq rt5677_irqs[] = {
5087 [RT5677_IRQ_JD1] = {
5088 .reg_offset = 0,
5089 .mask = RT5677_EN_IRQ_GPIO_JD1,
5090 },
5091 [RT5677_IRQ_JD2] = {
5092 .reg_offset = 0,
5093 .mask = RT5677_EN_IRQ_GPIO_JD2,
5094 },
5095 [RT5677_IRQ_JD3] = {
5096 .reg_offset = 0,
5097 .mask = RT5677_EN_IRQ_GPIO_JD3,
5098 },
5099 };
5100
5101 static struct regmap_irq_chip rt5677_irq_chip = {
5102 .name = "rt5677",
5103 .irqs = rt5677_irqs,
5104 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5105
5106 .num_regs = 1,
5107 .status_base = RT5677_IRQ_CTRL1,
5108 .mask_base = RT5677_IRQ_CTRL1,
5109 .mask_invert = 1,
5110 };
5111
5112 static int rt5677_init_irq(struct i2c_client *i2c)
5113 {
5114 int ret;
5115 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5116
5117 if (!rt5677->pdata.jd1_gpio &&
5118 !rt5677->pdata.jd2_gpio &&
5119 !rt5677->pdata.jd3_gpio)
5120 return 0;
5121
5122 if (!i2c->irq) {
5123 dev_err(&i2c->dev, "No interrupt specified\n");
5124 return -EINVAL;
5125 }
5126
5127 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5128 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5129 &rt5677_irq_chip, &rt5677->irq_data);
5130
5131 if (ret != 0) {
5132 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5133 return ret;
5134 }
5135
5136 return 0;
5137 }
5138
5139 static void rt5677_free_irq(struct i2c_client *i2c)
5140 {
5141 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5142
5143 if (rt5677->irq_data)
5144 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5145 }
5146
5147 static int rt5677_i2c_probe(struct i2c_client *i2c,
5148 const struct i2c_device_id *id)
5149 {
5150 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5151 struct rt5677_priv *rt5677;
5152 int ret;
5153 unsigned int val;
5154
5155 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5156 GFP_KERNEL);
5157 if (rt5677 == NULL)
5158 return -ENOMEM;
5159
5160 i2c_set_clientdata(i2c, rt5677);
5161
5162 rt5677->type = id->driver_data;
5163
5164 if (pdata)
5165 rt5677->pdata = *pdata;
5166 else if (i2c->dev.of_node)
5167 rt5677_read_device_properties(rt5677, &i2c->dev);
5168 else if (ACPI_HANDLE(&i2c->dev))
5169 rt5677_read_acpi_properties(rt5677, &i2c->dev);
5170 else
5171 return -EINVAL;
5172
5173 /* pow-ldo2 and reset are optional. The codec pins may be statically
5174 * connected on the board without gpios. If the gpio device property
5175 * isn't specified, devm_gpiod_get_optional returns NULL.
5176 */
5177 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5178 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5179 if (IS_ERR(rt5677->pow_ldo2)) {
5180 ret = PTR_ERR(rt5677->pow_ldo2);
5181 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5182 return ret;
5183 }
5184 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5185 "realtek,reset", GPIOD_OUT_LOW);
5186 if (IS_ERR(rt5677->reset_pin)) {
5187 ret = PTR_ERR(rt5677->reset_pin);
5188 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5189 return ret;
5190 }
5191
5192 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5193 /* Wait a while until I2C bus becomes available. The datasheet
5194 * does not specify the exact we should wait but startup
5195 * sequence mentiones at least a few milliseconds.
5196 */
5197 msleep(10);
5198 }
5199
5200 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5201 &rt5677_regmap_physical);
5202 if (IS_ERR(rt5677->regmap_physical)) {
5203 ret = PTR_ERR(rt5677->regmap_physical);
5204 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5205 ret);
5206 return ret;
5207 }
5208
5209 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5210 if (IS_ERR(rt5677->regmap)) {
5211 ret = PTR_ERR(rt5677->regmap);
5212 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5213 ret);
5214 return ret;
5215 }
5216
5217 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5218 if (val != RT5677_DEVICE_ID) {
5219 dev_err(&i2c->dev,
5220 "Device with ID register %#x is not rt5677\n", val);
5221 return -ENODEV;
5222 }
5223
5224 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5225
5226 ret = regmap_register_patch(rt5677->regmap, init_list,
5227 ARRAY_SIZE(init_list));
5228 if (ret != 0)
5229 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5230
5231 if (rt5677->pdata.in1_diff)
5232 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5233 RT5677_IN_DF1, RT5677_IN_DF1);
5234
5235 if (rt5677->pdata.in2_diff)
5236 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5237 RT5677_IN_DF2, RT5677_IN_DF2);
5238
5239 if (rt5677->pdata.lout1_diff)
5240 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5241 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5242
5243 if (rt5677->pdata.lout2_diff)
5244 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5245 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5246
5247 if (rt5677->pdata.lout3_diff)
5248 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5249 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5250
5251 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5252 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5253 RT5677_GPIO5_FUNC_MASK,
5254 RT5677_GPIO5_FUNC_DMIC);
5255 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5256 RT5677_GPIO5_DIR_MASK,
5257 RT5677_GPIO5_DIR_OUT);
5258 }
5259
5260 if (rt5677->pdata.micbias1_vdd_3v3)
5261 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5262 RT5677_MICBIAS1_CTRL_VDD_MASK,
5263 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5264
5265 rt5677_init_gpio(i2c);
5266 rt5677_init_irq(i2c);
5267
5268 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5269 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5270 }
5271
5272 static int rt5677_i2c_remove(struct i2c_client *i2c)
5273 {
5274 snd_soc_unregister_codec(&i2c->dev);
5275 rt5677_free_irq(i2c);
5276 rt5677_free_gpio(i2c);
5277
5278 return 0;
5279 }
5280
5281 static struct i2c_driver rt5677_i2c_driver = {
5282 .driver = {
5283 .name = "rt5677",
5284 .of_match_table = rt5677_of_match,
5285 .acpi_match_table = ACPI_PTR(rt5677_acpi_match),
5286 },
5287 .probe = rt5677_i2c_probe,
5288 .remove = rt5677_i2c_remove,
5289 .id_table = rt5677_i2c_id,
5290 };
5291 module_i2c_driver(rt5677_i2c_driver);
5292
5293 MODULE_DESCRIPTION("ASoC RT5677 driver");
5294 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5295 MODULE_LICENSE("GPL v2");
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