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ASoC: sti: fix missing clk_disable_unprepare() on error in uni_player_start()
[mirror_ubuntu-zesty-kernel.git] / sound / soc / codecs / rt5677.c
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/regmap.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/firmware.h>
23 #include <linux/property.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31
32 #include "rl6231.h"
33 #include "rt5677.h"
34 #include "rt5677-spi.h"
35
36 #define RT5677_DEVICE_ID 0x6327
37
38 #define RT5677_PR_RANGE_BASE (0xff + 1)
39 #define RT5677_PR_SPACING 0x100
40
41 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
42
43 static const struct regmap_range_cfg rt5677_ranges[] = {
44 {
45 .name = "PR",
46 .range_min = RT5677_PR_BASE,
47 .range_max = RT5677_PR_BASE + 0xfd,
48 .selector_reg = RT5677_PRIV_INDEX,
49 .selector_mask = 0xff,
50 .selector_shift = 0x0,
51 .window_start = RT5677_PRIV_DATA,
52 .window_len = 0x1,
53 },
54 };
55
56 static const struct reg_sequence init_list[] = {
57 {RT5677_ASRC_12, 0x0018},
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
64 {RT5677_PR_BASE + 0x15, 0x0490},
65 {RT5677_PR_BASE + 0x38, 0x0f71},
66 {RT5677_PR_BASE + 0x39, 0x0f71},
67 };
68 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
69
70 static const struct reg_default rt5677_reg[] = {
71 {RT5677_RESET , 0x0000},
72 {RT5677_LOUT1 , 0xa800},
73 {RT5677_IN1 , 0x0000},
74 {RT5677_MICBIAS , 0x0000},
75 {RT5677_SLIMBUS_PARAM , 0x0000},
76 {RT5677_SLIMBUS_RX , 0x0000},
77 {RT5677_SLIMBUS_CTRL , 0x0000},
78 {RT5677_SIDETONE_CTRL , 0x000b},
79 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
80 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
81 {RT5677_DAC4_DIG_VOL , 0xafaf},
82 {RT5677_DAC3_DIG_VOL , 0xafaf},
83 {RT5677_DAC1_DIG_VOL , 0xafaf},
84 {RT5677_DAC2_DIG_VOL , 0xafaf},
85 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
86 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO1_2_ADC_BST , 0x0000},
89 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_ADC_BST_CTRL2 , 0x0000},
91 {RT5677_STO3_4_ADC_BST , 0x0000},
92 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_MIXER , 0xd4c0},
95 {RT5677_STO3_ADC_MIXER , 0xd4c0},
96 {RT5677_STO2_ADC_MIXER , 0xd4c0},
97 {RT5677_STO1_ADC_MIXER , 0xd4c0},
98 {RT5677_MONO_ADC_MIXER , 0xd4d1},
99 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
100 {RT5677_STO1_DAC_MIXER , 0xaaaa},
101 {RT5677_MONO_DAC_MIXER , 0xaaaa},
102 {RT5677_DD1_MIXER , 0xaaaa},
103 {RT5677_DD2_MIXER , 0xaaaa},
104 {RT5677_IF3_DATA , 0x0000},
105 {RT5677_IF4_DATA , 0x0000},
106 {RT5677_PDM_OUT_CTRL , 0x8888},
107 {RT5677_PDM_DATA_CTRL1 , 0x0000},
108 {RT5677_PDM_DATA_CTRL2 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
115 {RT5677_TDM1_CTRL1 , 0x0300},
116 {RT5677_TDM1_CTRL2 , 0x0000},
117 {RT5677_TDM1_CTRL3 , 0x4000},
118 {RT5677_TDM1_CTRL4 , 0x0123},
119 {RT5677_TDM1_CTRL5 , 0x4567},
120 {RT5677_TDM2_CTRL1 , 0x0300},
121 {RT5677_TDM2_CTRL2 , 0x0000},
122 {RT5677_TDM2_CTRL3 , 0x4000},
123 {RT5677_TDM2_CTRL4 , 0x0123},
124 {RT5677_TDM2_CTRL5 , 0x4567},
125 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
126 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
133 {RT5677_DMIC_CTRL1 , 0x1505},
134 {RT5677_DMIC_CTRL2 , 0x0055},
135 {RT5677_HAP_GENE_CTRL1 , 0x0111},
136 {RT5677_HAP_GENE_CTRL2 , 0x0064},
137 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
142 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
143 {RT5677_HAP_GENE_CTRL9 , 0xf000},
144 {RT5677_HAP_GENE_CTRL10 , 0x0000},
145 {RT5677_PWR_DIG1 , 0x0000},
146 {RT5677_PWR_DIG2 , 0x0000},
147 {RT5677_PWR_ANLG1 , 0x0055},
148 {RT5677_PWR_ANLG2 , 0x0000},
149 {RT5677_PWR_DSP1 , 0x0001},
150 {RT5677_PWR_DSP_ST , 0x0000},
151 {RT5677_PWR_DSP2 , 0x0000},
152 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
153 {RT5677_PRIV_INDEX , 0x0000},
154 {RT5677_PRIV_DATA , 0x0000},
155 {RT5677_I2S4_SDP , 0x8000},
156 {RT5677_I2S1_SDP , 0x8000},
157 {RT5677_I2S2_SDP , 0x8000},
158 {RT5677_I2S3_SDP , 0x8000},
159 {RT5677_CLK_TREE_CTRL1 , 0x1111},
160 {RT5677_CLK_TREE_CTRL2 , 0x1111},
161 {RT5677_CLK_TREE_CTRL3 , 0x0000},
162 {RT5677_PLL1_CTRL1 , 0x0000},
163 {RT5677_PLL1_CTRL2 , 0x0000},
164 {RT5677_PLL2_CTRL1 , 0x0c60},
165 {RT5677_PLL2_CTRL2 , 0x2000},
166 {RT5677_GLB_CLK1 , 0x0000},
167 {RT5677_GLB_CLK2 , 0x0000},
168 {RT5677_ASRC_1 , 0x0000},
169 {RT5677_ASRC_2 , 0x0000},
170 {RT5677_ASRC_3 , 0x0000},
171 {RT5677_ASRC_4 , 0x0000},
172 {RT5677_ASRC_5 , 0x0000},
173 {RT5677_ASRC_6 , 0x0000},
174 {RT5677_ASRC_7 , 0x0000},
175 {RT5677_ASRC_8 , 0x0000},
176 {RT5677_ASRC_9 , 0x0000},
177 {RT5677_ASRC_10 , 0x0000},
178 {RT5677_ASRC_11 , 0x0000},
179 {RT5677_ASRC_12 , 0x0018},
180 {RT5677_ASRC_13 , 0x0000},
181 {RT5677_ASRC_14 , 0x0000},
182 {RT5677_ASRC_15 , 0x0000},
183 {RT5677_ASRC_16 , 0x0000},
184 {RT5677_ASRC_17 , 0x0000},
185 {RT5677_ASRC_18 , 0x0000},
186 {RT5677_ASRC_19 , 0x0000},
187 {RT5677_ASRC_20 , 0x0000},
188 {RT5677_ASRC_21 , 0x000c},
189 {RT5677_ASRC_22 , 0x0000},
190 {RT5677_ASRC_23 , 0x0000},
191 {RT5677_VAD_CTRL1 , 0x2184},
192 {RT5677_VAD_CTRL2 , 0x010a},
193 {RT5677_VAD_CTRL3 , 0x0aea},
194 {RT5677_VAD_CTRL4 , 0x000c},
195 {RT5677_VAD_CTRL5 , 0x0000},
196 {RT5677_DSP_INB_CTRL1 , 0x0000},
197 {RT5677_DSP_INB_CTRL2 , 0x0000},
198 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
199 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
203 {RT5677_ADC_EQ_CTRL1 , 0x6000},
204 {RT5677_ADC_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL1 , 0xc000},
206 {RT5677_EQ_CTRL2 , 0x0000},
207 {RT5677_EQ_CTRL3 , 0x0000},
208 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
209 {RT5677_JD_CTRL1 , 0x0000},
210 {RT5677_JD_CTRL2 , 0x0000},
211 {RT5677_JD_CTRL3 , 0x0000},
212 {RT5677_IRQ_CTRL1 , 0x0000},
213 {RT5677_IRQ_CTRL2 , 0x0000},
214 {RT5677_GPIO_ST , 0x0000},
215 {RT5677_GPIO_CTRL1 , 0x0000},
216 {RT5677_GPIO_CTRL2 , 0x0000},
217 {RT5677_GPIO_CTRL3 , 0x0000},
218 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
219 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
227 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
228 {RT5677_MB_DRC_CTRL1 , 0x0f20},
229 {RT5677_DRC1_CTRL1 , 0x001f},
230 {RT5677_DRC1_CTRL2 , 0x020c},
231 {RT5677_DRC1_CTRL3 , 0x1f00},
232 {RT5677_DRC1_CTRL4 , 0x0000},
233 {RT5677_DRC1_CTRL5 , 0x0000},
234 {RT5677_DRC1_CTRL6 , 0x0029},
235 {RT5677_DRC2_CTRL1 , 0x001f},
236 {RT5677_DRC2_CTRL2 , 0x020c},
237 {RT5677_DRC2_CTRL3 , 0x1f00},
238 {RT5677_DRC2_CTRL4 , 0x0000},
239 {RT5677_DRC2_CTRL5 , 0x0000},
240 {RT5677_DRC2_CTRL6 , 0x0029},
241 {RT5677_DRC1_HL_CTRL1 , 0x8000},
242 {RT5677_DRC1_HL_CTRL2 , 0x0200},
243 {RT5677_DRC2_HL_CTRL1 , 0x8000},
244 {RT5677_DRC2_HL_CTRL2 , 0x0200},
245 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
258 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
259 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
261 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
262 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
263 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
265 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
266 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
267 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
268 {RT5677_DIG_MISC , 0x0000},
269 {RT5677_GEN_CTRL1 , 0x0000},
270 {RT5677_GEN_CTRL2 , 0x0000},
271 {RT5677_VENDOR_ID , 0x0000},
272 {RT5677_VENDOR_ID1 , 0x10ec},
273 {RT5677_VENDOR_ID2 , 0x6327},
274 };
275
276 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
277 {
278 int i;
279
280 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
281 if (reg >= rt5677_ranges[i].range_min &&
282 reg <= rt5677_ranges[i].range_max) {
283 return true;
284 }
285 }
286
287 switch (reg) {
288 case RT5677_RESET:
289 case RT5677_SLIMBUS_PARAM:
290 case RT5677_PDM_DATA_CTRL1:
291 case RT5677_PDM_DATA_CTRL2:
292 case RT5677_PDM1_DATA_CTRL4:
293 case RT5677_PDM2_DATA_CTRL4:
294 case RT5677_I2C_MASTER_CTRL1:
295 case RT5677_I2C_MASTER_CTRL7:
296 case RT5677_I2C_MASTER_CTRL8:
297 case RT5677_HAP_GENE_CTRL2:
298 case RT5677_PWR_DSP_ST:
299 case RT5677_PRIV_DATA:
300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320 }
321
322 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323 {
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541 }
542
543 /**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
554 {
555 struct snd_soc_codec *codec = rt5677->codec;
556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595 err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599 }
600
601 /**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
606 *
607 *
608 * Returns 0 for success or negative error code.
609 */
610 static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
612 {
613 struct snd_soc_codec *codec = rt5677->codec;
614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
643
644 err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648 }
649
650 /**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
661 {
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
663 value, 0x0001);
664 }
665
666 /**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
671 *
672 *
673 * Returns 0 for success or negative error code.
674 */
675 static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
677 {
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
680
681 *value &= 0xffff;
682
683 return ret;
684 }
685
686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
687 {
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
689
690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
696 }
697 }
698
699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700 {
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
706 return -ENXIO;
707
708 if (on && !activity) {
709 activity = true;
710
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
713
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
721 switch (rt5677->type) {
722 case RT5677:
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
724 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
726 RT5677_PLL2_PR_SRC_MASK |
727 RT5677_DSP_CLK_SRC_MASK,
728 RT5677_PLL2_PR_SRC_MCLK2 |
729 RT5677_DSP_CLK_SRC_BYPASS);
730 break;
731 case RT5676:
732 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
733 RT5677_DSP_CLK_SRC_MASK,
734 RT5677_DSP_CLK_SRC_BYPASS);
735 break;
736 default:
737 break;
738 }
739 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
740 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
741 rt5677_set_dsp_mode(codec, true);
742
743 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
744 codec->dev);
745 if (ret == 0) {
746 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
747 release_firmware(rt5677->fw1);
748 }
749
750 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
751 codec->dev);
752 if (ret == 0) {
753 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
754 release_firmware(rt5677->fw2);
755 }
756
757 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
758
759 regcache_cache_bypass(rt5677->regmap, false);
760 regcache_cache_only(rt5677->regmap, true);
761 } else if (!on && activity) {
762 activity = false;
763
764 regcache_cache_only(rt5677->regmap, false);
765 regcache_cache_bypass(rt5677->regmap, true);
766
767 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
768 rt5677_set_dsp_mode(codec, false);
769 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
770
771 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
772
773 regcache_cache_bypass(rt5677->regmap, false);
774 regcache_mark_dirty(rt5677->regmap);
775 regcache_sync(rt5677->regmap);
776 }
777
778 return 0;
779 }
780
781 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
782 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
783 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
784 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
786 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
787
788 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
789 static const DECLARE_TLV_DB_RANGE(bst_tlv,
790 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
791 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
792 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
793 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
794 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
795 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
796 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
797 );
798
799 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
800 struct snd_ctl_elem_value *ucontrol)
801 {
802 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
803 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
804
805 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
806
807 return 0;
808 }
809
810 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
811 struct snd_ctl_elem_value *ucontrol)
812 {
813 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
814 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
815 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
816
817 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
818
819 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
820 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
821
822 return 0;
823 }
824
825 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
826 /* OUTPUT Control */
827 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
828 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
829 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
830 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
831 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
832 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
833
834 /* DAC Digital Volume */
835 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
836 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
837 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
839 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
841 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
842 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
843
844 /* IN1/IN2 Control */
845 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
846 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
847
848 /* ADC Digital Volume Control */
849 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
850 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
851 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
858 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859
860 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
861 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
862 adc_vol_tlv),
863 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
864 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
865 adc_vol_tlv),
866 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
867 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
868 adc_vol_tlv),
869 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
870 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
871 adc_vol_tlv),
872 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
873 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
874 adc_vol_tlv),
875
876 /* Sidetone Control */
877 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
878 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
879
880 /* ADC Boost Volume Control */
881 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
882 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
883 adc_bst_tlv),
884 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
885 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
886 adc_bst_tlv),
887 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
888 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
889 adc_bst_tlv),
890 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
891 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
892 adc_bst_tlv),
893 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
894 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
895 adc_bst_tlv),
896
897 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
898 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
899 };
900
901 /**
902 * set_dmic_clk - Set parameter of dmic.
903 *
904 * @w: DAPM widget.
905 * @kcontrol: The kcontrol of this widget.
906 * @event: Event id.
907 *
908 * Choose dmic clock between 1MHz and 3MHz.
909 * It is better for clock to approximate 3MHz.
910 */
911 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
912 struct snd_kcontrol *kcontrol, int event)
913 {
914 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
915 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
916 int idx, rate;
917
918 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
919 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
920 idx = rl6231_calc_dmic_clk(rate);
921 if (idx < 0)
922 dev_err(codec->dev, "Failed to set DMIC clock\n");
923 else
924 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
925 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
926 return idx;
927 }
928
929 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
930 struct snd_soc_dapm_widget *sink)
931 {
932 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
933 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
934 unsigned int val;
935
936 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
937 val &= RT5677_SCLK_SRC_MASK;
938 if (val == RT5677_SCLK_SRC_PLL1)
939 return 1;
940 else
941 return 0;
942 }
943
944 static int is_using_asrc(struct snd_soc_dapm_widget *source,
945 struct snd_soc_dapm_widget *sink)
946 {
947 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
948 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
949 unsigned int reg, shift, val;
950
951 if (source->reg == RT5677_ASRC_1) {
952 switch (source->shift) {
953 case 12:
954 reg = RT5677_ASRC_4;
955 shift = 0;
956 break;
957 case 13:
958 reg = RT5677_ASRC_4;
959 shift = 4;
960 break;
961 case 14:
962 reg = RT5677_ASRC_4;
963 shift = 8;
964 break;
965 case 15:
966 reg = RT5677_ASRC_4;
967 shift = 12;
968 break;
969 default:
970 return 0;
971 }
972 } else {
973 switch (source->shift) {
974 case 0:
975 reg = RT5677_ASRC_6;
976 shift = 8;
977 break;
978 case 1:
979 reg = RT5677_ASRC_6;
980 shift = 12;
981 break;
982 case 2:
983 reg = RT5677_ASRC_5;
984 shift = 0;
985 break;
986 case 3:
987 reg = RT5677_ASRC_5;
988 shift = 4;
989 break;
990 case 4:
991 reg = RT5677_ASRC_5;
992 shift = 8;
993 break;
994 case 5:
995 reg = RT5677_ASRC_5;
996 shift = 12;
997 break;
998 case 12:
999 reg = RT5677_ASRC_3;
1000 shift = 0;
1001 break;
1002 case 13:
1003 reg = RT5677_ASRC_3;
1004 shift = 4;
1005 break;
1006 case 14:
1007 reg = RT5677_ASRC_3;
1008 shift = 12;
1009 break;
1010 default:
1011 return 0;
1012 }
1013 }
1014
1015 regmap_read(rt5677->regmap, reg, &val);
1016 val = (val >> shift) & 0xf;
1017
1018 switch (val) {
1019 case 1 ... 6:
1020 return 1;
1021 default:
1022 return 0;
1023 }
1024
1025 }
1026
1027 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1028 struct snd_soc_dapm_widget *sink)
1029 {
1030 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1031 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1032
1033 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1034 return 1;
1035
1036 return 0;
1037 }
1038
1039 /**
1040 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1041 * @codec: SoC audio codec device.
1042 * @filter_mask: mask of filters.
1043 * @clk_src: clock source
1044 *
1045 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1046 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1047 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1048 * ASRC function will track i2s clock and generate a corresponding system clock
1049 * for codec. This function provides an API to select the clock source for a
1050 * set of filters specified by the mask. And the codec driver will turn on ASRC
1051 * for these filters if ASRC is selected as their clock source.
1052 */
1053 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1054 unsigned int filter_mask, unsigned int clk_src)
1055 {
1056 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1057 unsigned int asrc3_mask = 0, asrc3_value = 0;
1058 unsigned int asrc4_mask = 0, asrc4_value = 0;
1059 unsigned int asrc5_mask = 0, asrc5_value = 0;
1060 unsigned int asrc6_mask = 0, asrc6_value = 0;
1061 unsigned int asrc7_mask = 0, asrc7_value = 0;
1062 unsigned int asrc8_mask = 0, asrc8_value = 0;
1063
1064 switch (clk_src) {
1065 case RT5677_CLK_SEL_SYS:
1066 case RT5677_CLK_SEL_I2S1_ASRC:
1067 case RT5677_CLK_SEL_I2S2_ASRC:
1068 case RT5677_CLK_SEL_I2S3_ASRC:
1069 case RT5677_CLK_SEL_I2S4_ASRC:
1070 case RT5677_CLK_SEL_I2S5_ASRC:
1071 case RT5677_CLK_SEL_I2S6_ASRC:
1072 case RT5677_CLK_SEL_SYS2:
1073 case RT5677_CLK_SEL_SYS3:
1074 case RT5677_CLK_SEL_SYS4:
1075 case RT5677_CLK_SEL_SYS5:
1076 case RT5677_CLK_SEL_SYS6:
1077 case RT5677_CLK_SEL_SYS7:
1078 break;
1079
1080 default:
1081 return -EINVAL;
1082 }
1083
1084 /* ASRC 3 */
1085 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1086 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1087 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1088 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1092 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1093 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1094 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1098 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1099 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1100 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1101 }
1102
1103 if (asrc3_mask)
1104 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1105 asrc3_value);
1106
1107 /* ASRC 4 */
1108 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1109 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1110 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1111 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1112 }
1113
1114 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1115 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1116 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1117 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1118 }
1119
1120 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1121 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1122 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1123 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1124 }
1125
1126 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1127 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1128 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1129 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1130 }
1131
1132 if (asrc4_mask)
1133 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1134 asrc4_value);
1135
1136 /* ASRC 5 */
1137 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1138 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1139 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1140 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1141 }
1142
1143 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1144 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1145 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1146 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1147 }
1148
1149 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1150 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1151 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1152 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1153 }
1154
1155 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1156 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1157 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1158 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1159 }
1160
1161 if (asrc5_mask)
1162 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1163 asrc5_value);
1164
1165 /* ASRC 6 */
1166 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1167 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1168 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1169 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1170 }
1171
1172 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1173 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1174 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1175 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1176 }
1177
1178 if (asrc6_mask)
1179 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1180 asrc6_value);
1181
1182 /* ASRC 7 */
1183 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1184 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1185 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1186 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1187 }
1188
1189 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1190 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1191 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1192 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1193 }
1194
1195 if (asrc7_mask)
1196 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1197 asrc7_value);
1198
1199 /* ASRC 8 */
1200 if (filter_mask & RT5677_I2S1_SOURCE) {
1201 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1202 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1203 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1204 }
1205
1206 if (filter_mask & RT5677_I2S2_SOURCE) {
1207 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1208 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1209 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1210 }
1211
1212 if (filter_mask & RT5677_I2S3_SOURCE) {
1213 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1214 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1215 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1216 }
1217
1218 if (filter_mask & RT5677_I2S4_SOURCE) {
1219 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1220 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1221 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1222 }
1223
1224 if (asrc8_mask)
1225 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1226 asrc8_value);
1227
1228 return 0;
1229 }
1230 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1231
1232 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1233 struct snd_soc_dapm_widget *sink)
1234 {
1235 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1236 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1237 unsigned int asrc_setting;
1238
1239 switch (source->shift) {
1240 case 11:
1241 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1242 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1243 RT5677_AD_STO1_CLK_SEL_SFT;
1244 break;
1245
1246 case 10:
1247 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1248 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1249 RT5677_AD_STO2_CLK_SEL_SFT;
1250 break;
1251
1252 case 9:
1253 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1254 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1255 RT5677_AD_STO3_CLK_SEL_SFT;
1256 break;
1257
1258 case 8:
1259 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1260 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1261 RT5677_AD_STO4_CLK_SEL_SFT;
1262 break;
1263
1264 case 7:
1265 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1266 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1267 RT5677_AD_MONOL_CLK_SEL_SFT;
1268 break;
1269
1270 case 6:
1271 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1272 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1273 RT5677_AD_MONOR_CLK_SEL_SFT;
1274 break;
1275
1276 default:
1277 return 0;
1278 }
1279
1280 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1281 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1282 return 1;
1283
1284 return 0;
1285 }
1286
1287 /* Digital Mixer */
1288 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1289 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1290 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1291 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1292 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1293 };
1294
1295 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1296 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1297 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1298 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1299 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1300 };
1301
1302 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1303 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1304 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1305 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1306 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1307 };
1308
1309 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1310 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1311 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1312 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1313 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1314 };
1315
1316 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1317 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1318 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1319 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1320 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1321 };
1322
1323 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1324 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1325 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1326 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1327 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1328 };
1329
1330 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1331 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1332 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1333 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1334 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1335 };
1336
1337 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1338 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1339 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1340 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1341 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1342 };
1343
1344 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1345 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1346 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1347 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1348 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1349 };
1350
1351 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1352 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1353 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1354 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1355 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1356 };
1357
1358 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1359 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1360 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1361 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1362 RT5677_M_DAC1_L_SFT, 1, 1),
1363 };
1364
1365 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1366 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1367 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1368 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1369 RT5677_M_DAC1_R_SFT, 1, 1),
1370 };
1371
1372 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1373 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1374 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1375 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1376 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1377 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1378 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1379 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1380 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1381 };
1382
1383 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1384 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1385 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1386 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1387 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1388 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1389 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1390 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1391 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1392 };
1393
1394 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1395 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1396 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1397 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1398 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1399 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1400 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1401 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1402 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1403 };
1404
1405 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1406 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1407 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1408 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1409 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1410 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1411 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1412 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1413 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1414 };
1415
1416 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1417 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1418 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1419 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1420 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1421 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1422 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1423 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1424 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1425 };
1426
1427 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1428 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1429 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1430 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1431 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1432 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1433 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1434 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1435 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1436 };
1437
1438 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1439 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1440 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1441 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1442 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1443 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1444 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1445 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1446 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1447 };
1448
1449 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1450 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1451 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1452 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1453 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1454 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1455 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1456 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1457 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1458 };
1459
1460 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1461 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1462 RT5677_DSP_IB_01_H_SFT, 1, 1),
1463 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1464 RT5677_DSP_IB_23_H_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1466 RT5677_DSP_IB_45_H_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1468 RT5677_DSP_IB_6_H_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1470 RT5677_DSP_IB_7_H_SFT, 1, 1),
1471 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1472 RT5677_DSP_IB_8_H_SFT, 1, 1),
1473 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1474 RT5677_DSP_IB_9_H_SFT, 1, 1),
1475 };
1476
1477 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1478 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1479 RT5677_DSP_IB_01_L_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1481 RT5677_DSP_IB_23_L_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1483 RT5677_DSP_IB_45_L_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1485 RT5677_DSP_IB_6_L_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1487 RT5677_DSP_IB_7_L_SFT, 1, 1),
1488 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1489 RT5677_DSP_IB_8_L_SFT, 1, 1),
1490 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1491 RT5677_DSP_IB_9_L_SFT, 1, 1),
1492 };
1493
1494 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1495 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1496 RT5677_DSP_IB_01_H_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1498 RT5677_DSP_IB_23_H_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1500 RT5677_DSP_IB_45_H_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1502 RT5677_DSP_IB_6_H_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1504 RT5677_DSP_IB_7_H_SFT, 1, 1),
1505 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1506 RT5677_DSP_IB_8_H_SFT, 1, 1),
1507 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1508 RT5677_DSP_IB_9_H_SFT, 1, 1),
1509 };
1510
1511 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1512 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1513 RT5677_DSP_IB_01_L_SFT, 1, 1),
1514 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1515 RT5677_DSP_IB_23_L_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1517 RT5677_DSP_IB_45_L_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1519 RT5677_DSP_IB_6_L_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1521 RT5677_DSP_IB_7_L_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1523 RT5677_DSP_IB_8_L_SFT, 1, 1),
1524 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1525 RT5677_DSP_IB_9_L_SFT, 1, 1),
1526 };
1527
1528 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1529 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1530 RT5677_DSP_IB_01_H_SFT, 1, 1),
1531 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1532 RT5677_DSP_IB_23_H_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1534 RT5677_DSP_IB_45_H_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1536 RT5677_DSP_IB_6_H_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1538 RT5677_DSP_IB_7_H_SFT, 1, 1),
1539 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1540 RT5677_DSP_IB_8_H_SFT, 1, 1),
1541 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1542 RT5677_DSP_IB_9_H_SFT, 1, 1),
1543 };
1544
1545 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1546 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1547 RT5677_DSP_IB_01_L_SFT, 1, 1),
1548 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1549 RT5677_DSP_IB_23_L_SFT, 1, 1),
1550 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1551 RT5677_DSP_IB_45_L_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1553 RT5677_DSP_IB_6_L_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1555 RT5677_DSP_IB_7_L_SFT, 1, 1),
1556 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1557 RT5677_DSP_IB_8_L_SFT, 1, 1),
1558 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1559 RT5677_DSP_IB_9_L_SFT, 1, 1),
1560 };
1561
1562
1563 /* Mux */
1564 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1565 static const char * const rt5677_dac1_src[] = {
1566 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1567 "OB 01"
1568 };
1569
1570 static SOC_ENUM_SINGLE_DECL(
1571 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1572 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1573
1574 static const struct snd_kcontrol_new rt5677_dac1_mux =
1575 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1576
1577 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1578 static const char * const rt5677_adda1_src[] = {
1579 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1580 };
1581
1582 static SOC_ENUM_SINGLE_DECL(
1583 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1584 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1585
1586 static const struct snd_kcontrol_new rt5677_adda1_mux =
1587 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1588
1589
1590 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1591 static const char * const rt5677_dac2l_src[] = {
1592 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1593 "OB 2",
1594 };
1595
1596 static SOC_ENUM_SINGLE_DECL(
1597 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1598 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1599
1600 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1601 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1602
1603 static const char * const rt5677_dac2r_src[] = {
1604 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1605 "OB 3", "Haptic Generator", "VAD ADC"
1606 };
1607
1608 static SOC_ENUM_SINGLE_DECL(
1609 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1610 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1611
1612 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1613 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1614
1615 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1616 static const char * const rt5677_dac3l_src[] = {
1617 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1618 "SLB DAC 4", "OB 4"
1619 };
1620
1621 static SOC_ENUM_SINGLE_DECL(
1622 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1623 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1624
1625 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1626 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1627
1628 static const char * const rt5677_dac3r_src[] = {
1629 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1630 "SLB DAC 5", "OB 5"
1631 };
1632
1633 static SOC_ENUM_SINGLE_DECL(
1634 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1635 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1636
1637 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1638 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1639
1640 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1641 static const char * const rt5677_dac4l_src[] = {
1642 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1643 "SLB DAC 6", "OB 6"
1644 };
1645
1646 static SOC_ENUM_SINGLE_DECL(
1647 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1648 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1649
1650 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1651 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1652
1653 static const char * const rt5677_dac4r_src[] = {
1654 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1655 "SLB DAC 7", "OB 7"
1656 };
1657
1658 static SOC_ENUM_SINGLE_DECL(
1659 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1660 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1661
1662 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1663 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1664
1665 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1666 static const char * const rt5677_iob_bypass_src[] = {
1667 "Bypass", "Pass SRC"
1668 };
1669
1670 static SOC_ENUM_SINGLE_DECL(
1671 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1672 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1673
1674 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1675 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1676
1677 static SOC_ENUM_SINGLE_DECL(
1678 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1679 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1680
1681 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1682 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1683
1684 static SOC_ENUM_SINGLE_DECL(
1685 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1686 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1687
1688 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1689 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1690
1691 static SOC_ENUM_SINGLE_DECL(
1692 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1693 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1694
1695 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1696 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1697
1698 static SOC_ENUM_SINGLE_DECL(
1699 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1700 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1701
1702 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1703 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1704
1705 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1706 static const char * const rt5677_stereo_adc2_src[] = {
1707 "DD MIX1", "DMIC", "Stereo DAC MIX"
1708 };
1709
1710 static SOC_ENUM_SINGLE_DECL(
1711 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1712 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1713
1714 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1715 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1716
1717 static SOC_ENUM_SINGLE_DECL(
1718 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1719 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1720
1721 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1722 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1723
1724 static SOC_ENUM_SINGLE_DECL(
1725 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1726 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1727
1728 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1729 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1730
1731 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1732 static const char * const rt5677_dmic_src[] = {
1733 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1734 };
1735
1736 static SOC_ENUM_SINGLE_DECL(
1737 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1738 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1739
1740 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1741 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1742
1743 static SOC_ENUM_SINGLE_DECL(
1744 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1745 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1746
1747 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1748 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1749
1750 static SOC_ENUM_SINGLE_DECL(
1751 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1752 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1753
1754 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1755 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1756
1757 static SOC_ENUM_SINGLE_DECL(
1758 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1759 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1760
1761 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1762 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1763
1764 static SOC_ENUM_SINGLE_DECL(
1765 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1766 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1767
1768 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1769 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1770
1771 static SOC_ENUM_SINGLE_DECL(
1772 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1773 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1774
1775 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1776 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1777
1778 /* Stereo2 ADC Source */ /* MX-26 [0] */
1779 static const char * const rt5677_stereo2_adc_lr_src[] = {
1780 "L", "LR"
1781 };
1782
1783 static SOC_ENUM_SINGLE_DECL(
1784 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1785 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1786
1787 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1788 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1789
1790 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1791 static const char * const rt5677_stereo_adc1_src[] = {
1792 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1793 };
1794
1795 static SOC_ENUM_SINGLE_DECL(
1796 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1797 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1798
1799 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1800 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1801
1802 static SOC_ENUM_SINGLE_DECL(
1803 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1804 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1805
1806 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1807 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1808
1809 static SOC_ENUM_SINGLE_DECL(
1810 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1811 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1812
1813 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1814 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1815
1816 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1817 static const char * const rt5677_mono_adc2_l_src[] = {
1818 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1819 };
1820
1821 static SOC_ENUM_SINGLE_DECL(
1822 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1823 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1824
1825 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1826 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1827
1828 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1829 static const char * const rt5677_mono_adc1_l_src[] = {
1830 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1831 };
1832
1833 static SOC_ENUM_SINGLE_DECL(
1834 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1835 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1836
1837 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1838 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1839
1840 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1841 static const char * const rt5677_mono_adc2_r_src[] = {
1842 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1843 };
1844
1845 static SOC_ENUM_SINGLE_DECL(
1846 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1847 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1848
1849 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1850 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1851
1852 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1853 static const char * const rt5677_mono_adc1_r_src[] = {
1854 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1855 };
1856
1857 static SOC_ENUM_SINGLE_DECL(
1858 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1859 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1860
1861 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1862 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1863
1864 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1865 static const char * const rt5677_stereo4_adc2_src[] = {
1866 "DD MIX1", "DMIC", "DD MIX2"
1867 };
1868
1869 static SOC_ENUM_SINGLE_DECL(
1870 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1871 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1872
1873 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1874 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1875
1876
1877 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1878 static const char * const rt5677_stereo4_adc1_src[] = {
1879 "DD MIX1", "ADC1/2", "DD MIX2"
1880 };
1881
1882 static SOC_ENUM_SINGLE_DECL(
1883 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1884 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1885
1886 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1887 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1888
1889 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1890 static const char * const rt5677_inbound01_src[] = {
1891 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1892 "VAD ADC/DAC1 FS"
1893 };
1894
1895 static SOC_ENUM_SINGLE_DECL(
1896 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1897 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1898
1899 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1900 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1901
1902 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1903 static const char * const rt5677_inbound23_src[] = {
1904 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1905 "DAC1 FS", "IF4 DAC"
1906 };
1907
1908 static SOC_ENUM_SINGLE_DECL(
1909 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1910 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1911
1912 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1913 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1914
1915 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1916 static const char * const rt5677_inbound45_src[] = {
1917 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1918 "IF3 DAC"
1919 };
1920
1921 static SOC_ENUM_SINGLE_DECL(
1922 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1923 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1924
1925 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1926 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1927
1928 /* InBound6 Source */ /* MX-A3 [2:0] */
1929 static const char * const rt5677_inbound6_src[] = {
1930 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1931 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1932 };
1933
1934 static SOC_ENUM_SINGLE_DECL(
1935 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1936 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1937
1938 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1939 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1940
1941 /* InBound7 Source */ /* MX-A4 [14:12] */
1942 static const char * const rt5677_inbound7_src[] = {
1943 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1944 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1945 };
1946
1947 static SOC_ENUM_SINGLE_DECL(
1948 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1949 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1950
1951 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1952 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1953
1954 /* InBound8 Source */ /* MX-A4 [10:8] */
1955 static const char * const rt5677_inbound8_src[] = {
1956 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1957 "MONO ADC MIX L", "DACL1 FS"
1958 };
1959
1960 static SOC_ENUM_SINGLE_DECL(
1961 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1962 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1963
1964 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1965 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1966
1967 /* InBound9 Source */ /* MX-A4 [6:4] */
1968 static const char * const rt5677_inbound9_src[] = {
1969 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1970 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1971 };
1972
1973 static SOC_ENUM_SINGLE_DECL(
1974 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1975 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1976
1977 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1978 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1979
1980 /* VAD Source */ /* MX-9F [6:4] */
1981 static const char * const rt5677_vad_src[] = {
1982 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1983 "STO3 ADC MIX L"
1984 };
1985
1986 static SOC_ENUM_SINGLE_DECL(
1987 rt5677_vad_enum, RT5677_VAD_CTRL4,
1988 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1989
1990 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1991 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1992
1993 /* Sidetone Source */ /* MX-13 [11:9] */
1994 static const char * const rt5677_sidetone_src[] = {
1995 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1996 };
1997
1998 static SOC_ENUM_SINGLE_DECL(
1999 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2000 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2001
2002 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2003 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2004
2005 /* DAC1/2 Source */ /* MX-15 [1:0] */
2006 static const char * const rt5677_dac12_src[] = {
2007 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2008 };
2009
2010 static SOC_ENUM_SINGLE_DECL(
2011 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2012 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2013
2014 static const struct snd_kcontrol_new rt5677_dac12_mux =
2015 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2016
2017 /* DAC3 Source */ /* MX-15 [5:4] */
2018 static const char * const rt5677_dac3_src[] = {
2019 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2020 };
2021
2022 static SOC_ENUM_SINGLE_DECL(
2023 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2024 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2025
2026 static const struct snd_kcontrol_new rt5677_dac3_mux =
2027 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2028
2029 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2030 static const char * const rt5677_pdm_src[] = {
2031 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2032 };
2033
2034 static SOC_ENUM_SINGLE_DECL(
2035 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2036 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2037
2038 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2039 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2040
2041 static SOC_ENUM_SINGLE_DECL(
2042 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2043 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2044
2045 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2046 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2047
2048 static SOC_ENUM_SINGLE_DECL(
2049 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2050 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2051
2052 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2053 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2054
2055 static SOC_ENUM_SINGLE_DECL(
2056 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2057 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2058
2059 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2060 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2061
2062 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2063 static const char * const rt5677_if12_adc1_src[] = {
2064 "STO1 ADC MIX", "OB01", "VAD ADC"
2065 };
2066
2067 static SOC_ENUM_SINGLE_DECL(
2068 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2069 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2070
2071 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2072 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2073
2074 static SOC_ENUM_SINGLE_DECL(
2075 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2076 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2077
2078 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2079 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2080
2081 static SOC_ENUM_SINGLE_DECL(
2082 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2083 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2084
2085 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2086 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2087
2088 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2089 static const char * const rt5677_if12_adc2_src[] = {
2090 "STO2 ADC MIX", "OB23"
2091 };
2092
2093 static SOC_ENUM_SINGLE_DECL(
2094 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2095 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2096
2097 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2098 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2099
2100 static SOC_ENUM_SINGLE_DECL(
2101 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2102 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2103
2104 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2105 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2106
2107 static SOC_ENUM_SINGLE_DECL(
2108 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2109 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2110
2111 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2112 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2113
2114 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2115 static const char * const rt5677_if12_adc3_src[] = {
2116 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2117 };
2118
2119 static SOC_ENUM_SINGLE_DECL(
2120 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2121 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2122
2123 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2124 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2125
2126 static SOC_ENUM_SINGLE_DECL(
2127 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2128 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2129
2130 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2131 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2132
2133 static SOC_ENUM_SINGLE_DECL(
2134 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2135 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2136
2137 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2138 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2139
2140 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2141 static const char * const rt5677_if12_adc4_src[] = {
2142 "STO4 ADC MIX", "OB67", "OB01"
2143 };
2144
2145 static SOC_ENUM_SINGLE_DECL(
2146 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2147 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2148
2149 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2150 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2151
2152 static SOC_ENUM_SINGLE_DECL(
2153 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2154 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2155
2156 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2157 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2158
2159 static SOC_ENUM_SINGLE_DECL(
2160 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2161 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2162
2163 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2164 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2165
2166 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2167 static const char * const rt5677_if34_adc_src[] = {
2168 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2169 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2170 };
2171
2172 static SOC_ENUM_SINGLE_DECL(
2173 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2174 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2175
2176 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2177 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2178
2179 static SOC_ENUM_SINGLE_DECL(
2180 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2181 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2182
2183 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2184 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2185
2186 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2187 static const char * const rt5677_if12_adc_swap_src[] = {
2188 "L/R", "R/L", "L/L", "R/R"
2189 };
2190
2191 static SOC_ENUM_SINGLE_DECL(
2192 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2193 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2194
2195 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2196 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2197
2198 static SOC_ENUM_SINGLE_DECL(
2199 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2200 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2201
2202 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2203 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2204
2205 static SOC_ENUM_SINGLE_DECL(
2206 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2207 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2208
2209 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2210 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2211
2212 static SOC_ENUM_SINGLE_DECL(
2213 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2214 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2215
2216 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2217 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2218
2219 static SOC_ENUM_SINGLE_DECL(
2220 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2221 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2222
2223 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2224 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2225
2226 static SOC_ENUM_SINGLE_DECL(
2227 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2228 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2229
2230 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2231 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2232
2233 static SOC_ENUM_SINGLE_DECL(
2234 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2235 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2236
2237 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2238 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2239
2240 static SOC_ENUM_SINGLE_DECL(
2241 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2242 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2243
2244 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2245 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2246
2247 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2248 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2249 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2250 "3/1/2/4", "3/4/1/2"
2251 };
2252
2253 static SOC_ENUM_SINGLE_DECL(
2254 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2255 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2256
2257 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2258 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2259
2260 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2261 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2262 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2263 "2/3/1/4", "3/4/1/2"
2264 };
2265
2266 static SOC_ENUM_SINGLE_DECL(
2267 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2268 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2269
2270 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2271 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2272
2273 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2274 MX-3F[14:12][10:8][6:4][2:0]
2275 MX-43[14:12][10:8][6:4][2:0]
2276 MX-44[14:12][10:8][6:4][2:0] */
2277 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2278 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2279 };
2280
2281 static SOC_ENUM_SINGLE_DECL(
2282 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2283 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2284
2285 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2286 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2287
2288 static SOC_ENUM_SINGLE_DECL(
2289 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2290 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2291
2292 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2293 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2294
2295 static SOC_ENUM_SINGLE_DECL(
2296 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2297 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2298
2299 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2300 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2301
2302 static SOC_ENUM_SINGLE_DECL(
2303 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2304 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2305
2306 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2307 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2308
2309 static SOC_ENUM_SINGLE_DECL(
2310 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2311 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2312
2313 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2314 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2315
2316 static SOC_ENUM_SINGLE_DECL(
2317 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2318 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2319
2320 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2321 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2322
2323 static SOC_ENUM_SINGLE_DECL(
2324 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2325 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2326
2327 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2328 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2329
2330 static SOC_ENUM_SINGLE_DECL(
2331 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2332 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2333
2334 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2335 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2336
2337 static SOC_ENUM_SINGLE_DECL(
2338 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2339 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2340
2341 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2342 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2343
2344 static SOC_ENUM_SINGLE_DECL(
2345 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2346 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2347
2348 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2349 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2350
2351 static SOC_ENUM_SINGLE_DECL(
2352 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2353 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2354
2355 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2356 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2357
2358 static SOC_ENUM_SINGLE_DECL(
2359 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2360 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2361
2362 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2363 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2364
2365 static SOC_ENUM_SINGLE_DECL(
2366 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2367 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2368
2369 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2370 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2371
2372 static SOC_ENUM_SINGLE_DECL(
2373 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2374 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2375
2376 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2377 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2378
2379 static SOC_ENUM_SINGLE_DECL(
2380 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2381 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2382
2383 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2384 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2385
2386 static SOC_ENUM_SINGLE_DECL(
2387 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2388 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2389
2390 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2391 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2392
2393 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2394 struct snd_kcontrol *kcontrol, int event)
2395 {
2396 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2397 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2398
2399 switch (event) {
2400 case SND_SOC_DAPM_POST_PMU:
2401 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2402 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2403 break;
2404
2405 case SND_SOC_DAPM_PRE_PMD:
2406 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2407 RT5677_PWR_BST1_P, 0);
2408 break;
2409
2410 default:
2411 return 0;
2412 }
2413
2414 return 0;
2415 }
2416
2417 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2418 struct snd_kcontrol *kcontrol, int event)
2419 {
2420 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2421 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2422
2423 switch (event) {
2424 case SND_SOC_DAPM_POST_PMU:
2425 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2426 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2427 break;
2428
2429 case SND_SOC_DAPM_PRE_PMD:
2430 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2431 RT5677_PWR_BST2_P, 0);
2432 break;
2433
2434 default:
2435 return 0;
2436 }
2437
2438 return 0;
2439 }
2440
2441 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2442 struct snd_kcontrol *kcontrol, int event)
2443 {
2444 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2445 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2446
2447 switch (event) {
2448 case SND_SOC_DAPM_PRE_PMU:
2449 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2450 break;
2451
2452 case SND_SOC_DAPM_POST_PMU:
2453 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2454 break;
2455
2456 default:
2457 return 0;
2458 }
2459
2460 return 0;
2461 }
2462
2463 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2464 struct snd_kcontrol *kcontrol, int event)
2465 {
2466 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2467 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2468
2469 switch (event) {
2470 case SND_SOC_DAPM_PRE_PMU:
2471 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2472 break;
2473
2474 case SND_SOC_DAPM_POST_PMU:
2475 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2476 break;
2477
2478 default:
2479 return 0;
2480 }
2481
2482 return 0;
2483 }
2484
2485 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2486 struct snd_kcontrol *kcontrol, int event)
2487 {
2488 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2489 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2490
2491 switch (event) {
2492 case SND_SOC_DAPM_POST_PMU:
2493 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2494 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2495 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2496 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2497 break;
2498
2499 case SND_SOC_DAPM_PRE_PMD:
2500 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2501 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2502 RT5677_PWR_CLK_MB, 0);
2503 break;
2504
2505 default:
2506 return 0;
2507 }
2508
2509 return 0;
2510 }
2511
2512 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2513 struct snd_kcontrol *kcontrol, int event)
2514 {
2515 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2516 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2517 unsigned int value;
2518
2519 switch (event) {
2520 case SND_SOC_DAPM_PRE_PMU:
2521 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2522 if (value & RT5677_IF1_ADC_CTRL_MASK)
2523 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2524 RT5677_IF1_ADC_MODE_MASK,
2525 RT5677_IF1_ADC_MODE_TDM);
2526 break;
2527
2528 default:
2529 return 0;
2530 }
2531
2532 return 0;
2533 }
2534
2535 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2536 struct snd_kcontrol *kcontrol, int event)
2537 {
2538 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2539 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2540 unsigned int value;
2541
2542 switch (event) {
2543 case SND_SOC_DAPM_PRE_PMU:
2544 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2545 if (value & RT5677_IF2_ADC_CTRL_MASK)
2546 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2547 RT5677_IF2_ADC_MODE_MASK,
2548 RT5677_IF2_ADC_MODE_TDM);
2549 break;
2550
2551 default:
2552 return 0;
2553 }
2554
2555 return 0;
2556 }
2557
2558 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2559 struct snd_kcontrol *kcontrol, int event)
2560 {
2561 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2562 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2563
2564 switch (event) {
2565 case SND_SOC_DAPM_POST_PMU:
2566 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2567 !rt5677->is_vref_slow) {
2568 mdelay(20);
2569 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2570 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2571 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2572 rt5677->is_vref_slow = true;
2573 }
2574 break;
2575
2576 default:
2577 return 0;
2578 }
2579
2580 return 0;
2581 }
2582
2583 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2584 struct snd_kcontrol *kcontrol, int event)
2585 {
2586 switch (event) {
2587 case SND_SOC_DAPM_POST_PMU:
2588 msleep(50);
2589 break;
2590
2591 default:
2592 return 0;
2593 }
2594
2595 return 0;
2596 }
2597
2598 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2599 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2600 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2601 SND_SOC_DAPM_POST_PMU),
2602 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2603 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2604 SND_SOC_DAPM_POST_PMU),
2605
2606 /* ASRC */
2607 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2609 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2613 0),
2614 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2615 0),
2616 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2617 0),
2618 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2619 0),
2620 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2621 0),
2622 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2623 0),
2624 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2625 0),
2626 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2627 0),
2628 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2629 0),
2630 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2631 0),
2632 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2633 0),
2634 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2635 0),
2636 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2638 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2640 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2641 0),
2642 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2643 0),
2644
2645 /* Input Side */
2646 /* micbias */
2647 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2648 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2649 SND_SOC_DAPM_POST_PMU),
2650
2651 /* Input Lines */
2652 SND_SOC_DAPM_INPUT("DMIC L1"),
2653 SND_SOC_DAPM_INPUT("DMIC R1"),
2654 SND_SOC_DAPM_INPUT("DMIC L2"),
2655 SND_SOC_DAPM_INPUT("DMIC R2"),
2656 SND_SOC_DAPM_INPUT("DMIC L3"),
2657 SND_SOC_DAPM_INPUT("DMIC R3"),
2658 SND_SOC_DAPM_INPUT("DMIC L4"),
2659 SND_SOC_DAPM_INPUT("DMIC R4"),
2660
2661 SND_SOC_DAPM_INPUT("IN1P"),
2662 SND_SOC_DAPM_INPUT("IN1N"),
2663 SND_SOC_DAPM_INPUT("IN2P"),
2664 SND_SOC_DAPM_INPUT("IN2N"),
2665
2666 SND_SOC_DAPM_INPUT("Haptic Generator"),
2667
2668 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2669 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2670 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2671 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2672
2673 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2674 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2676 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2677 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2678 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2680 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2681
2682 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2683 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2684
2685 /* Boost */
2686 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2687 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2688 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2689 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2690 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2691 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2692
2693 /* ADCs */
2694 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2695 0, 0),
2696 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2697 0, 0),
2698 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2699
2700 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2701 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2703 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2705 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2707 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2708
2709 /* ADC Mux */
2710 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2711 &rt5677_sto1_dmic_mux),
2712 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_sto1_adc1_mux),
2714 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_sto1_adc2_mux),
2716 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_sto2_dmic_mux),
2718 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_sto2_adc1_mux),
2720 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2721 &rt5677_sto2_adc2_mux),
2722 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_sto2_adc_lr_mux),
2724 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2725 &rt5677_sto3_dmic_mux),
2726 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto3_adc1_mux),
2728 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto3_adc2_mux),
2730 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto4_dmic_mux),
2732 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_sto4_adc1_mux),
2734 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sto4_adc2_mux),
2736 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_mono_dmic_l_mux),
2738 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_mono_dmic_r_mux),
2740 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_mono_adc2_l_mux),
2742 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_mono_adc1_l_mux),
2744 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_mono_adc1_r_mux),
2746 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_mono_adc2_r_mux),
2748
2749 /* ADC Mixer */
2750 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2751 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2753 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2755 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2757 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2759 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2760 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2761 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2762 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2763 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2764 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2765 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2766 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2767 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2768 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2769 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2770 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2771 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2772 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2773 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2774 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2775 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2776 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2777 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2778 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2779 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2780 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2781 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2782
2783 /* ADC PGA */
2784 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2785 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2786 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2800
2801 /* DSP */
2802 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5677_ib9_src_mux),
2804 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5677_ib8_src_mux),
2806 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5677_ib7_src_mux),
2808 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5677_ib6_src_mux),
2810 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5677_ib45_src_mux),
2812 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5677_ib23_src_mux),
2814 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5677_ib01_src_mux),
2816 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_ib45_bypass_src_mux),
2818 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ib23_bypass_src_mux),
2820 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ib01_bypass_src_mux),
2822 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_ob23_bypass_src_mux),
2824 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_ob01_bypass_src_mux),
2826
2827 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2828 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2829
2830 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2831 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2833 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2836
2837 /* Digital Interface */
2838 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2839 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2840 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2856
2857 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2858 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2875
2876 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2877 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2884
2885 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2886 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2893
2894 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2895 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2912
2913 /* Digital Interface Select */
2914 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5677_if1_adc1_mux),
2916 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5677_if1_adc2_mux),
2918 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5677_if1_adc3_mux),
2920 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5677_if1_adc4_mux),
2922 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5677_if1_adc1_swap_mux),
2924 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5677_if1_adc2_swap_mux),
2926 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5677_if1_adc3_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5677_if1_adc4_swap_mux),
2930 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2932 SND_SOC_DAPM_PRE_PMU),
2933 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2934 &rt5677_if2_adc1_mux),
2935 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2936 &rt5677_if2_adc2_mux),
2937 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5677_if2_adc3_mux),
2939 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5677_if2_adc4_mux),
2941 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5677_if2_adc1_swap_mux),
2943 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5677_if2_adc2_swap_mux),
2945 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5677_if2_adc3_swap_mux),
2947 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5677_if2_adc4_swap_mux),
2949 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2951 SND_SOC_DAPM_PRE_PMU),
2952 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5677_if3_adc_mux),
2954 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5677_if4_adc_mux),
2956 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5677_slb_adc1_mux),
2958 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5677_slb_adc2_mux),
2960 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5677_slb_adc3_mux),
2962 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5677_slb_adc4_mux),
2964
2965 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_if1_dac0_tdm_sel_mux),
2967 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5677_if1_dac1_tdm_sel_mux),
2969 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5677_if1_dac2_tdm_sel_mux),
2971 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5677_if1_dac3_tdm_sel_mux),
2973 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_if1_dac4_tdm_sel_mux),
2975 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5677_if1_dac5_tdm_sel_mux),
2977 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5677_if1_dac6_tdm_sel_mux),
2979 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5677_if1_dac7_tdm_sel_mux),
2981
2982 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5677_if2_dac0_tdm_sel_mux),
2984 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5677_if2_dac1_tdm_sel_mux),
2986 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5677_if2_dac2_tdm_sel_mux),
2988 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5677_if2_dac3_tdm_sel_mux),
2990 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5677_if2_dac4_tdm_sel_mux),
2992 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5677_if2_dac5_tdm_sel_mux),
2994 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5677_if2_dac6_tdm_sel_mux),
2996 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5677_if2_dac7_tdm_sel_mux),
2998
2999 /* Audio Interface */
3000 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3001 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3010
3011 /* Sidetone Mux */
3012 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3013 &rt5677_sidetone_mux),
3014 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3015 RT5677_ST_EN_SFT, 0, NULL, 0),
3016
3017 /* VAD Mux*/
3018 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3019 &rt5677_vad_src_mux),
3020
3021 /* Tensilica DSP */
3022 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3023 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3024 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3025 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3026 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3027 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3028 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3029 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3030 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3031 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3032 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3033 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3034 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3035
3036 /* Output Side */
3037 /* DAC mixer before sound effect */
3038 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3039 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3040 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3041 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3042 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3043
3044 /* DAC Mux */
3045 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3046 &rt5677_dac1_mux),
3047 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3048 &rt5677_adda1_mux),
3049 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3050 &rt5677_dac12_mux),
3051 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3052 &rt5677_dac3_mux),
3053
3054 /* DAC2 channel Mux */
3055 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3056 &rt5677_dac2_l_mux),
3057 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3058 &rt5677_dac2_r_mux),
3059
3060 /* DAC3 channel Mux */
3061 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3062 &rt5677_dac3_l_mux),
3063 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3064 &rt5677_dac3_r_mux),
3065
3066 /* DAC4 channel Mux */
3067 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3068 &rt5677_dac4_l_mux),
3069 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3070 &rt5677_dac4_r_mux),
3071
3072 /* DAC Mixer */
3073 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3074 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3075 SND_SOC_DAPM_POST_PMU),
3076 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3077 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3078 SND_SOC_DAPM_POST_PMU),
3079 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3080 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3081 SND_SOC_DAPM_POST_PMU),
3082 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3083 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3084 SND_SOC_DAPM_POST_PMU),
3085 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3086 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3087 SND_SOC_DAPM_POST_PMU),
3088 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3089 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3090 SND_SOC_DAPM_POST_PMU),
3091 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3092 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3093 SND_SOC_DAPM_POST_PMU),
3094
3095 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3096 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3097 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3098 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3099 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3100 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3101 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3102 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3103 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3104 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3105 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3106 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3107 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3108 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3109 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3110 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3111 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3112 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3113 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3114 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3115
3116 /* DACs */
3117 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3118 RT5677_PWR_DAC1_BIT, 0),
3119 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3120 RT5677_PWR_DAC2_BIT, 0),
3121 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3122 RT5677_PWR_DAC3_BIT, 0),
3123
3124 /* PDM */
3125 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3126 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3127 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3128 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3129
3130 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3131 1, &rt5677_pdm1_l_mux),
3132 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3133 1, &rt5677_pdm1_r_mux),
3134 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3135 1, &rt5677_pdm2_l_mux),
3136 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3137 1, &rt5677_pdm2_r_mux),
3138
3139 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3140 0, NULL, 0),
3141 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3142 0, NULL, 0),
3143 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3144 0, NULL, 0),
3145
3146 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3147 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3148 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3149 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3150 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3151 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3152
3153 /* Output Lines */
3154 SND_SOC_DAPM_OUTPUT("LOUT1"),
3155 SND_SOC_DAPM_OUTPUT("LOUT2"),
3156 SND_SOC_DAPM_OUTPUT("LOUT3"),
3157 SND_SOC_DAPM_OUTPUT("PDM1L"),
3158 SND_SOC_DAPM_OUTPUT("PDM1R"),
3159 SND_SOC_DAPM_OUTPUT("PDM2L"),
3160 SND_SOC_DAPM_OUTPUT("PDM2R"),
3161
3162 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3163 };
3164
3165 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3166 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3167 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3168 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3169 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3170 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3171 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3172 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3173 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3174 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3175 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3176
3177 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3178 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3179 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3180 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3181 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3182 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3183 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3184 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3185 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3186 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3187 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3188 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3189 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3190
3191 { "DMIC1", NULL, "DMIC L1" },
3192 { "DMIC1", NULL, "DMIC R1" },
3193 { "DMIC2", NULL, "DMIC L2" },
3194 { "DMIC2", NULL, "DMIC R2" },
3195 { "DMIC3", NULL, "DMIC L3" },
3196 { "DMIC3", NULL, "DMIC R3" },
3197 { "DMIC4", NULL, "DMIC L4" },
3198 { "DMIC4", NULL, "DMIC R4" },
3199
3200 { "DMIC L1", NULL, "DMIC CLK" },
3201 { "DMIC R1", NULL, "DMIC CLK" },
3202 { "DMIC L2", NULL, "DMIC CLK" },
3203 { "DMIC R2", NULL, "DMIC CLK" },
3204 { "DMIC L3", NULL, "DMIC CLK" },
3205 { "DMIC R3", NULL, "DMIC CLK" },
3206 { "DMIC L4", NULL, "DMIC CLK" },
3207 { "DMIC R4", NULL, "DMIC CLK" },
3208
3209 { "DMIC L1", NULL, "DMIC1 power" },
3210 { "DMIC R1", NULL, "DMIC1 power" },
3211 { "DMIC L3", NULL, "DMIC3 power" },
3212 { "DMIC R3", NULL, "DMIC3 power" },
3213 { "DMIC L4", NULL, "DMIC4 power" },
3214 { "DMIC R4", NULL, "DMIC4 power" },
3215
3216 { "BST1", NULL, "IN1P" },
3217 { "BST1", NULL, "IN1N" },
3218 { "BST2", NULL, "IN2P" },
3219 { "BST2", NULL, "IN2N" },
3220
3221 { "IN1P", NULL, "MICBIAS1" },
3222 { "IN1N", NULL, "MICBIAS1" },
3223 { "IN2P", NULL, "MICBIAS1" },
3224 { "IN2N", NULL, "MICBIAS1" },
3225
3226 { "ADC 1", NULL, "BST1" },
3227 { "ADC 1", NULL, "ADC 1 power" },
3228 { "ADC 1", NULL, "ADC1 clock" },
3229 { "ADC 2", NULL, "BST2" },
3230 { "ADC 2", NULL, "ADC 2 power" },
3231 { "ADC 2", NULL, "ADC2 clock" },
3232
3233 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3234 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3235 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3236 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3237
3238 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3239 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3240 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3241 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3242
3243 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3244 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3245 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3246 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3247
3248 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3249 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3250 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3251 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3252
3253 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3254 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3255 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3256 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3257
3258 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3259 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3260 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3261 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3262
3263 { "ADC 1_2", NULL, "ADC 1" },
3264 { "ADC 1_2", NULL, "ADC 2" },
3265
3266 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3267 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3268 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3269
3270 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3271 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3272 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3273
3274 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3275 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3276 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3277
3278 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3279 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3280 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3281
3282 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3283 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3284 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3285
3286 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3287 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3288 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3289
3290 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3291 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3292 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3293
3294 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3295 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3296 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3297
3298 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3299 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3300 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3301
3302 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3303 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3304 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3305
3306 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3307 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3308 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3309
3310 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3311 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3312 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3313
3314 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3315 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3316 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3317 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3318
3319 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3320 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3321 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3322 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3323 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3324
3325 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3326 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3327
3328 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3329 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3330 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3331 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3332
3333 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3334 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3335
3336 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3337 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3338
3339 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3340 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3341 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3342 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3343 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3344
3345 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3346 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3347
3348 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3349 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3350 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3351 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3352
3353 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3354 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3355 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3356 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3357 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3358
3359 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3360 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3361
3362 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3363 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3364 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3365 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3366
3367 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3368 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3369 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3370 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3371 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3372
3373 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3374 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3375
3376 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3377 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3378 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3379 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3380
3381 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3382 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3383 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3384 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3385
3386 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3387 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3388
3389 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3390 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3391 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3392 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3393 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3394
3395 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3396 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3397 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3398
3399 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3400 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3401
3402 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3403 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3404 { "IF1 ADC3 Mux", "OB45", "OB45" },
3405
3406 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3407 { "IF1 ADC4 Mux", "OB67", "OB67" },
3408 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3409
3410 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3411 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3412 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3413 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3414
3415 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3416 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3417 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3418 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3419
3420 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3421 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3422 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3423 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3424
3425 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3426 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3427 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3428 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3429
3430 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3431 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3432 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3433 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3434
3435 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3436 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3437 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3438 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3439 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3440 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3441 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3442 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3443
3444 { "AIF1TX", NULL, "I2S1" },
3445 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3446
3447 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3448 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3449 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3450
3451 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3452 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3453
3454 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3455 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3456 { "IF2 ADC3 Mux", "OB45", "OB45" },
3457
3458 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3459 { "IF2 ADC4 Mux", "OB67", "OB67" },
3460 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3461
3462 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3463 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3464 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3465 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3466
3467 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3468 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3469 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3470 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3471
3472 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3473 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3474 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3475 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3476
3477 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3478 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3479 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3480 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3481
3482 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3483 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3484 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3485 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3486
3487 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3488 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3489 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3490 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3491 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3492 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3493 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3494 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3495
3496 { "AIF2TX", NULL, "I2S2" },
3497 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3498
3499 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3500 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3501 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3502 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3503 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3504 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3505 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3506 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3507
3508 { "AIF3TX", NULL, "I2S3" },
3509 { "AIF3TX", NULL, "IF3 ADC Mux" },
3510
3511 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3512 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3513 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3514 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3515 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3516 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3517 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3518 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3519
3520 { "AIF4TX", NULL, "I2S4" },
3521 { "AIF4TX", NULL, "IF4 ADC Mux" },
3522
3523 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3524 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3525 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3526
3527 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3528 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3529
3530 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3531 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3532 { "SLB ADC3 Mux", "OB45", "OB45" },
3533
3534 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3535 { "SLB ADC4 Mux", "OB67", "OB67" },
3536 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3537
3538 { "SLBTX", NULL, "SLB" },
3539 { "SLBTX", NULL, "SLB ADC1 Mux" },
3540 { "SLBTX", NULL, "SLB ADC2 Mux" },
3541 { "SLBTX", NULL, "SLB ADC3 Mux" },
3542 { "SLBTX", NULL, "SLB ADC4 Mux" },
3543
3544 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3545 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3546 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3547 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3548 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3549
3550 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3551 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3552
3553 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3554 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3555 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3556 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3557 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3558 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3559
3560 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3561 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3562
3563 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3564 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3565 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3566 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3567 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3568
3569 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3570 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3571
3572 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3573 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3574 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3575 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3576 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3577 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3578 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3579 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3580
3581 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3582 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3583 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3584 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3585 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3586 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3587 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3588 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3589
3590 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3591 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3592 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3593 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3594 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3595 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3596
3597 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3598 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3599 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3600 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3601 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3602 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3603 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3604
3605 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3606 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3607 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3608 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3609 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3610 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3611 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3612
3613 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3614 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3615 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3616 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3617 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3618 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3619 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3620
3621 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3622 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3623 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3624 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3625 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3626 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3627 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3628
3629 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3630 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3631 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3632 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3633 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3634 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3635 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3636
3637 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3638 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3639 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3640 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3641 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3642 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3643 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3644
3645 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3646 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3647 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3648 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3649 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3650 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3651 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3652
3653 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3654 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3655 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3656 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3657
3658 { "OutBound2", NULL, "OB23 Bypass Mux" },
3659 { "OutBound3", NULL, "OB23 Bypass Mux" },
3660 { "OutBound4", NULL, "OB4 MIX" },
3661 { "OutBound5", NULL, "OB5 MIX" },
3662 { "OutBound6", NULL, "OB6 MIX" },
3663 { "OutBound7", NULL, "OB7 MIX" },
3664
3665 { "OB45", NULL, "OutBound4" },
3666 { "OB45", NULL, "OutBound5" },
3667 { "OB67", NULL, "OutBound6" },
3668 { "OB67", NULL, "OutBound7" },
3669
3670 { "IF1 DAC0", NULL, "AIF1RX" },
3671 { "IF1 DAC1", NULL, "AIF1RX" },
3672 { "IF1 DAC2", NULL, "AIF1RX" },
3673 { "IF1 DAC3", NULL, "AIF1RX" },
3674 { "IF1 DAC4", NULL, "AIF1RX" },
3675 { "IF1 DAC5", NULL, "AIF1RX" },
3676 { "IF1 DAC6", NULL, "AIF1RX" },
3677 { "IF1 DAC7", NULL, "AIF1RX" },
3678 { "IF1 DAC0", NULL, "I2S1" },
3679 { "IF1 DAC1", NULL, "I2S1" },
3680 { "IF1 DAC2", NULL, "I2S1" },
3681 { "IF1 DAC3", NULL, "I2S1" },
3682 { "IF1 DAC4", NULL, "I2S1" },
3683 { "IF1 DAC5", NULL, "I2S1" },
3684 { "IF1 DAC6", NULL, "I2S1" },
3685 { "IF1 DAC7", NULL, "I2S1" },
3686
3687 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3688 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3689 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3690 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3691 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3692 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3693 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3694 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3695
3696 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3697 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3698 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3699 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3700 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3701 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3702 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3703 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3704
3705 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3706 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3707 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3708 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3709 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3710 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3711 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3712 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3713
3714 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3715 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3716 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3717 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3718 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3719 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3720 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3721 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3722
3723 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3724 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3725 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3726 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3727 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3728 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3729 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3730 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3731
3732 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3733 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3734 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3735 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3736 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3737 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3738 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3739 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3740
3741 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3742 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3743 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3744 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3745 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3746 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3747 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3748 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3749
3750 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3751 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3752 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3753 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3754 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3755 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3756 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3757 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3758
3759 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3760 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3761 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3762 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3763 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3764 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3765 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3766 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3767
3768 { "IF2 DAC0", NULL, "AIF2RX" },
3769 { "IF2 DAC1", NULL, "AIF2RX" },
3770 { "IF2 DAC2", NULL, "AIF2RX" },
3771 { "IF2 DAC3", NULL, "AIF2RX" },
3772 { "IF2 DAC4", NULL, "AIF2RX" },
3773 { "IF2 DAC5", NULL, "AIF2RX" },
3774 { "IF2 DAC6", NULL, "AIF2RX" },
3775 { "IF2 DAC7", NULL, "AIF2RX" },
3776 { "IF2 DAC0", NULL, "I2S2" },
3777 { "IF2 DAC1", NULL, "I2S2" },
3778 { "IF2 DAC2", NULL, "I2S2" },
3779 { "IF2 DAC3", NULL, "I2S2" },
3780 { "IF2 DAC4", NULL, "I2S2" },
3781 { "IF2 DAC5", NULL, "I2S2" },
3782 { "IF2 DAC6", NULL, "I2S2" },
3783 { "IF2 DAC7", NULL, "I2S2" },
3784
3785 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3786 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3787 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3788 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3789 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3790 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3791 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3792 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3793
3794 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3795 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3796 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3797 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3798 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3799 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3800 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3801 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3802
3803 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3804 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3805 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3806 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3807 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3808 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3809 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3810 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3811
3812 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3813 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3814 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3815 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3816 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3817 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3818 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3819 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3820
3821 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3822 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3823 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3824 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3825 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3826 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3827 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3828 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3829
3830 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3831 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3832 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3833 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3834 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3835 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3836 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3837 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3838
3839 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3840 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3841 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3842 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3843 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3844 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3845 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3846 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3847
3848 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3849 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3850 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3851 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3852 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3853 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3854 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3855 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3856
3857 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3858 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3859 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3860 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3861 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3862 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3863 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3864 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3865
3866 { "IF3 DAC", NULL, "AIF3RX" },
3867 { "IF3 DAC", NULL, "I2S3" },
3868
3869 { "IF4 DAC", NULL, "AIF4RX" },
3870 { "IF4 DAC", NULL, "I2S4" },
3871
3872 { "IF3 DAC L", NULL, "IF3 DAC" },
3873 { "IF3 DAC R", NULL, "IF3 DAC" },
3874
3875 { "IF4 DAC L", NULL, "IF4 DAC" },
3876 { "IF4 DAC R", NULL, "IF4 DAC" },
3877
3878 { "SLB DAC0", NULL, "SLBRX" },
3879 { "SLB DAC1", NULL, "SLBRX" },
3880 { "SLB DAC2", NULL, "SLBRX" },
3881 { "SLB DAC3", NULL, "SLBRX" },
3882 { "SLB DAC4", NULL, "SLBRX" },
3883 { "SLB DAC5", NULL, "SLBRX" },
3884 { "SLB DAC6", NULL, "SLBRX" },
3885 { "SLB DAC7", NULL, "SLBRX" },
3886 { "SLB DAC0", NULL, "SLB" },
3887 { "SLB DAC1", NULL, "SLB" },
3888 { "SLB DAC2", NULL, "SLB" },
3889 { "SLB DAC3", NULL, "SLB" },
3890 { "SLB DAC4", NULL, "SLB" },
3891 { "SLB DAC5", NULL, "SLB" },
3892 { "SLB DAC6", NULL, "SLB" },
3893 { "SLB DAC7", NULL, "SLB" },
3894
3895 { "SLB DAC01", NULL, "SLB DAC0" },
3896 { "SLB DAC01", NULL, "SLB DAC1" },
3897 { "SLB DAC23", NULL, "SLB DAC2" },
3898 { "SLB DAC23", NULL, "SLB DAC3" },
3899 { "SLB DAC45", NULL, "SLB DAC4" },
3900 { "SLB DAC45", NULL, "SLB DAC5" },
3901 { "SLB DAC67", NULL, "SLB DAC6" },
3902 { "SLB DAC67", NULL, "SLB DAC7" },
3903
3904 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3905 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3906 { "ADDA1 Mux", "OB 67", "OB67" },
3907
3908 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3909 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3910 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3911 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3912 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3913 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3914
3915 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3916 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3917 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3918 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3919
3920 { "DAC1 FS", NULL, "DAC1 MIXL" },
3921 { "DAC1 FS", NULL, "DAC1 MIXR" },
3922
3923 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3924 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3925 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3926 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3927 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3928 { "DAC2 L Mux", "OB 2", "OutBound2" },
3929
3930 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3931 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3932 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3933 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3934 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3935 { "DAC2 R Mux", "OB 3", "OutBound3" },
3936 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3937 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3938
3939 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3940 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3941 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3942 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3943 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3944 { "DAC3 L Mux", "OB 4", "OutBound4" },
3945
3946 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3947 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3948 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3949 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3950 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3951 { "DAC3 R Mux", "OB 5", "OutBound5" },
3952
3953 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3954 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3955 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3956 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3957 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3958 { "DAC4 L Mux", "OB 6", "OutBound6" },
3959
3960 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3961 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3962 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3963 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3964 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3965 { "DAC4 R Mux", "OB 7", "OutBound7" },
3966
3967 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3968 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3969 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3970 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3971 { "Sidetone Mux", "ADC1", "ADC 1" },
3972 { "Sidetone Mux", "ADC2", "ADC 2" },
3973 { "Sidetone Mux", NULL, "Sidetone Power" },
3974
3975 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3976 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3977 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3978 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3979 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3980 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3981 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3982 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3983 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3984 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3985 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3986
3987 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3988 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3989 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3990 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3991 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3992 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3993 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3994 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3995 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3996 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3997 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3998 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3999
4000 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4001 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4002 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4003 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4004 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4005 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4006 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4007 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4008 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4009 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4010 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4011 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4012
4013 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4014 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4015 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4016 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4017 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4018 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4019 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4020 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4021 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4022 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4023 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4024 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4025
4026 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4027 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4028 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4029 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4030 { "DD1 MIX", NULL, "DD1 MIXL" },
4031 { "DD1 MIX", NULL, "DD1 MIXR" },
4032 { "DD2 MIX", NULL, "DD2 MIXL" },
4033 { "DD2 MIX", NULL, "DD2 MIXR" },
4034
4035 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4036 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4037 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4038 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4039
4040 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4041 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4042 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4043 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4044
4045 { "DAC 1", NULL, "DAC12 SRC Mux" },
4046 { "DAC 2", NULL, "DAC12 SRC Mux" },
4047 { "DAC 3", NULL, "DAC3 SRC Mux" },
4048
4049 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4050 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4051 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4052 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4053 { "PDM1 L Mux", NULL, "PDM1 Power" },
4054 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4055 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4056 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4057 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4058 { "PDM1 R Mux", NULL, "PDM1 Power" },
4059 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4060 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4061 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4062 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4063 { "PDM2 L Mux", NULL, "PDM2 Power" },
4064 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4065 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4066 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4067 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4068 { "PDM2 R Mux", NULL, "PDM2 Power" },
4069
4070 { "LOUT1 amp", NULL, "DAC 1" },
4071 { "LOUT2 amp", NULL, "DAC 2" },
4072 { "LOUT3 amp", NULL, "DAC 3" },
4073
4074 { "LOUT1 vref", NULL, "LOUT1 amp" },
4075 { "LOUT2 vref", NULL, "LOUT2 amp" },
4076 { "LOUT3 vref", NULL, "LOUT3 amp" },
4077
4078 { "LOUT1", NULL, "LOUT1 vref" },
4079 { "LOUT2", NULL, "LOUT2 vref" },
4080 { "LOUT3", NULL, "LOUT3 vref" },
4081
4082 { "PDM1L", NULL, "PDM1 L Mux" },
4083 { "PDM1R", NULL, "PDM1 R Mux" },
4084 { "PDM2L", NULL, "PDM2 L Mux" },
4085 { "PDM2R", NULL, "PDM2 R Mux" },
4086 };
4087
4088 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4089 { "DMIC L2", NULL, "DMIC1 power" },
4090 { "DMIC R2", NULL, "DMIC1 power" },
4091 };
4092
4093 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4094 { "DMIC L2", NULL, "DMIC2 power" },
4095 { "DMIC R2", NULL, "DMIC2 power" },
4096 };
4097
4098 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4099 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4100 {
4101 struct snd_soc_codec *codec = dai->codec;
4102 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4103 unsigned int val_len = 0, val_clk, mask_clk;
4104 int pre_div, bclk_ms, frame_size;
4105
4106 rt5677->lrck[dai->id] = params_rate(params);
4107 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4108 if (pre_div < 0) {
4109 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4110 rt5677->sysclk, rt5677->lrck[dai->id]);
4111 return -EINVAL;
4112 }
4113 frame_size = snd_soc_params_to_frame_size(params);
4114 if (frame_size < 0) {
4115 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4116 return -EINVAL;
4117 }
4118 bclk_ms = frame_size > 32;
4119 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4120
4121 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4122 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4123 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4124 bclk_ms, pre_div, dai->id);
4125
4126 switch (params_width(params)) {
4127 case 16:
4128 break;
4129 case 20:
4130 val_len |= RT5677_I2S_DL_20;
4131 break;
4132 case 24:
4133 val_len |= RT5677_I2S_DL_24;
4134 break;
4135 case 8:
4136 val_len |= RT5677_I2S_DL_8;
4137 break;
4138 default:
4139 return -EINVAL;
4140 }
4141
4142 switch (dai->id) {
4143 case RT5677_AIF1:
4144 mask_clk = RT5677_I2S_PD1_MASK;
4145 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4146 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4147 RT5677_I2S_DL_MASK, val_len);
4148 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4149 mask_clk, val_clk);
4150 break;
4151 case RT5677_AIF2:
4152 mask_clk = RT5677_I2S_PD2_MASK;
4153 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4154 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4155 RT5677_I2S_DL_MASK, val_len);
4156 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4157 mask_clk, val_clk);
4158 break;
4159 case RT5677_AIF3:
4160 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4161 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4162 pre_div << RT5677_I2S_PD3_SFT;
4163 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4164 RT5677_I2S_DL_MASK, val_len);
4165 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4166 mask_clk, val_clk);
4167 break;
4168 case RT5677_AIF4:
4169 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4170 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4171 pre_div << RT5677_I2S_PD4_SFT;
4172 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4173 RT5677_I2S_DL_MASK, val_len);
4174 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4175 mask_clk, val_clk);
4176 break;
4177 default:
4178 break;
4179 }
4180
4181 return 0;
4182 }
4183
4184 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4185 {
4186 struct snd_soc_codec *codec = dai->codec;
4187 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4188 unsigned int reg_val = 0;
4189
4190 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4191 case SND_SOC_DAIFMT_CBM_CFM:
4192 rt5677->master[dai->id] = 1;
4193 break;
4194 case SND_SOC_DAIFMT_CBS_CFS:
4195 reg_val |= RT5677_I2S_MS_S;
4196 rt5677->master[dai->id] = 0;
4197 break;
4198 default:
4199 return -EINVAL;
4200 }
4201
4202 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4203 case SND_SOC_DAIFMT_NB_NF:
4204 break;
4205 case SND_SOC_DAIFMT_IB_NF:
4206 reg_val |= RT5677_I2S_BP_INV;
4207 break;
4208 default:
4209 return -EINVAL;
4210 }
4211
4212 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4213 case SND_SOC_DAIFMT_I2S:
4214 break;
4215 case SND_SOC_DAIFMT_LEFT_J:
4216 reg_val |= RT5677_I2S_DF_LEFT;
4217 break;
4218 case SND_SOC_DAIFMT_DSP_A:
4219 reg_val |= RT5677_I2S_DF_PCM_A;
4220 break;
4221 case SND_SOC_DAIFMT_DSP_B:
4222 reg_val |= RT5677_I2S_DF_PCM_B;
4223 break;
4224 default:
4225 return -EINVAL;
4226 }
4227
4228 switch (dai->id) {
4229 case RT5677_AIF1:
4230 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4231 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4232 RT5677_I2S_DF_MASK, reg_val);
4233 break;
4234 case RT5677_AIF2:
4235 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4236 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4237 RT5677_I2S_DF_MASK, reg_val);
4238 break;
4239 case RT5677_AIF3:
4240 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4241 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4242 RT5677_I2S_DF_MASK, reg_val);
4243 break;
4244 case RT5677_AIF4:
4245 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4246 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4247 RT5677_I2S_DF_MASK, reg_val);
4248 break;
4249 default:
4250 break;
4251 }
4252
4253
4254 return 0;
4255 }
4256
4257 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4258 int clk_id, unsigned int freq, int dir)
4259 {
4260 struct snd_soc_codec *codec = dai->codec;
4261 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4262 unsigned int reg_val = 0;
4263
4264 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4265 return 0;
4266
4267 switch (clk_id) {
4268 case RT5677_SCLK_S_MCLK:
4269 reg_val |= RT5677_SCLK_SRC_MCLK;
4270 break;
4271 case RT5677_SCLK_S_PLL1:
4272 reg_val |= RT5677_SCLK_SRC_PLL1;
4273 break;
4274 case RT5677_SCLK_S_RCCLK:
4275 reg_val |= RT5677_SCLK_SRC_RCCLK;
4276 break;
4277 default:
4278 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4279 return -EINVAL;
4280 }
4281 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4282 RT5677_SCLK_SRC_MASK, reg_val);
4283 rt5677->sysclk = freq;
4284 rt5677->sysclk_src = clk_id;
4285
4286 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4287
4288 return 0;
4289 }
4290
4291 /**
4292 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4293 * @freq_in: external clock provided to codec.
4294 * @freq_out: target clock which codec works on.
4295 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4296 *
4297 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4298 *
4299 * Returns 0 for success or negative error code.
4300 */
4301 static int rt5677_pll_calc(const unsigned int freq_in,
4302 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4303 {
4304 if (RT5677_PLL_INP_MIN > freq_in)
4305 return -EINVAL;
4306
4307 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4308 }
4309
4310 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4311 unsigned int freq_in, unsigned int freq_out)
4312 {
4313 struct snd_soc_codec *codec = dai->codec;
4314 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4315 struct rl6231_pll_code pll_code;
4316 int ret;
4317
4318 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4319 freq_out == rt5677->pll_out)
4320 return 0;
4321
4322 if (!freq_in || !freq_out) {
4323 dev_dbg(codec->dev, "PLL disabled\n");
4324
4325 rt5677->pll_in = 0;
4326 rt5677->pll_out = 0;
4327 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4328 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4329 return 0;
4330 }
4331
4332 switch (source) {
4333 case RT5677_PLL1_S_MCLK:
4334 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4335 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4336 break;
4337 case RT5677_PLL1_S_BCLK1:
4338 case RT5677_PLL1_S_BCLK2:
4339 case RT5677_PLL1_S_BCLK3:
4340 case RT5677_PLL1_S_BCLK4:
4341 switch (dai->id) {
4342 case RT5677_AIF1:
4343 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4344 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4345 break;
4346 case RT5677_AIF2:
4347 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4348 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4349 break;
4350 case RT5677_AIF3:
4351 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4352 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4353 break;
4354 case RT5677_AIF4:
4355 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4356 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4357 break;
4358 default:
4359 break;
4360 }
4361 break;
4362 default:
4363 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4364 return -EINVAL;
4365 }
4366
4367 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4368 if (ret < 0) {
4369 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4370 return ret;
4371 }
4372
4373 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4374 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4375 pll_code.n_code, pll_code.k_code);
4376
4377 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4378 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4379 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4380 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4381 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4382
4383 rt5677->pll_in = freq_in;
4384 rt5677->pll_out = freq_out;
4385 rt5677->pll_src = source;
4386
4387 return 0;
4388 }
4389
4390 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4391 unsigned int rx_mask, int slots, int slot_width)
4392 {
4393 struct snd_soc_codec *codec = dai->codec;
4394 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4395 unsigned int val = 0, slot_width_25 = 0;
4396
4397 if (rx_mask || tx_mask)
4398 val |= (1 << 12);
4399
4400 switch (slots) {
4401 case 4:
4402 val |= (1 << 10);
4403 break;
4404 case 6:
4405 val |= (2 << 10);
4406 break;
4407 case 8:
4408 val |= (3 << 10);
4409 break;
4410 case 2:
4411 default:
4412 break;
4413 }
4414
4415 switch (slot_width) {
4416 case 20:
4417 val |= (1 << 8);
4418 break;
4419 case 25:
4420 slot_width_25 = 0x8080;
4421 case 24:
4422 val |= (2 << 8);
4423 break;
4424 case 32:
4425 val |= (3 << 8);
4426 break;
4427 case 16:
4428 default:
4429 break;
4430 }
4431
4432 switch (dai->id) {
4433 case RT5677_AIF1:
4434 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4435 val);
4436 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4437 slot_width_25);
4438 break;
4439 case RT5677_AIF2:
4440 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4441 val);
4442 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4443 slot_width_25);
4444 break;
4445 default:
4446 break;
4447 }
4448
4449 return 0;
4450 }
4451
4452 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4453 enum snd_soc_bias_level level)
4454 {
4455 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4456
4457 switch (level) {
4458 case SND_SOC_BIAS_ON:
4459 break;
4460
4461 case SND_SOC_BIAS_PREPARE:
4462 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4463 rt5677_set_dsp_vad(codec, false);
4464
4465 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4466 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4467 0x0055);
4468 regmap_update_bits(rt5677->regmap,
4469 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4470 0x0f00, 0x0f00);
4471 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4472 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4473 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4474 RT5677_PWR_BG | RT5677_PWR_VREF2,
4475 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4476 RT5677_PWR_BG | RT5677_PWR_VREF2);
4477 rt5677->is_vref_slow = false;
4478 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4479 RT5677_PWR_CORE, RT5677_PWR_CORE);
4480 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4481 0x1, 0x1);
4482 }
4483 break;
4484
4485 case SND_SOC_BIAS_STANDBY:
4486 break;
4487
4488 case SND_SOC_BIAS_OFF:
4489 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4490 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4491 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4492 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4493 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4494 regmap_update_bits(rt5677->regmap,
4495 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4496
4497 if (rt5677->dsp_vad_en)
4498 rt5677_set_dsp_vad(codec, true);
4499 break;
4500
4501 default:
4502 break;
4503 }
4504
4505 return 0;
4506 }
4507
4508 #ifdef CONFIG_GPIOLIB
4509 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4510 {
4511 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4512
4513 switch (offset) {
4514 case RT5677_GPIO1 ... RT5677_GPIO5:
4515 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4516 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4517 break;
4518
4519 case RT5677_GPIO6:
4520 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4521 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4522 break;
4523
4524 default:
4525 break;
4526 }
4527 }
4528
4529 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4530 unsigned offset, int value)
4531 {
4532 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4533
4534 switch (offset) {
4535 case RT5677_GPIO1 ... RT5677_GPIO5:
4536 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4537 0x3 << (offset * 3 + 1),
4538 (0x2 | !!value) << (offset * 3 + 1));
4539 break;
4540
4541 case RT5677_GPIO6:
4542 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4543 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4544 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4545 break;
4546
4547 default:
4548 break;
4549 }
4550
4551 return 0;
4552 }
4553
4554 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4555 {
4556 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4557 int value, ret;
4558
4559 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4560 if (ret < 0)
4561 return ret;
4562
4563 return (value & (0x1 << offset)) >> offset;
4564 }
4565
4566 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4567 {
4568 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4569
4570 switch (offset) {
4571 case RT5677_GPIO1 ... RT5677_GPIO5:
4572 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4573 0x1 << (offset * 3 + 2), 0x0);
4574 break;
4575
4576 case RT5677_GPIO6:
4577 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4578 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4579 break;
4580
4581 default:
4582 break;
4583 }
4584
4585 return 0;
4586 }
4587
4588 /** Configures the gpio as
4589 * 0 - floating
4590 * 1 - pull down
4591 * 2 - pull up
4592 */
4593 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4594 int value)
4595 {
4596 int shift;
4597
4598 switch (offset) {
4599 case RT5677_GPIO1 ... RT5677_GPIO2:
4600 shift = 2 * (1 - offset);
4601 regmap_update_bits(rt5677->regmap,
4602 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4603 0x3 << shift,
4604 (value & 0x3) << shift);
4605 break;
4606
4607 case RT5677_GPIO3 ... RT5677_GPIO6:
4608 shift = 2 * (9 - offset);
4609 regmap_update_bits(rt5677->regmap,
4610 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4611 0x3 << shift,
4612 (value & 0x3) << shift);
4613 break;
4614
4615 default:
4616 break;
4617 }
4618 }
4619
4620 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4621 {
4622 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4623 struct regmap_irq_chip_data *data = rt5677->irq_data;
4624 int irq;
4625
4626 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4627 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4628 (rt5677->pdata.jd1_gpio == 2 &&
4629 offset == RT5677_GPIO2) ||
4630 (rt5677->pdata.jd1_gpio == 3 &&
4631 offset == RT5677_GPIO3)) {
4632 irq = RT5677_IRQ_JD1;
4633 } else {
4634 return -ENXIO;
4635 }
4636 }
4637
4638 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4639 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4640 (rt5677->pdata.jd2_gpio == 2 &&
4641 offset == RT5677_GPIO5) ||
4642 (rt5677->pdata.jd2_gpio == 3 &&
4643 offset == RT5677_GPIO6)) {
4644 irq = RT5677_IRQ_JD2;
4645 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4646 offset == RT5677_GPIO4) ||
4647 (rt5677->pdata.jd3_gpio == 2 &&
4648 offset == RT5677_GPIO5) ||
4649 (rt5677->pdata.jd3_gpio == 3 &&
4650 offset == RT5677_GPIO6)) {
4651 irq = RT5677_IRQ_JD3;
4652 } else {
4653 return -ENXIO;
4654 }
4655 }
4656
4657 return regmap_irq_get_virq(data, irq);
4658 }
4659
4660 static struct gpio_chip rt5677_template_chip = {
4661 .label = "rt5677",
4662 .owner = THIS_MODULE,
4663 .direction_output = rt5677_gpio_direction_out,
4664 .set = rt5677_gpio_set,
4665 .direction_input = rt5677_gpio_direction_in,
4666 .get = rt5677_gpio_get,
4667 .to_irq = rt5677_to_irq,
4668 .can_sleep = 1,
4669 };
4670
4671 static void rt5677_init_gpio(struct i2c_client *i2c)
4672 {
4673 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4674 int ret;
4675
4676 rt5677->gpio_chip = rt5677_template_chip;
4677 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4678 rt5677->gpio_chip.parent = &i2c->dev;
4679 rt5677->gpio_chip.base = -1;
4680
4681 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4682 if (ret != 0)
4683 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4684 }
4685
4686 static void rt5677_free_gpio(struct i2c_client *i2c)
4687 {
4688 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4689
4690 gpiochip_remove(&rt5677->gpio_chip);
4691 }
4692 #else
4693 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4694 int value)
4695 {
4696 }
4697
4698 static void rt5677_init_gpio(struct i2c_client *i2c)
4699 {
4700 }
4701
4702 static void rt5677_free_gpio(struct i2c_client *i2c)
4703 {
4704 }
4705 #endif
4706
4707 static int rt5677_probe(struct snd_soc_codec *codec)
4708 {
4709 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4710 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4711 int i;
4712
4713 rt5677->codec = codec;
4714
4715 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4716 snd_soc_dapm_add_routes(dapm,
4717 rt5677_dmic2_clk_2,
4718 ARRAY_SIZE(rt5677_dmic2_clk_2));
4719 } else { /*use dmic1 clock by default*/
4720 snd_soc_dapm_add_routes(dapm,
4721 rt5677_dmic2_clk_1,
4722 ARRAY_SIZE(rt5677_dmic2_clk_1));
4723 }
4724
4725 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4726
4727 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4728 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4729
4730 for (i = 0; i < RT5677_GPIO_NUM; i++)
4731 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4732
4733 if (rt5677->irq_data) {
4734 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4735 0x8000);
4736 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4737 0x0008);
4738
4739 if (rt5677->pdata.jd1_gpio)
4740 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4741 RT5677_SEL_GPIO_JD1_MASK,
4742 rt5677->pdata.jd1_gpio <<
4743 RT5677_SEL_GPIO_JD1_SFT);
4744
4745 if (rt5677->pdata.jd2_gpio)
4746 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4747 RT5677_SEL_GPIO_JD2_MASK,
4748 rt5677->pdata.jd2_gpio <<
4749 RT5677_SEL_GPIO_JD2_SFT);
4750
4751 if (rt5677->pdata.jd3_gpio)
4752 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4753 RT5677_SEL_GPIO_JD3_MASK,
4754 rt5677->pdata.jd3_gpio <<
4755 RT5677_SEL_GPIO_JD3_SFT);
4756 }
4757
4758 mutex_init(&rt5677->dsp_cmd_lock);
4759 mutex_init(&rt5677->dsp_pri_lock);
4760
4761 return 0;
4762 }
4763
4764 static int rt5677_remove(struct snd_soc_codec *codec)
4765 {
4766 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4767
4768 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4769 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4770 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4771
4772 return 0;
4773 }
4774
4775 #ifdef CONFIG_PM
4776 static int rt5677_suspend(struct snd_soc_codec *codec)
4777 {
4778 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4779
4780 if (!rt5677->dsp_vad_en) {
4781 regcache_cache_only(rt5677->regmap, true);
4782 regcache_mark_dirty(rt5677->regmap);
4783
4784 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4785 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4786 }
4787
4788 return 0;
4789 }
4790
4791 static int rt5677_resume(struct snd_soc_codec *codec)
4792 {
4793 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4794
4795 if (!rt5677->dsp_vad_en) {
4796 rt5677->pll_src = 0;
4797 rt5677->pll_in = 0;
4798 rt5677->pll_out = 0;
4799 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4800 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4801 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4802 msleep(10);
4803
4804 regcache_cache_only(rt5677->regmap, false);
4805 regcache_sync(rt5677->regmap);
4806 }
4807
4808 return 0;
4809 }
4810 #else
4811 #define rt5677_suspend NULL
4812 #define rt5677_resume NULL
4813 #endif
4814
4815 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4816 {
4817 struct i2c_client *client = context;
4818 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4819
4820 if (rt5677->is_dsp_mode) {
4821 if (reg > 0xff) {
4822 mutex_lock(&rt5677->dsp_pri_lock);
4823 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4824 reg & 0xff);
4825 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4826 mutex_unlock(&rt5677->dsp_pri_lock);
4827 } else {
4828 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4829 }
4830 } else {
4831 regmap_read(rt5677->regmap_physical, reg, val);
4832 }
4833
4834 return 0;
4835 }
4836
4837 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4838 {
4839 struct i2c_client *client = context;
4840 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4841
4842 if (rt5677->is_dsp_mode) {
4843 if (reg > 0xff) {
4844 mutex_lock(&rt5677->dsp_pri_lock);
4845 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4846 reg & 0xff);
4847 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4848 val);
4849 mutex_unlock(&rt5677->dsp_pri_lock);
4850 } else {
4851 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4852 }
4853 } else {
4854 regmap_write(rt5677->regmap_physical, reg, val);
4855 }
4856
4857 return 0;
4858 }
4859
4860 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4861 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4862 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4863
4864 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4865 .hw_params = rt5677_hw_params,
4866 .set_fmt = rt5677_set_dai_fmt,
4867 .set_sysclk = rt5677_set_dai_sysclk,
4868 .set_pll = rt5677_set_dai_pll,
4869 .set_tdm_slot = rt5677_set_tdm_slot,
4870 };
4871
4872 static struct snd_soc_dai_driver rt5677_dai[] = {
4873 {
4874 .name = "rt5677-aif1",
4875 .id = RT5677_AIF1,
4876 .playback = {
4877 .stream_name = "AIF1 Playback",
4878 .channels_min = 1,
4879 .channels_max = 2,
4880 .rates = RT5677_STEREO_RATES,
4881 .formats = RT5677_FORMATS,
4882 },
4883 .capture = {
4884 .stream_name = "AIF1 Capture",
4885 .channels_min = 1,
4886 .channels_max = 2,
4887 .rates = RT5677_STEREO_RATES,
4888 .formats = RT5677_FORMATS,
4889 },
4890 .ops = &rt5677_aif_dai_ops,
4891 },
4892 {
4893 .name = "rt5677-aif2",
4894 .id = RT5677_AIF2,
4895 .playback = {
4896 .stream_name = "AIF2 Playback",
4897 .channels_min = 1,
4898 .channels_max = 2,
4899 .rates = RT5677_STEREO_RATES,
4900 .formats = RT5677_FORMATS,
4901 },
4902 .capture = {
4903 .stream_name = "AIF2 Capture",
4904 .channels_min = 1,
4905 .channels_max = 2,
4906 .rates = RT5677_STEREO_RATES,
4907 .formats = RT5677_FORMATS,
4908 },
4909 .ops = &rt5677_aif_dai_ops,
4910 },
4911 {
4912 .name = "rt5677-aif3",
4913 .id = RT5677_AIF3,
4914 .playback = {
4915 .stream_name = "AIF3 Playback",
4916 .channels_min = 1,
4917 .channels_max = 2,
4918 .rates = RT5677_STEREO_RATES,
4919 .formats = RT5677_FORMATS,
4920 },
4921 .capture = {
4922 .stream_name = "AIF3 Capture",
4923 .channels_min = 1,
4924 .channels_max = 2,
4925 .rates = RT5677_STEREO_RATES,
4926 .formats = RT5677_FORMATS,
4927 },
4928 .ops = &rt5677_aif_dai_ops,
4929 },
4930 {
4931 .name = "rt5677-aif4",
4932 .id = RT5677_AIF4,
4933 .playback = {
4934 .stream_name = "AIF4 Playback",
4935 .channels_min = 1,
4936 .channels_max = 2,
4937 .rates = RT5677_STEREO_RATES,
4938 .formats = RT5677_FORMATS,
4939 },
4940 .capture = {
4941 .stream_name = "AIF4 Capture",
4942 .channels_min = 1,
4943 .channels_max = 2,
4944 .rates = RT5677_STEREO_RATES,
4945 .formats = RT5677_FORMATS,
4946 },
4947 .ops = &rt5677_aif_dai_ops,
4948 },
4949 {
4950 .name = "rt5677-slimbus",
4951 .id = RT5677_AIF5,
4952 .playback = {
4953 .stream_name = "SLIMBus Playback",
4954 .channels_min = 1,
4955 .channels_max = 2,
4956 .rates = RT5677_STEREO_RATES,
4957 .formats = RT5677_FORMATS,
4958 },
4959 .capture = {
4960 .stream_name = "SLIMBus Capture",
4961 .channels_min = 1,
4962 .channels_max = 2,
4963 .rates = RT5677_STEREO_RATES,
4964 .formats = RT5677_FORMATS,
4965 },
4966 .ops = &rt5677_aif_dai_ops,
4967 },
4968 };
4969
4970 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4971 .probe = rt5677_probe,
4972 .remove = rt5677_remove,
4973 .suspend = rt5677_suspend,
4974 .resume = rt5677_resume,
4975 .set_bias_level = rt5677_set_bias_level,
4976 .idle_bias_off = true,
4977 .controls = rt5677_snd_controls,
4978 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4979 .dapm_widgets = rt5677_dapm_widgets,
4980 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4981 .dapm_routes = rt5677_dapm_routes,
4982 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4983 };
4984
4985 static const struct regmap_config rt5677_regmap_physical = {
4986 .name = "physical",
4987 .reg_bits = 8,
4988 .val_bits = 16,
4989
4990 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4991 RT5677_PR_SPACING),
4992 .readable_reg = rt5677_readable_register,
4993
4994 .cache_type = REGCACHE_NONE,
4995 .ranges = rt5677_ranges,
4996 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4997 };
4998
4999 static const struct regmap_config rt5677_regmap = {
5000 .reg_bits = 8,
5001 .val_bits = 16,
5002
5003 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5004 RT5677_PR_SPACING),
5005
5006 .volatile_reg = rt5677_volatile_register,
5007 .readable_reg = rt5677_readable_register,
5008 .reg_read = rt5677_read,
5009 .reg_write = rt5677_write,
5010
5011 .cache_type = REGCACHE_RBTREE,
5012 .reg_defaults = rt5677_reg,
5013 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5014 .ranges = rt5677_ranges,
5015 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5016 };
5017
5018 static const struct i2c_device_id rt5677_i2c_id[] = {
5019 { "rt5677", RT5677 },
5020 { "rt5676", RT5676 },
5021 { }
5022 };
5023 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5024
5025 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5026 struct device *dev)
5027 {
5028 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5029 "realtek,in1-differential");
5030 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5031 "realtek,in2-differential");
5032 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5033 "realtek,lout1-differential");
5034 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5035 "realtek,lout2-differential");
5036 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5037 "realtek,lout3-differential");
5038
5039 device_property_read_u8_array(dev, "realtek,gpio-config",
5040 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5041
5042 device_property_read_u32(dev, "realtek,jd1-gpio",
5043 &rt5677->pdata.jd1_gpio);
5044 device_property_read_u32(dev, "realtek,jd2-gpio",
5045 &rt5677->pdata.jd2_gpio);
5046 device_property_read_u32(dev, "realtek,jd3-gpio",
5047 &rt5677->pdata.jd3_gpio);
5048 }
5049
5050 static struct regmap_irq rt5677_irqs[] = {
5051 [RT5677_IRQ_JD1] = {
5052 .reg_offset = 0,
5053 .mask = RT5677_EN_IRQ_GPIO_JD1,
5054 },
5055 [RT5677_IRQ_JD2] = {
5056 .reg_offset = 0,
5057 .mask = RT5677_EN_IRQ_GPIO_JD2,
5058 },
5059 [RT5677_IRQ_JD3] = {
5060 .reg_offset = 0,
5061 .mask = RT5677_EN_IRQ_GPIO_JD3,
5062 },
5063 };
5064
5065 static struct regmap_irq_chip rt5677_irq_chip = {
5066 .name = "rt5677",
5067 .irqs = rt5677_irqs,
5068 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5069
5070 .num_regs = 1,
5071 .status_base = RT5677_IRQ_CTRL1,
5072 .mask_base = RT5677_IRQ_CTRL1,
5073 .mask_invert = 1,
5074 };
5075
5076 static int rt5677_init_irq(struct i2c_client *i2c)
5077 {
5078 int ret;
5079 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5080
5081 if (!rt5677->pdata.jd1_gpio &&
5082 !rt5677->pdata.jd2_gpio &&
5083 !rt5677->pdata.jd3_gpio)
5084 return 0;
5085
5086 if (!i2c->irq) {
5087 dev_err(&i2c->dev, "No interrupt specified\n");
5088 return -EINVAL;
5089 }
5090
5091 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5092 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5093 &rt5677_irq_chip, &rt5677->irq_data);
5094
5095 if (ret != 0) {
5096 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5097 return ret;
5098 }
5099
5100 return 0;
5101 }
5102
5103 static void rt5677_free_irq(struct i2c_client *i2c)
5104 {
5105 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5106
5107 if (rt5677->irq_data)
5108 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5109 }
5110
5111 static int rt5677_i2c_probe(struct i2c_client *i2c,
5112 const struct i2c_device_id *id)
5113 {
5114 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5115 struct rt5677_priv *rt5677;
5116 int ret;
5117 unsigned int val;
5118
5119 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5120 GFP_KERNEL);
5121 if (rt5677 == NULL)
5122 return -ENOMEM;
5123
5124 i2c_set_clientdata(i2c, rt5677);
5125
5126 rt5677->type = id->driver_data;
5127
5128 if (pdata)
5129 rt5677->pdata = *pdata;
5130 else
5131 rt5677_read_device_properties(rt5677, &i2c->dev);
5132
5133 /* pow-ldo2 and reset are optional. The codec pins may be statically
5134 * connected on the board without gpios. If the gpio device property
5135 * isn't specified, devm_gpiod_get_optional returns NULL.
5136 */
5137 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5138 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5139 if (IS_ERR(rt5677->pow_ldo2)) {
5140 ret = PTR_ERR(rt5677->pow_ldo2);
5141 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5142 return ret;
5143 }
5144 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5145 "realtek,reset", GPIOD_OUT_LOW);
5146 if (IS_ERR(rt5677->reset_pin)) {
5147 ret = PTR_ERR(rt5677->reset_pin);
5148 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5149 return ret;
5150 }
5151
5152 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5153 /* Wait a while until I2C bus becomes available. The datasheet
5154 * does not specify the exact we should wait but startup
5155 * sequence mentiones at least a few milliseconds.
5156 */
5157 msleep(10);
5158 }
5159
5160 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5161 &rt5677_regmap_physical);
5162 if (IS_ERR(rt5677->regmap_physical)) {
5163 ret = PTR_ERR(rt5677->regmap_physical);
5164 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5165 ret);
5166 return ret;
5167 }
5168
5169 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5170 if (IS_ERR(rt5677->regmap)) {
5171 ret = PTR_ERR(rt5677->regmap);
5172 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5173 ret);
5174 return ret;
5175 }
5176
5177 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5178 if (val != RT5677_DEVICE_ID) {
5179 dev_err(&i2c->dev,
5180 "Device with ID register %#x is not rt5677\n", val);
5181 return -ENODEV;
5182 }
5183
5184 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5185
5186 ret = regmap_register_patch(rt5677->regmap, init_list,
5187 ARRAY_SIZE(init_list));
5188 if (ret != 0)
5189 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5190
5191 if (rt5677->pdata.in1_diff)
5192 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5193 RT5677_IN_DF1, RT5677_IN_DF1);
5194
5195 if (rt5677->pdata.in2_diff)
5196 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5197 RT5677_IN_DF2, RT5677_IN_DF2);
5198
5199 if (rt5677->pdata.lout1_diff)
5200 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5201 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5202
5203 if (rt5677->pdata.lout2_diff)
5204 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5205 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5206
5207 if (rt5677->pdata.lout3_diff)
5208 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5209 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5210
5211 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5212 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5213 RT5677_GPIO5_FUNC_MASK,
5214 RT5677_GPIO5_FUNC_DMIC);
5215 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5216 RT5677_GPIO5_DIR_MASK,
5217 RT5677_GPIO5_DIR_OUT);
5218 }
5219
5220 if (rt5677->pdata.micbias1_vdd_3v3)
5221 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5222 RT5677_MICBIAS1_CTRL_VDD_MASK,
5223 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5224
5225 rt5677_init_gpio(i2c);
5226 rt5677_init_irq(i2c);
5227
5228 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5229 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5230 }
5231
5232 static int rt5677_i2c_remove(struct i2c_client *i2c)
5233 {
5234 snd_soc_unregister_codec(&i2c->dev);
5235 rt5677_free_irq(i2c);
5236 rt5677_free_gpio(i2c);
5237
5238 return 0;
5239 }
5240
5241 static struct i2c_driver rt5677_i2c_driver = {
5242 .driver = {
5243 .name = "rt5677",
5244 },
5245 .probe = rt5677_i2c_probe,
5246 .remove = rt5677_i2c_remove,
5247 .id_table = rt5677_i2c_id,
5248 };
5249 module_i2c_driver(rt5677_i2c_driver);
5250
5251 MODULE_DESCRIPTION("ASoC RT5677 driver");
5252 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5253 MODULE_LICENSE("GPL v2");
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