2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/log2.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_device.h>
25 #include <sound/core.h>
26 #include <sound/tlv.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
35 #define SGTL5000_DAP_REG_OFFSET 0x0100
36 #define SGTL5000_MAX_REG_OFFSET 0x013A
38 /* default value of sgtl5000 registers */
39 static const struct reg_default sgtl5000_reg_defaults
[] = {
40 { SGTL5000_CHIP_DIG_POWER
, 0x0000 },
41 { SGTL5000_CHIP_I2S_CTRL
, 0x0010 },
42 { SGTL5000_CHIP_SSS_CTRL
, 0x0010 },
43 { SGTL5000_CHIP_ADCDAC_CTRL
, 0x020c },
44 { SGTL5000_CHIP_DAC_VOL
, 0x3c3c },
45 { SGTL5000_CHIP_PAD_STRENGTH
, 0x015f },
46 { SGTL5000_CHIP_ANA_ADC_CTRL
, 0x0000 },
47 { SGTL5000_CHIP_ANA_HP_CTRL
, 0x1818 },
48 { SGTL5000_CHIP_ANA_CTRL
, 0x0111 },
49 { SGTL5000_CHIP_REF_CTRL
, 0x0000 },
50 { SGTL5000_CHIP_MIC_CTRL
, 0x0000 },
51 { SGTL5000_CHIP_LINE_OUT_CTRL
, 0x0000 },
52 { SGTL5000_CHIP_LINE_OUT_VOL
, 0x0404 },
53 { SGTL5000_CHIP_PLL_CTRL
, 0x5000 },
54 { SGTL5000_CHIP_CLK_TOP_CTRL
, 0x0000 },
55 { SGTL5000_CHIP_ANA_STATUS
, 0x0000 },
56 { SGTL5000_CHIP_SHORT_CTRL
, 0x0000 },
57 { SGTL5000_CHIP_ANA_TEST2
, 0x0000 },
58 { SGTL5000_DAP_CTRL
, 0x0000 },
59 { SGTL5000_DAP_PEQ
, 0x0000 },
60 { SGTL5000_DAP_BASS_ENHANCE
, 0x0040 },
61 { SGTL5000_DAP_BASS_ENHANCE_CTRL
, 0x051f },
62 { SGTL5000_DAP_AUDIO_EQ
, 0x0000 },
63 { SGTL5000_DAP_SURROUND
, 0x0040 },
64 { SGTL5000_DAP_EQ_BASS_BAND0
, 0x002f },
65 { SGTL5000_DAP_EQ_BASS_BAND1
, 0x002f },
66 { SGTL5000_DAP_EQ_BASS_BAND2
, 0x002f },
67 { SGTL5000_DAP_EQ_BASS_BAND3
, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND4
, 0x002f },
69 { SGTL5000_DAP_MAIN_CHAN
, 0x8000 },
70 { SGTL5000_DAP_MIX_CHAN
, 0x0000 },
71 { SGTL5000_DAP_AVC_CTRL
, 0x0510 },
72 { SGTL5000_DAP_AVC_THRESHOLD
, 0x1473 },
73 { SGTL5000_DAP_AVC_ATTACK
, 0x0028 },
74 { SGTL5000_DAP_AVC_DECAY
, 0x0050 },
77 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
78 enum sgtl5000_regulator_supplies
{
85 /* vddd is optional supply */
86 static const char *supply_names
[SGTL5000_SUPPLY_NUM
] = {
92 #define LDO_VOLTAGE 1200000
93 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
95 enum sgtl5000_micbias_resistor
{
96 SGTL5000_MICBIAS_OFF
= 0,
97 SGTL5000_MICBIAS_2K
= 2,
98 SGTL5000_MICBIAS_4K
= 4,
99 SGTL5000_MICBIAS_8K
= 8,
103 I2S_LRCLK_STRENGTH_DISABLE
,
104 I2S_LRCLK_STRENGTH_LOW
,
105 I2S_LRCLK_STRENGTH_MEDIUM
,
106 I2S_LRCLK_STRENGTH_HIGH
,
109 /* sgtl5000 private structure in codec */
110 struct sgtl5000_priv
{
111 int sysclk
; /* sysclk rate */
112 int master
; /* i2s master or not */
113 int fmt
; /* i2s data format */
114 struct regulator_bulk_data supplies
[SGTL5000_SUPPLY_NUM
];
116 struct regmap
*regmap
;
125 * mic_bias power on/off share the same register bits with
126 * output impedance of mic bias, when power on mic bias, we
127 * need reclaim it to impedance value.
133 static int mic_bias_event(struct snd_soc_dapm_widget
*w
,
134 struct snd_kcontrol
*kcontrol
, int event
)
136 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
137 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
140 case SND_SOC_DAPM_POST_PMU
:
141 /* change mic bias resistor */
142 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
143 SGTL5000_BIAS_R_MASK
,
144 sgtl5000
->micbias_resistor
<< SGTL5000_BIAS_R_SHIFT
);
147 case SND_SOC_DAPM_PRE_PMD
:
148 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
149 SGTL5000_BIAS_R_MASK
, 0);
156 * As manual described, ADC/DAC only works when VAG powerup,
157 * So enabled VAG before ADC/DAC up.
158 * In power down case, we need wait 400ms when vag fully ramped down.
160 static int power_vag_event(struct snd_soc_dapm_widget
*w
,
161 struct snd_kcontrol
*kcontrol
, int event
)
163 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
164 const u32 mask
= SGTL5000_DAC_POWERUP
| SGTL5000_ADC_POWERUP
;
167 case SND_SOC_DAPM_POST_PMU
:
168 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
169 SGTL5000_VAG_POWERUP
, SGTL5000_VAG_POWERUP
);
173 case SND_SOC_DAPM_PRE_PMD
:
175 * Don't clear VAG_POWERUP, when both DAC and ADC are
176 * operational to prevent inadvertently starving the
179 if ((snd_soc_read(codec
, SGTL5000_CHIP_ANA_POWER
) &
181 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
182 SGTL5000_VAG_POWERUP
, 0);
193 /* input sources for ADC */
194 static const char *adc_mux_text
[] = {
198 static SOC_ENUM_SINGLE_DECL(adc_enum
,
199 SGTL5000_CHIP_ANA_CTRL
, 2,
202 static const struct snd_kcontrol_new adc_mux
=
203 SOC_DAPM_ENUM("Capture Mux", adc_enum
);
205 /* input sources for DAC */
206 static const char *dac_mux_text
[] = {
210 static SOC_ENUM_SINGLE_DECL(dac_enum
,
211 SGTL5000_CHIP_ANA_CTRL
, 6,
214 static const struct snd_kcontrol_new dac_mux
=
215 SOC_DAPM_ENUM("Headphone Mux", dac_enum
);
217 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets
[] = {
218 SND_SOC_DAPM_INPUT("LINE_IN"),
219 SND_SOC_DAPM_INPUT("MIC_IN"),
221 SND_SOC_DAPM_OUTPUT("HP_OUT"),
222 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
224 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL
, 8, 0,
226 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
228 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER
, 4, 0, NULL
, 0),
229 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER
, 0, 0, NULL
, 0),
231 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM
, 0, 0, &adc_mux
),
232 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM
, 0, 0, &dac_mux
),
234 /* aif for i2s input */
235 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
236 0, SGTL5000_CHIP_DIG_POWER
,
239 /* aif for i2s output */
240 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
241 0, SGTL5000_CHIP_DIG_POWER
,
244 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER
, 1, 0),
245 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER
, 3, 0),
247 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event
),
248 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event
),
251 /* routes for sgtl5000 */
252 static const struct snd_soc_dapm_route sgtl5000_dapm_routes
[] = {
253 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
254 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
256 {"ADC", NULL
, "Capture Mux"}, /* adc_mux --> adc */
257 {"AIFOUT", NULL
, "ADC"}, /* adc --> i2s_out */
259 {"DAC", NULL
, "AIFIN"}, /* i2s-->dac,skip audio mux */
260 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
261 {"LO", NULL
, "DAC"}, /* dac --> line_out */
263 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
264 {"HP", NULL
, "Headphone Mux"}, /* hp_mux --> hp */
266 {"LINE_OUT", NULL
, "LO"},
267 {"HP_OUT", NULL
, "HP"},
270 /* custom function to fetch info of PCM playback volume */
271 static int dac_info_volsw(struct snd_kcontrol
*kcontrol
,
272 struct snd_ctl_elem_info
*uinfo
)
274 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
276 uinfo
->value
.integer
.min
= 0;
277 uinfo
->value
.integer
.max
= 0xfc - 0x3c;
282 * custom function to get of PCM playback volume
284 * dac volume register
285 * 15-------------8-7--------------0
286 * | R channel vol | L channel vol |
287 * -------------------------------
289 * PCM volume with 0.5017 dB steps from 0 to -90 dB
291 * register values map to dB
292 * 0x3B and less = Reserved
296 * 0xFC and greater = Muted
298 * register value map to userspace value
300 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
301 * ------------------------------
302 * userspace value 0xc0 0
304 static int dac_get_volsw(struct snd_kcontrol
*kcontrol
,
305 struct snd_ctl_elem_value
*ucontrol
)
307 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
312 reg
= snd_soc_read(codec
, SGTL5000_CHIP_DAC_VOL
);
314 /* get left channel volume */
315 l
= (reg
& SGTL5000_DAC_VOL_LEFT_MASK
) >> SGTL5000_DAC_VOL_LEFT_SHIFT
;
317 /* get right channel volume */
318 r
= (reg
& SGTL5000_DAC_VOL_RIGHT_MASK
) >> SGTL5000_DAC_VOL_RIGHT_SHIFT
;
320 /* make sure value fall in (0x3c,0xfc) */
321 l
= clamp(l
, 0x3c, 0xfc);
322 r
= clamp(r
, 0x3c, 0xfc);
324 /* invert it and map to userspace value */
328 ucontrol
->value
.integer
.value
[0] = l
;
329 ucontrol
->value
.integer
.value
[1] = r
;
335 * custom function to put of PCM playback volume
337 * dac volume register
338 * 15-------------8-7--------------0
339 * | R channel vol | L channel vol |
340 * -------------------------------
342 * PCM volume with 0.5017 dB steps from 0 to -90 dB
344 * register values map to dB
345 * 0x3B and less = Reserved
349 * 0xFC and greater = Muted
351 * userspace value map to register value
353 * userspace value 0xc0 0
354 * ------------------------------
355 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
357 static int dac_put_volsw(struct snd_kcontrol
*kcontrol
,
358 struct snd_ctl_elem_value
*ucontrol
)
360 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
365 l
= ucontrol
->value
.integer
.value
[0];
366 r
= ucontrol
->value
.integer
.value
[1];
368 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
369 l
= clamp(l
, 0, 0xfc - 0x3c);
370 r
= clamp(r
, 0, 0xfc - 0x3c);
372 /* invert it, get the value can be set to register */
376 /* shift to get the register value */
377 reg
= l
<< SGTL5000_DAC_VOL_LEFT_SHIFT
|
378 r
<< SGTL5000_DAC_VOL_RIGHT_SHIFT
;
380 snd_soc_write(codec
, SGTL5000_CHIP_DAC_VOL
, reg
);
385 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate
, -600, 600, 0);
387 /* tlv for mic gain, 0db 20db 30db 40db */
388 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv
,
389 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
390 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
393 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
394 static const DECLARE_TLV_DB_SCALE(headphone_volume
, -5150, 50, 0);
396 /* tlv for lineout volume, 31 steps of .5db each */
397 static const DECLARE_TLV_DB_SCALE(lineout_volume
, -1550, 50, 0);
399 static const struct snd_kcontrol_new sgtl5000_snd_controls
[] = {
400 /* SOC_DOUBLE_S8_TLV with invert */
402 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
403 .name
= "PCM Playback Volume",
404 .access
= SNDRV_CTL_ELEM_ACCESS_TLV_READ
|
405 SNDRV_CTL_ELEM_ACCESS_READWRITE
,
406 .info
= dac_info_volsw
,
407 .get
= dac_get_volsw
,
408 .put
= dac_put_volsw
,
411 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL
, 0, 4, 0xf, 0),
412 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
413 SGTL5000_CHIP_ANA_ADC_CTRL
,
414 8, 1, 0, capture_6db_attenuate
),
415 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL
, 1, 1, 0),
417 SOC_DOUBLE_TLV("Headphone Playback Volume",
418 SGTL5000_CHIP_ANA_HP_CTRL
,
422 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL
,
424 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL
,
427 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL
,
428 0, 3, 0, mic_gain_tlv
),
430 SOC_DOUBLE_TLV("Lineout Playback Volume",
431 SGTL5000_CHIP_LINE_OUT_VOL
,
432 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT
,
433 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT
,
436 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL
, 8, 1, 1),
439 /* mute the codec used by alsa core */
440 static int sgtl5000_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
442 struct snd_soc_codec
*codec
= codec_dai
->codec
;
443 u16 adcdac_ctrl
= SGTL5000_DAC_MUTE_LEFT
| SGTL5000_DAC_MUTE_RIGHT
;
445 snd_soc_update_bits(codec
, SGTL5000_CHIP_ADCDAC_CTRL
,
446 adcdac_ctrl
, mute
? adcdac_ctrl
: 0);
451 /* set codec format */
452 static int sgtl5000_set_dai_fmt(struct snd_soc_dai
*codec_dai
, unsigned int fmt
)
454 struct snd_soc_codec
*codec
= codec_dai
->codec
;
455 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
458 sgtl5000
->master
= 0;
460 * i2s clock and frame master setting.
462 * - clock and frame slave,
463 * - clock and frame master
465 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
466 case SND_SOC_DAIFMT_CBS_CFS
:
468 case SND_SOC_DAIFMT_CBM_CFM
:
469 i2sctl
|= SGTL5000_I2S_MASTER
;
470 sgtl5000
->master
= 1;
476 /* setting i2s data format */
477 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
478 case SND_SOC_DAIFMT_DSP_A
:
479 i2sctl
|= SGTL5000_I2S_MODE_PCM
<< SGTL5000_I2S_MODE_SHIFT
;
481 case SND_SOC_DAIFMT_DSP_B
:
482 i2sctl
|= SGTL5000_I2S_MODE_PCM
<< SGTL5000_I2S_MODE_SHIFT
;
483 i2sctl
|= SGTL5000_I2S_LRALIGN
;
485 case SND_SOC_DAIFMT_I2S
:
486 i2sctl
|= SGTL5000_I2S_MODE_I2S_LJ
<< SGTL5000_I2S_MODE_SHIFT
;
488 case SND_SOC_DAIFMT_RIGHT_J
:
489 i2sctl
|= SGTL5000_I2S_MODE_RJ
<< SGTL5000_I2S_MODE_SHIFT
;
490 i2sctl
|= SGTL5000_I2S_LRPOL
;
492 case SND_SOC_DAIFMT_LEFT_J
:
493 i2sctl
|= SGTL5000_I2S_MODE_I2S_LJ
<< SGTL5000_I2S_MODE_SHIFT
;
494 i2sctl
|= SGTL5000_I2S_LRALIGN
;
500 sgtl5000
->fmt
= fmt
& SND_SOC_DAIFMT_FORMAT_MASK
;
502 /* Clock inversion */
503 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
504 case SND_SOC_DAIFMT_NB_NF
:
506 case SND_SOC_DAIFMT_IB_NF
:
507 i2sctl
|= SGTL5000_I2S_SCLK_INV
;
513 snd_soc_write(codec
, SGTL5000_CHIP_I2S_CTRL
, i2sctl
);
518 /* set codec sysclk */
519 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
520 int clk_id
, unsigned int freq
, int dir
)
522 struct snd_soc_codec
*codec
= codec_dai
->codec
;
523 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
526 case SGTL5000_SYSCLK
:
527 sgtl5000
->sysclk
= freq
;
537 * set clock according to i2s frame clock,
538 * sgtl5000 provides 2 clock sources:
539 * 1. sys_mclk: sample freq can only be configured to
540 * 1/256, 1/384, 1/512 of sys_mclk.
541 * 2. pll: can derive any audio clocks.
543 * clock setting rules:
544 * 1. in slave mode, only sys_mclk can be used
545 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
547 * 3. usage of sys_mclk is preferred over pll to save power.
549 static int sgtl5000_set_clock(struct snd_soc_codec
*codec
, int frame_rate
)
551 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
553 int sys_fs
; /* sample freq */
556 * sample freq should be divided by frame clock,
557 * if frame clock is lower than 44.1 kHz, sample freq should be set to
558 * 32 kHz or 44.1 kHz.
560 switch (frame_rate
) {
574 /* set divided factor of frame clock */
575 switch (sys_fs
/ frame_rate
) {
577 clk_ctl
|= SGTL5000_RATE_MODE_DIV_4
<< SGTL5000_RATE_MODE_SHIFT
;
580 clk_ctl
|= SGTL5000_RATE_MODE_DIV_2
<< SGTL5000_RATE_MODE_SHIFT
;
583 clk_ctl
|= SGTL5000_RATE_MODE_DIV_1
<< SGTL5000_RATE_MODE_SHIFT
;
589 /* set the sys_fs according to frame rate */
592 clk_ctl
|= SGTL5000_SYS_FS_32k
<< SGTL5000_SYS_FS_SHIFT
;
595 clk_ctl
|= SGTL5000_SYS_FS_44_1k
<< SGTL5000_SYS_FS_SHIFT
;
598 clk_ctl
|= SGTL5000_SYS_FS_48k
<< SGTL5000_SYS_FS_SHIFT
;
601 clk_ctl
|= SGTL5000_SYS_FS_96k
<< SGTL5000_SYS_FS_SHIFT
;
604 dev_err(codec
->dev
, "frame rate %d not supported\n",
610 * calculate the divider of mclk/sample_freq,
611 * factor of freq = 96 kHz can only be 256, since mclk is in the range
614 switch (sgtl5000
->sysclk
/ frame_rate
) {
616 clk_ctl
|= SGTL5000_MCLK_FREQ_256FS
<<
617 SGTL5000_MCLK_FREQ_SHIFT
;
620 clk_ctl
|= SGTL5000_MCLK_FREQ_384FS
<<
621 SGTL5000_MCLK_FREQ_SHIFT
;
624 clk_ctl
|= SGTL5000_MCLK_FREQ_512FS
<<
625 SGTL5000_MCLK_FREQ_SHIFT
;
628 /* if mclk does not satisfy the divider, use pll */
629 if (sgtl5000
->master
) {
630 clk_ctl
|= SGTL5000_MCLK_FREQ_PLL
<<
631 SGTL5000_MCLK_FREQ_SHIFT
;
634 "PLL not supported in slave mode\n");
635 dev_err(codec
->dev
, "%d ratio is not supported. "
636 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
637 sgtl5000
->sysclk
/ frame_rate
);
642 /* if using pll, please check manual 6.4.2 for detail */
643 if ((clk_ctl
& SGTL5000_MCLK_FREQ_MASK
) == SGTL5000_MCLK_FREQ_PLL
) {
647 unsigned int in
, int_div
, frac_div
;
649 if (sgtl5000
->sysclk
> 17000000) {
651 in
= sgtl5000
->sysclk
/ 2;
654 in
= sgtl5000
->sysclk
;
665 pll_ctl
= int_div
<< SGTL5000_PLL_INT_DIV_SHIFT
|
666 frac_div
<< SGTL5000_PLL_FRAC_DIV_SHIFT
;
668 snd_soc_write(codec
, SGTL5000_CHIP_PLL_CTRL
, pll_ctl
);
670 snd_soc_update_bits(codec
,
671 SGTL5000_CHIP_CLK_TOP_CTRL
,
672 SGTL5000_INPUT_FREQ_DIV2
,
673 SGTL5000_INPUT_FREQ_DIV2
);
675 snd_soc_update_bits(codec
,
676 SGTL5000_CHIP_CLK_TOP_CTRL
,
677 SGTL5000_INPUT_FREQ_DIV2
,
681 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
682 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
,
683 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
);
685 /* if using pll, clk_ctrl must be set after pll power up */
686 snd_soc_write(codec
, SGTL5000_CHIP_CLK_CTRL
, clk_ctl
);
688 /* otherwise, clk_ctrl must be set before pll power down */
689 snd_soc_write(codec
, SGTL5000_CHIP_CLK_CTRL
, clk_ctl
);
692 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
693 SGTL5000_PLL_POWERUP
| SGTL5000_VCOAMP_POWERUP
,
701 * Set PCM DAI bit size and sample rate.
702 * input: params_rate, params_fmt
704 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream
*substream
,
705 struct snd_pcm_hw_params
*params
,
706 struct snd_soc_dai
*dai
)
708 struct snd_soc_codec
*codec
= dai
->codec
;
709 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
710 int channels
= params_channels(params
);
715 /* sysclk should already set */
716 if (!sgtl5000
->sysclk
) {
717 dev_err(codec
->dev
, "%s: set sysclk first!\n", __func__
);
721 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
722 stereo
= SGTL5000_DAC_STEREO
;
724 stereo
= SGTL5000_ADC_STEREO
;
726 /* set mono to save power */
727 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
, stereo
,
728 channels
== 1 ? 0 : stereo
);
730 /* set codec clock base on lrclk */
731 ret
= sgtl5000_set_clock(codec
, params_rate(params
));
735 /* set i2s data format */
736 switch (params_width(params
)) {
738 if (sgtl5000
->fmt
== SND_SOC_DAIFMT_RIGHT_J
)
740 i2s_ctl
|= SGTL5000_I2S_DLEN_16
<< SGTL5000_I2S_DLEN_SHIFT
;
741 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_32FS
<<
742 SGTL5000_I2S_SCLKFREQ_SHIFT
;
745 i2s_ctl
|= SGTL5000_I2S_DLEN_20
<< SGTL5000_I2S_DLEN_SHIFT
;
746 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
747 SGTL5000_I2S_SCLKFREQ_SHIFT
;
750 i2s_ctl
|= SGTL5000_I2S_DLEN_24
<< SGTL5000_I2S_DLEN_SHIFT
;
751 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
752 SGTL5000_I2S_SCLKFREQ_SHIFT
;
755 if (sgtl5000
->fmt
== SND_SOC_DAIFMT_RIGHT_J
)
757 i2s_ctl
|= SGTL5000_I2S_DLEN_32
<< SGTL5000_I2S_DLEN_SHIFT
;
758 i2s_ctl
|= SGTL5000_I2S_SCLKFREQ_64FS
<<
759 SGTL5000_I2S_SCLKFREQ_SHIFT
;
765 snd_soc_update_bits(codec
, SGTL5000_CHIP_I2S_CTRL
,
766 SGTL5000_I2S_DLEN_MASK
| SGTL5000_I2S_SCLKFREQ_MASK
,
774 * common state changes:
776 * off --> standby --> prepare --> on
777 * standby --> prepare --> on
780 * on --> prepare --> standby
782 static int sgtl5000_set_bias_level(struct snd_soc_codec
*codec
,
783 enum snd_soc_bias_level level
)
786 case SND_SOC_BIAS_ON
:
787 case SND_SOC_BIAS_PREPARE
:
788 case SND_SOC_BIAS_STANDBY
:
789 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
790 SGTL5000_REFTOP_POWERUP
,
791 SGTL5000_REFTOP_POWERUP
);
793 case SND_SOC_BIAS_OFF
:
794 snd_soc_update_bits(codec
, SGTL5000_CHIP_ANA_POWER
,
795 SGTL5000_REFTOP_POWERUP
, 0);
802 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
803 SNDRV_PCM_FMTBIT_S20_3LE |\
804 SNDRV_PCM_FMTBIT_S24_LE |\
805 SNDRV_PCM_FMTBIT_S32_LE)
807 static const struct snd_soc_dai_ops sgtl5000_ops
= {
808 .hw_params
= sgtl5000_pcm_hw_params
,
809 .digital_mute
= sgtl5000_digital_mute
,
810 .set_fmt
= sgtl5000_set_dai_fmt
,
811 .set_sysclk
= sgtl5000_set_dai_sysclk
,
814 static struct snd_soc_dai_driver sgtl5000_dai
= {
817 .stream_name
= "Playback",
821 * only support 8~48K + 96K,
822 * TODO modify hw_param to support more
824 .rates
= SNDRV_PCM_RATE_8000_48000
| SNDRV_PCM_RATE_96000
,
825 .formats
= SGTL5000_FORMATS
,
828 .stream_name
= "Capture",
831 .rates
= SNDRV_PCM_RATE_8000_48000
| SNDRV_PCM_RATE_96000
,
832 .formats
= SGTL5000_FORMATS
,
834 .ops
= &sgtl5000_ops
,
835 .symmetric_rates
= 1,
838 static bool sgtl5000_volatile(struct device
*dev
, unsigned int reg
)
841 case SGTL5000_CHIP_ID
:
842 case SGTL5000_CHIP_ADCDAC_CTRL
:
843 case SGTL5000_CHIP_ANA_STATUS
:
850 static bool sgtl5000_readable(struct device
*dev
, unsigned int reg
)
853 case SGTL5000_CHIP_ID
:
854 case SGTL5000_CHIP_DIG_POWER
:
855 case SGTL5000_CHIP_CLK_CTRL
:
856 case SGTL5000_CHIP_I2S_CTRL
:
857 case SGTL5000_CHIP_SSS_CTRL
:
858 case SGTL5000_CHIP_ADCDAC_CTRL
:
859 case SGTL5000_CHIP_DAC_VOL
:
860 case SGTL5000_CHIP_PAD_STRENGTH
:
861 case SGTL5000_CHIP_ANA_ADC_CTRL
:
862 case SGTL5000_CHIP_ANA_HP_CTRL
:
863 case SGTL5000_CHIP_ANA_CTRL
:
864 case SGTL5000_CHIP_LINREG_CTRL
:
865 case SGTL5000_CHIP_REF_CTRL
:
866 case SGTL5000_CHIP_MIC_CTRL
:
867 case SGTL5000_CHIP_LINE_OUT_CTRL
:
868 case SGTL5000_CHIP_LINE_OUT_VOL
:
869 case SGTL5000_CHIP_ANA_POWER
:
870 case SGTL5000_CHIP_PLL_CTRL
:
871 case SGTL5000_CHIP_CLK_TOP_CTRL
:
872 case SGTL5000_CHIP_ANA_STATUS
:
873 case SGTL5000_CHIP_SHORT_CTRL
:
874 case SGTL5000_CHIP_ANA_TEST2
:
875 case SGTL5000_DAP_CTRL
:
876 case SGTL5000_DAP_PEQ
:
877 case SGTL5000_DAP_BASS_ENHANCE
:
878 case SGTL5000_DAP_BASS_ENHANCE_CTRL
:
879 case SGTL5000_DAP_AUDIO_EQ
:
880 case SGTL5000_DAP_SURROUND
:
881 case SGTL5000_DAP_FLT_COEF_ACCESS
:
882 case SGTL5000_DAP_COEF_WR_B0_MSB
:
883 case SGTL5000_DAP_COEF_WR_B0_LSB
:
884 case SGTL5000_DAP_EQ_BASS_BAND0
:
885 case SGTL5000_DAP_EQ_BASS_BAND1
:
886 case SGTL5000_DAP_EQ_BASS_BAND2
:
887 case SGTL5000_DAP_EQ_BASS_BAND3
:
888 case SGTL5000_DAP_EQ_BASS_BAND4
:
889 case SGTL5000_DAP_MAIN_CHAN
:
890 case SGTL5000_DAP_MIX_CHAN
:
891 case SGTL5000_DAP_AVC_CTRL
:
892 case SGTL5000_DAP_AVC_THRESHOLD
:
893 case SGTL5000_DAP_AVC_ATTACK
:
894 case SGTL5000_DAP_AVC_DECAY
:
895 case SGTL5000_DAP_COEF_WR_B1_MSB
:
896 case SGTL5000_DAP_COEF_WR_B1_LSB
:
897 case SGTL5000_DAP_COEF_WR_B2_MSB
:
898 case SGTL5000_DAP_COEF_WR_B2_LSB
:
899 case SGTL5000_DAP_COEF_WR_A1_MSB
:
900 case SGTL5000_DAP_COEF_WR_A1_LSB
:
901 case SGTL5000_DAP_COEF_WR_A2_MSB
:
902 case SGTL5000_DAP_COEF_WR_A2_LSB
:
911 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
912 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
913 * The calculatation was done for all possible register values which
914 * is the array index and the following formula: 10^((idx−15)/40) * 100
916 static const u8 vol_quot_table
[] = {
917 42, 45, 47, 50, 53, 56, 60, 63,
918 67, 71, 75, 79, 84, 89, 94, 100,
919 106, 112, 119, 126, 133, 141, 150, 158,
920 168, 178, 188, 200, 211, 224, 237, 251
924 * sgtl5000 has 3 internal power supplies:
925 * 1. VAG, normally set to vdda/2
926 * 2. charge pump, set to different value
927 * according to voltage of vdda and vddio
928 * 3. line out VAG, normally set to vddio/2
930 * and should be set according to:
931 * 1. vddd provided by external or not
932 * 2. vdda and vddio voltage value. > 3.1v or not
934 static int sgtl5000_set_power_regs(struct snd_soc_codec
*codec
)
946 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
948 vdda
= regulator_get_voltage(sgtl5000
->supplies
[VDDA
].consumer
);
949 vddio
= regulator_get_voltage(sgtl5000
->supplies
[VDDIO
].consumer
);
950 vddd
= (sgtl5000
->num_supplies
> VDDD
)
951 ? regulator_get_voltage(sgtl5000
->supplies
[VDDD
].consumer
)
955 vddio
= vddio
/ 1000;
958 if (vdda
<= 0 || vddio
<= 0 || vddd
< 0) {
959 dev_err(codec
->dev
, "regulator voltage not set correctly\n");
964 /* according to datasheet, maximum voltage of supplies */
965 if (vdda
> 3600 || vddio
> 3600 || vddd
> 1980) {
967 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
974 ana_pwr
= snd_soc_read(codec
, SGTL5000_CHIP_ANA_POWER
);
975 ana_pwr
|= SGTL5000_DAC_STEREO
|
976 SGTL5000_ADC_STEREO
|
977 SGTL5000_REFTOP_POWERUP
;
978 lreg_ctrl
= snd_soc_read(codec
, SGTL5000_CHIP_LINREG_CTRL
);
980 if (vddio
< 3100 && vdda
< 3100) {
981 /* enable internal oscillator used for charge pump */
982 snd_soc_update_bits(codec
, SGTL5000_CHIP_CLK_TOP_CTRL
,
984 SGTL5000_INT_OSC_EN
);
985 /* Enable VDDC charge pump */
986 ana_pwr
|= SGTL5000_VDDC_CHRGPMP_POWERUP
;
987 } else if (vddio
>= 3100 && vdda
>= 3100) {
988 ana_pwr
&= ~SGTL5000_VDDC_CHRGPMP_POWERUP
;
989 /* VDDC use VDDIO rail */
990 lreg_ctrl
|= SGTL5000_VDDC_ASSN_OVRD
;
991 lreg_ctrl
|= SGTL5000_VDDC_MAN_ASSN_VDDIO
<<
992 SGTL5000_VDDC_MAN_ASSN_SHIFT
;
995 snd_soc_write(codec
, SGTL5000_CHIP_LINREG_CTRL
, lreg_ctrl
);
997 snd_soc_write(codec
, SGTL5000_CHIP_ANA_POWER
, ana_pwr
);
1000 * set ADC/DAC VAG to vdda / 2,
1001 * should stay in range (0.8v, 1.575v)
1004 if (vag
<= SGTL5000_ANA_GND_BASE
)
1006 else if (vag
>= SGTL5000_ANA_GND_BASE
+ SGTL5000_ANA_GND_STP
*
1007 (SGTL5000_ANA_GND_MASK
>> SGTL5000_ANA_GND_SHIFT
))
1008 vag
= SGTL5000_ANA_GND_MASK
>> SGTL5000_ANA_GND_SHIFT
;
1010 vag
= (vag
- SGTL5000_ANA_GND_BASE
) / SGTL5000_ANA_GND_STP
;
1012 snd_soc_update_bits(codec
, SGTL5000_CHIP_REF_CTRL
,
1013 SGTL5000_ANA_GND_MASK
, vag
<< SGTL5000_ANA_GND_SHIFT
);
1015 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1017 if (lo_vag
<= SGTL5000_LINE_OUT_GND_BASE
)
1019 else if (lo_vag
>= SGTL5000_LINE_OUT_GND_BASE
+
1020 SGTL5000_LINE_OUT_GND_STP
* SGTL5000_LINE_OUT_GND_MAX
)
1021 lo_vag
= SGTL5000_LINE_OUT_GND_MAX
;
1023 lo_vag
= (lo_vag
- SGTL5000_LINE_OUT_GND_BASE
) /
1024 SGTL5000_LINE_OUT_GND_STP
;
1026 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINE_OUT_CTRL
,
1027 SGTL5000_LINE_OUT_CURRENT_MASK
|
1028 SGTL5000_LINE_OUT_GND_MASK
,
1029 lo_vag
<< SGTL5000_LINE_OUT_GND_SHIFT
|
1030 SGTL5000_LINE_OUT_CURRENT_360u
<<
1031 SGTL5000_LINE_OUT_CURRENT_SHIFT
);
1034 * Set lineout output level in range (0..31)
1035 * the same value is used for right and left channel
1037 * Searching for a suitable index solving this formula:
1038 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1040 vol_quot
= (vag
* 100) / lo_vag
;
1042 for (i
= 0; i
< ARRAY_SIZE(vol_quot_table
); i
++) {
1043 if (vol_quot
>= vol_quot_table
[i
])
1049 snd_soc_update_bits(codec
, SGTL5000_CHIP_LINE_OUT_VOL
,
1050 SGTL5000_LINE_OUT_VOL_RIGHT_MASK
|
1051 SGTL5000_LINE_OUT_VOL_LEFT_MASK
,
1052 lo_vol
<< SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT
|
1053 lo_vol
<< SGTL5000_LINE_OUT_VOL_LEFT_SHIFT
);
1058 static int sgtl5000_enable_regulators(struct i2c_client
*client
)
1062 int external_vddd
= 0;
1063 struct regulator
*vddd
;
1064 struct sgtl5000_priv
*sgtl5000
= i2c_get_clientdata(client
);
1066 for (i
= 0; i
< ARRAY_SIZE(sgtl5000
->supplies
); i
++)
1067 sgtl5000
->supplies
[i
].supply
= supply_names
[i
];
1069 vddd
= regulator_get_optional(&client
->dev
, "VDDD");
1071 /* See if it's just not registered yet */
1072 if (PTR_ERR(vddd
) == -EPROBE_DEFER
)
1073 return -EPROBE_DEFER
;
1076 regulator_put(vddd
);
1079 sgtl5000
->num_supplies
= ARRAY_SIZE(sgtl5000
->supplies
)
1080 - 1 + external_vddd
;
1081 ret
= regulator_bulk_get(&client
->dev
, sgtl5000
->num_supplies
,
1082 sgtl5000
->supplies
);
1086 ret
= regulator_bulk_enable(sgtl5000
->num_supplies
,
1087 sgtl5000
->supplies
);
1089 usleep_range(10, 20);
1091 regulator_bulk_free(sgtl5000
->num_supplies
,
1092 sgtl5000
->supplies
);
1097 static int sgtl5000_probe(struct snd_soc_codec
*codec
)
1101 struct sgtl5000_priv
*sgtl5000
= snd_soc_codec_get_drvdata(codec
);
1103 /* power up sgtl5000 */
1104 ret
= sgtl5000_set_power_regs(codec
);
1108 /* enable small pop, introduce 400ms delay in turning off */
1109 snd_soc_update_bits(codec
, SGTL5000_CHIP_REF_CTRL
,
1110 SGTL5000_SMALL_POP
, 1);
1112 /* disable short cut detector */
1113 snd_soc_write(codec
, SGTL5000_CHIP_SHORT_CTRL
, 0);
1116 * set i2s as default input of sound switch
1117 * TODO: add sound switch to control and dapm widge.
1119 snd_soc_write(codec
, SGTL5000_CHIP_SSS_CTRL
,
1120 SGTL5000_DAC_SEL_I2S_IN
<< SGTL5000_DAC_SEL_SHIFT
);
1121 snd_soc_write(codec
, SGTL5000_CHIP_DIG_POWER
,
1122 SGTL5000_ADC_EN
| SGTL5000_DAC_EN
);
1124 /* enable dac volume ramp by default */
1125 snd_soc_write(codec
, SGTL5000_CHIP_ADCDAC_CTRL
,
1126 SGTL5000_DAC_VOL_RAMP_EN
|
1127 SGTL5000_DAC_MUTE_RIGHT
|
1128 SGTL5000_DAC_MUTE_LEFT
);
1130 reg
= ((sgtl5000
->lrclk_strength
) << SGTL5000_PAD_I2S_LRCLK_SHIFT
| 0x5f);
1131 snd_soc_write(codec
, SGTL5000_CHIP_PAD_STRENGTH
, reg
);
1133 snd_soc_write(codec
, SGTL5000_CHIP_ANA_CTRL
,
1134 SGTL5000_HP_ZCD_EN
|
1135 SGTL5000_ADC_ZCD_EN
);
1137 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
1138 SGTL5000_BIAS_R_MASK
,
1139 sgtl5000
->micbias_resistor
<< SGTL5000_BIAS_R_SHIFT
);
1141 snd_soc_update_bits(codec
, SGTL5000_CHIP_MIC_CTRL
,
1142 SGTL5000_BIAS_VOLT_MASK
,
1143 sgtl5000
->micbias_voltage
<< SGTL5000_BIAS_VOLT_SHIFT
);
1147 * Enable DAP in kcontrol and dapm.
1149 snd_soc_write(codec
, SGTL5000_DAP_CTRL
, 0);
1157 static int sgtl5000_remove(struct snd_soc_codec
*codec
)
1162 static struct snd_soc_codec_driver sgtl5000_driver
= {
1163 .probe
= sgtl5000_probe
,
1164 .remove
= sgtl5000_remove
,
1165 .set_bias_level
= sgtl5000_set_bias_level
,
1166 .suspend_bias_off
= true,
1167 .component_driver
= {
1168 .controls
= sgtl5000_snd_controls
,
1169 .num_controls
= ARRAY_SIZE(sgtl5000_snd_controls
),
1170 .dapm_widgets
= sgtl5000_dapm_widgets
,
1171 .num_dapm_widgets
= ARRAY_SIZE(sgtl5000_dapm_widgets
),
1172 .dapm_routes
= sgtl5000_dapm_routes
,
1173 .num_dapm_routes
= ARRAY_SIZE(sgtl5000_dapm_routes
),
1177 static const struct regmap_config sgtl5000_regmap
= {
1182 .max_register
= SGTL5000_MAX_REG_OFFSET
,
1183 .volatile_reg
= sgtl5000_volatile
,
1184 .readable_reg
= sgtl5000_readable
,
1186 .cache_type
= REGCACHE_RBTREE
,
1187 .reg_defaults
= sgtl5000_reg_defaults
,
1188 .num_reg_defaults
= ARRAY_SIZE(sgtl5000_reg_defaults
),
1192 * Write all the default values from sgtl5000_reg_defaults[] array into the
1193 * sgtl5000 registers, to make sure we always start with the sane registers
1194 * values as stated in the datasheet.
1196 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1197 * we follow this approach to guarantee we always start from the default values
1198 * and avoid problems like, not being able to probe after an audio playback
1199 * followed by a system reset or a 'reboot' command in Linux
1201 static void sgtl5000_fill_defaults(struct i2c_client
*client
)
1203 struct sgtl5000_priv
*sgtl5000
= i2c_get_clientdata(client
);
1204 int i
, ret
, val
, index
;
1206 for (i
= 0; i
< ARRAY_SIZE(sgtl5000_reg_defaults
); i
++) {
1207 val
= sgtl5000_reg_defaults
[i
].def
;
1208 index
= sgtl5000_reg_defaults
[i
].reg
;
1209 ret
= regmap_write(sgtl5000
->regmap
, index
, val
);
1211 dev_err(&client
->dev
,
1212 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1213 __func__
, ret
, index
, val
);
1217 static int sgtl5000_i2c_probe(struct i2c_client
*client
,
1218 const struct i2c_device_id
*id
)
1220 struct sgtl5000_priv
*sgtl5000
;
1222 struct device_node
*np
= client
->dev
.of_node
;
1226 sgtl5000
= devm_kzalloc(&client
->dev
, sizeof(*sgtl5000
), GFP_KERNEL
);
1230 i2c_set_clientdata(client
, sgtl5000
);
1232 ret
= sgtl5000_enable_regulators(client
);
1236 sgtl5000
->regmap
= devm_regmap_init_i2c(client
, &sgtl5000_regmap
);
1237 if (IS_ERR(sgtl5000
->regmap
)) {
1238 ret
= PTR_ERR(sgtl5000
->regmap
);
1239 dev_err(&client
->dev
, "Failed to allocate regmap: %d\n", ret
);
1243 sgtl5000
->mclk
= devm_clk_get(&client
->dev
, NULL
);
1244 if (IS_ERR(sgtl5000
->mclk
)) {
1245 ret
= PTR_ERR(sgtl5000
->mclk
);
1246 dev_err(&client
->dev
, "Failed to get mclock: %d\n", ret
);
1247 /* Defer the probe to see if the clk will be provided later */
1249 ret
= -EPROBE_DEFER
;
1253 ret
= clk_prepare_enable(sgtl5000
->mclk
);
1255 dev_err(&client
->dev
, "Error enabling clock %d\n", ret
);
1259 /* Need 8 clocks before I2C accesses */
1262 /* read chip information */
1263 ret
= regmap_read(sgtl5000
->regmap
, SGTL5000_CHIP_ID
, ®
);
1265 dev_err(&client
->dev
, "Error reading chip id %d\n", ret
);
1269 if (((reg
& SGTL5000_PARTID_MASK
) >> SGTL5000_PARTID_SHIFT
) !=
1270 SGTL5000_PARTID_PART_ID
) {
1271 dev_err(&client
->dev
,
1272 "Device with ID register %x is not a sgtl5000\n", reg
);
1277 rev
= (reg
& SGTL5000_REVID_MASK
) >> SGTL5000_REVID_SHIFT
;
1278 dev_info(&client
->dev
, "sgtl5000 revision 0x%x\n", rev
);
1279 sgtl5000
->revision
= rev
;
1281 /* reconfigure the clocks in case we're using the PLL */
1282 ret
= regmap_write(sgtl5000
->regmap
,
1283 SGTL5000_CHIP_CLK_CTRL
,
1284 SGTL5000_CHIP_CLK_CTRL_DEFAULT
);
1286 dev_err(&client
->dev
,
1287 "Error %d initializing CHIP_CLK_CTRL\n", ret
);
1289 /* Follow section 2.2.1.1 of AN3663 */
1290 ana_pwr
= SGTL5000_ANA_POWER_DEFAULT
;
1291 if (sgtl5000
->num_supplies
<= VDDD
) {
1292 /* internal VDDD at 1.2V */
1293 ret
= regmap_update_bits(sgtl5000
->regmap
,
1294 SGTL5000_CHIP_LINREG_CTRL
,
1295 SGTL5000_LINREG_VDDD_MASK
,
1298 dev_err(&client
->dev
,
1299 "Error %d setting LINREG_VDDD\n", ret
);
1301 ana_pwr
|= SGTL5000_LINEREG_D_POWERUP
;
1302 dev_info(&client
->dev
,
1303 "Using internal LDO instead of VDDD: check ER1\n");
1305 /* using external LDO for VDDD
1306 * Clear startup powerup and simple powerup
1307 * bits to save power
1309 ana_pwr
&= ~(SGTL5000_STARTUP_POWERUP
1310 | SGTL5000_LINREG_SIMPLE_POWERUP
);
1311 dev_dbg(&client
->dev
, "Using external VDDD\n");
1313 ret
= regmap_write(sgtl5000
->regmap
, SGTL5000_CHIP_ANA_POWER
, ana_pwr
);
1315 dev_err(&client
->dev
,
1316 "Error %d setting CHIP_ANA_POWER to %04x\n",
1320 if (!of_property_read_u32(np
,
1321 "micbias-resistor-k-ohms", &value
)) {
1323 case SGTL5000_MICBIAS_OFF
:
1324 sgtl5000
->micbias_resistor
= 0;
1326 case SGTL5000_MICBIAS_2K
:
1327 sgtl5000
->micbias_resistor
= 1;
1329 case SGTL5000_MICBIAS_4K
:
1330 sgtl5000
->micbias_resistor
= 2;
1332 case SGTL5000_MICBIAS_8K
:
1333 sgtl5000
->micbias_resistor
= 3;
1336 sgtl5000
->micbias_resistor
= 2;
1337 dev_err(&client
->dev
,
1338 "Unsuitable MicBias resistor\n");
1341 /* default is 4Kohms */
1342 sgtl5000
->micbias_resistor
= 2;
1344 if (!of_property_read_u32(np
,
1345 "micbias-voltage-m-volts", &value
)) {
1347 /* steps of 250mV */
1348 if ((value
>= 1250) && (value
<= 3000))
1349 sgtl5000
->micbias_voltage
= (value
/ 250) - 5;
1351 sgtl5000
->micbias_voltage
= 0;
1352 dev_err(&client
->dev
,
1353 "Unsuitable MicBias voltage\n");
1356 sgtl5000
->micbias_voltage
= 0;
1360 sgtl5000
->lrclk_strength
= I2S_LRCLK_STRENGTH_LOW
;
1361 if (!of_property_read_u32(np
, "lrclk-strength", &value
)) {
1362 if (value
> I2S_LRCLK_STRENGTH_HIGH
)
1363 value
= I2S_LRCLK_STRENGTH_LOW
;
1364 sgtl5000
->lrclk_strength
= value
;
1367 /* Ensure sgtl5000 will start with sane register values */
1368 sgtl5000_fill_defaults(client
);
1370 ret
= snd_soc_register_codec(&client
->dev
,
1371 &sgtl5000_driver
, &sgtl5000_dai
, 1);
1378 clk_disable_unprepare(sgtl5000
->mclk
);
1381 regulator_bulk_disable(sgtl5000
->num_supplies
, sgtl5000
->supplies
);
1382 regulator_bulk_free(sgtl5000
->num_supplies
, sgtl5000
->supplies
);
1387 static int sgtl5000_i2c_remove(struct i2c_client
*client
)
1389 struct sgtl5000_priv
*sgtl5000
= i2c_get_clientdata(client
);
1391 snd_soc_unregister_codec(&client
->dev
);
1392 clk_disable_unprepare(sgtl5000
->mclk
);
1393 regulator_bulk_disable(sgtl5000
->num_supplies
, sgtl5000
->supplies
);
1394 regulator_bulk_free(sgtl5000
->num_supplies
, sgtl5000
->supplies
);
1399 static const struct i2c_device_id sgtl5000_id
[] = {
1404 MODULE_DEVICE_TABLE(i2c
, sgtl5000_id
);
1406 static const struct of_device_id sgtl5000_dt_ids
[] = {
1407 { .compatible
= "fsl,sgtl5000", },
1410 MODULE_DEVICE_TABLE(of
, sgtl5000_dt_ids
);
1412 static struct i2c_driver sgtl5000_i2c_driver
= {
1415 .of_match_table
= sgtl5000_dt_ids
,
1417 .probe
= sgtl5000_i2c_probe
,
1418 .remove
= sgtl5000_i2c_remove
,
1419 .id_table
= sgtl5000_id
,
1422 module_i2c_driver(sgtl5000_i2c_driver
);
1424 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1425 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1426 MODULE_LICENSE("GPL");