sound/soc/codecs/tlv320adcx140.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 // TLV320ADCX104 Sound driver
   3 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   4
   5 #ifndef _TLV320ADCX140_H
   6 #define _TLV320ADCX140_H
   7
   8 #define ADCX140_RATES   (SNDRV_PCM_RATE_44100 | \
   9                          SNDRV_PCM_RATE_48000)
  10
  11 #define ADCX140_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  12                          SNDRV_PCM_FMTBIT_S20_3LE | \
  13                          SNDRV_PCM_FMTBIT_S24_3LE | \
  14                          SNDRV_PCM_FMTBIT_S24_LE | \
  15                          SNDRV_PCM_FMTBIT_S32_LE)
  16
  17 #define ADCX140_PAGE_SELECT     0x00
  18 #define ADCX140_SW_RESET        0x01
  19 #define ADCX140_SLEEP_CFG       0x02
  20 #define ADCX140_SHDN_CFG        0x05
  21 #define ADCX140_ASI_CFG0        0x07
  22 #define ADCX140_ASI_CFG1        0x08
  23 #define ADCX140_ASI_CFG2        0x09
  24 #define ADCX140_ASI_CH1         0x0b
  25 #define ADCX140_ASI_CH2         0x0c
  26 #define ADCX140_ASI_CH3         0x0d
  27 #define ADCX140_ASI_CH4         0x0e
  28 #define ADCX140_ASI_CH5         0x0f
  29 #define ADCX140_ASI_CH6         0x10
  30 #define ADCX140_ASI_CH7         0x11
  31 #define ADCX140_ASI_CH8         0x12
  32 #define ADCX140_MST_CFG0        0x13
  33 #define ADCX140_MST_CFG1        0x14
  34 #define ADCX140_ASI_STS         0x15
  35 #define ADCX140_CLK_SRC         0x16
  36 #define ADCX140_PDMCLK_CFG      0x1f
  37 #define ADCX140_PDM_CFG         0x20
  38 #define ADCX140_GPIO_CFG0       0x21
  39 #define ADCX140_GPO_CFG1        0x22
  40 #define ADCX140_GPO_CFG2        0x23
  41 #define ADCX140_GPO_CFG3        0x24
  42 #define ADCX140_GPO_CFG4        0x25
  43 #define ADCX140_GPO_VAL         0x29
  44 #define ADCX140_GPIO_MON        0x2a
  45 #define ADCX140_GPI_CFG0        0x2b
  46 #define ADCX140_GPI_CFG1        0x2c
  47 #define ADCX140_GPI_MON         0x2f
  48 #define ADCX140_INT_CFG         0x32
  49 #define ADCX140_INT_MASK0       0x33
  50 #define ADCX140_INT_LTCH0       0x36
  51 #define ADCX140_BIAS_CFG        0x3b
  52 #define ADCX140_CH1_CFG0        0x3c
  53 #define ADCX140_CH1_CFG1        0x3d
  54 #define ADCX140_CH1_CFG2        0x3e
  55 #define ADCX140_CH1_CFG3        0x3f
  56 #define ADCX140_CH1_CFG4        0x40
  57 #define ADCX140_CH2_CFG0        0x41
  58 #define ADCX140_CH2_CFG1        0x42
  59 #define ADCX140_CH2_CFG2        0x43
  60 #define ADCX140_CH2_CFG3        0x44
  61 #define ADCX140_CH2_CFG4        0x45
  62 #define ADCX140_CH3_CFG0        0x46
  63 #define ADCX140_CH3_CFG1        0x47
  64 #define ADCX140_CH3_CFG2        0x48
  65 #define ADCX140_CH3_CFG3        0x49
  66 #define ADCX140_CH3_CFG4        0x4a
  67 #define ADCX140_CH4_CFG0        0x4b
  68 #define ADCX140_CH4_CFG1        0x4c
  69 #define ADCX140_CH4_CFG2        0x4d
  70 #define ADCX140_CH4_CFG3        0x4e
  71 #define ADCX140_CH4_CFG4        0x4f
  72 #define ADCX140_CH5_CFG2        0x52
  73 #define ADCX140_CH5_CFG3        0x53
  74 #define ADCX140_CH5_CFG4        0x54
  75 #define ADCX140_CH6_CFG2        0x57
  76 #define ADCX140_CH6_CFG3        0x58
  77 #define ADCX140_CH6_CFG4        0x59
  78 #define ADCX140_CH7_CFG2        0x5c
  79 #define ADCX140_CH7_CFG3        0x5d
  80 #define ADCX140_CH7_CFG4        0x5e
  81 #define ADCX140_CH8_CFG2        0x61
  82 #define ADCX140_CH8_CFG3        0x62
  83 #define ADCX140_CH8_CFG4        0x63
  84 #define ADCX140_DSP_CFG0        0x6b
  85 #define ADCX140_DSP_CFG1        0x6c
  86 #define ADCX140_DRE_CFG0        0x6d
  87 #define ADCX140_AGC_CFG0        0x70
  88 #define ADCX140_IN_CH_EN        0x73
  89 #define ADCX140_ASI_OUT_CH_EN   0x74
  90 #define ADCX140_PWR_CFG         0x75
  91 #define ADCX140_DEV_STS0        0x76
  92 #define ADCX140_DEV_STS1        0x77
  93
  94 #define ADCX140_RESET   BIT(0)
  95
  96 #define ADCX140_WAKE_DEV        BIT(0)
  97 #define ADCX140_AREG_INTERNAL   BIT(7)
  98
  99 #define ADCX140_BCLKINV_BIT     BIT(2)
 100 #define ADCX140_FSYNCINV_BIT    BIT(3)
 101 #define ADCX140_INV_MSK         (ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT)
 102 #define ADCX140_BCLK_FSYNC_MASTER       BIT(7)
 103 #define ADCX140_I2S_MODE_BIT    BIT(6)
 104 #define ADCX140_LEFT_JUST_BIT   BIT(7)
 105 #define ADCX140_ASI_FORMAT_MSK  (ADCX140_I2S_MODE_BIT | ADCX140_LEFT_JUST_BIT)
 106
 107 #define ADCX140_16_BIT_WORD     0x0
 108 #define ADCX140_20_BIT_WORD     BIT(4)
 109 #define ADCX140_24_BIT_WORD     BIT(5)
 110 #define ADCX140_32_BIT_WORD     (BIT(4) | BIT(5))
 111 #define ADCX140_WORD_LEN_MSK    0x30
 112
 113 #define ADCX140_MAX_CHANNELS    8
 114
 115 #define ADCX140_MIC_BIAS_VAL_VREF       0
 116 #define ADCX140_MIC_BIAS_VAL_VREF_1096  1
 117 #define ADCX140_MIC_BIAS_VAL_AVDD       6
 118 #define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4)
 119
 120 #define ADCX140_MIC_BIAS_VREF_275V      0
 121 #define ADCX140_MIC_BIAS_VREF_25V       1
 122 #define ADCX140_MIC_BIAS_VREF_1375V     2
 123 #define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0)
 124
 125 #define ADCX140_PWR_CFG_BIAS_PDZ        BIT(7)
 126 #define ADCX140_PWR_CFG_ADC_PDZ         BIT(6)
 127 #define ADCX140_PWR_CFG_PLL_PDZ         BIT(5)
 128
 129 #define ADCX140_TX_OFFSET_MASK          GENMASK(4, 0)
 130
 131 #endif /* _TLV320ADCX140_ */