1 // SPDX-License-Identifier: GPL-2.0
3 * ALSA SoC TLV320AIC31xx CODEC Driver
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6 * Jyri Sarha <jsarha@ti.com>
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
12 * and mono/stereo Class-D speaker driver.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/acpi.h>
25 #include <linux/of_gpio.h>
26 #include <linux/slab.h>
27 #include <sound/core.h>
28 #include <sound/jack.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
34 #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
36 #include "tlv320aic31xx.h"
38 static const struct reg_default aic31xx_reg_defaults
[] = {
39 { AIC31XX_CLKMUX
, 0x00 },
40 { AIC31XX_PLLPR
, 0x11 },
41 { AIC31XX_PLLJ
, 0x04 },
42 { AIC31XX_PLLDMSB
, 0x00 },
43 { AIC31XX_PLLDLSB
, 0x00 },
44 { AIC31XX_NDAC
, 0x01 },
45 { AIC31XX_MDAC
, 0x01 },
46 { AIC31XX_DOSRMSB
, 0x00 },
47 { AIC31XX_DOSRLSB
, 0x80 },
48 { AIC31XX_NADC
, 0x01 },
49 { AIC31XX_MADC
, 0x01 },
50 { AIC31XX_AOSR
, 0x80 },
51 { AIC31XX_IFACE1
, 0x00 },
52 { AIC31XX_DATA_OFFSET
, 0x00 },
53 { AIC31XX_IFACE2
, 0x00 },
54 { AIC31XX_BCLKN
, 0x01 },
55 { AIC31XX_DACSETUP
, 0x14 },
56 { AIC31XX_DACMUTE
, 0x0c },
57 { AIC31XX_LDACVOL
, 0x00 },
58 { AIC31XX_RDACVOL
, 0x00 },
59 { AIC31XX_ADCSETUP
, 0x00 },
60 { AIC31XX_ADCFGA
, 0x80 },
61 { AIC31XX_ADCVOL
, 0x00 },
62 { AIC31XX_HPDRIVER
, 0x04 },
63 { AIC31XX_SPKAMP
, 0x06 },
64 { AIC31XX_DACMIXERROUTE
, 0x00 },
65 { AIC31XX_LANALOGHPL
, 0x7f },
66 { AIC31XX_RANALOGHPR
, 0x7f },
67 { AIC31XX_LANALOGSPL
, 0x7f },
68 { AIC31XX_RANALOGSPR
, 0x7f },
69 { AIC31XX_HPLGAIN
, 0x02 },
70 { AIC31XX_HPRGAIN
, 0x02 },
71 { AIC31XX_SPLGAIN
, 0x00 },
72 { AIC31XX_SPRGAIN
, 0x00 },
73 { AIC31XX_MICBIAS
, 0x00 },
74 { AIC31XX_MICPGA
, 0x80 },
75 { AIC31XX_MICPGAPI
, 0x00 },
76 { AIC31XX_MICPGAMI
, 0x00 },
79 static bool aic31xx_volatile(struct device
*dev
, unsigned int reg
)
82 case AIC31XX_PAGECTL
: /* regmap implementation requires this */
83 case AIC31XX_RESET
: /* always clears after write */
86 case AIC31XX_DACFLAG1
:
87 case AIC31XX_DACFLAG2
:
88 case AIC31XX_OFFLAG
: /* Sticky interrupt flags */
89 case AIC31XX_INTRDACFLAG
: /* Sticky interrupt flags */
90 case AIC31XX_INTRADCFLAG
: /* Sticky interrupt flags */
91 case AIC31XX_INTRDACFLAG2
:
92 case AIC31XX_INTRADCFLAG2
:
93 case AIC31XX_HSDETECT
:
99 static bool aic31xx_writeable(struct device
*dev
, unsigned int reg
)
102 case AIC31XX_OT_FLAG
:
103 case AIC31XX_ADCFLAG
:
104 case AIC31XX_DACFLAG1
:
105 case AIC31XX_DACFLAG2
:
106 case AIC31XX_OFFLAG
: /* Sticky interrupt flags */
107 case AIC31XX_INTRDACFLAG
: /* Sticky interrupt flags */
108 case AIC31XX_INTRADCFLAG
: /* Sticky interrupt flags */
109 case AIC31XX_INTRDACFLAG2
:
110 case AIC31XX_INTRADCFLAG2
:
116 static const struct regmap_range_cfg aic31xx_ranges
[] = {
119 .range_max
= 12 * 128,
120 .selector_reg
= AIC31XX_PAGECTL
,
121 .selector_mask
= 0xff,
128 static const struct regmap_config aic31xx_i2c_regmap
= {
131 .writeable_reg
= aic31xx_writeable
,
132 .volatile_reg
= aic31xx_volatile
,
133 .reg_defaults
= aic31xx_reg_defaults
,
134 .num_reg_defaults
= ARRAY_SIZE(aic31xx_reg_defaults
),
135 .cache_type
= REGCACHE_RBTREE
,
136 .ranges
= aic31xx_ranges
,
137 .num_ranges
= ARRAY_SIZE(aic31xx_ranges
),
138 .max_register
= 12 * 128,
141 static const char * const aic31xx_supply_names
[] = {
150 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
152 struct aic31xx_disable_nb
{
153 struct notifier_block nb
;
154 struct aic31xx_priv
*aic31xx
;
157 struct aic31xx_priv
{
158 struct snd_soc_component
*component
;
161 struct regmap
*regmap
;
162 enum aic31xx_type codec_type
;
163 struct gpio_desc
*gpio_reset
;
165 struct aic31xx_pdata pdata
;
166 struct regulator_bulk_data supplies
[AIC31XX_NUM_SUPPLIES
];
167 struct aic31xx_disable_nb disable_nb
[AIC31XX_NUM_SUPPLIES
];
168 struct snd_soc_jack
*jack
;
172 bool master_dapm_route_applied
;
176 struct aic31xx_rate_divs
{
189 /* ADC dividers can be disabled by configuring them to 0 */
190 static const struct aic31xx_rate_divs aic31xx_divs
[] = {
191 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
193 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
194 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
195 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
197 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
198 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
199 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
201 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
202 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
203 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
205 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
206 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
207 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
209 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
210 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
211 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
213 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
214 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
215 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
217 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
218 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
219 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
221 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
222 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
223 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
225 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
226 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
227 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
229 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
230 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
231 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
233 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
234 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
235 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
238 static const char * const ldac_in_text
[] = {
239 "Off", "Left Data", "Right Data", "Mono"
242 static const char * const rdac_in_text
[] = {
243 "Off", "Right Data", "Left Data", "Mono"
246 static SOC_ENUM_SINGLE_DECL(ldac_in_enum
, AIC31XX_DACSETUP
, 4, ldac_in_text
);
248 static SOC_ENUM_SINGLE_DECL(rdac_in_enum
, AIC31XX_DACSETUP
, 2, rdac_in_text
);
250 static const char * const mic_select_text
[] = {
251 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
254 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum
, AIC31XX_MICPGAPI
, 6,
256 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum
, AIC31XX_MICPGAPI
, 4,
258 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum
, AIC31XX_MICPGAPI
, 2,
261 static SOC_ENUM_SINGLE_DECL(cm_m_enum
, AIC31XX_MICPGAMI
, 6, mic_select_text
);
262 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum
, AIC31XX_MICPGAMI
, 4,
265 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv
, -6350, 50, 0);
266 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv
, 0, 10, 0);
267 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv
, -2000, 50, 0);
268 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv
, 0, 50, 0);
269 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv
, 0, 100, 0);
270 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv
, 600, 600, 0);
271 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv
, -6350, 50, 0);
272 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv
, -6350, 50, 0);
275 * controls to be exported to the user space
277 static const struct snd_kcontrol_new common31xx_snd_controls
[] = {
278 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL
,
279 AIC31XX_RDACVOL
, 0, -127, 48, 7, 0, dac_vol_tlv
),
281 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN
,
282 AIC31XX_HPRGAIN
, 2, 1, 0),
283 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN
,
284 AIC31XX_HPRGAIN
, 3, 0x09, 0, hp_drv_tlv
),
286 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL
,
287 AIC31XX_RANALOGHPR
, 0, 0x7F, 1, hp_vol_tlv
),
290 static const struct snd_kcontrol_new aic31xx_snd_controls
[] = {
291 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA
, 4, 4, 1,
294 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA
, 7, 1, 1),
295 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL
, AIC31XX_ADCVOL
,
296 0, -24, 40, 6, 0, adc_cgain_tlv
),
298 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA
, 0,
299 119, 0, mic_pga_tlv
),
302 static const struct snd_kcontrol_new aic311x_snd_controls
[] = {
303 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN
,
304 AIC31XX_SPRGAIN
, 2, 1, 0),
305 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN
,
306 AIC31XX_SPRGAIN
, 3, 3, 0, class_D_drv_tlv
),
308 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL
,
309 AIC31XX_RANALOGSPR
, 0, 0x7F, 1, sp_vol_tlv
),
312 static const struct snd_kcontrol_new aic310x_snd_controls
[] = {
313 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN
,
315 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN
,
316 3, 3, 0, class_D_drv_tlv
),
318 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL
,
319 0, 0x7F, 1, sp_vol_tlv
),
322 static const struct snd_kcontrol_new ldac_in_control
=
323 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum
);
325 static const struct snd_kcontrol_new rdac_in_control
=
326 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum
);
328 static int aic31xx_wait_bits(struct aic31xx_priv
*aic31xx
, unsigned int reg
,
329 unsigned int mask
, unsigned int wbits
, int sleep
,
334 int ret
= regmap_read(aic31xx
->regmap
, reg
, &bits
);
336 while ((bits
& mask
) != wbits
&& counter
&& !ret
) {
337 usleep_range(sleep
, sleep
* 2);
338 ret
= regmap_read(aic31xx
->regmap
, reg
, &bits
);
341 if ((bits
& mask
) != wbits
) {
342 dev_err(aic31xx
->dev
,
343 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
344 __func__
, reg
, bits
, wbits
, ret
, mask
,
345 (count
- counter
) * sleep
);
351 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
353 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget
*w
,
354 struct snd_kcontrol
*kcontrol
, int event
)
356 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
357 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
358 unsigned int reg
= AIC31XX_DACFLAG1
;
361 switch (WIDGET_BIT(w
->reg
, w
->shift
)) {
362 case WIDGET_BIT(AIC31XX_DACSETUP
, 7):
363 mask
= AIC31XX_LDACPWRSTATUS_MASK
;
365 case WIDGET_BIT(AIC31XX_DACSETUP
, 6):
366 mask
= AIC31XX_RDACPWRSTATUS_MASK
;
368 case WIDGET_BIT(AIC31XX_HPDRIVER
, 7):
369 mask
= AIC31XX_HPLDRVPWRSTATUS_MASK
;
371 case WIDGET_BIT(AIC31XX_HPDRIVER
, 6):
372 mask
= AIC31XX_HPRDRVPWRSTATUS_MASK
;
374 case WIDGET_BIT(AIC31XX_SPKAMP
, 7):
375 mask
= AIC31XX_SPLDRVPWRSTATUS_MASK
;
377 case WIDGET_BIT(AIC31XX_SPKAMP
, 6):
378 mask
= AIC31XX_SPRDRVPWRSTATUS_MASK
;
380 case WIDGET_BIT(AIC31XX_ADCSETUP
, 7):
381 mask
= AIC31XX_ADCPWRSTATUS_MASK
;
382 reg
= AIC31XX_ADCFLAG
;
385 dev_err(component
->dev
, "Unknown widget '%s' calling %s\n",
391 case SND_SOC_DAPM_POST_PMU
:
392 return aic31xx_wait_bits(aic31xx
, reg
, mask
, mask
, 5000, 100);
393 case SND_SOC_DAPM_POST_PMD
:
394 return aic31xx_wait_bits(aic31xx
, reg
, mask
, 0, 5000, 100);
396 dev_dbg(component
->dev
,
397 "Unhandled dapm widget event %d from %s\n",
403 static const struct snd_kcontrol_new aic31xx_left_output_switches
[] = {
404 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE
, 6, 1, 0),
405 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE
, 5, 1, 0),
406 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE
, 4, 1, 0),
409 static const struct snd_kcontrol_new aic31xx_right_output_switches
[] = {
410 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE
, 2, 1, 0),
411 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE
, 1, 1, 0),
414 static const struct snd_kcontrol_new dac31xx_left_output_switches
[] = {
415 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE
, 6, 1, 0),
416 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE
, 5, 1, 0),
417 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE
, 4, 1, 0),
420 static const struct snd_kcontrol_new dac31xx_right_output_switches
[] = {
421 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE
, 2, 1, 0),
422 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE
, 1, 1, 0),
425 static const struct snd_kcontrol_new p_term_mic1lp
=
426 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum
);
428 static const struct snd_kcontrol_new p_term_mic1rp
=
429 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum
);
431 static const struct snd_kcontrol_new p_term_mic1lm
=
432 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum
);
434 static const struct snd_kcontrol_new m_term_mic1lm
=
435 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum
);
437 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch
=
438 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL
, 7, 1, 0);
440 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch
=
441 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR
, 7, 1, 0);
443 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch
=
444 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL
, 7, 1, 0);
446 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch
=
447 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR
, 7, 1, 0);
449 static int mic_bias_event(struct snd_soc_dapm_widget
*w
,
450 struct snd_kcontrol
*kcontrol
, int event
)
452 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
453 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
456 case SND_SOC_DAPM_POST_PMU
:
457 /* change mic bias voltage to user defined */
458 snd_soc_component_update_bits(component
, AIC31XX_MICBIAS
,
459 AIC31XX_MICBIAS_MASK
,
460 aic31xx
->micbias_vg
<<
461 AIC31XX_MICBIAS_SHIFT
);
462 dev_dbg(component
->dev
, "%s: turned on\n", __func__
);
464 case SND_SOC_DAPM_PRE_PMD
:
465 /* turn mic bias off */
466 snd_soc_component_update_bits(component
, AIC31XX_MICBIAS
,
467 AIC31XX_MICBIAS_MASK
, 0);
468 dev_dbg(component
->dev
, "%s: turned off\n", __func__
);
474 static const struct snd_soc_dapm_widget common31xx_dapm_widgets
[] = {
475 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM
, 0, 0),
477 SND_SOC_DAPM_MUX("DAC Left Input",
478 SND_SOC_NOPM
, 0, 0, &ldac_in_control
),
479 SND_SOC_DAPM_MUX("DAC Right Input",
480 SND_SOC_NOPM
, 0, 0, &rdac_in_control
),
482 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
483 AIC31XX_DACSETUP
, 7, 0, aic31xx_dapm_power_event
,
484 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
486 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
487 AIC31XX_DACSETUP
, 6, 0, aic31xx_dapm_power_event
,
488 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
491 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM
, 0, 0,
492 &aic31xx_dapm_hpl_switch
),
493 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM
, 0, 0,
494 &aic31xx_dapm_hpr_switch
),
497 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER
, 7, 0,
498 NULL
, 0, aic31xx_dapm_power_event
,
499 SND_SOC_DAPM_POST_PMD
| SND_SOC_DAPM_POST_PMU
),
500 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER
, 6, 0,
501 NULL
, 0, aic31xx_dapm_power_event
,
502 SND_SOC_DAPM_POST_PMD
| SND_SOC_DAPM_POST_PMU
),
505 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM
, 0, 0, mic_bias_event
,
506 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
508 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
509 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2
, 2, 0,
513 SND_SOC_DAPM_OUTPUT("HPL"),
514 SND_SOC_DAPM_OUTPUT("HPR"),
517 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets
[] = {
519 SND_SOC_DAPM_INPUT("AIN1"),
520 SND_SOC_DAPM_INPUT("AIN2"),
523 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM
, 0, 0,
524 dac31xx_left_output_switches
,
525 ARRAY_SIZE(dac31xx_left_output_switches
)),
526 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM
, 0, 0,
527 dac31xx_right_output_switches
,
528 ARRAY_SIZE(dac31xx_right_output_switches
)),
531 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets
[] = {
533 SND_SOC_DAPM_INPUT("MIC1LP"),
534 SND_SOC_DAPM_INPUT("MIC1RP"),
535 SND_SOC_DAPM_INPUT("MIC1LM"),
537 /* Input Selection to MIC_PGA */
538 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM
, 0, 0,
540 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM
, 0, 0,
542 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM
, 0, 0,
546 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP
, 7, 0,
547 aic31xx_dapm_power_event
, SND_SOC_DAPM_POST_PMU
|
548 SND_SOC_DAPM_POST_PMD
),
550 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM
, 0, 0,
553 /* Enabling & Disabling MIC Gain Ctl */
554 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA
,
558 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM
, 0, 0,
559 aic31xx_left_output_switches
,
560 ARRAY_SIZE(aic31xx_left_output_switches
)),
561 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM
, 0, 0,
562 aic31xx_right_output_switches
,
563 ARRAY_SIZE(aic31xx_right_output_switches
)),
565 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM
, 0, 0),
568 static const struct snd_soc_dapm_widget aic311x_dapm_widgets
[] = {
569 /* AIC3111 and AIC3110 have stereo class-D amplifier */
570 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP
, 7, 0, NULL
, 0,
571 aic31xx_dapm_power_event
, SND_SOC_DAPM_POST_PMU
|
572 SND_SOC_DAPM_POST_PMD
),
573 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP
, 6, 0, NULL
, 0,
574 aic31xx_dapm_power_event
, SND_SOC_DAPM_POST_PMU
|
575 SND_SOC_DAPM_POST_PMD
),
576 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM
, 0, 0,
577 &aic31xx_dapm_spl_switch
),
578 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM
, 0, 0,
579 &aic31xx_dapm_spr_switch
),
580 SND_SOC_DAPM_OUTPUT("SPL"),
581 SND_SOC_DAPM_OUTPUT("SPR"),
584 /* AIC3100 and AIC3120 have only mono class-D amplifier */
585 static const struct snd_soc_dapm_widget aic310x_dapm_widgets
[] = {
586 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP
, 7, 0, NULL
, 0,
587 aic31xx_dapm_power_event
, SND_SOC_DAPM_POST_PMU
|
588 SND_SOC_DAPM_POST_PMD
),
589 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM
, 0, 0,
590 &aic31xx_dapm_spl_switch
),
591 SND_SOC_DAPM_OUTPUT("SPK"),
594 static const struct snd_soc_dapm_route
595 common31xx_audio_map
[] = {
596 /* DAC Input Routing */
597 {"DAC Left Input", "Left Data", "AIF IN"},
598 {"DAC Left Input", "Right Data", "AIF IN"},
599 {"DAC Left Input", "Mono", "AIF IN"},
600 {"DAC Right Input", "Left Data", "AIF IN"},
601 {"DAC Right Input", "Right Data", "AIF IN"},
602 {"DAC Right Input", "Mono", "AIF IN"},
603 {"DAC Left", NULL
, "DAC Left Input"},
604 {"DAC Right", NULL
, "DAC Right Input"},
607 {"HP Left", "Switch", "Output Left"},
608 {"HPL Driver", NULL
, "HP Left"},
609 {"HPL", NULL
, "HPL Driver"},
612 {"HP Right", "Switch", "Output Right"},
613 {"HPR Driver", NULL
, "HP Right"},
614 {"HPR", NULL
, "HPR Driver"},
617 static const struct snd_soc_dapm_route
618 dac31xx_audio_map
[] = {
620 {"Output Left", "From Left DAC", "DAC Left"},
621 {"Output Left", "From AIN1", "AIN1"},
622 {"Output Left", "From AIN2", "AIN2"},
625 {"Output Right", "From Right DAC", "DAC Right"},
626 {"Output Right", "From AIN2", "AIN2"},
629 static const struct snd_soc_dapm_route
630 aic31xx_audio_map
[] = {
632 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
633 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
634 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
635 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
636 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
637 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
638 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
639 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
640 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
642 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
643 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
644 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
646 {"MIC_GAIN_CTL", NULL
, "MIC1LP P-Terminal"},
647 {"MIC_GAIN_CTL", NULL
, "MIC1RP P-Terminal"},
648 {"MIC_GAIN_CTL", NULL
, "MIC1LM P-Terminal"},
649 {"MIC_GAIN_CTL", NULL
, "MIC1LM M-Terminal"},
651 {"ADC", NULL
, "MIC_GAIN_CTL"},
653 {"AIF OUT", NULL
, "ADC"},
656 {"Output Left", "From Left DAC", "DAC Left"},
657 {"Output Left", "From MIC1LP", "MIC1LP"},
658 {"Output Left", "From MIC1RP", "MIC1RP"},
661 {"Output Right", "From Right DAC", "DAC Right"},
662 {"Output Right", "From MIC1RP", "MIC1RP"},
665 static const struct snd_soc_dapm_route
666 aic311x_audio_map
[] = {
668 {"Speaker Left", "Switch", "Output Left"},
669 {"SPL ClassD", NULL
, "Speaker Left"},
670 {"SPL", NULL
, "SPL ClassD"},
673 {"Speaker Right", "Switch", "Output Right"},
674 {"SPR ClassD", NULL
, "Speaker Right"},
675 {"SPR", NULL
, "SPR ClassD"},
678 static const struct snd_soc_dapm_route
679 aic310x_audio_map
[] = {
681 {"Speaker", "Switch", "Output Left"},
682 {"SPK ClassD", NULL
, "Speaker"},
683 {"SPK", NULL
, "SPK ClassD"},
687 * Always connected DAPM routes for codec clock master modes.
688 * If the codec is the master on the I2S bus, we need to power up components
689 * to have valid DAC_CLK.
691 * In order to have the I2S clocks on the bus either the DACs/ADC need to be
692 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
694 * Otherwise the codec will not generate clocks on the bus.
696 static const struct snd_soc_dapm_route
697 common31xx_cm_audio_map
[] = {
698 {"HPL", NULL
, "AIF IN"},
699 {"HPR", NULL
, "AIF IN"},
701 {"AIF IN", NULL
, "Activate I2S clocks"},
704 static const struct snd_soc_dapm_route
705 aic31xx_cm_audio_map
[] = {
706 {"AIF OUT", NULL
, "MIC1LP"},
707 {"AIF OUT", NULL
, "MIC1RP"},
708 {"AIF OUT", NULL
, "MIC1LM"},
710 {"AIF OUT", NULL
, "Activate I2S clocks"},
713 static int aic31xx_add_controls(struct snd_soc_component
*component
)
716 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
718 if (!(aic31xx
->codec_type
& DAC31XX_BIT
))
719 ret
= snd_soc_add_component_controls(
720 component
, aic31xx_snd_controls
,
721 ARRAY_SIZE(aic31xx_snd_controls
));
725 if (aic31xx
->codec_type
& AIC31XX_STEREO_CLASS_D_BIT
)
726 ret
= snd_soc_add_component_controls(
727 component
, aic311x_snd_controls
,
728 ARRAY_SIZE(aic311x_snd_controls
));
730 ret
= snd_soc_add_component_controls(
731 component
, aic310x_snd_controls
,
732 ARRAY_SIZE(aic310x_snd_controls
));
737 static int aic31xx_add_widgets(struct snd_soc_component
*component
)
739 struct snd_soc_dapm_context
*dapm
= snd_soc_component_get_dapm(component
);
740 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
743 if (aic31xx
->codec_type
& DAC31XX_BIT
) {
744 ret
= snd_soc_dapm_new_controls(
745 dapm
, dac31xx_dapm_widgets
,
746 ARRAY_SIZE(dac31xx_dapm_widgets
));
750 ret
= snd_soc_dapm_add_routes(dapm
, dac31xx_audio_map
,
751 ARRAY_SIZE(dac31xx_audio_map
));
755 ret
= snd_soc_dapm_new_controls(
756 dapm
, aic31xx_dapm_widgets
,
757 ARRAY_SIZE(aic31xx_dapm_widgets
));
761 ret
= snd_soc_dapm_add_routes(dapm
, aic31xx_audio_map
,
762 ARRAY_SIZE(aic31xx_audio_map
));
767 if (aic31xx
->codec_type
& AIC31XX_STEREO_CLASS_D_BIT
) {
768 ret
= snd_soc_dapm_new_controls(
769 dapm
, aic311x_dapm_widgets
,
770 ARRAY_SIZE(aic311x_dapm_widgets
));
774 ret
= snd_soc_dapm_add_routes(dapm
, aic311x_audio_map
,
775 ARRAY_SIZE(aic311x_audio_map
));
779 ret
= snd_soc_dapm_new_controls(
780 dapm
, aic310x_dapm_widgets
,
781 ARRAY_SIZE(aic310x_dapm_widgets
));
785 ret
= snd_soc_dapm_add_routes(dapm
, aic310x_audio_map
,
786 ARRAY_SIZE(aic310x_audio_map
));
794 static int aic31xx_setup_pll(struct snd_soc_component
*component
,
795 struct snd_pcm_hw_params
*params
)
797 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
798 int bclk_score
= snd_soc_params_to_frame_size(params
);
804 if (!aic31xx
->sysclk
|| !aic31xx
->p_div
) {
805 dev_err(component
->dev
, "Master clock not supplied\n");
808 mclk_p
= aic31xx
->sysclk
/ aic31xx
->p_div
;
810 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
811 snd_soc_component_update_bits(component
, AIC31XX_CLKMUX
,
812 AIC31XX_CODEC_CLKIN_MASK
, AIC31XX_CODEC_CLKIN_PLL
);
813 snd_soc_component_update_bits(component
, AIC31XX_IFACE2
,
814 AIC31XX_BDIVCLK_MASK
, AIC31XX_DAC2BCLK
);
816 for (i
= 0; i
< ARRAY_SIZE(aic31xx_divs
); i
++) {
817 if (aic31xx_divs
[i
].rate
== params_rate(params
) &&
818 aic31xx_divs
[i
].mclk_p
== mclk_p
) {
819 int s
= (aic31xx_divs
[i
].dosr
* aic31xx_divs
[i
].mdac
) %
820 snd_soc_params_to_frame_size(params
);
821 int bn
= (aic31xx_divs
[i
].dosr
* aic31xx_divs
[i
].mdac
) /
822 snd_soc_params_to_frame_size(params
);
823 if (s
< bclk_score
&& bn
> 0) {
832 dev_err(component
->dev
,
833 "%s: Sample rate (%u) and format not supported\n",
834 __func__
, params_rate(params
));
835 /* See bellow for details how fix this. */
838 if (bclk_score
!= 0) {
839 dev_warn(component
->dev
, "Can not produce exact bitclock");
840 /* This is fine if using dsp format, but if using i2s
841 there may be trouble. To fix the issue edit the
842 aic31xx_divs table for your mclk and sample
843 rate. Details can be found from:
844 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
845 Section: 5.6 CLOCK Generation and PLL
850 /* PLL configuration */
851 snd_soc_component_update_bits(component
, AIC31XX_PLLPR
, AIC31XX_PLL_MASK
,
852 (aic31xx
->p_div
<< 4) | 0x01);
853 snd_soc_component_write(component
, AIC31XX_PLLJ
, aic31xx_divs
[i
].pll_j
);
855 snd_soc_component_write(component
, AIC31XX_PLLDMSB
,
856 aic31xx_divs
[i
].pll_d
>> 8);
857 snd_soc_component_write(component
, AIC31XX_PLLDLSB
,
858 aic31xx_divs
[i
].pll_d
& 0xff);
860 /* DAC dividers configuration */
861 snd_soc_component_update_bits(component
, AIC31XX_NDAC
, AIC31XX_PLL_MASK
,
862 aic31xx_divs
[i
].ndac
);
863 snd_soc_component_update_bits(component
, AIC31XX_MDAC
, AIC31XX_PLL_MASK
,
864 aic31xx_divs
[i
].mdac
);
866 snd_soc_component_write(component
, AIC31XX_DOSRMSB
, aic31xx_divs
[i
].dosr
>> 8);
867 snd_soc_component_write(component
, AIC31XX_DOSRLSB
, aic31xx_divs
[i
].dosr
& 0xff);
869 /* ADC dividers configuration. Write reset value 1 if not used. */
870 snd_soc_component_update_bits(component
, AIC31XX_NADC
, AIC31XX_PLL_MASK
,
871 aic31xx_divs
[i
].nadc
? aic31xx_divs
[i
].nadc
: 1);
872 snd_soc_component_update_bits(component
, AIC31XX_MADC
, AIC31XX_PLL_MASK
,
873 aic31xx_divs
[i
].madc
? aic31xx_divs
[i
].madc
: 1);
875 snd_soc_component_write(component
, AIC31XX_AOSR
, aic31xx_divs
[i
].aosr
);
877 /* Bit clock divider configuration. */
878 snd_soc_component_update_bits(component
, AIC31XX_BCLKN
,
879 AIC31XX_PLL_MASK
, bclk_n
);
881 aic31xx
->rate_div_line
= i
;
883 dev_dbg(component
->dev
,
884 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
885 aic31xx_divs
[i
].pll_j
,
886 aic31xx_divs
[i
].pll_d
,
888 aic31xx_divs
[i
].dosr
,
889 aic31xx_divs
[i
].ndac
,
890 aic31xx_divs
[i
].mdac
,
891 aic31xx_divs
[i
].aosr
,
892 aic31xx_divs
[i
].nadc
,
893 aic31xx_divs
[i
].madc
,
900 static int aic31xx_hw_params(struct snd_pcm_substream
*substream
,
901 struct snd_pcm_hw_params
*params
,
902 struct snd_soc_dai
*dai
)
904 struct snd_soc_component
*component
= dai
->component
;
907 dev_dbg(component
->dev
, "## %s: width %d rate %d\n",
908 __func__
, params_width(params
),
909 params_rate(params
));
911 switch (params_width(params
)) {
915 data
= (AIC31XX_WORD_LEN_20BITS
<<
916 AIC31XX_IFACE1_DATALEN_SHIFT
);
919 data
= (AIC31XX_WORD_LEN_24BITS
<<
920 AIC31XX_IFACE1_DATALEN_SHIFT
);
923 data
= (AIC31XX_WORD_LEN_32BITS
<<
924 AIC31XX_IFACE1_DATALEN_SHIFT
);
927 dev_err(component
->dev
, "%s: Unsupported width %d\n",
928 __func__
, params_width(params
));
932 snd_soc_component_update_bits(component
, AIC31XX_IFACE1
,
933 AIC31XX_IFACE1_DATALEN_MASK
,
936 return aic31xx_setup_pll(component
, params
);
939 static int aic31xx_dac_mute(struct snd_soc_dai
*codec_dai
, int mute
)
941 struct snd_soc_component
*component
= codec_dai
->component
;
944 snd_soc_component_update_bits(component
, AIC31XX_DACMUTE
,
945 AIC31XX_DACMUTE_MASK
,
946 AIC31XX_DACMUTE_MASK
);
948 snd_soc_component_update_bits(component
, AIC31XX_DACMUTE
,
949 AIC31XX_DACMUTE_MASK
, 0x0);
955 static int aic31xx_clock_master_routes(struct snd_soc_component
*component
,
958 struct snd_soc_dapm_context
*dapm
= snd_soc_component_get_dapm(component
);
959 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
962 fmt
&= SND_SOC_DAIFMT_MASTER_MASK
;
963 if (fmt
== SND_SOC_DAIFMT_CBS_CFS
&&
964 aic31xx
->master_dapm_route_applied
) {
966 * Remove the DAPM route(s) for codec clock master modes,
969 ret
= snd_soc_dapm_del_routes(dapm
, common31xx_cm_audio_map
,
970 ARRAY_SIZE(common31xx_cm_audio_map
));
971 if (!ret
&& !(aic31xx
->codec_type
& DAC31XX_BIT
))
972 ret
= snd_soc_dapm_del_routes(dapm
,
973 aic31xx_cm_audio_map
,
974 ARRAY_SIZE(aic31xx_cm_audio_map
));
979 aic31xx
->master_dapm_route_applied
= false;
980 } else if (fmt
!= SND_SOC_DAIFMT_CBS_CFS
&&
981 !aic31xx
->master_dapm_route_applied
) {
983 * Add the needed DAPM route(s) for codec clock master modes,
984 * if it is not done already
986 ret
= snd_soc_dapm_add_routes(dapm
, common31xx_cm_audio_map
,
987 ARRAY_SIZE(common31xx_cm_audio_map
));
988 if (!ret
&& !(aic31xx
->codec_type
& DAC31XX_BIT
))
989 ret
= snd_soc_dapm_add_routes(dapm
,
990 aic31xx_cm_audio_map
,
991 ARRAY_SIZE(aic31xx_cm_audio_map
));
996 aic31xx
->master_dapm_route_applied
= true;
1002 static int aic31xx_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1005 struct snd_soc_component
*component
= codec_dai
->component
;
1010 dev_dbg(component
->dev
, "## %s: fmt = 0x%x\n", __func__
, fmt
);
1012 /* set master/slave audio interface */
1013 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1014 case SND_SOC_DAIFMT_CBM_CFM
:
1015 iface_reg1
|= AIC31XX_BCLK_MASTER
| AIC31XX_WCLK_MASTER
;
1017 case SND_SOC_DAIFMT_CBS_CFM
:
1018 iface_reg1
|= AIC31XX_WCLK_MASTER
;
1020 case SND_SOC_DAIFMT_CBM_CFS
:
1021 iface_reg1
|= AIC31XX_BCLK_MASTER
;
1023 case SND_SOC_DAIFMT_CBS_CFS
:
1026 dev_err(component
->dev
, "Invalid DAI master/slave interface\n");
1030 /* signal polarity */
1031 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1032 case SND_SOC_DAIFMT_NB_NF
:
1034 case SND_SOC_DAIFMT_IB_NF
:
1035 iface_reg2
|= AIC31XX_BCLKINV_MASK
;
1038 dev_err(component
->dev
, "Invalid DAI clock signal polarity\n");
1042 /* interface format */
1043 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1044 case SND_SOC_DAIFMT_I2S
:
1046 case SND_SOC_DAIFMT_DSP_A
:
1047 dsp_a_val
= 0x1; /* fall through */
1048 case SND_SOC_DAIFMT_DSP_B
:
1050 * NOTE: This CODEC samples on the falling edge of BCLK in
1051 * DSP mode, this is inverted compared to what most DAIs
1052 * expect, so we invert for this mode
1054 iface_reg2
^= AIC31XX_BCLKINV_MASK
;
1055 iface_reg1
|= (AIC31XX_DSP_MODE
<<
1056 AIC31XX_IFACE1_DATATYPE_SHIFT
);
1058 case SND_SOC_DAIFMT_RIGHT_J
:
1059 iface_reg1
|= (AIC31XX_RIGHT_JUSTIFIED_MODE
<<
1060 AIC31XX_IFACE1_DATATYPE_SHIFT
);
1062 case SND_SOC_DAIFMT_LEFT_J
:
1063 iface_reg1
|= (AIC31XX_LEFT_JUSTIFIED_MODE
<<
1064 AIC31XX_IFACE1_DATATYPE_SHIFT
);
1067 dev_err(component
->dev
, "Invalid DAI interface format\n");
1071 snd_soc_component_update_bits(component
, AIC31XX_IFACE1
,
1072 AIC31XX_IFACE1_DATATYPE_MASK
|
1073 AIC31XX_IFACE1_MASTER_MASK
,
1075 snd_soc_component_update_bits(component
, AIC31XX_DATA_OFFSET
,
1076 AIC31XX_DATA_OFFSET_MASK
,
1078 snd_soc_component_update_bits(component
, AIC31XX_IFACE2
,
1079 AIC31XX_BCLKINV_MASK
,
1082 return aic31xx_clock_master_routes(component
, fmt
);
1085 static int aic31xx_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1086 int clk_id
, unsigned int freq
, int dir
)
1088 struct snd_soc_component
*component
= codec_dai
->component
;
1089 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
1092 dev_dbg(component
->dev
, "## %s: clk_id = %d, freq = %d, dir = %d\n",
1093 __func__
, clk_id
, freq
, dir
);
1095 for (i
= 1; i
< 8; i
++)
1096 if (freq
/ i
<= 20000000)
1098 if (freq
/i
> 20000000) {
1099 dev_err(aic31xx
->dev
, "%s: Too high mclk frequency %u\n",
1105 for (i
= 0; i
< ARRAY_SIZE(aic31xx_divs
); i
++)
1106 if (aic31xx_divs
[i
].mclk_p
== freq
/ aic31xx
->p_div
)
1108 if (i
== ARRAY_SIZE(aic31xx_divs
)) {
1109 dev_err(aic31xx
->dev
, "%s: Unsupported frequency %d\n",
1114 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
1115 snd_soc_component_update_bits(component
, AIC31XX_CLKMUX
, AIC31XX_PLL_CLKIN_MASK
,
1116 clk_id
<< AIC31XX_PLL_CLKIN_SHIFT
);
1118 aic31xx
->sysclk
= freq
;
1123 static int aic31xx_regulator_event(struct notifier_block
*nb
,
1124 unsigned long event
, void *data
)
1126 struct aic31xx_disable_nb
*disable_nb
=
1127 container_of(nb
, struct aic31xx_disable_nb
, nb
);
1128 struct aic31xx_priv
*aic31xx
= disable_nb
->aic31xx
;
1130 if (event
& REGULATOR_EVENT_DISABLE
) {
1132 * Put codec to reset and as at least one of the
1133 * supplies was disabled.
1135 if (aic31xx
->gpio_reset
)
1136 gpiod_set_value(aic31xx
->gpio_reset
, 1);
1138 regcache_mark_dirty(aic31xx
->regmap
);
1139 dev_dbg(aic31xx
->dev
, "## %s: DISABLE received\n", __func__
);
1145 static int aic31xx_reset(struct aic31xx_priv
*aic31xx
)
1149 if (aic31xx
->gpio_reset
) {
1150 gpiod_set_value(aic31xx
->gpio_reset
, 1);
1151 ndelay(10); /* At least 10ns */
1152 gpiod_set_value(aic31xx
->gpio_reset
, 0);
1154 ret
= regmap_write(aic31xx
->regmap
, AIC31XX_RESET
, 1);
1156 mdelay(1); /* At least 1ms */
1161 static void aic31xx_clk_on(struct snd_soc_component
*component
)
1163 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
1164 u8 mask
= AIC31XX_PM_MASK
;
1165 u8 on
= AIC31XX_PM_MASK
;
1167 dev_dbg(component
->dev
, "codec clock -> on (rate %d)\n",
1168 aic31xx_divs
[aic31xx
->rate_div_line
].rate
);
1169 snd_soc_component_update_bits(component
, AIC31XX_PLLPR
, mask
, on
);
1171 snd_soc_component_update_bits(component
, AIC31XX_NDAC
, mask
, on
);
1172 snd_soc_component_update_bits(component
, AIC31XX_MDAC
, mask
, on
);
1173 if (aic31xx_divs
[aic31xx
->rate_div_line
].nadc
)
1174 snd_soc_component_update_bits(component
, AIC31XX_NADC
, mask
, on
);
1175 if (aic31xx_divs
[aic31xx
->rate_div_line
].madc
)
1176 snd_soc_component_update_bits(component
, AIC31XX_MADC
, mask
, on
);
1177 snd_soc_component_update_bits(component
, AIC31XX_BCLKN
, mask
, on
);
1180 static void aic31xx_clk_off(struct snd_soc_component
*component
)
1182 u8 mask
= AIC31XX_PM_MASK
;
1185 dev_dbg(component
->dev
, "codec clock -> off\n");
1186 snd_soc_component_update_bits(component
, AIC31XX_BCLKN
, mask
, off
);
1187 snd_soc_component_update_bits(component
, AIC31XX_MADC
, mask
, off
);
1188 snd_soc_component_update_bits(component
, AIC31XX_NADC
, mask
, off
);
1189 snd_soc_component_update_bits(component
, AIC31XX_MDAC
, mask
, off
);
1190 snd_soc_component_update_bits(component
, AIC31XX_NDAC
, mask
, off
);
1191 snd_soc_component_update_bits(component
, AIC31XX_PLLPR
, mask
, off
);
1194 static int aic31xx_power_on(struct snd_soc_component
*component
)
1196 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
1199 ret
= regulator_bulk_enable(ARRAY_SIZE(aic31xx
->supplies
),
1204 regcache_cache_only(aic31xx
->regmap
, false);
1206 /* Reset device registers for a consistent power-on like state */
1207 ret
= aic31xx_reset(aic31xx
);
1209 dev_err(aic31xx
->dev
, "Could not reset device: %d\n", ret
);
1211 ret
= regcache_sync(aic31xx
->regmap
);
1213 dev_err(component
->dev
,
1214 "Failed to restore cache: %d\n", ret
);
1215 regcache_cache_only(aic31xx
->regmap
, true);
1216 regulator_bulk_disable(ARRAY_SIZE(aic31xx
->supplies
),
1224 static void aic31xx_power_off(struct snd_soc_component
*component
)
1226 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
1228 regcache_cache_only(aic31xx
->regmap
, true);
1229 regulator_bulk_disable(ARRAY_SIZE(aic31xx
->supplies
),
1233 static int aic31xx_set_bias_level(struct snd_soc_component
*component
,
1234 enum snd_soc_bias_level level
)
1236 dev_dbg(component
->dev
, "## %s: %d -> %d\n", __func__
,
1237 snd_soc_component_get_bias_level(component
), level
);
1240 case SND_SOC_BIAS_ON
:
1242 case SND_SOC_BIAS_PREPARE
:
1243 if (snd_soc_component_get_bias_level(component
) == SND_SOC_BIAS_STANDBY
)
1244 aic31xx_clk_on(component
);
1246 case SND_SOC_BIAS_STANDBY
:
1247 switch (snd_soc_component_get_bias_level(component
)) {
1248 case SND_SOC_BIAS_OFF
:
1249 aic31xx_power_on(component
);
1251 case SND_SOC_BIAS_PREPARE
:
1252 aic31xx_clk_off(component
);
1258 case SND_SOC_BIAS_OFF
:
1259 if (snd_soc_component_get_bias_level(component
) == SND_SOC_BIAS_STANDBY
)
1260 aic31xx_power_off(component
);
1267 int aic31xx_set_jack(struct snd_soc_component
*component
,
1268 struct snd_soc_jack
*jack
, void *data
)
1270 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
1272 aic31xx
->jack
= jack
;
1274 /* Enable/Disable jack detection */
1275 regmap_write(aic31xx
->regmap
, AIC31XX_HSDETECT
,
1276 jack
? AIC31XX_HSD_ENABLE
: 0);
1281 static int aic31xx_codec_probe(struct snd_soc_component
*component
)
1283 struct aic31xx_priv
*aic31xx
= snd_soc_component_get_drvdata(component
);
1286 dev_dbg(aic31xx
->dev
, "## %s\n", __func__
);
1288 aic31xx
->component
= component
;
1290 for (i
= 0; i
< ARRAY_SIZE(aic31xx
->supplies
); i
++) {
1291 aic31xx
->disable_nb
[i
].nb
.notifier_call
=
1292 aic31xx_regulator_event
;
1293 aic31xx
->disable_nb
[i
].aic31xx
= aic31xx
;
1294 ret
= devm_regulator_register_notifier(
1295 aic31xx
->supplies
[i
].consumer
,
1296 &aic31xx
->disable_nb
[i
].nb
);
1298 dev_err(component
->dev
,
1299 "Failed to request regulator notifier: %d\n",
1305 regcache_cache_only(aic31xx
->regmap
, true);
1306 regcache_mark_dirty(aic31xx
->regmap
);
1308 ret
= aic31xx_add_controls(component
);
1312 ret
= aic31xx_add_widgets(component
);
1319 static const struct snd_soc_component_driver soc_codec_driver_aic31xx
= {
1320 .probe
= aic31xx_codec_probe
,
1321 .set_jack
= aic31xx_set_jack
,
1322 .set_bias_level
= aic31xx_set_bias_level
,
1323 .controls
= common31xx_snd_controls
,
1324 .num_controls
= ARRAY_SIZE(common31xx_snd_controls
),
1325 .dapm_widgets
= common31xx_dapm_widgets
,
1326 .num_dapm_widgets
= ARRAY_SIZE(common31xx_dapm_widgets
),
1327 .dapm_routes
= common31xx_audio_map
,
1328 .num_dapm_routes
= ARRAY_SIZE(common31xx_audio_map
),
1329 .suspend_bias_off
= 1,
1331 .use_pmdown_time
= 1,
1333 .non_legacy_dai_naming
= 1,
1336 static const struct snd_soc_dai_ops aic31xx_dai_ops
= {
1337 .hw_params
= aic31xx_hw_params
,
1338 .set_sysclk
= aic31xx_set_dai_sysclk
,
1339 .set_fmt
= aic31xx_set_dai_fmt
,
1340 .digital_mute
= aic31xx_dac_mute
,
1343 static struct snd_soc_dai_driver dac31xx_dai_driver
[] = {
1345 .name
= "tlv320dac31xx-hifi",
1347 .stream_name
= "Playback",
1350 .rates
= AIC31XX_RATES
,
1351 .formats
= AIC31XX_FORMATS
,
1353 .ops
= &aic31xx_dai_ops
,
1354 .symmetric_rates
= 1,
1358 static struct snd_soc_dai_driver aic31xx_dai_driver
[] = {
1360 .name
= "tlv320aic31xx-hifi",
1362 .stream_name
= "Playback",
1365 .rates
= AIC31XX_RATES
,
1366 .formats
= AIC31XX_FORMATS
,
1369 .stream_name
= "Capture",
1372 .rates
= AIC31XX_RATES
,
1373 .formats
= AIC31XX_FORMATS
,
1375 .ops
= &aic31xx_dai_ops
,
1376 .symmetric_rates
= 1,
1380 #if defined(CONFIG_OF)
1381 static const struct of_device_id tlv320aic31xx_of_match
[] = {
1382 { .compatible
= "ti,tlv320aic310x" },
1383 { .compatible
= "ti,tlv320aic311x" },
1384 { .compatible
= "ti,tlv320aic3100" },
1385 { .compatible
= "ti,tlv320aic3110" },
1386 { .compatible
= "ti,tlv320aic3120" },
1387 { .compatible
= "ti,tlv320aic3111" },
1388 { .compatible
= "ti,tlv320dac3100" },
1389 { .compatible
= "ti,tlv320dac3101" },
1392 MODULE_DEVICE_TABLE(of
, tlv320aic31xx_of_match
);
1393 #endif /* CONFIG_OF */
1396 static const struct acpi_device_id aic31xx_acpi_match
[] = {
1400 MODULE_DEVICE_TABLE(acpi
, aic31xx_acpi_match
);
1403 static irqreturn_t
aic31xx_irq(int irq
, void *data
)
1405 struct aic31xx_priv
*aic31xx
= data
;
1406 struct device
*dev
= aic31xx
->dev
;
1408 bool handled
= false;
1411 ret
= regmap_read(aic31xx
->regmap
, AIC31XX_INTRDACFLAG
, &value
);
1413 dev_err(dev
, "Failed to read interrupt mask: %d\n", ret
);
1422 if (value
& AIC31XX_HPLSCDETECT
)
1423 dev_err(dev
, "Short circuit on Left output is detected\n");
1424 if (value
& AIC31XX_HPRSCDETECT
)
1425 dev_err(dev
, "Short circuit on Right output is detected\n");
1426 if (value
& (AIC31XX_HSPLUG
| AIC31XX_BUTTONPRESS
)) {
1430 ret
= regmap_read(aic31xx
->regmap
, AIC31XX_INTRDACFLAG2
,
1433 dev_err(dev
, "Failed to read interrupt mask: %d\n",
1438 if (val
& AIC31XX_BUTTONPRESS
)
1439 status
|= SND_JACK_BTN_0
;
1441 ret
= regmap_read(aic31xx
->regmap
, AIC31XX_HSDETECT
, &val
);
1443 dev_err(dev
, "Failed to read headset type: %d\n", ret
);
1447 switch ((val
& AIC31XX_HSD_TYPE_MASK
) >>
1448 AIC31XX_HSD_TYPE_SHIFT
) {
1449 case AIC31XX_HSD_HP
:
1450 status
|= SND_JACK_HEADPHONE
;
1452 case AIC31XX_HSD_HS
:
1453 status
|= SND_JACK_HEADSET
;
1460 snd_soc_jack_report(aic31xx
->jack
, status
,
1463 if (value
& ~(AIC31XX_HPLSCDETECT
|
1464 AIC31XX_HPRSCDETECT
|
1466 AIC31XX_BUTTONPRESS
))
1467 dev_err(dev
, "Unknown DAC interrupt flags: 0x%08x\n", value
);
1470 ret
= regmap_read(aic31xx
->regmap
, AIC31XX_OFFLAG
, &value
);
1472 dev_err(dev
, "Failed to read overflow flag: %d\n", ret
);
1481 if (value
& AIC31XX_DAC_OF_LEFT
)
1482 dev_warn(dev
, "Left-channel DAC overflow has occurred\n");
1483 if (value
& AIC31XX_DAC_OF_RIGHT
)
1484 dev_warn(dev
, "Right-channel DAC overflow has occurred\n");
1485 if (value
& AIC31XX_DAC_OF_SHIFTER
)
1486 dev_warn(dev
, "DAC barrel shifter overflow has occurred\n");
1487 if (value
& AIC31XX_ADC_OF
)
1488 dev_warn(dev
, "ADC overflow has occurred\n");
1489 if (value
& AIC31XX_ADC_OF_SHIFTER
)
1490 dev_warn(dev
, "ADC barrel shifter overflow has occurred\n");
1491 if (value
& ~(AIC31XX_DAC_OF_LEFT
|
1492 AIC31XX_DAC_OF_RIGHT
|
1493 AIC31XX_DAC_OF_SHIFTER
|
1495 AIC31XX_ADC_OF_SHIFTER
))
1496 dev_warn(dev
, "Unknown overflow interrupt flags: 0x%08x\n", value
);
1505 static int aic31xx_i2c_probe(struct i2c_client
*i2c
,
1506 const struct i2c_device_id
*id
)
1508 struct aic31xx_priv
*aic31xx
;
1509 unsigned int micbias_value
= MICBIAS_2_0V
;
1512 dev_dbg(&i2c
->dev
, "## %s: %s codec_type = %d\n", __func__
,
1513 id
->name
, (int)id
->driver_data
);
1515 aic31xx
= devm_kzalloc(&i2c
->dev
, sizeof(*aic31xx
), GFP_KERNEL
);
1519 aic31xx
->regmap
= devm_regmap_init_i2c(i2c
, &aic31xx_i2c_regmap
);
1520 if (IS_ERR(aic31xx
->regmap
)) {
1521 ret
= PTR_ERR(aic31xx
->regmap
);
1522 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
1526 aic31xx
->dev
= &i2c
->dev
;
1527 aic31xx
->irq
= i2c
->irq
;
1529 aic31xx
->codec_type
= id
->driver_data
;
1531 dev_set_drvdata(aic31xx
->dev
, aic31xx
);
1533 fwnode_property_read_u32(aic31xx
->dev
->fwnode
, "ai31xx-micbias-vg",
1535 switch (micbias_value
) {
1539 aic31xx
->micbias_vg
= micbias_value
;
1542 dev_err(aic31xx
->dev
, "Bad ai31xx-micbias-vg value %d\n",
1544 aic31xx
->micbias_vg
= MICBIAS_2_0V
;
1547 if (dev_get_platdata(aic31xx
->dev
)) {
1548 memcpy(&aic31xx
->pdata
, dev_get_platdata(aic31xx
->dev
), sizeof(aic31xx
->pdata
));
1549 aic31xx
->codec_type
= aic31xx
->pdata
.codec_type
;
1550 aic31xx
->micbias_vg
= aic31xx
->pdata
.micbias_vg
;
1553 aic31xx
->gpio_reset
= devm_gpiod_get_optional(aic31xx
->dev
, "reset",
1555 if (IS_ERR(aic31xx
->gpio_reset
)) {
1556 dev_err(aic31xx
->dev
, "not able to acquire gpio\n");
1557 return PTR_ERR(aic31xx
->gpio_reset
);
1560 for (i
= 0; i
< ARRAY_SIZE(aic31xx
->supplies
); i
++)
1561 aic31xx
->supplies
[i
].supply
= aic31xx_supply_names
[i
];
1563 ret
= devm_regulator_bulk_get(aic31xx
->dev
,
1564 ARRAY_SIZE(aic31xx
->supplies
),
1567 dev_err(aic31xx
->dev
, "Failed to request supplies: %d\n", ret
);
1571 if (aic31xx
->irq
> 0) {
1572 regmap_update_bits(aic31xx
->regmap
, AIC31XX_GPIO1
,
1573 AIC31XX_GPIO1_FUNC_MASK
,
1574 AIC31XX_GPIO1_INT1
<<
1575 AIC31XX_GPIO1_FUNC_SHIFT
);
1577 regmap_write(aic31xx
->regmap
, AIC31XX_INT1CTRL
,
1579 AIC31XX_BUTTONPRESSDET
|
1583 ret
= devm_request_threaded_irq(aic31xx
->dev
, aic31xx
->irq
,
1585 IRQF_ONESHOT
, "aic31xx-irq",
1588 dev_err(aic31xx
->dev
, "Unable to request IRQ\n");
1593 if (aic31xx
->codec_type
& DAC31XX_BIT
)
1594 return devm_snd_soc_register_component(&i2c
->dev
,
1595 &soc_codec_driver_aic31xx
,
1597 ARRAY_SIZE(dac31xx_dai_driver
));
1599 return devm_snd_soc_register_component(&i2c
->dev
,
1600 &soc_codec_driver_aic31xx
,
1602 ARRAY_SIZE(aic31xx_dai_driver
));
1605 static const struct i2c_device_id aic31xx_i2c_id
[] = {
1606 { "tlv320aic310x", AIC3100
},
1607 { "tlv320aic311x", AIC3110
},
1608 { "tlv320aic3100", AIC3100
},
1609 { "tlv320aic3110", AIC3110
},
1610 { "tlv320aic3120", AIC3120
},
1611 { "tlv320aic3111", AIC3111
},
1612 { "tlv320dac3100", DAC3100
},
1613 { "tlv320dac3101", DAC3101
},
1616 MODULE_DEVICE_TABLE(i2c
, aic31xx_i2c_id
);
1618 static struct i2c_driver aic31xx_i2c_driver
= {
1620 .name
= "tlv320aic31xx-codec",
1621 .of_match_table
= of_match_ptr(tlv320aic31xx_of_match
),
1622 .acpi_match_table
= ACPI_PTR(aic31xx_acpi_match
),
1624 .probe
= aic31xx_i2c_probe
,
1625 .id_table
= aic31xx_i2c_id
,
1627 module_i2c_driver(aic31xx_i2c_driver
);
1629 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1630 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1631 MODULE_LICENSE("GPL v2");