1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/sound/soc/codecs/tlv320aic32x4.c
5 * Copyright 2011 Vista Silicon S.L.
7 * Author: Javier Martin <javier.martin@vista-silicon.com>
9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/of_gpio.h>
19 #include <linux/cdev.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
22 #include <linux/of_clk.h>
23 #include <linux/regulator/consumer.h>
25 #include <sound/tlv320aic32x4.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
34 #include "tlv320aic32x4.h"
37 struct regmap
*regmap
;
42 const char *mclk_name
;
44 struct regulator
*supply_ldo
;
45 struct regulator
*supply_iov
;
46 struct regulator
*supply_dv
;
47 struct regulator
*supply_av
;
49 struct aic32x4_setup_data
*setup
;
53 static int aic32x4_reset_adc(struct snd_soc_dapm_widget
*w
,
54 struct snd_kcontrol
*kcontrol
, int event
)
56 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
60 * Workaround: the datasheet does not mention a required programming
61 * sequence but experiments show the ADC needs to be reset after each
62 * capture to avoid audible artifacts.
65 case SND_SOC_DAPM_POST_PMD
:
66 adc_reg
= snd_soc_component_read(component
, AIC32X4_ADCSETUP
);
67 snd_soc_component_write(component
, AIC32X4_ADCSETUP
, adc_reg
|
68 AIC32X4_LADC_EN
| AIC32X4_RADC_EN
);
69 snd_soc_component_write(component
, AIC32X4_ADCSETUP
, adc_reg
);
75 static int mic_bias_event(struct snd_soc_dapm_widget
*w
,
76 struct snd_kcontrol
*kcontrol
, int event
)
78 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
81 case SND_SOC_DAPM_POST_PMU
:
82 /* Change Mic Bias Registor */
83 snd_soc_component_update_bits(component
, AIC32X4_MICBIAS
,
85 AIC32X4_MICBIAS_LDOIN
|
86 AIC32X4_MICBIAS_2075V
);
87 printk(KERN_DEBUG
"%s: Mic Bias will be turned ON\n", __func__
);
89 case SND_SOC_DAPM_PRE_PMD
:
90 snd_soc_component_update_bits(component
, AIC32X4_MICBIAS
,
91 AIC32x4_MICBIAS_MASK
, 0);
92 printk(KERN_DEBUG
"%s: Mic Bias will be turned OFF\n",
101 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol
*kcontrol
,
102 struct snd_ctl_elem_value
*ucontrol
)
104 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
107 val
= snd_soc_component_read(component
, AIC32X4_DINCTL
);
109 ucontrol
->value
.integer
.value
[0] = (val
& 0x01);
114 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol
*kcontrol
,
115 struct snd_ctl_elem_value
*ucontrol
)
117 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
121 val
= snd_soc_component_read(component
, AIC32X4_DOUTCTL
);
122 gpio_check
= (val
& AIC32X4_MFP_GPIO_ENABLED
);
123 if (gpio_check
!= AIC32X4_MFP_GPIO_ENABLED
) {
124 printk(KERN_ERR
"%s: MFP2 is not configure as a GPIO output\n",
129 if (ucontrol
->value
.integer
.value
[0] == (val
& AIC32X4_MFP2_GPIO_OUT_HIGH
))
132 if (ucontrol
->value
.integer
.value
[0])
133 val
|= ucontrol
->value
.integer
.value
[0];
135 val
&= ~AIC32X4_MFP2_GPIO_OUT_HIGH
;
137 snd_soc_component_write(component
, AIC32X4_DOUTCTL
, val
);
142 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol
*kcontrol
,
143 struct snd_ctl_elem_value
*ucontrol
)
145 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
148 val
= snd_soc_component_read(component
, AIC32X4_SCLKCTL
);
150 ucontrol
->value
.integer
.value
[0] = (val
& 0x01);
155 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol
*kcontrol
,
156 struct snd_ctl_elem_value
*ucontrol
)
158 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
162 val
= snd_soc_component_read(component
, AIC32X4_MISOCTL
);
163 gpio_check
= (val
& AIC32X4_MFP_GPIO_ENABLED
);
164 if (gpio_check
!= AIC32X4_MFP_GPIO_ENABLED
) {
165 printk(KERN_ERR
"%s: MFP4 is not configure as a GPIO output\n",
170 if (ucontrol
->value
.integer
.value
[0] == (val
& AIC32X4_MFP5_GPIO_OUT_HIGH
))
173 if (ucontrol
->value
.integer
.value
[0])
174 val
|= ucontrol
->value
.integer
.value
[0];
176 val
&= ~AIC32X4_MFP5_GPIO_OUT_HIGH
;
178 snd_soc_component_write(component
, AIC32X4_MISOCTL
, val
);
183 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol
*kcontrol
,
184 struct snd_ctl_elem_value
*ucontrol
)
186 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
189 val
= snd_soc_component_read(component
, AIC32X4_GPIOCTL
);
190 ucontrol
->value
.integer
.value
[0] = ((val
& 0x2) >> 1);
195 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol
*kcontrol
,
196 struct snd_ctl_elem_value
*ucontrol
)
198 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
202 val
= snd_soc_component_read(component
, AIC32X4_GPIOCTL
);
203 gpio_check
= (val
& AIC32X4_MFP5_GPIO_OUTPUT
);
204 if (gpio_check
!= AIC32X4_MFP5_GPIO_OUTPUT
) {
205 printk(KERN_ERR
"%s: MFP5 is not configure as a GPIO output\n",
210 if (ucontrol
->value
.integer
.value
[0] == (val
& 0x1))
213 if (ucontrol
->value
.integer
.value
[0])
214 val
|= ucontrol
->value
.integer
.value
[0];
218 snd_soc_component_write(component
, AIC32X4_GPIOCTL
, val
);
223 static const struct snd_kcontrol_new aic32x4_mfp1
[] = {
224 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio
, NULL
),
227 static const struct snd_kcontrol_new aic32x4_mfp2
[] = {
228 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL
, aic32x4_set_mfp2_gpio
),
231 static const struct snd_kcontrol_new aic32x4_mfp3
[] = {
232 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio
, NULL
),
235 static const struct snd_kcontrol_new aic32x4_mfp4
[] = {
236 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL
, aic32x4_set_mfp4_gpio
),
239 static const struct snd_kcontrol_new aic32x4_mfp5
[] = {
240 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio
,
241 aic32x4_set_mfp5_gpio
),
244 /* 0dB min, 0.5dB steps */
245 static DECLARE_TLV_DB_SCALE(tlv_step_0_5
, 0, 50, 0);
246 /* -63.5dB min, 0.5dB steps */
247 static DECLARE_TLV_DB_SCALE(tlv_pcm
, -6350, 50, 0);
248 /* -6dB min, 1dB steps */
249 static DECLARE_TLV_DB_SCALE(tlv_driver_gain
, -600, 100, 0);
250 /* -12dB min, 0.5dB steps */
251 static DECLARE_TLV_DB_SCALE(tlv_adc_vol
, -1200, 50, 0);
253 static const char * const lo_cm_text
[] = {
254 "Full Chip", "1.65V",
257 static SOC_ENUM_SINGLE_DECL(lo_cm_enum
, AIC32X4_CMMODE
, 3, lo_cm_text
);
259 static const char * const ptm_text
[] = {
263 static SOC_ENUM_SINGLE_DECL(l_ptm_enum
, AIC32X4_LPLAYBACK
, 2, ptm_text
);
264 static SOC_ENUM_SINGLE_DECL(r_ptm_enum
, AIC32X4_RPLAYBACK
, 2, ptm_text
);
266 static const struct snd_kcontrol_new aic32x4_snd_controls
[] = {
267 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL
,
268 AIC32X4_RDACVOL
, 0, -0x7f, 0x30, 7, 0, tlv_pcm
),
269 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum
),
270 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum
),
271 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN
,
272 AIC32X4_HPRGAIN
, 0, -0x6, 0x1d, 5, 0,
274 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN
,
275 AIC32X4_LORGAIN
, 0, -0x6, 0x1d, 5, 0,
277 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN
,
278 AIC32X4_HPRGAIN
, 6, 0x01, 1),
279 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN
,
280 AIC32X4_LORGAIN
, 6, 0x01, 1),
281 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum
),
282 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL
,
283 AIC32X4_RMICPGAVOL
, 7, 0x01, 1),
285 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA
, 7, 1, 0),
286 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA
, 3, 1, 0),
288 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL
,
289 AIC32X4_RADCVOL
, 0, -0x18, 0x28, 6, 0, tlv_adc_vol
),
290 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL
,
291 AIC32X4_RMICPGAVOL
, 0, 0x5f, 0, tlv_step_0_5
),
293 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE
, 4, 7, 0),
295 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1
, 7, 1, 0),
296 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1
, 7, 1, 0),
297 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1
, AIC32X4_RAGC1
,
299 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1
, AIC32X4_RAGC1
,
301 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2
, AIC32X4_RAGC2
,
303 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2
, AIC32X4_RAGC2
,
305 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3
, AIC32X4_RAGC3
,
307 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4
, AIC32X4_RAGC4
,
309 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5
, AIC32X4_RAGC5
,
311 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6
, AIC32X4_RAGC6
,
313 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7
, AIC32X4_RAGC7
,
317 static const struct snd_kcontrol_new hpl_output_mixer_controls
[] = {
318 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE
, 3, 1, 0),
319 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE
, 2, 1, 0),
322 static const struct snd_kcontrol_new hpr_output_mixer_controls
[] = {
323 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE
, 3, 1, 0),
324 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE
, 2, 1, 0),
327 static const struct snd_kcontrol_new lol_output_mixer_controls
[] = {
328 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE
, 3, 1, 0),
331 static const struct snd_kcontrol_new lor_output_mixer_controls
[] = {
332 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE
, 3, 1, 0),
335 static const char * const resistor_text
[] = {
336 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
339 /* Left mixer pins */
340 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum
, AIC32X4_LMICPGAPIN
, 6, resistor_text
);
341 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum
, AIC32X4_LMICPGAPIN
, 4, resistor_text
);
342 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum
, AIC32X4_LMICPGAPIN
, 2, resistor_text
);
343 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum
, AIC32X4_LMICPGAPIN
, 0, resistor_text
);
345 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum
, AIC32X4_LMICPGANIN
, 6, resistor_text
);
346 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum
, AIC32X4_LMICPGANIN
, 4, resistor_text
);
347 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum
, AIC32X4_LMICPGANIN
, 2, resistor_text
);
349 static const struct snd_kcontrol_new in1l_to_lmixer_controls
[] = {
350 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum
),
352 static const struct snd_kcontrol_new in2l_to_lmixer_controls
[] = {
353 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum
),
355 static const struct snd_kcontrol_new in3l_to_lmixer_controls
[] = {
356 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum
),
358 static const struct snd_kcontrol_new in1r_to_lmixer_controls
[] = {
359 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum
),
361 static const struct snd_kcontrol_new cml_to_lmixer_controls
[] = {
362 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum
),
364 static const struct snd_kcontrol_new in2r_to_lmixer_controls
[] = {
365 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum
),
367 static const struct snd_kcontrol_new in3r_to_lmixer_controls
[] = {
368 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum
),
371 /* Right mixer pins */
372 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum
, AIC32X4_RMICPGAPIN
, 6, resistor_text
);
373 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum
, AIC32X4_RMICPGAPIN
, 4, resistor_text
);
374 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum
, AIC32X4_RMICPGAPIN
, 2, resistor_text
);
375 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum
, AIC32X4_RMICPGAPIN
, 0, resistor_text
);
376 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum
, AIC32X4_RMICPGANIN
, 6, resistor_text
);
377 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum
, AIC32X4_RMICPGANIN
, 4, resistor_text
);
378 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum
, AIC32X4_RMICPGANIN
, 2, resistor_text
);
380 static const struct snd_kcontrol_new in1r_to_rmixer_controls
[] = {
381 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum
),
383 static const struct snd_kcontrol_new in2r_to_rmixer_controls
[] = {
384 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum
),
386 static const struct snd_kcontrol_new in3r_to_rmixer_controls
[] = {
387 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum
),
389 static const struct snd_kcontrol_new in2l_to_rmixer_controls
[] = {
390 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum
),
392 static const struct snd_kcontrol_new cmr_to_rmixer_controls
[] = {
393 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum
),
395 static const struct snd_kcontrol_new in1l_to_rmixer_controls
[] = {
396 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum
),
398 static const struct snd_kcontrol_new in3l_to_rmixer_controls
[] = {
399 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum
),
402 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets
[] = {
403 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP
, 7, 0),
404 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM
, 0, 0,
405 &hpl_output_mixer_controls
[0],
406 ARRAY_SIZE(hpl_output_mixer_controls
)),
407 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL
, 5, 0, NULL
, 0),
409 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM
, 0, 0,
410 &lol_output_mixer_controls
[0],
411 ARRAY_SIZE(lol_output_mixer_controls
)),
412 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL
, 3, 0, NULL
, 0),
414 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP
, 6, 0),
415 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM
, 0, 0,
416 &hpr_output_mixer_controls
[0],
417 ARRAY_SIZE(hpr_output_mixer_controls
)),
418 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL
, 4, 0, NULL
, 0),
419 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM
, 0, 0,
420 &lor_output_mixer_controls
[0],
421 ARRAY_SIZE(lor_output_mixer_controls
)),
422 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL
, 2, 0, NULL
, 0),
424 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP
, 6, 0),
425 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
426 in1r_to_rmixer_controls
),
427 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
428 in2r_to_rmixer_controls
),
429 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
430 in3r_to_rmixer_controls
),
431 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
432 in2l_to_rmixer_controls
),
433 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM
, 0, 0,
434 cmr_to_rmixer_controls
),
435 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM
, 0, 0,
436 in1l_to_rmixer_controls
),
437 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM
, 0, 0,
438 in3l_to_rmixer_controls
),
440 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP
, 7, 0),
441 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
442 in1l_to_lmixer_controls
),
443 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
444 in2l_to_lmixer_controls
),
445 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
446 in3l_to_lmixer_controls
),
447 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM
, 0, 0,
448 in1r_to_lmixer_controls
),
449 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM
, 0, 0,
450 cml_to_lmixer_controls
),
451 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM
, 0, 0,
452 in2r_to_lmixer_controls
),
453 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM
, 0, 0,
454 in3r_to_lmixer_controls
),
456 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS
, 6, 0, mic_bias_event
,
457 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
459 SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc
),
461 SND_SOC_DAPM_OUTPUT("HPL"),
462 SND_SOC_DAPM_OUTPUT("HPR"),
463 SND_SOC_DAPM_OUTPUT("LOL"),
464 SND_SOC_DAPM_OUTPUT("LOR"),
465 SND_SOC_DAPM_INPUT("IN1_L"),
466 SND_SOC_DAPM_INPUT("IN1_R"),
467 SND_SOC_DAPM_INPUT("IN2_L"),
468 SND_SOC_DAPM_INPUT("IN2_R"),
469 SND_SOC_DAPM_INPUT("IN3_L"),
470 SND_SOC_DAPM_INPUT("IN3_R"),
471 SND_SOC_DAPM_INPUT("CM_L"),
472 SND_SOC_DAPM_INPUT("CM_R"),
475 static const struct snd_soc_dapm_route aic32x4_dapm_routes
[] = {
477 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
478 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
480 {"HPL Power", NULL
, "HPL Output Mixer"},
481 {"HPL", NULL
, "HPL Power"},
483 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
485 {"LOL Power", NULL
, "LOL Output Mixer"},
486 {"LOL", NULL
, "LOL Power"},
489 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
490 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
492 {"HPR Power", NULL
, "HPR Output Mixer"},
493 {"HPR", NULL
, "HPR Power"},
495 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
497 {"LOR Power", NULL
, "LOR Output Mixer"},
498 {"LOR", NULL
, "LOR Power"},
501 {"Right ADC", NULL
, "IN1_R to Right Mixer Positive Resistor"},
502 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
503 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
504 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
506 {"Right ADC", NULL
, "IN2_R to Right Mixer Positive Resistor"},
507 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
508 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
509 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
511 {"Right ADC", NULL
, "IN3_R to Right Mixer Positive Resistor"},
512 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
513 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
514 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
516 {"Right ADC", NULL
, "IN2_L to Right Mixer Positive Resistor"},
517 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
518 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
519 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
521 {"Right ADC", NULL
, "CM_R to Right Mixer Negative Resistor"},
522 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
523 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
524 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
526 {"Right ADC", NULL
, "IN1_L to Right Mixer Negative Resistor"},
527 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
528 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
529 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
531 {"Right ADC", NULL
, "IN3_L to Right Mixer Negative Resistor"},
532 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
533 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
534 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
537 {"Left ADC", NULL
, "IN1_L to Left Mixer Positive Resistor"},
538 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
539 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
540 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
542 {"Left ADC", NULL
, "IN2_L to Left Mixer Positive Resistor"},
543 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
544 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
545 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
547 {"Left ADC", NULL
, "IN3_L to Left Mixer Positive Resistor"},
548 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
549 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
550 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
552 {"Left ADC", NULL
, "IN1_R to Left Mixer Positive Resistor"},
553 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
554 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
555 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
557 {"Left ADC", NULL
, "CM_L to Left Mixer Negative Resistor"},
558 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
559 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
560 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
562 {"Left ADC", NULL
, "IN2_R to Left Mixer Negative Resistor"},
563 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
564 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
565 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
567 {"Left ADC", NULL
, "IN3_R to Left Mixer Negative Resistor"},
568 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
569 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
570 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
573 static const struct regmap_range_cfg aic32x4_regmap_pages
[] = {
576 .selector_mask
= 0xff,
580 .range_max
= AIC32X4_RMICPGAVOL
,
584 const struct regmap_config aic32x4_regmap_config
= {
585 .max_register
= AIC32X4_RMICPGAVOL
,
586 .ranges
= aic32x4_regmap_pages
,
587 .num_ranges
= ARRAY_SIZE(aic32x4_regmap_pages
),
589 EXPORT_SYMBOL(aic32x4_regmap_config
);
591 static int aic32x4_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
592 int clk_id
, unsigned int freq
, int dir
)
594 struct snd_soc_component
*component
= codec_dai
->component
;
598 pll
= devm_clk_get(component
->dev
, "pll");
602 mclk
= clk_get_parent(pll
);
604 return clk_set_rate(mclk
, freq
);
607 static int aic32x4_set_dai_fmt(struct snd_soc_dai
*codec_dai
, unsigned int fmt
)
609 struct snd_soc_component
*component
= codec_dai
->component
;
614 /* set master/slave audio interface */
615 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
616 case SND_SOC_DAIFMT_CBM_CFM
:
617 iface_reg_1
|= AIC32X4_BCLKMASTER
| AIC32X4_WCLKMASTER
;
619 case SND_SOC_DAIFMT_CBS_CFS
:
622 printk(KERN_ERR
"aic32x4: invalid DAI master/slave interface\n");
626 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
627 case SND_SOC_DAIFMT_I2S
:
629 case SND_SOC_DAIFMT_DSP_A
:
630 iface_reg_1
|= (AIC32X4_DSP_MODE
<<
631 AIC32X4_IFACE1_DATATYPE_SHIFT
);
632 iface_reg_3
|= AIC32X4_BCLKINV_MASK
; /* invert bit clock */
633 iface_reg_2
= 0x01; /* add offset 1 */
635 case SND_SOC_DAIFMT_DSP_B
:
636 iface_reg_1
|= (AIC32X4_DSP_MODE
<<
637 AIC32X4_IFACE1_DATATYPE_SHIFT
);
638 iface_reg_3
|= AIC32X4_BCLKINV_MASK
; /* invert bit clock */
640 case SND_SOC_DAIFMT_RIGHT_J
:
641 iface_reg_1
|= (AIC32X4_RIGHT_JUSTIFIED_MODE
<<
642 AIC32X4_IFACE1_DATATYPE_SHIFT
);
644 case SND_SOC_DAIFMT_LEFT_J
:
645 iface_reg_1
|= (AIC32X4_LEFT_JUSTIFIED_MODE
<<
646 AIC32X4_IFACE1_DATATYPE_SHIFT
);
649 printk(KERN_ERR
"aic32x4: invalid DAI interface format\n");
653 snd_soc_component_update_bits(component
, AIC32X4_IFACE1
,
654 AIC32X4_IFACE1_DATATYPE_MASK
|
655 AIC32X4_IFACE1_MASTER_MASK
, iface_reg_1
);
656 snd_soc_component_update_bits(component
, AIC32X4_IFACE2
,
657 AIC32X4_DATA_OFFSET_MASK
, iface_reg_2
);
658 snd_soc_component_update_bits(component
, AIC32X4_IFACE3
,
659 AIC32X4_BCLKINV_MASK
, iface_reg_3
);
664 static int aic32x4_set_aosr(struct snd_soc_component
*component
, u8 aosr
)
666 return snd_soc_component_write(component
, AIC32X4_AOSR
, aosr
);
669 static int aic32x4_set_dosr(struct snd_soc_component
*component
, u16 dosr
)
671 snd_soc_component_write(component
, AIC32X4_DOSRMSB
, dosr
>> 8);
672 snd_soc_component_write(component
, AIC32X4_DOSRLSB
,
678 static int aic32x4_set_processing_blocks(struct snd_soc_component
*component
,
679 u8 r_block
, u8 p_block
)
681 if (r_block
> 18 || p_block
> 25)
684 snd_soc_component_write(component
, AIC32X4_ADCSPB
, r_block
);
685 snd_soc_component_write(component
, AIC32X4_DACSPB
, p_block
);
690 static int aic32x4_setup_clocks(struct snd_soc_component
*component
,
691 unsigned int sample_rate
, unsigned int channel
,
692 unsigned int bit_depth
)
696 u8 adc_resource_class
, dac_resource_class
;
697 u8 madc
, nadc
, mdac
, ndac
, max_nadc
, min_mdac
, max_ndac
;
699 u16 max_dosr
, min_dosr
;
700 unsigned long adc_clock_rate
, dac_clock_rate
;
703 struct clk_bulk_data clocks
[] = {
711 ret
= devm_clk_bulk_get(component
->dev
, ARRAY_SIZE(clocks
), clocks
);
715 if (sample_rate
<= 48000) {
717 adc_resource_class
= 6;
718 dac_resource_class
= 8;
720 aic32x4_set_processing_blocks(component
, 1, 1);
721 } else if (sample_rate
<= 96000) {
723 adc_resource_class
= 6;
724 dac_resource_class
= 8;
726 aic32x4_set_processing_blocks(component
, 1, 9);
727 } else if (sample_rate
== 192000) {
729 adc_resource_class
= 3;
730 dac_resource_class
= 4;
732 aic32x4_set_processing_blocks(component
, 13, 19);
734 dev_err(component
->dev
, "Sampling rate not supported\n");
738 madc
= DIV_ROUND_UP((32 * adc_resource_class
), aosr
);
739 max_dosr
= (AIC32X4_MAX_DOSR_FREQ
/ sample_rate
/ dosr_increment
) *
741 min_dosr
= (AIC32X4_MIN_DOSR_FREQ
/ sample_rate
/ dosr_increment
) *
743 max_nadc
= AIC32X4_MAX_CODEC_CLKIN_FREQ
/ (madc
* aosr
* sample_rate
);
745 for (nadc
= max_nadc
; nadc
> 0; --nadc
) {
746 adc_clock_rate
= nadc
* madc
* aosr
* sample_rate
;
747 for (dosr
= max_dosr
; dosr
>= min_dosr
;
748 dosr
-= dosr_increment
) {
749 min_mdac
= DIV_ROUND_UP((32 * dac_resource_class
), dosr
);
750 max_ndac
= AIC32X4_MAX_CODEC_CLKIN_FREQ
/
751 (min_mdac
* dosr
* sample_rate
);
752 for (mdac
= min_mdac
; mdac
<= 128; ++mdac
) {
753 for (ndac
= max_ndac
; ndac
> 0; --ndac
) {
754 dac_clock_rate
= ndac
* mdac
* dosr
*
756 if (dac_clock_rate
== adc_clock_rate
) {
757 if (clk_round_rate(clocks
[0].clk
, dac_clock_rate
) == 0)
760 clk_set_rate(clocks
[0].clk
,
763 clk_set_rate(clocks
[1].clk
,
766 clk_set_rate(clocks
[2].clk
,
768 aic32x4_set_aosr(component
,
771 clk_set_rate(clocks
[3].clk
,
774 clk_set_rate(clocks
[4].clk
,
776 aic32x4_set_dosr(component
,
779 clk_set_rate(clocks
[5].clk
,
780 sample_rate
* channel
*
789 dev_err(component
->dev
,
790 "Could not set clocks to support sample rate.\n");
794 static int aic32x4_hw_params(struct snd_pcm_substream
*substream
,
795 struct snd_pcm_hw_params
*params
,
796 struct snd_soc_dai
*dai
)
798 struct snd_soc_component
*component
= dai
->component
;
799 struct aic32x4_priv
*aic32x4
= snd_soc_component_get_drvdata(component
);
803 aic32x4_setup_clocks(component
, params_rate(params
),
804 params_channels(params
),
805 params_physical_width(params
));
807 switch (params_physical_width(params
)) {
809 iface1_reg
|= (AIC32X4_WORD_LEN_16BITS
<<
810 AIC32X4_IFACE1_DATALEN_SHIFT
);
813 iface1_reg
|= (AIC32X4_WORD_LEN_20BITS
<<
814 AIC32X4_IFACE1_DATALEN_SHIFT
);
817 iface1_reg
|= (AIC32X4_WORD_LEN_24BITS
<<
818 AIC32X4_IFACE1_DATALEN_SHIFT
);
821 iface1_reg
|= (AIC32X4_WORD_LEN_32BITS
<<
822 AIC32X4_IFACE1_DATALEN_SHIFT
);
825 snd_soc_component_update_bits(component
, AIC32X4_IFACE1
,
826 AIC32X4_IFACE1_DATALEN_MASK
, iface1_reg
);
828 if (params_channels(params
) == 1) {
829 dacsetup_reg
= AIC32X4_RDAC2LCHN
| AIC32X4_LDAC2LCHN
;
831 if (aic32x4
->swapdacs
)
832 dacsetup_reg
= AIC32X4_RDAC2LCHN
| AIC32X4_LDAC2RCHN
;
834 dacsetup_reg
= AIC32X4_LDAC2LCHN
| AIC32X4_RDAC2RCHN
;
836 snd_soc_component_update_bits(component
, AIC32X4_DACSETUP
,
837 AIC32X4_DAC_CHAN_MASK
, dacsetup_reg
);
842 static int aic32x4_mute(struct snd_soc_dai
*dai
, int mute
, int direction
)
844 struct snd_soc_component
*component
= dai
->component
;
846 snd_soc_component_update_bits(component
, AIC32X4_DACMUTE
,
847 AIC32X4_MUTEON
, mute
? AIC32X4_MUTEON
: 0);
852 static int aic32x4_set_bias_level(struct snd_soc_component
*component
,
853 enum snd_soc_bias_level level
)
857 struct clk_bulk_data clocks
[] = {
863 ret
= devm_clk_bulk_get(component
->dev
, ARRAY_SIZE(clocks
), clocks
);
868 case SND_SOC_BIAS_ON
:
869 ret
= clk_bulk_prepare_enable(ARRAY_SIZE(clocks
), clocks
);
871 dev_err(component
->dev
, "Failed to enable clocks\n");
875 case SND_SOC_BIAS_PREPARE
:
877 case SND_SOC_BIAS_STANDBY
:
878 /* Initial cold start */
879 if (snd_soc_component_get_bias_level(component
) == SND_SOC_BIAS_OFF
)
882 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks
), clocks
);
884 case SND_SOC_BIAS_OFF
:
890 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
891 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
892 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
893 | SNDRV_PCM_FMTBIT_S32_LE)
895 static const struct snd_soc_dai_ops aic32x4_ops
= {
896 .hw_params
= aic32x4_hw_params
,
897 .mute_stream
= aic32x4_mute
,
898 .set_fmt
= aic32x4_set_dai_fmt
,
899 .set_sysclk
= aic32x4_set_dai_sysclk
,
900 .no_capture_mute
= 1,
903 static struct snd_soc_dai_driver aic32x4_dai
= {
904 .name
= "tlv320aic32x4-hifi",
906 .stream_name
= "Playback",
909 .rates
= AIC32X4_RATES
,
910 .formats
= AIC32X4_FORMATS
,},
912 .stream_name
= "Capture",
915 .rates
= AIC32X4_RATES
,
916 .formats
= AIC32X4_FORMATS
,},
918 .symmetric_rates
= 1,
921 static void aic32x4_setup_gpios(struct snd_soc_component
*component
)
923 struct aic32x4_priv
*aic32x4
= snd_soc_component_get_drvdata(component
);
925 /* setup GPIO functions */
927 if (aic32x4
->setup
->gpio_func
[0] != AIC32X4_MFPX_DEFAULT_VALUE
) {
928 snd_soc_component_write(component
, AIC32X4_DINCTL
,
929 aic32x4
->setup
->gpio_func
[0]);
930 snd_soc_add_component_controls(component
, aic32x4_mfp1
,
931 ARRAY_SIZE(aic32x4_mfp1
));
935 if (aic32x4
->setup
->gpio_func
[1] != AIC32X4_MFPX_DEFAULT_VALUE
) {
936 snd_soc_component_write(component
, AIC32X4_DOUTCTL
,
937 aic32x4
->setup
->gpio_func
[1]);
938 snd_soc_add_component_controls(component
, aic32x4_mfp2
,
939 ARRAY_SIZE(aic32x4_mfp2
));
943 if (aic32x4
->setup
->gpio_func
[2] != AIC32X4_MFPX_DEFAULT_VALUE
) {
944 snd_soc_component_write(component
, AIC32X4_SCLKCTL
,
945 aic32x4
->setup
->gpio_func
[2]);
946 snd_soc_add_component_controls(component
, aic32x4_mfp3
,
947 ARRAY_SIZE(aic32x4_mfp3
));
951 if (aic32x4
->setup
->gpio_func
[3] != AIC32X4_MFPX_DEFAULT_VALUE
) {
952 snd_soc_component_write(component
, AIC32X4_MISOCTL
,
953 aic32x4
->setup
->gpio_func
[3]);
954 snd_soc_add_component_controls(component
, aic32x4_mfp4
,
955 ARRAY_SIZE(aic32x4_mfp4
));
959 if (aic32x4
->setup
->gpio_func
[4] != AIC32X4_MFPX_DEFAULT_VALUE
) {
960 snd_soc_component_write(component
, AIC32X4_GPIOCTL
,
961 aic32x4
->setup
->gpio_func
[4]);
962 snd_soc_add_component_controls(component
, aic32x4_mfp5
,
963 ARRAY_SIZE(aic32x4_mfp5
));
967 static int aic32x4_component_probe(struct snd_soc_component
*component
)
969 struct aic32x4_priv
*aic32x4
= snd_soc_component_get_drvdata(component
);
973 struct clk_bulk_data clocks
[] = {
974 { .id
= "codec_clkin" },
980 ret
= devm_clk_bulk_get(component
->dev
, ARRAY_SIZE(clocks
), clocks
);
985 aic32x4_setup_gpios(component
);
987 clk_set_parent(clocks
[0].clk
, clocks
[1].clk
);
988 clk_set_parent(clocks
[2].clk
, clocks
[3].clk
);
990 /* Power platform configuration */
991 if (aic32x4
->power_cfg
& AIC32X4_PWR_MICBIAS_2075_LDOIN
) {
992 snd_soc_component_write(component
, AIC32X4_MICBIAS
,
993 AIC32X4_MICBIAS_LDOIN
| AIC32X4_MICBIAS_2075V
);
995 if (aic32x4
->power_cfg
& AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE
)
996 snd_soc_component_write(component
, AIC32X4_PWRCFG
, AIC32X4_AVDDWEAKDISABLE
);
998 tmp_reg
= (aic32x4
->power_cfg
& AIC32X4_PWR_AIC32X4_LDO_ENABLE
) ?
999 AIC32X4_LDOCTLEN
: 0;
1000 snd_soc_component_write(component
, AIC32X4_LDOCTL
, tmp_reg
);
1002 tmp_reg
= snd_soc_component_read(component
, AIC32X4_CMMODE
);
1003 if (aic32x4
->power_cfg
& AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36
)
1004 tmp_reg
|= AIC32X4_LDOIN_18_36
;
1005 if (aic32x4
->power_cfg
& AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED
)
1006 tmp_reg
|= AIC32X4_LDOIN2HP
;
1007 snd_soc_component_write(component
, AIC32X4_CMMODE
, tmp_reg
);
1009 /* Mic PGA routing */
1010 if (aic32x4
->micpga_routing
& AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K
)
1011 snd_soc_component_write(component
, AIC32X4_LMICPGANIN
,
1012 AIC32X4_LMICPGANIN_IN2R_10K
);
1014 snd_soc_component_write(component
, AIC32X4_LMICPGANIN
,
1015 AIC32X4_LMICPGANIN_CM1L_10K
);
1016 if (aic32x4
->micpga_routing
& AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K
)
1017 snd_soc_component_write(component
, AIC32X4_RMICPGANIN
,
1018 AIC32X4_RMICPGANIN_IN1L_10K
);
1020 snd_soc_component_write(component
, AIC32X4_RMICPGANIN
,
1021 AIC32X4_RMICPGANIN_CM1R_10K
);
1024 * Workaround: for an unknown reason, the ADC needs to be powered up
1025 * and down for the first capture to work properly. It seems related to
1026 * a HW BUG or some kind of behavior not documented in the datasheet.
1028 tmp_reg
= snd_soc_component_read(component
, AIC32X4_ADCSETUP
);
1029 snd_soc_component_write(component
, AIC32X4_ADCSETUP
, tmp_reg
|
1030 AIC32X4_LADC_EN
| AIC32X4_RADC_EN
);
1031 snd_soc_component_write(component
, AIC32X4_ADCSETUP
, tmp_reg
);
1036 static const struct snd_soc_component_driver soc_component_dev_aic32x4
= {
1037 .probe
= aic32x4_component_probe
,
1038 .set_bias_level
= aic32x4_set_bias_level
,
1039 .controls
= aic32x4_snd_controls
,
1040 .num_controls
= ARRAY_SIZE(aic32x4_snd_controls
),
1041 .dapm_widgets
= aic32x4_dapm_widgets
,
1042 .num_dapm_widgets
= ARRAY_SIZE(aic32x4_dapm_widgets
),
1043 .dapm_routes
= aic32x4_dapm_routes
,
1044 .num_dapm_routes
= ARRAY_SIZE(aic32x4_dapm_routes
),
1045 .suspend_bias_off
= 1,
1047 .use_pmdown_time
= 1,
1049 .non_legacy_dai_naming
= 1,
1052 static int aic32x4_parse_dt(struct aic32x4_priv
*aic32x4
,
1053 struct device_node
*np
)
1055 struct aic32x4_setup_data
*aic32x4_setup
;
1058 aic32x4_setup
= devm_kzalloc(aic32x4
->dev
, sizeof(*aic32x4_setup
),
1063 ret
= of_property_match_string(np
, "clock-names", "mclk");
1066 aic32x4
->mclk_name
= of_clk_get_parent_name(np
, ret
);
1068 aic32x4
->swapdacs
= false;
1069 aic32x4
->micpga_routing
= 0;
1070 aic32x4
->rstn_gpio
= of_get_named_gpio(np
, "reset-gpios", 0);
1072 if (of_property_read_u32_array(np
, "aic32x4-gpio-func",
1073 aic32x4_setup
->gpio_func
, 5) >= 0)
1074 aic32x4
->setup
= aic32x4_setup
;
1078 static void aic32x4_disable_regulators(struct aic32x4_priv
*aic32x4
)
1080 regulator_disable(aic32x4
->supply_iov
);
1082 if (!IS_ERR(aic32x4
->supply_ldo
))
1083 regulator_disable(aic32x4
->supply_ldo
);
1085 if (!IS_ERR(aic32x4
->supply_dv
))
1086 regulator_disable(aic32x4
->supply_dv
);
1088 if (!IS_ERR(aic32x4
->supply_av
))
1089 regulator_disable(aic32x4
->supply_av
);
1092 static int aic32x4_setup_regulators(struct device
*dev
,
1093 struct aic32x4_priv
*aic32x4
)
1097 aic32x4
->supply_ldo
= devm_regulator_get_optional(dev
, "ldoin");
1098 aic32x4
->supply_iov
= devm_regulator_get(dev
, "iov");
1099 aic32x4
->supply_dv
= devm_regulator_get_optional(dev
, "dv");
1100 aic32x4
->supply_av
= devm_regulator_get_optional(dev
, "av");
1102 /* Check if the regulator requirements are fulfilled */
1104 if (IS_ERR(aic32x4
->supply_iov
)) {
1105 dev_err(dev
, "Missing supply 'iov'\n");
1106 return PTR_ERR(aic32x4
->supply_iov
);
1109 if (IS_ERR(aic32x4
->supply_ldo
)) {
1110 if (PTR_ERR(aic32x4
->supply_ldo
) == -EPROBE_DEFER
)
1111 return -EPROBE_DEFER
;
1113 if (IS_ERR(aic32x4
->supply_dv
)) {
1114 dev_err(dev
, "Missing supply 'dv' or 'ldoin'\n");
1115 return PTR_ERR(aic32x4
->supply_dv
);
1117 if (IS_ERR(aic32x4
->supply_av
)) {
1118 dev_err(dev
, "Missing supply 'av' or 'ldoin'\n");
1119 return PTR_ERR(aic32x4
->supply_av
);
1122 if (PTR_ERR(aic32x4
->supply_dv
) == -EPROBE_DEFER
)
1123 return -EPROBE_DEFER
;
1124 if (PTR_ERR(aic32x4
->supply_av
) == -EPROBE_DEFER
)
1125 return -EPROBE_DEFER
;
1128 ret
= regulator_enable(aic32x4
->supply_iov
);
1130 dev_err(dev
, "Failed to enable regulator iov\n");
1134 if (!IS_ERR(aic32x4
->supply_ldo
)) {
1135 ret
= regulator_enable(aic32x4
->supply_ldo
);
1137 dev_err(dev
, "Failed to enable regulator ldo\n");
1142 if (!IS_ERR(aic32x4
->supply_dv
)) {
1143 ret
= regulator_enable(aic32x4
->supply_dv
);
1145 dev_err(dev
, "Failed to enable regulator dv\n");
1150 if (!IS_ERR(aic32x4
->supply_av
)) {
1151 ret
= regulator_enable(aic32x4
->supply_av
);
1153 dev_err(dev
, "Failed to enable regulator av\n");
1158 if (!IS_ERR(aic32x4
->supply_ldo
) && IS_ERR(aic32x4
->supply_av
))
1159 aic32x4
->power_cfg
|= AIC32X4_PWR_AIC32X4_LDO_ENABLE
;
1164 if (!IS_ERR(aic32x4
->supply_dv
))
1165 regulator_disable(aic32x4
->supply_dv
);
1168 if (!IS_ERR(aic32x4
->supply_ldo
))
1169 regulator_disable(aic32x4
->supply_ldo
);
1172 regulator_disable(aic32x4
->supply_iov
);
1176 int aic32x4_probe(struct device
*dev
, struct regmap
*regmap
)
1178 struct aic32x4_priv
*aic32x4
;
1179 struct aic32x4_pdata
*pdata
= dev
->platform_data
;
1180 struct device_node
*np
= dev
->of_node
;
1184 return PTR_ERR(regmap
);
1186 aic32x4
= devm_kzalloc(dev
, sizeof(struct aic32x4_priv
),
1188 if (aic32x4
== NULL
)
1192 dev_set_drvdata(dev
, aic32x4
);
1195 aic32x4
->power_cfg
= pdata
->power_cfg
;
1196 aic32x4
->swapdacs
= pdata
->swapdacs
;
1197 aic32x4
->micpga_routing
= pdata
->micpga_routing
;
1198 aic32x4
->rstn_gpio
= pdata
->rstn_gpio
;
1199 aic32x4
->mclk_name
= "mclk";
1201 ret
= aic32x4_parse_dt(aic32x4
, np
);
1203 dev_err(dev
, "Failed to parse DT node\n");
1207 aic32x4
->power_cfg
= 0;
1208 aic32x4
->swapdacs
= false;
1209 aic32x4
->micpga_routing
= 0;
1210 aic32x4
->rstn_gpio
= -1;
1211 aic32x4
->mclk_name
= "mclk";
1214 if (gpio_is_valid(aic32x4
->rstn_gpio
)) {
1215 ret
= devm_gpio_request_one(dev
, aic32x4
->rstn_gpio
,
1216 GPIOF_OUT_INIT_LOW
, "tlv320aic32x4 rstn");
1221 ret
= aic32x4_setup_regulators(dev
, aic32x4
);
1223 dev_err(dev
, "Failed to setup regulators\n");
1227 if (gpio_is_valid(aic32x4
->rstn_gpio
)) {
1229 gpio_set_value_cansleep(aic32x4
->rstn_gpio
, 1);
1233 ret
= regmap_write(regmap
, AIC32X4_RESET
, 0x01);
1235 goto err_disable_regulators
;
1237 ret
= devm_snd_soc_register_component(dev
,
1238 &soc_component_dev_aic32x4
, &aic32x4_dai
, 1);
1240 dev_err(dev
, "Failed to register component\n");
1241 goto err_disable_regulators
;
1244 ret
= aic32x4_register_clocks(dev
, aic32x4
->mclk_name
);
1246 goto err_disable_regulators
;
1250 err_disable_regulators
:
1251 aic32x4_disable_regulators(aic32x4
);
1255 EXPORT_SYMBOL(aic32x4_probe
);
1257 int aic32x4_remove(struct device
*dev
)
1259 struct aic32x4_priv
*aic32x4
= dev_get_drvdata(dev
);
1261 aic32x4_disable_regulators(aic32x4
);
1265 EXPORT_SYMBOL(aic32x4_remove
);
1267 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1268 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1269 MODULE_LICENSE("GPL");