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ASoC: multi-component - ASoC Multi-Component Support
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/soc-dapm.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 /* codec private data */
65 struct aic3x_priv {
66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
69 void *control_data;
70 unsigned int sysclk;
71 int master;
72 int gpio_reset;
73 };
74
75 /*
76 * AIC3X register cache
77 * We can't read the AIC3X register space when we are
78 * using 2 wire for device control, so we cache them instead.
79 * There is no point in caching the reset register
80 */
81 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
82 0x00, 0x00, 0x00, 0x10, /* 0 */
83 0x04, 0x00, 0x00, 0x00, /* 4 */
84 0x00, 0x00, 0x00, 0x01, /* 8 */
85 0x00, 0x00, 0x00, 0x80, /* 12 */
86 0x80, 0xff, 0xff, 0x78, /* 16 */
87 0x78, 0x78, 0x78, 0x78, /* 20 */
88 0x78, 0x00, 0x00, 0xfe, /* 24 */
89 0x00, 0x00, 0xfe, 0x00, /* 28 */
90 0x18, 0x18, 0x00, 0x00, /* 32 */
91 0x00, 0x00, 0x00, 0x00, /* 36 */
92 0x00, 0x00, 0x00, 0x80, /* 40 */
93 0x80, 0x00, 0x00, 0x00, /* 44 */
94 0x00, 0x00, 0x00, 0x04, /* 48 */
95 0x00, 0x00, 0x00, 0x00, /* 52 */
96 0x00, 0x00, 0x04, 0x00, /* 56 */
97 0x00, 0x00, 0x00, 0x00, /* 60 */
98 0x00, 0x04, 0x00, 0x00, /* 64 */
99 0x00, 0x00, 0x00, 0x00, /* 68 */
100 0x04, 0x00, 0x00, 0x00, /* 72 */
101 0x00, 0x00, 0x00, 0x00, /* 76 */
102 0x00, 0x00, 0x00, 0x00, /* 80 */
103 0x00, 0x00, 0x00, 0x00, /* 84 */
104 0x00, 0x00, 0x00, 0x00, /* 88 */
105 0x00, 0x00, 0x00, 0x00, /* 92 */
106 0x00, 0x00, 0x00, 0x00, /* 96 */
107 0x00, 0x00, 0x02, /* 100 */
108 };
109
110 /*
111 * read aic3x register cache
112 */
113 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
114 unsigned int reg)
115 {
116 u8 *cache = codec->reg_cache;
117 if (reg >= AIC3X_CACHEREGNUM)
118 return -1;
119 return cache[reg];
120 }
121
122 /*
123 * write aic3x register cache
124 */
125 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
126 u8 reg, u8 value)
127 {
128 u8 *cache = codec->reg_cache;
129 if (reg >= AIC3X_CACHEREGNUM)
130 return;
131 cache[reg] = value;
132 }
133
134 /*
135 * write to the aic3x register space
136 */
137 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
138 unsigned int value)
139 {
140 u8 data[2];
141
142 /* data is
143 * D15..D8 aic3x register offset
144 * D7...D0 register data
145 */
146 data[0] = reg & 0xff;
147 data[1] = value & 0xff;
148
149 aic3x_write_reg_cache(codec, data[0], data[1]);
150 if (codec->hw_write(codec->control_data, data, 2) == 2)
151 return 0;
152 else
153 return -EIO;
154 }
155
156 /*
157 * read from the aic3x register space
158 */
159 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
160 u8 *value)
161 {
162 *value = reg & 0xff;
163
164 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
165
166 aic3x_write_reg_cache(codec, reg, *value);
167 return 0;
168 }
169
170 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
171 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
172 .info = snd_soc_info_volsw, \
173 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
174 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
175
176 /*
177 * All input lines are connected when !0xf and disconnected with 0xf bit field,
178 * so we have to use specific dapm_put call for input mixer
179 */
180 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
181 struct snd_ctl_elem_value *ucontrol)
182 {
183 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
184 struct soc_mixer_control *mc =
185 (struct soc_mixer_control *)kcontrol->private_value;
186 unsigned int reg = mc->reg;
187 unsigned int shift = mc->shift;
188 int max = mc->max;
189 unsigned int mask = (1 << fls(max)) - 1;
190 unsigned int invert = mc->invert;
191 unsigned short val, val_mask;
192 int ret;
193 struct snd_soc_dapm_path *path;
194 int found = 0;
195
196 val = (ucontrol->value.integer.value[0] & mask);
197
198 mask = 0xf;
199 if (val)
200 val = mask;
201
202 if (invert)
203 val = mask - val;
204 val_mask = mask << shift;
205 val = val << shift;
206
207 mutex_lock(&widget->codec->mutex);
208
209 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
210 /* find dapm widget path assoc with kcontrol */
211 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
212 if (path->kcontrol != kcontrol)
213 continue;
214
215 /* found, now check type */
216 found = 1;
217 if (val)
218 /* new connection */
219 path->connect = invert ? 0 : 1;
220 else
221 /* old connection must be powered down */
222 path->connect = invert ? 1 : 0;
223 break;
224 }
225
226 if (found)
227 snd_soc_dapm_sync(widget->codec);
228 }
229
230 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
231
232 mutex_unlock(&widget->codec->mutex);
233 return ret;
234 }
235
236 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
237 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
238 static const char *aic3x_left_hpcom_mux[] =
239 { "differential of HPLOUT", "constant VCM", "single-ended" };
240 static const char *aic3x_right_hpcom_mux[] =
241 { "differential of HPROUT", "constant VCM", "single-ended",
242 "differential of HPLCOM", "external feedback" };
243 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
244 static const char *aic3x_adc_hpf[] =
245 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
246
247 #define LDAC_ENUM 0
248 #define RDAC_ENUM 1
249 #define LHPCOM_ENUM 2
250 #define RHPCOM_ENUM 3
251 #define LINE1L_ENUM 4
252 #define LINE1R_ENUM 5
253 #define LINE2L_ENUM 6
254 #define LINE2R_ENUM 7
255 #define ADC_HPF_ENUM 8
256
257 static const struct soc_enum aic3x_enum[] = {
258 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
259 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
260 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
261 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
262 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
263 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
264 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
265 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
266 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
267 };
268
269 /*
270 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
271 */
272 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
273 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
274 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
275 /*
276 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
277 * Step size is approximately 0.5 dB over most of the scale but increasing
278 * near the very low levels.
279 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
280 * but having increasing dB difference below that (and where it doesn't count
281 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
282 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
283 */
284 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
285
286 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
287 /* Output */
288 SOC_DOUBLE_R_TLV("PCM Playback Volume",
289 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
290
291 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
292 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
293 0, 118, 1, output_stage_tlv),
294 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
295 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
296 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
297 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
298 0, 118, 1, output_stage_tlv),
299 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
300 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
301 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
302 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
303 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
304 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
305 0, 118, 1, output_stage_tlv),
306 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
307 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
308 0, 118, 1, output_stage_tlv),
309
310 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
311 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
312 0, 118, 1, output_stage_tlv),
313 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
314 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
315 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
316 0, 118, 1, output_stage_tlv),
317 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
318 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
319 0, 118, 1, output_stage_tlv),
320
321 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
322 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
323 0, 118, 1, output_stage_tlv),
324 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
325 0x01, 0),
326 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
327 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
328 0, 118, 1, output_stage_tlv),
329 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
330 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
331 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
332 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
333 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
334 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
335 0, 118, 1, output_stage_tlv),
336
337 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
338 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
339 0, 118, 1, output_stage_tlv),
340 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
341 0x01, 0),
342 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
343 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
344 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
345 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
346 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
347 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
348 0, 118, 1, output_stage_tlv),
349
350 /*
351 * Note: enable Automatic input Gain Controller with care. It can
352 * adjust PGA to max value when ADC is on and will never go back.
353 */
354 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
355
356 /* Input */
357 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
358 0, 119, 0, adc_tlv),
359 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
360
361 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
362 };
363
364 /* Left DAC Mux */
365 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
366 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
367
368 /* Right DAC Mux */
369 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
370 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
371
372 /* Left HPCOM Mux */
373 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
374 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
375
376 /* Right HPCOM Mux */
377 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
378 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
379
380 /* Left DAC_L1 Mixer */
381 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
382 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
383 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
384 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
385 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
386 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
387 };
388
389 /* Right DAC_R1 Mixer */
390 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
391 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
392 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
393 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
396 };
397
398 /* Left PGA Mixer */
399 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
400 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
401 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
402 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
403 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
404 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
405 };
406
407 /* Right PGA Mixer */
408 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
409 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
410 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
411 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
412 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
413 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
414 };
415
416 /* Left Line1 Mux */
417 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
418 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
419
420 /* Right Line1 Mux */
421 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
422 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
423
424 /* Left Line2 Mux */
425 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
426 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
427
428 /* Right Line2 Mux */
429 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
430 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
431
432 /* Left PGA Bypass Mixer */
433 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
434 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
441 };
442
443 /* Right PGA Bypass Mixer */
444 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
445 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
452 };
453
454 /* Left Line2 Bypass Mixer */
455 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
456 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
461 };
462
463 /* Right Line2 Bypass Mixer */
464 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
465 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
470 };
471
472 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
473 /* Left DAC to Left Outputs */
474 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
475 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
476 &aic3x_left_dac_mux_controls),
477 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
478 &aic3x_left_dac_mixer_controls[0],
479 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
480 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
481 &aic3x_left_hpcom_mux_controls),
482 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
483 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
484 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
485
486 /* Right DAC to Right Outputs */
487 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
488 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
489 &aic3x_right_dac_mux_controls),
490 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
491 &aic3x_right_dac_mixer_controls[0],
492 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
493 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
494 &aic3x_right_hpcom_mux_controls),
495 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
496 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
497 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
498
499 /* Mono Output */
500 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
501
502 /* Inputs to Left ADC */
503 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
504 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
505 &aic3x_left_pga_mixer_controls[0],
506 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
507 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
508 &aic3x_left_line1_mux_controls),
509 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
510 &aic3x_left_line1_mux_controls),
511 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
512 &aic3x_left_line2_mux_controls),
513
514 /* Inputs to Right ADC */
515 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
516 LINE1R_2_RADC_CTRL, 2, 0),
517 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
518 &aic3x_right_pga_mixer_controls[0],
519 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
520 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
521 &aic3x_right_line1_mux_controls),
522 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
523 &aic3x_right_line1_mux_controls),
524 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
525 &aic3x_right_line2_mux_controls),
526
527 /*
528 * Not a real mic bias widget but similar function. This is for dynamic
529 * control of GPIO1 digital mic modulator clock output function when
530 * using digital mic.
531 */
532 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
533 AIC3X_GPIO1_REG, 4, 0xf,
534 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
535 AIC3X_GPIO1_FUNC_DISABLED),
536
537 /*
538 * Also similar function like mic bias. Selects digital mic with
539 * configurable oversampling rate instead of ADC converter.
540 */
541 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
542 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
543 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
544 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
545 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
546 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
547
548 /* Mic Bias */
549 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
550 MICBIAS_CTRL, 6, 3, 1, 0),
551 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
552 MICBIAS_CTRL, 6, 3, 2, 0),
553 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
554 MICBIAS_CTRL, 6, 3, 3, 0),
555
556 /* Left PGA to Left Output bypass */
557 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
558 &aic3x_left_pga_bp_mixer_controls[0],
559 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
560
561 /* Right PGA to Right Output bypass */
562 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
563 &aic3x_right_pga_bp_mixer_controls[0],
564 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
565
566 /* Left Line2 to Left Output bypass */
567 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
568 &aic3x_left_line2_bp_mixer_controls[0],
569 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
570
571 /* Right Line2 to Right Output bypass */
572 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
573 &aic3x_right_line2_bp_mixer_controls[0],
574 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
575
576 SND_SOC_DAPM_OUTPUT("LLOUT"),
577 SND_SOC_DAPM_OUTPUT("RLOUT"),
578 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
579 SND_SOC_DAPM_OUTPUT("HPLOUT"),
580 SND_SOC_DAPM_OUTPUT("HPROUT"),
581 SND_SOC_DAPM_OUTPUT("HPLCOM"),
582 SND_SOC_DAPM_OUTPUT("HPRCOM"),
583
584 SND_SOC_DAPM_INPUT("MIC3L"),
585 SND_SOC_DAPM_INPUT("MIC3R"),
586 SND_SOC_DAPM_INPUT("LINE1L"),
587 SND_SOC_DAPM_INPUT("LINE1R"),
588 SND_SOC_DAPM_INPUT("LINE2L"),
589 SND_SOC_DAPM_INPUT("LINE2R"),
590 };
591
592 static const struct snd_soc_dapm_route intercon[] = {
593 /* Left Output */
594 {"Left DAC Mux", "DAC_L1", "Left DAC"},
595 {"Left DAC Mux", "DAC_L2", "Left DAC"},
596 {"Left DAC Mux", "DAC_L3", "Left DAC"},
597
598 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
599 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
600 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
601 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
602 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
603 {"Left Line Out", NULL, "Left DAC Mux"},
604 {"Left HP Out", NULL, "Left DAC Mux"},
605
606 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
607 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
608 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
609
610 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
611 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
612 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
613 {"Left HP Com", NULL, "Left HPCOM Mux"},
614
615 {"LLOUT", NULL, "Left Line Out"},
616 {"LLOUT", NULL, "Left Line Out"},
617 {"HPLOUT", NULL, "Left HP Out"},
618 {"HPLCOM", NULL, "Left HP Com"},
619
620 /* Right Output */
621 {"Right DAC Mux", "DAC_R1", "Right DAC"},
622 {"Right DAC Mux", "DAC_R2", "Right DAC"},
623 {"Right DAC Mux", "DAC_R3", "Right DAC"},
624
625 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
626 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
627 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
628 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
629 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
630 {"Right Line Out", NULL, "Right DAC Mux"},
631 {"Right HP Out", NULL, "Right DAC Mux"},
632
633 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
634 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
635 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
636 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
637 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
638
639 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
640 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
641 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
642 {"Right HP Com", NULL, "Right HPCOM Mux"},
643
644 {"RLOUT", NULL, "Right Line Out"},
645 {"RLOUT", NULL, "Right Line Out"},
646 {"HPROUT", NULL, "Right HP Out"},
647 {"HPRCOM", NULL, "Right HP Com"},
648
649 /* Mono Output */
650 {"MONO_LOUT", NULL, "Mono Out"},
651 {"MONO_LOUT", NULL, "Mono Out"},
652
653 /* Left Input */
654 {"Left Line1L Mux", "single-ended", "LINE1L"},
655 {"Left Line1L Mux", "differential", "LINE1L"},
656
657 {"Left Line2L Mux", "single-ended", "LINE2L"},
658 {"Left Line2L Mux", "differential", "LINE2L"},
659
660 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
661 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
662 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
663 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
664 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
665
666 {"Left ADC", NULL, "Left PGA Mixer"},
667 {"Left ADC", NULL, "GPIO1 dmic modclk"},
668
669 /* Right Input */
670 {"Right Line1R Mux", "single-ended", "LINE1R"},
671 {"Right Line1R Mux", "differential", "LINE1R"},
672
673 {"Right Line2R Mux", "single-ended", "LINE2R"},
674 {"Right Line2R Mux", "differential", "LINE2R"},
675
676 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
677 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
678 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
679 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
680 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
681
682 {"Right ADC", NULL, "Right PGA Mixer"},
683 {"Right ADC", NULL, "GPIO1 dmic modclk"},
684
685 /* Left PGA Bypass */
686 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
687 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
688 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
689 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
690 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
691 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
692 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
693
694 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
695 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
696 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
697
698 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
699 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
700 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
701
702 /* Right PGA Bypass */
703 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
704 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
705 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
706 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
707 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
708 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
709 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
710
711 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
712 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
713 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
714 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
715 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
716
717 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
718 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
719 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
720
721 /* Left Line2 Bypass */
722 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
723 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
724 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
725 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
726 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
727
728 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
729 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
730 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
731
732 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
733 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
734 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
735
736 /* Right Line2 Bypass */
737 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
738 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
739 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
740 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
741 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
742
743 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
744 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
745 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
746 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
747 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
748
749 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
750 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
751 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
752
753 /*
754 * Logical path between digital mic enable and GPIO1 modulator clock
755 * output function
756 */
757 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
758 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
759 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
760 };
761
762 static int aic3x_add_widgets(struct snd_soc_codec *codec)
763 {
764 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
765 ARRAY_SIZE(aic3x_dapm_widgets));
766
767 /* set up audio path interconnects */
768 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
769
770 return 0;
771 }
772
773 static int aic3x_hw_params(struct snd_pcm_substream *substream,
774 struct snd_pcm_hw_params *params,
775 struct snd_soc_dai *dai)
776 {
777 struct snd_soc_pcm_runtime *rtd = substream->private_data;
778 struct snd_soc_codec *codec =rtd->codec;
779 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
780 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
781 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
782 u16 d, pll_d = 1;
783 u8 reg;
784 int clk;
785
786 /* select data word length */
787 data =
788 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
789 switch (params_format(params)) {
790 case SNDRV_PCM_FORMAT_S16_LE:
791 break;
792 case SNDRV_PCM_FORMAT_S20_3LE:
793 data |= (0x01 << 4);
794 break;
795 case SNDRV_PCM_FORMAT_S24_LE:
796 data |= (0x02 << 4);
797 break;
798 case SNDRV_PCM_FORMAT_S32_LE:
799 data |= (0x03 << 4);
800 break;
801 }
802 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
803
804 /* Fsref can be 44100 or 48000 */
805 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
806
807 /* Try to find a value for Q which allows us to bypass the PLL and
808 * generate CODEC_CLK directly. */
809 for (pll_q = 2; pll_q < 18; pll_q++)
810 if (aic3x->sysclk / (128 * pll_q) == fsref) {
811 bypass_pll = 1;
812 break;
813 }
814
815 if (bypass_pll) {
816 pll_q &= 0xf;
817 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
818 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
819 /* disable PLL if it is bypassed */
820 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
821 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
822
823 } else {
824 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
825 /* enable PLL when it is used */
826 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
827 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
828 }
829
830 /* Route Left DAC to left channel input and
831 * right DAC to right channel input */
832 data = (LDAC2LCH | RDAC2RCH);
833 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
834 if (params_rate(params) >= 64000)
835 data |= DUAL_RATE_MODE;
836 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
837
838 /* codec sample rate select */
839 data = (fsref * 20) / params_rate(params);
840 if (params_rate(params) < 64000)
841 data /= 2;
842 data /= 5;
843 data -= 2;
844 data |= (data << 4);
845 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
846
847 if (bypass_pll)
848 return 0;
849
850 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
851 * one wins the game. Try with d==0 first, next with d!=0.
852 * Constraints for j are according to the datasheet.
853 * The sysclk is divided by 1000 to prevent integer overflows.
854 */
855
856 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
857
858 for (r = 1; r <= 16; r++)
859 for (p = 1; p <= 8; p++) {
860 for (j = 4; j <= 55; j++) {
861 /* This is actually 1000*((j+(d/10000))*r)/p
862 * The term had to be converted to get
863 * rid of the division by 10000; d = 0 here
864 */
865 int tmp_clk = (1000 * j * r) / p;
866
867 /* Check whether this values get closer than
868 * the best ones we had before
869 */
870 if (abs(codec_clk - tmp_clk) <
871 abs(codec_clk - last_clk)) {
872 pll_j = j; pll_d = 0;
873 pll_r = r; pll_p = p;
874 last_clk = tmp_clk;
875 }
876
877 /* Early exit for exact matches */
878 if (tmp_clk == codec_clk)
879 goto found;
880 }
881 }
882
883 /* try with d != 0 */
884 for (p = 1; p <= 8; p++) {
885 j = codec_clk * p / 1000;
886
887 if (j < 4 || j > 11)
888 continue;
889
890 /* do not use codec_clk here since we'd loose precision */
891 d = ((2048 * p * fsref) - j * aic3x->sysclk)
892 * 100 / (aic3x->sysclk/100);
893
894 clk = (10000 * j + d) / (10 * p);
895
896 /* check whether this values get closer than the best
897 * ones we had before */
898 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
899 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
900 last_clk = clk;
901 }
902
903 /* Early exit for exact matches */
904 if (clk == codec_clk)
905 goto found;
906 }
907
908 if (last_clk == 0) {
909 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
910 return -EINVAL;
911 }
912
913 found:
914 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
915 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
916 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
917 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
918 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
919 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
920 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
921
922 return 0;
923 }
924
925 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
926 {
927 struct snd_soc_codec *codec = dai->codec;
928 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
929 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
930
931 if (mute) {
932 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
933 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
934 } else {
935 aic3x_write(codec, LDAC_VOL, ldac_reg);
936 aic3x_write(codec, RDAC_VOL, rdac_reg);
937 }
938
939 return 0;
940 }
941
942 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
943 int clk_id, unsigned int freq, int dir)
944 {
945 struct snd_soc_codec *codec = codec_dai->codec;
946 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
947
948 aic3x->sysclk = freq;
949 return 0;
950 }
951
952 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
953 unsigned int fmt)
954 {
955 struct snd_soc_codec *codec = codec_dai->codec;
956 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
957 u8 iface_areg, iface_breg;
958 int delay = 0;
959
960 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
961 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
962
963 /* set master/slave audio interface */
964 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
965 case SND_SOC_DAIFMT_CBM_CFM:
966 aic3x->master = 1;
967 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
968 break;
969 case SND_SOC_DAIFMT_CBS_CFS:
970 aic3x->master = 0;
971 break;
972 default:
973 return -EINVAL;
974 }
975
976 /*
977 * match both interface format and signal polarities since they
978 * are fixed
979 */
980 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
981 SND_SOC_DAIFMT_INV_MASK)) {
982 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
983 break;
984 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
985 delay = 1;
986 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
987 iface_breg |= (0x01 << 6);
988 break;
989 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
990 iface_breg |= (0x02 << 6);
991 break;
992 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
993 iface_breg |= (0x03 << 6);
994 break;
995 default:
996 return -EINVAL;
997 }
998
999 /* set iface */
1000 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1001 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1002 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1003
1004 return 0;
1005 }
1006
1007 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1008 enum snd_soc_bias_level level)
1009 {
1010 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1011 u8 reg;
1012
1013 switch (level) {
1014 case SND_SOC_BIAS_ON:
1015 break;
1016 case SND_SOC_BIAS_PREPARE:
1017 if (aic3x->master) {
1018 /* enable pll */
1019 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1020 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1021 reg | PLL_ENABLE);
1022 }
1023 break;
1024 case SND_SOC_BIAS_STANDBY:
1025 /* fall through and disable pll */
1026 case SND_SOC_BIAS_OFF:
1027 if (aic3x->master) {
1028 /* disable pll */
1029 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1030 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1031 reg & ~PLL_ENABLE);
1032 }
1033 break;
1034 }
1035 codec->bias_level = level;
1036
1037 return 0;
1038 }
1039
1040 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1041 {
1042 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1043 u8 bit = gpio ? 3: 0;
1044 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1045 aic3x_write(codec, reg, val | (!!state << bit));
1046 }
1047 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1048
1049 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1050 {
1051 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1052 u8 val, bit = gpio ? 2: 1;
1053
1054 aic3x_read(codec, reg, &val);
1055 return (val >> bit) & 1;
1056 }
1057 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1058
1059 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1060 int headset_debounce, int button_debounce)
1061 {
1062 u8 val;
1063
1064 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1065 << AIC3X_HEADSET_DETECT_SHIFT) |
1066 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1067 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1068 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1069 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1070
1071 if (detect & AIC3X_HEADSET_DETECT_MASK)
1072 val |= AIC3X_HEADSET_DETECT_ENABLED;
1073
1074 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1075 }
1076 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1077
1078 int aic3x_headset_detected(struct snd_soc_codec *codec)
1079 {
1080 u8 val;
1081 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1082 return (val >> 4) & 1;
1083 }
1084 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1085
1086 int aic3x_button_pressed(struct snd_soc_codec *codec)
1087 {
1088 u8 val;
1089 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1090 return (val >> 5) & 1;
1091 }
1092 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1093
1094 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1095 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1096 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1097
1098 static struct snd_soc_dai_ops aic3x_dai_ops = {
1099 .hw_params = aic3x_hw_params,
1100 .digital_mute = aic3x_mute,
1101 .set_sysclk = aic3x_set_dai_sysclk,
1102 .set_fmt = aic3x_set_dai_fmt,
1103 };
1104
1105 static struct snd_soc_dai_driver aic3x_dai = {
1106 .name = "tlv320aic3x-hifi",
1107 .playback = {
1108 .stream_name = "Playback",
1109 .channels_min = 1,
1110 .channels_max = 2,
1111 .rates = AIC3X_RATES,
1112 .formats = AIC3X_FORMATS,},
1113 .capture = {
1114 .stream_name = "Capture",
1115 .channels_min = 1,
1116 .channels_max = 2,
1117 .rates = AIC3X_RATES,
1118 .formats = AIC3X_FORMATS,},
1119 .ops = &aic3x_dai_ops,
1120 };
1121
1122 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1123 {
1124 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1125
1126 return 0;
1127 }
1128
1129 static int aic3x_resume(struct snd_soc_codec *codec)
1130 {
1131 int i;
1132 u8 data[2];
1133 u8 *cache = codec->reg_cache;
1134
1135 /* Sync reg_cache with the hardware */
1136 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1137 data[0] = i;
1138 data[1] = cache[i];
1139 codec->hw_write(codec->control_data, data, 2);
1140 }
1141
1142 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1143
1144 return 0;
1145 }
1146
1147 /*
1148 * initialise the AIC3X driver
1149 * register the mixer and dsp interfaces with the kernel
1150 */
1151 static int aic3x_init(struct snd_soc_codec *codec)
1152 {
1153 int reg;
1154
1155 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1156 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1157
1158 /* DAC default volume and mute */
1159 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1160 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1161
1162 /* DAC to HP default volume and route to Output mixer */
1163 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1164 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1165 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1166 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1167 /* DAC to Line Out default volume and route to Output mixer */
1168 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1169 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1170 /* DAC to Mono Line Out default volume and route to Output mixer */
1171 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1172 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1173
1174 /* unmute all outputs */
1175 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1176 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1177 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1178 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1179 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1180 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1181 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1182 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1183 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1184 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1185 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1186 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1187 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1188 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1189
1190 /* ADC default volume and unmute */
1191 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1192 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1193 /* By default route Line1 to ADC PGA mixer */
1194 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1195 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1196
1197 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1198 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1199 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1200 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1201 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1202 /* PGA to Line Out default volume, disconnect from Output Mixer */
1203 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1204 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1205 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1206 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1207 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1208
1209 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1210 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1211 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1212 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1213 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1214 /* Line2 Line Out default volume, disconnect from Output Mixer */
1215 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1216 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1217 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1218 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1219 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1220
1221 /* off, with power on */
1222 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1223
1224 return 0;
1225 }
1226
1227 static int aic3x_probe(struct snd_soc_codec *codec)
1228 {
1229 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1230
1231 codec->hw_write = (hw_write_t) i2c_master_send;
1232 codec->control_data = aic3x->control_data;
1233
1234 if (aic3x->setup) {
1235 /* setup GPIO functions */
1236 aic3x_write(codec, AIC3X_GPIO1_REG,
1237 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1238 aic3x_write(codec, AIC3X_GPIO2_REG,
1239 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1240 }
1241
1242 aic3x_init(codec);
1243
1244 snd_soc_add_controls(codec, aic3x_snd_controls,
1245 ARRAY_SIZE(aic3x_snd_controls));
1246
1247 aic3x_add_widgets(codec);
1248
1249 return 0;
1250 }
1251
1252 static int aic3x_remove(struct snd_soc_codec *codec)
1253 {
1254 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1255 return 0;
1256 }
1257
1258 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1259 .read = aic3x_read_reg_cache,
1260 .write = aic3x_write,
1261 .set_bias_level = aic3x_set_bias_level,
1262 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1263 .reg_word_size = sizeof(u8),
1264 .reg_cache_default = aic3x_reg,
1265 .probe = aic3x_probe,
1266 .remove = aic3x_remove,
1267 .suspend = aic3x_suspend,
1268 .resume = aic3x_resume,
1269 };
1270
1271 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1272 /*
1273 * AIC3X 2 wire address can be up to 4 devices with device addresses
1274 * 0x18, 0x19, 0x1A, 0x1B
1275 */
1276
1277 /*
1278 * If the i2c layer weren't so broken, we could pass this kind of data
1279 * around
1280 */
1281 static int aic3x_i2c_probe(struct i2c_client *i2c,
1282 const struct i2c_device_id *id)
1283 {
1284 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1285 struct aic3x_setup_data *setup = pdata->setup;
1286 struct aic3x_priv *aic3x;
1287 int ret, i;
1288
1289 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1290 if (aic3x == NULL) {
1291 dev_err(&i2c->dev, "failed to create private data\n");
1292 return -ENOMEM;
1293 }
1294
1295 aic3x->control_data = i2c;
1296 aic3x->setup = setup;
1297 i2c_set_clientdata(i2c, aic3x);
1298
1299 aic3x->gpio_reset = -1;
1300 if (pdata && pdata->gpio_reset >= 0) {
1301 ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
1302 if (ret != 0)
1303 goto err_gpio;
1304 aic3x->gpio_reset = pdata->gpio_reset;
1305 gpio_direction_output(aic3x->gpio_reset, 0);
1306 }
1307
1308 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1309 aic3x->supplies[i].supply = aic3x_supply_names[i];
1310
1311 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1312 aic3x->supplies);
1313 if (ret != 0) {
1314 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1315 goto err_get;
1316 }
1317
1318 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1319 aic3x->supplies);
1320 if (ret != 0) {
1321 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1322 goto err_enable;
1323 }
1324
1325 if (aic3x->gpio_reset >= 0) {
1326 udelay(1);
1327 gpio_set_value(aic3x->gpio_reset, 1);
1328 }
1329
1330 ret = snd_soc_register_codec(&i2c->dev,
1331 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1332 if (ret < 0)
1333 goto err_enable;
1334 return ret;
1335
1336 err_enable:
1337 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1338 err_get:
1339 if (aic3x->gpio_reset >= 0)
1340 gpio_free(aic3x->gpio_reset);
1341 err_gpio:
1342 kfree(aic3x);
1343 return ret;
1344 }
1345
1346 static int aic3x_i2c_remove(struct i2c_client *client)
1347 {
1348 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1349
1350 if (aic3x->gpio_reset >= 0) {
1351 gpio_set_value(aic3x->gpio_reset, 0);
1352 gpio_free(aic3x->gpio_reset);
1353 }
1354 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1355 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1356
1357 snd_soc_unregister_codec(&client->dev);
1358 kfree(i2c_get_clientdata(client));
1359 return 0;
1360 }
1361
1362 static const struct i2c_device_id aic3x_i2c_id[] = {
1363 { "tlv320aic3x", 0 },
1364 { "tlv320aic33", 0 },
1365 { }
1366 };
1367 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1368
1369 /* machine i2c codec control layer */
1370 static struct i2c_driver aic3x_i2c_driver = {
1371 .driver = {
1372 .name = "tlv320aic3x-codec",
1373 .owner = THIS_MODULE,
1374 },
1375 .probe = aic3x_i2c_probe,
1376 .remove = aic3x_i2c_remove,
1377 .id_table = aic3x_i2c_id,
1378 };
1379
1380 static inline void aic3x_i2c_init(void)
1381 {
1382 int ret;
1383
1384 ret = i2c_add_driver(&aic3x_i2c_driver);
1385 if (ret)
1386 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1387 __func__, ret);
1388 }
1389
1390 static inline void aic3x_i2c_exit(void)
1391 {
1392 i2c_del_driver(&aic3x_i2c_driver);
1393 }
1394 #endif
1395
1396 static int __init aic3x_modinit(void)
1397 {
1398 int ret = 0;
1399 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1400 ret = i2c_add_driver(&aic3x_i2c_driver);
1401 if (ret != 0) {
1402 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1403 ret);
1404 }
1405 #endif
1406 return ret;
1407 }
1408 module_init(aic3x_modinit);
1409
1410 static void __exit aic3x_exit(void)
1411 {
1412 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1413 i2c_del_driver(&aic3x_i2c_driver);
1414 #endif
1415 }
1416 module_exit(aic3x_exit);
1417
1418 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1419 MODULE_AUTHOR("Vladimir Barinov");
1420 MODULE_LICENSE("GPL");
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