2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
46 * The internal FIFO is 24576 bytes long
47 * It can be configured to hold 16bit or 24bit samples
48 * In 16bit configuration the FIFO can hold 6144 stereo samples
49 * In 24bit configuration the FIFO can hold 4096 stereo samples
51 #define DAC33_FIFO_SIZE_16BIT 6144
52 #define DAC33_FIFO_SIZE_24BIT 4096
53 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
55 #define BURST_BASEFREQ_HZ 49152000
57 #define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
60 #define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
66 static void dac33_calculate_times(struct snd_pcm_substream
*substream
);
67 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
);
76 enum dac33_fifo_modes
{
77 DAC33_FIFO_BYPASS
= 0,
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
90 struct tlv320dac33_priv
{
92 struct workqueue_struct
*dac33_wq
;
93 struct work_struct work
;
94 struct snd_soc_codec
*codec
;
95 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
96 struct snd_pcm_substream
*substream
;
102 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
103 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
104 unsigned int fifo_size
; /* Size of the FIFO in samples */
105 unsigned int nsample
; /* burst read amount from host */
106 int mode1_latency
; /* latency caused by the i2c writes in
108 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
109 unsigned int burst_rate
; /* Interface speed in Burst modes */
111 int keep_bclk
; /* Keep the BCLK continuously running
114 unsigned long long t_stamp1
; /* Time stamp for FIFO modes to */
115 unsigned long long t_stamp2
; /* calculate the FIFO caused delay */
117 unsigned int mode1_us_burst
; /* Time to burst read n number of
119 unsigned int mode7_us_to_lthr
; /* Time to reach lthr from uthr */
123 enum dac33_state state
;
124 enum snd_soc_control_type control_type
;
128 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
143 0x00, 0x00, /* 0x38 - 0x39 */
144 /* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
149 0x00, 0x80, /* 0x44 - 0x45 */
150 /* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
153 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
154 /* Registers 0x4b - 0x7c are reserved */
156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
173 /* Register read and write */
174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
177 u8
*cache
= codec
->reg_cache
;
178 if (reg
>= DAC33_CACHEREGNUM
)
184 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
187 u8
*cache
= codec
->reg_cache
;
188 if (reg
>= DAC33_CACHEREGNUM
)
194 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
197 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
202 /* If powered off, return the cached value */
203 if (dac33
->chip_power
) {
204 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
206 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
207 value
[0] = dac33_read_reg_cache(codec
, reg
);
211 dac33_write_reg_cache(codec
, reg
, val
);
214 value
[0] = dac33_read_reg_cache(codec
, reg
);
220 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
223 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
232 data
[0] = reg
& 0xff;
233 data
[1] = value
& 0xff;
235 dac33_write_reg_cache(codec
, data
[0], data
[1]);
236 if (dac33
->chip_power
) {
237 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
239 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
247 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
250 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
253 mutex_lock(&dac33
->mutex
);
254 ret
= dac33_write(codec
, reg
, value
);
255 mutex_unlock(&dac33
->mutex
);
260 #define DAC33_I2C_ADDR_AUTOINC 0x80
261 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
264 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
274 data
[0] = reg
& 0xff;
275 data
[1] = (value
>> 8) & 0xff;
276 data
[2] = value
& 0xff;
278 dac33_write_reg_cache(codec
, data
[0], data
[1]);
279 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
281 if (dac33
->chip_power
) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
284 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
286 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
294 static void dac33_init_chip(struct snd_soc_codec
*codec
)
296 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
298 if (unlikely(!dac33
->chip_power
))
301 /* 44-46: DAC Control Registers */
302 /* A : DAC sample rate Fsref/1.5 */
303 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(0));
304 /* B : DAC src=normal, not muted */
305 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
308 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
310 /* 73 : volume soft stepping control,
311 clock source = internal osc (?) */
312 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
314 /* Restore only selected registers (gains mostly) */
315 dac33_write(codec
, DAC33_LDAC_DIG_VOL_CTRL
,
316 dac33_read_reg_cache(codec
, DAC33_LDAC_DIG_VOL_CTRL
));
317 dac33_write(codec
, DAC33_RDAC_DIG_VOL_CTRL
,
318 dac33_read_reg_cache(codec
, DAC33_RDAC_DIG_VOL_CTRL
));
320 dac33_write(codec
, DAC33_LINEL_TO_LLO_VOL
,
321 dac33_read_reg_cache(codec
, DAC33_LINEL_TO_LLO_VOL
));
322 dac33_write(codec
, DAC33_LINER_TO_RLO_VOL
,
323 dac33_read_reg_cache(codec
, DAC33_LINER_TO_RLO_VOL
));
326 static inline int dac33_read_id(struct snd_soc_codec
*codec
)
331 for (i
= 0; i
< 3; i
++) {
332 ret
= dac33_read(codec
, DAC33_DEVICE_ID_MSB
+ i
, ®
);
340 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
344 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
346 reg
|= DAC33_PDNALLB
;
348 reg
&= ~(DAC33_PDNALLB
| DAC33_OSCPDNB
|
349 DAC33_DACRPDNB
| DAC33_DACLPDNB
);
350 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
353 static inline void dac33_disable_digital(struct snd_soc_codec
*codec
)
357 /* Stop the DAI clock */
358 reg
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
359 reg
&= ~DAC33_BCLKON
;
360 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, reg
);
362 /* Power down the Oscillator, and DACs */
363 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
364 reg
&= ~(DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
);
365 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
368 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
370 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
373 mutex_lock(&dac33
->mutex
);
376 if (unlikely(power
== dac33
->chip_power
)) {
377 dev_dbg(codec
->dev
, "Trying to set the same power state: %s\n",
378 power
? "ON" : "OFF");
383 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
387 "Failed to enable supplies: %d\n", ret
);
391 if (dac33
->power_gpio
>= 0)
392 gpio_set_value(dac33
->power_gpio
, 1);
394 dac33
->chip_power
= 1;
396 dac33_soft_power(codec
, 0);
397 if (dac33
->power_gpio
>= 0)
398 gpio_set_value(dac33
->power_gpio
, 0);
400 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
404 "Failed to disable supplies: %d\n", ret
);
408 dac33
->chip_power
= 0;
412 mutex_unlock(&dac33
->mutex
);
416 static int dac33_playback_event(struct snd_soc_dapm_widget
*w
,
417 struct snd_kcontrol
*kcontrol
, int event
)
419 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(w
->codec
);
422 case SND_SOC_DAPM_PRE_PMU
:
423 if (likely(dac33
->substream
)) {
424 dac33_calculate_times(dac33
->substream
);
425 dac33_prepare_chip(dac33
->substream
);
428 case SND_SOC_DAPM_POST_PMD
:
429 dac33_disable_digital(w
->codec
);
435 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
436 struct snd_ctl_elem_value
*ucontrol
)
438 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
439 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
441 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
446 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
447 struct snd_ctl_elem_value
*ucontrol
)
449 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
450 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
453 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
455 /* Do not allow changes while stream is running*/
459 if (ucontrol
->value
.integer
.value
[0] < 0 ||
460 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
463 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
468 /* Codec operation modes */
469 static const char *dac33_fifo_mode_texts
[] = {
470 "Bypass", "Mode 1", "Mode 7"
473 static const struct soc_enum dac33_fifo_mode_enum
=
474 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
475 dac33_fifo_mode_texts
);
477 /* L/R Line Output Gain */
478 static const char *lr_lineout_gain_texts
[] = {
479 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
480 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
483 static const struct soc_enum l_lineout_gain_enum
=
484 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL
, 0,
485 ARRAY_SIZE(lr_lineout_gain_texts
),
486 lr_lineout_gain_texts
);
488 static const struct soc_enum r_lineout_gain_enum
=
489 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL
, 0,
490 ARRAY_SIZE(lr_lineout_gain_texts
),
491 lr_lineout_gain_texts
);
494 * DACL/R digital volume control:
495 * from 0 dB to -63.5 in 0.5 dB steps
496 * Need to be inverted later on:
500 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
502 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
503 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
504 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
505 0, 0x7f, 1, dac_digivol_tlv
),
506 SOC_DOUBLE_R("DAC Digital Playback Switch",
507 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
508 SOC_DOUBLE_R("Line to Line Out Volume",
509 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
510 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum
),
511 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum
),
514 static const struct snd_kcontrol_new dac33_mode_snd_controls
[] = {
515 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
516 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
520 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
521 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
523 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
524 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
526 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
527 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
528 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
530 SND_SOC_DAPM_INPUT("LINEL"),
531 SND_SOC_DAPM_INPUT("LINER"),
533 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM
, 0, 0),
534 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM
, 0, 0),
537 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
538 &dac33_dapm_abypassl_control
),
539 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
540 &dac33_dapm_abypassr_control
),
542 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amplifier",
543 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
544 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amplifier",
545 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
547 SND_SOC_DAPM_SUPPLY("Left DAC Power",
548 DAC33_LDAC_PWR_CTRL
, 2, 0, NULL
, 0),
549 SND_SOC_DAPM_SUPPLY("Right DAC Power",
550 DAC33_RDAC_PWR_CTRL
, 2, 0, NULL
, 0),
552 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event
),
553 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event
),
556 static const struct snd_soc_dapm_route audio_map
[] = {
558 {"Analog Left Bypass", "Switch", "LINEL"},
559 {"Analog Right Bypass", "Switch", "LINER"},
561 {"Output Left Amplifier", NULL
, "DACL"},
562 {"Output Right Amplifier", NULL
, "DACR"},
564 {"Output Left Amplifier", NULL
, "Analog Left Bypass"},
565 {"Output Right Amplifier", NULL
, "Analog Right Bypass"},
567 {"Output Left Amplifier", NULL
, "Left DAC Power"},
568 {"Output Right Amplifier", NULL
, "Right DAC Power"},
571 {"LEFT_LO", NULL
, "Output Left Amplifier"},
572 {"RIGHT_LO", NULL
, "Output Right Amplifier"},
575 static int dac33_add_widgets(struct snd_soc_codec
*codec
)
577 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
579 snd_soc_dapm_new_controls(dapm
, dac33_dapm_widgets
,
580 ARRAY_SIZE(dac33_dapm_widgets
));
581 /* set up audio path interconnects */
582 snd_soc_dapm_add_routes(dapm
, audio_map
, ARRAY_SIZE(audio_map
));
587 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
588 enum snd_soc_bias_level level
)
590 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
594 case SND_SOC_BIAS_ON
:
595 if (!dac33
->substream
)
596 dac33_soft_power(codec
, 1);
598 case SND_SOC_BIAS_PREPARE
:
600 case SND_SOC_BIAS_STANDBY
:
601 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
602 /* Coming from OFF, switch on the codec */
603 ret
= dac33_hard_power(codec
, 1);
607 dac33_init_chip(codec
);
610 case SND_SOC_BIAS_OFF
:
611 /* Do not power off, when the codec is already off */
612 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
)
614 ret
= dac33_hard_power(codec
, 0);
619 codec
->dapm
.bias_level
= level
;
624 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
626 struct snd_soc_codec
*codec
= dac33
->codec
;
629 switch (dac33
->fifo_mode
) {
630 case DAC33_FIFO_MODE1
:
631 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
632 DAC33_THRREG(dac33
->nsample
));
634 /* Take the timestamps */
635 spin_lock_irq(&dac33
->lock
);
636 dac33
->t_stamp2
= ktime_to_us(ktime_get());
637 dac33
->t_stamp1
= dac33
->t_stamp2
;
638 spin_unlock_irq(&dac33
->lock
);
640 dac33_write16(codec
, DAC33_PREFILL_MSB
,
641 DAC33_THRREG(dac33
->alarm_threshold
));
642 /* Enable Alarm Threshold IRQ with a delay */
643 delay
= SAMPLES_TO_US(dac33
->burst_rate
,
644 dac33
->alarm_threshold
) + 1000;
645 usleep_range(delay
, delay
+ 500);
646 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
648 case DAC33_FIFO_MODE7
:
649 /* Take the timestamp */
650 spin_lock_irq(&dac33
->lock
);
651 dac33
->t_stamp1
= ktime_to_us(ktime_get());
652 /* Move back the timestamp with drain time */
653 dac33
->t_stamp1
-= dac33
->mode7_us_to_lthr
;
654 spin_unlock_irq(&dac33
->lock
);
656 dac33_write16(codec
, DAC33_PREFILL_MSB
,
657 DAC33_THRREG(DAC33_MODE7_MARGIN
));
659 /* Enable Upper Threshold IRQ */
660 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MUT
);
663 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
669 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
671 struct snd_soc_codec
*codec
= dac33
->codec
;
673 switch (dac33
->fifo_mode
) {
674 case DAC33_FIFO_MODE1
:
675 /* Take the timestamp */
676 spin_lock_irq(&dac33
->lock
);
677 dac33
->t_stamp2
= ktime_to_us(ktime_get());
678 spin_unlock_irq(&dac33
->lock
);
680 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
681 DAC33_THRREG(dac33
->nsample
));
683 case DAC33_FIFO_MODE7
:
684 /* At the moment we are not using interrupts in mode7 */
687 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
693 static void dac33_work(struct work_struct
*work
)
695 struct snd_soc_codec
*codec
;
696 struct tlv320dac33_priv
*dac33
;
699 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
700 codec
= dac33
->codec
;
702 mutex_lock(&dac33
->mutex
);
703 switch (dac33
->state
) {
705 dac33
->state
= DAC33_PLAYBACK
;
706 dac33_prefill_handler(dac33
);
709 dac33_playback_handler(dac33
);
714 dac33
->state
= DAC33_IDLE
;
715 /* Mask all interrupts from dac33 */
716 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
719 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
720 reg
|= DAC33_FIFOFLUSH
;
721 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
724 mutex_unlock(&dac33
->mutex
);
727 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
729 struct snd_soc_codec
*codec
= dev
;
730 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
732 spin_lock(&dac33
->lock
);
733 dac33
->t_stamp1
= ktime_to_us(ktime_get());
734 spin_unlock(&dac33
->lock
);
736 /* Do not schedule the workqueue in Mode7 */
737 if (dac33
->fifo_mode
!= DAC33_FIFO_MODE7
)
738 queue_work(dac33
->dac33_wq
, &dac33
->work
);
743 static void dac33_oscwait(struct snd_soc_codec
*codec
)
749 usleep_range(1000, 2000);
750 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
751 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
752 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
754 "internal oscillator calibration failed\n");
757 static int dac33_startup(struct snd_pcm_substream
*substream
,
758 struct snd_soc_dai
*dai
)
760 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
761 struct snd_soc_codec
*codec
= rtd
->codec
;
762 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
764 /* Stream started, save the substream pointer */
765 dac33
->substream
= substream
;
767 snd_pcm_hw_constraint_msbits(substream
->runtime
, 0, 32, 24);
772 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
773 struct snd_soc_dai
*dai
)
775 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
776 struct snd_soc_codec
*codec
= rtd
->codec
;
777 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
779 dac33
->substream
= NULL
;
782 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
783 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
784 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
785 struct snd_pcm_hw_params
*params
,
786 struct snd_soc_dai
*dai
)
788 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
789 struct snd_soc_codec
*codec
= rtd
->codec
;
790 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
792 /* Check parameters for validity */
793 switch (params_rate(params
)) {
798 dev_err(codec
->dev
, "unsupported rate %d\n",
799 params_rate(params
));
803 switch (params_format(params
)) {
804 case SNDRV_PCM_FORMAT_S16_LE
:
805 dac33
->fifo_size
= DAC33_FIFO_SIZE_16BIT
;
806 dac33
->burst_rate
= CALC_BURST_RATE(dac33
->burst_bclkdiv
, 32);
808 case SNDRV_PCM_FORMAT_S32_LE
:
809 dac33
->fifo_size
= DAC33_FIFO_SIZE_24BIT
;
810 dac33
->burst_rate
= CALC_BURST_RATE(dac33
->burst_bclkdiv
, 64);
813 dev_err(codec
->dev
, "unsupported format %d\n",
814 params_format(params
));
821 #define CALC_OSCSET(rate, refclk) ( \
822 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
823 #define CALC_RATIOSET(rate, refclk) ( \
824 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
827 * tlv320dac33 is strict on the sequence of the register writes, if the register
828 * writes happens in different order, than dac33 might end up in unknown state.
829 * Use the known, working sequence of register writes to initialize the dac33.
831 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
833 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
834 struct snd_soc_codec
*codec
= rtd
->codec
;
835 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
836 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
837 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
839 switch (substream
->runtime
->rate
) {
842 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
843 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
847 dev_err(codec
->dev
, "unsupported rate %d\n",
848 substream
->runtime
->rate
);
853 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
854 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
855 /* Read FIFO control A, and clear FIFO flush bit */
856 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
857 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
859 fifoctrl_a
&= ~DAC33_WIDTH
;
860 switch (substream
->runtime
->format
) {
861 case SNDRV_PCM_FORMAT_S16_LE
:
862 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
863 fifoctrl_a
|= DAC33_WIDTH
;
865 case SNDRV_PCM_FORMAT_S32_LE
:
866 aictrl_a
|= (DAC33_NCYCL_32
| DAC33_WLEN_24
);
869 dev_err(codec
->dev
, "unsupported format %d\n",
870 substream
->runtime
->format
);
874 mutex_lock(&dac33
->mutex
);
876 if (!dac33
->chip_power
) {
878 * Chip is not powered yet.
879 * Do the init in the dac33_set_bias_level later.
881 mutex_unlock(&dac33
->mutex
);
885 dac33_soft_power(codec
, 0);
886 dac33_soft_power(codec
, 1);
888 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
889 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
891 /* Write registers 0x08 and 0x09 (MSB, LSB) */
892 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
894 /* calib time: 128 is a nice number ;) */
895 dac33_write(codec
, DAC33_CALIB_TIME
, 128);
897 /* adjustment treshold & step */
898 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
901 /* div=4 / gain=1 / div */
902 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
904 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
905 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
906 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
908 dac33_oscwait(codec
);
910 if (dac33
->fifo_mode
) {
911 /* Generic for all FIFO modes */
912 /* 50-51 : ASRC Control registers */
913 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCLKDIV(1));
914 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
916 /* Write registers 0x34 and 0x35 (MSB, LSB) */
917 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
919 /* Set interrupts to high active */
920 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
922 /* FIFO bypass mode */
923 /* 50-51 : ASRC Control registers */
924 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
925 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
928 /* Interrupt behaviour configuration */
929 switch (dac33
->fifo_mode
) {
930 case DAC33_FIFO_MODE1
:
931 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
932 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
934 case DAC33_FIFO_MODE7
:
935 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_A
,
936 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL
));
939 /* in FIFO bypass mode, the interrupts are not used */
943 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
945 switch (dac33
->fifo_mode
) {
946 case DAC33_FIFO_MODE1
:
949 * Disable the FIFO bypass (Enable the use of FIFO)
950 * Select nSample mode
951 * BCLK is only running when data is needed by DAC33
953 fifoctrl_a
&= ~DAC33_FBYPAS
;
954 fifoctrl_a
&= ~DAC33_FAUTO
;
955 if (dac33
->keep_bclk
)
956 aictrl_b
|= DAC33_BCLKON
;
958 aictrl_b
&= ~DAC33_BCLKON
;
960 case DAC33_FIFO_MODE7
:
963 * Disable the FIFO bypass (Enable the use of FIFO)
964 * Select Threshold mode
965 * BCLK is only running when data is needed by DAC33
967 fifoctrl_a
&= ~DAC33_FBYPAS
;
968 fifoctrl_a
|= DAC33_FAUTO
;
969 if (dac33
->keep_bclk
)
970 aictrl_b
|= DAC33_BCLKON
;
972 aictrl_b
&= ~DAC33_BCLKON
;
976 * For FIFO bypass mode:
977 * Enable the FIFO bypass (Disable the FIFO use)
978 * Set the BCLK as continous
980 fifoctrl_a
|= DAC33_FBYPAS
;
981 aictrl_b
|= DAC33_BCLKON
;
985 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
986 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
987 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
998 if (dac33
->fifo_mode
)
999 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
1000 dac33
->burst_bclkdiv
);
1002 if (substream
->runtime
->format
== SNDRV_PCM_FORMAT_S16_LE
)
1003 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
1005 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 16);
1007 switch (dac33
->fifo_mode
) {
1008 case DAC33_FIFO_MODE1
:
1009 dac33_write16(codec
, DAC33_ATHR_MSB
,
1010 DAC33_THRREG(dac33
->alarm_threshold
));
1012 case DAC33_FIFO_MODE7
:
1014 * Configure the threshold levels, and leave 10 sample space
1015 * at the bottom, and also at the top of the FIFO
1017 dac33_write16(codec
, DAC33_UTHR_MSB
, DAC33_THRREG(dac33
->uthr
));
1018 dac33_write16(codec
, DAC33_LTHR_MSB
,
1019 DAC33_THRREG(DAC33_MODE7_MARGIN
));
1025 mutex_unlock(&dac33
->mutex
);
1030 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
1032 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1033 struct snd_soc_codec
*codec
= rtd
->codec
;
1034 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1035 unsigned int period_size
= substream
->runtime
->period_size
;
1036 unsigned int rate
= substream
->runtime
->rate
;
1037 unsigned int nsample_limit
;
1039 /* In bypass mode we don't need to calculate */
1040 if (!dac33
->fifo_mode
)
1043 switch (dac33
->fifo_mode
) {
1044 case DAC33_FIFO_MODE1
:
1045 /* Number of samples under i2c latency */
1046 dac33
->alarm_threshold
= US_TO_SAMPLES(rate
,
1047 dac33
->mode1_latency
);
1048 nsample_limit
= dac33
->fifo_size
- dac33
->alarm_threshold
;
1050 if (period_size
<= dac33
->alarm_threshold
)
1052 * Configure nSamaple to number of periods,
1053 * which covers the latency requironment.
1055 dac33
->nsample
= period_size
*
1056 ((dac33
->alarm_threshold
/ period_size
) +
1057 (dac33
->alarm_threshold
% period_size
?
1059 else if (period_size
> nsample_limit
)
1060 dac33
->nsample
= nsample_limit
;
1062 dac33
->nsample
= period_size
;
1064 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
1066 dac33
->t_stamp1
= 0;
1067 dac33
->t_stamp2
= 0;
1069 case DAC33_FIFO_MODE7
:
1070 dac33
->uthr
= UTHR_FROM_PERIOD_SIZE(period_size
, rate
,
1071 dac33
->burst_rate
) + 9;
1072 if (dac33
->uthr
> (dac33
->fifo_size
- DAC33_MODE7_MARGIN
))
1073 dac33
->uthr
= dac33
->fifo_size
- DAC33_MODE7_MARGIN
;
1074 if (dac33
->uthr
< (DAC33_MODE7_MARGIN
+ 10))
1075 dac33
->uthr
= (DAC33_MODE7_MARGIN
+ 10);
1077 dac33
->mode7_us_to_lthr
=
1078 SAMPLES_TO_US(substream
->runtime
->rate
,
1079 dac33
->uthr
- DAC33_MODE7_MARGIN
+ 1);
1080 dac33
->t_stamp1
= 0;
1088 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1089 struct snd_soc_dai
*dai
)
1091 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1092 struct snd_soc_codec
*codec
= rtd
->codec
;
1093 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1097 case SNDRV_PCM_TRIGGER_START
:
1098 case SNDRV_PCM_TRIGGER_RESUME
:
1099 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1100 if (dac33
->fifo_mode
) {
1101 dac33
->state
= DAC33_PREFILL
;
1102 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1105 case SNDRV_PCM_TRIGGER_STOP
:
1106 case SNDRV_PCM_TRIGGER_SUSPEND
:
1107 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1108 if (dac33
->fifo_mode
) {
1109 dac33
->state
= DAC33_FLUSH
;
1110 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1120 static snd_pcm_sframes_t
dac33_dai_delay(
1121 struct snd_pcm_substream
*substream
,
1122 struct snd_soc_dai
*dai
)
1124 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1125 struct snd_soc_codec
*codec
= rtd
->codec
;
1126 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1127 unsigned long long t0
, t1
, t_now
;
1128 unsigned int time_delta
, uthr
;
1129 int samples_out
, samples_in
, samples
;
1130 snd_pcm_sframes_t delay
= 0;
1132 switch (dac33
->fifo_mode
) {
1133 case DAC33_FIFO_BYPASS
:
1135 case DAC33_FIFO_MODE1
:
1136 spin_lock(&dac33
->lock
);
1137 t0
= dac33
->t_stamp1
;
1138 t1
= dac33
->t_stamp2
;
1139 spin_unlock(&dac33
->lock
);
1140 t_now
= ktime_to_us(ktime_get());
1142 /* We have not started to fill the FIFO yet, delay is 0 */
1149 * After Alarm threshold, and before nSample write
1151 time_delta
= t_now
- t0
;
1152 samples_out
= time_delta
? US_TO_SAMPLES(
1153 substream
->runtime
->rate
,
1156 if (likely(dac33
->alarm_threshold
> samples_out
))
1157 delay
= dac33
->alarm_threshold
- samples_out
;
1160 } else if ((t_now
- t1
) <= dac33
->mode1_us_burst
) {
1163 * After nSample write (during burst operation)
1165 time_delta
= t_now
- t0
;
1166 samples_out
= time_delta
? US_TO_SAMPLES(
1167 substream
->runtime
->rate
,
1170 time_delta
= t_now
- t1
;
1171 samples_in
= time_delta
? US_TO_SAMPLES(
1175 samples
= dac33
->alarm_threshold
;
1176 samples
+= (samples_in
- samples_out
);
1178 if (likely(samples
> 0))
1185 * After burst operation, before next alarm threshold
1187 time_delta
= t_now
- t0
;
1188 samples_out
= time_delta
? US_TO_SAMPLES(
1189 substream
->runtime
->rate
,
1192 samples_in
= dac33
->nsample
;
1193 samples
= dac33
->alarm_threshold
;
1194 samples
+= (samples_in
- samples_out
);
1196 if (likely(samples
> 0))
1197 delay
= samples
> dac33
->fifo_size
?
1198 dac33
->fifo_size
: samples
;
1203 case DAC33_FIFO_MODE7
:
1204 spin_lock(&dac33
->lock
);
1205 t0
= dac33
->t_stamp1
;
1207 spin_unlock(&dac33
->lock
);
1208 t_now
= ktime_to_us(ktime_get());
1210 /* We have not started to fill the FIFO yet, delay is 0 */
1216 * Either the timestamps are messed or equal. Report
1223 time_delta
= t_now
- t0
;
1224 if (time_delta
<= dac33
->mode7_us_to_lthr
) {
1227 * After burst (draining phase)
1229 samples_out
= US_TO_SAMPLES(
1230 substream
->runtime
->rate
,
1233 if (likely(uthr
> samples_out
))
1234 delay
= uthr
- samples_out
;
1240 * During burst operation
1242 time_delta
= time_delta
- dac33
->mode7_us_to_lthr
;
1244 samples_out
= US_TO_SAMPLES(
1245 substream
->runtime
->rate
,
1247 samples_in
= US_TO_SAMPLES(
1250 delay
= DAC33_MODE7_MARGIN
+ samples_in
- samples_out
;
1252 if (unlikely(delay
> uthr
))
1257 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
1265 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1266 int clk_id
, unsigned int freq
, int dir
)
1268 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1269 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1270 u8 ioc_reg
, asrcb_reg
;
1272 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
1273 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
1275 case TLV320DAC33_MCLK
:
1276 ioc_reg
|= DAC33_REFSEL
;
1277 asrcb_reg
|= DAC33_SRCREFSEL
;
1279 case TLV320DAC33_SLEEPCLK
:
1280 ioc_reg
&= ~DAC33_REFSEL
;
1281 asrcb_reg
&= ~DAC33_SRCREFSEL
;
1284 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
1287 dac33
->refclk
= freq
;
1289 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1290 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1295 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1298 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1299 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1300 u8 aictrl_a
, aictrl_b
;
1302 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1303 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1304 /* set master/slave audio interface */
1305 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1306 case SND_SOC_DAIFMT_CBM_CFM
:
1308 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1310 case SND_SOC_DAIFMT_CBS_CFS
:
1312 if (dac33
->fifo_mode
) {
1313 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1316 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1322 aictrl_a
&= ~DAC33_AFMT_MASK
;
1323 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1324 case SND_SOC_DAIFMT_I2S
:
1325 aictrl_a
|= DAC33_AFMT_I2S
;
1327 case SND_SOC_DAIFMT_DSP_A
:
1328 aictrl_a
|= DAC33_AFMT_DSP
;
1329 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1330 aictrl_b
|= DAC33_DATA_DELAY(0);
1332 case SND_SOC_DAIFMT_RIGHT_J
:
1333 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1335 case SND_SOC_DAIFMT_LEFT_J
:
1336 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1339 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1340 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1344 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1345 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1350 static int dac33_soc_probe(struct snd_soc_codec
*codec
)
1352 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1355 codec
->control_data
= dac33
->control_data
;
1356 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1357 codec
->dapm
.idle_bias_off
= 1;
1358 dac33
->codec
= codec
;
1360 /* Read the tlv320dac33 ID registers */
1361 ret
= dac33_hard_power(codec
, 1);
1363 dev_err(codec
->dev
, "Failed to power up codec: %d\n", ret
);
1366 ret
= dac33_read_id(codec
);
1367 dac33_hard_power(codec
, 0);
1370 dev_err(codec
->dev
, "Failed to read chip ID: %d\n", ret
);
1375 /* Check if the IRQ number is valid and request it */
1376 if (dac33
->irq
>= 0) {
1377 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1378 IRQF_TRIGGER_RISING
| IRQF_DISABLED
,
1379 codec
->name
, codec
);
1381 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1385 if (dac33
->irq
!= -1) {
1386 /* Setup work queue */
1388 create_singlethread_workqueue("tlv320dac33");
1389 if (dac33
->dac33_wq
== NULL
) {
1390 free_irq(dac33
->irq
, codec
);
1394 INIT_WORK(&dac33
->work
, dac33_work
);
1398 snd_soc_add_controls(codec
, dac33_snd_controls
,
1399 ARRAY_SIZE(dac33_snd_controls
));
1400 /* Only add the FIFO controls, if we have valid IRQ number */
1401 if (dac33
->irq
>= 0)
1402 snd_soc_add_controls(codec
, dac33_mode_snd_controls
,
1403 ARRAY_SIZE(dac33_mode_snd_controls
));
1405 dac33_add_widgets(codec
);
1411 static int dac33_soc_remove(struct snd_soc_codec
*codec
)
1413 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1415 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1417 if (dac33
->irq
>= 0) {
1418 free_irq(dac33
->irq
, dac33
->codec
);
1419 destroy_workqueue(dac33
->dac33_wq
);
1424 static int dac33_soc_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1426 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1431 static int dac33_soc_resume(struct snd_soc_codec
*codec
)
1433 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1438 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33
= {
1439 .read
= dac33_read_reg_cache
,
1440 .write
= dac33_write_locked
,
1441 .set_bias_level
= dac33_set_bias_level
,
1442 .reg_cache_size
= ARRAY_SIZE(dac33_reg
),
1443 .reg_word_size
= sizeof(u8
),
1444 .reg_cache_default
= dac33_reg
,
1445 .probe
= dac33_soc_probe
,
1446 .remove
= dac33_soc_remove
,
1447 .suspend
= dac33_soc_suspend
,
1448 .resume
= dac33_soc_resume
,
1451 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1452 SNDRV_PCM_RATE_48000)
1453 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1455 static struct snd_soc_dai_ops dac33_dai_ops
= {
1456 .startup
= dac33_startup
,
1457 .shutdown
= dac33_shutdown
,
1458 .hw_params
= dac33_hw_params
,
1459 .trigger
= dac33_pcm_trigger
,
1460 .delay
= dac33_dai_delay
,
1461 .set_sysclk
= dac33_set_dai_sysclk
,
1462 .set_fmt
= dac33_set_dai_fmt
,
1465 static struct snd_soc_dai_driver dac33_dai
= {
1466 .name
= "tlv320dac33-hifi",
1468 .stream_name
= "Playback",
1471 .rates
= DAC33_RATES
,
1472 .formats
= DAC33_FORMATS
,},
1473 .ops
= &dac33_dai_ops
,
1476 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1477 const struct i2c_device_id
*id
)
1479 struct tlv320dac33_platform_data
*pdata
;
1480 struct tlv320dac33_priv
*dac33
;
1483 if (client
->dev
.platform_data
== NULL
) {
1484 dev_err(&client
->dev
, "Platform data not set\n");
1487 pdata
= client
->dev
.platform_data
;
1489 dac33
= kzalloc(sizeof(struct tlv320dac33_priv
), GFP_KERNEL
);
1493 dac33
->control_data
= client
;
1494 mutex_init(&dac33
->mutex
);
1495 spin_lock_init(&dac33
->lock
);
1497 i2c_set_clientdata(client
, dac33
);
1499 dac33
->power_gpio
= pdata
->power_gpio
;
1500 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1501 dac33
->keep_bclk
= pdata
->keep_bclk
;
1502 dac33
->mode1_latency
= pdata
->mode1_latency
;
1503 if (!dac33
->mode1_latency
)
1504 dac33
->mode1_latency
= 10000; /* 10ms */
1505 dac33
->irq
= client
->irq
;
1506 /* Disable FIFO use by default */
1507 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1509 /* Check if the reset GPIO number is valid and request it */
1510 if (dac33
->power_gpio
>= 0) {
1511 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1513 dev_err(&client
->dev
,
1514 "Failed to request reset GPIO (%d)\n",
1518 gpio_direction_output(dac33
->power_gpio
, 0);
1521 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1522 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1524 ret
= regulator_bulk_get(&client
->dev
, ARRAY_SIZE(dac33
->supplies
),
1528 dev_err(&client
->dev
, "Failed to request supplies: %d\n", ret
);
1532 ret
= snd_soc_register_codec(&client
->dev
,
1533 &soc_codec_dev_tlv320dac33
, &dac33_dai
, 1);
1539 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1541 if (dac33
->power_gpio
>= 0)
1542 gpio_free(dac33
->power_gpio
);
1548 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1550 struct tlv320dac33_priv
*dac33
= i2c_get_clientdata(client
);
1552 if (unlikely(dac33
->chip_power
))
1553 dac33_hard_power(dac33
->codec
, 0);
1555 if (dac33
->power_gpio
>= 0)
1556 gpio_free(dac33
->power_gpio
);
1558 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1560 snd_soc_unregister_codec(&client
->dev
);
1566 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1568 .name
= "tlv320dac33",
1574 static struct i2c_driver tlv320dac33_i2c_driver
= {
1576 .name
= "tlv320dac33-codec",
1577 .owner
= THIS_MODULE
,
1579 .probe
= dac33_i2c_probe
,
1580 .remove
= __devexit_p(dac33_i2c_remove
),
1581 .id_table
= tlv320dac33_i2c_id
,
1584 static int __init
dac33_module_init(void)
1587 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1589 printk(KERN_ERR
"DAC33: driver registration failed\n");
1594 module_init(dac33_module_init
);
1596 static void __exit
dac33_module_exit(void)
1598 i2c_del_driver(&tlv320dac33_i2c_driver
);
1600 module_exit(dac33_module_exit
);
1603 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1604 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1605 MODULE_LICENSE("GPL");