2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
42 #include <sound/tlv320dac33-plat.h>
43 #include "tlv320dac33.h"
45 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
47 #define DAC33_BUFFER_SIZE_SAMPLES 6144
49 #define NSAMPLE_MAX 5700
52 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
54 #define BURST_BASEFREQ_HZ 49152000
56 #define SAMPLES_TO_US(rate, samples) \
57 (1000000000 / ((rate * 1000) / samples))
59 #define US_TO_SAMPLES(rate, us) \
60 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
62 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
63 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
65 static void dac33_calculate_times(struct snd_pcm_substream
*substream
);
66 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
);
75 enum dac33_fifo_modes
{
76 DAC33_FIFO_BYPASS
= 0,
82 #define DAC33_NUM_SUPPLIES 3
83 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
89 struct tlv320dac33_priv
{
91 struct workqueue_struct
*dac33_wq
;
92 struct work_struct work
;
93 struct snd_soc_codec
*codec
;
94 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
95 struct snd_pcm_substream
*substream
;
101 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
102 unsigned int nsample_min
; /* nsample should not be lower than
104 unsigned int nsample_max
; /* nsample should not be higher than
106 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
107 unsigned int nsample
; /* burst read amount from host */
108 int mode1_latency
; /* latency caused by the i2c writes in
110 int auto_fifo_config
; /* Configure the FIFO based on the
112 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
113 unsigned int burst_rate
; /* Interface speed in Burst modes */
115 int keep_bclk
; /* Keep the BCLK continuously running
118 unsigned long long t_stamp1
; /* Time stamp for FIFO modes to */
119 unsigned long long t_stamp2
; /* calculate the FIFO caused delay */
121 unsigned int mode1_us_burst
; /* Time to burst read n number of
123 unsigned int mode7_us_to_lthr
; /* Time to reach lthr from uthr */
127 enum dac33_state state
;
128 enum snd_soc_control_type control_type
;
132 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
133 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
134 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
135 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
136 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
137 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
138 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
139 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
140 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
141 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
142 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
143 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
144 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
145 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
146 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
147 0x00, 0x00, /* 0x38 - 0x39 */
148 /* Registers 0x3a - 0x3f are reserved */
149 0x00, 0x00, /* 0x3a - 0x3b */
150 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
152 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
153 0x00, 0x80, /* 0x44 - 0x45 */
154 /* Registers 0x46 - 0x47 are reserved */
155 0x80, 0x80, /* 0x46 - 0x47 */
157 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
158 /* Registers 0x4b - 0x7c are reserved */
160 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
161 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
162 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
163 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
164 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
165 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
166 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
167 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
168 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
169 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
170 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
171 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
174 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
177 /* Register read and write */
178 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
181 u8
*cache
= codec
->reg_cache
;
182 if (reg
>= DAC33_CACHEREGNUM
)
188 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
191 u8
*cache
= codec
->reg_cache
;
192 if (reg
>= DAC33_CACHEREGNUM
)
198 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
201 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
206 /* If powered off, return the cached value */
207 if (dac33
->chip_power
) {
208 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
210 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
211 value
[0] = dac33_read_reg_cache(codec
, reg
);
215 dac33_write_reg_cache(codec
, reg
, val
);
218 value
[0] = dac33_read_reg_cache(codec
, reg
);
224 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
227 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
233 * D15..D8 dac33 register offset
234 * D7...D0 register data
236 data
[0] = reg
& 0xff;
237 data
[1] = value
& 0xff;
239 dac33_write_reg_cache(codec
, data
[0], data
[1]);
240 if (dac33
->chip_power
) {
241 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
243 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
251 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
254 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
257 mutex_lock(&dac33
->mutex
);
258 ret
= dac33_write(codec
, reg
, value
);
259 mutex_unlock(&dac33
->mutex
);
264 #define DAC33_I2C_ADDR_AUTOINC 0x80
265 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
268 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
274 * D23..D16 dac33 register offset
275 * D15..D8 register data MSB
276 * D7...D0 register data LSB
278 data
[0] = reg
& 0xff;
279 data
[1] = (value
>> 8) & 0xff;
280 data
[2] = value
& 0xff;
282 dac33_write_reg_cache(codec
, data
[0], data
[1]);
283 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
285 if (dac33
->chip_power
) {
286 /* We need to set autoincrement mode for 16 bit writes */
287 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
288 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
290 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
298 static void dac33_init_chip(struct snd_soc_codec
*codec
)
300 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
302 if (unlikely(!dac33
->chip_power
))
305 /* 44-46: DAC Control Registers */
306 /* A : DAC sample rate Fsref/1.5 */
307 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(0));
308 /* B : DAC src=normal, not muted */
309 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
312 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
314 /* 73 : volume soft stepping control,
315 clock source = internal osc (?) */
316 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
318 /* Restore only selected registers (gains mostly) */
319 dac33_write(codec
, DAC33_LDAC_DIG_VOL_CTRL
,
320 dac33_read_reg_cache(codec
, DAC33_LDAC_DIG_VOL_CTRL
));
321 dac33_write(codec
, DAC33_RDAC_DIG_VOL_CTRL
,
322 dac33_read_reg_cache(codec
, DAC33_RDAC_DIG_VOL_CTRL
));
324 dac33_write(codec
, DAC33_LINEL_TO_LLO_VOL
,
325 dac33_read_reg_cache(codec
, DAC33_LINEL_TO_LLO_VOL
));
326 dac33_write(codec
, DAC33_LINER_TO_RLO_VOL
,
327 dac33_read_reg_cache(codec
, DAC33_LINER_TO_RLO_VOL
));
330 static inline int dac33_read_id(struct snd_soc_codec
*codec
)
335 for (i
= 0; i
< 3; i
++) {
336 ret
= dac33_read(codec
, DAC33_DEVICE_ID_MSB
+ i
, ®
);
344 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
348 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
350 reg
|= DAC33_PDNALLB
;
352 reg
&= ~(DAC33_PDNALLB
| DAC33_OSCPDNB
|
353 DAC33_DACRPDNB
| DAC33_DACLPDNB
);
354 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
357 static inline void dac33_disable_digital(struct snd_soc_codec
*codec
)
361 /* Stop the DAI clock */
362 reg
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
363 reg
&= ~DAC33_BCLKON
;
364 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, reg
);
366 /* Power down the Oscillator, and DACs */
367 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
368 reg
&= ~(DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
);
369 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
372 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
374 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
377 mutex_lock(&dac33
->mutex
);
380 if (unlikely(power
== dac33
->chip_power
)) {
381 dev_dbg(codec
->dev
, "Trying to set the same power state: %s\n",
382 power
? "ON" : "OFF");
387 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
391 "Failed to enable supplies: %d\n", ret
);
395 if (dac33
->power_gpio
>= 0)
396 gpio_set_value(dac33
->power_gpio
, 1);
398 dac33
->chip_power
= 1;
400 dac33_soft_power(codec
, 0);
401 if (dac33
->power_gpio
>= 0)
402 gpio_set_value(dac33
->power_gpio
, 0);
404 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
408 "Failed to disable supplies: %d\n", ret
);
412 dac33
->chip_power
= 0;
416 mutex_unlock(&dac33
->mutex
);
420 static int dac33_playback_event(struct snd_soc_dapm_widget
*w
,
421 struct snd_kcontrol
*kcontrol
, int event
)
423 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(w
->codec
);
426 case SND_SOC_DAPM_PRE_PMU
:
427 if (likely(dac33
->substream
)) {
428 dac33_calculate_times(dac33
->substream
);
429 dac33_prepare_chip(dac33
->substream
);
432 case SND_SOC_DAPM_POST_PMD
:
433 dac33_disable_digital(w
->codec
);
439 static int dac33_get_nsample(struct snd_kcontrol
*kcontrol
,
440 struct snd_ctl_elem_value
*ucontrol
)
442 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
443 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
445 ucontrol
->value
.integer
.value
[0] = dac33
->nsample
;
450 static int dac33_set_nsample(struct snd_kcontrol
*kcontrol
,
451 struct snd_ctl_elem_value
*ucontrol
)
453 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
454 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
457 if (dac33
->nsample
== ucontrol
->value
.integer
.value
[0])
460 if (ucontrol
->value
.integer
.value
[0] < dac33
->nsample_min
||
461 ucontrol
->value
.integer
.value
[0] > dac33
->nsample_max
) {
464 dac33
->nsample
= ucontrol
->value
.integer
.value
[0];
465 /* Re calculate the burst time */
466 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
473 static int dac33_get_uthr(struct snd_kcontrol
*kcontrol
,
474 struct snd_ctl_elem_value
*ucontrol
)
476 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
477 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
479 ucontrol
->value
.integer
.value
[0] = dac33
->uthr
;
484 static int dac33_set_uthr(struct snd_kcontrol
*kcontrol
,
485 struct snd_ctl_elem_value
*ucontrol
)
487 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
488 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
491 if (dac33
->substream
)
494 if (dac33
->uthr
== ucontrol
->value
.integer
.value
[0])
497 if (ucontrol
->value
.integer
.value
[0] < (MODE7_LTHR
+ 10) ||
498 ucontrol
->value
.integer
.value
[0] > MODE7_UTHR
)
501 dac33
->uthr
= ucontrol
->value
.integer
.value
[0];
506 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
507 struct snd_ctl_elem_value
*ucontrol
)
509 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
510 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
512 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
517 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
518 struct snd_ctl_elem_value
*ucontrol
)
520 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
521 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
524 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
526 /* Do not allow changes while stream is running*/
530 if (ucontrol
->value
.integer
.value
[0] < 0 ||
531 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
534 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
539 /* Codec operation modes */
540 static const char *dac33_fifo_mode_texts
[] = {
541 "Bypass", "Mode 1", "Mode 7"
544 static const struct soc_enum dac33_fifo_mode_enum
=
545 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
546 dac33_fifo_mode_texts
);
548 /* L/R Line Output Gain */
549 static const char *lr_lineout_gain_texts
[] = {
550 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
551 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
554 static const struct soc_enum l_lineout_gain_enum
=
555 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL
, 0,
556 ARRAY_SIZE(lr_lineout_gain_texts
),
557 lr_lineout_gain_texts
);
559 static const struct soc_enum r_lineout_gain_enum
=
560 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL
, 0,
561 ARRAY_SIZE(lr_lineout_gain_texts
),
562 lr_lineout_gain_texts
);
565 * DACL/R digital volume control:
566 * from 0 dB to -63.5 in 0.5 dB steps
567 * Need to be inverted later on:
571 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
573 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
574 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
575 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
576 0, 0x7f, 1, dac_digivol_tlv
),
577 SOC_DOUBLE_R("DAC Digital Playback Switch",
578 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
579 SOC_DOUBLE_R("Line to Line Out Volume",
580 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
581 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum
),
582 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum
),
585 static const struct snd_kcontrol_new dac33_mode_snd_controls
[] = {
586 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
587 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
590 static const struct snd_kcontrol_new dac33_fifo_snd_controls
[] = {
591 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
592 dac33_get_nsample
, dac33_set_nsample
),
593 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR
, 0,
594 dac33_get_uthr
, dac33_set_uthr
),
598 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
599 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
601 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
602 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
604 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
605 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
606 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
608 SND_SOC_DAPM_INPUT("LINEL"),
609 SND_SOC_DAPM_INPUT("LINER"),
611 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM
, 0, 0),
612 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM
, 0, 0),
615 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
616 &dac33_dapm_abypassl_control
),
617 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
618 &dac33_dapm_abypassr_control
),
620 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amplifier",
621 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
622 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amplifier",
623 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
625 SND_SOC_DAPM_SUPPLY("Left DAC Power",
626 DAC33_LDAC_PWR_CTRL
, 2, 0, NULL
, 0),
627 SND_SOC_DAPM_SUPPLY("Right DAC Power",
628 DAC33_RDAC_PWR_CTRL
, 2, 0, NULL
, 0),
630 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event
),
631 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event
),
634 static const struct snd_soc_dapm_route audio_map
[] = {
636 {"Analog Left Bypass", "Switch", "LINEL"},
637 {"Analog Right Bypass", "Switch", "LINER"},
639 {"Output Left Amplifier", NULL
, "DACL"},
640 {"Output Right Amplifier", NULL
, "DACR"},
642 {"Output Left Amplifier", NULL
, "Analog Left Bypass"},
643 {"Output Right Amplifier", NULL
, "Analog Right Bypass"},
645 {"Output Left Amplifier", NULL
, "Left DAC Power"},
646 {"Output Right Amplifier", NULL
, "Right DAC Power"},
649 {"LEFT_LO", NULL
, "Output Left Amplifier"},
650 {"RIGHT_LO", NULL
, "Output Right Amplifier"},
653 static int dac33_add_widgets(struct snd_soc_codec
*codec
)
655 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
657 snd_soc_dapm_new_controls(dapm
, dac33_dapm_widgets
,
658 ARRAY_SIZE(dac33_dapm_widgets
));
659 /* set up audio path interconnects */
660 snd_soc_dapm_add_routes(dapm
, audio_map
, ARRAY_SIZE(audio_map
));
665 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
666 enum snd_soc_bias_level level
)
668 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
672 case SND_SOC_BIAS_ON
:
673 if (!dac33
->substream
)
674 dac33_soft_power(codec
, 1);
676 case SND_SOC_BIAS_PREPARE
:
678 case SND_SOC_BIAS_STANDBY
:
679 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
680 /* Coming from OFF, switch on the codec */
681 ret
= dac33_hard_power(codec
, 1);
685 dac33_init_chip(codec
);
688 case SND_SOC_BIAS_OFF
:
689 /* Do not power off, when the codec is already off */
690 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
)
692 ret
= dac33_hard_power(codec
, 0);
697 codec
->dapm
.bias_level
= level
;
702 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
704 struct snd_soc_codec
*codec
= dac33
->codec
;
707 switch (dac33
->fifo_mode
) {
708 case DAC33_FIFO_MODE1
:
709 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
710 DAC33_THRREG(dac33
->nsample
));
712 /* Take the timestamps */
713 spin_lock_irq(&dac33
->lock
);
714 dac33
->t_stamp2
= ktime_to_us(ktime_get());
715 dac33
->t_stamp1
= dac33
->t_stamp2
;
716 spin_unlock_irq(&dac33
->lock
);
718 dac33_write16(codec
, DAC33_PREFILL_MSB
,
719 DAC33_THRREG(dac33
->alarm_threshold
));
720 /* Enable Alarm Threshold IRQ with a delay */
721 delay
= SAMPLES_TO_US(dac33
->burst_rate
,
722 dac33
->alarm_threshold
) + 1000;
723 usleep_range(delay
, delay
+ 500);
724 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
726 case DAC33_FIFO_MODE7
:
727 /* Take the timestamp */
728 spin_lock_irq(&dac33
->lock
);
729 dac33
->t_stamp1
= ktime_to_us(ktime_get());
730 /* Move back the timestamp with drain time */
731 dac33
->t_stamp1
-= dac33
->mode7_us_to_lthr
;
732 spin_unlock_irq(&dac33
->lock
);
734 dac33_write16(codec
, DAC33_PREFILL_MSB
,
735 DAC33_THRREG(MODE7_LTHR
));
737 /* Enable Upper Threshold IRQ */
738 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MUT
);
741 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
747 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
749 struct snd_soc_codec
*codec
= dac33
->codec
;
751 switch (dac33
->fifo_mode
) {
752 case DAC33_FIFO_MODE1
:
753 /* Take the timestamp */
754 spin_lock_irq(&dac33
->lock
);
755 dac33
->t_stamp2
= ktime_to_us(ktime_get());
756 spin_unlock_irq(&dac33
->lock
);
758 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
759 DAC33_THRREG(dac33
->nsample
));
761 case DAC33_FIFO_MODE7
:
762 /* At the moment we are not using interrupts in mode7 */
765 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
771 static void dac33_work(struct work_struct
*work
)
773 struct snd_soc_codec
*codec
;
774 struct tlv320dac33_priv
*dac33
;
777 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
778 codec
= dac33
->codec
;
780 mutex_lock(&dac33
->mutex
);
781 switch (dac33
->state
) {
783 dac33
->state
= DAC33_PLAYBACK
;
784 dac33_prefill_handler(dac33
);
787 dac33_playback_handler(dac33
);
792 dac33
->state
= DAC33_IDLE
;
793 /* Mask all interrupts from dac33 */
794 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
797 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
798 reg
|= DAC33_FIFOFLUSH
;
799 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
802 mutex_unlock(&dac33
->mutex
);
805 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
807 struct snd_soc_codec
*codec
= dev
;
808 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
810 spin_lock(&dac33
->lock
);
811 dac33
->t_stamp1
= ktime_to_us(ktime_get());
812 spin_unlock(&dac33
->lock
);
814 /* Do not schedule the workqueue in Mode7 */
815 if (dac33
->fifo_mode
!= DAC33_FIFO_MODE7
)
816 queue_work(dac33
->dac33_wq
, &dac33
->work
);
821 static void dac33_oscwait(struct snd_soc_codec
*codec
)
827 usleep_range(1000, 2000);
828 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
829 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
830 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
832 "internal oscillator calibration failed\n");
835 static int dac33_startup(struct snd_pcm_substream
*substream
,
836 struct snd_soc_dai
*dai
)
838 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
839 struct snd_soc_codec
*codec
= rtd
->codec
;
840 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
842 /* Stream started, save the substream pointer */
843 dac33
->substream
= substream
;
848 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
849 struct snd_soc_dai
*dai
)
851 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
852 struct snd_soc_codec
*codec
= rtd
->codec
;
853 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
855 dac33
->substream
= NULL
;
857 /* Reset the nSample restrictions */
858 dac33
->nsample_min
= 0;
859 dac33
->nsample_max
= NSAMPLE_MAX
;
862 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
863 struct snd_pcm_hw_params
*params
,
864 struct snd_soc_dai
*dai
)
866 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
867 struct snd_soc_codec
*codec
= rtd
->codec
;
869 /* Check parameters for validity */
870 switch (params_rate(params
)) {
875 dev_err(codec
->dev
, "unsupported rate %d\n",
876 params_rate(params
));
880 switch (params_format(params
)) {
881 case SNDRV_PCM_FORMAT_S16_LE
:
884 dev_err(codec
->dev
, "unsupported format %d\n",
885 params_format(params
));
892 #define CALC_OSCSET(rate, refclk) ( \
893 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
894 #define CALC_RATIOSET(rate, refclk) ( \
895 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
898 * tlv320dac33 is strict on the sequence of the register writes, if the register
899 * writes happens in different order, than dac33 might end up in unknown state.
900 * Use the known, working sequence of register writes to initialize the dac33.
902 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
904 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
905 struct snd_soc_codec
*codec
= rtd
->codec
;
906 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
907 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
908 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
910 switch (substream
->runtime
->rate
) {
913 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
914 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
918 dev_err(codec
->dev
, "unsupported rate %d\n",
919 substream
->runtime
->rate
);
924 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
925 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
926 /* Read FIFO control A, and clear FIFO flush bit */
927 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
928 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
930 fifoctrl_a
&= ~DAC33_WIDTH
;
931 switch (substream
->runtime
->format
) {
932 case SNDRV_PCM_FORMAT_S16_LE
:
933 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
934 fifoctrl_a
|= DAC33_WIDTH
;
937 dev_err(codec
->dev
, "unsupported format %d\n",
938 substream
->runtime
->format
);
942 mutex_lock(&dac33
->mutex
);
944 if (!dac33
->chip_power
) {
946 * Chip is not powered yet.
947 * Do the init in the dac33_set_bias_level later.
949 mutex_unlock(&dac33
->mutex
);
953 dac33_soft_power(codec
, 0);
954 dac33_soft_power(codec
, 1);
956 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
957 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
959 /* Write registers 0x08 and 0x09 (MSB, LSB) */
960 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
962 /* calib time: 128 is a nice number ;) */
963 dac33_write(codec
, DAC33_CALIB_TIME
, 128);
965 /* adjustment treshold & step */
966 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
969 /* div=4 / gain=1 / div */
970 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
972 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
973 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
974 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
976 dac33_oscwait(codec
);
978 if (dac33
->fifo_mode
) {
979 /* Generic for all FIFO modes */
980 /* 50-51 : ASRC Control registers */
981 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCLKDIV(1));
982 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
984 /* Write registers 0x34 and 0x35 (MSB, LSB) */
985 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
987 /* Set interrupts to high active */
988 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
990 /* FIFO bypass mode */
991 /* 50-51 : ASRC Control registers */
992 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
993 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
996 /* Interrupt behaviour configuration */
997 switch (dac33
->fifo_mode
) {
998 case DAC33_FIFO_MODE1
:
999 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
1000 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
1002 case DAC33_FIFO_MODE7
:
1003 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_A
,
1004 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL
));
1007 /* in FIFO bypass mode, the interrupts are not used */
1011 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1013 switch (dac33
->fifo_mode
) {
1014 case DAC33_FIFO_MODE1
:
1017 * Disable the FIFO bypass (Enable the use of FIFO)
1018 * Select nSample mode
1019 * BCLK is only running when data is needed by DAC33
1021 fifoctrl_a
&= ~DAC33_FBYPAS
;
1022 fifoctrl_a
&= ~DAC33_FAUTO
;
1023 if (dac33
->keep_bclk
)
1024 aictrl_b
|= DAC33_BCLKON
;
1026 aictrl_b
&= ~DAC33_BCLKON
;
1028 case DAC33_FIFO_MODE7
:
1031 * Disable the FIFO bypass (Enable the use of FIFO)
1032 * Select Threshold mode
1033 * BCLK is only running when data is needed by DAC33
1035 fifoctrl_a
&= ~DAC33_FBYPAS
;
1036 fifoctrl_a
|= DAC33_FAUTO
;
1037 if (dac33
->keep_bclk
)
1038 aictrl_b
|= DAC33_BCLKON
;
1040 aictrl_b
&= ~DAC33_BCLKON
;
1044 * For FIFO bypass mode:
1045 * Enable the FIFO bypass (Disable the FIFO use)
1046 * Set the BCLK as continous
1048 fifoctrl_a
|= DAC33_FBYPAS
;
1049 aictrl_b
|= DAC33_BCLKON
;
1053 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
1054 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1055 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1066 if (dac33
->fifo_mode
)
1067 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
1068 dac33
->burst_bclkdiv
);
1070 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
1072 switch (dac33
->fifo_mode
) {
1073 case DAC33_FIFO_MODE1
:
1074 dac33_write16(codec
, DAC33_ATHR_MSB
,
1075 DAC33_THRREG(dac33
->alarm_threshold
));
1077 case DAC33_FIFO_MODE7
:
1079 * Configure the threshold levels, and leave 10 sample space
1080 * at the bottom, and also at the top of the FIFO
1082 dac33_write16(codec
, DAC33_UTHR_MSB
, DAC33_THRREG(dac33
->uthr
));
1083 dac33_write16(codec
, DAC33_LTHR_MSB
, DAC33_THRREG(MODE7_LTHR
));
1089 mutex_unlock(&dac33
->mutex
);
1094 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
1096 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1097 struct snd_soc_codec
*codec
= rtd
->codec
;
1098 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1099 unsigned int period_size
= substream
->runtime
->period_size
;
1100 unsigned int rate
= substream
->runtime
->rate
;
1101 unsigned int nsample_limit
;
1103 /* In bypass mode we don't need to calculate */
1104 if (!dac33
->fifo_mode
)
1107 switch (dac33
->fifo_mode
) {
1108 case DAC33_FIFO_MODE1
:
1109 /* Number of samples under i2c latency */
1110 dac33
->alarm_threshold
= US_TO_SAMPLES(rate
,
1111 dac33
->mode1_latency
);
1112 nsample_limit
= DAC33_BUFFER_SIZE_SAMPLES
-
1113 dac33
->alarm_threshold
;
1115 if (dac33
->auto_fifo_config
) {
1116 if (period_size
<= dac33
->alarm_threshold
)
1118 * Configure nSamaple to number of periods,
1119 * which covers the latency requironment.
1121 dac33
->nsample
= period_size
*
1122 ((dac33
->alarm_threshold
/ period_size
) +
1123 (dac33
->alarm_threshold
% period_size
?
1125 else if (period_size
> nsample_limit
)
1126 dac33
->nsample
= nsample_limit
;
1128 dac33
->nsample
= period_size
;
1130 /* nSample time shall not be shorter than i2c latency */
1131 dac33
->nsample_min
= dac33
->alarm_threshold
;
1133 * nSample should not be bigger than alsa buffer minus
1134 * size of one period to avoid overruns
1136 dac33
->nsample_max
= substream
->runtime
->buffer_size
-
1139 if (dac33
->nsample_max
> nsample_limit
)
1140 dac33
->nsample_max
= nsample_limit
;
1142 /* Correct the nSample if it is outside of the ranges */
1143 if (dac33
->nsample
< dac33
->nsample_min
)
1144 dac33
->nsample
= dac33
->nsample_min
;
1145 if (dac33
->nsample
> dac33
->nsample_max
)
1146 dac33
->nsample
= dac33
->nsample_max
;
1149 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
1151 dac33
->t_stamp1
= 0;
1152 dac33
->t_stamp2
= 0;
1154 case DAC33_FIFO_MODE7
:
1155 if (dac33
->auto_fifo_config
) {
1156 dac33
->uthr
= UTHR_FROM_PERIOD_SIZE(
1159 dac33
->burst_rate
) + 9;
1160 if (dac33
->uthr
> MODE7_UTHR
)
1161 dac33
->uthr
= MODE7_UTHR
;
1162 if (dac33
->uthr
< (MODE7_LTHR
+ 10))
1163 dac33
->uthr
= (MODE7_LTHR
+ 10);
1165 dac33
->mode7_us_to_lthr
=
1166 SAMPLES_TO_US(substream
->runtime
->rate
,
1167 dac33
->uthr
- MODE7_LTHR
+ 1);
1168 dac33
->t_stamp1
= 0;
1176 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1177 struct snd_soc_dai
*dai
)
1179 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1180 struct snd_soc_codec
*codec
= rtd
->codec
;
1181 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1185 case SNDRV_PCM_TRIGGER_START
:
1186 case SNDRV_PCM_TRIGGER_RESUME
:
1187 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1188 if (dac33
->fifo_mode
) {
1189 dac33
->state
= DAC33_PREFILL
;
1190 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1193 case SNDRV_PCM_TRIGGER_STOP
:
1194 case SNDRV_PCM_TRIGGER_SUSPEND
:
1195 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1196 if (dac33
->fifo_mode
) {
1197 dac33
->state
= DAC33_FLUSH
;
1198 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1208 static snd_pcm_sframes_t
dac33_dai_delay(
1209 struct snd_pcm_substream
*substream
,
1210 struct snd_soc_dai
*dai
)
1212 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1213 struct snd_soc_codec
*codec
= rtd
->codec
;
1214 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1215 unsigned long long t0
, t1
, t_now
;
1216 unsigned int time_delta
, uthr
;
1217 int samples_out
, samples_in
, samples
;
1218 snd_pcm_sframes_t delay
= 0;
1220 switch (dac33
->fifo_mode
) {
1221 case DAC33_FIFO_BYPASS
:
1223 case DAC33_FIFO_MODE1
:
1224 spin_lock(&dac33
->lock
);
1225 t0
= dac33
->t_stamp1
;
1226 t1
= dac33
->t_stamp2
;
1227 spin_unlock(&dac33
->lock
);
1228 t_now
= ktime_to_us(ktime_get());
1230 /* We have not started to fill the FIFO yet, delay is 0 */
1237 * After Alarm threshold, and before nSample write
1239 time_delta
= t_now
- t0
;
1240 samples_out
= time_delta
? US_TO_SAMPLES(
1241 substream
->runtime
->rate
,
1244 if (likely(dac33
->alarm_threshold
> samples_out
))
1245 delay
= dac33
->alarm_threshold
- samples_out
;
1248 } else if ((t_now
- t1
) <= dac33
->mode1_us_burst
) {
1251 * After nSample write (during burst operation)
1253 time_delta
= t_now
- t0
;
1254 samples_out
= time_delta
? US_TO_SAMPLES(
1255 substream
->runtime
->rate
,
1258 time_delta
= t_now
- t1
;
1259 samples_in
= time_delta
? US_TO_SAMPLES(
1263 samples
= dac33
->alarm_threshold
;
1264 samples
+= (samples_in
- samples_out
);
1266 if (likely(samples
> 0))
1273 * After burst operation, before next alarm threshold
1275 time_delta
= t_now
- t0
;
1276 samples_out
= time_delta
? US_TO_SAMPLES(
1277 substream
->runtime
->rate
,
1280 samples_in
= dac33
->nsample
;
1281 samples
= dac33
->alarm_threshold
;
1282 samples
+= (samples_in
- samples_out
);
1284 if (likely(samples
> 0))
1285 delay
= samples
> DAC33_BUFFER_SIZE_SAMPLES
?
1286 DAC33_BUFFER_SIZE_SAMPLES
: samples
;
1291 case DAC33_FIFO_MODE7
:
1292 spin_lock(&dac33
->lock
);
1293 t0
= dac33
->t_stamp1
;
1295 spin_unlock(&dac33
->lock
);
1296 t_now
= ktime_to_us(ktime_get());
1298 /* We have not started to fill the FIFO yet, delay is 0 */
1304 * Either the timestamps are messed or equal. Report
1311 time_delta
= t_now
- t0
;
1312 if (time_delta
<= dac33
->mode7_us_to_lthr
) {
1315 * After burst (draining phase)
1317 samples_out
= US_TO_SAMPLES(
1318 substream
->runtime
->rate
,
1321 if (likely(uthr
> samples_out
))
1322 delay
= uthr
- samples_out
;
1328 * During burst operation
1330 time_delta
= time_delta
- dac33
->mode7_us_to_lthr
;
1332 samples_out
= US_TO_SAMPLES(
1333 substream
->runtime
->rate
,
1335 samples_in
= US_TO_SAMPLES(
1338 delay
= MODE7_LTHR
+ samples_in
- samples_out
;
1340 if (unlikely(delay
> uthr
))
1345 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
1353 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1354 int clk_id
, unsigned int freq
, int dir
)
1356 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1357 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1358 u8 ioc_reg
, asrcb_reg
;
1360 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
1361 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
1363 case TLV320DAC33_MCLK
:
1364 ioc_reg
|= DAC33_REFSEL
;
1365 asrcb_reg
|= DAC33_SRCREFSEL
;
1367 case TLV320DAC33_SLEEPCLK
:
1368 ioc_reg
&= ~DAC33_REFSEL
;
1369 asrcb_reg
&= ~DAC33_SRCREFSEL
;
1372 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
1375 dac33
->refclk
= freq
;
1377 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1378 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1383 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1386 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1387 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1388 u8 aictrl_a
, aictrl_b
;
1390 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1391 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1392 /* set master/slave audio interface */
1393 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1394 case SND_SOC_DAIFMT_CBM_CFM
:
1396 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1398 case SND_SOC_DAIFMT_CBS_CFS
:
1400 if (dac33
->fifo_mode
) {
1401 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1404 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1410 aictrl_a
&= ~DAC33_AFMT_MASK
;
1411 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1412 case SND_SOC_DAIFMT_I2S
:
1413 aictrl_a
|= DAC33_AFMT_I2S
;
1415 case SND_SOC_DAIFMT_DSP_A
:
1416 aictrl_a
|= DAC33_AFMT_DSP
;
1417 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1418 aictrl_b
|= DAC33_DATA_DELAY(0);
1420 case SND_SOC_DAIFMT_RIGHT_J
:
1421 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1423 case SND_SOC_DAIFMT_LEFT_J
:
1424 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1427 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1428 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1432 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1433 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1438 static int dac33_soc_probe(struct snd_soc_codec
*codec
)
1440 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1443 codec
->control_data
= dac33
->control_data
;
1444 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1445 codec
->dapm
.idle_bias_off
= 1;
1446 dac33
->codec
= codec
;
1448 /* Read the tlv320dac33 ID registers */
1449 ret
= dac33_hard_power(codec
, 1);
1451 dev_err(codec
->dev
, "Failed to power up codec: %d\n", ret
);
1454 ret
= dac33_read_id(codec
);
1455 dac33_hard_power(codec
, 0);
1458 dev_err(codec
->dev
, "Failed to read chip ID: %d\n", ret
);
1463 /* Check if the IRQ number is valid and request it */
1464 if (dac33
->irq
>= 0) {
1465 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1466 IRQF_TRIGGER_RISING
| IRQF_DISABLED
,
1467 codec
->name
, codec
);
1469 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1473 if (dac33
->irq
!= -1) {
1474 /* Setup work queue */
1476 create_singlethread_workqueue("tlv320dac33");
1477 if (dac33
->dac33_wq
== NULL
) {
1478 free_irq(dac33
->irq
, codec
);
1482 INIT_WORK(&dac33
->work
, dac33_work
);
1486 snd_soc_add_controls(codec
, dac33_snd_controls
,
1487 ARRAY_SIZE(dac33_snd_controls
));
1488 /* Only add the FIFO controls, if we have valid IRQ number */
1489 if (dac33
->irq
>= 0) {
1490 snd_soc_add_controls(codec
, dac33_mode_snd_controls
,
1491 ARRAY_SIZE(dac33_mode_snd_controls
));
1492 /* FIFO usage controls only, if autoio config is not selected */
1493 if (!dac33
->auto_fifo_config
)
1494 snd_soc_add_controls(codec
, dac33_fifo_snd_controls
,
1495 ARRAY_SIZE(dac33_fifo_snd_controls
));
1497 dac33_add_widgets(codec
);
1503 static int dac33_soc_remove(struct snd_soc_codec
*codec
)
1505 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1507 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1509 if (dac33
->irq
>= 0) {
1510 free_irq(dac33
->irq
, dac33
->codec
);
1511 destroy_workqueue(dac33
->dac33_wq
);
1516 static int dac33_soc_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1518 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1523 static int dac33_soc_resume(struct snd_soc_codec
*codec
)
1525 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1530 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33
= {
1531 .read
= dac33_read_reg_cache
,
1532 .write
= dac33_write_locked
,
1533 .set_bias_level
= dac33_set_bias_level
,
1534 .reg_cache_size
= ARRAY_SIZE(dac33_reg
),
1535 .reg_word_size
= sizeof(u8
),
1536 .reg_cache_default
= dac33_reg
,
1537 .probe
= dac33_soc_probe
,
1538 .remove
= dac33_soc_remove
,
1539 .suspend
= dac33_soc_suspend
,
1540 .resume
= dac33_soc_resume
,
1543 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1544 SNDRV_PCM_RATE_48000)
1545 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1547 static struct snd_soc_dai_ops dac33_dai_ops
= {
1548 .startup
= dac33_startup
,
1549 .shutdown
= dac33_shutdown
,
1550 .hw_params
= dac33_hw_params
,
1551 .trigger
= dac33_pcm_trigger
,
1552 .delay
= dac33_dai_delay
,
1553 .set_sysclk
= dac33_set_dai_sysclk
,
1554 .set_fmt
= dac33_set_dai_fmt
,
1557 static struct snd_soc_dai_driver dac33_dai
= {
1558 .name
= "tlv320dac33-hifi",
1560 .stream_name
= "Playback",
1563 .rates
= DAC33_RATES
,
1564 .formats
= DAC33_FORMATS
,},
1565 .ops
= &dac33_dai_ops
,
1568 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1569 const struct i2c_device_id
*id
)
1571 struct tlv320dac33_platform_data
*pdata
;
1572 struct tlv320dac33_priv
*dac33
;
1575 if (client
->dev
.platform_data
== NULL
) {
1576 dev_err(&client
->dev
, "Platform data not set\n");
1579 pdata
= client
->dev
.platform_data
;
1581 dac33
= kzalloc(sizeof(struct tlv320dac33_priv
), GFP_KERNEL
);
1585 dac33
->control_data
= client
;
1586 mutex_init(&dac33
->mutex
);
1587 spin_lock_init(&dac33
->lock
);
1589 i2c_set_clientdata(client
, dac33
);
1591 dac33
->power_gpio
= pdata
->power_gpio
;
1592 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1593 /* Pre calculate the burst rate */
1594 dac33
->burst_rate
= BURST_BASEFREQ_HZ
/ dac33
->burst_bclkdiv
/ 32;
1595 dac33
->keep_bclk
= pdata
->keep_bclk
;
1596 dac33
->auto_fifo_config
= pdata
->auto_fifo_config
;
1597 dac33
->mode1_latency
= pdata
->mode1_latency
;
1598 if (!dac33
->mode1_latency
)
1599 dac33
->mode1_latency
= 10000; /* 10ms */
1600 dac33
->irq
= client
->irq
;
1601 dac33
->nsample
= NSAMPLE_MAX
;
1602 dac33
->nsample_max
= NSAMPLE_MAX
;
1603 dac33
->uthr
= MODE7_UTHR
;
1604 /* Disable FIFO use by default */
1605 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1607 /* Check if the reset GPIO number is valid and request it */
1608 if (dac33
->power_gpio
>= 0) {
1609 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1611 dev_err(&client
->dev
,
1612 "Failed to request reset GPIO (%d)\n",
1616 gpio_direction_output(dac33
->power_gpio
, 0);
1619 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1620 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1622 ret
= regulator_bulk_get(&client
->dev
, ARRAY_SIZE(dac33
->supplies
),
1626 dev_err(&client
->dev
, "Failed to request supplies: %d\n", ret
);
1630 ret
= snd_soc_register_codec(&client
->dev
,
1631 &soc_codec_dev_tlv320dac33
, &dac33_dai
, 1);
1637 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1639 if (dac33
->power_gpio
>= 0)
1640 gpio_free(dac33
->power_gpio
);
1646 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1648 struct tlv320dac33_priv
*dac33
= i2c_get_clientdata(client
);
1650 if (unlikely(dac33
->chip_power
))
1651 dac33_hard_power(dac33
->codec
, 0);
1653 if (dac33
->power_gpio
>= 0)
1654 gpio_free(dac33
->power_gpio
);
1656 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1658 snd_soc_unregister_codec(&client
->dev
);
1664 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1666 .name
= "tlv320dac33",
1672 static struct i2c_driver tlv320dac33_i2c_driver
= {
1674 .name
= "tlv320dac33-codec",
1675 .owner
= THIS_MODULE
,
1677 .probe
= dac33_i2c_probe
,
1678 .remove
= __devexit_p(dac33_i2c_remove
),
1679 .id_table
= tlv320dac33_i2c_id
,
1682 static int __init
dac33_module_init(void)
1685 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1687 printk(KERN_ERR
"DAC33: driver registration failed\n");
1692 module_init(dac33_module_init
);
1694 static void __exit
dac33_module_exit(void)
1696 i2c_del_driver(&tlv320dac33_i2c_driver
);
1698 module_exit(dac33_module_exit
);
1701 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1702 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1703 MODULE_LICENSE("GPL");