2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/soc-dapm.h>
40 #include <sound/initval.h>
41 #include <sound/tlv.h>
43 #include <sound/tlv320dac33-plat.h>
44 #include "tlv320dac33.h"
46 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
48 #define DAC33_BUFFER_SIZE_SAMPLES 6144
50 #define NSAMPLE_MAX 5700
52 #define LATENCY_TIME_MS 20
54 static struct snd_soc_codec
*tlv320dac33_codec
;
63 enum dac33_fifo_modes
{
64 DAC33_FIFO_BYPASS
= 0,
70 #define DAC33_NUM_SUPPLIES 3
71 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
77 struct tlv320dac33_priv
{
79 struct workqueue_struct
*dac33_wq
;
80 struct work_struct work
;
81 struct snd_soc_codec codec
;
82 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
88 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
89 unsigned int nsample_min
; /* nsample should not be lower than
91 unsigned int nsample_max
; /* nsample should not be higher than
93 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
94 unsigned int nsample
; /* burst read amount from host */
95 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
97 enum dac33_state state
;
100 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
101 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
102 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
103 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
104 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
105 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
106 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
107 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
108 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
109 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
110 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
111 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
112 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
113 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
114 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
115 0x00, 0x00, /* 0x38 - 0x39 */
116 /* Registers 0x3a - 0x3f are reserved */
117 0x00, 0x00, /* 0x3a - 0x3b */
118 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
120 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
121 0x00, 0x80, /* 0x44 - 0x45 */
122 /* Registers 0x46 - 0x47 are reserved */
123 0x80, 0x80, /* 0x46 - 0x47 */
125 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
126 /* Registers 0x4b - 0x7c are reserved */
128 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
129 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
130 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
131 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
132 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
133 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
134 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
135 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
136 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
137 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
138 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
139 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
142 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
145 /* Register read and write */
146 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
149 u8
*cache
= codec
->reg_cache
;
150 if (reg
>= DAC33_CACHEREGNUM
)
156 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
159 u8
*cache
= codec
->reg_cache
;
160 if (reg
>= DAC33_CACHEREGNUM
)
166 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
169 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
174 /* If powered off, return the cached value */
175 if (dac33
->chip_power
) {
176 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
178 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
179 value
[0] = dac33_read_reg_cache(codec
, reg
);
182 dac33_write_reg_cache(codec
, reg
, val
);
185 value
[0] = dac33_read_reg_cache(codec
, reg
);
191 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
194 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
200 * D15..D8 dac33 register offset
201 * D7...D0 register data
203 data
[0] = reg
& 0xff;
204 data
[1] = value
& 0xff;
206 dac33_write_reg_cache(codec
, data
[0], data
[1]);
207 if (dac33
->chip_power
) {
208 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
210 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
218 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
221 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
224 mutex_lock(&dac33
->mutex
);
225 ret
= dac33_write(codec
, reg
, value
);
226 mutex_unlock(&dac33
->mutex
);
231 #define DAC33_I2C_ADDR_AUTOINC 0x80
232 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
235 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
241 * D23..D16 dac33 register offset
242 * D15..D8 register data MSB
243 * D7...D0 register data LSB
245 data
[0] = reg
& 0xff;
246 data
[1] = (value
>> 8) & 0xff;
247 data
[2] = value
& 0xff;
249 dac33_write_reg_cache(codec
, data
[0], data
[1]);
250 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
252 if (dac33
->chip_power
) {
253 /* We need to set autoincrement mode for 16 bit writes */
254 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
255 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
257 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
265 static void dac33_restore_regs(struct snd_soc_codec
*codec
)
267 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
268 u8
*cache
= codec
->reg_cache
;
272 if (!dac33
->chip_power
)
275 for (i
= DAC33_PWR_CTRL
; i
<= DAC33_INTP_CTRL_B
; i
++) {
278 /* Skip the read only registers */
279 if ((i
>= DAC33_INT_OSC_STATUS
&&
280 i
<= DAC33_INT_OSC_FREQ_RAT_READ_B
) ||
281 (i
>= DAC33_FIFO_WPTR_MSB
&& i
<= DAC33_FIFO_IRQ_FLAG
) ||
282 i
== DAC33_DAC_STATUS_FLAGS
||
283 i
== DAC33_SRC_EST_REF_CLK_RATIO_A
||
284 i
== DAC33_SRC_EST_REF_CLK_RATIO_B
)
286 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
288 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
290 for (i
= DAC33_LDAC_PWR_CTRL
; i
<= DAC33_LINEL_TO_LLO_VOL
; i
++) {
293 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
295 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
297 for (i
= DAC33_LINER_TO_RLO_VOL
; i
<= DAC33_OSC_TRIM
; i
++) {
300 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
302 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
306 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
310 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
312 reg
|= DAC33_PDNALLB
;
314 reg
&= ~DAC33_PDNALLB
;
315 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
318 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
320 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
323 mutex_lock(&dac33
->mutex
);
325 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
329 "Failed to enable supplies: %d\n", ret
);
333 if (dac33
->power_gpio
>= 0)
334 gpio_set_value(dac33
->power_gpio
, 1);
336 dac33
->chip_power
= 1;
338 /* Restore registers */
339 dac33_restore_regs(codec
);
341 dac33_soft_power(codec
, 1);
343 dac33_soft_power(codec
, 0);
344 if (dac33
->power_gpio
>= 0)
345 gpio_set_value(dac33
->power_gpio
, 0);
347 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
351 "Failed to disable supplies: %d\n", ret
);
355 dac33
->chip_power
= 0;
359 mutex_unlock(&dac33
->mutex
);
363 static int dac33_get_nsample(struct snd_kcontrol
*kcontrol
,
364 struct snd_ctl_elem_value
*ucontrol
)
366 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
367 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
369 ucontrol
->value
.integer
.value
[0] = dac33
->nsample
;
374 static int dac33_set_nsample(struct snd_kcontrol
*kcontrol
,
375 struct snd_ctl_elem_value
*ucontrol
)
377 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
378 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
381 if (dac33
->nsample
== ucontrol
->value
.integer
.value
[0])
384 if (ucontrol
->value
.integer
.value
[0] < dac33
->nsample_min
||
385 ucontrol
->value
.integer
.value
[0] > dac33
->nsample_max
)
388 dac33
->nsample
= ucontrol
->value
.integer
.value
[0];
393 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
394 struct snd_ctl_elem_value
*ucontrol
)
396 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
397 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
399 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
404 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
405 struct snd_ctl_elem_value
*ucontrol
)
407 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
408 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
411 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
413 /* Do not allow changes while stream is running*/
417 if (ucontrol
->value
.integer
.value
[0] < 0 ||
418 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
421 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
426 /* Codec operation modes */
427 static const char *dac33_fifo_mode_texts
[] = {
428 "Bypass", "Mode 1", "Mode 7"
431 static const struct soc_enum dac33_fifo_mode_enum
=
432 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
433 dac33_fifo_mode_texts
);
436 * DACL/R digital volume control:
437 * from 0 dB to -63.5 in 0.5 dB steps
438 * Need to be inverted later on:
442 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
444 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
445 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
446 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
447 0, 0x7f, 1, dac_digivol_tlv
),
448 SOC_DOUBLE_R("DAC Digital Playback Switch",
449 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
450 SOC_DOUBLE_R("Line to Line Out Volume",
451 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
454 static const struct snd_kcontrol_new dac33_nsample_snd_controls
[] = {
455 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
456 dac33_get_nsample
, dac33_set_nsample
),
457 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
458 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
462 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
463 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
465 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
466 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
468 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
469 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
470 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
472 SND_SOC_DAPM_INPUT("LINEL"),
473 SND_SOC_DAPM_INPUT("LINER"),
475 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL
, 2, 0),
476 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL
, 2, 0),
479 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
480 &dac33_dapm_abypassl_control
),
481 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
482 &dac33_dapm_abypassr_control
),
484 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amp Power",
485 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
486 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amp Power",
487 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
490 static const struct snd_soc_dapm_route audio_map
[] = {
492 {"Analog Left Bypass", "Switch", "LINEL"},
493 {"Analog Right Bypass", "Switch", "LINER"},
495 {"Output Left Amp Power", NULL
, "DACL"},
496 {"Output Right Amp Power", NULL
, "DACR"},
498 {"Output Left Amp Power", NULL
, "Analog Left Bypass"},
499 {"Output Right Amp Power", NULL
, "Analog Right Bypass"},
502 {"LEFT_LO", NULL
, "Output Left Amp Power"},
503 {"RIGHT_LO", NULL
, "Output Right Amp Power"},
506 static int dac33_add_widgets(struct snd_soc_codec
*codec
)
508 snd_soc_dapm_new_controls(codec
, dac33_dapm_widgets
,
509 ARRAY_SIZE(dac33_dapm_widgets
));
511 /* set up audio path interconnects */
512 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
517 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
518 enum snd_soc_bias_level level
)
523 case SND_SOC_BIAS_ON
:
524 dac33_soft_power(codec
, 1);
526 case SND_SOC_BIAS_PREPARE
:
528 case SND_SOC_BIAS_STANDBY
:
529 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
530 ret
= dac33_hard_power(codec
, 1);
535 dac33_soft_power(codec
, 0);
537 case SND_SOC_BIAS_OFF
:
538 ret
= dac33_hard_power(codec
, 0);
544 codec
->bias_level
= level
;
549 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
551 struct snd_soc_codec
*codec
;
553 codec
= &dac33
->codec
;
555 switch (dac33
->fifo_mode
) {
556 case DAC33_FIFO_MODE1
:
557 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
558 DAC33_THRREG(dac33
->nsample
));
559 dac33_write16(codec
, DAC33_PREFILL_MSB
,
560 DAC33_THRREG(dac33
->alarm_threshold
));
562 case DAC33_FIFO_MODE7
:
563 dac33_write16(codec
, DAC33_PREFILL_MSB
,
567 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
573 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
575 struct snd_soc_codec
*codec
;
577 codec
= &dac33
->codec
;
579 switch (dac33
->fifo_mode
) {
580 case DAC33_FIFO_MODE1
:
581 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
582 DAC33_THRREG(dac33
->nsample
));
584 case DAC33_FIFO_MODE7
:
585 /* At the moment we are not using interrupts in mode7 */
588 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
594 static void dac33_work(struct work_struct
*work
)
596 struct snd_soc_codec
*codec
;
597 struct tlv320dac33_priv
*dac33
;
600 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
601 codec
= &dac33
->codec
;
603 mutex_lock(&dac33
->mutex
);
604 switch (dac33
->state
) {
606 dac33
->state
= DAC33_PLAYBACK
;
607 dac33_prefill_handler(dac33
);
610 dac33_playback_handler(dac33
);
615 dac33
->state
= DAC33_IDLE
;
616 /* Mask all interrupts from dac33 */
617 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
620 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
621 reg
|= DAC33_FIFOFLUSH
;
622 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
625 mutex_unlock(&dac33
->mutex
);
628 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
630 struct snd_soc_codec
*codec
= dev
;
631 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
633 queue_work(dac33
->dac33_wq
, &dac33
->work
);
638 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
639 struct snd_soc_dai
*dai
)
641 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
642 struct snd_soc_device
*socdev
= rtd
->socdev
;
643 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
644 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
645 unsigned int pwr_ctrl
;
647 /* Stop pending workqueue */
648 if (dac33
->fifo_mode
)
649 cancel_work_sync(&dac33
->work
);
651 mutex_lock(&dac33
->mutex
);
652 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
653 pwr_ctrl
&= ~(DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
);
654 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
655 mutex_unlock(&dac33
->mutex
);
658 static void dac33_oscwait(struct snd_soc_codec
*codec
)
665 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
666 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
667 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
669 "internal oscillator calibration failed\n");
672 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
673 struct snd_pcm_hw_params
*params
,
674 struct snd_soc_dai
*dai
)
676 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
677 struct snd_soc_device
*socdev
= rtd
->socdev
;
678 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
680 /* Check parameters for validity */
681 switch (params_rate(params
)) {
686 dev_err(codec
->dev
, "unsupported rate %d\n",
687 params_rate(params
));
691 switch (params_format(params
)) {
692 case SNDRV_PCM_FORMAT_S16_LE
:
695 dev_err(codec
->dev
, "unsupported format %d\n",
696 params_format(params
));
703 #define CALC_OSCSET(rate, refclk) ( \
704 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
705 #define CALC_RATIOSET(rate, refclk) ( \
706 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
709 * tlv320dac33 is strict on the sequence of the register writes, if the register
710 * writes happens in different order, than dac33 might end up in unknown state.
711 * Use the known, working sequence of register writes to initialize the dac33.
713 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
715 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
716 struct snd_soc_device
*socdev
= rtd
->socdev
;
717 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
718 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
719 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
720 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
722 switch (substream
->runtime
->rate
) {
725 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
726 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
730 dev_err(codec
->dev
, "unsupported rate %d\n",
731 substream
->runtime
->rate
);
736 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
737 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
738 /* Read FIFO control A, and clear FIFO flush bit */
739 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
740 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
742 fifoctrl_a
&= ~DAC33_WIDTH
;
743 switch (substream
->runtime
->format
) {
744 case SNDRV_PCM_FORMAT_S16_LE
:
745 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
746 fifoctrl_a
|= DAC33_WIDTH
;
749 dev_err(codec
->dev
, "unsupported format %d\n",
750 substream
->runtime
->format
);
754 mutex_lock(&dac33
->mutex
);
755 dac33_soft_power(codec
, 1);
757 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
758 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
760 /* Write registers 0x08 and 0x09 (MSB, LSB) */
761 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
763 /* calib time: 128 is a nice number ;) */
764 dac33_write(codec
, DAC33_CALIB_TIME
, 128);
766 /* adjustment treshold & step */
767 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
770 /* div=4 / gain=1 / div */
771 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
773 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
774 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
775 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
777 dac33_oscwait(codec
);
779 if (dac33
->fifo_mode
) {
780 /* Generic for all FIFO modes */
781 /* 50-51 : ASRC Control registers */
782 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCLKDIV(1));
783 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
785 /* Write registers 0x34 and 0x35 (MSB, LSB) */
786 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
788 /* Set interrupts to high active */
789 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
791 /* FIFO bypass mode */
792 /* 50-51 : ASRC Control registers */
793 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
794 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
797 /* Interrupt behaviour configuration */
798 switch (dac33
->fifo_mode
) {
799 case DAC33_FIFO_MODE1
:
800 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
801 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
802 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
804 case DAC33_FIFO_MODE7
:
805 /* Disable all interrupts */
806 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
809 /* in FIFO bypass mode, the interrupts are not used */
813 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
815 switch (dac33
->fifo_mode
) {
816 case DAC33_FIFO_MODE1
:
819 * Disable the FIFO bypass (Enable the use of FIFO)
820 * Select nSample mode
821 * BCLK is only running when data is needed by DAC33
823 fifoctrl_a
&= ~DAC33_FBYPAS
;
824 fifoctrl_a
&= ~DAC33_FAUTO
;
825 aictrl_b
&= ~DAC33_BCLKON
;
827 case DAC33_FIFO_MODE7
:
830 * Disable the FIFO bypass (Enable the use of FIFO)
831 * Select Threshold mode
832 * BCLK is only running when data is needed by DAC33
834 fifoctrl_a
&= ~DAC33_FBYPAS
;
835 fifoctrl_a
|= DAC33_FAUTO
;
836 aictrl_b
&= ~DAC33_BCLKON
;
840 * For FIFO bypass mode:
841 * Enable the FIFO bypass (Disable the FIFO use)
842 * Set the BCLK as continous
844 fifoctrl_a
|= DAC33_FBYPAS
;
845 aictrl_b
|= DAC33_BCLKON
;
849 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
850 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
851 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
862 if (dac33
->fifo_mode
)
863 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
864 dac33
->burst_bclkdiv
);
866 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
868 switch (dac33
->fifo_mode
) {
869 case DAC33_FIFO_MODE1
:
870 dac33_write16(codec
, DAC33_ATHR_MSB
,
871 DAC33_THRREG(dac33
->alarm_threshold
));
873 case DAC33_FIFO_MODE7
:
875 * Configure the threshold levels, and leave 10 sample space
876 * at the bottom, and also at the top of the FIFO
878 dac33_write16(codec
, DAC33_UTHR_MSB
,
879 DAC33_THRREG(DAC33_BUFFER_SIZE_SAMPLES
- 10));
880 dac33_write16(codec
, DAC33_LTHR_MSB
,
887 mutex_unlock(&dac33
->mutex
);
892 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
894 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
895 struct snd_soc_device
*socdev
= rtd
->socdev
;
896 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
897 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
898 unsigned int nsample_limit
;
900 /* Number of samples (16bit, stereo) in one period */
901 dac33
->nsample_min
= snd_pcm_lib_period_bytes(substream
) / 4;
903 /* Number of samples (16bit, stereo) in ALSA buffer */
904 dac33
->nsample_max
= snd_pcm_lib_buffer_bytes(substream
) / 4;
905 /* Subtract one period from the total */
906 dac33
->nsample_max
-= dac33
->nsample_min
;
908 /* Number of samples for LATENCY_TIME_MS / 2 */
909 dac33
->alarm_threshold
= substream
->runtime
->rate
/
910 (1000 / (LATENCY_TIME_MS
/ 2));
912 /* Find and fix up the lowest nsmaple limit */
913 nsample_limit
= substream
->runtime
->rate
/ (1000 / LATENCY_TIME_MS
);
915 if (dac33
->nsample_min
< nsample_limit
)
916 dac33
->nsample_min
= nsample_limit
;
918 if (dac33
->nsample
< dac33
->nsample_min
)
919 dac33
->nsample
= dac33
->nsample_min
;
922 * Find and fix up the highest nsmaple limit
923 * In order to not overflow the DAC33 buffer substract the
924 * alarm_threshold value from the size of the DAC33 buffer
926 nsample_limit
= DAC33_BUFFER_SIZE_SAMPLES
- dac33
->alarm_threshold
;
928 if (dac33
->nsample_max
> nsample_limit
)
929 dac33
->nsample_max
= nsample_limit
;
931 if (dac33
->nsample
> dac33
->nsample_max
)
932 dac33
->nsample
= dac33
->nsample_max
;
935 static int dac33_pcm_prepare(struct snd_pcm_substream
*substream
,
936 struct snd_soc_dai
*dai
)
938 dac33_calculate_times(substream
);
939 dac33_prepare_chip(substream
);
944 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
945 struct snd_soc_dai
*dai
)
947 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
948 struct snd_soc_device
*socdev
= rtd
->socdev
;
949 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
950 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
954 case SNDRV_PCM_TRIGGER_START
:
955 case SNDRV_PCM_TRIGGER_RESUME
:
956 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
957 if (dac33
->fifo_mode
) {
958 dac33
->state
= DAC33_PREFILL
;
959 queue_work(dac33
->dac33_wq
, &dac33
->work
);
962 case SNDRV_PCM_TRIGGER_STOP
:
963 case SNDRV_PCM_TRIGGER_SUSPEND
:
964 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
965 if (dac33
->fifo_mode
) {
966 dac33
->state
= DAC33_FLUSH
;
967 queue_work(dac33
->dac33_wq
, &dac33
->work
);
977 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
978 int clk_id
, unsigned int freq
, int dir
)
980 struct snd_soc_codec
*codec
= codec_dai
->codec
;
981 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
982 u8 ioc_reg
, asrcb_reg
;
984 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
985 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
987 case TLV320DAC33_MCLK
:
988 ioc_reg
|= DAC33_REFSEL
;
989 asrcb_reg
|= DAC33_SRCREFSEL
;
991 case TLV320DAC33_SLEEPCLK
:
992 ioc_reg
&= ~DAC33_REFSEL
;
993 asrcb_reg
&= ~DAC33_SRCREFSEL
;
996 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
999 dac33
->refclk
= freq
;
1001 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1002 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1007 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1010 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1011 struct tlv320dac33_priv
*dac33
= codec
->private_data
;
1012 u8 aictrl_a
, aictrl_b
;
1014 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1015 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1016 /* set master/slave audio interface */
1017 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1018 case SND_SOC_DAIFMT_CBM_CFM
:
1020 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1022 case SND_SOC_DAIFMT_CBS_CFS
:
1024 if (dac33
->fifo_mode
) {
1025 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1028 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1034 aictrl_a
&= ~DAC33_AFMT_MASK
;
1035 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1036 case SND_SOC_DAIFMT_I2S
:
1037 aictrl_a
|= DAC33_AFMT_I2S
;
1039 case SND_SOC_DAIFMT_DSP_A
:
1040 aictrl_a
|= DAC33_AFMT_DSP
;
1041 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1042 aictrl_b
|= DAC33_DATA_DELAY(0);
1044 case SND_SOC_DAIFMT_RIGHT_J
:
1045 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1047 case SND_SOC_DAIFMT_LEFT_J
:
1048 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1051 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1052 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1056 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1057 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1062 static void dac33_init_chip(struct snd_soc_codec
*codec
)
1064 /* 44-46: DAC Control Registers */
1065 /* A : DAC sample rate Fsref/1.5 */
1066 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(0));
1067 /* B : DAC src=normal, not muted */
1068 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
1069 DAC33_DACSRCL_LEFT
);
1070 /* C : (defaults) */
1071 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
1073 /* 64-65 : L&R DAC power control
1074 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1075 dac33_write(codec
, DAC33_LDAC_PWR_CTRL
, DAC33_LROUT_GAIN(2));
1076 dac33_write(codec
, DAC33_RDAC_PWR_CTRL
, DAC33_LROUT_GAIN(2));
1078 /* 73 : volume soft stepping control,
1079 clock source = internal osc (?) */
1080 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
1082 /* 66 : LOP/LOM Modes */
1083 dac33_write(codec
, DAC33_OUT_AMP_CM_CTRL
, 0xff);
1085 /* 68 : LOM inverted from LOP */
1086 dac33_write(codec
, DAC33_OUT_AMP_CTRL
, (3<<2));
1088 dac33_write(codec
, DAC33_PWR_CTRL
, DAC33_PDNALLB
);
1091 static int dac33_soc_probe(struct platform_device
*pdev
)
1093 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1094 struct snd_soc_codec
*codec
;
1095 struct tlv320dac33_priv
*dac33
;
1098 BUG_ON(!tlv320dac33_codec
);
1100 codec
= tlv320dac33_codec
;
1101 socdev
->card
->codec
= codec
;
1102 dac33
= codec
->private_data
;
1104 /* Power up the codec */
1105 dac33_hard_power(codec
, 1);
1106 /* Set default configuration */
1107 dac33_init_chip(codec
);
1110 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1112 dev_err(codec
->dev
, "failed to create pcms\n");
1116 snd_soc_add_controls(codec
, dac33_snd_controls
,
1117 ARRAY_SIZE(dac33_snd_controls
));
1118 /* Only add the nSample controls, if we have valid IRQ number */
1119 if (dac33
->irq
>= 0)
1120 snd_soc_add_controls(codec
, dac33_nsample_snd_controls
,
1121 ARRAY_SIZE(dac33_nsample_snd_controls
));
1123 dac33_add_widgets(codec
);
1125 /* power on device */
1126 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1128 /* Bias level configuration has enabled regulator an extra time */
1129 regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1134 dac33_hard_power(codec
, 0);
1138 static int dac33_soc_remove(struct platform_device
*pdev
)
1140 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1141 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1143 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1145 snd_soc_free_pcms(socdev
);
1146 snd_soc_dapm_free(socdev
);
1151 static int dac33_soc_suspend(struct platform_device
*pdev
, pm_message_t state
)
1153 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1154 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1156 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1161 static int dac33_soc_resume(struct platform_device
*pdev
)
1163 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1164 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1166 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1167 dac33_set_bias_level(codec
, codec
->suspend_bias_level
);
1172 struct snd_soc_codec_device soc_codec_dev_tlv320dac33
= {
1173 .probe
= dac33_soc_probe
,
1174 .remove
= dac33_soc_remove
,
1175 .suspend
= dac33_soc_suspend
,
1176 .resume
= dac33_soc_resume
,
1178 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33
);
1180 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1181 SNDRV_PCM_RATE_48000)
1182 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1184 static struct snd_soc_dai_ops dac33_dai_ops
= {
1185 .shutdown
= dac33_shutdown
,
1186 .hw_params
= dac33_hw_params
,
1187 .prepare
= dac33_pcm_prepare
,
1188 .trigger
= dac33_pcm_trigger
,
1189 .set_sysclk
= dac33_set_dai_sysclk
,
1190 .set_fmt
= dac33_set_dai_fmt
,
1193 struct snd_soc_dai dac33_dai
= {
1194 .name
= "tlv320dac33",
1196 .stream_name
= "Playback",
1199 .rates
= DAC33_RATES
,
1200 .formats
= DAC33_FORMATS
,},
1201 .ops
= &dac33_dai_ops
,
1203 EXPORT_SYMBOL_GPL(dac33_dai
);
1205 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1206 const struct i2c_device_id
*id
)
1208 struct tlv320dac33_platform_data
*pdata
;
1209 struct tlv320dac33_priv
*dac33
;
1210 struct snd_soc_codec
*codec
;
1213 if (client
->dev
.platform_data
== NULL
) {
1214 dev_err(&client
->dev
, "Platform data not set\n");
1217 pdata
= client
->dev
.platform_data
;
1219 dac33
= kzalloc(sizeof(struct tlv320dac33_priv
), GFP_KERNEL
);
1223 codec
= &dac33
->codec
;
1224 codec
->private_data
= dac33
;
1225 codec
->control_data
= client
;
1227 mutex_init(&codec
->mutex
);
1228 mutex_init(&dac33
->mutex
);
1229 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1230 INIT_LIST_HEAD(&codec
->dapm_paths
);
1232 codec
->name
= "tlv320dac33";
1233 codec
->owner
= THIS_MODULE
;
1234 codec
->read
= dac33_read_reg_cache
;
1235 codec
->write
= dac33_write_locked
;
1236 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1237 codec
->bias_level
= SND_SOC_BIAS_OFF
;
1238 codec
->set_bias_level
= dac33_set_bias_level
;
1239 codec
->dai
= &dac33_dai
;
1241 codec
->reg_cache_size
= ARRAY_SIZE(dac33_reg
);
1242 codec
->reg_cache
= kmemdup(dac33_reg
, ARRAY_SIZE(dac33_reg
),
1244 if (codec
->reg_cache
== NULL
) {
1249 i2c_set_clientdata(client
, dac33
);
1251 dac33
->power_gpio
= pdata
->power_gpio
;
1252 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1253 dac33
->irq
= client
->irq
;
1254 dac33
->nsample
= NSAMPLE_MAX
;
1255 /* Disable FIFO use by default */
1256 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1258 tlv320dac33_codec
= codec
;
1260 codec
->dev
= &client
->dev
;
1261 dac33_dai
.dev
= codec
->dev
;
1263 /* Check if the reset GPIO number is valid and request it */
1264 if (dac33
->power_gpio
>= 0) {
1265 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1268 "Failed to request reset GPIO (%d)\n",
1270 snd_soc_unregister_dai(&dac33_dai
);
1271 snd_soc_unregister_codec(codec
);
1274 gpio_direction_output(dac33
->power_gpio
, 0);
1276 dac33
->chip_power
= 1;
1279 /* Check if the IRQ number is valid and request it */
1280 if (dac33
->irq
>= 0) {
1281 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1282 IRQF_TRIGGER_RISING
| IRQF_DISABLED
,
1283 codec
->name
, codec
);
1285 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1289 if (dac33
->irq
!= -1) {
1290 /* Setup work queue */
1292 create_singlethread_workqueue("tlv320dac33");
1293 if (dac33
->dac33_wq
== NULL
) {
1294 free_irq(dac33
->irq
, &dac33
->codec
);
1299 INIT_WORK(&dac33
->work
, dac33_work
);
1303 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1304 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1306 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(dac33
->supplies
),
1310 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
1314 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
1317 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
1321 ret
= snd_soc_register_codec(codec
);
1323 dev_err(codec
->dev
, "Failed to register codec: %d\n", ret
);
1327 ret
= snd_soc_register_dai(&dac33_dai
);
1329 dev_err(codec
->dev
, "Failed to register DAI: %d\n", ret
);
1330 snd_soc_unregister_codec(codec
);
1334 /* Shut down the codec for now */
1335 dac33_hard_power(codec
, 0);
1340 regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1342 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1344 if (dac33
->irq
>= 0) {
1345 free_irq(dac33
->irq
, &dac33
->codec
);
1346 destroy_workqueue(dac33
->dac33_wq
);
1349 if (dac33
->power_gpio
>= 0)
1350 gpio_free(dac33
->power_gpio
);
1352 kfree(codec
->reg_cache
);
1354 tlv320dac33_codec
= NULL
;
1360 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1362 struct tlv320dac33_priv
*dac33
;
1364 dac33
= i2c_get_clientdata(client
);
1365 dac33_hard_power(&dac33
->codec
, 0);
1367 if (dac33
->power_gpio
>= 0)
1368 gpio_free(dac33
->power_gpio
);
1369 if (dac33
->irq
>= 0)
1370 free_irq(dac33
->irq
, &dac33
->codec
);
1372 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1374 destroy_workqueue(dac33
->dac33_wq
);
1375 snd_soc_unregister_dai(&dac33_dai
);
1376 snd_soc_unregister_codec(&dac33
->codec
);
1377 kfree(dac33
->codec
.reg_cache
);
1379 tlv320dac33_codec
= NULL
;
1384 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1386 .name
= "tlv320dac33",
1392 static struct i2c_driver tlv320dac33_i2c_driver
= {
1394 .name
= "tlv320dac33",
1395 .owner
= THIS_MODULE
,
1397 .probe
= dac33_i2c_probe
,
1398 .remove
= __devexit_p(dac33_i2c_remove
),
1399 .id_table
= tlv320dac33_i2c_id
,
1402 static int __init
dac33_module_init(void)
1405 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1407 printk(KERN_ERR
"DAC33: driver registration failed\n");
1412 module_init(dac33_module_init
);
1414 static void __exit
dac33_module_exit(void)
1416 i2c_del_driver(&tlv320dac33_i2c_driver
);
1418 module_exit(dac33_module_exit
);
1421 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1422 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1423 MODULE_LICENSE("GPL");