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[mirror_ubuntu-zesty-kernel.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x91, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
119 };
120
121 /* codec private data */
122 struct twl4030_priv {
123 struct snd_soc_codec codec;
124
125 unsigned int codec_powered;
126 unsigned int apll_enabled;
127
128 struct snd_pcm_substream *master_substream;
129 struct snd_pcm_substream *slave_substream;
130
131 unsigned int configured;
132 unsigned int rate;
133 unsigned int sample_bits;
134 unsigned int channels;
135
136 unsigned int sysclk;
137
138 /* Headset output state handling */
139 unsigned int hsl_enabled;
140 unsigned int hsr_enabled;
141 };
142
143 /*
144 * read twl4030 register cache
145 */
146 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
147 unsigned int reg)
148 {
149 u8 *cache = codec->reg_cache;
150
151 if (reg >= TWL4030_CACHEREGNUM)
152 return -EIO;
153
154 return cache[reg];
155 }
156
157 /*
158 * write twl4030 register cache
159 */
160 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
161 u8 reg, u8 value)
162 {
163 u8 *cache = codec->reg_cache;
164
165 if (reg >= TWL4030_CACHEREGNUM)
166 return;
167 cache[reg] = value;
168 }
169
170 /*
171 * write to the twl4030 register space
172 */
173 static int twl4030_write(struct snd_soc_codec *codec,
174 unsigned int reg, unsigned int value)
175 {
176 twl4030_write_reg_cache(codec, reg, value);
177 if (likely(reg < TWL4030_REG_SW_SHADOW))
178 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
179 reg);
180 else
181 return 0;
182 }
183
184 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
185 {
186 struct twl4030_priv *twl4030 = codec->private_data;
187 int mode;
188
189 if (enable == twl4030->codec_powered)
190 return;
191
192 if (enable)
193 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
194 else
195 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
196
197 if (mode >= 0) {
198 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
199 twl4030->codec_powered = enable;
200 }
201
202 /* REVISIT: this delay is present in TI sample drivers */
203 /* but there seems to be no TRM requirement for it */
204 udelay(10);
205 }
206
207 static void twl4030_init_chip(struct snd_soc_codec *codec)
208 {
209 u8 *cache = codec->reg_cache;
210 int i;
211
212 /* clear CODECPDZ prior to setting register defaults */
213 twl4030_codec_enable(codec, 0);
214
215 /* set all audio section registers to reasonable defaults */
216 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
217 twl4030_write(codec, i, cache[i]);
218
219 }
220
221 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
222 {
223 struct twl4030_priv *twl4030 = codec->private_data;
224 int status;
225
226 if (enable == twl4030->apll_enabled)
227 return;
228
229 if (enable)
230 /* Enable PLL */
231 status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
232 else
233 /* Disable PLL */
234 status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
235
236 if (status >= 0)
237 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
238
239 twl4030->apll_enabled = enable;
240 }
241
242 static void twl4030_power_up(struct snd_soc_codec *codec)
243 {
244 struct twl4030_priv *twl4030 = codec->private_data;
245 u8 anamicl, regmisc1, byte;
246 int i = 0;
247
248 if (twl4030->codec_powered)
249 return;
250
251 /* set CODECPDZ to turn on codec */
252 twl4030_codec_enable(codec, 1);
253
254 /* initiate offset cancellation */
255 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
256 twl4030_write(codec, TWL4030_REG_ANAMICL,
257 anamicl | TWL4030_CNCL_OFFSET_START);
258
259 /* wait for offset cancellation to complete */
260 do {
261 /* this takes a little while, so don't slam i2c */
262 udelay(2000);
263 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
264 TWL4030_REG_ANAMICL);
265 } while ((i++ < 100) &&
266 ((byte & TWL4030_CNCL_OFFSET_START) ==
267 TWL4030_CNCL_OFFSET_START));
268
269 /* Make sure that the reg_cache has the same value as the HW */
270 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
271
272 /* anti-pop when changing analog gain */
273 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
274 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
275 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
276
277 /* toggle CODECPDZ as per TRM */
278 twl4030_codec_enable(codec, 0);
279 twl4030_codec_enable(codec, 1);
280 }
281
282 /*
283 * Unconditional power down
284 */
285 static void twl4030_power_down(struct snd_soc_codec *codec)
286 {
287 /* power down */
288 twl4030_codec_enable(codec, 0);
289 }
290
291 /* Earpiece */
292 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
293 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
294 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
295 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
296 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
297 };
298
299 /* PreDrive Left */
300 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
301 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
302 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
303 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
304 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
305 };
306
307 /* PreDrive Right */
308 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
309 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
310 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
311 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
312 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
313 };
314
315 /* Headset Left */
316 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
317 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
318 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
319 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
320 };
321
322 /* Headset Right */
323 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
324 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
325 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
326 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
327 };
328
329 /* Carkit Left */
330 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
331 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
332 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
333 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
334 };
335
336 /* Carkit Right */
337 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
338 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
340 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
341 };
342
343 /* Handsfree Left */
344 static const char *twl4030_handsfreel_texts[] =
345 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
346
347 static const struct soc_enum twl4030_handsfreel_enum =
348 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
349 ARRAY_SIZE(twl4030_handsfreel_texts),
350 twl4030_handsfreel_texts);
351
352 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
353 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
354
355 /* Handsfree Left virtual mute */
356 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
357 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
358
359 /* Handsfree Right */
360 static const char *twl4030_handsfreer_texts[] =
361 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
362
363 static const struct soc_enum twl4030_handsfreer_enum =
364 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
365 ARRAY_SIZE(twl4030_handsfreer_texts),
366 twl4030_handsfreer_texts);
367
368 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
369 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
370
371 /* Handsfree Right virtual mute */
372 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
373 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
374
375 /* Vibra */
376 /* Vibra audio path selection */
377 static const char *twl4030_vibra_texts[] =
378 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
379
380 static const struct soc_enum twl4030_vibra_enum =
381 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
382 ARRAY_SIZE(twl4030_vibra_texts),
383 twl4030_vibra_texts);
384
385 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
386 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
387
388 /* Vibra path selection: local vibrator (PWM) or audio driven */
389 static const char *twl4030_vibrapath_texts[] =
390 {"Local vibrator", "Audio"};
391
392 static const struct soc_enum twl4030_vibrapath_enum =
393 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
394 ARRAY_SIZE(twl4030_vibrapath_texts),
395 twl4030_vibrapath_texts);
396
397 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
398 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
399
400 /* Left analog microphone selection */
401 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
402 SOC_DAPM_SINGLE("Main Mic Capture Switch",
403 TWL4030_REG_ANAMICL, 0, 1, 0),
404 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
405 TWL4030_REG_ANAMICL, 1, 1, 0),
406 SOC_DAPM_SINGLE("AUXL Capture Switch",
407 TWL4030_REG_ANAMICL, 2, 1, 0),
408 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
409 TWL4030_REG_ANAMICL, 3, 1, 0),
410 };
411
412 /* Right analog microphone selection */
413 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
414 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
415 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
416 };
417
418 /* TX1 L/R Analog/Digital microphone selection */
419 static const char *twl4030_micpathtx1_texts[] =
420 {"Analog", "Digimic0"};
421
422 static const struct soc_enum twl4030_micpathtx1_enum =
423 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
424 ARRAY_SIZE(twl4030_micpathtx1_texts),
425 twl4030_micpathtx1_texts);
426
427 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
428 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
429
430 /* TX2 L/R Analog/Digital microphone selection */
431 static const char *twl4030_micpathtx2_texts[] =
432 {"Analog", "Digimic1"};
433
434 static const struct soc_enum twl4030_micpathtx2_enum =
435 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
436 ARRAY_SIZE(twl4030_micpathtx2_texts),
437 twl4030_micpathtx2_texts);
438
439 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
440 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
441
442 /* Analog bypass for AudioR1 */
443 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
444 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
445
446 /* Analog bypass for AudioL1 */
447 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
448 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
449
450 /* Analog bypass for AudioR2 */
451 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
452 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
453
454 /* Analog bypass for AudioL2 */
455 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
456 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
457
458 /* Analog bypass for Voice */
459 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
460 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
461
462 /* Digital bypass gain, 0 mutes the bypass */
463 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
464 TLV_DB_RANGE_HEAD(2),
465 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
466 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
467 };
468
469 /* Digital bypass left (TX1L -> RX2L) */
470 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
471 SOC_DAPM_SINGLE_TLV("Volume",
472 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
473 twl4030_dapm_dbypass_tlv);
474
475 /* Digital bypass right (TX1R -> RX2R) */
476 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
477 SOC_DAPM_SINGLE_TLV("Volume",
478 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
479 twl4030_dapm_dbypass_tlv);
480
481 /*
482 * Voice Sidetone GAIN volume control:
483 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
484 */
485 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
486
487 /* Digital bypass voice: sidetone (VUL -> VDL)*/
488 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
489 SOC_DAPM_SINGLE_TLV("Volume",
490 TWL4030_REG_VSTPGA, 0, 0x29, 0,
491 twl4030_dapm_dbypassv_tlv);
492
493 static int micpath_event(struct snd_soc_dapm_widget *w,
494 struct snd_kcontrol *kcontrol, int event)
495 {
496 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
497 unsigned char adcmicsel, micbias_ctl;
498
499 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
500 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
501 /* Prepare the bits for the given TX path:
502 * shift_l == 0: TX1 microphone path
503 * shift_l == 2: TX2 microphone path */
504 if (e->shift_l) {
505 /* TX2 microphone path */
506 if (adcmicsel & TWL4030_TX2IN_SEL)
507 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
508 else
509 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
510 } else {
511 /* TX1 microphone path */
512 if (adcmicsel & TWL4030_TX1IN_SEL)
513 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
514 else
515 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
516 }
517
518 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
519
520 return 0;
521 }
522
523 /*
524 * Output PGA builder:
525 * Handle the muting and unmuting of the given output (turning off the
526 * amplifier associated with the output pin)
527 * On mute bypass the reg_cache and mute the volume
528 * On unmute: restore the register content
529 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
530 */
531 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
532 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
533 struct snd_kcontrol *kcontrol, int event) \
534 { \
535 u8 reg_val; \
536 \
537 switch (event) { \
538 case SND_SOC_DAPM_POST_PMU: \
539 twl4030_write(w->codec, reg, \
540 twl4030_read_reg_cache(w->codec, reg)); \
541 break; \
542 case SND_SOC_DAPM_POST_PMD: \
543 reg_val = twl4030_read_reg_cache(w->codec, reg); \
544 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
545 reg_val & (~mask), \
546 reg); \
547 break; \
548 } \
549 return 0; \
550 }
551
552 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
553 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
554 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
555 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
556 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
557
558 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
559 {
560 unsigned char hs_ctl;
561
562 hs_ctl = twl4030_read_reg_cache(codec, reg);
563
564 if (ramp) {
565 /* HF ramp-up */
566 hs_ctl |= TWL4030_HF_CTL_REF_EN;
567 twl4030_write(codec, reg, hs_ctl);
568 udelay(10);
569 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
570 twl4030_write(codec, reg, hs_ctl);
571 udelay(40);
572 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
573 hs_ctl |= TWL4030_HF_CTL_HB_EN;
574 twl4030_write(codec, reg, hs_ctl);
575 } else {
576 /* HF ramp-down */
577 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
578 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
579 twl4030_write(codec, reg, hs_ctl);
580 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
581 twl4030_write(codec, reg, hs_ctl);
582 udelay(40);
583 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
584 twl4030_write(codec, reg, hs_ctl);
585 }
586 }
587
588 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
589 struct snd_kcontrol *kcontrol, int event)
590 {
591 switch (event) {
592 case SND_SOC_DAPM_POST_PMU:
593 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
594 break;
595 case SND_SOC_DAPM_POST_PMD:
596 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
597 break;
598 }
599 return 0;
600 }
601
602 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
603 struct snd_kcontrol *kcontrol, int event)
604 {
605 switch (event) {
606 case SND_SOC_DAPM_POST_PMU:
607 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
608 break;
609 case SND_SOC_DAPM_POST_PMD:
610 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
611 break;
612 }
613 return 0;
614 }
615
616 static int vibramux_event(struct snd_soc_dapm_widget *w,
617 struct snd_kcontrol *kcontrol, int event)
618 {
619 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
620 return 0;
621 }
622
623 static int apll_event(struct snd_soc_dapm_widget *w,
624 struct snd_kcontrol *kcontrol, int event)
625 {
626 switch (event) {
627 case SND_SOC_DAPM_PRE_PMU:
628 twl4030_apll_enable(w->codec, 1);
629 break;
630 case SND_SOC_DAPM_POST_PMD:
631 twl4030_apll_enable(w->codec, 0);
632 break;
633 }
634 return 0;
635 }
636
637 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
638 {
639 struct snd_soc_device *socdev = codec->socdev;
640 struct twl4030_setup_data *setup = socdev->codec_data;
641
642 unsigned char hs_gain, hs_pop;
643 struct twl4030_priv *twl4030 = codec->private_data;
644 /* Base values for ramp delay calculation: 2^19 - 2^26 */
645 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
646 8388608, 16777216, 33554432, 67108864};
647
648 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
649 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
650
651 /* Enable external mute control, this dramatically reduces
652 * the pop-noise */
653 if (setup && setup->hs_extmute) {
654 if (setup->set_hs_extmute) {
655 setup->set_hs_extmute(1);
656 } else {
657 hs_pop |= TWL4030_EXTMUTE;
658 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
659 }
660 }
661
662 if (ramp) {
663 /* Headset ramp-up according to the TRM */
664 hs_pop |= TWL4030_VMID_EN;
665 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
666 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
667 hs_pop |= TWL4030_RAMP_EN;
668 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
669 /* Wait ramp delay time + 1, so the VMID can settle */
670 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
671 twl4030->sysclk) + 1);
672 } else {
673 /* Headset ramp-down _not_ according to
674 * the TRM, but in a way that it is working */
675 hs_pop &= ~TWL4030_RAMP_EN;
676 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
677 /* Wait ramp delay time + 1, so the VMID can settle */
678 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
679 twl4030->sysclk) + 1);
680 /* Bypass the reg_cache to mute the headset */
681 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
682 hs_gain & (~0x0f),
683 TWL4030_REG_HS_GAIN_SET);
684
685 hs_pop &= ~TWL4030_VMID_EN;
686 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
687 }
688
689 /* Disable external mute */
690 if (setup && setup->hs_extmute) {
691 if (setup->set_hs_extmute) {
692 setup->set_hs_extmute(0);
693 } else {
694 hs_pop &= ~TWL4030_EXTMUTE;
695 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
696 }
697 }
698 }
699
700 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
701 struct snd_kcontrol *kcontrol, int event)
702 {
703 struct twl4030_priv *twl4030 = w->codec->private_data;
704
705 switch (event) {
706 case SND_SOC_DAPM_POST_PMU:
707 /* Do the ramp-up only once */
708 if (!twl4030->hsr_enabled)
709 headset_ramp(w->codec, 1);
710
711 twl4030->hsl_enabled = 1;
712 break;
713 case SND_SOC_DAPM_POST_PMD:
714 /* Do the ramp-down only if both headsetL/R is disabled */
715 if (!twl4030->hsr_enabled)
716 headset_ramp(w->codec, 0);
717
718 twl4030->hsl_enabled = 0;
719 break;
720 }
721 return 0;
722 }
723
724 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
725 struct snd_kcontrol *kcontrol, int event)
726 {
727 struct twl4030_priv *twl4030 = w->codec->private_data;
728
729 switch (event) {
730 case SND_SOC_DAPM_POST_PMU:
731 /* Do the ramp-up only once */
732 if (!twl4030->hsl_enabled)
733 headset_ramp(w->codec, 1);
734
735 twl4030->hsr_enabled = 1;
736 break;
737 case SND_SOC_DAPM_POST_PMD:
738 /* Do the ramp-down only if both headsetL/R is disabled */
739 if (!twl4030->hsl_enabled)
740 headset_ramp(w->codec, 0);
741
742 twl4030->hsr_enabled = 0;
743 break;
744 }
745 return 0;
746 }
747
748 /*
749 * Some of the gain controls in TWL (mostly those which are associated with
750 * the outputs) are implemented in an interesting way:
751 * 0x0 : Power down (mute)
752 * 0x1 : 6dB
753 * 0x2 : 0 dB
754 * 0x3 : -6 dB
755 * Inverting not going to help with these.
756 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
757 */
758 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
759 xinvert, tlv_array) \
760 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
761 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
762 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
763 .tlv.p = (tlv_array), \
764 .info = snd_soc_info_volsw, \
765 .get = snd_soc_get_volsw_twl4030, \
766 .put = snd_soc_put_volsw_twl4030, \
767 .private_value = (unsigned long)&(struct soc_mixer_control) \
768 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
769 .max = xmax, .invert = xinvert} }
770 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
771 xinvert, tlv_array) \
772 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
773 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
774 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
775 .tlv.p = (tlv_array), \
776 .info = snd_soc_info_volsw_2r, \
777 .get = snd_soc_get_volsw_r2_twl4030,\
778 .put = snd_soc_put_volsw_r2_twl4030, \
779 .private_value = (unsigned long)&(struct soc_mixer_control) \
780 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
781 .rshift = xshift, .max = xmax, .invert = xinvert} }
782 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
783 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
784 xinvert, tlv_array)
785
786 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
787 struct snd_ctl_elem_value *ucontrol)
788 {
789 struct soc_mixer_control *mc =
790 (struct soc_mixer_control *)kcontrol->private_value;
791 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
792 unsigned int reg = mc->reg;
793 unsigned int shift = mc->shift;
794 unsigned int rshift = mc->rshift;
795 int max = mc->max;
796 int mask = (1 << fls(max)) - 1;
797
798 ucontrol->value.integer.value[0] =
799 (snd_soc_read(codec, reg) >> shift) & mask;
800 if (ucontrol->value.integer.value[0])
801 ucontrol->value.integer.value[0] =
802 max + 1 - ucontrol->value.integer.value[0];
803
804 if (shift != rshift) {
805 ucontrol->value.integer.value[1] =
806 (snd_soc_read(codec, reg) >> rshift) & mask;
807 if (ucontrol->value.integer.value[1])
808 ucontrol->value.integer.value[1] =
809 max + 1 - ucontrol->value.integer.value[1];
810 }
811
812 return 0;
813 }
814
815 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
816 struct snd_ctl_elem_value *ucontrol)
817 {
818 struct soc_mixer_control *mc =
819 (struct soc_mixer_control *)kcontrol->private_value;
820 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
821 unsigned int reg = mc->reg;
822 unsigned int shift = mc->shift;
823 unsigned int rshift = mc->rshift;
824 int max = mc->max;
825 int mask = (1 << fls(max)) - 1;
826 unsigned short val, val2, val_mask;
827
828 val = (ucontrol->value.integer.value[0] & mask);
829
830 val_mask = mask << shift;
831 if (val)
832 val = max + 1 - val;
833 val = val << shift;
834 if (shift != rshift) {
835 val2 = (ucontrol->value.integer.value[1] & mask);
836 val_mask |= mask << rshift;
837 if (val2)
838 val2 = max + 1 - val2;
839 val |= val2 << rshift;
840 }
841 return snd_soc_update_bits(codec, reg, val_mask, val);
842 }
843
844 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
845 struct snd_ctl_elem_value *ucontrol)
846 {
847 struct soc_mixer_control *mc =
848 (struct soc_mixer_control *)kcontrol->private_value;
849 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
850 unsigned int reg = mc->reg;
851 unsigned int reg2 = mc->rreg;
852 unsigned int shift = mc->shift;
853 int max = mc->max;
854 int mask = (1<<fls(max))-1;
855
856 ucontrol->value.integer.value[0] =
857 (snd_soc_read(codec, reg) >> shift) & mask;
858 ucontrol->value.integer.value[1] =
859 (snd_soc_read(codec, reg2) >> shift) & mask;
860
861 if (ucontrol->value.integer.value[0])
862 ucontrol->value.integer.value[0] =
863 max + 1 - ucontrol->value.integer.value[0];
864 if (ucontrol->value.integer.value[1])
865 ucontrol->value.integer.value[1] =
866 max + 1 - ucontrol->value.integer.value[1];
867
868 return 0;
869 }
870
871 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
872 struct snd_ctl_elem_value *ucontrol)
873 {
874 struct soc_mixer_control *mc =
875 (struct soc_mixer_control *)kcontrol->private_value;
876 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
877 unsigned int reg = mc->reg;
878 unsigned int reg2 = mc->rreg;
879 unsigned int shift = mc->shift;
880 int max = mc->max;
881 int mask = (1 << fls(max)) - 1;
882 int err;
883 unsigned short val, val2, val_mask;
884
885 val_mask = mask << shift;
886 val = (ucontrol->value.integer.value[0] & mask);
887 val2 = (ucontrol->value.integer.value[1] & mask);
888
889 if (val)
890 val = max + 1 - val;
891 if (val2)
892 val2 = max + 1 - val2;
893
894 val = val << shift;
895 val2 = val2 << shift;
896
897 err = snd_soc_update_bits(codec, reg, val_mask, val);
898 if (err < 0)
899 return err;
900
901 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
902 return err;
903 }
904
905 /* Codec operation modes */
906 static const char *twl4030_op_modes_texts[] = {
907 "Option 2 (voice/audio)", "Option 1 (audio)"
908 };
909
910 static const struct soc_enum twl4030_op_modes_enum =
911 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
912 ARRAY_SIZE(twl4030_op_modes_texts),
913 twl4030_op_modes_texts);
914
915 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
916 struct snd_ctl_elem_value *ucontrol)
917 {
918 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
919 struct twl4030_priv *twl4030 = codec->private_data;
920 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
921 unsigned short val;
922 unsigned short mask, bitmask;
923
924 if (twl4030->configured) {
925 printk(KERN_ERR "twl4030 operation mode cannot be "
926 "changed on-the-fly\n");
927 return -EBUSY;
928 }
929
930 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
931 ;
932 if (ucontrol->value.enumerated.item[0] > e->max - 1)
933 return -EINVAL;
934
935 val = ucontrol->value.enumerated.item[0] << e->shift_l;
936 mask = (bitmask - 1) << e->shift_l;
937 if (e->shift_l != e->shift_r) {
938 if (ucontrol->value.enumerated.item[1] > e->max - 1)
939 return -EINVAL;
940 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
941 mask |= (bitmask - 1) << e->shift_r;
942 }
943
944 return snd_soc_update_bits(codec, e->reg, mask, val);
945 }
946
947 /*
948 * FGAIN volume control:
949 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
950 */
951 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
952
953 /*
954 * CGAIN volume control:
955 * 0 dB to 12 dB in 6 dB steps
956 * value 2 and 3 means 12 dB
957 */
958 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
959
960 /*
961 * Voice Downlink GAIN volume control:
962 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
963 */
964 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
965
966 /*
967 * Analog playback gain
968 * -24 dB to 12 dB in 2 dB steps
969 */
970 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
971
972 /*
973 * Gain controls tied to outputs
974 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
975 */
976 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
977
978 /*
979 * Gain control for earpiece amplifier
980 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
981 */
982 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
983
984 /*
985 * Capture gain after the ADCs
986 * from 0 dB to 31 dB in 1 dB steps
987 */
988 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
989
990 /*
991 * Gain control for input amplifiers
992 * 0 dB to 30 dB in 6 dB steps
993 */
994 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
995
996 /* AVADC clock priority */
997 static const char *twl4030_avadc_clk_priority_texts[] = {
998 "Voice high priority", "HiFi high priority"
999 };
1000
1001 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1002 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1003 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1004 twl4030_avadc_clk_priority_texts);
1005
1006 static const char *twl4030_rampdelay_texts[] = {
1007 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1008 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1009 "3495/2581/1748 ms"
1010 };
1011
1012 static const struct soc_enum twl4030_rampdelay_enum =
1013 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1014 ARRAY_SIZE(twl4030_rampdelay_texts),
1015 twl4030_rampdelay_texts);
1016
1017 /* Vibra H-bridge direction mode */
1018 static const char *twl4030_vibradirmode_texts[] = {
1019 "Vibra H-bridge direction", "Audio data MSB",
1020 };
1021
1022 static const struct soc_enum twl4030_vibradirmode_enum =
1023 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1024 ARRAY_SIZE(twl4030_vibradirmode_texts),
1025 twl4030_vibradirmode_texts);
1026
1027 /* Vibra H-bridge direction */
1028 static const char *twl4030_vibradir_texts[] = {
1029 "Positive polarity", "Negative polarity",
1030 };
1031
1032 static const struct soc_enum twl4030_vibradir_enum =
1033 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1034 ARRAY_SIZE(twl4030_vibradir_texts),
1035 twl4030_vibradir_texts);
1036
1037 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1038 /* Codec operation mode control */
1039 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1040 snd_soc_get_enum_double,
1041 snd_soc_put_twl4030_opmode_enum_double),
1042
1043 /* Common playback gain controls */
1044 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1045 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1046 0, 0x3f, 0, digital_fine_tlv),
1047 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1048 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1049 0, 0x3f, 0, digital_fine_tlv),
1050
1051 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1052 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1053 6, 0x2, 0, digital_coarse_tlv),
1054 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1055 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1056 6, 0x2, 0, digital_coarse_tlv),
1057
1058 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1059 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1060 3, 0x12, 1, analog_tlv),
1061 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1062 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1063 3, 0x12, 1, analog_tlv),
1064 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1065 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1066 1, 1, 0),
1067 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1068 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1069 1, 1, 0),
1070
1071 /* Common voice downlink gain controls */
1072 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1073 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1074
1075 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1076 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1077
1078 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1079 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1080
1081 /* Separate output gain controls */
1082 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1083 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1084 4, 3, 0, output_tvl),
1085
1086 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1087 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1088
1089 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1090 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1091 4, 3, 0, output_tvl),
1092
1093 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
1094 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
1095
1096 /* Common capture gain controls */
1097 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1098 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1099 0, 0x1f, 0, digital_capture_tlv),
1100 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1101 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1102 0, 0x1f, 0, digital_capture_tlv),
1103
1104 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1105 0, 3, 5, 0, input_gain_tlv),
1106
1107 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1108
1109 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1110
1111 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1112 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1113 };
1114
1115 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1116 /* Left channel inputs */
1117 SND_SOC_DAPM_INPUT("MAINMIC"),
1118 SND_SOC_DAPM_INPUT("HSMIC"),
1119 SND_SOC_DAPM_INPUT("AUXL"),
1120 SND_SOC_DAPM_INPUT("CARKITMIC"),
1121 /* Right channel inputs */
1122 SND_SOC_DAPM_INPUT("SUBMIC"),
1123 SND_SOC_DAPM_INPUT("AUXR"),
1124 /* Digital microphones (Stereo) */
1125 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1126 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1127
1128 /* Outputs */
1129 SND_SOC_DAPM_OUTPUT("OUTL"),
1130 SND_SOC_DAPM_OUTPUT("OUTR"),
1131 SND_SOC_DAPM_OUTPUT("EARPIECE"),
1132 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1133 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1134 SND_SOC_DAPM_OUTPUT("HSOL"),
1135 SND_SOC_DAPM_OUTPUT("HSOR"),
1136 SND_SOC_DAPM_OUTPUT("CARKITL"),
1137 SND_SOC_DAPM_OUTPUT("CARKITR"),
1138 SND_SOC_DAPM_OUTPUT("HFL"),
1139 SND_SOC_DAPM_OUTPUT("HFR"),
1140 SND_SOC_DAPM_OUTPUT("VIBRA"),
1141
1142 /* DACs */
1143 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
1144 SND_SOC_NOPM, 0, 0),
1145 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
1146 SND_SOC_NOPM, 0, 0),
1147 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
1148 SND_SOC_NOPM, 0, 0),
1149 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
1150 SND_SOC_NOPM, 0, 0),
1151 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
1152 SND_SOC_NOPM, 0, 0),
1153
1154 /* Analog bypasses */
1155 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1156 &twl4030_dapm_abypassr1_control),
1157 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1158 &twl4030_dapm_abypassl1_control),
1159 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1160 &twl4030_dapm_abypassr2_control),
1161 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1162 &twl4030_dapm_abypassl2_control),
1163 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1164 &twl4030_dapm_abypassv_control),
1165
1166 /* Master analog loopback switch */
1167 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1168 NULL, 0),
1169
1170 /* Digital bypasses */
1171 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1172 &twl4030_dapm_dbypassl_control),
1173 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1174 &twl4030_dapm_dbypassr_control),
1175 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1176 &twl4030_dapm_dbypassv_control),
1177
1178 /* Digital mixers, power control for the physical DACs */
1179 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1180 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1181 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1182 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1183 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1184 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1185 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1186 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1187 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1188 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1189
1190 /* Analog mixers, power control for the physical PGAs */
1191 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1192 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1193 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1194 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1195 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1196 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1197 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1198 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1199 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1200 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1201
1202 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1203 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1204
1205 /* Output MIXER controls */
1206 /* Earpiece */
1207 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1208 &twl4030_dapm_earpiece_controls[0],
1209 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1210 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1211 0, 0, NULL, 0, earpiecepga_event,
1212 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1213 /* PreDrivL/R */
1214 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1215 &twl4030_dapm_predrivel_controls[0],
1216 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1217 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1218 0, 0, NULL, 0, predrivelpga_event,
1219 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1220 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1221 &twl4030_dapm_predriver_controls[0],
1222 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1223 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1224 0, 0, NULL, 0, predriverpga_event,
1225 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1226 /* HeadsetL/R */
1227 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1228 &twl4030_dapm_hsol_controls[0],
1229 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1230 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1231 0, 0, NULL, 0, headsetlpga_event,
1232 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1233 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1234 &twl4030_dapm_hsor_controls[0],
1235 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1236 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1237 0, 0, NULL, 0, headsetrpga_event,
1238 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1239 /* CarkitL/R */
1240 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1241 &twl4030_dapm_carkitl_controls[0],
1242 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1243 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1244 0, 0, NULL, 0, carkitlpga_event,
1245 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1246 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1247 &twl4030_dapm_carkitr_controls[0],
1248 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1249 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1250 0, 0, NULL, 0, carkitrpga_event,
1251 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1252
1253 /* Output MUX controls */
1254 /* HandsfreeL/R */
1255 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1256 &twl4030_dapm_handsfreel_control),
1257 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1258 &twl4030_dapm_handsfreelmute_control),
1259 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1260 0, 0, NULL, 0, handsfreelpga_event,
1261 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1262 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1263 &twl4030_dapm_handsfreer_control),
1264 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1265 &twl4030_dapm_handsfreermute_control),
1266 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1267 0, 0, NULL, 0, handsfreerpga_event,
1268 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1269 /* Vibra */
1270 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1271 &twl4030_dapm_vibra_control, vibramux_event,
1272 SND_SOC_DAPM_PRE_PMU),
1273 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1274 &twl4030_dapm_vibrapath_control),
1275
1276 /* Introducing four virtual ADC, since TWL4030 have four channel for
1277 capture */
1278 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1279 SND_SOC_NOPM, 0, 0),
1280 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1281 SND_SOC_NOPM, 0, 0),
1282 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1283 SND_SOC_NOPM, 0, 0),
1284 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1285 SND_SOC_NOPM, 0, 0),
1286
1287 /* Analog/Digital mic path selection.
1288 TX1 Left/Right: either analog Left/Right or Digimic0
1289 TX2 Left/Right: either analog Left/Right or Digimic1 */
1290 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1291 &twl4030_dapm_micpathtx1_control, micpath_event,
1292 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1293 SND_SOC_DAPM_POST_REG),
1294 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1295 &twl4030_dapm_micpathtx2_control, micpath_event,
1296 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1297 SND_SOC_DAPM_POST_REG),
1298
1299 /* Analog input mixers for the capture amplifiers */
1300 SND_SOC_DAPM_MIXER("Analog Left",
1301 TWL4030_REG_ANAMICL, 4, 0,
1302 &twl4030_dapm_analoglmic_controls[0],
1303 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1304 SND_SOC_DAPM_MIXER("Analog Right",
1305 TWL4030_REG_ANAMICR, 4, 0,
1306 &twl4030_dapm_analogrmic_controls[0],
1307 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1308
1309 SND_SOC_DAPM_PGA("ADC Physical Left",
1310 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1311 SND_SOC_DAPM_PGA("ADC Physical Right",
1312 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1313
1314 SND_SOC_DAPM_PGA("Digimic0 Enable",
1315 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1316 SND_SOC_DAPM_PGA("Digimic1 Enable",
1317 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1318
1319 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1320 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1321 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1322
1323 };
1324
1325 static const struct snd_soc_dapm_route intercon[] = {
1326 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1327 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1328 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1329 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1330 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1331
1332 /* Supply for the digital part (APLL) */
1333 {"Digital R1 Playback Mixer", NULL, "APLL Enable"},
1334 {"Digital L1 Playback Mixer", NULL, "APLL Enable"},
1335 {"Digital R2 Playback Mixer", NULL, "APLL Enable"},
1336 {"Digital L2 Playback Mixer", NULL, "APLL Enable"},
1337 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1338
1339 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1340 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1341 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1342 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1343 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1344
1345 /* Internal playback routings */
1346 /* Earpiece */
1347 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1348 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1349 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1350 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1351 {"Earpiece PGA", NULL, "Earpiece Mixer"},
1352 /* PreDrivL */
1353 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1354 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1355 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1356 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1357 {"PredriveL PGA", NULL, "PredriveL Mixer"},
1358 /* PreDrivR */
1359 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1360 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1361 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1362 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1363 {"PredriveR PGA", NULL, "PredriveR Mixer"},
1364 /* HeadsetL */
1365 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1366 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1367 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1368 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1369 /* HeadsetR */
1370 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1371 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1372 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1373 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1374 /* CarkitL */
1375 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1376 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1377 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1378 {"CarkitL PGA", NULL, "CarkitL Mixer"},
1379 /* CarkitR */
1380 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1381 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1382 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1383 {"CarkitR PGA", NULL, "CarkitR Mixer"},
1384 /* HandsfreeL */
1385 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1386 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1387 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1388 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1389 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1390 {"HandsfreeL PGA", NULL, "HandsfreeL"},
1391 /* HandsfreeR */
1392 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1393 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1394 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1395 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1396 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1397 {"HandsfreeR PGA", NULL, "HandsfreeR"},
1398 /* Vibra */
1399 {"Vibra Mux", "AudioL1", "DAC Left1"},
1400 {"Vibra Mux", "AudioR1", "DAC Right1"},
1401 {"Vibra Mux", "AudioL2", "DAC Left2"},
1402 {"Vibra Mux", "AudioR2", "DAC Right2"},
1403
1404 /* outputs */
1405 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1406 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1407 {"EARPIECE", NULL, "Earpiece PGA"},
1408 {"PREDRIVEL", NULL, "PredriveL PGA"},
1409 {"PREDRIVER", NULL, "PredriveR PGA"},
1410 {"HSOL", NULL, "HeadsetL PGA"},
1411 {"HSOR", NULL, "HeadsetR PGA"},
1412 {"CARKITL", NULL, "CarkitL PGA"},
1413 {"CARKITR", NULL, "CarkitR PGA"},
1414 {"HFL", NULL, "HandsfreeL PGA"},
1415 {"HFR", NULL, "HandsfreeR PGA"},
1416 {"Vibra Route", "Audio", "Vibra Mux"},
1417 {"VIBRA", NULL, "Vibra Route"},
1418
1419 /* Capture path */
1420 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1421 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1422 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1423 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1424
1425 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1426 {"Analog Right", "AUXR Capture Switch", "AUXR"},
1427
1428 {"ADC Physical Left", NULL, "Analog Left"},
1429 {"ADC Physical Right", NULL, "Analog Right"},
1430
1431 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1432 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1433
1434 /* TX1 Left capture path */
1435 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1436 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1437 /* TX1 Right capture path */
1438 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1439 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1440 /* TX2 Left capture path */
1441 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1442 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1443 /* TX2 Right capture path */
1444 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1445 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1446
1447 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1448 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1449 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1450 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1451
1452 {"ADC Virtual Left1", NULL, "APLL Enable"},
1453 {"ADC Virtual Right1", NULL, "APLL Enable"},
1454 {"ADC Virtual Left2", NULL, "APLL Enable"},
1455 {"ADC Virtual Right2", NULL, "APLL Enable"},
1456
1457 /* Analog bypass routes */
1458 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1459 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1460 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1461 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1462 {"Voice Analog Loopback", "Switch", "Analog Left"},
1463
1464 /* Supply for the Analog loopbacks */
1465 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1466 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1467 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1468 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1469 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1470
1471 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1472 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1473 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1474 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1475 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1476
1477 /* Digital bypass routes */
1478 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1479 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1480 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1481
1482 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1483 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1484 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1485
1486 };
1487
1488 static int twl4030_add_widgets(struct snd_soc_codec *codec)
1489 {
1490 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1491 ARRAY_SIZE(twl4030_dapm_widgets));
1492
1493 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1494
1495 snd_soc_dapm_new_widgets(codec);
1496 return 0;
1497 }
1498
1499 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1500 enum snd_soc_bias_level level)
1501 {
1502 switch (level) {
1503 case SND_SOC_BIAS_ON:
1504 break;
1505 case SND_SOC_BIAS_PREPARE:
1506 break;
1507 case SND_SOC_BIAS_STANDBY:
1508 if (codec->bias_level == SND_SOC_BIAS_OFF)
1509 twl4030_power_up(codec);
1510 break;
1511 case SND_SOC_BIAS_OFF:
1512 twl4030_power_down(codec);
1513 break;
1514 }
1515 codec->bias_level = level;
1516
1517 return 0;
1518 }
1519
1520 static void twl4030_constraints(struct twl4030_priv *twl4030,
1521 struct snd_pcm_substream *mst_substream)
1522 {
1523 struct snd_pcm_substream *slv_substream;
1524
1525 /* Pick the stream, which need to be constrained */
1526 if (mst_substream == twl4030->master_substream)
1527 slv_substream = twl4030->slave_substream;
1528 else if (mst_substream == twl4030->slave_substream)
1529 slv_substream = twl4030->master_substream;
1530 else /* This should not happen.. */
1531 return;
1532
1533 /* Set the constraints according to the already configured stream */
1534 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1535 SNDRV_PCM_HW_PARAM_RATE,
1536 twl4030->rate,
1537 twl4030->rate);
1538
1539 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1540 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1541 twl4030->sample_bits,
1542 twl4030->sample_bits);
1543
1544 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1545 SNDRV_PCM_HW_PARAM_CHANNELS,
1546 twl4030->channels,
1547 twl4030->channels);
1548 }
1549
1550 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1551 * capture has to be enabled/disabled. */
1552 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1553 int enable)
1554 {
1555 u8 reg, mask;
1556
1557 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1558
1559 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1560 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1561 else
1562 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1563
1564 if (enable)
1565 reg |= mask;
1566 else
1567 reg &= ~mask;
1568
1569 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1570 }
1571
1572 static int twl4030_startup(struct snd_pcm_substream *substream,
1573 struct snd_soc_dai *dai)
1574 {
1575 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1576 struct snd_soc_device *socdev = rtd->socdev;
1577 struct snd_soc_codec *codec = socdev->card->codec;
1578 struct twl4030_priv *twl4030 = codec->private_data;
1579
1580 if (twl4030->master_substream) {
1581 twl4030->slave_substream = substream;
1582 /* The DAI has one configuration for playback and capture, so
1583 * if the DAI has been already configured then constrain this
1584 * substream to match it. */
1585 if (twl4030->configured)
1586 twl4030_constraints(twl4030, twl4030->master_substream);
1587 } else {
1588 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1589 TWL4030_OPTION_1)) {
1590 /* In option2 4 channel is not supported, set the
1591 * constraint for the first stream for channels, the
1592 * second stream will 'inherit' this cosntraint */
1593 snd_pcm_hw_constraint_minmax(substream->runtime,
1594 SNDRV_PCM_HW_PARAM_CHANNELS,
1595 2, 2);
1596 }
1597 twl4030->master_substream = substream;
1598 }
1599
1600 return 0;
1601 }
1602
1603 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1604 struct snd_soc_dai *dai)
1605 {
1606 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1607 struct snd_soc_device *socdev = rtd->socdev;
1608 struct snd_soc_codec *codec = socdev->card->codec;
1609 struct twl4030_priv *twl4030 = codec->private_data;
1610
1611 if (twl4030->master_substream == substream)
1612 twl4030->master_substream = twl4030->slave_substream;
1613
1614 twl4030->slave_substream = NULL;
1615
1616 /* If all streams are closed, or the remaining stream has not yet
1617 * been configured than set the DAI as not configured. */
1618 if (!twl4030->master_substream)
1619 twl4030->configured = 0;
1620 else if (!twl4030->master_substream->runtime->channels)
1621 twl4030->configured = 0;
1622
1623 /* If the closing substream had 4 channel, do the necessary cleanup */
1624 if (substream->runtime->channels == 4)
1625 twl4030_tdm_enable(codec, substream->stream, 0);
1626 }
1627
1628 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1629 struct snd_pcm_hw_params *params,
1630 struct snd_soc_dai *dai)
1631 {
1632 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1633 struct snd_soc_device *socdev = rtd->socdev;
1634 struct snd_soc_codec *codec = socdev->card->codec;
1635 struct twl4030_priv *twl4030 = codec->private_data;
1636 u8 mode, old_mode, format, old_format;
1637
1638 /* If the substream has 4 channel, do the necessary setup */
1639 if (params_channels(params) == 4) {
1640 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1641 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1642
1643 /* Safety check: are we in the correct operating mode and
1644 * the interface is in TDM mode? */
1645 if ((mode & TWL4030_OPTION_1) &&
1646 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1647 twl4030_tdm_enable(codec, substream->stream, 1);
1648 else
1649 return -EINVAL;
1650 }
1651
1652 if (twl4030->configured)
1653 /* Ignoring hw_params for already configured DAI */
1654 return 0;
1655
1656 /* bit rate */
1657 old_mode = twl4030_read_reg_cache(codec,
1658 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1659 mode = old_mode & ~TWL4030_APLL_RATE;
1660
1661 switch (params_rate(params)) {
1662 case 8000:
1663 mode |= TWL4030_APLL_RATE_8000;
1664 break;
1665 case 11025:
1666 mode |= TWL4030_APLL_RATE_11025;
1667 break;
1668 case 12000:
1669 mode |= TWL4030_APLL_RATE_12000;
1670 break;
1671 case 16000:
1672 mode |= TWL4030_APLL_RATE_16000;
1673 break;
1674 case 22050:
1675 mode |= TWL4030_APLL_RATE_22050;
1676 break;
1677 case 24000:
1678 mode |= TWL4030_APLL_RATE_24000;
1679 break;
1680 case 32000:
1681 mode |= TWL4030_APLL_RATE_32000;
1682 break;
1683 case 44100:
1684 mode |= TWL4030_APLL_RATE_44100;
1685 break;
1686 case 48000:
1687 mode |= TWL4030_APLL_RATE_48000;
1688 break;
1689 case 96000:
1690 mode |= TWL4030_APLL_RATE_96000;
1691 break;
1692 default:
1693 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1694 params_rate(params));
1695 return -EINVAL;
1696 }
1697
1698 if (mode != old_mode) {
1699 /* change rate and set CODECPDZ */
1700 twl4030_codec_enable(codec, 0);
1701 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1702 twl4030_codec_enable(codec, 1);
1703 }
1704
1705 /* sample size */
1706 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1707 format = old_format;
1708 format &= ~TWL4030_DATA_WIDTH;
1709 switch (params_format(params)) {
1710 case SNDRV_PCM_FORMAT_S16_LE:
1711 format |= TWL4030_DATA_WIDTH_16S_16W;
1712 break;
1713 case SNDRV_PCM_FORMAT_S24_LE:
1714 format |= TWL4030_DATA_WIDTH_32S_24W;
1715 break;
1716 default:
1717 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1718 params_format(params));
1719 return -EINVAL;
1720 }
1721
1722 if (format != old_format) {
1723
1724 /* clear CODECPDZ before changing format (codec requirement) */
1725 twl4030_codec_enable(codec, 0);
1726
1727 /* change format */
1728 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1729
1730 /* set CODECPDZ afterwards */
1731 twl4030_codec_enable(codec, 1);
1732 }
1733
1734 /* Store the important parameters for the DAI configuration and set
1735 * the DAI as configured */
1736 twl4030->configured = 1;
1737 twl4030->rate = params_rate(params);
1738 twl4030->sample_bits = hw_param_interval(params,
1739 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1740 twl4030->channels = params_channels(params);
1741
1742 /* If both playback and capture streams are open, and one of them
1743 * is setting the hw parameters right now (since we are here), set
1744 * constraints to the other stream to match the current one. */
1745 if (twl4030->slave_substream)
1746 twl4030_constraints(twl4030, substream);
1747
1748 return 0;
1749 }
1750
1751 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1752 int clk_id, unsigned int freq, int dir)
1753 {
1754 struct snd_soc_codec *codec = codec_dai->codec;
1755 struct twl4030_priv *twl4030 = codec->private_data;
1756 u8 apll_ctrl;
1757
1758 apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
1759 apll_ctrl &= ~TWL4030_APLL_INFREQ;
1760 switch (freq) {
1761 case 19200000:
1762 apll_ctrl |= TWL4030_APLL_INFREQ_19200KHZ;
1763 twl4030->sysclk = 19200;
1764 break;
1765 case 26000000:
1766 apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
1767 twl4030->sysclk = 26000;
1768 break;
1769 case 38400000:
1770 apll_ctrl |= TWL4030_APLL_INFREQ_38400KHZ;
1771 twl4030->sysclk = 38400;
1772 break;
1773 default:
1774 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1775 freq);
1776 return -EINVAL;
1777 }
1778
1779 twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
1780
1781 return 0;
1782 }
1783
1784 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1785 unsigned int fmt)
1786 {
1787 struct snd_soc_codec *codec = codec_dai->codec;
1788 u8 old_format, format;
1789
1790 /* get format */
1791 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1792 format = old_format;
1793
1794 /* set master/slave audio interface */
1795 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1796 case SND_SOC_DAIFMT_CBM_CFM:
1797 format &= ~(TWL4030_AIF_SLAVE_EN);
1798 format &= ~(TWL4030_CLK256FS_EN);
1799 break;
1800 case SND_SOC_DAIFMT_CBS_CFS:
1801 format |= TWL4030_AIF_SLAVE_EN;
1802 format |= TWL4030_CLK256FS_EN;
1803 break;
1804 default:
1805 return -EINVAL;
1806 }
1807
1808 /* interface format */
1809 format &= ~TWL4030_AIF_FORMAT;
1810 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1811 case SND_SOC_DAIFMT_I2S:
1812 format |= TWL4030_AIF_FORMAT_CODEC;
1813 break;
1814 case SND_SOC_DAIFMT_DSP_A:
1815 format |= TWL4030_AIF_FORMAT_TDM;
1816 break;
1817 default:
1818 return -EINVAL;
1819 }
1820
1821 if (format != old_format) {
1822
1823 /* clear CODECPDZ before changing format (codec requirement) */
1824 twl4030_codec_enable(codec, 0);
1825
1826 /* change format */
1827 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1828
1829 /* set CODECPDZ afterwards */
1830 twl4030_codec_enable(codec, 1);
1831 }
1832
1833 return 0;
1834 }
1835
1836 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1837 {
1838 struct snd_soc_codec *codec = dai->codec;
1839 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1840
1841 if (tristate)
1842 reg |= TWL4030_AIF_TRI_EN;
1843 else
1844 reg &= ~TWL4030_AIF_TRI_EN;
1845
1846 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1847 }
1848
1849 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1850 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1851 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1852 int enable)
1853 {
1854 u8 reg, mask;
1855
1856 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1857
1858 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1859 mask = TWL4030_ARXL1_VRX_EN;
1860 else
1861 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1862
1863 if (enable)
1864 reg |= mask;
1865 else
1866 reg &= ~mask;
1867
1868 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1869 }
1870
1871 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1872 struct snd_soc_dai *dai)
1873 {
1874 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1875 struct snd_soc_device *socdev = rtd->socdev;
1876 struct snd_soc_codec *codec = socdev->card->codec;
1877 u8 infreq;
1878 u8 mode;
1879
1880 /* If the system master clock is not 26MHz, the voice PCM interface is
1881 * not avilable.
1882 */
1883 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1884 & TWL4030_APLL_INFREQ;
1885
1886 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1887 printk(KERN_ERR "TWL4030 voice startup: "
1888 "MCLK is not 26MHz, call set_sysclk() on init\n");
1889 return -EINVAL;
1890 }
1891
1892 /* If the codec mode is not option2, the voice PCM interface is not
1893 * avilable.
1894 */
1895 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1896 & TWL4030_OPT_MODE;
1897
1898 if (mode != TWL4030_OPTION_2) {
1899 printk(KERN_ERR "TWL4030 voice startup: "
1900 "the codec mode is not option2\n");
1901 return -EINVAL;
1902 }
1903
1904 return 0;
1905 }
1906
1907 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1908 struct snd_soc_dai *dai)
1909 {
1910 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1911 struct snd_soc_device *socdev = rtd->socdev;
1912 struct snd_soc_codec *codec = socdev->card->codec;
1913
1914 /* Enable voice digital filters */
1915 twl4030_voice_enable(codec, substream->stream, 0);
1916 }
1917
1918 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1919 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1920 {
1921 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1922 struct snd_soc_device *socdev = rtd->socdev;
1923 struct snd_soc_codec *codec = socdev->card->codec;
1924 u8 old_mode, mode;
1925
1926 /* Enable voice digital filters */
1927 twl4030_voice_enable(codec, substream->stream, 1);
1928
1929 /* bit rate */
1930 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1931 & ~(TWL4030_CODECPDZ);
1932 mode = old_mode;
1933
1934 switch (params_rate(params)) {
1935 case 8000:
1936 mode &= ~(TWL4030_SEL_16K);
1937 break;
1938 case 16000:
1939 mode |= TWL4030_SEL_16K;
1940 break;
1941 default:
1942 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1943 params_rate(params));
1944 return -EINVAL;
1945 }
1946
1947 if (mode != old_mode) {
1948 /* change rate and set CODECPDZ */
1949 twl4030_codec_enable(codec, 0);
1950 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1951 twl4030_codec_enable(codec, 1);
1952 }
1953
1954 return 0;
1955 }
1956
1957 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1958 int clk_id, unsigned int freq, int dir)
1959 {
1960 struct snd_soc_codec *codec = codec_dai->codec;
1961 u8 apll_ctrl;
1962
1963 apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
1964 apll_ctrl &= ~TWL4030_APLL_INFREQ;
1965 switch (freq) {
1966 case 26000000:
1967 apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
1968 break;
1969 default:
1970 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1971 freq);
1972 return -EINVAL;
1973 }
1974
1975 twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
1976
1977 return 0;
1978 }
1979
1980 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1981 unsigned int fmt)
1982 {
1983 struct snd_soc_codec *codec = codec_dai->codec;
1984 u8 old_format, format;
1985
1986 /* get format */
1987 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1988 format = old_format;
1989
1990 /* set master/slave audio interface */
1991 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1992 case SND_SOC_DAIFMT_CBM_CFM:
1993 format &= ~(TWL4030_VIF_SLAVE_EN);
1994 break;
1995 case SND_SOC_DAIFMT_CBS_CFS:
1996 format |= TWL4030_VIF_SLAVE_EN;
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
2002 /* clock inversion */
2003 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2004 case SND_SOC_DAIFMT_IB_NF:
2005 format &= ~(TWL4030_VIF_FORMAT);
2006 break;
2007 case SND_SOC_DAIFMT_NB_IF:
2008 format |= TWL4030_VIF_FORMAT;
2009 break;
2010 default:
2011 return -EINVAL;
2012 }
2013
2014 if (format != old_format) {
2015 /* change format and set CODECPDZ */
2016 twl4030_codec_enable(codec, 0);
2017 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2018 twl4030_codec_enable(codec, 1);
2019 }
2020
2021 return 0;
2022 }
2023
2024 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2025 {
2026 struct snd_soc_codec *codec = dai->codec;
2027 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2028
2029 if (tristate)
2030 reg |= TWL4030_VIF_TRI_EN;
2031 else
2032 reg &= ~TWL4030_VIF_TRI_EN;
2033
2034 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2035 }
2036
2037 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2038 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2039
2040 static struct snd_soc_dai_ops twl4030_dai_ops = {
2041 .startup = twl4030_startup,
2042 .shutdown = twl4030_shutdown,
2043 .hw_params = twl4030_hw_params,
2044 .set_sysclk = twl4030_set_dai_sysclk,
2045 .set_fmt = twl4030_set_dai_fmt,
2046 .set_tristate = twl4030_set_tristate,
2047 };
2048
2049 static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2050 .startup = twl4030_voice_startup,
2051 .shutdown = twl4030_voice_shutdown,
2052 .hw_params = twl4030_voice_hw_params,
2053 .set_sysclk = twl4030_voice_set_dai_sysclk,
2054 .set_fmt = twl4030_voice_set_dai_fmt,
2055 .set_tristate = twl4030_voice_set_tristate,
2056 };
2057
2058 struct snd_soc_dai twl4030_dai[] = {
2059 {
2060 .name = "twl4030",
2061 .playback = {
2062 .stream_name = "HiFi Playback",
2063 .channels_min = 2,
2064 .channels_max = 4,
2065 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2066 .formats = TWL4030_FORMATS,},
2067 .capture = {
2068 .stream_name = "Capture",
2069 .channels_min = 2,
2070 .channels_max = 4,
2071 .rates = TWL4030_RATES,
2072 .formats = TWL4030_FORMATS,},
2073 .ops = &twl4030_dai_ops,
2074 },
2075 {
2076 .name = "twl4030 Voice",
2077 .playback = {
2078 .stream_name = "Voice Playback",
2079 .channels_min = 1,
2080 .channels_max = 1,
2081 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2082 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2083 .capture = {
2084 .stream_name = "Capture",
2085 .channels_min = 1,
2086 .channels_max = 2,
2087 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2088 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2089 .ops = &twl4030_dai_voice_ops,
2090 },
2091 };
2092 EXPORT_SYMBOL_GPL(twl4030_dai);
2093
2094 static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
2095 {
2096 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2097 struct snd_soc_codec *codec = socdev->card->codec;
2098
2099 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2100
2101 return 0;
2102 }
2103
2104 static int twl4030_soc_resume(struct platform_device *pdev)
2105 {
2106 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2107 struct snd_soc_codec *codec = socdev->card->codec;
2108
2109 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2110 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2111 return 0;
2112 }
2113
2114 static struct snd_soc_codec *twl4030_codec;
2115
2116 static int twl4030_soc_probe(struct platform_device *pdev)
2117 {
2118 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2119 struct twl4030_setup_data *setup = socdev->codec_data;
2120 struct snd_soc_codec *codec;
2121 struct twl4030_priv *twl4030;
2122 int ret;
2123
2124 BUG_ON(!twl4030_codec);
2125
2126 codec = twl4030_codec;
2127 twl4030 = codec->private_data;
2128 socdev->card->codec = codec;
2129
2130 /* Configuration for headset ramp delay from setup data */
2131 if (setup) {
2132 unsigned char hs_pop;
2133
2134 if (setup->sysclk)
2135 twl4030->sysclk = setup->sysclk;
2136 else
2137 twl4030->sysclk = 26000;
2138
2139 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2140 hs_pop &= ~TWL4030_RAMP_DELAY;
2141 hs_pop |= (setup->ramp_delay_value << 2);
2142 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2143 } else {
2144 twl4030->sysclk = 26000;
2145 }
2146
2147 /* register pcms */
2148 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2149 if (ret < 0) {
2150 dev_err(&pdev->dev, "failed to create pcms\n");
2151 return ret;
2152 }
2153
2154 snd_soc_add_controls(codec, twl4030_snd_controls,
2155 ARRAY_SIZE(twl4030_snd_controls));
2156 twl4030_add_widgets(codec);
2157
2158 ret = snd_soc_init_card(socdev);
2159 if (ret < 0) {
2160 dev_err(&pdev->dev, "failed to register card\n");
2161 goto card_err;
2162 }
2163
2164 return 0;
2165
2166 card_err:
2167 snd_soc_free_pcms(socdev);
2168 snd_soc_dapm_free(socdev);
2169
2170 return ret;
2171 }
2172
2173 static int twl4030_soc_remove(struct platform_device *pdev)
2174 {
2175 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2176 struct snd_soc_codec *codec = socdev->card->codec;
2177
2178 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2179 snd_soc_free_pcms(socdev);
2180 snd_soc_dapm_free(socdev);
2181 kfree(codec->private_data);
2182 kfree(codec);
2183
2184 return 0;
2185 }
2186
2187 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2188 {
2189 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
2190 struct snd_soc_codec *codec;
2191 struct twl4030_priv *twl4030;
2192 int ret;
2193
2194 if (!pdata || !(pdata->audio_mclk == 19200000 ||
2195 pdata->audio_mclk == 26000000 ||
2196 pdata->audio_mclk == 38400000)) {
2197 dev_err(&pdev->dev, "Invalid platform_data\n");
2198 return -EINVAL;
2199 }
2200
2201 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2202 if (twl4030 == NULL) {
2203 dev_err(&pdev->dev, "Can not allocate memroy\n");
2204 return -ENOMEM;
2205 }
2206
2207 codec = &twl4030->codec;
2208 codec->private_data = twl4030;
2209 codec->dev = &pdev->dev;
2210 twl4030_dai[0].dev = &pdev->dev;
2211 twl4030_dai[1].dev = &pdev->dev;
2212
2213 mutex_init(&codec->mutex);
2214 INIT_LIST_HEAD(&codec->dapm_widgets);
2215 INIT_LIST_HEAD(&codec->dapm_paths);
2216
2217 codec->name = "twl4030";
2218 codec->owner = THIS_MODULE;
2219 codec->read = twl4030_read_reg_cache;
2220 codec->write = twl4030_write;
2221 codec->set_bias_level = twl4030_set_bias_level;
2222 codec->dai = twl4030_dai;
2223 codec->num_dai = ARRAY_SIZE(twl4030_dai),
2224 codec->reg_cache_size = sizeof(twl4030_reg);
2225 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2226 GFP_KERNEL);
2227 if (codec->reg_cache == NULL) {
2228 ret = -ENOMEM;
2229 goto error_cache;
2230 }
2231
2232 platform_set_drvdata(pdev, twl4030);
2233 twl4030_codec = codec;
2234
2235 /* Set the defaults, and power up the codec */
2236 twl4030_init_chip(codec);
2237 codec->bias_level = SND_SOC_BIAS_OFF;
2238 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2239
2240 ret = snd_soc_register_codec(codec);
2241 if (ret != 0) {
2242 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2243 goto error_codec;
2244 }
2245
2246 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2247 if (ret != 0) {
2248 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2249 snd_soc_unregister_codec(codec);
2250 goto error_codec;
2251 }
2252
2253 return 0;
2254
2255 error_codec:
2256 twl4030_power_down(codec);
2257 kfree(codec->reg_cache);
2258 error_cache:
2259 kfree(twl4030);
2260 return ret;
2261 }
2262
2263 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2264 {
2265 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
2266
2267 kfree(twl4030);
2268
2269 twl4030_codec = NULL;
2270 return 0;
2271 }
2272
2273 MODULE_ALIAS("platform:twl4030_codec_audio");
2274
2275 static struct platform_driver twl4030_codec_driver = {
2276 .probe = twl4030_codec_probe,
2277 .remove = __devexit_p(twl4030_codec_remove),
2278 .driver = {
2279 .name = "twl4030_codec_audio",
2280 .owner = THIS_MODULE,
2281 },
2282 };
2283
2284 static int __init twl4030_modinit(void)
2285 {
2286 return platform_driver_register(&twl4030_codec_driver);
2287 }
2288 module_init(twl4030_modinit);
2289
2290 static void __exit twl4030_exit(void)
2291 {
2292 platform_driver_unregister(&twl4030_codec_driver);
2293 }
2294 module_exit(twl4030_exit);
2295
2296 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2297 .probe = twl4030_soc_probe,
2298 .remove = twl4030_soc_remove,
2299 .suspend = twl4030_soc_suspend,
2300 .resume = twl4030_soc_resume,
2301 };
2302 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2303
2304 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2305 MODULE_AUTHOR("Steve Sakoman");
2306 MODULE_LICENSE("GPL");
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