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ASoC: TWL4030: Remove wrapper for power down
[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / twl4030.c
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x00, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0f, /* REG_ATXL1PGA (0xA) */
55 0x0f, /* REG_ATXR1PGA (0xB) */
56 0x0f, /* REG_AVTXL2PGA (0xC) */
57 0x0f, /* REG_AVTXR2PGA (0xD) */
58 0x00, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x3f, /* REG_ARXR1PGA (0x10) */
61 0x3f, /* REG_ARXL1PGA (0x11) */
62 0x3f, /* REG_ARXR2PGA (0x12) */
63 0x3f, /* REG_ARXL2PGA (0x13) */
64 0x25, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x00, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x55, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x00, /* REG_HS_SEL (0x22) */
79 0x00, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x05, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x13, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x79, /* REG_DTMF_TONOFF (0x35) */
98 0x11, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x06, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x32, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
119 };
120
121 /* codec private data */
122 struct twl4030_priv {
123 struct snd_soc_codec codec;
124
125 unsigned int codec_powered;
126
127 /* reference counts of AIF/APLL users */
128 unsigned int apll_enabled;
129
130 struct snd_pcm_substream *master_substream;
131 struct snd_pcm_substream *slave_substream;
132
133 unsigned int configured;
134 unsigned int rate;
135 unsigned int sample_bits;
136 unsigned int channels;
137
138 unsigned int sysclk;
139
140 /* Output (with associated amp) states */
141 u8 hsl_enabled, hsr_enabled;
142 u8 earpiece_enabled;
143 u8 predrivel_enabled, predriver_enabled;
144 u8 carkitl_enabled, carkitr_enabled;
145 };
146
147 /*
148 * read twl4030 register cache
149 */
150 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
151 unsigned int reg)
152 {
153 u8 *cache = codec->reg_cache;
154
155 if (reg >= TWL4030_CACHEREGNUM)
156 return -EIO;
157
158 return cache[reg];
159 }
160
161 /*
162 * write twl4030 register cache
163 */
164 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
165 u8 reg, u8 value)
166 {
167 u8 *cache = codec->reg_cache;
168
169 if (reg >= TWL4030_CACHEREGNUM)
170 return;
171 cache[reg] = value;
172 }
173
174 /*
175 * write to the twl4030 register space
176 */
177 static int twl4030_write(struct snd_soc_codec *codec,
178 unsigned int reg, unsigned int value)
179 {
180 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
181 int write_to_reg = 0;
182
183 twl4030_write_reg_cache(codec, reg, value);
184 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
185 /* Decide if the given register can be written */
186 switch (reg) {
187 case TWL4030_REG_EAR_CTL:
188 if (twl4030->earpiece_enabled)
189 write_to_reg = 1;
190 break;
191 case TWL4030_REG_PREDL_CTL:
192 if (twl4030->predrivel_enabled)
193 write_to_reg = 1;
194 break;
195 case TWL4030_REG_PREDR_CTL:
196 if (twl4030->predriver_enabled)
197 write_to_reg = 1;
198 break;
199 case TWL4030_REG_PRECKL_CTL:
200 if (twl4030->carkitl_enabled)
201 write_to_reg = 1;
202 break;
203 case TWL4030_REG_PRECKR_CTL:
204 if (twl4030->carkitr_enabled)
205 write_to_reg = 1;
206 break;
207 case TWL4030_REG_HS_GAIN_SET:
208 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
209 write_to_reg = 1;
210 break;
211 default:
212 /* All other register can be written */
213 write_to_reg = 1;
214 break;
215 }
216 if (write_to_reg)
217 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
218 value, reg);
219 }
220 return 0;
221 }
222
223 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
224 {
225 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
226 int mode;
227
228 if (enable == twl4030->codec_powered)
229 return;
230
231 if (enable)
232 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
233 else
234 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
235
236 if (mode >= 0) {
237 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
238 twl4030->codec_powered = enable;
239 }
240
241 /* REVISIT: this delay is present in TI sample drivers */
242 /* but there seems to be no TRM requirement for it */
243 udelay(10);
244 }
245
246 static void twl4030_init_chip(struct snd_soc_codec *codec)
247 {
248 u8 *cache = codec->reg_cache;
249 int i;
250
251 /* clear CODECPDZ prior to setting register defaults */
252 twl4030_codec_enable(codec, 0);
253
254 /* set all audio section registers to reasonable defaults */
255 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
256 if (i != TWL4030_REG_APLL_CTL)
257 twl4030_write(codec, i, cache[i]);
258
259 }
260
261 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
262 {
263 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
264 int status = -1;
265
266 if (enable) {
267 twl4030->apll_enabled++;
268 if (twl4030->apll_enabled == 1)
269 status = twl4030_codec_enable_resource(
270 TWL4030_CODEC_RES_APLL);
271 } else {
272 twl4030->apll_enabled--;
273 if (!twl4030->apll_enabled)
274 status = twl4030_codec_disable_resource(
275 TWL4030_CODEC_RES_APLL);
276 }
277
278 if (status >= 0)
279 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
280 }
281
282 static void twl4030_power_up(struct snd_soc_codec *codec)
283 {
284 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
285 u8 anamicl, regmisc1, byte;
286 int i = 0;
287
288 if (twl4030->codec_powered)
289 return;
290
291 /* set CODECPDZ to turn on codec */
292 twl4030_codec_enable(codec, 1);
293
294 /* initiate offset cancellation */
295 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
296 twl4030_write(codec, TWL4030_REG_ANAMICL,
297 anamicl | TWL4030_CNCL_OFFSET_START);
298
299 /* wait for offset cancellation to complete */
300 do {
301 /* this takes a little while, so don't slam i2c */
302 udelay(2000);
303 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
304 TWL4030_REG_ANAMICL);
305 } while ((i++ < 100) &&
306 ((byte & TWL4030_CNCL_OFFSET_START) ==
307 TWL4030_CNCL_OFFSET_START));
308
309 /* Make sure that the reg_cache has the same value as the HW */
310 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
311
312 /* anti-pop when changing analog gain */
313 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
314 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
315 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
316
317 /* toggle CODECPDZ as per TRM */
318 twl4030_codec_enable(codec, 0);
319 twl4030_codec_enable(codec, 1);
320 }
321
322 /* Earpiece */
323 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
324 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
325 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
326 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
327 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
328 };
329
330 /* PreDrive Left */
331 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
332 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
333 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
334 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
335 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
336 };
337
338 /* PreDrive Right */
339 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
340 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
341 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
342 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
343 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
344 };
345
346 /* Headset Left */
347 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
348 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
349 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
350 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
351 };
352
353 /* Headset Right */
354 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
355 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
356 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
357 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
358 };
359
360 /* Carkit Left */
361 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
362 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
363 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
364 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
365 };
366
367 /* Carkit Right */
368 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
369 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
370 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
371 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
372 };
373
374 /* Handsfree Left */
375 static const char *twl4030_handsfreel_texts[] =
376 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
377
378 static const struct soc_enum twl4030_handsfreel_enum =
379 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
380 ARRAY_SIZE(twl4030_handsfreel_texts),
381 twl4030_handsfreel_texts);
382
383 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
384 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
385
386 /* Handsfree Left virtual mute */
387 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
388 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
389
390 /* Handsfree Right */
391 static const char *twl4030_handsfreer_texts[] =
392 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
393
394 static const struct soc_enum twl4030_handsfreer_enum =
395 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
396 ARRAY_SIZE(twl4030_handsfreer_texts),
397 twl4030_handsfreer_texts);
398
399 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
400 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
401
402 /* Handsfree Right virtual mute */
403 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
404 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
405
406 /* Vibra */
407 /* Vibra audio path selection */
408 static const char *twl4030_vibra_texts[] =
409 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
410
411 static const struct soc_enum twl4030_vibra_enum =
412 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
413 ARRAY_SIZE(twl4030_vibra_texts),
414 twl4030_vibra_texts);
415
416 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
417 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
418
419 /* Vibra path selection: local vibrator (PWM) or audio driven */
420 static const char *twl4030_vibrapath_texts[] =
421 {"Local vibrator", "Audio"};
422
423 static const struct soc_enum twl4030_vibrapath_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
425 ARRAY_SIZE(twl4030_vibrapath_texts),
426 twl4030_vibrapath_texts);
427
428 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
429 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
430
431 /* Left analog microphone selection */
432 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
433 SOC_DAPM_SINGLE("Main Mic Capture Switch",
434 TWL4030_REG_ANAMICL, 0, 1, 0),
435 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
436 TWL4030_REG_ANAMICL, 1, 1, 0),
437 SOC_DAPM_SINGLE("AUXL Capture Switch",
438 TWL4030_REG_ANAMICL, 2, 1, 0),
439 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
440 TWL4030_REG_ANAMICL, 3, 1, 0),
441 };
442
443 /* Right analog microphone selection */
444 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
445 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
446 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
447 };
448
449 /* TX1 L/R Analog/Digital microphone selection */
450 static const char *twl4030_micpathtx1_texts[] =
451 {"Analog", "Digimic0"};
452
453 static const struct soc_enum twl4030_micpathtx1_enum =
454 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
455 ARRAY_SIZE(twl4030_micpathtx1_texts),
456 twl4030_micpathtx1_texts);
457
458 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
459 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
460
461 /* TX2 L/R Analog/Digital microphone selection */
462 static const char *twl4030_micpathtx2_texts[] =
463 {"Analog", "Digimic1"};
464
465 static const struct soc_enum twl4030_micpathtx2_enum =
466 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
467 ARRAY_SIZE(twl4030_micpathtx2_texts),
468 twl4030_micpathtx2_texts);
469
470 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
471 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
472
473 /* Analog bypass for AudioR1 */
474 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
475 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
476
477 /* Analog bypass for AudioL1 */
478 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
479 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
480
481 /* Analog bypass for AudioR2 */
482 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
483 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
484
485 /* Analog bypass for AudioL2 */
486 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
487 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
488
489 /* Analog bypass for Voice */
490 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
491 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
492
493 /* Digital bypass gain, 0 mutes the bypass */
494 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
495 TLV_DB_RANGE_HEAD(2),
496 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
497 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
498 };
499
500 /* Digital bypass left (TX1L -> RX2L) */
501 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
502 SOC_DAPM_SINGLE_TLV("Volume",
503 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
504 twl4030_dapm_dbypass_tlv);
505
506 /* Digital bypass right (TX1R -> RX2R) */
507 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
508 SOC_DAPM_SINGLE_TLV("Volume",
509 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
510 twl4030_dapm_dbypass_tlv);
511
512 /*
513 * Voice Sidetone GAIN volume control:
514 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
515 */
516 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
517
518 /* Digital bypass voice: sidetone (VUL -> VDL)*/
519 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
520 SOC_DAPM_SINGLE_TLV("Volume",
521 TWL4030_REG_VSTPGA, 0, 0x29, 0,
522 twl4030_dapm_dbypassv_tlv);
523
524 static int micpath_event(struct snd_soc_dapm_widget *w,
525 struct snd_kcontrol *kcontrol, int event)
526 {
527 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
528 unsigned char adcmicsel, micbias_ctl;
529
530 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
531 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
532 /* Prepare the bits for the given TX path:
533 * shift_l == 0: TX1 microphone path
534 * shift_l == 2: TX2 microphone path */
535 if (e->shift_l) {
536 /* TX2 microphone path */
537 if (adcmicsel & TWL4030_TX2IN_SEL)
538 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
539 else
540 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
541 } else {
542 /* TX1 microphone path */
543 if (adcmicsel & TWL4030_TX1IN_SEL)
544 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
545 else
546 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
547 }
548
549 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
550
551 return 0;
552 }
553
554 /*
555 * Output PGA builder:
556 * Handle the muting and unmuting of the given output (turning off the
557 * amplifier associated with the output pin)
558 * On mute bypass the reg_cache and write 0 to the register
559 * On unmute: restore the register content from the reg_cache
560 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
561 */
562 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
563 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
564 struct snd_kcontrol *kcontrol, int event) \
565 { \
566 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
567 \
568 switch (event) { \
569 case SND_SOC_DAPM_POST_PMU: \
570 twl4030->pin_name##_enabled = 1; \
571 twl4030_write(w->codec, reg, \
572 twl4030_read_reg_cache(w->codec, reg)); \
573 break; \
574 case SND_SOC_DAPM_POST_PMD: \
575 twl4030->pin_name##_enabled = 0; \
576 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
577 0, reg); \
578 break; \
579 } \
580 return 0; \
581 }
582
583 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
584 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
585 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
586 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
587 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
588
589 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
590 {
591 unsigned char hs_ctl;
592
593 hs_ctl = twl4030_read_reg_cache(codec, reg);
594
595 if (ramp) {
596 /* HF ramp-up */
597 hs_ctl |= TWL4030_HF_CTL_REF_EN;
598 twl4030_write(codec, reg, hs_ctl);
599 udelay(10);
600 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
601 twl4030_write(codec, reg, hs_ctl);
602 udelay(40);
603 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
604 hs_ctl |= TWL4030_HF_CTL_HB_EN;
605 twl4030_write(codec, reg, hs_ctl);
606 } else {
607 /* HF ramp-down */
608 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
609 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
610 twl4030_write(codec, reg, hs_ctl);
611 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
612 twl4030_write(codec, reg, hs_ctl);
613 udelay(40);
614 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
615 twl4030_write(codec, reg, hs_ctl);
616 }
617 }
618
619 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
620 struct snd_kcontrol *kcontrol, int event)
621 {
622 switch (event) {
623 case SND_SOC_DAPM_POST_PMU:
624 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
625 break;
626 case SND_SOC_DAPM_POST_PMD:
627 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
628 break;
629 }
630 return 0;
631 }
632
633 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
634 struct snd_kcontrol *kcontrol, int event)
635 {
636 switch (event) {
637 case SND_SOC_DAPM_POST_PMU:
638 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
639 break;
640 case SND_SOC_DAPM_POST_PMD:
641 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
642 break;
643 }
644 return 0;
645 }
646
647 static int vibramux_event(struct snd_soc_dapm_widget *w,
648 struct snd_kcontrol *kcontrol, int event)
649 {
650 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
651 return 0;
652 }
653
654 static int apll_event(struct snd_soc_dapm_widget *w,
655 struct snd_kcontrol *kcontrol, int event)
656 {
657 switch (event) {
658 case SND_SOC_DAPM_PRE_PMU:
659 twl4030_apll_enable(w->codec, 1);
660 break;
661 case SND_SOC_DAPM_POST_PMD:
662 twl4030_apll_enable(w->codec, 0);
663 break;
664 }
665 return 0;
666 }
667
668 static int aif_event(struct snd_soc_dapm_widget *w,
669 struct snd_kcontrol *kcontrol, int event)
670 {
671 u8 audio_if;
672
673 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
674 switch (event) {
675 case SND_SOC_DAPM_PRE_PMU:
676 /* Enable AIF */
677 /* enable the PLL before we use it to clock the DAI */
678 twl4030_apll_enable(w->codec, 1);
679
680 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
681 audio_if | TWL4030_AIF_EN);
682 break;
683 case SND_SOC_DAPM_POST_PMD:
684 /* disable the DAI before we stop it's source PLL */
685 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
686 audio_if & ~TWL4030_AIF_EN);
687 twl4030_apll_enable(w->codec, 0);
688 break;
689 }
690 return 0;
691 }
692
693 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
694 {
695 struct snd_soc_device *socdev = codec->socdev;
696 struct twl4030_setup_data *setup = socdev->codec_data;
697
698 unsigned char hs_gain, hs_pop;
699 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
700 /* Base values for ramp delay calculation: 2^19 - 2^26 */
701 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
702 8388608, 16777216, 33554432, 67108864};
703
704 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
705 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
706
707 /* Enable external mute control, this dramatically reduces
708 * the pop-noise */
709 if (setup && setup->hs_extmute) {
710 if (setup->set_hs_extmute) {
711 setup->set_hs_extmute(1);
712 } else {
713 hs_pop |= TWL4030_EXTMUTE;
714 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
715 }
716 }
717
718 if (ramp) {
719 /* Headset ramp-up according to the TRM */
720 hs_pop |= TWL4030_VMID_EN;
721 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
722 /* Actually write to the register */
723 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
724 hs_gain,
725 TWL4030_REG_HS_GAIN_SET);
726 hs_pop |= TWL4030_RAMP_EN;
727 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
728 /* Wait ramp delay time + 1, so the VMID can settle */
729 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
730 twl4030->sysclk) + 1);
731 } else {
732 /* Headset ramp-down _not_ according to
733 * the TRM, but in a way that it is working */
734 hs_pop &= ~TWL4030_RAMP_EN;
735 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
736 /* Wait ramp delay time + 1, so the VMID can settle */
737 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
738 twl4030->sysclk) + 1);
739 /* Bypass the reg_cache to mute the headset */
740 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
741 hs_gain & (~0x0f),
742 TWL4030_REG_HS_GAIN_SET);
743
744 hs_pop &= ~TWL4030_VMID_EN;
745 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
746 }
747
748 /* Disable external mute */
749 if (setup && setup->hs_extmute) {
750 if (setup->set_hs_extmute) {
751 setup->set_hs_extmute(0);
752 } else {
753 hs_pop &= ~TWL4030_EXTMUTE;
754 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
755 }
756 }
757 }
758
759 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
760 struct snd_kcontrol *kcontrol, int event)
761 {
762 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
763
764 switch (event) {
765 case SND_SOC_DAPM_POST_PMU:
766 /* Do the ramp-up only once */
767 if (!twl4030->hsr_enabled)
768 headset_ramp(w->codec, 1);
769
770 twl4030->hsl_enabled = 1;
771 break;
772 case SND_SOC_DAPM_POST_PMD:
773 /* Do the ramp-down only if both headsetL/R is disabled */
774 if (!twl4030->hsr_enabled)
775 headset_ramp(w->codec, 0);
776
777 twl4030->hsl_enabled = 0;
778 break;
779 }
780 return 0;
781 }
782
783 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
784 struct snd_kcontrol *kcontrol, int event)
785 {
786 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
787
788 switch (event) {
789 case SND_SOC_DAPM_POST_PMU:
790 /* Do the ramp-up only once */
791 if (!twl4030->hsl_enabled)
792 headset_ramp(w->codec, 1);
793
794 twl4030->hsr_enabled = 1;
795 break;
796 case SND_SOC_DAPM_POST_PMD:
797 /* Do the ramp-down only if both headsetL/R is disabled */
798 if (!twl4030->hsl_enabled)
799 headset_ramp(w->codec, 0);
800
801 twl4030->hsr_enabled = 0;
802 break;
803 }
804 return 0;
805 }
806
807 /*
808 * Some of the gain controls in TWL (mostly those which are associated with
809 * the outputs) are implemented in an interesting way:
810 * 0x0 : Power down (mute)
811 * 0x1 : 6dB
812 * 0x2 : 0 dB
813 * 0x3 : -6 dB
814 * Inverting not going to help with these.
815 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
816 */
817 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
818 xinvert, tlv_array) \
819 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
820 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
821 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
822 .tlv.p = (tlv_array), \
823 .info = snd_soc_info_volsw, \
824 .get = snd_soc_get_volsw_twl4030, \
825 .put = snd_soc_put_volsw_twl4030, \
826 .private_value = (unsigned long)&(struct soc_mixer_control) \
827 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
828 .max = xmax, .invert = xinvert} }
829 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
830 xinvert, tlv_array) \
831 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
832 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
833 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
834 .tlv.p = (tlv_array), \
835 .info = snd_soc_info_volsw_2r, \
836 .get = snd_soc_get_volsw_r2_twl4030,\
837 .put = snd_soc_put_volsw_r2_twl4030, \
838 .private_value = (unsigned long)&(struct soc_mixer_control) \
839 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
840 .rshift = xshift, .max = xmax, .invert = xinvert} }
841 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
842 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
843 xinvert, tlv_array)
844
845 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
846 struct snd_ctl_elem_value *ucontrol)
847 {
848 struct soc_mixer_control *mc =
849 (struct soc_mixer_control *)kcontrol->private_value;
850 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
851 unsigned int reg = mc->reg;
852 unsigned int shift = mc->shift;
853 unsigned int rshift = mc->rshift;
854 int max = mc->max;
855 int mask = (1 << fls(max)) - 1;
856
857 ucontrol->value.integer.value[0] =
858 (snd_soc_read(codec, reg) >> shift) & mask;
859 if (ucontrol->value.integer.value[0])
860 ucontrol->value.integer.value[0] =
861 max + 1 - ucontrol->value.integer.value[0];
862
863 if (shift != rshift) {
864 ucontrol->value.integer.value[1] =
865 (snd_soc_read(codec, reg) >> rshift) & mask;
866 if (ucontrol->value.integer.value[1])
867 ucontrol->value.integer.value[1] =
868 max + 1 - ucontrol->value.integer.value[1];
869 }
870
871 return 0;
872 }
873
874 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
875 struct snd_ctl_elem_value *ucontrol)
876 {
877 struct soc_mixer_control *mc =
878 (struct soc_mixer_control *)kcontrol->private_value;
879 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
880 unsigned int reg = mc->reg;
881 unsigned int shift = mc->shift;
882 unsigned int rshift = mc->rshift;
883 int max = mc->max;
884 int mask = (1 << fls(max)) - 1;
885 unsigned short val, val2, val_mask;
886
887 val = (ucontrol->value.integer.value[0] & mask);
888
889 val_mask = mask << shift;
890 if (val)
891 val = max + 1 - val;
892 val = val << shift;
893 if (shift != rshift) {
894 val2 = (ucontrol->value.integer.value[1] & mask);
895 val_mask |= mask << rshift;
896 if (val2)
897 val2 = max + 1 - val2;
898 val |= val2 << rshift;
899 }
900 return snd_soc_update_bits(codec, reg, val_mask, val);
901 }
902
903 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
904 struct snd_ctl_elem_value *ucontrol)
905 {
906 struct soc_mixer_control *mc =
907 (struct soc_mixer_control *)kcontrol->private_value;
908 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
909 unsigned int reg = mc->reg;
910 unsigned int reg2 = mc->rreg;
911 unsigned int shift = mc->shift;
912 int max = mc->max;
913 int mask = (1<<fls(max))-1;
914
915 ucontrol->value.integer.value[0] =
916 (snd_soc_read(codec, reg) >> shift) & mask;
917 ucontrol->value.integer.value[1] =
918 (snd_soc_read(codec, reg2) >> shift) & mask;
919
920 if (ucontrol->value.integer.value[0])
921 ucontrol->value.integer.value[0] =
922 max + 1 - ucontrol->value.integer.value[0];
923 if (ucontrol->value.integer.value[1])
924 ucontrol->value.integer.value[1] =
925 max + 1 - ucontrol->value.integer.value[1];
926
927 return 0;
928 }
929
930 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
931 struct snd_ctl_elem_value *ucontrol)
932 {
933 struct soc_mixer_control *mc =
934 (struct soc_mixer_control *)kcontrol->private_value;
935 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
936 unsigned int reg = mc->reg;
937 unsigned int reg2 = mc->rreg;
938 unsigned int shift = mc->shift;
939 int max = mc->max;
940 int mask = (1 << fls(max)) - 1;
941 int err;
942 unsigned short val, val2, val_mask;
943
944 val_mask = mask << shift;
945 val = (ucontrol->value.integer.value[0] & mask);
946 val2 = (ucontrol->value.integer.value[1] & mask);
947
948 if (val)
949 val = max + 1 - val;
950 if (val2)
951 val2 = max + 1 - val2;
952
953 val = val << shift;
954 val2 = val2 << shift;
955
956 err = snd_soc_update_bits(codec, reg, val_mask, val);
957 if (err < 0)
958 return err;
959
960 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
961 return err;
962 }
963
964 /* Codec operation modes */
965 static const char *twl4030_op_modes_texts[] = {
966 "Option 2 (voice/audio)", "Option 1 (audio)"
967 };
968
969 static const struct soc_enum twl4030_op_modes_enum =
970 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
971 ARRAY_SIZE(twl4030_op_modes_texts),
972 twl4030_op_modes_texts);
973
974 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
975 struct snd_ctl_elem_value *ucontrol)
976 {
977 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
978 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
979 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
980 unsigned short val;
981 unsigned short mask, bitmask;
982
983 if (twl4030->configured) {
984 printk(KERN_ERR "twl4030 operation mode cannot be "
985 "changed on-the-fly\n");
986 return -EBUSY;
987 }
988
989 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
990 ;
991 if (ucontrol->value.enumerated.item[0] > e->max - 1)
992 return -EINVAL;
993
994 val = ucontrol->value.enumerated.item[0] << e->shift_l;
995 mask = (bitmask - 1) << e->shift_l;
996 if (e->shift_l != e->shift_r) {
997 if (ucontrol->value.enumerated.item[1] > e->max - 1)
998 return -EINVAL;
999 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1000 mask |= (bitmask - 1) << e->shift_r;
1001 }
1002
1003 return snd_soc_update_bits(codec, e->reg, mask, val);
1004 }
1005
1006 /*
1007 * FGAIN volume control:
1008 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1009 */
1010 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1011
1012 /*
1013 * CGAIN volume control:
1014 * 0 dB to 12 dB in 6 dB steps
1015 * value 2 and 3 means 12 dB
1016 */
1017 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1018
1019 /*
1020 * Voice Downlink GAIN volume control:
1021 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1022 */
1023 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1024
1025 /*
1026 * Analog playback gain
1027 * -24 dB to 12 dB in 2 dB steps
1028 */
1029 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1030
1031 /*
1032 * Gain controls tied to outputs
1033 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1034 */
1035 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1036
1037 /*
1038 * Gain control for earpiece amplifier
1039 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1040 */
1041 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1042
1043 /*
1044 * Capture gain after the ADCs
1045 * from 0 dB to 31 dB in 1 dB steps
1046 */
1047 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1048
1049 /*
1050 * Gain control for input amplifiers
1051 * 0 dB to 30 dB in 6 dB steps
1052 */
1053 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1054
1055 /* AVADC clock priority */
1056 static const char *twl4030_avadc_clk_priority_texts[] = {
1057 "Voice high priority", "HiFi high priority"
1058 };
1059
1060 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1061 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1062 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1063 twl4030_avadc_clk_priority_texts);
1064
1065 static const char *twl4030_rampdelay_texts[] = {
1066 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1067 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1068 "3495/2581/1748 ms"
1069 };
1070
1071 static const struct soc_enum twl4030_rampdelay_enum =
1072 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1073 ARRAY_SIZE(twl4030_rampdelay_texts),
1074 twl4030_rampdelay_texts);
1075
1076 /* Vibra H-bridge direction mode */
1077 static const char *twl4030_vibradirmode_texts[] = {
1078 "Vibra H-bridge direction", "Audio data MSB",
1079 };
1080
1081 static const struct soc_enum twl4030_vibradirmode_enum =
1082 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1083 ARRAY_SIZE(twl4030_vibradirmode_texts),
1084 twl4030_vibradirmode_texts);
1085
1086 /* Vibra H-bridge direction */
1087 static const char *twl4030_vibradir_texts[] = {
1088 "Positive polarity", "Negative polarity",
1089 };
1090
1091 static const struct soc_enum twl4030_vibradir_enum =
1092 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1093 ARRAY_SIZE(twl4030_vibradir_texts),
1094 twl4030_vibradir_texts);
1095
1096 /* Digimic Left and right swapping */
1097 static const char *twl4030_digimicswap_texts[] = {
1098 "Not swapped", "Swapped",
1099 };
1100
1101 static const struct soc_enum twl4030_digimicswap_enum =
1102 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1103 ARRAY_SIZE(twl4030_digimicswap_texts),
1104 twl4030_digimicswap_texts);
1105
1106 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1107 /* Codec operation mode control */
1108 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1109 snd_soc_get_enum_double,
1110 snd_soc_put_twl4030_opmode_enum_double),
1111
1112 /* Common playback gain controls */
1113 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1114 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1115 0, 0x3f, 0, digital_fine_tlv),
1116 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1117 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1118 0, 0x3f, 0, digital_fine_tlv),
1119
1120 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1121 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1122 6, 0x2, 0, digital_coarse_tlv),
1123 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1124 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1125 6, 0x2, 0, digital_coarse_tlv),
1126
1127 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1128 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1129 3, 0x12, 1, analog_tlv),
1130 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1131 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1132 3, 0x12, 1, analog_tlv),
1133 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1134 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1135 1, 1, 0),
1136 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1137 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1138 1, 1, 0),
1139
1140 /* Common voice downlink gain controls */
1141 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1142 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1143
1144 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1145 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1146
1147 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1148 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1149
1150 /* Separate output gain controls */
1151 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1152 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1153 4, 3, 0, output_tvl),
1154
1155 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1156 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1157
1158 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1159 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1160 4, 3, 0, output_tvl),
1161
1162 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
1163 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
1164
1165 /* Common capture gain controls */
1166 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1167 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1168 0, 0x1f, 0, digital_capture_tlv),
1169 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1170 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1171 0, 0x1f, 0, digital_capture_tlv),
1172
1173 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1174 0, 3, 5, 0, input_gain_tlv),
1175
1176 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1177
1178 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1179
1180 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1181 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1182
1183 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1184 };
1185
1186 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1187 /* Left channel inputs */
1188 SND_SOC_DAPM_INPUT("MAINMIC"),
1189 SND_SOC_DAPM_INPUT("HSMIC"),
1190 SND_SOC_DAPM_INPUT("AUXL"),
1191 SND_SOC_DAPM_INPUT("CARKITMIC"),
1192 /* Right channel inputs */
1193 SND_SOC_DAPM_INPUT("SUBMIC"),
1194 SND_SOC_DAPM_INPUT("AUXR"),
1195 /* Digital microphones (Stereo) */
1196 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1197 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1198
1199 /* Outputs */
1200 SND_SOC_DAPM_OUTPUT("EARPIECE"),
1201 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1202 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1203 SND_SOC_DAPM_OUTPUT("HSOL"),
1204 SND_SOC_DAPM_OUTPUT("HSOR"),
1205 SND_SOC_DAPM_OUTPUT("CARKITL"),
1206 SND_SOC_DAPM_OUTPUT("CARKITR"),
1207 SND_SOC_DAPM_OUTPUT("HFL"),
1208 SND_SOC_DAPM_OUTPUT("HFR"),
1209 SND_SOC_DAPM_OUTPUT("VIBRA"),
1210
1211 /* AIF and APLL clocks for running DAIs (including loopback) */
1212 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1213 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1214 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1215
1216 /* DACs */
1217 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
1218 SND_SOC_NOPM, 0, 0),
1219 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
1220 SND_SOC_NOPM, 0, 0),
1221 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
1222 SND_SOC_NOPM, 0, 0),
1223 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
1224 SND_SOC_NOPM, 0, 0),
1225 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
1226 SND_SOC_NOPM, 0, 0),
1227
1228 /* Analog bypasses */
1229 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1230 &twl4030_dapm_abypassr1_control),
1231 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1232 &twl4030_dapm_abypassl1_control),
1233 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1234 &twl4030_dapm_abypassr2_control),
1235 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1236 &twl4030_dapm_abypassl2_control),
1237 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1238 &twl4030_dapm_abypassv_control),
1239
1240 /* Master analog loopback switch */
1241 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1242 NULL, 0),
1243
1244 /* Digital bypasses */
1245 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1246 &twl4030_dapm_dbypassl_control),
1247 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1248 &twl4030_dapm_dbypassr_control),
1249 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1250 &twl4030_dapm_dbypassv_control),
1251
1252 /* Digital mixers, power control for the physical DACs */
1253 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1254 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1255 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1256 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1257 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1258 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1259 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1260 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1261 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1262 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1263
1264 /* Analog mixers, power control for the physical PGAs */
1265 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1266 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1267 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1268 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1269 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1270 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1271 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1272 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1273 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1274 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1275
1276 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1277 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1278
1279 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1280 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1281
1282 /* Output MIXER controls */
1283 /* Earpiece */
1284 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1285 &twl4030_dapm_earpiece_controls[0],
1286 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1287 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1288 0, 0, NULL, 0, earpiecepga_event,
1289 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1290 /* PreDrivL/R */
1291 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1292 &twl4030_dapm_predrivel_controls[0],
1293 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1294 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1295 0, 0, NULL, 0, predrivelpga_event,
1296 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1297 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1298 &twl4030_dapm_predriver_controls[0],
1299 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1300 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1301 0, 0, NULL, 0, predriverpga_event,
1302 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1303 /* HeadsetL/R */
1304 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1305 &twl4030_dapm_hsol_controls[0],
1306 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1307 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1308 0, 0, NULL, 0, headsetlpga_event,
1309 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1310 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1311 &twl4030_dapm_hsor_controls[0],
1312 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1313 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1314 0, 0, NULL, 0, headsetrpga_event,
1315 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1316 /* CarkitL/R */
1317 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1318 &twl4030_dapm_carkitl_controls[0],
1319 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1320 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1321 0, 0, NULL, 0, carkitlpga_event,
1322 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1323 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1324 &twl4030_dapm_carkitr_controls[0],
1325 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1326 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1327 0, 0, NULL, 0, carkitrpga_event,
1328 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1329
1330 /* Output MUX controls */
1331 /* HandsfreeL/R */
1332 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1333 &twl4030_dapm_handsfreel_control),
1334 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1335 &twl4030_dapm_handsfreelmute_control),
1336 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1337 0, 0, NULL, 0, handsfreelpga_event,
1338 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1339 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1340 &twl4030_dapm_handsfreer_control),
1341 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1342 &twl4030_dapm_handsfreermute_control),
1343 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1344 0, 0, NULL, 0, handsfreerpga_event,
1345 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1346 /* Vibra */
1347 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1348 &twl4030_dapm_vibra_control, vibramux_event,
1349 SND_SOC_DAPM_PRE_PMU),
1350 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1351 &twl4030_dapm_vibrapath_control),
1352
1353 /* Introducing four virtual ADC, since TWL4030 have four channel for
1354 capture */
1355 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1356 SND_SOC_NOPM, 0, 0),
1357 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1358 SND_SOC_NOPM, 0, 0),
1359 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1360 SND_SOC_NOPM, 0, 0),
1361 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1362 SND_SOC_NOPM, 0, 0),
1363
1364 /* Analog/Digital mic path selection.
1365 TX1 Left/Right: either analog Left/Right or Digimic0
1366 TX2 Left/Right: either analog Left/Right or Digimic1 */
1367 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1368 &twl4030_dapm_micpathtx1_control, micpath_event,
1369 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1370 SND_SOC_DAPM_POST_REG),
1371 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1372 &twl4030_dapm_micpathtx2_control, micpath_event,
1373 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1374 SND_SOC_DAPM_POST_REG),
1375
1376 /* Analog input mixers for the capture amplifiers */
1377 SND_SOC_DAPM_MIXER("Analog Left",
1378 TWL4030_REG_ANAMICL, 4, 0,
1379 &twl4030_dapm_analoglmic_controls[0],
1380 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1381 SND_SOC_DAPM_MIXER("Analog Right",
1382 TWL4030_REG_ANAMICR, 4, 0,
1383 &twl4030_dapm_analogrmic_controls[0],
1384 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1385
1386 SND_SOC_DAPM_PGA("ADC Physical Left",
1387 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1388 SND_SOC_DAPM_PGA("ADC Physical Right",
1389 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1390
1391 SND_SOC_DAPM_PGA("Digimic0 Enable",
1392 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1393 SND_SOC_DAPM_PGA("Digimic1 Enable",
1394 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1395
1396 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1397 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1398 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1399
1400 };
1401
1402 static const struct snd_soc_dapm_route intercon[] = {
1403 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1404 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1405 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1406 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1407 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1408
1409 /* Supply for the digital part (APLL) */
1410 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1411
1412 {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
1413 {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
1414 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1415 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1416
1417 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1418 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1419 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1420 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1421 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1422
1423 /* Internal playback routings */
1424 /* Earpiece */
1425 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1426 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1427 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1428 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1429 {"Earpiece PGA", NULL, "Earpiece Mixer"},
1430 /* PreDrivL */
1431 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1432 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1433 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1434 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1435 {"PredriveL PGA", NULL, "PredriveL Mixer"},
1436 /* PreDrivR */
1437 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1438 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1439 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1440 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1441 {"PredriveR PGA", NULL, "PredriveR Mixer"},
1442 /* HeadsetL */
1443 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1444 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1445 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1446 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1447 /* HeadsetR */
1448 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1449 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1450 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1451 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1452 /* CarkitL */
1453 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1454 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1455 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1456 {"CarkitL PGA", NULL, "CarkitL Mixer"},
1457 /* CarkitR */
1458 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1459 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1460 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1461 {"CarkitR PGA", NULL, "CarkitR Mixer"},
1462 /* HandsfreeL */
1463 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1464 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1465 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1466 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1467 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1468 {"HandsfreeL PGA", NULL, "HandsfreeL"},
1469 /* HandsfreeR */
1470 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1471 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1472 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1473 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1474 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1475 {"HandsfreeR PGA", NULL, "HandsfreeR"},
1476 /* Vibra */
1477 {"Vibra Mux", "AudioL1", "DAC Left1"},
1478 {"Vibra Mux", "AudioR1", "DAC Right1"},
1479 {"Vibra Mux", "AudioL2", "DAC Left2"},
1480 {"Vibra Mux", "AudioR2", "DAC Right2"},
1481
1482 /* outputs */
1483 /* Must be always connected (for AIF and APLL) */
1484 {"Virtual HiFi OUT", NULL, "Digital L1 Playback Mixer"},
1485 {"Virtual HiFi OUT", NULL, "Digital R1 Playback Mixer"},
1486 {"Virtual HiFi OUT", NULL, "Digital L2 Playback Mixer"},
1487 {"Virtual HiFi OUT", NULL, "Digital R2 Playback Mixer"},
1488 /* Must be always connected (for APLL) */
1489 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1490 /* Physical outputs */
1491 {"EARPIECE", NULL, "Earpiece PGA"},
1492 {"PREDRIVEL", NULL, "PredriveL PGA"},
1493 {"PREDRIVER", NULL, "PredriveR PGA"},
1494 {"HSOL", NULL, "HeadsetL PGA"},
1495 {"HSOR", NULL, "HeadsetR PGA"},
1496 {"CARKITL", NULL, "CarkitL PGA"},
1497 {"CARKITR", NULL, "CarkitR PGA"},
1498 {"HFL", NULL, "HandsfreeL PGA"},
1499 {"HFR", NULL, "HandsfreeR PGA"},
1500 {"Vibra Route", "Audio", "Vibra Mux"},
1501 {"VIBRA", NULL, "Vibra Route"},
1502
1503 /* Capture path */
1504 /* Must be always connected (for AIF and APLL) */
1505 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1506 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1507 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1508 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1509 /* Physical inputs */
1510 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1511 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1512 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1513 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1514
1515 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1516 {"Analog Right", "AUXR Capture Switch", "AUXR"},
1517
1518 {"ADC Physical Left", NULL, "Analog Left"},
1519 {"ADC Physical Right", NULL, "Analog Right"},
1520
1521 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1522 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1523
1524 /* TX1 Left capture path */
1525 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1526 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1527 /* TX1 Right capture path */
1528 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1529 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1530 /* TX2 Left capture path */
1531 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1532 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1533 /* TX2 Right capture path */
1534 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1535 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1536
1537 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1538 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1539 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1540 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1541
1542 {"ADC Virtual Left1", NULL, "AIF Enable"},
1543 {"ADC Virtual Right1", NULL, "AIF Enable"},
1544 {"ADC Virtual Left2", NULL, "AIF Enable"},
1545 {"ADC Virtual Right2", NULL, "AIF Enable"},
1546
1547 /* Analog bypass routes */
1548 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1549 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1550 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1551 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1552 {"Voice Analog Loopback", "Switch", "Analog Left"},
1553
1554 /* Supply for the Analog loopbacks */
1555 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1556 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1557 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1558 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1559 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1560
1561 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1562 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1563 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1564 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1565 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1566
1567 /* Digital bypass routes */
1568 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1569 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1570 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1571
1572 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1573 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1574 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1575
1576 };
1577
1578 static int twl4030_add_widgets(struct snd_soc_codec *codec)
1579 {
1580 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1581 ARRAY_SIZE(twl4030_dapm_widgets));
1582
1583 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1584
1585 return 0;
1586 }
1587
1588 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1589 enum snd_soc_bias_level level)
1590 {
1591 switch (level) {
1592 case SND_SOC_BIAS_ON:
1593 break;
1594 case SND_SOC_BIAS_PREPARE:
1595 break;
1596 case SND_SOC_BIAS_STANDBY:
1597 if (codec->bias_level == SND_SOC_BIAS_OFF)
1598 twl4030_power_up(codec);
1599 break;
1600 case SND_SOC_BIAS_OFF:
1601 twl4030_codec_enable(codec, 0);
1602 break;
1603 }
1604 codec->bias_level = level;
1605
1606 return 0;
1607 }
1608
1609 static void twl4030_constraints(struct twl4030_priv *twl4030,
1610 struct snd_pcm_substream *mst_substream)
1611 {
1612 struct snd_pcm_substream *slv_substream;
1613
1614 /* Pick the stream, which need to be constrained */
1615 if (mst_substream == twl4030->master_substream)
1616 slv_substream = twl4030->slave_substream;
1617 else if (mst_substream == twl4030->slave_substream)
1618 slv_substream = twl4030->master_substream;
1619 else /* This should not happen.. */
1620 return;
1621
1622 /* Set the constraints according to the already configured stream */
1623 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1624 SNDRV_PCM_HW_PARAM_RATE,
1625 twl4030->rate,
1626 twl4030->rate);
1627
1628 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1629 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1630 twl4030->sample_bits,
1631 twl4030->sample_bits);
1632
1633 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1634 SNDRV_PCM_HW_PARAM_CHANNELS,
1635 twl4030->channels,
1636 twl4030->channels);
1637 }
1638
1639 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1640 * capture has to be enabled/disabled. */
1641 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1642 int enable)
1643 {
1644 u8 reg, mask;
1645
1646 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1647
1648 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1649 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1650 else
1651 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1652
1653 if (enable)
1654 reg |= mask;
1655 else
1656 reg &= ~mask;
1657
1658 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1659 }
1660
1661 static int twl4030_startup(struct snd_pcm_substream *substream,
1662 struct snd_soc_dai *dai)
1663 {
1664 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1665 struct snd_soc_device *socdev = rtd->socdev;
1666 struct snd_soc_codec *codec = socdev->card->codec;
1667 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1668
1669 if (twl4030->master_substream) {
1670 twl4030->slave_substream = substream;
1671 /* The DAI has one configuration for playback and capture, so
1672 * if the DAI has been already configured then constrain this
1673 * substream to match it. */
1674 if (twl4030->configured)
1675 twl4030_constraints(twl4030, twl4030->master_substream);
1676 } else {
1677 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1678 TWL4030_OPTION_1)) {
1679 /* In option2 4 channel is not supported, set the
1680 * constraint for the first stream for channels, the
1681 * second stream will 'inherit' this cosntraint */
1682 snd_pcm_hw_constraint_minmax(substream->runtime,
1683 SNDRV_PCM_HW_PARAM_CHANNELS,
1684 2, 2);
1685 }
1686 twl4030->master_substream = substream;
1687 }
1688
1689 return 0;
1690 }
1691
1692 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1693 struct snd_soc_dai *dai)
1694 {
1695 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1696 struct snd_soc_device *socdev = rtd->socdev;
1697 struct snd_soc_codec *codec = socdev->card->codec;
1698 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1699
1700 if (twl4030->master_substream == substream)
1701 twl4030->master_substream = twl4030->slave_substream;
1702
1703 twl4030->slave_substream = NULL;
1704
1705 /* If all streams are closed, or the remaining stream has not yet
1706 * been configured than set the DAI as not configured. */
1707 if (!twl4030->master_substream)
1708 twl4030->configured = 0;
1709 else if (!twl4030->master_substream->runtime->channels)
1710 twl4030->configured = 0;
1711
1712 /* If the closing substream had 4 channel, do the necessary cleanup */
1713 if (substream->runtime->channels == 4)
1714 twl4030_tdm_enable(codec, substream->stream, 0);
1715 }
1716
1717 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1718 struct snd_pcm_hw_params *params,
1719 struct snd_soc_dai *dai)
1720 {
1721 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1722 struct snd_soc_device *socdev = rtd->socdev;
1723 struct snd_soc_codec *codec = socdev->card->codec;
1724 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1725 u8 mode, old_mode, format, old_format;
1726
1727 /* If the substream has 4 channel, do the necessary setup */
1728 if (params_channels(params) == 4) {
1729 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1730 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1731
1732 /* Safety check: are we in the correct operating mode and
1733 * the interface is in TDM mode? */
1734 if ((mode & TWL4030_OPTION_1) &&
1735 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1736 twl4030_tdm_enable(codec, substream->stream, 1);
1737 else
1738 return -EINVAL;
1739 }
1740
1741 if (twl4030->configured)
1742 /* Ignoring hw_params for already configured DAI */
1743 return 0;
1744
1745 /* bit rate */
1746 old_mode = twl4030_read_reg_cache(codec,
1747 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1748 mode = old_mode & ~TWL4030_APLL_RATE;
1749
1750 switch (params_rate(params)) {
1751 case 8000:
1752 mode |= TWL4030_APLL_RATE_8000;
1753 break;
1754 case 11025:
1755 mode |= TWL4030_APLL_RATE_11025;
1756 break;
1757 case 12000:
1758 mode |= TWL4030_APLL_RATE_12000;
1759 break;
1760 case 16000:
1761 mode |= TWL4030_APLL_RATE_16000;
1762 break;
1763 case 22050:
1764 mode |= TWL4030_APLL_RATE_22050;
1765 break;
1766 case 24000:
1767 mode |= TWL4030_APLL_RATE_24000;
1768 break;
1769 case 32000:
1770 mode |= TWL4030_APLL_RATE_32000;
1771 break;
1772 case 44100:
1773 mode |= TWL4030_APLL_RATE_44100;
1774 break;
1775 case 48000:
1776 mode |= TWL4030_APLL_RATE_48000;
1777 break;
1778 case 96000:
1779 mode |= TWL4030_APLL_RATE_96000;
1780 break;
1781 default:
1782 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1783 params_rate(params));
1784 return -EINVAL;
1785 }
1786
1787 if (mode != old_mode) {
1788 /* change rate and set CODECPDZ */
1789 twl4030_codec_enable(codec, 0);
1790 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1791 twl4030_codec_enable(codec, 1);
1792 }
1793
1794 /* sample size */
1795 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1796 format = old_format;
1797 format &= ~TWL4030_DATA_WIDTH;
1798 switch (params_format(params)) {
1799 case SNDRV_PCM_FORMAT_S16_LE:
1800 format |= TWL4030_DATA_WIDTH_16S_16W;
1801 break;
1802 case SNDRV_PCM_FORMAT_S24_LE:
1803 format |= TWL4030_DATA_WIDTH_32S_24W;
1804 break;
1805 default:
1806 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1807 params_format(params));
1808 return -EINVAL;
1809 }
1810
1811 if (format != old_format) {
1812
1813 /* clear CODECPDZ before changing format (codec requirement) */
1814 twl4030_codec_enable(codec, 0);
1815
1816 /* change format */
1817 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1818
1819 /* set CODECPDZ afterwards */
1820 twl4030_codec_enable(codec, 1);
1821 }
1822
1823 /* Store the important parameters for the DAI configuration and set
1824 * the DAI as configured */
1825 twl4030->configured = 1;
1826 twl4030->rate = params_rate(params);
1827 twl4030->sample_bits = hw_param_interval(params,
1828 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1829 twl4030->channels = params_channels(params);
1830
1831 /* If both playback and capture streams are open, and one of them
1832 * is setting the hw parameters right now (since we are here), set
1833 * constraints to the other stream to match the current one. */
1834 if (twl4030->slave_substream)
1835 twl4030_constraints(twl4030, substream);
1836
1837 return 0;
1838 }
1839
1840 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1841 int clk_id, unsigned int freq, int dir)
1842 {
1843 struct snd_soc_codec *codec = codec_dai->codec;
1844 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1845
1846 switch (freq) {
1847 case 19200000:
1848 case 26000000:
1849 case 38400000:
1850 break;
1851 default:
1852 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
1853 return -EINVAL;
1854 }
1855
1856 if ((freq / 1000) != twl4030->sysclk) {
1857 dev_err(codec->dev,
1858 "Mismatch in APLL mclk: %u (configured: %u)\n",
1859 freq, twl4030->sysclk * 1000);
1860 return -EINVAL;
1861 }
1862
1863 return 0;
1864 }
1865
1866 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1867 unsigned int fmt)
1868 {
1869 struct snd_soc_codec *codec = codec_dai->codec;
1870 u8 old_format, format;
1871
1872 /* get format */
1873 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1874 format = old_format;
1875
1876 /* set master/slave audio interface */
1877 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1878 case SND_SOC_DAIFMT_CBM_CFM:
1879 format &= ~(TWL4030_AIF_SLAVE_EN);
1880 format &= ~(TWL4030_CLK256FS_EN);
1881 break;
1882 case SND_SOC_DAIFMT_CBS_CFS:
1883 format |= TWL4030_AIF_SLAVE_EN;
1884 format |= TWL4030_CLK256FS_EN;
1885 break;
1886 default:
1887 return -EINVAL;
1888 }
1889
1890 /* interface format */
1891 format &= ~TWL4030_AIF_FORMAT;
1892 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1893 case SND_SOC_DAIFMT_I2S:
1894 format |= TWL4030_AIF_FORMAT_CODEC;
1895 break;
1896 case SND_SOC_DAIFMT_DSP_A:
1897 format |= TWL4030_AIF_FORMAT_TDM;
1898 break;
1899 default:
1900 return -EINVAL;
1901 }
1902
1903 if (format != old_format) {
1904
1905 /* clear CODECPDZ before changing format (codec requirement) */
1906 twl4030_codec_enable(codec, 0);
1907
1908 /* change format */
1909 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1910
1911 /* set CODECPDZ afterwards */
1912 twl4030_codec_enable(codec, 1);
1913 }
1914
1915 return 0;
1916 }
1917
1918 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1919 {
1920 struct snd_soc_codec *codec = dai->codec;
1921 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1922
1923 if (tristate)
1924 reg |= TWL4030_AIF_TRI_EN;
1925 else
1926 reg &= ~TWL4030_AIF_TRI_EN;
1927
1928 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1929 }
1930
1931 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1932 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1933 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1934 int enable)
1935 {
1936 u8 reg, mask;
1937
1938 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1939
1940 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1941 mask = TWL4030_ARXL1_VRX_EN;
1942 else
1943 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1944
1945 if (enable)
1946 reg |= mask;
1947 else
1948 reg &= ~mask;
1949
1950 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1951 }
1952
1953 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1954 struct snd_soc_dai *dai)
1955 {
1956 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1957 struct snd_soc_device *socdev = rtd->socdev;
1958 struct snd_soc_codec *codec = socdev->card->codec;
1959 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1960 u8 mode;
1961
1962 /* If the system master clock is not 26MHz, the voice PCM interface is
1963 * not avilable.
1964 */
1965 if (twl4030->sysclk != 26000) {
1966 dev_err(codec->dev, "The board is configured for %u Hz, while"
1967 "the Voice interface needs 26MHz APLL mclk\n",
1968 twl4030->sysclk * 1000);
1969 return -EINVAL;
1970 }
1971
1972 /* If the codec mode is not option2, the voice PCM interface is not
1973 * avilable.
1974 */
1975 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1976 & TWL4030_OPT_MODE;
1977
1978 if (mode != TWL4030_OPTION_2) {
1979 printk(KERN_ERR "TWL4030 voice startup: "
1980 "the codec mode is not option2\n");
1981 return -EINVAL;
1982 }
1983
1984 return 0;
1985 }
1986
1987 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1988 struct snd_soc_dai *dai)
1989 {
1990 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1991 struct snd_soc_device *socdev = rtd->socdev;
1992 struct snd_soc_codec *codec = socdev->card->codec;
1993
1994 /* Enable voice digital filters */
1995 twl4030_voice_enable(codec, substream->stream, 0);
1996 }
1997
1998 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1999 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2000 {
2001 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2002 struct snd_soc_device *socdev = rtd->socdev;
2003 struct snd_soc_codec *codec = socdev->card->codec;
2004 u8 old_mode, mode;
2005
2006 /* Enable voice digital filters */
2007 twl4030_voice_enable(codec, substream->stream, 1);
2008
2009 /* bit rate */
2010 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2011 & ~(TWL4030_CODECPDZ);
2012 mode = old_mode;
2013
2014 switch (params_rate(params)) {
2015 case 8000:
2016 mode &= ~(TWL4030_SEL_16K);
2017 break;
2018 case 16000:
2019 mode |= TWL4030_SEL_16K;
2020 break;
2021 default:
2022 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2023 params_rate(params));
2024 return -EINVAL;
2025 }
2026
2027 if (mode != old_mode) {
2028 /* change rate and set CODECPDZ */
2029 twl4030_codec_enable(codec, 0);
2030 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2031 twl4030_codec_enable(codec, 1);
2032 }
2033
2034 return 0;
2035 }
2036
2037 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2038 int clk_id, unsigned int freq, int dir)
2039 {
2040 struct snd_soc_codec *codec = codec_dai->codec;
2041 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2042
2043 if (freq != 26000000) {
2044 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2045 "interface needs 26MHz APLL mclk\n", freq);
2046 return -EINVAL;
2047 }
2048 if ((freq / 1000) != twl4030->sysclk) {
2049 dev_err(codec->dev,
2050 "Mismatch in APLL mclk: %u (configured: %u)\n",
2051 freq, twl4030->sysclk * 1000);
2052 return -EINVAL;
2053 }
2054 return 0;
2055 }
2056
2057 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2058 unsigned int fmt)
2059 {
2060 struct snd_soc_codec *codec = codec_dai->codec;
2061 u8 old_format, format;
2062
2063 /* get format */
2064 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2065 format = old_format;
2066
2067 /* set master/slave audio interface */
2068 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2069 case SND_SOC_DAIFMT_CBM_CFM:
2070 format &= ~(TWL4030_VIF_SLAVE_EN);
2071 break;
2072 case SND_SOC_DAIFMT_CBS_CFS:
2073 format |= TWL4030_VIF_SLAVE_EN;
2074 break;
2075 default:
2076 return -EINVAL;
2077 }
2078
2079 /* clock inversion */
2080 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2081 case SND_SOC_DAIFMT_IB_NF:
2082 format &= ~(TWL4030_VIF_FORMAT);
2083 break;
2084 case SND_SOC_DAIFMT_NB_IF:
2085 format |= TWL4030_VIF_FORMAT;
2086 break;
2087 default:
2088 return -EINVAL;
2089 }
2090
2091 if (format != old_format) {
2092 /* change format and set CODECPDZ */
2093 twl4030_codec_enable(codec, 0);
2094 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2095 twl4030_codec_enable(codec, 1);
2096 }
2097
2098 return 0;
2099 }
2100
2101 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2102 {
2103 struct snd_soc_codec *codec = dai->codec;
2104 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2105
2106 if (tristate)
2107 reg |= TWL4030_VIF_TRI_EN;
2108 else
2109 reg &= ~TWL4030_VIF_TRI_EN;
2110
2111 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2112 }
2113
2114 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2115 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2116
2117 static struct snd_soc_dai_ops twl4030_dai_ops = {
2118 .startup = twl4030_startup,
2119 .shutdown = twl4030_shutdown,
2120 .hw_params = twl4030_hw_params,
2121 .set_sysclk = twl4030_set_dai_sysclk,
2122 .set_fmt = twl4030_set_dai_fmt,
2123 .set_tristate = twl4030_set_tristate,
2124 };
2125
2126 static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2127 .startup = twl4030_voice_startup,
2128 .shutdown = twl4030_voice_shutdown,
2129 .hw_params = twl4030_voice_hw_params,
2130 .set_sysclk = twl4030_voice_set_dai_sysclk,
2131 .set_fmt = twl4030_voice_set_dai_fmt,
2132 .set_tristate = twl4030_voice_set_tristate,
2133 };
2134
2135 struct snd_soc_dai twl4030_dai[] = {
2136 {
2137 .name = "twl4030",
2138 .playback = {
2139 .stream_name = "HiFi Playback",
2140 .channels_min = 2,
2141 .channels_max = 4,
2142 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2143 .formats = TWL4030_FORMATS,},
2144 .capture = {
2145 .stream_name = "Capture",
2146 .channels_min = 2,
2147 .channels_max = 4,
2148 .rates = TWL4030_RATES,
2149 .formats = TWL4030_FORMATS,},
2150 .ops = &twl4030_dai_ops,
2151 },
2152 {
2153 .name = "twl4030 Voice",
2154 .playback = {
2155 .stream_name = "Voice Playback",
2156 .channels_min = 1,
2157 .channels_max = 1,
2158 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2159 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2160 .capture = {
2161 .stream_name = "Capture",
2162 .channels_min = 1,
2163 .channels_max = 2,
2164 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2165 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2166 .ops = &twl4030_dai_voice_ops,
2167 },
2168 };
2169 EXPORT_SYMBOL_GPL(twl4030_dai);
2170
2171 static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
2172 {
2173 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2174 struct snd_soc_codec *codec = socdev->card->codec;
2175
2176 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2177
2178 return 0;
2179 }
2180
2181 static int twl4030_soc_resume(struct platform_device *pdev)
2182 {
2183 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2184 struct snd_soc_codec *codec = socdev->card->codec;
2185
2186 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2187 return 0;
2188 }
2189
2190 static struct snd_soc_codec *twl4030_codec;
2191
2192 static int twl4030_soc_probe(struct platform_device *pdev)
2193 {
2194 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2195 struct twl4030_setup_data *setup = socdev->codec_data;
2196 struct snd_soc_codec *codec;
2197 struct twl4030_priv *twl4030;
2198 int ret;
2199
2200 BUG_ON(!twl4030_codec);
2201
2202 codec = twl4030_codec;
2203 twl4030 = snd_soc_codec_get_drvdata(codec);
2204 socdev->card->codec = codec;
2205
2206 /* Configuration for headset ramp delay from setup data */
2207 if (setup) {
2208 unsigned char hs_pop;
2209
2210 if (setup->sysclk != twl4030->sysclk)
2211 dev_warn(&pdev->dev,
2212 "Mismatch in APLL mclk: %u (configured: %u)\n",
2213 setup->sysclk, twl4030->sysclk);
2214
2215 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2216 hs_pop &= ~TWL4030_RAMP_DELAY;
2217 hs_pop |= (setup->ramp_delay_value << 2);
2218 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2219 }
2220
2221 /* register pcms */
2222 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2223 if (ret < 0) {
2224 dev_err(&pdev->dev, "failed to create pcms\n");
2225 return ret;
2226 }
2227
2228 snd_soc_add_controls(codec, twl4030_snd_controls,
2229 ARRAY_SIZE(twl4030_snd_controls));
2230 twl4030_add_widgets(codec);
2231
2232 return 0;
2233 }
2234
2235 static int twl4030_soc_remove(struct platform_device *pdev)
2236 {
2237 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2238 struct snd_soc_codec *codec = socdev->card->codec;
2239
2240 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2241 snd_soc_free_pcms(socdev);
2242 snd_soc_dapm_free(socdev);
2243
2244 return 0;
2245 }
2246
2247 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2248 {
2249 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
2250 struct snd_soc_codec *codec;
2251 struct twl4030_priv *twl4030;
2252 int ret;
2253
2254 if (!pdata) {
2255 dev_err(&pdev->dev, "platform_data is missing\n");
2256 return -EINVAL;
2257 }
2258
2259 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2260 if (twl4030 == NULL) {
2261 dev_err(&pdev->dev, "Can not allocate memroy\n");
2262 return -ENOMEM;
2263 }
2264
2265 codec = &twl4030->codec;
2266 snd_soc_codec_set_drvdata(codec, twl4030);
2267 codec->dev = &pdev->dev;
2268 twl4030_dai[0].dev = &pdev->dev;
2269 twl4030_dai[1].dev = &pdev->dev;
2270
2271 mutex_init(&codec->mutex);
2272 INIT_LIST_HEAD(&codec->dapm_widgets);
2273 INIT_LIST_HEAD(&codec->dapm_paths);
2274
2275 codec->name = "twl4030";
2276 codec->owner = THIS_MODULE;
2277 codec->read = twl4030_read_reg_cache;
2278 codec->write = twl4030_write;
2279 codec->set_bias_level = twl4030_set_bias_level;
2280 codec->dai = twl4030_dai;
2281 codec->num_dai = ARRAY_SIZE(twl4030_dai);
2282 codec->reg_cache_size = sizeof(twl4030_reg);
2283 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2284 GFP_KERNEL);
2285 if (codec->reg_cache == NULL) {
2286 ret = -ENOMEM;
2287 goto error_cache;
2288 }
2289
2290 platform_set_drvdata(pdev, twl4030);
2291 twl4030_codec = codec;
2292
2293 /* Set the defaults, and power up the codec */
2294 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
2295 twl4030_init_chip(codec);
2296 codec->bias_level = SND_SOC_BIAS_OFF;
2297 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2298
2299 ret = snd_soc_register_codec(codec);
2300 if (ret != 0) {
2301 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2302 goto error_codec;
2303 }
2304
2305 ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2306 if (ret != 0) {
2307 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
2308 snd_soc_unregister_codec(codec);
2309 goto error_codec;
2310 }
2311
2312 return 0;
2313
2314 error_codec:
2315 twl4030_codec_enable(codec, 0);
2316 kfree(codec->reg_cache);
2317 error_cache:
2318 kfree(twl4030);
2319 return ret;
2320 }
2321
2322 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2323 {
2324 struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
2325
2326 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2327 snd_soc_unregister_codec(&twl4030->codec);
2328 kfree(twl4030->codec.reg_cache);
2329 kfree(twl4030);
2330
2331 twl4030_codec = NULL;
2332 return 0;
2333 }
2334
2335 MODULE_ALIAS("platform:twl4030_codec_audio");
2336
2337 static struct platform_driver twl4030_codec_driver = {
2338 .probe = twl4030_codec_probe,
2339 .remove = __devexit_p(twl4030_codec_remove),
2340 .driver = {
2341 .name = "twl4030_codec_audio",
2342 .owner = THIS_MODULE,
2343 },
2344 };
2345
2346 static int __init twl4030_modinit(void)
2347 {
2348 return platform_driver_register(&twl4030_codec_driver);
2349 }
2350 module_init(twl4030_modinit);
2351
2352 static void __exit twl4030_exit(void)
2353 {
2354 platform_driver_unregister(&twl4030_codec_driver);
2355 }
2356 module_exit(twl4030_exit);
2357
2358 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2359 .probe = twl4030_soc_probe,
2360 .remove = twl4030_soc_remove,
2361 .suspend = twl4030_soc_suspend,
2362 .resume = twl4030_soc_resume,
2363 };
2364 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2365
2366 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2367 MODULE_AUTHOR("Steve Sakoman");
2368 MODULE_LICENSE("GPL");
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