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[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / wm8904.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * wm8904.c -- WM8904 ALSA SoC Audio driver
4 *
5 * Copyright 2009-12 Wolfson Microelectronics plc
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/wm8904.h>
26
27 #include "wm8904.h"
28
29 enum wm8904_type {
30 WM8904,
31 WM8912,
32 };
33
34 #define WM8904_NUM_DCS_CHANNELS 4
35
36 #define WM8904_NUM_SUPPLIES 5
37 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
38 "DCVDD",
39 "DBVDD",
40 "AVDD",
41 "CPVDD",
42 "MICVDD",
43 };
44
45 /* codec private data */
46 struct wm8904_priv {
47 struct regmap *regmap;
48 struct clk *mclk;
49
50 enum wm8904_type devtype;
51
52 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
53
54 struct wm8904_pdata *pdata;
55
56 int deemph;
57
58 /* Platform provided DRC configuration */
59 const char **drc_texts;
60 int drc_cfg;
61 struct soc_enum drc_enum;
62
63 /* Platform provided ReTune mobile configuration */
64 int num_retune_mobile_texts;
65 const char **retune_mobile_texts;
66 int retune_mobile_cfg;
67 struct soc_enum retune_mobile_enum;
68
69 /* FLL setup */
70 int fll_src;
71 int fll_fref;
72 int fll_fout;
73
74 /* Clocking configuration */
75 unsigned int mclk_rate;
76 int sysclk_src;
77 unsigned int sysclk_rate;
78
79 int tdm_width;
80 int tdm_slots;
81 int bclk;
82 int fs;
83
84 /* DC servo configuration - cached offset values */
85 int dcs_state[WM8904_NUM_DCS_CHANNELS];
86 };
87
88 static const struct reg_default wm8904_reg_defaults[] = {
89 { 4, 0x0018 }, /* R4 - Bias Control 0 */
90 { 5, 0x0000 }, /* R5 - VMID Control 0 */
91 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
92 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
93 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
94 { 9, 0x9696 }, /* R9 - mic Filter Control */
95 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
96 { 12, 0x0000 }, /* R12 - Power Management 0 */
97 { 14, 0x0000 }, /* R14 - Power Management 2 */
98 { 15, 0x0000 }, /* R15 - Power Management 3 */
99 { 18, 0x0000 }, /* R18 - Power Management 6 */
100 { 20, 0x945E }, /* R20 - Clock Rates 0 */
101 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
102 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
103 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
104 { 25, 0x000A }, /* R25 - Audio Interface 1 */
105 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
106 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
107 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
108 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
109 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
110 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
111 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
112 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
113 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
114 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
115 { 40, 0x01AF }, /* R40 - DRC 0 */
116 { 41, 0x3248 }, /* R41 - DRC 1 */
117 { 42, 0x0000 }, /* R42 - DRC 2 */
118 { 43, 0x0000 }, /* R43 - DRC 3 */
119 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
120 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
121 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
122 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
123 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
124 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
125 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
126 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
127 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
128 { 67, 0x0000 }, /* R67 - DC Servo 0 */
129 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
130 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
131 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
132 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
133 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
134 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
135 { 104, 0x0004 }, /* R104 - Class W 0 */
136 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
137 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
138 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
139 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
140 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
141 { 116, 0x0000 }, /* R116 - FLL Control 1 */
142 { 117, 0x0007 }, /* R117 - FLL Control 2 */
143 { 118, 0x0000 }, /* R118 - FLL Control 3 */
144 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
145 { 120, 0x0004 }, /* R120 - FLL Control 5 */
146 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
147 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
148 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
149 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
150 { 126, 0x0000 }, /* R126 - Digital Pulls */
151 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
152 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
153 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
154 { 134, 0x0000 }, /* R134 - EQ1 */
155 { 135, 0x000C }, /* R135 - EQ2 */
156 { 136, 0x000C }, /* R136 - EQ3 */
157 { 137, 0x000C }, /* R137 - EQ4 */
158 { 138, 0x000C }, /* R138 - EQ5 */
159 { 139, 0x000C }, /* R139 - EQ6 */
160 { 140, 0x0FCA }, /* R140 - EQ7 */
161 { 141, 0x0400 }, /* R141 - EQ8 */
162 { 142, 0x00D8 }, /* R142 - EQ9 */
163 { 143, 0x1EB5 }, /* R143 - EQ10 */
164 { 144, 0xF145 }, /* R144 - EQ11 */
165 { 145, 0x0B75 }, /* R145 - EQ12 */
166 { 146, 0x01C5 }, /* R146 - EQ13 */
167 { 147, 0x1C58 }, /* R147 - EQ14 */
168 { 148, 0xF373 }, /* R148 - EQ15 */
169 { 149, 0x0A54 }, /* R149 - EQ16 */
170 { 150, 0x0558 }, /* R150 - EQ17 */
171 { 151, 0x168E }, /* R151 - EQ18 */
172 { 152, 0xF829 }, /* R152 - EQ19 */
173 { 153, 0x07AD }, /* R153 - EQ20 */
174 { 154, 0x1103 }, /* R154 - EQ21 */
175 { 155, 0x0564 }, /* R155 - EQ22 */
176 { 156, 0x0559 }, /* R156 - EQ23 */
177 { 157, 0x4000 }, /* R157 - EQ24 */
178 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
179 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
180 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
181 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
182 };
183
184 static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
185 {
186 switch (reg) {
187 case WM8904_SW_RESET_AND_ID:
188 case WM8904_REVISION:
189 case WM8904_DC_SERVO_1:
190 case WM8904_DC_SERVO_6:
191 case WM8904_DC_SERVO_7:
192 case WM8904_DC_SERVO_8:
193 case WM8904_DC_SERVO_9:
194 case WM8904_DC_SERVO_READBACK_0:
195 case WM8904_INTERRUPT_STATUS:
196 return true;
197 default:
198 return false;
199 }
200 }
201
202 static bool wm8904_readable_register(struct device *dev, unsigned int reg)
203 {
204 switch (reg) {
205 case WM8904_SW_RESET_AND_ID:
206 case WM8904_REVISION:
207 case WM8904_BIAS_CONTROL_0:
208 case WM8904_VMID_CONTROL_0:
209 case WM8904_MIC_BIAS_CONTROL_0:
210 case WM8904_MIC_BIAS_CONTROL_1:
211 case WM8904_ANALOGUE_DAC_0:
212 case WM8904_MIC_FILTER_CONTROL:
213 case WM8904_ANALOGUE_ADC_0:
214 case WM8904_POWER_MANAGEMENT_0:
215 case WM8904_POWER_MANAGEMENT_2:
216 case WM8904_POWER_MANAGEMENT_3:
217 case WM8904_POWER_MANAGEMENT_6:
218 case WM8904_CLOCK_RATES_0:
219 case WM8904_CLOCK_RATES_1:
220 case WM8904_CLOCK_RATES_2:
221 case WM8904_AUDIO_INTERFACE_0:
222 case WM8904_AUDIO_INTERFACE_1:
223 case WM8904_AUDIO_INTERFACE_2:
224 case WM8904_AUDIO_INTERFACE_3:
225 case WM8904_DAC_DIGITAL_VOLUME_LEFT:
226 case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
227 case WM8904_DAC_DIGITAL_0:
228 case WM8904_DAC_DIGITAL_1:
229 case WM8904_ADC_DIGITAL_VOLUME_LEFT:
230 case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
231 case WM8904_ADC_DIGITAL_0:
232 case WM8904_DIGITAL_MICROPHONE_0:
233 case WM8904_DRC_0:
234 case WM8904_DRC_1:
235 case WM8904_DRC_2:
236 case WM8904_DRC_3:
237 case WM8904_ANALOGUE_LEFT_INPUT_0:
238 case WM8904_ANALOGUE_RIGHT_INPUT_0:
239 case WM8904_ANALOGUE_LEFT_INPUT_1:
240 case WM8904_ANALOGUE_RIGHT_INPUT_1:
241 case WM8904_ANALOGUE_OUT1_LEFT:
242 case WM8904_ANALOGUE_OUT1_RIGHT:
243 case WM8904_ANALOGUE_OUT2_LEFT:
244 case WM8904_ANALOGUE_OUT2_RIGHT:
245 case WM8904_ANALOGUE_OUT12_ZC:
246 case WM8904_DC_SERVO_0:
247 case WM8904_DC_SERVO_1:
248 case WM8904_DC_SERVO_2:
249 case WM8904_DC_SERVO_4:
250 case WM8904_DC_SERVO_5:
251 case WM8904_DC_SERVO_6:
252 case WM8904_DC_SERVO_7:
253 case WM8904_DC_SERVO_8:
254 case WM8904_DC_SERVO_9:
255 case WM8904_DC_SERVO_READBACK_0:
256 case WM8904_ANALOGUE_HP_0:
257 case WM8904_ANALOGUE_LINEOUT_0:
258 case WM8904_CHARGE_PUMP_0:
259 case WM8904_CLASS_W_0:
260 case WM8904_WRITE_SEQUENCER_0:
261 case WM8904_WRITE_SEQUENCER_1:
262 case WM8904_WRITE_SEQUENCER_2:
263 case WM8904_WRITE_SEQUENCER_3:
264 case WM8904_WRITE_SEQUENCER_4:
265 case WM8904_FLL_CONTROL_1:
266 case WM8904_FLL_CONTROL_2:
267 case WM8904_FLL_CONTROL_3:
268 case WM8904_FLL_CONTROL_4:
269 case WM8904_FLL_CONTROL_5:
270 case WM8904_GPIO_CONTROL_1:
271 case WM8904_GPIO_CONTROL_2:
272 case WM8904_GPIO_CONTROL_3:
273 case WM8904_GPIO_CONTROL_4:
274 case WM8904_DIGITAL_PULLS:
275 case WM8904_INTERRUPT_STATUS:
276 case WM8904_INTERRUPT_STATUS_MASK:
277 case WM8904_INTERRUPT_POLARITY:
278 case WM8904_INTERRUPT_DEBOUNCE:
279 case WM8904_EQ1:
280 case WM8904_EQ2:
281 case WM8904_EQ3:
282 case WM8904_EQ4:
283 case WM8904_EQ5:
284 case WM8904_EQ6:
285 case WM8904_EQ7:
286 case WM8904_EQ8:
287 case WM8904_EQ9:
288 case WM8904_EQ10:
289 case WM8904_EQ11:
290 case WM8904_EQ12:
291 case WM8904_EQ13:
292 case WM8904_EQ14:
293 case WM8904_EQ15:
294 case WM8904_EQ16:
295 case WM8904_EQ17:
296 case WM8904_EQ18:
297 case WM8904_EQ19:
298 case WM8904_EQ20:
299 case WM8904_EQ21:
300 case WM8904_EQ22:
301 case WM8904_EQ23:
302 case WM8904_EQ24:
303 case WM8904_CONTROL_INTERFACE_TEST_1:
304 case WM8904_ADC_TEST_0:
305 case WM8904_ANALOGUE_OUTPUT_BIAS_0:
306 case WM8904_FLL_NCO_TEST_0:
307 case WM8904_FLL_NCO_TEST_1:
308 return true;
309 default:
310 return false;
311 }
312 }
313
314 static int wm8904_configure_clocking(struct snd_soc_component *component)
315 {
316 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
317 unsigned int clock0, clock2, rate;
318
319 /* Gate the clock while we're updating to avoid misclocking */
320 clock2 = snd_soc_component_read32(component, WM8904_CLOCK_RATES_2);
321 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
322 WM8904_SYSCLK_SRC, 0);
323
324 /* This should be done on init() for bypass paths */
325 switch (wm8904->sysclk_src) {
326 case WM8904_CLK_MCLK:
327 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
328
329 clock2 &= ~WM8904_SYSCLK_SRC;
330 rate = wm8904->mclk_rate;
331
332 /* Ensure the FLL is stopped */
333 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
334 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
335 break;
336
337 case WM8904_CLK_FLL:
338 dev_dbg(component->dev, "Using %dHz FLL clock\n",
339 wm8904->fll_fout);
340
341 clock2 |= WM8904_SYSCLK_SRC;
342 rate = wm8904->fll_fout;
343 break;
344
345 default:
346 dev_err(component->dev, "System clock not configured\n");
347 return -EINVAL;
348 }
349
350 /* SYSCLK shouldn't be over 13.5MHz */
351 if (rate > 13500000) {
352 clock0 = WM8904_MCLK_DIV;
353 wm8904->sysclk_rate = rate / 2;
354 } else {
355 clock0 = 0;
356 wm8904->sysclk_rate = rate;
357 }
358
359 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
360 clock0);
361
362 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
363 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
364
365 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
366
367 return 0;
368 }
369
370 static void wm8904_set_drc(struct snd_soc_component *component)
371 {
372 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
373 struct wm8904_pdata *pdata = wm8904->pdata;
374 int save, i;
375
376 /* Save any enables; the configuration should clear them. */
377 save = snd_soc_component_read32(component, WM8904_DRC_0);
378
379 for (i = 0; i < WM8904_DRC_REGS; i++)
380 snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff,
381 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
382
383 /* Reenable the DRC */
384 snd_soc_component_update_bits(component, WM8904_DRC_0,
385 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
386 }
387
388 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
389 struct snd_ctl_elem_value *ucontrol)
390 {
391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
392 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
393 struct wm8904_pdata *pdata = wm8904->pdata;
394 int value = ucontrol->value.enumerated.item[0];
395
396 if (value >= pdata->num_drc_cfgs)
397 return -EINVAL;
398
399 wm8904->drc_cfg = value;
400
401 wm8904_set_drc(component);
402
403 return 0;
404 }
405
406 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
408 {
409 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
410 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
411
412 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
413
414 return 0;
415 }
416
417 static void wm8904_set_retune_mobile(struct snd_soc_component *component)
418 {
419 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
420 struct wm8904_pdata *pdata = wm8904->pdata;
421 int best, best_val, save, i, cfg;
422
423 if (!pdata || !wm8904->num_retune_mobile_texts)
424 return;
425
426 /* Find the version of the currently selected configuration
427 * with the nearest sample rate. */
428 cfg = wm8904->retune_mobile_cfg;
429 best = 0;
430 best_val = INT_MAX;
431 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
432 if (strcmp(pdata->retune_mobile_cfgs[i].name,
433 wm8904->retune_mobile_texts[cfg]) == 0 &&
434 abs(pdata->retune_mobile_cfgs[i].rate
435 - wm8904->fs) < best_val) {
436 best = i;
437 best_val = abs(pdata->retune_mobile_cfgs[i].rate
438 - wm8904->fs);
439 }
440 }
441
442 dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
443 pdata->retune_mobile_cfgs[best].name,
444 pdata->retune_mobile_cfgs[best].rate,
445 wm8904->fs);
446
447 /* The EQ will be disabled while reconfiguring it, remember the
448 * current configuration.
449 */
450 save = snd_soc_component_read32(component, WM8904_EQ1);
451
452 for (i = 0; i < WM8904_EQ_REGS; i++)
453 snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff,
454 pdata->retune_mobile_cfgs[best].regs[i]);
455
456 snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save);
457 }
458
459 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_value *ucontrol)
461 {
462 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
463 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
464 struct wm8904_pdata *pdata = wm8904->pdata;
465 int value = ucontrol->value.enumerated.item[0];
466
467 if (value >= pdata->num_retune_mobile_cfgs)
468 return -EINVAL;
469
470 wm8904->retune_mobile_cfg = value;
471
472 wm8904_set_retune_mobile(component);
473
474 return 0;
475 }
476
477 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
478 struct snd_ctl_elem_value *ucontrol)
479 {
480 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
481 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
482
483 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
484
485 return 0;
486 }
487
488 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
489
490 static int wm8904_set_deemph(struct snd_soc_component *component)
491 {
492 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
493 int val, i, best;
494
495 /* If we're using deemphasis select the nearest available sample
496 * rate.
497 */
498 if (wm8904->deemph) {
499 best = 1;
500 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
501 if (abs(deemph_settings[i] - wm8904->fs) <
502 abs(deemph_settings[best] - wm8904->fs))
503 best = i;
504 }
505
506 val = best << WM8904_DEEMPH_SHIFT;
507 } else {
508 val = 0;
509 }
510
511 dev_dbg(component->dev, "Set deemphasis %d\n", val);
512
513 return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
514 WM8904_DEEMPH_MASK, val);
515 }
516
517 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
518 struct snd_ctl_elem_value *ucontrol)
519 {
520 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
521 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
522
523 ucontrol->value.integer.value[0] = wm8904->deemph;
524 return 0;
525 }
526
527 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
528 struct snd_ctl_elem_value *ucontrol)
529 {
530 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
531 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
532 unsigned int deemph = ucontrol->value.integer.value[0];
533
534 if (deemph > 1)
535 return -EINVAL;
536
537 wm8904->deemph = deemph;
538
539 return wm8904_set_deemph(component);
540 }
541
542 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
543 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
544 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
545 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
546 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
547
548 static const char *hpf_mode_text[] = {
549 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
550 };
551
552 static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
553 hpf_mode_text);
554
555 static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
556 struct snd_ctl_elem_value *ucontrol)
557 {
558 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
559 unsigned int val;
560 int ret;
561
562 ret = snd_soc_put_volsw(kcontrol, ucontrol);
563 if (ret < 0)
564 return ret;
565
566 if (ucontrol->value.integer.value[0])
567 val = 0;
568 else
569 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
570
571 snd_soc_component_update_bits(component, WM8904_ADC_TEST_0,
572 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
573 val);
574
575 return ret;
576 }
577
578 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
579 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
580 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
581
582 /* No TLV since it depends on mode */
583 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
584 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
585 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
586 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
587
588 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
589 SOC_ENUM("High Pass Filter Mode", hpf_mode),
590 SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
591 snd_soc_get_volsw, wm8904_adc_osr_put),
592 };
593
594 static const char *drc_path_text[] = {
595 "ADC", "DAC"
596 };
597
598 static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
599
600 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
601 SOC_SINGLE_TLV("Digital Playback Boost Volume",
602 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
603 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
604 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
605
606 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
607 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
608 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
609 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
610 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
611 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
612
613 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
614 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
615 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
616 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
617 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
618 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
619
620 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
621 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
622 SOC_ENUM("DRC Path", drc_path),
623 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
624 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
625 wm8904_get_deemph, wm8904_put_deemph),
626 };
627
628 static const struct snd_kcontrol_new wm8904_snd_controls[] = {
629 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
630 sidetone_tlv),
631 };
632
633 static const struct snd_kcontrol_new wm8904_eq_controls[] = {
634 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
635 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
636 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
637 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
638 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
639 };
640
641 static int cp_event(struct snd_soc_dapm_widget *w,
642 struct snd_kcontrol *kcontrol, int event)
643 {
644 if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
645 return -EINVAL;
646
647 /* Maximum startup time */
648 udelay(500);
649
650 return 0;
651 }
652
653 static int sysclk_event(struct snd_soc_dapm_widget *w,
654 struct snd_kcontrol *kcontrol, int event)
655 {
656 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
657 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
658
659 switch (event) {
660 case SND_SOC_DAPM_PRE_PMU:
661 /* If we're using the FLL then we only start it when
662 * required; we assume that the configuration has been
663 * done previously and all we need to do is kick it
664 * off.
665 */
666 switch (wm8904->sysclk_src) {
667 case WM8904_CLK_FLL:
668 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
669 WM8904_FLL_OSC_ENA,
670 WM8904_FLL_OSC_ENA);
671
672 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
673 WM8904_FLL_ENA,
674 WM8904_FLL_ENA);
675 break;
676
677 default:
678 break;
679 }
680 break;
681
682 case SND_SOC_DAPM_POST_PMD:
683 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
684 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
685 break;
686 }
687
688 return 0;
689 }
690
691 static int out_pga_event(struct snd_soc_dapm_widget *w,
692 struct snd_kcontrol *kcontrol, int event)
693 {
694 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
695 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
696 int reg, val;
697 int dcs_mask;
698 int dcs_l, dcs_r;
699 int dcs_l_reg, dcs_r_reg;
700 int timeout;
701 int pwr_reg;
702
703 /* This code is shared between HP and LINEOUT; we do all our
704 * power management in stereo pairs to avoid latency issues so
705 * we reuse shift to identify which rather than strcmp() the
706 * name. */
707 reg = w->shift;
708
709 switch (reg) {
710 case WM8904_ANALOGUE_HP_0:
711 pwr_reg = WM8904_POWER_MANAGEMENT_2;
712 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
713 dcs_r_reg = WM8904_DC_SERVO_8;
714 dcs_l_reg = WM8904_DC_SERVO_9;
715 dcs_l = 0;
716 dcs_r = 1;
717 break;
718 case WM8904_ANALOGUE_LINEOUT_0:
719 pwr_reg = WM8904_POWER_MANAGEMENT_3;
720 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
721 dcs_r_reg = WM8904_DC_SERVO_6;
722 dcs_l_reg = WM8904_DC_SERVO_7;
723 dcs_l = 2;
724 dcs_r = 3;
725 break;
726 default:
727 WARN(1, "Invalid reg %d\n", reg);
728 return -EINVAL;
729 }
730
731 switch (event) {
732 case SND_SOC_DAPM_PRE_PMU:
733 /* Power on the PGAs */
734 snd_soc_component_update_bits(component, pwr_reg,
735 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
736 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
737
738 /* Power on the amplifier */
739 snd_soc_component_update_bits(component, reg,
740 WM8904_HPL_ENA | WM8904_HPR_ENA,
741 WM8904_HPL_ENA | WM8904_HPR_ENA);
742
743
744 /* Enable the first stage */
745 snd_soc_component_update_bits(component, reg,
746 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
747 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
748
749 /* Power up the DC servo */
750 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
751 dcs_mask, dcs_mask);
752
753 /* Either calibrate the DC servo or restore cached state
754 * if we have that.
755 */
756 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
757 dev_dbg(component->dev, "Restoring DC servo state\n");
758
759 snd_soc_component_write(component, dcs_l_reg,
760 wm8904->dcs_state[dcs_l]);
761 snd_soc_component_write(component, dcs_r_reg,
762 wm8904->dcs_state[dcs_r]);
763
764 snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask);
765
766 timeout = 20;
767 } else {
768 dev_dbg(component->dev, "Calibrating DC servo\n");
769
770 snd_soc_component_write(component, WM8904_DC_SERVO_1,
771 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
772
773 timeout = 500;
774 }
775
776 /* Wait for DC servo to complete */
777 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
778 do {
779 val = snd_soc_component_read32(component, WM8904_DC_SERVO_READBACK_0);
780 if ((val & dcs_mask) == dcs_mask)
781 break;
782
783 msleep(1);
784 } while (--timeout);
785
786 if ((val & dcs_mask) != dcs_mask)
787 dev_warn(component->dev, "DC servo timed out\n");
788 else
789 dev_dbg(component->dev, "DC servo ready\n");
790
791 /* Enable the output stage */
792 snd_soc_component_update_bits(component, reg,
793 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
794 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
795 break;
796
797 case SND_SOC_DAPM_POST_PMU:
798 /* Unshort the output itself */
799 snd_soc_component_update_bits(component, reg,
800 WM8904_HPL_RMV_SHORT |
801 WM8904_HPR_RMV_SHORT,
802 WM8904_HPL_RMV_SHORT |
803 WM8904_HPR_RMV_SHORT);
804
805 break;
806
807 case SND_SOC_DAPM_PRE_PMD:
808 /* Short the output */
809 snd_soc_component_update_bits(component, reg,
810 WM8904_HPL_RMV_SHORT |
811 WM8904_HPR_RMV_SHORT, 0);
812 break;
813
814 case SND_SOC_DAPM_POST_PMD:
815 /* Cache the DC servo configuration; this will be
816 * invalidated if we change the configuration. */
817 wm8904->dcs_state[dcs_l] = snd_soc_component_read32(component, dcs_l_reg);
818 wm8904->dcs_state[dcs_r] = snd_soc_component_read32(component, dcs_r_reg);
819
820 snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
821 dcs_mask, 0);
822
823 /* Disable the amplifier input and output stages */
824 snd_soc_component_update_bits(component, reg,
825 WM8904_HPL_ENA | WM8904_HPR_ENA |
826 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
827 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
828 0);
829
830 /* PGAs too */
831 snd_soc_component_update_bits(component, pwr_reg,
832 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
833 0);
834 break;
835 }
836
837 return 0;
838 }
839
840 static const char *input_mode_text[] = {
841 "Single-Ended", "Differential Line", "Differential Mic"
842 };
843
844 static const char *lin_text[] = {
845 "IN1L", "IN2L", "IN3L"
846 };
847
848 static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
849 lin_text);
850
851 static const struct snd_kcontrol_new lin_mux =
852 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
853
854 static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
855 lin_text);
856
857 static const struct snd_kcontrol_new lin_inv_mux =
858 SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum);
859
860 static SOC_ENUM_SINGLE_DECL(lin_mode_enum,
861 WM8904_ANALOGUE_LEFT_INPUT_1, 0,
862 input_mode_text);
863
864 static const struct snd_kcontrol_new lin_mode =
865 SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum);
866
867 static const char *rin_text[] = {
868 "IN1R", "IN2R", "IN3R"
869 };
870
871 static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
872 rin_text);
873
874 static const struct snd_kcontrol_new rin_mux =
875 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
876
877 static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
878 rin_text);
879
880 static const struct snd_kcontrol_new rin_inv_mux =
881 SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum);
882
883 static SOC_ENUM_SINGLE_DECL(rin_mode_enum,
884 WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
885 input_mode_text);
886
887 static const struct snd_kcontrol_new rin_mode =
888 SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum);
889
890 static const char *aif_text[] = {
891 "Left", "Right"
892 };
893
894 static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
895 aif_text);
896
897 static const struct snd_kcontrol_new aifoutl_mux =
898 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
899
900 static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
901 aif_text);
902
903 static const struct snd_kcontrol_new aifoutr_mux =
904 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
905
906 static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
907 aif_text);
908
909 static const struct snd_kcontrol_new aifinl_mux =
910 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
911
912 static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
913 aif_text);
914
915 static const struct snd_kcontrol_new aifinr_mux =
916 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
917
918 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
919 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
920 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
921 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
922 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
923 };
924
925 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
926 SND_SOC_DAPM_INPUT("IN1L"),
927 SND_SOC_DAPM_INPUT("IN1R"),
928 SND_SOC_DAPM_INPUT("IN2L"),
929 SND_SOC_DAPM_INPUT("IN2R"),
930 SND_SOC_DAPM_INPUT("IN3L"),
931 SND_SOC_DAPM_INPUT("IN3R"),
932
933 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
934
935 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
936 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
937 &lin_inv_mux),
938 SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode),
939 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
940 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
941 &rin_inv_mux),
942 SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode),
943
944 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
945 NULL, 0),
946 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
947 NULL, 0),
948
949 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
950 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
951
952 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
953 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
954
955 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
956 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
957 };
958
959 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
960 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
961 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
962
963 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
964 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
965
966 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
967 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
968
969 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
970 SND_SOC_DAPM_POST_PMU),
971
972 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
973 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
974
975 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
976 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
977
978 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
979 0, NULL, 0, out_pga_event,
980 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
981 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
982 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
983 0, NULL, 0, out_pga_event,
984 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
985 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
986
987 SND_SOC_DAPM_OUTPUT("HPOUTL"),
988 SND_SOC_DAPM_OUTPUT("HPOUTR"),
989 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
990 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
991 };
992
993 static const char *out_mux_text[] = {
994 "DAC", "Bypass"
995 };
996
997 static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
998 out_mux_text);
999
1000 static const struct snd_kcontrol_new hpl_mux =
1001 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1002
1003 static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
1004 out_mux_text);
1005
1006 static const struct snd_kcontrol_new hpr_mux =
1007 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1008
1009 static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
1010 out_mux_text);
1011
1012 static const struct snd_kcontrol_new linel_mux =
1013 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1014
1015 static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
1016 out_mux_text);
1017
1018 static const struct snd_kcontrol_new liner_mux =
1019 SOC_DAPM_ENUM("LINER Mux", liner_enum);
1020
1021 static const char *sidetone_text[] = {
1022 "None", "Left", "Right"
1023 };
1024
1025 static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
1026 sidetone_text);
1027
1028 static const struct snd_kcontrol_new dacl_sidetone_mux =
1029 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1030
1031 static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
1032 sidetone_text);
1033
1034 static const struct snd_kcontrol_new dacr_sidetone_mux =
1035 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1036
1037 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1038 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1039 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1040 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1041
1042 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1043 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1044
1045 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1046 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1047 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1048 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1049 };
1050
1051 static const struct snd_soc_dapm_route core_intercon[] = {
1052 { "CLK_DSP", NULL, "SYSCLK" },
1053 { "TOCLK", NULL, "SYSCLK" },
1054 };
1055
1056 static const struct snd_soc_dapm_route adc_intercon[] = {
1057 { "Left Capture Mux", "IN1L", "IN1L" },
1058 { "Left Capture Mux", "IN2L", "IN2L" },
1059 { "Left Capture Mux", "IN3L", "IN3L" },
1060
1061 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1062 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1063 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1064
1065 { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
1066 { "Left Capture Mode", "Differential Line", "Left Capture Mux" },
1067 { "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" },
1068 { "Left Capture Mode", "Differential Mic", "Left Capture Mux" },
1069 { "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" },
1070
1071 { "Right Capture Mux", "IN1R", "IN1R" },
1072 { "Right Capture Mux", "IN2R", "IN2R" },
1073 { "Right Capture Mux", "IN3R", "IN3R" },
1074
1075 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1076 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1077 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1078
1079 { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
1080 { "Right Capture Mode", "Differential Line", "Right Capture Mux" },
1081 { "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" },
1082 { "Right Capture Mode", "Differential Mic", "Right Capture Mux" },
1083 { "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" },
1084
1085 { "Left Capture PGA", NULL, "Left Capture Mode" },
1086 { "Right Capture PGA", NULL, "Right Capture Mode" },
1087
1088 { "AIFOUTL Mux", "Left", "ADCL" },
1089 { "AIFOUTL Mux", "Right", "ADCR" },
1090 { "AIFOUTR Mux", "Left", "ADCL" },
1091 { "AIFOUTR Mux", "Right", "ADCR" },
1092
1093 { "AIFOUTL", NULL, "AIFOUTL Mux" },
1094 { "AIFOUTR", NULL, "AIFOUTR Mux" },
1095
1096 { "ADCL", NULL, "CLK_DSP" },
1097 { "ADCL", NULL, "Left Capture PGA" },
1098
1099 { "ADCR", NULL, "CLK_DSP" },
1100 { "ADCR", NULL, "Right Capture PGA" },
1101 };
1102
1103 static const struct snd_soc_dapm_route dac_intercon[] = {
1104 { "DACL Mux", "Left", "AIFINL" },
1105 { "DACL Mux", "Right", "AIFINR" },
1106
1107 { "DACR Mux", "Left", "AIFINL" },
1108 { "DACR Mux", "Right", "AIFINR" },
1109
1110 { "DACL", NULL, "DACL Mux" },
1111 { "DACL", NULL, "CLK_DSP" },
1112
1113 { "DACR", NULL, "DACR Mux" },
1114 { "DACR", NULL, "CLK_DSP" },
1115
1116 { "Charge pump", NULL, "SYSCLK" },
1117
1118 { "Headphone Output", NULL, "HPL PGA" },
1119 { "Headphone Output", NULL, "HPR PGA" },
1120 { "Headphone Output", NULL, "Charge pump" },
1121 { "Headphone Output", NULL, "TOCLK" },
1122
1123 { "Line Output", NULL, "LINEL PGA" },
1124 { "Line Output", NULL, "LINER PGA" },
1125 { "Line Output", NULL, "Charge pump" },
1126 { "Line Output", NULL, "TOCLK" },
1127
1128 { "HPOUTL", NULL, "Headphone Output" },
1129 { "HPOUTR", NULL, "Headphone Output" },
1130
1131 { "LINEOUTL", NULL, "Line Output" },
1132 { "LINEOUTR", NULL, "Line Output" },
1133 };
1134
1135 static const struct snd_soc_dapm_route wm8904_intercon[] = {
1136 { "Left Sidetone", "Left", "ADCL" },
1137 { "Left Sidetone", "Right", "ADCR" },
1138 { "DACL", NULL, "Left Sidetone" },
1139
1140 { "Right Sidetone", "Left", "ADCL" },
1141 { "Right Sidetone", "Right", "ADCR" },
1142 { "DACR", NULL, "Right Sidetone" },
1143
1144 { "Left Bypass", NULL, "Class G" },
1145 { "Left Bypass", NULL, "Left Capture PGA" },
1146
1147 { "Right Bypass", NULL, "Class G" },
1148 { "Right Bypass", NULL, "Right Capture PGA" },
1149
1150 { "HPL Mux", "DAC", "DACL" },
1151 { "HPL Mux", "Bypass", "Left Bypass" },
1152
1153 { "HPR Mux", "DAC", "DACR" },
1154 { "HPR Mux", "Bypass", "Right Bypass" },
1155
1156 { "LINEL Mux", "DAC", "DACL" },
1157 { "LINEL Mux", "Bypass", "Left Bypass" },
1158
1159 { "LINER Mux", "DAC", "DACR" },
1160 { "LINER Mux", "Bypass", "Right Bypass" },
1161
1162 { "HPL PGA", NULL, "HPL Mux" },
1163 { "HPR PGA", NULL, "HPR Mux" },
1164
1165 { "LINEL PGA", NULL, "LINEL Mux" },
1166 { "LINER PGA", NULL, "LINER Mux" },
1167 };
1168
1169 static const struct snd_soc_dapm_route wm8912_intercon[] = {
1170 { "HPL PGA", NULL, "DACL" },
1171 { "HPR PGA", NULL, "DACR" },
1172
1173 { "LINEL PGA", NULL, "DACL" },
1174 { "LINER PGA", NULL, "DACR" },
1175 };
1176
1177 static int wm8904_add_widgets(struct snd_soc_component *component)
1178 {
1179 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1180 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1181
1182 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
1183 ARRAY_SIZE(wm8904_core_dapm_widgets));
1184 snd_soc_dapm_add_routes(dapm, core_intercon,
1185 ARRAY_SIZE(core_intercon));
1186
1187 switch (wm8904->devtype) {
1188 case WM8904:
1189 snd_soc_add_component_controls(component, wm8904_adc_snd_controls,
1190 ARRAY_SIZE(wm8904_adc_snd_controls));
1191 snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
1192 ARRAY_SIZE(wm8904_dac_snd_controls));
1193 snd_soc_add_component_controls(component, wm8904_snd_controls,
1194 ARRAY_SIZE(wm8904_snd_controls));
1195
1196 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1197 ARRAY_SIZE(wm8904_adc_dapm_widgets));
1198 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1199 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1200 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1201 ARRAY_SIZE(wm8904_dapm_widgets));
1202
1203 snd_soc_dapm_add_routes(dapm, adc_intercon,
1204 ARRAY_SIZE(adc_intercon));
1205 snd_soc_dapm_add_routes(dapm, dac_intercon,
1206 ARRAY_SIZE(dac_intercon));
1207 snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1208 ARRAY_SIZE(wm8904_intercon));
1209 break;
1210
1211 case WM8912:
1212 snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
1213 ARRAY_SIZE(wm8904_dac_snd_controls));
1214
1215 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1216 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1217
1218 snd_soc_dapm_add_routes(dapm, dac_intercon,
1219 ARRAY_SIZE(dac_intercon));
1220 snd_soc_dapm_add_routes(dapm, wm8912_intercon,
1221 ARRAY_SIZE(wm8912_intercon));
1222 break;
1223 }
1224
1225 return 0;
1226 }
1227
1228 static struct {
1229 int ratio;
1230 unsigned int clk_sys_rate;
1231 } clk_sys_rates[] = {
1232 { 64, 0 },
1233 { 128, 1 },
1234 { 192, 2 },
1235 { 256, 3 },
1236 { 384, 4 },
1237 { 512, 5 },
1238 { 786, 6 },
1239 { 1024, 7 },
1240 { 1408, 8 },
1241 { 1536, 9 },
1242 };
1243
1244 static struct {
1245 int rate;
1246 int sample_rate;
1247 } sample_rates[] = {
1248 { 8000, 0 },
1249 { 11025, 1 },
1250 { 12000, 1 },
1251 { 16000, 2 },
1252 { 22050, 3 },
1253 { 24000, 3 },
1254 { 32000, 4 },
1255 { 44100, 5 },
1256 { 48000, 5 },
1257 };
1258
1259 static struct {
1260 int div; /* *10 due to .5s */
1261 int bclk_div;
1262 } bclk_divs[] = {
1263 { 10, 0 },
1264 { 15, 1 },
1265 { 20, 2 },
1266 { 30, 3 },
1267 { 40, 4 },
1268 { 50, 5 },
1269 { 55, 6 },
1270 { 60, 7 },
1271 { 80, 8 },
1272 { 100, 9 },
1273 { 110, 10 },
1274 { 120, 11 },
1275 { 160, 12 },
1276 { 200, 13 },
1277 { 220, 14 },
1278 { 240, 16 },
1279 { 200, 17 },
1280 { 320, 18 },
1281 { 440, 19 },
1282 { 480, 20 },
1283 };
1284
1285
1286 static int wm8904_hw_params(struct snd_pcm_substream *substream,
1287 struct snd_pcm_hw_params *params,
1288 struct snd_soc_dai *dai)
1289 {
1290 struct snd_soc_component *component = dai->component;
1291 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1292 int ret, i, best, best_val, cur_val;
1293 unsigned int aif1 = 0;
1294 unsigned int aif2 = 0;
1295 unsigned int aif3 = 0;
1296 unsigned int clock1 = 0;
1297 unsigned int dac_digital1 = 0;
1298
1299 /* What BCLK do we need? */
1300 wm8904->fs = params_rate(params);
1301 if (wm8904->tdm_slots) {
1302 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1303 wm8904->tdm_slots, wm8904->tdm_width);
1304 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1305 wm8904->tdm_width, 2,
1306 wm8904->tdm_slots);
1307 } else {
1308 wm8904->bclk = snd_soc_params_to_bclk(params);
1309 }
1310
1311 switch (params_width(params)) {
1312 case 16:
1313 break;
1314 case 20:
1315 aif1 |= 0x40;
1316 break;
1317 case 24:
1318 aif1 |= 0x80;
1319 break;
1320 case 32:
1321 aif1 |= 0xc0;
1322 break;
1323 default:
1324 return -EINVAL;
1325 }
1326
1327
1328 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1329
1330 ret = wm8904_configure_clocking(component);
1331 if (ret != 0)
1332 return ret;
1333
1334 /* Select nearest CLK_SYS_RATE */
1335 best = 0;
1336 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1337 - wm8904->fs);
1338 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1339 cur_val = abs((wm8904->sysclk_rate /
1340 clk_sys_rates[i].ratio) - wm8904->fs);
1341 if (cur_val < best_val) {
1342 best = i;
1343 best_val = cur_val;
1344 }
1345 }
1346 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1347 clk_sys_rates[best].ratio);
1348 clock1 |= (clk_sys_rates[best].clk_sys_rate
1349 << WM8904_CLK_SYS_RATE_SHIFT);
1350
1351 /* SAMPLE_RATE */
1352 best = 0;
1353 best_val = abs(wm8904->fs - sample_rates[0].rate);
1354 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1355 /* Closest match */
1356 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1357 if (cur_val < best_val) {
1358 best = i;
1359 best_val = cur_val;
1360 }
1361 }
1362 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1363 sample_rates[best].rate);
1364 clock1 |= (sample_rates[best].sample_rate
1365 << WM8904_SAMPLE_RATE_SHIFT);
1366
1367 /* Enable sloping stopband filter for low sample rates */
1368 if (wm8904->fs <= 24000)
1369 dac_digital1 |= WM8904_DAC_SB_FILT;
1370
1371 /* BCLK_DIV */
1372 best = 0;
1373 best_val = INT_MAX;
1374 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1375 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1376 - wm8904->bclk;
1377 if (cur_val < 0) /* Table is sorted */
1378 break;
1379 if (cur_val < best_val) {
1380 best = i;
1381 best_val = cur_val;
1382 }
1383 }
1384 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1385 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1386 bclk_divs[best].div, wm8904->bclk);
1387 aif2 |= bclk_divs[best].bclk_div;
1388
1389 /* LRCLK is a simple fraction of BCLK */
1390 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1391 aif3 |= wm8904->bclk / wm8904->fs;
1392
1393 /* Apply the settings */
1394 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
1395 WM8904_DAC_SB_FILT, dac_digital1);
1396 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1397 WM8904_AIF_WL_MASK, aif1);
1398 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2,
1399 WM8904_BCLK_DIV_MASK, aif2);
1400 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
1401 WM8904_LRCLK_RATE_MASK, aif3);
1402 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1,
1403 WM8904_SAMPLE_RATE_MASK |
1404 WM8904_CLK_SYS_RATE_MASK, clock1);
1405
1406 /* Update filters for the new settings */
1407 wm8904_set_retune_mobile(component);
1408 wm8904_set_deemph(component);
1409
1410 return 0;
1411 }
1412
1413 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1414 {
1415 struct snd_soc_component *component = dai->component;
1416 unsigned int aif1 = 0;
1417 unsigned int aif3 = 0;
1418
1419 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1420 case SND_SOC_DAIFMT_CBS_CFS:
1421 break;
1422 case SND_SOC_DAIFMT_CBS_CFM:
1423 aif3 |= WM8904_LRCLK_DIR;
1424 break;
1425 case SND_SOC_DAIFMT_CBM_CFS:
1426 aif1 |= WM8904_BCLK_DIR;
1427 break;
1428 case SND_SOC_DAIFMT_CBM_CFM:
1429 aif1 |= WM8904_BCLK_DIR;
1430 aif3 |= WM8904_LRCLK_DIR;
1431 break;
1432 default:
1433 return -EINVAL;
1434 }
1435
1436 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1437 case SND_SOC_DAIFMT_DSP_B:
1438 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
1439 /* fall through */
1440 case SND_SOC_DAIFMT_DSP_A:
1441 aif1 |= 0x3;
1442 break;
1443 case SND_SOC_DAIFMT_I2S:
1444 aif1 |= 0x2;
1445 break;
1446 case SND_SOC_DAIFMT_RIGHT_J:
1447 break;
1448 case SND_SOC_DAIFMT_LEFT_J:
1449 aif1 |= 0x1;
1450 break;
1451 default:
1452 return -EINVAL;
1453 }
1454
1455 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1456 case SND_SOC_DAIFMT_DSP_A:
1457 case SND_SOC_DAIFMT_DSP_B:
1458 /* frame inversion not valid for DSP modes */
1459 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1460 case SND_SOC_DAIFMT_NB_NF:
1461 break;
1462 case SND_SOC_DAIFMT_IB_NF:
1463 aif1 |= WM8904_AIF_BCLK_INV;
1464 break;
1465 default:
1466 return -EINVAL;
1467 }
1468 break;
1469
1470 case SND_SOC_DAIFMT_I2S:
1471 case SND_SOC_DAIFMT_RIGHT_J:
1472 case SND_SOC_DAIFMT_LEFT_J:
1473 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1474 case SND_SOC_DAIFMT_NB_NF:
1475 break;
1476 case SND_SOC_DAIFMT_IB_IF:
1477 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1478 break;
1479 case SND_SOC_DAIFMT_IB_NF:
1480 aif1 |= WM8904_AIF_BCLK_INV;
1481 break;
1482 case SND_SOC_DAIFMT_NB_IF:
1483 aif1 |= WM8904_AIF_LRCLK_INV;
1484 break;
1485 default:
1486 return -EINVAL;
1487 }
1488 break;
1489 default:
1490 return -EINVAL;
1491 }
1492
1493 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1494 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1495 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1496 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
1497 WM8904_LRCLK_DIR, aif3);
1498
1499 return 0;
1500 }
1501
1502
1503 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1504 unsigned int rx_mask, int slots, int slot_width)
1505 {
1506 struct snd_soc_component *component = dai->component;
1507 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1508 int aif1 = 0;
1509
1510 /* Don't need to validate anything if we're turning off TDM */
1511 if (slots == 0)
1512 goto out;
1513
1514 /* Note that we allow configurations we can't handle ourselves -
1515 * for example, we can generate clocks for slots 2 and up even if
1516 * we can't use those slots ourselves.
1517 */
1518 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1519
1520 switch (rx_mask) {
1521 case 3:
1522 break;
1523 case 0xc:
1524 aif1 |= WM8904_AIFADC_TDM_CHAN;
1525 break;
1526 default:
1527 return -EINVAL;
1528 }
1529
1530
1531 switch (tx_mask) {
1532 case 3:
1533 break;
1534 case 0xc:
1535 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1536 break;
1537 default:
1538 return -EINVAL;
1539 }
1540
1541 out:
1542 wm8904->tdm_width = slot_width;
1543 wm8904->tdm_slots = slots / 2;
1544
1545 snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1546 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1547 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1548
1549 return 0;
1550 }
1551
1552 struct _fll_div {
1553 u16 fll_fratio;
1554 u16 fll_outdiv;
1555 u16 fll_clk_ref_div;
1556 u16 n;
1557 u16 k;
1558 };
1559
1560 /* The size in bits of the FLL divide multiplied by 10
1561 * to allow rounding later */
1562 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1563
1564 static struct {
1565 unsigned int min;
1566 unsigned int max;
1567 u16 fll_fratio;
1568 int ratio;
1569 } fll_fratios[] = {
1570 { 0, 64000, 4, 16 },
1571 { 64000, 128000, 3, 8 },
1572 { 128000, 256000, 2, 4 },
1573 { 256000, 1000000, 1, 2 },
1574 { 1000000, 13500000, 0, 1 },
1575 };
1576
1577 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1578 unsigned int Fout)
1579 {
1580 u64 Kpart;
1581 unsigned int K, Ndiv, Nmod, target;
1582 unsigned int div;
1583 int i;
1584
1585 /* Fref must be <=13.5MHz */
1586 div = 1;
1587 fll_div->fll_clk_ref_div = 0;
1588 while ((Fref / div) > 13500000) {
1589 div *= 2;
1590 fll_div->fll_clk_ref_div++;
1591
1592 if (div > 8) {
1593 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1594 Fref);
1595 return -EINVAL;
1596 }
1597 }
1598
1599 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1600
1601 /* Apply the division for our remaining calculations */
1602 Fref /= div;
1603
1604 /* Fvco should be 90-100MHz; don't check the upper bound */
1605 div = 4;
1606 while (Fout * div < 90000000) {
1607 div++;
1608 if (div > 64) {
1609 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1610 Fout);
1611 return -EINVAL;
1612 }
1613 }
1614 target = Fout * div;
1615 fll_div->fll_outdiv = div - 1;
1616
1617 pr_debug("Fvco=%dHz\n", target);
1618
1619 /* Find an appropriate FLL_FRATIO and factor it out of the target */
1620 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1621 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1622 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1623 target /= fll_fratios[i].ratio;
1624 break;
1625 }
1626 }
1627 if (i == ARRAY_SIZE(fll_fratios)) {
1628 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1629 return -EINVAL;
1630 }
1631
1632 /* Now, calculate N.K */
1633 Ndiv = target / Fref;
1634
1635 fll_div->n = Ndiv;
1636 Nmod = target % Fref;
1637 pr_debug("Nmod=%d\n", Nmod);
1638
1639 /* Calculate fractional part - scale up so we can round. */
1640 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1641
1642 do_div(Kpart, Fref);
1643
1644 K = Kpart & 0xFFFFFFFF;
1645
1646 if ((K % 10) >= 5)
1647 K += 5;
1648
1649 /* Move down to proper range now rounding is done */
1650 fll_div->k = K / 10;
1651
1652 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1653 fll_div->n, fll_div->k,
1654 fll_div->fll_fratio, fll_div->fll_outdiv,
1655 fll_div->fll_clk_ref_div);
1656
1657 return 0;
1658 }
1659
1660 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1661 unsigned int Fref, unsigned int Fout)
1662 {
1663 struct snd_soc_component *component = dai->component;
1664 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1665 struct _fll_div fll_div;
1666 int ret, val;
1667 int clock2, fll1;
1668
1669 /* Any change? */
1670 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1671 Fout == wm8904->fll_fout)
1672 return 0;
1673
1674 clock2 = snd_soc_component_read32(component, WM8904_CLOCK_RATES_2);
1675
1676 if (Fout == 0) {
1677 dev_dbg(component->dev, "FLL disabled\n");
1678
1679 wm8904->fll_fref = 0;
1680 wm8904->fll_fout = 0;
1681
1682 /* Gate SYSCLK to avoid glitches */
1683 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1684 WM8904_CLK_SYS_ENA, 0);
1685
1686 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1687 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1688
1689 goto out;
1690 }
1691
1692 /* Validate the FLL ID */
1693 switch (source) {
1694 case WM8904_FLL_MCLK:
1695 case WM8904_FLL_LRCLK:
1696 case WM8904_FLL_BCLK:
1697 ret = fll_factors(&fll_div, Fref, Fout);
1698 if (ret != 0)
1699 return ret;
1700 break;
1701
1702 case WM8904_FLL_FREE_RUNNING:
1703 dev_dbg(component->dev, "Using free running FLL\n");
1704 /* Force 12MHz and output/4 for now */
1705 Fout = 12000000;
1706 Fref = 12000000;
1707
1708 memset(&fll_div, 0, sizeof(fll_div));
1709 fll_div.fll_outdiv = 3;
1710 break;
1711
1712 default:
1713 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
1714 return -EINVAL;
1715 }
1716
1717 /* Save current state then disable the FLL and SYSCLK to avoid
1718 * misclocking */
1719 fll1 = snd_soc_component_read32(component, WM8904_FLL_CONTROL_1);
1720 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1721 WM8904_CLK_SYS_ENA, 0);
1722 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1723 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1724
1725 /* Unlock forced oscilator control to switch it on/off */
1726 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
1727 WM8904_USER_KEY, WM8904_USER_KEY);
1728
1729 if (fll_id == WM8904_FLL_FREE_RUNNING) {
1730 val = WM8904_FLL_FRC_NCO;
1731 } else {
1732 val = 0;
1733 }
1734
1735 snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1736 val);
1737 snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
1738 WM8904_USER_KEY, 0);
1739
1740 switch (fll_id) {
1741 case WM8904_FLL_MCLK:
1742 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1743 WM8904_FLL_CLK_REF_SRC_MASK, 0);
1744 break;
1745
1746 case WM8904_FLL_LRCLK:
1747 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1748 WM8904_FLL_CLK_REF_SRC_MASK, 1);
1749 break;
1750
1751 case WM8904_FLL_BCLK:
1752 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1753 WM8904_FLL_CLK_REF_SRC_MASK, 2);
1754 break;
1755 }
1756
1757 if (fll_div.k)
1758 val = WM8904_FLL_FRACN_ENA;
1759 else
1760 val = 0;
1761 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1762 WM8904_FLL_FRACN_ENA, val);
1763
1764 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2,
1765 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1766 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1767 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1768
1769 snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k);
1770
1771 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1772 fll_div.n << WM8904_FLL_N_SHIFT);
1773
1774 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1775 WM8904_FLL_CLK_REF_DIV_MASK,
1776 fll_div.fll_clk_ref_div
1777 << WM8904_FLL_CLK_REF_DIV_SHIFT);
1778
1779 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1780
1781 wm8904->fll_fref = Fref;
1782 wm8904->fll_fout = Fout;
1783 wm8904->fll_src = source;
1784
1785 /* Enable the FLL if it was previously active */
1786 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1787 WM8904_FLL_OSC_ENA, fll1);
1788 snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1789 WM8904_FLL_ENA, fll1);
1790
1791 out:
1792 /* Reenable SYSCLK if it was previously active */
1793 snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1794 WM8904_CLK_SYS_ENA, clock2);
1795
1796 return 0;
1797 }
1798
1799 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1800 unsigned int freq, int dir)
1801 {
1802 struct snd_soc_component *component = dai->component;
1803 struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
1804 unsigned long mclk_freq;
1805 int ret;
1806
1807 switch (clk_id) {
1808 case WM8904_CLK_AUTO:
1809 /* We don't have any rate constraints, so just ignore the
1810 * request to disable constraining.
1811 */
1812 if (!freq)
1813 return 0;
1814
1815 mclk_freq = clk_get_rate(priv->mclk);
1816 /* enable FLL if a different sysclk is desired */
1817 if (mclk_freq != freq) {
1818 priv->sysclk_src = WM8904_CLK_FLL;
1819 ret = wm8904_set_fll(dai, WM8904_FLL_MCLK,
1820 WM8904_FLL_MCLK,
1821 mclk_freq, freq);
1822 if (ret)
1823 return ret;
1824 break;
1825 }
1826 clk_id = WM8904_CLK_MCLK;
1827 /* fallthrough */
1828
1829 case WM8904_CLK_MCLK:
1830 priv->sysclk_src = clk_id;
1831 priv->mclk_rate = freq;
1832 break;
1833
1834 case WM8904_CLK_FLL:
1835 priv->sysclk_src = clk_id;
1836 break;
1837
1838 default:
1839 return -EINVAL;
1840 }
1841
1842 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1843
1844 wm8904_configure_clocking(component);
1845
1846 return 0;
1847 }
1848
1849 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1850 {
1851 struct snd_soc_component *component = codec_dai->component;
1852 int val;
1853
1854 if (mute)
1855 val = WM8904_DAC_MUTE;
1856 else
1857 val = 0;
1858
1859 snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1860
1861 return 0;
1862 }
1863
1864 static int wm8904_set_bias_level(struct snd_soc_component *component,
1865 enum snd_soc_bias_level level)
1866 {
1867 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1868 int ret;
1869
1870 switch (level) {
1871 case SND_SOC_BIAS_ON:
1872 break;
1873
1874 case SND_SOC_BIAS_PREPARE:
1875 /* VMID resistance 2*50k */
1876 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1877 WM8904_VMID_RES_MASK,
1878 0x1 << WM8904_VMID_RES_SHIFT);
1879
1880 /* Normal bias current */
1881 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1882 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1883 break;
1884
1885 case SND_SOC_BIAS_STANDBY:
1886 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1887 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1888 wm8904->supplies);
1889 if (ret != 0) {
1890 dev_err(component->dev,
1891 "Failed to enable supplies: %d\n",
1892 ret);
1893 return ret;
1894 }
1895
1896 ret = clk_prepare_enable(wm8904->mclk);
1897 if (ret) {
1898 dev_err(component->dev,
1899 "Failed to enable MCLK: %d\n", ret);
1900 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1901 wm8904->supplies);
1902 return ret;
1903 }
1904
1905 regcache_cache_only(wm8904->regmap, false);
1906 regcache_sync(wm8904->regmap);
1907
1908 /* Enable bias */
1909 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1910 WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1911
1912 /* Enable VMID, VMID buffering, 2*5k resistance */
1913 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1914 WM8904_VMID_ENA |
1915 WM8904_VMID_RES_MASK,
1916 WM8904_VMID_ENA |
1917 0x3 << WM8904_VMID_RES_SHIFT);
1918
1919 /* Let VMID ramp */
1920 msleep(1);
1921 }
1922
1923 /* Maintain VMID with 2*250k */
1924 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1925 WM8904_VMID_RES_MASK,
1926 0x2 << WM8904_VMID_RES_SHIFT);
1927
1928 /* Bias current *0.5 */
1929 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1930 WM8904_ISEL_MASK, 0);
1931 break;
1932
1933 case SND_SOC_BIAS_OFF:
1934 /* Turn off VMID */
1935 snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1936 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1937
1938 /* Stop bias generation */
1939 snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1940 WM8904_BIAS_ENA, 0);
1941
1942 snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0);
1943 regcache_cache_only(wm8904->regmap, true);
1944 regcache_mark_dirty(wm8904->regmap);
1945
1946 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1947 wm8904->supplies);
1948 clk_disable_unprepare(wm8904->mclk);
1949 break;
1950 }
1951 return 0;
1952 }
1953
1954 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1955
1956 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1957 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1958
1959 static const struct snd_soc_dai_ops wm8904_dai_ops = {
1960 .set_sysclk = wm8904_set_sysclk,
1961 .set_fmt = wm8904_set_fmt,
1962 .set_tdm_slot = wm8904_set_tdm_slot,
1963 .set_pll = wm8904_set_fll,
1964 .hw_params = wm8904_hw_params,
1965 .digital_mute = wm8904_digital_mute,
1966 };
1967
1968 static struct snd_soc_dai_driver wm8904_dai = {
1969 .name = "wm8904-hifi",
1970 .playback = {
1971 .stream_name = "Playback",
1972 .channels_min = 2,
1973 .channels_max = 2,
1974 .rates = WM8904_RATES,
1975 .formats = WM8904_FORMATS,
1976 },
1977 .capture = {
1978 .stream_name = "Capture",
1979 .channels_min = 2,
1980 .channels_max = 2,
1981 .rates = WM8904_RATES,
1982 .formats = WM8904_FORMATS,
1983 },
1984 .ops = &wm8904_dai_ops,
1985 .symmetric_rates = 1,
1986 };
1987
1988 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component)
1989 {
1990 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1991 struct wm8904_pdata *pdata = wm8904->pdata;
1992 struct snd_kcontrol_new control =
1993 SOC_ENUM_EXT("EQ Mode",
1994 wm8904->retune_mobile_enum,
1995 wm8904_get_retune_mobile_enum,
1996 wm8904_put_retune_mobile_enum);
1997 int ret, i, j;
1998 const char **t;
1999
2000 /* We need an array of texts for the enum API but the number
2001 * of texts is likely to be less than the number of
2002 * configurations due to the sample rate dependency of the
2003 * configurations. */
2004 wm8904->num_retune_mobile_texts = 0;
2005 wm8904->retune_mobile_texts = NULL;
2006 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2007 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2008 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2009 wm8904->retune_mobile_texts[j]) == 0)
2010 break;
2011 }
2012
2013 if (j != wm8904->num_retune_mobile_texts)
2014 continue;
2015
2016 /* Expand the array... */
2017 t = krealloc(wm8904->retune_mobile_texts,
2018 sizeof(char *) *
2019 (wm8904->num_retune_mobile_texts + 1),
2020 GFP_KERNEL);
2021 if (t == NULL)
2022 continue;
2023
2024 /* ...store the new entry... */
2025 t[wm8904->num_retune_mobile_texts] =
2026 pdata->retune_mobile_cfgs[i].name;
2027
2028 /* ...and remember the new version. */
2029 wm8904->num_retune_mobile_texts++;
2030 wm8904->retune_mobile_texts = t;
2031 }
2032
2033 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
2034 wm8904->num_retune_mobile_texts);
2035
2036 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
2037 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2038
2039 ret = snd_soc_add_component_controls(component, &control, 1);
2040 if (ret != 0)
2041 dev_err(component->dev,
2042 "Failed to add ReTune Mobile control: %d\n", ret);
2043 }
2044
2045 static void wm8904_handle_pdata(struct snd_soc_component *component)
2046 {
2047 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2048 struct wm8904_pdata *pdata = wm8904->pdata;
2049 int ret, i;
2050
2051 if (!pdata) {
2052 snd_soc_add_component_controls(component, wm8904_eq_controls,
2053 ARRAY_SIZE(wm8904_eq_controls));
2054 return;
2055 }
2056
2057 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2058
2059 if (pdata->num_drc_cfgs) {
2060 struct snd_kcontrol_new control =
2061 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2062 wm8904_get_drc_enum, wm8904_put_drc_enum);
2063
2064 /* We need an array of texts for the enum API */
2065 wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs,
2066 sizeof(char *),
2067 GFP_KERNEL);
2068 if (!wm8904->drc_texts)
2069 return;
2070
2071 for (i = 0; i < pdata->num_drc_cfgs; i++)
2072 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2073
2074 wm8904->drc_enum.items = pdata->num_drc_cfgs;
2075 wm8904->drc_enum.texts = wm8904->drc_texts;
2076
2077 ret = snd_soc_add_component_controls(component, &control, 1);
2078 if (ret != 0)
2079 dev_err(component->dev,
2080 "Failed to add DRC mode control: %d\n", ret);
2081
2082 wm8904_set_drc(component);
2083 }
2084
2085 dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
2086 pdata->num_retune_mobile_cfgs);
2087
2088 if (pdata->num_retune_mobile_cfgs)
2089 wm8904_handle_retune_mobile_pdata(component);
2090 else
2091 snd_soc_add_component_controls(component, wm8904_eq_controls,
2092 ARRAY_SIZE(wm8904_eq_controls));
2093 }
2094
2095
2096 static int wm8904_probe(struct snd_soc_component *component)
2097 {
2098 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2099
2100 switch (wm8904->devtype) {
2101 case WM8904:
2102 break;
2103 case WM8912:
2104 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2105 break;
2106 default:
2107 dev_err(component->dev, "Unknown device type %d\n",
2108 wm8904->devtype);
2109 return -EINVAL;
2110 }
2111
2112 wm8904_handle_pdata(component);
2113
2114 wm8904_add_widgets(component);
2115
2116 return 0;
2117 }
2118
2119 static void wm8904_remove(struct snd_soc_component *component)
2120 {
2121 struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2122
2123 kfree(wm8904->retune_mobile_texts);
2124 kfree(wm8904->drc_texts);
2125 }
2126
2127 static const struct snd_soc_component_driver soc_component_dev_wm8904 = {
2128 .probe = wm8904_probe,
2129 .remove = wm8904_remove,
2130 .set_bias_level = wm8904_set_bias_level,
2131 .use_pmdown_time = 1,
2132 .endianness = 1,
2133 .non_legacy_dai_naming = 1,
2134 };
2135
2136 static const struct regmap_config wm8904_regmap = {
2137 .reg_bits = 8,
2138 .val_bits = 16,
2139
2140 .max_register = WM8904_MAX_REGISTER,
2141 .volatile_reg = wm8904_volatile_register,
2142 .readable_reg = wm8904_readable_register,
2143
2144 .cache_type = REGCACHE_RBTREE,
2145 .reg_defaults = wm8904_reg_defaults,
2146 .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
2147 };
2148
2149 #ifdef CONFIG_OF
2150 static const struct of_device_id wm8904_of_match[] = {
2151 {
2152 .compatible = "wlf,wm8904",
2153 .data = (void *)WM8904,
2154 }, {
2155 .compatible = "wlf,wm8912",
2156 .data = (void *)WM8912,
2157 }, {
2158 /* sentinel */
2159 }
2160 };
2161 MODULE_DEVICE_TABLE(of, wm8904_of_match);
2162 #endif
2163
2164 static int wm8904_i2c_probe(struct i2c_client *i2c,
2165 const struct i2c_device_id *id)
2166 {
2167 struct wm8904_priv *wm8904;
2168 unsigned int val;
2169 int ret, i;
2170
2171 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2172 GFP_KERNEL);
2173 if (wm8904 == NULL)
2174 return -ENOMEM;
2175
2176 wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
2177 if (IS_ERR(wm8904->mclk)) {
2178 ret = PTR_ERR(wm8904->mclk);
2179 dev_err(&i2c->dev, "Failed to get MCLK\n");
2180 return ret;
2181 }
2182
2183 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
2184 if (IS_ERR(wm8904->regmap)) {
2185 ret = PTR_ERR(wm8904->regmap);
2186 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2187 ret);
2188 return ret;
2189 }
2190
2191 if (i2c->dev.of_node) {
2192 const struct of_device_id *match;
2193
2194 match = of_match_node(wm8904_of_match, i2c->dev.of_node);
2195 if (match == NULL)
2196 return -EINVAL;
2197 wm8904->devtype = (enum wm8904_type)match->data;
2198 } else {
2199 wm8904->devtype = id->driver_data;
2200 }
2201
2202 i2c_set_clientdata(i2c, wm8904);
2203 wm8904->pdata = i2c->dev.platform_data;
2204
2205 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2206 wm8904->supplies[i].supply = wm8904_supply_names[i];
2207
2208 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2209 wm8904->supplies);
2210 if (ret != 0) {
2211 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2212 return ret;
2213 }
2214
2215 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2216 wm8904->supplies);
2217 if (ret != 0) {
2218 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2219 return ret;
2220 }
2221
2222 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2223 if (ret < 0) {
2224 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2225 goto err_enable;
2226 }
2227 if (val != 0x8904) {
2228 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2229 ret = -EINVAL;
2230 goto err_enable;
2231 }
2232
2233 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2234 if (ret < 0) {
2235 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2236 ret);
2237 goto err_enable;
2238 }
2239 dev_info(&i2c->dev, "revision %c\n", val + 'A');
2240
2241 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2242 if (ret < 0) {
2243 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2244 goto err_enable;
2245 }
2246
2247 /* Change some default settings - latch VU and enable ZC */
2248 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2249 WM8904_ADC_VU, WM8904_ADC_VU);
2250 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2251 WM8904_ADC_VU, WM8904_ADC_VU);
2252 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2253 WM8904_DAC_VU, WM8904_DAC_VU);
2254 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2255 WM8904_DAC_VU, WM8904_DAC_VU);
2256 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2257 WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2258 WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2259 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2260 WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2261 WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2262 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2263 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2264 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2265 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2266 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2267 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2268 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2269 WM8904_SR_MODE, 0);
2270
2271 /* Apply configuration from the platform data. */
2272 if (wm8904->pdata) {
2273 for (i = 0; i < WM8904_GPIO_REGS; i++) {
2274 if (!wm8904->pdata->gpio_cfg[i])
2275 continue;
2276
2277 regmap_update_bits(wm8904->regmap,
2278 WM8904_GPIO_CONTROL_1 + i,
2279 0xffff,
2280 wm8904->pdata->gpio_cfg[i]);
2281 }
2282
2283 /* Zero is the default value for these anyway */
2284 for (i = 0; i < WM8904_MIC_REGS; i++)
2285 regmap_update_bits(wm8904->regmap,
2286 WM8904_MIC_BIAS_CONTROL_0 + i,
2287 0xffff,
2288 wm8904->pdata->mic_cfg[i]);
2289 }
2290
2291 /* Set Class W by default - this will be managed by the Class
2292 * G widget at runtime where bypass paths are available.
2293 */
2294 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2295 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2296
2297 /* Use normal bias source */
2298 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2299 WM8904_POBCTRL, 0);
2300
2301 /* Can leave the device powered off until we need it */
2302 regcache_cache_only(wm8904->regmap, true);
2303 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2304
2305 ret = devm_snd_soc_register_component(&i2c->dev,
2306 &soc_component_dev_wm8904, &wm8904_dai, 1);
2307 if (ret != 0)
2308 return ret;
2309
2310 return 0;
2311
2312 err_enable:
2313 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2314 return ret;
2315 }
2316
2317 static const struct i2c_device_id wm8904_i2c_id[] = {
2318 { "wm8904", WM8904 },
2319 { "wm8912", WM8912 },
2320 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
2321 { }
2322 };
2323 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2324
2325 static struct i2c_driver wm8904_i2c_driver = {
2326 .driver = {
2327 .name = "wm8904",
2328 .of_match_table = of_match_ptr(wm8904_of_match),
2329 },
2330 .probe = wm8904_i2c_probe,
2331 .id_table = wm8904_i2c_id,
2332 };
2333
2334 module_i2c_driver(wm8904_i2c_driver);
2335
2336 MODULE_DESCRIPTION("ASoC WM8904 driver");
2337 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2338 MODULE_LICENSE("GPL");
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