sound/soc/codecs/wm8962.c

   1 /*
   2  * wm8962.c  --  WM8962 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/input.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/slab.h>
  26 #include <linux/workqueue.h>
  27 #include <sound/core.h>
  28 #include <sound/jack.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/initval.h>
  33 #include <sound/tlv.h>
  34 #include <sound/wm8962.h>
  35 #include <trace/events/asoc.h>
  36
  37 #include "wm8962.h"
  38
  39 #define WM8962_NUM_SUPPLIES 8
  40 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  41         "DCVDD",
  42         "DBVDD",
  43         "AVDD",
  44         "CPVDD",
  45         "MICVDD",
  46         "PLLVDD",
  47         "SPKVDD1",
  48         "SPKVDD2",
  49 };
  50
  51 /* codec private data */
  52 struct wm8962_priv {
  53         struct snd_soc_codec *codec;
  54
  55         int sysclk;
  56         int sysclk_rate;
  57
  58         int bclk;  /* Desired BCLK */
  59         int lrclk;
  60
  61         struct completion fll_lock;
  62         int fll_src;
  63         int fll_fref;
  64         int fll_fout;
  65
  66         struct delayed_work mic_work;
  67         struct snd_soc_jack *jack;
  68
  69         struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  70         struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  71
  72 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  73         struct input_dev *beep;
  74         struct work_struct beep_work;
  75         int beep_rate;
  76 #endif
  77
  78 #ifdef CONFIG_GPIOLIB
  79         struct gpio_chip gpio_chip;
  80 #endif
  81
  82         int irq;
  83 };
  84
  85 /* We can't use the same notifier block for more than one supply and
  86  * there's no way I can see to get from a callback to the caller
  87  * except container_of().
  88  */
  89 #define WM8962_REGULATOR_EVENT(n) \
  90 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  91                                     unsigned long event, void *data)    \
  92 { \
  93         struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  94                                                   disable_nb[n]); \
  95         if (event & REGULATOR_EVENT_DISABLE) { \
  96                 wm8962->codec->cache_sync = 1; \
  97         } \
  98         return 0; \
  99 }
 100
 101 WM8962_REGULATOR_EVENT(0)
 102 WM8962_REGULATOR_EVENT(1)
 103 WM8962_REGULATOR_EVENT(2)
 104 WM8962_REGULATOR_EVENT(3)
 105 WM8962_REGULATOR_EVENT(4)
 106 WM8962_REGULATOR_EVENT(5)
 107 WM8962_REGULATOR_EVENT(6)
 108 WM8962_REGULATOR_EVENT(7)
 109
 110 static const u16 wm8962_reg[WM8962_MAX_REGISTER + 1] = {
 111         [0] = 0x009F,     /* R0     - Left Input volume */
 112         [1] = 0x049F,     /* R1     - Right Input volume */
 113         [2] = 0x0000,     /* R2     - HPOUTL volume */
 114         [3] = 0x0000,     /* R3     - HPOUTR volume */
 115         [4] = 0x0020,     /* R4     - Clocking1 */
 116         [5] = 0x0018,     /* R5     - ADC & DAC Control 1 */
 117         [6] = 0x2008,     /* R6     - ADC & DAC Control 2 */
 118         [7] = 0x000A,     /* R7     - Audio Interface 0 */
 119         [8] = 0x01E4,     /* R8     - Clocking2 */
 120         [9] = 0x0300,     /* R9     - Audio Interface 1 */
 121         [10] = 0x00C0,    /* R10    - Left DAC volume */
 122         [11] = 0x00C0,    /* R11    - Right DAC volume */
 123
 124         [14] = 0x0040,     /* R14    - Audio Interface 2 */
 125         [15] = 0x6243,     /* R15    - Software Reset */
 126
 127         [17] = 0x007B,     /* R17    - ALC1 */
 128         [18] = 0x0000,     /* R18    - ALC2 */
 129         [19] = 0x1C32,     /* R19    - ALC3 */
 130         [20] = 0x3200,     /* R20    - Noise Gate */
 131         [21] = 0x00C0,     /* R21    - Left ADC volume */
 132         [22] = 0x00C0,     /* R22    - Right ADC volume */
 133         [23] = 0x0160,     /* R23    - Additional control(1) */
 134         [24] = 0x0000,     /* R24    - Additional control(2) */
 135         [25] = 0x0000,     /* R25    - Pwr Mgmt (1) */
 136         [26] = 0x0000,     /* R26    - Pwr Mgmt (2) */
 137         [27] = 0x0010,     /* R27    - Additional Control (3) */
 138         [28] = 0x0000,     /* R28    - Anti-pop */
 139
 140         [30] = 0x005E,     /* R30    - Clocking 3 */
 141         [31] = 0x0000,     /* R31    - Input mixer control (1) */
 142         [32] = 0x0145,     /* R32    - Left input mixer volume */
 143         [33] = 0x0145,     /* R33    - Right input mixer volume */
 144         [34] = 0x0009,     /* R34    - Input mixer control (2) */
 145         [35] = 0x0003,     /* R35    - Input bias control */
 146         [37] = 0x0008,     /* R37    - Left input PGA control */
 147         [38] = 0x0008,     /* R38    - Right input PGA control */
 148
 149         [40] = 0x0000,     /* R40    - SPKOUTL volume */
 150         [41] = 0x0000,     /* R41    - SPKOUTR volume */
 151
 152         [47] = 0x0000,     /* R47    - Thermal Shutdown Status */
 153         [48] = 0x8027,     /* R48    - Additional Control (4) */
 154         [49] = 0x0010,     /* R49    - Class D Control 1 */
 155
 156         [51] = 0x0003,     /* R51    - Class D Control 2 */
 157
 158         [56] = 0x0506,     /* R56    - Clocking 4 */
 159         [57] = 0x0000,     /* R57    - DAC DSP Mixing (1) */
 160         [58] = 0x0000,     /* R58    - DAC DSP Mixing (2) */
 161
 162         [60] = 0x0300,     /* R60    - DC Servo 0 */
 163         [61] = 0x0300,     /* R61    - DC Servo 1 */
 164
 165         [64] = 0x0810,     /* R64    - DC Servo 4 */
 166
 167         [66] = 0x0000,     /* R66    - DC Servo 6 */
 168
 169         [68] = 0x001B,     /* R68    - Analogue PGA Bias */
 170         [69] = 0x0000,     /* R69    - Analogue HP 0 */
 171
 172         [71] = 0x01FB,     /* R71    - Analogue HP 2 */
 173         [72] = 0x0000,     /* R72    - Charge Pump 1 */
 174
 175         [82] = 0x0004,     /* R82    - Charge Pump B */
 176
 177         [87] = 0x0000,     /* R87    - Write Sequencer Control 1 */
 178
 179         [90] = 0x0000,     /* R90    - Write Sequencer Control 2 */
 180
 181         [93] = 0x0000,     /* R93    - Write Sequencer Control 3 */
 182         [94] = 0x0000,     /* R94    - Control Interface */
 183
 184         [99] = 0x0000,     /* R99    - Mixer Enables */
 185         [100] = 0x0000,     /* R100   - Headphone Mixer (1) */
 186         [101] = 0x0000,     /* R101   - Headphone Mixer (2) */
 187         [102] = 0x013F,     /* R102   - Headphone Mixer (3) */
 188         [103] = 0x013F,     /* R103   - Headphone Mixer (4) */
 189
 190         [105] = 0x0000,     /* R105   - Speaker Mixer (1) */
 191         [106] = 0x0000,     /* R106   - Speaker Mixer (2) */
 192         [107] = 0x013F,     /* R107   - Speaker Mixer (3) */
 193         [108] = 0x013F,     /* R108   - Speaker Mixer (4) */
 194         [109] = 0x0003,     /* R109   - Speaker Mixer (5) */
 195         [110] = 0x0002,     /* R110   - Beep Generator (1) */
 196
 197         [115] = 0x0006,     /* R115   - Oscillator Trim (3) */
 198         [116] = 0x0026,     /* R116   - Oscillator Trim (4) */
 199
 200         [119] = 0x0000,     /* R119   - Oscillator Trim (7) */
 201
 202         [124] = 0x0011,     /* R124   - Analogue Clocking1 */
 203         [125] = 0x004B,     /* R125   - Analogue Clocking2 */
 204         [126] = 0x000D,     /* R126   - Analogue Clocking3 */
 205         [127] = 0x0000,     /* R127   - PLL Software Reset */
 206
 207         [129] = 0x0000,     /* R129   - PLL2 */
 208
 209         [131] = 0x0000,     /* R131   - PLL 4 */
 210
 211         [136] = 0x0067,     /* R136   - PLL 9 */
 212         [137] = 0x001C,     /* R137   - PLL 10 */
 213         [138] = 0x0071,     /* R138   - PLL 11 */
 214         [139] = 0x00C7,     /* R139   - PLL 12 */
 215         [140] = 0x0067,     /* R140   - PLL 13 */
 216         [141] = 0x0048,     /* R141   - PLL 14 */
 217         [142] = 0x0022,     /* R142   - PLL 15 */
 218         [143] = 0x0097,     /* R143   - PLL 16 */
 219
 220         [155] = 0x000C,     /* R155   - FLL Control (1) */
 221         [156] = 0x0039,     /* R156   - FLL Control (2) */
 222         [157] = 0x0180,     /* R157   - FLL Control (3) */
 223
 224         [159] = 0x0032,     /* R159   - FLL Control (5) */
 225         [160] = 0x0018,     /* R160   - FLL Control (6) */
 226         [161] = 0x007D,     /* R161   - FLL Control (7) */
 227         [162] = 0x0008,     /* R162   - FLL Control (8) */
 228
 229         [252] = 0x0005,     /* R252   - General test 1 */
 230
 231         [256] = 0x0000,     /* R256   - DF1 */
 232         [257] = 0x0000,     /* R257   - DF2 */
 233         [258] = 0x0000,     /* R258   - DF3 */
 234         [259] = 0x0000,     /* R259   - DF4 */
 235         [260] = 0x0000,     /* R260   - DF5 */
 236         [261] = 0x0000,     /* R261   - DF6 */
 237         [262] = 0x0000,     /* R262   - DF7 */
 238
 239         [264] = 0x0000,     /* R264   - LHPF1 */
 240         [265] = 0x0000,     /* R265   - LHPF2 */
 241
 242         [268] = 0x0000,     /* R268   - THREED1 */
 243         [269] = 0x0000,     /* R269   - THREED2 */
 244         [270] = 0x0000,     /* R270   - THREED3 */
 245         [271] = 0x0000,     /* R271   - THREED4 */
 246
 247         [276] = 0x000C,     /* R276   - DRC 1 */
 248         [277] = 0x0925,     /* R277   - DRC 2 */
 249         [278] = 0x0000,     /* R278   - DRC 3 */
 250         [279] = 0x0000,     /* R279   - DRC 4 */
 251         [280] = 0x0000,     /* R280   - DRC 5 */
 252
 253         [285] = 0x0000,     /* R285   - Tloopback */
 254
 255         [335] = 0x0004,     /* R335   - EQ1 */
 256         [336] = 0x6318,     /* R336   - EQ2 */
 257         [337] = 0x6300,     /* R337   - EQ3 */
 258         [338] = 0x0FCA,     /* R338   - EQ4 */
 259         [339] = 0x0400,     /* R339   - EQ5 */
 260         [340] = 0x00D8,     /* R340   - EQ6 */
 261         [341] = 0x1EB5,     /* R341   - EQ7 */
 262         [342] = 0xF145,     /* R342   - EQ8 */
 263         [343] = 0x0B75,     /* R343   - EQ9 */
 264         [344] = 0x01C5,     /* R344   - EQ10 */
 265         [345] = 0x1C58,     /* R345   - EQ11 */
 266         [346] = 0xF373,     /* R346   - EQ12 */
 267         [347] = 0x0A54,     /* R347   - EQ13 */
 268         [348] = 0x0558,     /* R348   - EQ14 */
 269         [349] = 0x168E,     /* R349   - EQ15 */
 270         [350] = 0xF829,     /* R350   - EQ16 */
 271         [351] = 0x07AD,     /* R351   - EQ17 */
 272         [352] = 0x1103,     /* R352   - EQ18 */
 273         [353] = 0x0564,     /* R353   - EQ19 */
 274         [354] = 0x0559,     /* R354   - EQ20 */
 275         [355] = 0x4000,     /* R355   - EQ21 */
 276         [356] = 0x6318,     /* R356   - EQ22 */
 277         [357] = 0x6300,     /* R357   - EQ23 */
 278         [358] = 0x0FCA,     /* R358   - EQ24 */
 279         [359] = 0x0400,     /* R359   - EQ25 */
 280         [360] = 0x00D8,     /* R360   - EQ26 */
 281         [361] = 0x1EB5,     /* R361   - EQ27 */
 282         [362] = 0xF145,     /* R362   - EQ28 */
 283         [363] = 0x0B75,     /* R363   - EQ29 */
 284         [364] = 0x01C5,     /* R364   - EQ30 */
 285         [365] = 0x1C58,     /* R365   - EQ31 */
 286         [366] = 0xF373,     /* R366   - EQ32 */
 287         [367] = 0x0A54,     /* R367   - EQ33 */
 288         [368] = 0x0558,     /* R368   - EQ34 */
 289         [369] = 0x168E,     /* R369   - EQ35 */
 290         [370] = 0xF829,     /* R370   - EQ36 */
 291         [371] = 0x07AD,     /* R371   - EQ37 */
 292         [372] = 0x1103,     /* R372   - EQ38 */
 293         [373] = 0x0564,     /* R373   - EQ39 */
 294         [374] = 0x0559,     /* R374   - EQ40 */
 295         [375] = 0x4000,     /* R375   - EQ41 */
 296
 297         [513] = 0x0000,     /* R513   - GPIO 2 */
 298         [514] = 0x0000,     /* R514   - GPIO 3 */
 299
 300         [516] = 0x8100,     /* R516   - GPIO 5 */
 301         [517] = 0x8100,     /* R517   - GPIO 6 */
 302
 303         [560] = 0x0000,     /* R560   - Interrupt Status 1 */
 304         [561] = 0x0000,     /* R561   - Interrupt Status 2 */
 305
 306         [568] = 0x0030,     /* R568   - Interrupt Status 1 Mask */
 307         [569] = 0xFFED,     /* R569   - Interrupt Status 2 Mask */
 308
 309         [576] = 0x0000,     /* R576   - Interrupt Control */
 310
 311         [584] = 0x002D,     /* R584   - IRQ Debounce */
 312
 313         [586] = 0x0000,     /* R586   -  MICINT Source Pol */
 314
 315         [768] = 0x1C00,     /* R768   - DSP2 Power Management */
 316
 317         [1037] = 0x0000,     /* R1037  - DSP2_ExecControl */
 318
 319         [8192] = 0x0000,     /* R8192  - DSP2 Instruction RAM 0 */
 320
 321         [9216] = 0x0030,     /* R9216  - DSP2 Address RAM 2 */
 322         [9217] = 0x0000,     /* R9217  - DSP2 Address RAM 1 */
 323         [9218] = 0x0000,     /* R9218  - DSP2 Address RAM 0 */
 324
 325         [12288] = 0x0000,     /* R12288 - DSP2 Data1 RAM 1 */
 326         [12289] = 0x0000,     /* R12289 - DSP2 Data1 RAM 0 */
 327
 328         [13312] = 0x0000,     /* R13312 - DSP2 Data2 RAM 1 */
 329         [13313] = 0x0000,     /* R13313 - DSP2 Data2 RAM 0 */
 330
 331         [14336] = 0x0000,     /* R14336 - DSP2 Data3 RAM 1 */
 332         [14337] = 0x0000,     /* R14337 - DSP2 Data3 RAM 0 */
 333
 334         [15360] = 0x000A,     /* R15360 - DSP2 Coeff RAM 0 */
 335
 336         [16384] = 0x0000,     /* R16384 - RETUNEADC_SHARED_COEFF_1 */
 337         [16385] = 0x0000,     /* R16385 - RETUNEADC_SHARED_COEFF_0 */
 338         [16386] = 0x0000,     /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
 339         [16387] = 0x0000,     /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
 340         [16388] = 0x0000,     /* R16388 - SOUNDSTAGE_ENABLES_1 */
 341         [16389] = 0x0000,     /* R16389 - SOUNDSTAGE_ENABLES_0 */
 342
 343         [16896] = 0x0002,     /* R16896 - HDBASS_AI_1 */
 344         [16897] = 0xBD12,     /* R16897 - HDBASS_AI_0 */
 345         [16898] = 0x007C,     /* R16898 - HDBASS_AR_1 */
 346         [16899] = 0x586C,     /* R16899 - HDBASS_AR_0 */
 347         [16900] = 0x0053,     /* R16900 - HDBASS_B_1 */
 348         [16901] = 0x8121,     /* R16901 - HDBASS_B_0 */
 349         [16902] = 0x003F,     /* R16902 - HDBASS_K_1 */
 350         [16903] = 0x8BD8,     /* R16903 - HDBASS_K_0 */
 351         [16904] = 0x0032,     /* R16904 - HDBASS_N1_1 */
 352         [16905] = 0xF52D,     /* R16905 - HDBASS_N1_0 */
 353         [16906] = 0x0065,     /* R16906 - HDBASS_N2_1 */
 354         [16907] = 0xAC8C,     /* R16907 - HDBASS_N2_0 */
 355         [16908] = 0x006B,     /* R16908 - HDBASS_N3_1 */
 356         [16909] = 0xE087,     /* R16909 - HDBASS_N3_0 */
 357         [16910] = 0x0072,     /* R16910 - HDBASS_N4_1 */
 358         [16911] = 0x1483,     /* R16911 - HDBASS_N4_0 */
 359         [16912] = 0x0072,     /* R16912 - HDBASS_N5_1 */
 360         [16913] = 0x1483,     /* R16913 - HDBASS_N5_0 */
 361         [16914] = 0x0043,     /* R16914 - HDBASS_X1_1 */
 362         [16915] = 0x3525,     /* R16915 - HDBASS_X1_0 */
 363         [16916] = 0x0006,     /* R16916 - HDBASS_X2_1 */
 364         [16917] = 0x6A4A,     /* R16917 - HDBASS_X2_0 */
 365         [16918] = 0x0043,     /* R16918 - HDBASS_X3_1 */
 366         [16919] = 0x6079,     /* R16919 - HDBASS_X3_0 */
 367         [16920] = 0x0008,     /* R16920 - HDBASS_ATK_1 */
 368         [16921] = 0x0000,     /* R16921 - HDBASS_ATK_0 */
 369         [16922] = 0x0001,     /* R16922 - HDBASS_DCY_1 */
 370         [16923] = 0x0000,     /* R16923 - HDBASS_DCY_0 */
 371         [16924] = 0x0059,     /* R16924 - HDBASS_PG_1 */
 372         [16925] = 0x999A,     /* R16925 - HDBASS_PG_0 */
 373
 374         [17048] = 0x0083,     /* R17408 - HPF_C_1 */
 375         [17049] = 0x98AD,     /* R17409 - HPF_C_0 */
 376
 377         [17920] = 0x007F,     /* R17920 - ADCL_RETUNE_C1_1 */
 378         [17921] = 0xFFFF,     /* R17921 - ADCL_RETUNE_C1_0 */
 379         [17922] = 0x0000,     /* R17922 - ADCL_RETUNE_C2_1 */
 380         [17923] = 0x0000,     /* R17923 - ADCL_RETUNE_C2_0 */
 381         [17924] = 0x0000,     /* R17924 - ADCL_RETUNE_C3_1 */
 382         [17925] = 0x0000,     /* R17925 - ADCL_RETUNE_C3_0 */
 383         [17926] = 0x0000,     /* R17926 - ADCL_RETUNE_C4_1 */
 384         [17927] = 0x0000,     /* R17927 - ADCL_RETUNE_C4_0 */
 385         [17928] = 0x0000,     /* R17928 - ADCL_RETUNE_C5_1 */
 386         [17929] = 0x0000,     /* R17929 - ADCL_RETUNE_C5_0 */
 387         [17930] = 0x0000,     /* R17930 - ADCL_RETUNE_C6_1 */
 388         [17931] = 0x0000,     /* R17931 - ADCL_RETUNE_C6_0 */
 389         [17932] = 0x0000,     /* R17932 - ADCL_RETUNE_C7_1 */
 390         [17933] = 0x0000,     /* R17933 - ADCL_RETUNE_C7_0 */
 391         [17934] = 0x0000,     /* R17934 - ADCL_RETUNE_C8_1 */
 392         [17935] = 0x0000,     /* R17935 - ADCL_RETUNE_C8_0 */
 393         [17936] = 0x0000,     /* R17936 - ADCL_RETUNE_C9_1 */
 394         [17937] = 0x0000,     /* R17937 - ADCL_RETUNE_C9_0 */
 395         [17938] = 0x0000,     /* R17938 - ADCL_RETUNE_C10_1 */
 396         [17939] = 0x0000,     /* R17939 - ADCL_RETUNE_C10_0 */
 397         [17940] = 0x0000,     /* R17940 - ADCL_RETUNE_C11_1 */
 398         [17941] = 0x0000,     /* R17941 - ADCL_RETUNE_C11_0 */
 399         [17942] = 0x0000,     /* R17942 - ADCL_RETUNE_C12_1 */
 400         [17943] = 0x0000,     /* R17943 - ADCL_RETUNE_C12_0 */
 401         [17944] = 0x0000,     /* R17944 - ADCL_RETUNE_C13_1 */
 402         [17945] = 0x0000,     /* R17945 - ADCL_RETUNE_C13_0 */
 403         [17946] = 0x0000,     /* R17946 - ADCL_RETUNE_C14_1 */
 404         [17947] = 0x0000,     /* R17947 - ADCL_RETUNE_C14_0 */
 405         [17948] = 0x0000,     /* R17948 - ADCL_RETUNE_C15_1 */
 406         [17949] = 0x0000,     /* R17949 - ADCL_RETUNE_C15_0 */
 407         [17950] = 0x0000,     /* R17950 - ADCL_RETUNE_C16_1 */
 408         [17951] = 0x0000,     /* R17951 - ADCL_RETUNE_C16_0 */
 409         [17952] = 0x0000,     /* R17952 - ADCL_RETUNE_C17_1 */
 410         [17953] = 0x0000,     /* R17953 - ADCL_RETUNE_C17_0 */
 411         [17954] = 0x0000,     /* R17954 - ADCL_RETUNE_C18_1 */
 412         [17955] = 0x0000,     /* R17955 - ADCL_RETUNE_C18_0 */
 413         [17956] = 0x0000,     /* R17956 - ADCL_RETUNE_C19_1 */
 414         [17957] = 0x0000,     /* R17957 - ADCL_RETUNE_C19_0 */
 415         [17958] = 0x0000,     /* R17958 - ADCL_RETUNE_C20_1 */
 416         [17959] = 0x0000,     /* R17959 - ADCL_RETUNE_C20_0 */
 417         [17960] = 0x0000,     /* R17960 - ADCL_RETUNE_C21_1 */
 418         [17961] = 0x0000,     /* R17961 - ADCL_RETUNE_C21_0 */
 419         [17962] = 0x0000,     /* R17962 - ADCL_RETUNE_C22_1 */
 420         [17963] = 0x0000,     /* R17963 - ADCL_RETUNE_C22_0 */
 421         [17964] = 0x0000,     /* R17964 - ADCL_RETUNE_C23_1 */
 422         [17965] = 0x0000,     /* R17965 - ADCL_RETUNE_C23_0 */
 423         [17966] = 0x0000,     /* R17966 - ADCL_RETUNE_C24_1 */
 424         [17967] = 0x0000,     /* R17967 - ADCL_RETUNE_C24_0 */
 425         [17968] = 0x0000,     /* R17968 - ADCL_RETUNE_C25_1 */
 426         [17969] = 0x0000,     /* R17969 - ADCL_RETUNE_C25_0 */
 427         [17970] = 0x0000,     /* R17970 - ADCL_RETUNE_C26_1 */
 428         [17971] = 0x0000,     /* R17971 - ADCL_RETUNE_C26_0 */
 429         [17972] = 0x0000,     /* R17972 - ADCL_RETUNE_C27_1 */
 430         [17973] = 0x0000,     /* R17973 - ADCL_RETUNE_C27_0 */
 431         [17974] = 0x0000,     /* R17974 - ADCL_RETUNE_C28_1 */
 432         [17975] = 0x0000,     /* R17975 - ADCL_RETUNE_C28_0 */
 433         [17976] = 0x0000,     /* R17976 - ADCL_RETUNE_C29_1 */
 434         [17977] = 0x0000,     /* R17977 - ADCL_RETUNE_C29_0 */
 435         [17978] = 0x0000,     /* R17978 - ADCL_RETUNE_C30_1 */
 436         [17979] = 0x0000,     /* R17979 - ADCL_RETUNE_C30_0 */
 437         [17980] = 0x0000,     /* R17980 - ADCL_RETUNE_C31_1 */
 438         [17981] = 0x0000,     /* R17981 - ADCL_RETUNE_C31_0 */
 439         [17982] = 0x0000,     /* R17982 - ADCL_RETUNE_C32_1 */
 440         [17983] = 0x0000,     /* R17983 - ADCL_RETUNE_C32_0 */
 441
 442         [18432] = 0x0020,     /* R18432 - RETUNEADC_PG2_1 */
 443         [18433] = 0x0000,     /* R18433 - RETUNEADC_PG2_0 */
 444         [18434] = 0x0040,     /* R18434 - RETUNEADC_PG_1 */
 445         [18435] = 0x0000,     /* R18435 - RETUNEADC_PG_0 */
 446
 447         [18944] = 0x007F,     /* R18944 - ADCR_RETUNE_C1_1 */
 448         [18945] = 0xFFFF,     /* R18945 - ADCR_RETUNE_C1_0 */
 449         [18946] = 0x0000,     /* R18946 - ADCR_RETUNE_C2_1 */
 450         [18947] = 0x0000,     /* R18947 - ADCR_RETUNE_C2_0 */
 451         [18948] = 0x0000,     /* R18948 - ADCR_RETUNE_C3_1 */
 452         [18949] = 0x0000,     /* R18949 - ADCR_RETUNE_C3_0 */
 453         [18950] = 0x0000,     /* R18950 - ADCR_RETUNE_C4_1 */
 454         [18951] = 0x0000,     /* R18951 - ADCR_RETUNE_C4_0 */
 455         [18952] = 0x0000,     /* R18952 - ADCR_RETUNE_C5_1 */
 456         [18953] = 0x0000,     /* R18953 - ADCR_RETUNE_C5_0 */
 457         [18954] = 0x0000,     /* R18954 - ADCR_RETUNE_C6_1 */
 458         [18955] = 0x0000,     /* R18955 - ADCR_RETUNE_C6_0 */
 459         [18956] = 0x0000,     /* R18956 - ADCR_RETUNE_C7_1 */
 460         [18957] = 0x0000,     /* R18957 - ADCR_RETUNE_C7_0 */
 461         [18958] = 0x0000,     /* R18958 - ADCR_RETUNE_C8_1 */
 462         [18959] = 0x0000,     /* R18959 - ADCR_RETUNE_C8_0 */
 463         [18960] = 0x0000,     /* R18960 - ADCR_RETUNE_C9_1 */
 464         [18961] = 0x0000,     /* R18961 - ADCR_RETUNE_C9_0 */
 465         [18962] = 0x0000,     /* R18962 - ADCR_RETUNE_C10_1 */
 466         [18963] = 0x0000,     /* R18963 - ADCR_RETUNE_C10_0 */
 467         [18964] = 0x0000,     /* R18964 - ADCR_RETUNE_C11_1 */
 468         [18965] = 0x0000,     /* R18965 - ADCR_RETUNE_C11_0 */
 469         [18966] = 0x0000,     /* R18966 - ADCR_RETUNE_C12_1 */
 470         [18967] = 0x0000,     /* R18967 - ADCR_RETUNE_C12_0 */
 471         [18968] = 0x0000,     /* R18968 - ADCR_RETUNE_C13_1 */
 472         [18969] = 0x0000,     /* R18969 - ADCR_RETUNE_C13_0 */
 473         [18970] = 0x0000,     /* R18970 - ADCR_RETUNE_C14_1 */
 474         [18971] = 0x0000,     /* R18971 - ADCR_RETUNE_C14_0 */
 475         [18972] = 0x0000,     /* R18972 - ADCR_RETUNE_C15_1 */
 476         [18973] = 0x0000,     /* R18973 - ADCR_RETUNE_C15_0 */
 477         [18974] = 0x0000,     /* R18974 - ADCR_RETUNE_C16_1 */
 478         [18975] = 0x0000,     /* R18975 - ADCR_RETUNE_C16_0 */
 479         [18976] = 0x0000,     /* R18976 - ADCR_RETUNE_C17_1 */
 480         [18977] = 0x0000,     /* R18977 - ADCR_RETUNE_C17_0 */
 481         [18978] = 0x0000,     /* R18978 - ADCR_RETUNE_C18_1 */
 482         [18979] = 0x0000,     /* R18979 - ADCR_RETUNE_C18_0 */
 483         [18980] = 0x0000,     /* R18980 - ADCR_RETUNE_C19_1 */
 484         [18981] = 0x0000,     /* R18981 - ADCR_RETUNE_C19_0 */
 485         [18982] = 0x0000,     /* R18982 - ADCR_RETUNE_C20_1 */
 486         [18983] = 0x0000,     /* R18983 - ADCR_RETUNE_C20_0 */
 487         [18984] = 0x0000,     /* R18984 - ADCR_RETUNE_C21_1 */
 488         [18985] = 0x0000,     /* R18985 - ADCR_RETUNE_C21_0 */
 489         [18986] = 0x0000,     /* R18986 - ADCR_RETUNE_C22_1 */
 490         [18987] = 0x0000,     /* R18987 - ADCR_RETUNE_C22_0 */
 491         [18988] = 0x0000,     /* R18988 - ADCR_RETUNE_C23_1 */
 492         [18989] = 0x0000,     /* R18989 - ADCR_RETUNE_C23_0 */
 493         [18990] = 0x0000,     /* R18990 - ADCR_RETUNE_C24_1 */
 494         [18991] = 0x0000,     /* R18991 - ADCR_RETUNE_C24_0 */
 495         [18992] = 0x0000,     /* R18992 - ADCR_RETUNE_C25_1 */
 496         [18993] = 0x0000,     /* R18993 - ADCR_RETUNE_C25_0 */
 497         [18994] = 0x0000,     /* R18994 - ADCR_RETUNE_C26_1 */
 498         [18995] = 0x0000,     /* R18995 - ADCR_RETUNE_C26_0 */
 499         [18996] = 0x0000,     /* R18996 - ADCR_RETUNE_C27_1 */
 500         [18997] = 0x0000,     /* R18997 - ADCR_RETUNE_C27_0 */
 501         [18998] = 0x0000,     /* R18998 - ADCR_RETUNE_C28_1 */
 502         [18999] = 0x0000,     /* R18999 - ADCR_RETUNE_C28_0 */
 503         [19000] = 0x0000,     /* R19000 - ADCR_RETUNE_C29_1 */
 504         [19001] = 0x0000,     /* R19001 - ADCR_RETUNE_C29_0 */
 505         [19002] = 0x0000,     /* R19002 - ADCR_RETUNE_C30_1 */
 506         [19003] = 0x0000,     /* R19003 - ADCR_RETUNE_C30_0 */
 507         [19004] = 0x0000,     /* R19004 - ADCR_RETUNE_C31_1 */
 508         [19005] = 0x0000,     /* R19005 - ADCR_RETUNE_C31_0 */
 509         [19006] = 0x0000,     /* R19006 - ADCR_RETUNE_C32_1 */
 510         [19007] = 0x0000,     /* R19007 - ADCR_RETUNE_C32_0 */
 511
 512         [19456] = 0x007F,     /* R19456 - DACL_RETUNE_C1_1 */
 513         [19457] = 0xFFFF,     /* R19457 - DACL_RETUNE_C1_0 */
 514         [19458] = 0x0000,     /* R19458 - DACL_RETUNE_C2_1 */
 515         [19459] = 0x0000,     /* R19459 - DACL_RETUNE_C2_0 */
 516         [19460] = 0x0000,     /* R19460 - DACL_RETUNE_C3_1 */
 517         [19461] = 0x0000,     /* R19461 - DACL_RETUNE_C3_0 */
 518         [19462] = 0x0000,     /* R19462 - DACL_RETUNE_C4_1 */
 519         [19463] = 0x0000,     /* R19463 - DACL_RETUNE_C4_0 */
 520         [19464] = 0x0000,     /* R19464 - DACL_RETUNE_C5_1 */
 521         [19465] = 0x0000,     /* R19465 - DACL_RETUNE_C5_0 */
 522         [19466] = 0x0000,     /* R19466 - DACL_RETUNE_C6_1 */
 523         [19467] = 0x0000,     /* R19467 - DACL_RETUNE_C6_0 */
 524         [19468] = 0x0000,     /* R19468 - DACL_RETUNE_C7_1 */
 525         [19469] = 0x0000,     /* R19469 - DACL_RETUNE_C7_0 */
 526         [19470] = 0x0000,     /* R19470 - DACL_RETUNE_C8_1 */
 527         [19471] = 0x0000,     /* R19471 - DACL_RETUNE_C8_0 */
 528         [19472] = 0x0000,     /* R19472 - DACL_RETUNE_C9_1 */
 529         [19473] = 0x0000,     /* R19473 - DACL_RETUNE_C9_0 */
 530         [19474] = 0x0000,     /* R19474 - DACL_RETUNE_C10_1 */
 531         [19475] = 0x0000,     /* R19475 - DACL_RETUNE_C10_0 */
 532         [19476] = 0x0000,     /* R19476 - DACL_RETUNE_C11_1 */
 533         [19477] = 0x0000,     /* R19477 - DACL_RETUNE_C11_0 */
 534         [19478] = 0x0000,     /* R19478 - DACL_RETUNE_C12_1 */
 535         [19479] = 0x0000,     /* R19479 - DACL_RETUNE_C12_0 */
 536         [19480] = 0x0000,     /* R19480 - DACL_RETUNE_C13_1 */
 537         [19481] = 0x0000,     /* R19481 - DACL_RETUNE_C13_0 */
 538         [19482] = 0x0000,     /* R19482 - DACL_RETUNE_C14_1 */
 539         [19483] = 0x0000,     /* R19483 - DACL_RETUNE_C14_0 */
 540         [19484] = 0x0000,     /* R19484 - DACL_RETUNE_C15_1 */
 541         [19485] = 0x0000,     /* R19485 - DACL_RETUNE_C15_0 */
 542         [19486] = 0x0000,     /* R19486 - DACL_RETUNE_C16_1 */
 543         [19487] = 0x0000,     /* R19487 - DACL_RETUNE_C16_0 */
 544         [19488] = 0x0000,     /* R19488 - DACL_RETUNE_C17_1 */
 545         [19489] = 0x0000,     /* R19489 - DACL_RETUNE_C17_0 */
 546         [19490] = 0x0000,     /* R19490 - DACL_RETUNE_C18_1 */
 547         [19491] = 0x0000,     /* R19491 - DACL_RETUNE_C18_0 */
 548         [19492] = 0x0000,     /* R19492 - DACL_RETUNE_C19_1 */
 549         [19493] = 0x0000,     /* R19493 - DACL_RETUNE_C19_0 */
 550         [19494] = 0x0000,     /* R19494 - DACL_RETUNE_C20_1 */
 551         [19495] = 0x0000,     /* R19495 - DACL_RETUNE_C20_0 */
 552         [19496] = 0x0000,     /* R19496 - DACL_RETUNE_C21_1 */
 553         [19497] = 0x0000,     /* R19497 - DACL_RETUNE_C21_0 */
 554         [19498] = 0x0000,     /* R19498 - DACL_RETUNE_C22_1 */
 555         [19499] = 0x0000,     /* R19499 - DACL_RETUNE_C22_0 */
 556         [19500] = 0x0000,     /* R19500 - DACL_RETUNE_C23_1 */
 557         [19501] = 0x0000,     /* R19501 - DACL_RETUNE_C23_0 */
 558         [19502] = 0x0000,     /* R19502 - DACL_RETUNE_C24_1 */
 559         [19503] = 0x0000,     /* R19503 - DACL_RETUNE_C24_0 */
 560         [19504] = 0x0000,     /* R19504 - DACL_RETUNE_C25_1 */
 561         [19505] = 0x0000,     /* R19505 - DACL_RETUNE_C25_0 */
 562         [19506] = 0x0000,     /* R19506 - DACL_RETUNE_C26_1 */
 563         [19507] = 0x0000,     /* R19507 - DACL_RETUNE_C26_0 */
 564         [19508] = 0x0000,     /* R19508 - DACL_RETUNE_C27_1 */
 565         [19509] = 0x0000,     /* R19509 - DACL_RETUNE_C27_0 */
 566         [19510] = 0x0000,     /* R19510 - DACL_RETUNE_C28_1 */
 567         [19511] = 0x0000,     /* R19511 - DACL_RETUNE_C28_0 */
 568         [19512] = 0x0000,     /* R19512 - DACL_RETUNE_C29_1 */
 569         [19513] = 0x0000,     /* R19513 - DACL_RETUNE_C29_0 */
 570         [19514] = 0x0000,     /* R19514 - DACL_RETUNE_C30_1 */
 571         [19515] = 0x0000,     /* R19515 - DACL_RETUNE_C30_0 */
 572         [19516] = 0x0000,     /* R19516 - DACL_RETUNE_C31_1 */
 573         [19517] = 0x0000,     /* R19517 - DACL_RETUNE_C31_0 */
 574         [19518] = 0x0000,     /* R19518 - DACL_RETUNE_C32_1 */
 575         [19519] = 0x0000,     /* R19519 - DACL_RETUNE_C32_0 */
 576
 577         [19968] = 0x0020,     /* R19968 - RETUNEDAC_PG2_1 */
 578         [19969] = 0x0000,     /* R19969 - RETUNEDAC_PG2_0 */
 579         [19970] = 0x0040,     /* R19970 - RETUNEDAC_PG_1 */
 580         [19971] = 0x0000,     /* R19971 - RETUNEDAC_PG_0 */
 581
 582         [20480] = 0x007F,     /* R20480 - DACR_RETUNE_C1_1 */
 583         [20481] = 0xFFFF,     /* R20481 - DACR_RETUNE_C1_0 */
 584         [20482] = 0x0000,     /* R20482 - DACR_RETUNE_C2_1 */
 585         [20483] = 0x0000,     /* R20483 - DACR_RETUNE_C2_0 */
 586         [20484] = 0x0000,     /* R20484 - DACR_RETUNE_C3_1 */
 587         [20485] = 0x0000,     /* R20485 - DACR_RETUNE_C3_0 */
 588         [20486] = 0x0000,     /* R20486 - DACR_RETUNE_C4_1 */
 589         [20487] = 0x0000,     /* R20487 - DACR_RETUNE_C4_0 */
 590         [20488] = 0x0000,     /* R20488 - DACR_RETUNE_C5_1 */
 591         [20489] = 0x0000,     /* R20489 - DACR_RETUNE_C5_0 */
 592         [20490] = 0x0000,     /* R20490 - DACR_RETUNE_C6_1 */
 593         [20491] = 0x0000,     /* R20491 - DACR_RETUNE_C6_0 */
 594         [20492] = 0x0000,     /* R20492 - DACR_RETUNE_C7_1 */
 595         [20493] = 0x0000,     /* R20493 - DACR_RETUNE_C7_0 */
 596         [20494] = 0x0000,     /* R20494 - DACR_RETUNE_C8_1 */
 597         [20495] = 0x0000,     /* R20495 - DACR_RETUNE_C8_0 */
 598         [20496] = 0x0000,     /* R20496 - DACR_RETUNE_C9_1 */
 599         [20497] = 0x0000,     /* R20497 - DACR_RETUNE_C9_0 */
 600         [20498] = 0x0000,     /* R20498 - DACR_RETUNE_C10_1 */
 601         [20499] = 0x0000,     /* R20499 - DACR_RETUNE_C10_0 */
 602         [20500] = 0x0000,     /* R20500 - DACR_RETUNE_C11_1 */
 603         [20501] = 0x0000,     /* R20501 - DACR_RETUNE_C11_0 */
 604         [20502] = 0x0000,     /* R20502 - DACR_RETUNE_C12_1 */
 605         [20503] = 0x0000,     /* R20503 - DACR_RETUNE_C12_0 */
 606         [20504] = 0x0000,     /* R20504 - DACR_RETUNE_C13_1 */
 607         [20505] = 0x0000,     /* R20505 - DACR_RETUNE_C13_0 */
 608         [20506] = 0x0000,     /* R20506 - DACR_RETUNE_C14_1 */
 609         [20507] = 0x0000,     /* R20507 - DACR_RETUNE_C14_0 */
 610         [20508] = 0x0000,     /* R20508 - DACR_RETUNE_C15_1 */
 611         [20509] = 0x0000,     /* R20509 - DACR_RETUNE_C15_0 */
 612         [20510] = 0x0000,     /* R20510 - DACR_RETUNE_C16_1 */
 613         [20511] = 0x0000,     /* R20511 - DACR_RETUNE_C16_0 */
 614         [20512] = 0x0000,     /* R20512 - DACR_RETUNE_C17_1 */
 615         [20513] = 0x0000,     /* R20513 - DACR_RETUNE_C17_0 */
 616         [20514] = 0x0000,     /* R20514 - DACR_RETUNE_C18_1 */
 617         [20515] = 0x0000,     /* R20515 - DACR_RETUNE_C18_0 */
 618         [20516] = 0x0000,     /* R20516 - DACR_RETUNE_C19_1 */
 619         [20517] = 0x0000,     /* R20517 - DACR_RETUNE_C19_0 */
 620         [20518] = 0x0000,     /* R20518 - DACR_RETUNE_C20_1 */
 621         [20519] = 0x0000,     /* R20519 - DACR_RETUNE_C20_0 */
 622         [20520] = 0x0000,     /* R20520 - DACR_RETUNE_C21_1 */
 623         [20521] = 0x0000,     /* R20521 - DACR_RETUNE_C21_0 */
 624         [20522] = 0x0000,     /* R20522 - DACR_RETUNE_C22_1 */
 625         [20523] = 0x0000,     /* R20523 - DACR_RETUNE_C22_0 */
 626         [20524] = 0x0000,     /* R20524 - DACR_RETUNE_C23_1 */
 627         [20525] = 0x0000,     /* R20525 - DACR_RETUNE_C23_0 */
 628         [20526] = 0x0000,     /* R20526 - DACR_RETUNE_C24_1 */
 629         [20527] = 0x0000,     /* R20527 - DACR_RETUNE_C24_0 */
 630         [20528] = 0x0000,     /* R20528 - DACR_RETUNE_C25_1 */
 631         [20529] = 0x0000,     /* R20529 - DACR_RETUNE_C25_0 */
 632         [20530] = 0x0000,     /* R20530 - DACR_RETUNE_C26_1 */
 633         [20531] = 0x0000,     /* R20531 - DACR_RETUNE_C26_0 */
 634         [20532] = 0x0000,     /* R20532 - DACR_RETUNE_C27_1 */
 635         [20533] = 0x0000,     /* R20533 - DACR_RETUNE_C27_0 */
 636         [20534] = 0x0000,     /* R20534 - DACR_RETUNE_C28_1 */
 637         [20535] = 0x0000,     /* R20535 - DACR_RETUNE_C28_0 */
 638         [20536] = 0x0000,     /* R20536 - DACR_RETUNE_C29_1 */
 639         [20537] = 0x0000,     /* R20537 - DACR_RETUNE_C29_0 */
 640         [20538] = 0x0000,     /* R20538 - DACR_RETUNE_C30_1 */
 641         [20539] = 0x0000,     /* R20539 - DACR_RETUNE_C30_0 */
 642         [20540] = 0x0000,     /* R20540 - DACR_RETUNE_C31_1 */
 643         [20541] = 0x0000,     /* R20541 - DACR_RETUNE_C31_0 */
 644         [20542] = 0x0000,     /* R20542 - DACR_RETUNE_C32_1 */
 645         [20543] = 0x0000,     /* R20543 - DACR_RETUNE_C32_0 */
 646
 647         [20992] = 0x008C,     /* R20992 - VSS_XHD2_1 */
 648         [20993] = 0x0200,     /* R20993 - VSS_XHD2_0 */
 649         [20994] = 0x0035,     /* R20994 - VSS_XHD3_1 */
 650         [20995] = 0x0700,     /* R20995 - VSS_XHD3_0 */
 651         [20996] = 0x003A,     /* R20996 - VSS_XHN1_1 */
 652         [20997] = 0x4100,     /* R20997 - VSS_XHN1_0 */
 653         [20998] = 0x008B,     /* R20998 - VSS_XHN2_1 */
 654         [20999] = 0x7D00,     /* R20999 - VSS_XHN2_0 */
 655         [21000] = 0x003A,     /* R21000 - VSS_XHN3_1 */
 656         [21001] = 0x4100,     /* R21001 - VSS_XHN3_0 */
 657         [21002] = 0x008C,     /* R21002 - VSS_XLA_1 */
 658         [21003] = 0xFEE8,     /* R21003 - VSS_XLA_0 */
 659         [21004] = 0x0078,     /* R21004 - VSS_XLB_1 */
 660         [21005] = 0x0000,     /* R21005 - VSS_XLB_0 */
 661         [21006] = 0x003F,     /* R21006 - VSS_XLG_1 */
 662         [21007] = 0xB260,     /* R21007 - VSS_XLG_0 */
 663         [21008] = 0x002D,     /* R21008 - VSS_PG2_1 */
 664         [21009] = 0x1818,     /* R21009 - VSS_PG2_0 */
 665         [21010] = 0x0020,     /* R21010 - VSS_PG_1 */
 666         [21011] = 0x0000,     /* R21011 - VSS_PG_0 */
 667         [21012] = 0x00F1,     /* R21012 - VSS_XTD1_1 */
 668         [21013] = 0x8340,     /* R21013 - VSS_XTD1_0 */
 669         [21014] = 0x00FB,     /* R21014 - VSS_XTD2_1 */
 670         [21015] = 0x8300,     /* R21015 - VSS_XTD2_0 */
 671         [21016] = 0x00EE,     /* R21016 - VSS_XTD3_1 */
 672         [21017] = 0xAEC0,     /* R21017 - VSS_XTD3_0 */
 673         [21018] = 0x00FB,     /* R21018 - VSS_XTD4_1 */
 674         [21019] = 0xAC40,     /* R21019 - VSS_XTD4_0 */
 675         [21020] = 0x00F1,     /* R21020 - VSS_XTD5_1 */
 676         [21021] = 0x7F80,     /* R21021 - VSS_XTD5_0 */
 677         [21022] = 0x00F4,     /* R21022 - VSS_XTD6_1 */
 678         [21023] = 0x3B40,     /* R21023 - VSS_XTD6_0 */
 679         [21024] = 0x00F5,     /* R21024 - VSS_XTD7_1 */
 680         [21025] = 0xFB00,     /* R21025 - VSS_XTD7_0 */
 681         [21026] = 0x00EA,     /* R21026 - VSS_XTD8_1 */
 682         [21027] = 0x10C0,     /* R21027 - VSS_XTD8_0 */
 683         [21028] = 0x00FC,     /* R21028 - VSS_XTD9_1 */
 684         [21029] = 0xC580,     /* R21029 - VSS_XTD9_0 */
 685         [21030] = 0x00E2,     /* R21030 - VSS_XTD10_1 */
 686         [21031] = 0x75C0,     /* R21031 - VSS_XTD10_0 */
 687         [21032] = 0x0004,     /* R21032 - VSS_XTD11_1 */
 688         [21033] = 0xB480,     /* R21033 - VSS_XTD11_0 */
 689         [21034] = 0x00D4,     /* R21034 - VSS_XTD12_1 */
 690         [21035] = 0xF980,     /* R21035 - VSS_XTD12_0 */
 691         [21036] = 0x0004,     /* R21036 - VSS_XTD13_1 */
 692         [21037] = 0x9140,     /* R21037 - VSS_XTD13_0 */
 693         [21038] = 0x00D8,     /* R21038 - VSS_XTD14_1 */
 694         [21039] = 0xA480,     /* R21039 - VSS_XTD14_0 */
 695         [21040] = 0x0002,     /* R21040 - VSS_XTD15_1 */
 696         [21041] = 0x3DC0,     /* R21041 - VSS_XTD15_0 */
 697         [21042] = 0x00CF,     /* R21042 - VSS_XTD16_1 */
 698         [21043] = 0x7A80,     /* R21043 - VSS_XTD16_0 */
 699         [21044] = 0x00DC,     /* R21044 - VSS_XTD17_1 */
 700         [21045] = 0x0600,     /* R21045 - VSS_XTD17_0 */
 701         [21046] = 0x00F2,     /* R21046 - VSS_XTD18_1 */
 702         [21047] = 0xDAC0,     /* R21047 - VSS_XTD18_0 */
 703         [21048] = 0x00BA,     /* R21048 - VSS_XTD19_1 */
 704         [21049] = 0xF340,     /* R21049 - VSS_XTD19_0 */
 705         [21050] = 0x000A,     /* R21050 - VSS_XTD20_1 */
 706         [21051] = 0x7940,     /* R21051 - VSS_XTD20_0 */
 707         [21052] = 0x001C,     /* R21052 - VSS_XTD21_1 */
 708         [21053] = 0x0680,     /* R21053 - VSS_XTD21_0 */
 709         [21054] = 0x00FD,     /* R21054 - VSS_XTD22_1 */
 710         [21055] = 0x2D00,     /* R21055 - VSS_XTD22_0 */
 711         [21056] = 0x001C,     /* R21056 - VSS_XTD23_1 */
 712         [21057] = 0xE840,     /* R21057 - VSS_XTD23_0 */
 713         [21058] = 0x000D,     /* R21058 - VSS_XTD24_1 */
 714         [21059] = 0xDC40,     /* R21059 - VSS_XTD24_0 */
 715         [21060] = 0x00FC,     /* R21060 - VSS_XTD25_1 */
 716         [21061] = 0x9D00,     /* R21061 - VSS_XTD25_0 */
 717         [21062] = 0x0009,     /* R21062 - VSS_XTD26_1 */
 718         [21063] = 0x5580,     /* R21063 - VSS_XTD26_0 */
 719         [21064] = 0x00FE,     /* R21064 - VSS_XTD27_1 */
 720         [21065] = 0x7E80,     /* R21065 - VSS_XTD27_0 */
 721         [21066] = 0x000E,     /* R21066 - VSS_XTD28_1 */
 722         [21067] = 0xAB40,     /* R21067 - VSS_XTD28_0 */
 723         [21068] = 0x00F9,     /* R21068 - VSS_XTD29_1 */
 724         [21069] = 0x9880,     /* R21069 - VSS_XTD29_0 */
 725         [21070] = 0x0009,     /* R21070 - VSS_XTD30_1 */
 726         [21071] = 0x87C0,     /* R21071 - VSS_XTD30_0 */
 727         [21072] = 0x00FD,     /* R21072 - VSS_XTD31_1 */
 728         [21073] = 0x2C40,     /* R21073 - VSS_XTD31_0 */
 729         [21074] = 0x0009,     /* R21074 - VSS_XTD32_1 */
 730         [21075] = 0x4800,     /* R21075 - VSS_XTD32_0 */
 731         [21076] = 0x0003,     /* R21076 - VSS_XTS1_1 */
 732         [21077] = 0x5F40,     /* R21077 - VSS_XTS1_0 */
 733         [21078] = 0x0000,     /* R21078 - VSS_XTS2_1 */
 734         [21079] = 0x8700,     /* R21079 - VSS_XTS2_0 */
 735         [21080] = 0x00FA,     /* R21080 - VSS_XTS3_1 */
 736         [21081] = 0xE4C0,     /* R21081 - VSS_XTS3_0 */
 737         [21082] = 0x0000,     /* R21082 - VSS_XTS4_1 */
 738         [21083] = 0x0B40,     /* R21083 - VSS_XTS4_0 */
 739         [21084] = 0x0004,     /* R21084 - VSS_XTS5_1 */
 740         [21085] = 0xE180,     /* R21085 - VSS_XTS5_0 */
 741         [21086] = 0x0001,     /* R21086 - VSS_XTS6_1 */
 742         [21087] = 0x1F40,     /* R21087 - VSS_XTS6_0 */
 743         [21088] = 0x00F8,     /* R21088 - VSS_XTS7_1 */
 744         [21089] = 0xB000,     /* R21089 - VSS_XTS7_0 */
 745         [21090] = 0x00FB,     /* R21090 - VSS_XTS8_1 */
 746         [21091] = 0xCBC0,     /* R21091 - VSS_XTS8_0 */
 747         [21092] = 0x0004,     /* R21092 - VSS_XTS9_1 */
 748         [21093] = 0xF380,     /* R21093 - VSS_XTS9_0 */
 749         [21094] = 0x0007,     /* R21094 - VSS_XTS10_1 */
 750         [21095] = 0xDF40,     /* R21095 - VSS_XTS10_0 */
 751         [21096] = 0x00FF,     /* R21096 - VSS_XTS11_1 */
 752         [21097] = 0x0700,     /* R21097 - VSS_XTS11_0 */
 753         [21098] = 0x00EF,     /* R21098 - VSS_XTS12_1 */
 754         [21099] = 0xD700,     /* R21099 - VSS_XTS12_0 */
 755         [21100] = 0x00FB,     /* R21100 - VSS_XTS13_1 */
 756         [21101] = 0xAF40,     /* R21101 - VSS_XTS13_0 */
 757         [21102] = 0x0010,     /* R21102 - VSS_XTS14_1 */
 758         [21103] = 0x8A80,     /* R21103 - VSS_XTS14_0 */
 759         [21104] = 0x0011,     /* R21104 - VSS_XTS15_1 */
 760         [21105] = 0x07C0,     /* R21105 - VSS_XTS15_0 */
 761         [21106] = 0x00E0,     /* R21106 - VSS_XTS16_1 */
 762         [21107] = 0x0800,     /* R21107 - VSS_XTS16_0 */
 763         [21108] = 0x00D2,     /* R21108 - VSS_XTS17_1 */
 764         [21109] = 0x7600,     /* R21109 - VSS_XTS17_0 */
 765         [21110] = 0x0020,     /* R21110 - VSS_XTS18_1 */
 766         [21111] = 0xCF40,     /* R21111 - VSS_XTS18_0 */
 767         [21112] = 0x0030,     /* R21112 - VSS_XTS19_1 */
 768         [21113] = 0x2340,     /* R21113 - VSS_XTS19_0 */
 769         [21114] = 0x00FD,     /* R21114 - VSS_XTS20_1 */
 770         [21115] = 0x69C0,     /* R21115 - VSS_XTS20_0 */
 771         [21116] = 0x0028,     /* R21116 - VSS_XTS21_1 */
 772         [21117] = 0x3500,     /* R21117 - VSS_XTS21_0 */
 773         [21118] = 0x0006,     /* R21118 - VSS_XTS22_1 */
 774         [21119] = 0x3300,     /* R21119 - VSS_XTS22_0 */
 775         [21120] = 0x00D9,     /* R21120 - VSS_XTS23_1 */
 776         [21121] = 0xF6C0,     /* R21121 - VSS_XTS23_0 */
 777         [21122] = 0x00F3,     /* R21122 - VSS_XTS24_1 */
 778         [21123] = 0x3340,     /* R21123 - VSS_XTS24_0 */
 779         [21124] = 0x000F,     /* R21124 - VSS_XTS25_1 */
 780         [21125] = 0x4200,     /* R21125 - VSS_XTS25_0 */
 781         [21126] = 0x0004,     /* R21126 - VSS_XTS26_1 */
 782         [21127] = 0x0C80,     /* R21127 - VSS_XTS26_0 */
 783         [21128] = 0x00FB,     /* R21128 - VSS_XTS27_1 */
 784         [21129] = 0x3F80,     /* R21129 - VSS_XTS27_0 */
 785         [21130] = 0x00F7,     /* R21130 - VSS_XTS28_1 */
 786         [21131] = 0x57C0,     /* R21131 - VSS_XTS28_0 */
 787         [21132] = 0x0003,     /* R21132 - VSS_XTS29_1 */
 788         [21133] = 0x5400,     /* R21133 - VSS_XTS29_0 */
 789         [21134] = 0x0000,     /* R21134 - VSS_XTS30_1 */
 790         [21135] = 0xC6C0,     /* R21135 - VSS_XTS30_0 */
 791         [21136] = 0x0003,     /* R21136 - VSS_XTS31_1 */
 792         [21137] = 0x12C0,     /* R21137 - VSS_XTS31_0 */
 793         [21138] = 0x00FD,     /* R21138 - VSS_XTS32_1 */
 794         [21139] = 0x8580,     /* R21139 - VSS_XTS32_0 */
 795 };
 796
 797 static const struct wm8962_reg_access {
 798         u16 read;
 799         u16 write;
 800         u16 vol;
 801 } wm8962_reg_access[WM8962_MAX_REGISTER + 1] = {
 802         [0] = { 0x00FF, 0x01FF, 0x0000 }, /* R0     - Left Input volume */
 803         [1] = { 0xFEFF, 0x01FF, 0xFFFF }, /* R1     - Right Input volume */
 804         [2] = { 0x00FF, 0x01FF, 0x0000 }, /* R2     - HPOUTL volume */
 805         [3] = { 0x00FF, 0x01FF, 0x0000 }, /* R3     - HPOUTR volume */
 806         [4] = { 0x07FE, 0x07FE, 0xFFFF }, /* R4     - Clocking1 */
 807         [5] = { 0x007F, 0x007F, 0x0000 }, /* R5     - ADC & DAC Control 1 */
 808         [6] = { 0x37ED, 0x37ED, 0x0000 }, /* R6     - ADC & DAC Control 2 */
 809         [7] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R7     - Audio Interface 0 */
 810         [8] = { 0x0FEF, 0x0FEF, 0xFFFF }, /* R8     - Clocking2 */
 811         [9] = { 0x0B9F, 0x039F, 0x0000 }, /* R9     - Audio Interface 1 */
 812         [10] = { 0x00FF, 0x01FF, 0x0000 }, /* R10    - Left DAC volume */
 813         [11] = { 0x00FF, 0x01FF, 0x0000 }, /* R11    - Right DAC volume */
 814         [14] = { 0x07FF, 0x07FF, 0x0000 }, /* R14    - Audio Interface 2 */
 815         [15] = { 0xFFFF, 0xFFFF, 0xFFFF }, /* R15    - Software Reset */
 816         [17] = { 0x07FF, 0x07FF, 0x0000 }, /* R17    - ALC1 */
 817         [18] = { 0xF8FF, 0x00FF, 0xFFFF }, /* R18    - ALC2 */
 818         [19] = { 0x1DFF, 0x1DFF, 0x0000 }, /* R19    - ALC3 */
 819         [20] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20    - Noise Gate */
 820         [21] = { 0x00FF, 0x01FF, 0x0000 }, /* R21    - Left ADC volume */
 821         [22] = { 0x00FF, 0x01FF, 0x0000 }, /* R22    - Right ADC volume */
 822         [23] = { 0x0161, 0x0161, 0x0000 }, /* R23    - Additional control(1) */
 823         [24] = { 0x0008, 0x0008, 0x0000 }, /* R24    - Additional control(2) */
 824         [25] = { 0x07FE, 0x07FE, 0x0000 }, /* R25    - Pwr Mgmt (1) */
 825         [26] = { 0x01FB, 0x01FB, 0x0000 }, /* R26    - Pwr Mgmt (2) */
 826         [27] = { 0x0017, 0x0017, 0x0000 }, /* R27    - Additional Control (3) */
 827         [28] = { 0x001C, 0x001C, 0x0000 }, /* R28    - Anti-pop */
 828
 829         [30] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R30    - Clocking 3 */
 830         [31] = { 0x000F, 0x000F, 0x0000 }, /* R31    - Input mixer control (1) */
 831         [32] = { 0x01FF, 0x01FF, 0x0000 }, /* R32    - Left input mixer volume */
 832         [33] = { 0x01FF, 0x01FF, 0x0000 }, /* R33    - Right input mixer volume */
 833         [34] = { 0x003F, 0x003F, 0x0000 }, /* R34    - Input mixer control (2) */
 834         [35] = { 0x003F, 0x003F, 0x0000 }, /* R35    - Input bias control */
 835         [37] = { 0x001F, 0x001F, 0x0000 }, /* R37    - Left input PGA control */
 836         [38] = { 0x001F, 0x001F, 0x0000 }, /* R38    - Right input PGA control */
 837         [40] = { 0x00FF, 0x01FF, 0x0000 }, /* R40    - SPKOUTL volume */
 838         [41] = { 0x00FF, 0x01FF, 0x0000 }, /* R41    - SPKOUTR volume */
 839
 840         [47] = { 0x000F, 0x0000, 0x0000 }, /* R47    - Thermal Shutdown Status */
 841         [48] = { 0x7EC7, 0x7E07, 0xFFFF }, /* R48    - Additional Control (4) */
 842         [49] = { 0x00D3, 0x00D7, 0xFFFF }, /* R49    - Class D Control 1 */
 843         [51] = { 0x0047, 0x0047, 0x0000 }, /* R51    - Class D Control 2 */
 844         [56] = { 0x001E, 0x001E, 0x0000 }, /* R56    - Clocking 4 */
 845         [57] = { 0x02FC, 0x02FC, 0x0000 }, /* R57    - DAC DSP Mixing (1) */
 846         [58] = { 0x00FC, 0x00FC, 0x0000 }, /* R58    - DAC DSP Mixing (2) */
 847         [60] = { 0x00CC, 0x00CC, 0x0000 }, /* R60    - DC Servo 0 */
 848         [61] = { 0x00DD, 0x00DD, 0x0000 }, /* R61    - DC Servo 1 */
 849         [64] = { 0x3F80, 0x3F80, 0x0000 }, /* R64    - DC Servo 4 */
 850         [66] = { 0x0780, 0x0000, 0xFFFF }, /* R66    - DC Servo 6 */
 851         [68] = { 0x0007, 0x0007, 0x0000 }, /* R68    - Analogue PGA Bias */
 852         [69] = { 0x00FF, 0x00FF, 0x0000 }, /* R69    - Analogue HP 0 */
 853         [71] = { 0x01FF, 0x01FF, 0x0000 }, /* R71    - Analogue HP 2 */
 854         [72] = { 0x0001, 0x0001, 0x0000 }, /* R72    - Charge Pump 1 */
 855         [82] = { 0x0001, 0x0001, 0x0000 }, /* R82    - Charge Pump B */
 856         [87] = { 0x00A0, 0x00A0, 0x0000 }, /* R87    - Write Sequencer Control 1 */
 857         [90] = { 0x007F, 0x01FF, 0x0000 }, /* R90    - Write Sequencer Control 2 */
 858         [93] = { 0x03F9, 0x0000, 0x0000 }, /* R93    - Write Sequencer Control 3 */
 859         [94] = { 0x0070, 0x0070, 0x0000 }, /* R94    - Control Interface */
 860         [99] = { 0x000F, 0x000F, 0x0000 }, /* R99    - Mixer Enables */
 861         [100] = { 0x00BF, 0x00BF, 0x0000 }, /* R100   - Headphone Mixer (1) */
 862         [101] = { 0x00BF, 0x00BF, 0x0000 }, /* R101   - Headphone Mixer (2) */
 863         [102] = { 0x01FF, 0x01FF, 0x0000 }, /* R102   - Headphone Mixer (3) */
 864         [103] = { 0x01FF, 0x01FF, 0x0000 }, /* R103   - Headphone Mixer (4) */
 865         [105] = { 0x00BF, 0x00BF, 0x0000 }, /* R105   - Speaker Mixer (1) */
 866         [106] = { 0x00BF, 0x00BF, 0x0000 }, /* R106   - Speaker Mixer (2) */
 867         [107] = { 0x01FF, 0x01FF, 0x0000 }, /* R107   - Speaker Mixer (3) */
 868         [108] = { 0x01FF, 0x01FF, 0x0000 }, /* R108   - Speaker Mixer (4) */
 869         [109] = { 0x00F0, 0x00F0, 0x0000 }, /* R109   - Speaker Mixer (5) */
 870         [110] = { 0x00F7, 0x00F7, 0x0000 }, /* R110   - Beep Generator (1) */
 871         [115] = { 0x001F, 0x001F, 0x0000 }, /* R115   - Oscillator Trim (3) */
 872         [116] = { 0x001F, 0x001F, 0x0000 }, /* R116   - Oscillator Trim (4) */
 873         [119] = { 0x00FF, 0x00FF, 0x0000 }, /* R119   - Oscillator Trim (7) */
 874         [124] = { 0x0079, 0x0079, 0x0000 }, /* R124   - Analogue Clocking1 */
 875         [125] = { 0x00DF, 0x00DF, 0x0000 }, /* R125   - Analogue Clocking2 */
 876         [126] = { 0x000D, 0x000D, 0x0000 }, /* R126   - Analogue Clocking3 */
 877         [127] = { 0x0000, 0xFFFF, 0x0000 }, /* R127   - PLL Software Reset */
 878         [129] = { 0x00B0, 0x00B0, 0x0000 }, /* R129   - PLL2 */
 879         [131] = { 0x0003, 0x0003, 0x0000 }, /* R131   - PLL 4 */
 880         [136] = { 0x005F, 0x005F, 0x0000 }, /* R136   - PLL 9 */
 881         [137] = { 0x00FF, 0x00FF, 0x0000 }, /* R137   - PLL 10 */
 882         [138] = { 0x00FF, 0x00FF, 0x0000 }, /* R138   - PLL 11 */
 883         [139] = { 0x00FF, 0x00FF, 0x0000 }, /* R139   - PLL 12 */
 884         [140] = { 0x005F, 0x005F, 0x0000 }, /* R140   - PLL 13 */
 885         [141] = { 0x00FF, 0x00FF, 0x0000 }, /* R141   - PLL 14 */
 886         [142] = { 0x00FF, 0x00FF, 0x0000 }, /* R142   - PLL 15 */
 887         [143] = { 0x00FF, 0x00FF, 0x0000 }, /* R143   - PLL 16 */
 888         [155] = { 0x0067, 0x0067, 0x0000 }, /* R155   - FLL Control (1) */
 889         [156] = { 0x01FB, 0x01FB, 0x0000 }, /* R156   - FLL Control (2) */
 890         [157] = { 0x0007, 0x0007, 0x0000 }, /* R157   - FLL Control (3) */
 891         [159] = { 0x007F, 0x007F, 0x0000 }, /* R159   - FLL Control (5) */
 892         [160] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R160   - FLL Control (6) */
 893         [161] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R161   - FLL Control (7) */
 894         [162] = { 0x03FF, 0x03FF, 0x0000 }, /* R162   - FLL Control (8) */
 895         [252] = { 0x0005, 0x0005, 0x0000 }, /* R252   - General test 1 */
 896         [256] = { 0x000F, 0x000F, 0x0000 }, /* R256   - DF1 */
 897         [257] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R257   - DF2 */
 898         [258] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R258   - DF3 */
 899         [259] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R259   - DF4 */
 900         [260] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R260   - DF5 */
 901         [261] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R261   - DF6 */
 902         [262] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R262   - DF7 */
 903         [264] = { 0x0003, 0x0003, 0x0000 }, /* R264   - LHPF1 */
 904         [265] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R265   - LHPF2 */
 905         [268] = { 0x0077, 0x0077, 0x0000 }, /* R268   - THREED1 */
 906         [269] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R269   - THREED2 */
 907         [270] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R270   - THREED3 */
 908         [271] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R271   - THREED4 */
 909         [276] = { 0x7FFF, 0x7FFF, 0x0000 }, /* R276   - DRC 1 */
 910         [277] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R277   - DRC 2 */
 911         [278] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R278   - DRC 3 */
 912         [279] = { 0x07FF, 0x07FF, 0x0000 }, /* R279   - DRC 4 */
 913         [280] = { 0x03FF, 0x03FF, 0x0000 }, /* R280   - DRC 5 */
 914         [285] = { 0x0003, 0x0003, 0x0000 }, /* R285   - Tloopback */
 915         [335] = { 0x0007, 0x0007, 0x0000 }, /* R335   - EQ1 */
 916         [336] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R336   - EQ2 */
 917         [337] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R337   - EQ3 */
 918         [338] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R338   - EQ4 */
 919         [339] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R339   - EQ5 */
 920         [340] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R340   - EQ6 */
 921         [341] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R341   - EQ7 */
 922         [342] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R342   - EQ8 */
 923         [343] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R343   - EQ9 */
 924         [344] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R344   - EQ10 */
 925         [345] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R345   - EQ11 */
 926         [346] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R346   - EQ12 */
 927         [347] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R347   - EQ13 */
 928         [348] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R348   - EQ14 */
 929         [349] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R349   - EQ15 */
 930         [350] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R350   - EQ16 */
 931         [351] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R351   - EQ17 */
 932         [352] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R352   - EQ18 */
 933         [353] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R353   - EQ19 */
 934         [354] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R354   - EQ20 */
 935         [355] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R355   - EQ21 */
 936         [356] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R356   - EQ22 */
 937         [357] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R357   - EQ23 */
 938         [358] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R358   - EQ24 */
 939         [359] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R359   - EQ25 */
 940         [360] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R360   - EQ26 */
 941         [361] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R361   - EQ27 */
 942         [362] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R362   - EQ28 */
 943         [363] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R363   - EQ29 */
 944         [364] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R364   - EQ30 */
 945         [365] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R365   - EQ31 */
 946         [366] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R366   - EQ32 */
 947         [367] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R367   - EQ33 */
 948         [368] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R368   - EQ34 */
 949         [369] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R369   - EQ35 */
 950         [370] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R370   - EQ36 */
 951         [371] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R371   - EQ37 */
 952         [372] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R372   - EQ38 */
 953         [373] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R373   - EQ39 */
 954         [374] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R374   - EQ40 */
 955         [375] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R375   - EQ41 */
 956         [513] = { 0x045F, 0x045F, 0x0000 }, /* R513   - GPIO 2 */
 957         [514] = { 0x045F, 0x045F, 0x0000 }, /* R514   - GPIO 3 */
 958         [516] = { 0xE75F, 0xE75F, 0x0000 }, /* R516   - GPIO 5 */
 959         [517] = { 0xE75F, 0xE75F, 0x0000 }, /* R517   - GPIO 6 */
 960         [560] = { 0x0030, 0x0030, 0xFFFF }, /* R560   - Interrupt Status 1 */
 961         [561] = { 0xFFED, 0xFFED, 0xFFFF }, /* R561   - Interrupt Status 2 */
 962         [568] = { 0x0030, 0x0030, 0x0000 }, /* R568   - Interrupt Status 1 Mask */
 963         [569] = { 0xFFED, 0xFFED, 0x0000 }, /* R569   - Interrupt Status 2 Mask */
 964         [576] = { 0x0001, 0x0001, 0x0000 }, /* R576   - Interrupt Control */
 965         [584] = { 0x002D, 0x002D, 0x0000 }, /* R584   - IRQ Debounce */
 966         [586] = { 0xC000, 0xC000, 0x0000 }, /* R586   -  MICINT Source Pol */
 967         [768] = { 0x0001, 0x0001, 0x0000 }, /* R768   - DSP2 Power Management */
 968         [1037] = { 0x0000, 0x003F, 0x0000 }, /* R1037  - DSP2_ExecControl */
 969         [4096] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4096  - Write Sequencer 0 */
 970         [4097] = { 0x00FF, 0x00FF, 0x0000 }, /* R4097  - Write Sequencer 1 */
 971         [4098] = { 0x070F, 0x070F, 0x0000 }, /* R4098  - Write Sequencer 2 */
 972         [4099] = { 0x010F, 0x010F, 0x0000 }, /* R4099  - Write Sequencer 3 */
 973         [4100] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4100  - Write Sequencer 4 */
 974         [4101] = { 0x00FF, 0x00FF, 0x0000 }, /* R4101  - Write Sequencer 5 */
 975         [4102] = { 0x070F, 0x070F, 0x0000 }, /* R4102  - Write Sequencer 6 */
 976         [4103] = { 0x010F, 0x010F, 0x0000 }, /* R4103  - Write Sequencer 7 */
 977         [4104] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4104  - Write Sequencer 8 */
 978         [4105] = { 0x00FF, 0x00FF, 0x0000 }, /* R4105  - Write Sequencer 9 */
 979         [4106] = { 0x070F, 0x070F, 0x0000 }, /* R4106  - Write Sequencer 10 */
 980         [4107] = { 0x010F, 0x010F, 0x0000 }, /* R4107  - Write Sequencer 11 */
 981         [4108] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4108  - Write Sequencer 12 */
 982         [4109] = { 0x00FF, 0x00FF, 0x0000 }, /* R4109  - Write Sequencer 13 */
 983         [4110] = { 0x070F, 0x070F, 0x0000 }, /* R4110  - Write Sequencer 14 */
 984         [4111] = { 0x010F, 0x010F, 0x0000 }, /* R4111  - Write Sequencer 15 */
 985         [4112] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4112  - Write Sequencer 16 */
 986         [4113] = { 0x00FF, 0x00FF, 0x0000 }, /* R4113  - Write Sequencer 17 */
 987         [4114] = { 0x070F, 0x070F, 0x0000 }, /* R4114  - Write Sequencer 18 */
 988         [4115] = { 0x010F, 0x010F, 0x0000 }, /* R4115  - Write Sequencer 19 */
 989         [4116] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4116  - Write Sequencer 20 */
 990         [4117] = { 0x00FF, 0x00FF, 0x0000 }, /* R4117  - Write Sequencer 21 */
 991         [4118] = { 0x070F, 0x070F, 0x0000 }, /* R4118  - Write Sequencer 22 */
 992         [4119] = { 0x010F, 0x010F, 0x0000 }, /* R4119  - Write Sequencer 23 */
 993         [4120] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4120  - Write Sequencer 24 */
 994         [4121] = { 0x00FF, 0x00FF, 0x0000 }, /* R4121  - Write Sequencer 25 */
 995         [4122] = { 0x070F, 0x070F, 0x0000 }, /* R4122  - Write Sequencer 26 */
 996         [4123] = { 0x010F, 0x010F, 0x0000 }, /* R4123  - Write Sequencer 27 */
 997         [4124] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4124  - Write Sequencer 28 */
 998         [4125] = { 0x00FF, 0x00FF, 0x0000 }, /* R4125  - Write Sequencer 29 */
 999         [4126] = { 0x070F, 0x070F, 0x0000 }, /* R4126  - Write Sequencer 30 */
1000         [4127] = { 0x010F, 0x010F, 0x0000 }, /* R4127  - Write Sequencer 31 */
1001         [4128] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4128  - Write Sequencer 32 */
1002         [4129] = { 0x00FF, 0x00FF, 0x0000 }, /* R4129  - Write Sequencer 33 */
1003         [4130] = { 0x070F, 0x070F, 0x0000 }, /* R4130  - Write Sequencer 34 */
1004         [4131] = { 0x010F, 0x010F, 0x0000 }, /* R4131  - Write Sequencer 35 */
1005         [4132] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4132  - Write Sequencer 36 */
1006         [4133] = { 0x00FF, 0x00FF, 0x0000 }, /* R4133  - Write Sequencer 37 */
1007         [4134] = { 0x070F, 0x070F, 0x0000 }, /* R4134  - Write Sequencer 38 */
1008         [4135] = { 0x010F, 0x010F, 0x0000 }, /* R4135  - Write Sequencer 39 */
1009         [4136] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4136  - Write Sequencer 40 */
1010         [4137] = { 0x00FF, 0x00FF, 0x0000 }, /* R4137  - Write Sequencer 41 */
1011         [4138] = { 0x070F, 0x070F, 0x0000 }, /* R4138  - Write Sequencer 42 */
1012         [4139] = { 0x010F, 0x010F, 0x0000 }, /* R4139  - Write Sequencer 43 */
1013         [4140] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4140  - Write Sequencer 44 */
1014         [4141] = { 0x00FF, 0x00FF, 0x0000 }, /* R4141  - Write Sequencer 45 */
1015         [4142] = { 0x070F, 0x070F, 0x0000 }, /* R4142  - Write Sequencer 46 */
1016         [4143] = { 0x010F, 0x010F, 0x0000 }, /* R4143  - Write Sequencer 47 */
1017         [4144] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4144  - Write Sequencer 48 */
1018         [4145] = { 0x00FF, 0x00FF, 0x0000 }, /* R4145  - Write Sequencer 49 */
1019         [4146] = { 0x070F, 0x070F, 0x0000 }, /* R4146  - Write Sequencer 50 */
1020         [4147] = { 0x010F, 0x010F, 0x0000 }, /* R4147  - Write Sequencer 51 */
1021         [4148] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4148  - Write Sequencer 52 */
1022         [4149] = { 0x00FF, 0x00FF, 0x0000 }, /* R4149  - Write Sequencer 53 */
1023         [4150] = { 0x070F, 0x070F, 0x0000 }, /* R4150  - Write Sequencer 54 */
1024         [4151] = { 0x010F, 0x010F, 0x0000 }, /* R4151  - Write Sequencer 55 */
1025         [4152] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4152  - Write Sequencer 56 */
1026         [4153] = { 0x00FF, 0x00FF, 0x0000 }, /* R4153  - Write Sequencer 57 */
1027         [4154] = { 0x070F, 0x070F, 0x0000 }, /* R4154  - Write Sequencer 58 */
1028         [4155] = { 0x010F, 0x010F, 0x0000 }, /* R4155  - Write Sequencer 59 */
1029         [4156] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4156  - Write Sequencer 60 */
1030         [4157] = { 0x00FF, 0x00FF, 0x0000 }, /* R4157  - Write Sequencer 61 */
1031         [4158] = { 0x070F, 0x070F, 0x0000 }, /* R4158  - Write Sequencer 62 */
1032         [4159] = { 0x010F, 0x010F, 0x0000 }, /* R4159  - Write Sequencer 63 */
1033         [4160] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4160  - Write Sequencer 64 */
1034         [4161] = { 0x00FF, 0x00FF, 0x0000 }, /* R4161  - Write Sequencer 65 */
1035         [4162] = { 0x070F, 0x070F, 0x0000 }, /* R4162  - Write Sequencer 66 */
1036         [4163] = { 0x010F, 0x010F, 0x0000 }, /* R4163  - Write Sequencer 67 */
1037         [4164] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4164  - Write Sequencer 68 */
1038         [4165] = { 0x00FF, 0x00FF, 0x0000 }, /* R4165  - Write Sequencer 69 */
1039         [4166] = { 0x070F, 0x070F, 0x0000 }, /* R4166  - Write Sequencer 70 */
1040         [4167] = { 0x010F, 0x010F, 0x0000 }, /* R4167  - Write Sequencer 71 */
1041         [4168] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4168  - Write Sequencer 72 */
1042         [4169] = { 0x00FF, 0x00FF, 0x0000 }, /* R4169  - Write Sequencer 73 */
1043         [4170] = { 0x070F, 0x070F, 0x0000 }, /* R4170  - Write Sequencer 74 */
1044         [4171] = { 0x010F, 0x010F, 0x0000 }, /* R4171  - Write Sequencer 75 */
1045         [4172] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4172  - Write Sequencer 76 */
1046         [4173] = { 0x00FF, 0x00FF, 0x0000 }, /* R4173  - Write Sequencer 77 */
1047         [4174] = { 0x070F, 0x070F, 0x0000 }, /* R4174  - Write Sequencer 78 */
1048         [4175] = { 0x010F, 0x010F, 0x0000 }, /* R4175  - Write Sequencer 79 */
1049         [4176] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4176  - Write Sequencer 80 */
1050         [4177] = { 0x00FF, 0x00FF, 0x0000 }, /* R4177  - Write Sequencer 81 */
1051         [4178] = { 0x070F, 0x070F, 0x0000 }, /* R4178  - Write Sequencer 82 */
1052         [4179] = { 0x010F, 0x010F, 0x0000 }, /* R4179  - Write Sequencer 83 */
1053         [4180] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4180  - Write Sequencer 84 */
1054         [4181] = { 0x00FF, 0x00FF, 0x0000 }, /* R4181  - Write Sequencer 85 */
1055         [4182] = { 0x070F, 0x070F, 0x0000 }, /* R4182  - Write Sequencer 86 */
1056         [4183] = { 0x010F, 0x010F, 0x0000 }, /* R4183  - Write Sequencer 87 */
1057         [4184] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4184  - Write Sequencer 88 */
1058         [4185] = { 0x00FF, 0x00FF, 0x0000 }, /* R4185  - Write Sequencer 89 */
1059         [4186] = { 0x070F, 0x070F, 0x0000 }, /* R4186  - Write Sequencer 90 */
1060         [4187] = { 0x010F, 0x010F, 0x0000 }, /* R4187  - Write Sequencer 91 */
1061         [4188] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4188  - Write Sequencer 92 */
1062         [4189] = { 0x00FF, 0x00FF, 0x0000 }, /* R4189  - Write Sequencer 93 */
1063         [4190] = { 0x070F, 0x070F, 0x0000 }, /* R4190  - Write Sequencer 94 */
1064         [4191] = { 0x010F, 0x010F, 0x0000 }, /* R4191  - Write Sequencer 95 */
1065         [4192] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4192  - Write Sequencer 96 */
1066         [4193] = { 0x00FF, 0x00FF, 0x0000 }, /* R4193  - Write Sequencer 97 */
1067         [4194] = { 0x070F, 0x070F, 0x0000 }, /* R4194  - Write Sequencer 98 */
1068         [4195] = { 0x010F, 0x010F, 0x0000 }, /* R4195  - Write Sequencer 99 */
1069         [4196] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4196  - Write Sequencer 100 */
1070         [4197] = { 0x00FF, 0x00FF, 0x0000 }, /* R4197  - Write Sequencer 101 */
1071         [4198] = { 0x070F, 0x070F, 0x0000 }, /* R4198  - Write Sequencer 102 */
1072         [4199] = { 0x010F, 0x010F, 0x0000 }, /* R4199  - Write Sequencer 103 */
1073         [4200] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4200  - Write Sequencer 104 */
1074         [4201] = { 0x00FF, 0x00FF, 0x0000 }, /* R4201  - Write Sequencer 105 */
1075         [4202] = { 0x070F, 0x070F, 0x0000 }, /* R4202  - Write Sequencer 106 */
1076         [4203] = { 0x010F, 0x010F, 0x0000 }, /* R4203  - Write Sequencer 107 */
1077         [4204] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4204  - Write Sequencer 108 */
1078         [4205] = { 0x00FF, 0x00FF, 0x0000 }, /* R4205  - Write Sequencer 109 */
1079         [4206] = { 0x070F, 0x070F, 0x0000 }, /* R4206  - Write Sequencer 110 */
1080         [4207] = { 0x010F, 0x010F, 0x0000 }, /* R4207  - Write Sequencer 111 */
1081         [4208] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4208  - Write Sequencer 112 */
1082         [4209] = { 0x00FF, 0x00FF, 0x0000 }, /* R4209  - Write Sequencer 113 */
1083         [4210] = { 0x070F, 0x070F, 0x0000 }, /* R4210  - Write Sequencer 114 */
1084         [4211] = { 0x010F, 0x010F, 0x0000 }, /* R4211  - Write Sequencer 115 */
1085         [4212] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4212  - Write Sequencer 116 */
1086         [4213] = { 0x00FF, 0x00FF, 0x0000 }, /* R4213  - Write Sequencer 117 */
1087         [4214] = { 0x070F, 0x070F, 0x0000 }, /* R4214  - Write Sequencer 118 */
1088         [4215] = { 0x010F, 0x010F, 0x0000 }, /* R4215  - Write Sequencer 119 */
1089         [4216] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4216  - Write Sequencer 120 */
1090         [4217] = { 0x00FF, 0x00FF, 0x0000 }, /* R4217  - Write Sequencer 121 */
1091         [4218] = { 0x070F, 0x070F, 0x0000 }, /* R4218  - Write Sequencer 122 */
1092         [4219] = { 0x010F, 0x010F, 0x0000 }, /* R4219  - Write Sequencer 123 */
1093         [4220] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4220  - Write Sequencer 124 */
1094         [4221] = { 0x00FF, 0x00FF, 0x0000 }, /* R4221  - Write Sequencer 125 */
1095         [4222] = { 0x070F, 0x070F, 0x0000 }, /* R4222  - Write Sequencer 126 */
1096         [4223] = { 0x010F, 0x010F, 0x0000 }, /* R4223  - Write Sequencer 127 */
1097         [4224] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4224  - Write Sequencer 128 */
1098         [4225] = { 0x00FF, 0x00FF, 0x0000 }, /* R4225  - Write Sequencer 129 */
1099         [4226] = { 0x070F, 0x070F, 0x0000 }, /* R4226  - Write Sequencer 130 */
1100         [4227] = { 0x010F, 0x010F, 0x0000 }, /* R4227  - Write Sequencer 131 */
1101         [4228] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4228  - Write Sequencer 132 */
1102         [4229] = { 0x00FF, 0x00FF, 0x0000 }, /* R4229  - Write Sequencer 133 */
1103         [4230] = { 0x070F, 0x070F, 0x0000 }, /* R4230  - Write Sequencer 134 */
1104         [4231] = { 0x010F, 0x010F, 0x0000 }, /* R4231  - Write Sequencer 135 */
1105         [4232] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4232  - Write Sequencer 136 */
1106         [4233] = { 0x00FF, 0x00FF, 0x0000 }, /* R4233  - Write Sequencer 137 */
1107         [4234] = { 0x070F, 0x070F, 0x0000 }, /* R4234  - Write Sequencer 138 */
1108         [4235] = { 0x010F, 0x010F, 0x0000 }, /* R4235  - Write Sequencer 139 */
1109         [4236] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4236  - Write Sequencer 140 */
1110         [4237] = { 0x00FF, 0x00FF, 0x0000 }, /* R4237  - Write Sequencer 141 */
1111         [4238] = { 0x070F, 0x070F, 0x0000 }, /* R4238  - Write Sequencer 142 */
1112         [4239] = { 0x010F, 0x010F, 0x0000 }, /* R4239  - Write Sequencer 143 */
1113         [4240] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4240  - Write Sequencer 144 */
1114         [4241] = { 0x00FF, 0x00FF, 0x0000 }, /* R4241  - Write Sequencer 145 */
1115         [4242] = { 0x070F, 0x070F, 0x0000 }, /* R4242  - Write Sequencer 146 */
1116         [4243] = { 0x010F, 0x010F, 0x0000 }, /* R4243  - Write Sequencer 147 */
1117         [4244] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4244  - Write Sequencer 148 */
1118         [4245] = { 0x00FF, 0x00FF, 0x0000 }, /* R4245  - Write Sequencer 149 */
1119         [4246] = { 0x070F, 0x070F, 0x0000 }, /* R4246  - Write Sequencer 150 */
1120         [4247] = { 0x010F, 0x010F, 0x0000 }, /* R4247  - Write Sequencer 151 */
1121         [4248] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4248  - Write Sequencer 152 */
1122         [4249] = { 0x00FF, 0x00FF, 0x0000 }, /* R4249  - Write Sequencer 153 */
1123         [4250] = { 0x070F, 0x070F, 0x0000 }, /* R4250  - Write Sequencer 154 */
1124         [4251] = { 0x010F, 0x010F, 0x0000 }, /* R4251  - Write Sequencer 155 */
1125         [4252] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4252  - Write Sequencer 156 */
1126         [4253] = { 0x00FF, 0x00FF, 0x0000 }, /* R4253  - Write Sequencer 157 */
1127         [4254] = { 0x070F, 0x070F, 0x0000 }, /* R4254  - Write Sequencer 158 */
1128         [4255] = { 0x010F, 0x010F, 0x0000 }, /* R4255  - Write Sequencer 159 */
1129         [4256] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4256  - Write Sequencer 160 */
1130         [4257] = { 0x00FF, 0x00FF, 0x0000 }, /* R4257  - Write Sequencer 161 */
1131         [4258] = { 0x070F, 0x070F, 0x0000 }, /* R4258  - Write Sequencer 162 */
1132         [4259] = { 0x010F, 0x010F, 0x0000 }, /* R4259  - Write Sequencer 163 */
1133         [4260] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4260  - Write Sequencer 164 */
1134         [4261] = { 0x00FF, 0x00FF, 0x0000 }, /* R4261  - Write Sequencer 165 */
1135         [4262] = { 0x070F, 0x070F, 0x0000 }, /* R4262  - Write Sequencer 166 */
1136         [4263] = { 0x010F, 0x010F, 0x0000 }, /* R4263  - Write Sequencer 167 */
1137         [4264] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4264  - Write Sequencer 168 */
1138         [4265] = { 0x00FF, 0x00FF, 0x0000 }, /* R4265  - Write Sequencer 169 */
1139         [4266] = { 0x070F, 0x070F, 0x0000 }, /* R4266  - Write Sequencer 170 */
1140         [4267] = { 0x010F, 0x010F, 0x0000 }, /* R4267  - Write Sequencer 171 */
1141         [4268] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4268  - Write Sequencer 172 */
1142         [4269] = { 0x00FF, 0x00FF, 0x0000 }, /* R4269  - Write Sequencer 173 */
1143         [4270] = { 0x070F, 0x070F, 0x0000 }, /* R4270  - Write Sequencer 174 */
1144         [4271] = { 0x010F, 0x010F, 0x0000 }, /* R4271  - Write Sequencer 175 */
1145         [4272] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4272  - Write Sequencer 176 */
1146         [4273] = { 0x00FF, 0x00FF, 0x0000 }, /* R4273  - Write Sequencer 177 */
1147         [4274] = { 0x070F, 0x070F, 0x0000 }, /* R4274  - Write Sequencer 178 */
1148         [4275] = { 0x010F, 0x010F, 0x0000 }, /* R4275  - Write Sequencer 179 */
1149         [4276] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4276  - Write Sequencer 180 */
1150         [4277] = { 0x00FF, 0x00FF, 0x0000 }, /* R4277  - Write Sequencer 181 */
1151         [4278] = { 0x070F, 0x070F, 0x0000 }, /* R4278  - Write Sequencer 182 */
1152         [4279] = { 0x010F, 0x010F, 0x0000 }, /* R4279  - Write Sequencer 183 */
1153         [4280] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4280  - Write Sequencer 184 */
1154         [4281] = { 0x00FF, 0x00FF, 0x0000 }, /* R4281  - Write Sequencer 185 */
1155         [4282] = { 0x070F, 0x070F, 0x0000 }, /* R4282  - Write Sequencer 186 */
1156         [4283] = { 0x010F, 0x010F, 0x0000 }, /* R4283  - Write Sequencer 187 */
1157         [4284] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4284  - Write Sequencer 188 */
1158         [4285] = { 0x00FF, 0x00FF, 0x0000 }, /* R4285  - Write Sequencer 189 */
1159         [4286] = { 0x070F, 0x070F, 0x0000 }, /* R4286  - Write Sequencer 190 */
1160         [4287] = { 0x010F, 0x010F, 0x0000 }, /* R4287  - Write Sequencer 191 */
1161         [4288] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4288  - Write Sequencer 192 */
1162         [4289] = { 0x00FF, 0x00FF, 0x0000 }, /* R4289  - Write Sequencer 193 */
1163         [4290] = { 0x070F, 0x070F, 0x0000 }, /* R4290  - Write Sequencer 194 */
1164         [4291] = { 0x010F, 0x010F, 0x0000 }, /* R4291  - Write Sequencer 195 */
1165         [4292] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4292  - Write Sequencer 196 */
1166         [4293] = { 0x00FF, 0x00FF, 0x0000 }, /* R4293  - Write Sequencer 197 */
1167         [4294] = { 0x070F, 0x070F, 0x0000 }, /* R4294  - Write Sequencer 198 */
1168         [4295] = { 0x010F, 0x010F, 0x0000 }, /* R4295  - Write Sequencer 199 */
1169         [4296] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4296  - Write Sequencer 200 */
1170         [4297] = { 0x00FF, 0x00FF, 0x0000 }, /* R4297  - Write Sequencer 201 */
1171         [4298] = { 0x070F, 0x070F, 0x0000 }, /* R4298  - Write Sequencer 202 */
1172         [4299] = { 0x010F, 0x010F, 0x0000 }, /* R4299  - Write Sequencer 203 */
1173         [4300] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4300  - Write Sequencer 204 */
1174         [4301] = { 0x00FF, 0x00FF, 0x0000 }, /* R4301  - Write Sequencer 205 */
1175         [4302] = { 0x070F, 0x070F, 0x0000 }, /* R4302  - Write Sequencer 206 */
1176         [4303] = { 0x010F, 0x010F, 0x0000 }, /* R4303  - Write Sequencer 207 */
1177         [4304] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4304  - Write Sequencer 208 */
1178         [4305] = { 0x00FF, 0x00FF, 0x0000 }, /* R4305  - Write Sequencer 209 */
1179         [4306] = { 0x070F, 0x070F, 0x0000 }, /* R4306  - Write Sequencer 210 */
1180         [4307] = { 0x010F, 0x010F, 0x0000 }, /* R4307  - Write Sequencer 211 */
1181         [4308] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4308  - Write Sequencer 212 */
1182         [4309] = { 0x00FF, 0x00FF, 0x0000 }, /* R4309  - Write Sequencer 213 */
1183         [4310] = { 0x070F, 0x070F, 0x0000 }, /* R4310  - Write Sequencer 214 */
1184         [4311] = { 0x010F, 0x010F, 0x0000 }, /* R4311  - Write Sequencer 215 */
1185         [4312] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4312  - Write Sequencer 216 */
1186         [4313] = { 0x00FF, 0x00FF, 0x0000 }, /* R4313  - Write Sequencer 217 */
1187         [4314] = { 0x070F, 0x070F, 0x0000 }, /* R4314  - Write Sequencer 218 */
1188         [4315] = { 0x010F, 0x010F, 0x0000 }, /* R4315  - Write Sequencer 219 */
1189         [4316] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4316  - Write Sequencer 220 */
1190         [4317] = { 0x00FF, 0x00FF, 0x0000 }, /* R4317  - Write Sequencer 221 */
1191         [4318] = { 0x070F, 0x070F, 0x0000 }, /* R4318  - Write Sequencer 222 */
1192         [4319] = { 0x010F, 0x010F, 0x0000 }, /* R4319  - Write Sequencer 223 */
1193         [4320] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4320  - Write Sequencer 224 */
1194         [4321] = { 0x00FF, 0x00FF, 0x0000 }, /* R4321  - Write Sequencer 225 */
1195         [4322] = { 0x070F, 0x070F, 0x0000 }, /* R4322  - Write Sequencer 226 */
1196         [4323] = { 0x010F, 0x010F, 0x0000 }, /* R4323  - Write Sequencer 227 */
1197         [4324] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4324  - Write Sequencer 228 */
1198         [4325] = { 0x00FF, 0x00FF, 0x0000 }, /* R4325  - Write Sequencer 229 */
1199         [4326] = { 0x070F, 0x070F, 0x0000 }, /* R4326  - Write Sequencer 230 */
1200         [4327] = { 0x010F, 0x010F, 0x0000 }, /* R4327  - Write Sequencer 231 */
1201         [4328] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4328  - Write Sequencer 232 */
1202         [4329] = { 0x00FF, 0x00FF, 0x0000 }, /* R4329  - Write Sequencer 233 */
1203         [4330] = { 0x070F, 0x070F, 0x0000 }, /* R4330  - Write Sequencer 234 */
1204         [4331] = { 0x010F, 0x010F, 0x0000 }, /* R4331  - Write Sequencer 235 */
1205         [4332] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4332  - Write Sequencer 236 */
1206         [4333] = { 0x00FF, 0x00FF, 0x0000 }, /* R4333  - Write Sequencer 237 */
1207         [4334] = { 0x070F, 0x070F, 0x0000 }, /* R4334  - Write Sequencer 238 */
1208         [4335] = { 0x010F, 0x010F, 0x0000 }, /* R4335  - Write Sequencer 239 */
1209         [4336] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4336  - Write Sequencer 240 */
1210         [4337] = { 0x00FF, 0x00FF, 0x0000 }, /* R4337  - Write Sequencer 241 */
1211         [4338] = { 0x070F, 0x070F, 0x0000 }, /* R4338  - Write Sequencer 242 */
1212         [4339] = { 0x010F, 0x010F, 0x0000 }, /* R4339  - Write Sequencer 243 */
1213         [4340] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4340  - Write Sequencer 244 */
1214         [4341] = { 0x00FF, 0x00FF, 0x0000 }, /* R4341  - Write Sequencer 245 */
1215         [4342] = { 0x070F, 0x070F, 0x0000 }, /* R4342  - Write Sequencer 246 */
1216         [4343] = { 0x010F, 0x010F, 0x0000 }, /* R4343  - Write Sequencer 247 */
1217         [4344] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4344  - Write Sequencer 248 */
1218         [4345] = { 0x00FF, 0x00FF, 0x0000 }, /* R4345  - Write Sequencer 249 */
1219         [4346] = { 0x070F, 0x070F, 0x0000 }, /* R4346  - Write Sequencer 250 */
1220         [4347] = { 0x010F, 0x010F, 0x0000 }, /* R4347  - Write Sequencer 251 */
1221         [4348] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4348  - Write Sequencer 252 */
1222         [4349] = { 0x00FF, 0x00FF, 0x0000 }, /* R4349  - Write Sequencer 253 */
1223         [4350] = { 0x070F, 0x070F, 0x0000 }, /* R4350  - Write Sequencer 254 */
1224         [4351] = { 0x010F, 0x010F, 0x0000 }, /* R4351  - Write Sequencer 255 */
1225         [4352] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4352  - Write Sequencer 256 */
1226         [4353] = { 0x00FF, 0x00FF, 0x0000 }, /* R4353  - Write Sequencer 257 */
1227         [4354] = { 0x070F, 0x070F, 0x0000 }, /* R4354  - Write Sequencer 258 */
1228         [4355] = { 0x010F, 0x010F, 0x0000 }, /* R4355  - Write Sequencer 259 */
1229         [4356] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4356  - Write Sequencer 260 */
1230         [4357] = { 0x00FF, 0x00FF, 0x0000 }, /* R4357  - Write Sequencer 261 */
1231         [4358] = { 0x070F, 0x070F, 0x0000 }, /* R4358  - Write Sequencer 262 */
1232         [4359] = { 0x010F, 0x010F, 0x0000 }, /* R4359  - Write Sequencer 263 */
1233         [4360] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4360  - Write Sequencer 264 */
1234         [4361] = { 0x00FF, 0x00FF, 0x0000 }, /* R4361  - Write Sequencer 265 */
1235         [4362] = { 0x070F, 0x070F, 0x0000 }, /* R4362  - Write Sequencer 266 */
1236         [4363] = { 0x010F, 0x010F, 0x0000 }, /* R4363  - Write Sequencer 267 */
1237         [4364] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4364  - Write Sequencer 268 */
1238         [4365] = { 0x00FF, 0x00FF, 0x0000 }, /* R4365  - Write Sequencer 269 */
1239         [4366] = { 0x070F, 0x070F, 0x0000 }, /* R4366  - Write Sequencer 270 */
1240         [4367] = { 0x010F, 0x010F, 0x0000 }, /* R4367  - Write Sequencer 271 */
1241         [4368] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4368  - Write Sequencer 272 */
1242         [4369] = { 0x00FF, 0x00FF, 0x0000 }, /* R4369  - Write Sequencer 273 */
1243         [4370] = { 0x070F, 0x070F, 0x0000 }, /* R4370  - Write Sequencer 274 */
1244         [4371] = { 0x010F, 0x010F, 0x0000 }, /* R4371  - Write Sequencer 275 */
1245         [4372] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4372  - Write Sequencer 276 */
1246         [4373] = { 0x00FF, 0x00FF, 0x0000 }, /* R4373  - Write Sequencer 277 */
1247         [4374] = { 0x070F, 0x070F, 0x0000 }, /* R4374  - Write Sequencer 278 */
1248         [4375] = { 0x010F, 0x010F, 0x0000 }, /* R4375  - Write Sequencer 279 */
1249         [4376] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4376  - Write Sequencer 280 */
1250         [4377] = { 0x00FF, 0x00FF, 0x0000 }, /* R4377  - Write Sequencer 281 */
1251         [4378] = { 0x070F, 0x070F, 0x0000 }, /* R4378  - Write Sequencer 282 */
1252         [4379] = { 0x010F, 0x010F, 0x0000 }, /* R4379  - Write Sequencer 283 */
1253         [4380] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4380  - Write Sequencer 284 */
1254         [4381] = { 0x00FF, 0x00FF, 0x0000 }, /* R4381  - Write Sequencer 285 */
1255         [4382] = { 0x070F, 0x070F, 0x0000 }, /* R4382  - Write Sequencer 286 */
1256         [4383] = { 0x010F, 0x010F, 0x0000 }, /* R4383  - Write Sequencer 287 */
1257         [4384] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4384  - Write Sequencer 288 */
1258         [4385] = { 0x00FF, 0x00FF, 0x0000 }, /* R4385  - Write Sequencer 289 */
1259         [4386] = { 0x070F, 0x070F, 0x0000 }, /* R4386  - Write Sequencer 290 */
1260         [4387] = { 0x010F, 0x010F, 0x0000 }, /* R4387  - Write Sequencer 291 */
1261         [4388] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4388  - Write Sequencer 292 */
1262         [4389] = { 0x00FF, 0x00FF, 0x0000 }, /* R4389  - Write Sequencer 293 */
1263         [4390] = { 0x070F, 0x070F, 0x0000 }, /* R4390  - Write Sequencer 294 */
1264         [4391] = { 0x010F, 0x010F, 0x0000 }, /* R4391  - Write Sequencer 295 */
1265         [4392] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4392  - Write Sequencer 296 */
1266         [4393] = { 0x00FF, 0x00FF, 0x0000 }, /* R4393  - Write Sequencer 297 */
1267         [4394] = { 0x070F, 0x070F, 0x0000 }, /* R4394  - Write Sequencer 298 */
1268         [4395] = { 0x010F, 0x010F, 0x0000 }, /* R4395  - Write Sequencer 299 */
1269         [4396] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4396  - Write Sequencer 300 */
1270         [4397] = { 0x00FF, 0x00FF, 0x0000 }, /* R4397  - Write Sequencer 301 */
1271         [4398] = { 0x070F, 0x070F, 0x0000 }, /* R4398  - Write Sequencer 302 */
1272         [4399] = { 0x010F, 0x010F, 0x0000 }, /* R4399  - Write Sequencer 303 */
1273         [4400] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4400  - Write Sequencer 304 */
1274         [4401] = { 0x00FF, 0x00FF, 0x0000 }, /* R4401  - Write Sequencer 305 */
1275         [4402] = { 0x070F, 0x070F, 0x0000 }, /* R4402  - Write Sequencer 306 */
1276         [4403] = { 0x010F, 0x010F, 0x0000 }, /* R4403  - Write Sequencer 307 */
1277         [4404] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4404  - Write Sequencer 308 */
1278         [4405] = { 0x00FF, 0x00FF, 0x0000 }, /* R4405  - Write Sequencer 309 */
1279         [4406] = { 0x070F, 0x070F, 0x0000 }, /* R4406  - Write Sequencer 310 */
1280         [4407] = { 0x010F, 0x010F, 0x0000 }, /* R4407  - Write Sequencer 311 */
1281         [4408] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4408  - Write Sequencer 312 */
1282         [4409] = { 0x00FF, 0x00FF, 0x0000 }, /* R4409  - Write Sequencer 313 */
1283         [4410] = { 0x070F, 0x070F, 0x0000 }, /* R4410  - Write Sequencer 314 */
1284         [4411] = { 0x010F, 0x010F, 0x0000 }, /* R4411  - Write Sequencer 315 */
1285         [4412] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4412  - Write Sequencer 316 */
1286         [4413] = { 0x00FF, 0x00FF, 0x0000 }, /* R4413  - Write Sequencer 317 */
1287         [4414] = { 0x070F, 0x070F, 0x0000 }, /* R4414  - Write Sequencer 318 */
1288         [4415] = { 0x010F, 0x010F, 0x0000 }, /* R4415  - Write Sequencer 319 */
1289         [4416] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4416  - Write Sequencer 320 */
1290         [4417] = { 0x00FF, 0x00FF, 0x0000 }, /* R4417  - Write Sequencer 321 */
1291         [4418] = { 0x070F, 0x070F, 0x0000 }, /* R4418  - Write Sequencer 322 */
1292         [4419] = { 0x010F, 0x010F, 0x0000 }, /* R4419  - Write Sequencer 323 */
1293         [4420] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4420  - Write Sequencer 324 */
1294         [4421] = { 0x00FF, 0x00FF, 0x0000 }, /* R4421  - Write Sequencer 325 */
1295         [4422] = { 0x070F, 0x070F, 0x0000 }, /* R4422  - Write Sequencer 326 */
1296         [4423] = { 0x010F, 0x010F, 0x0000 }, /* R4423  - Write Sequencer 327 */
1297         [4424] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4424  - Write Sequencer 328 */
1298         [4425] = { 0x00FF, 0x00FF, 0x0000 }, /* R4425  - Write Sequencer 329 */
1299         [4426] = { 0x070F, 0x070F, 0x0000 }, /* R4426  - Write Sequencer 330 */
1300         [4427] = { 0x010F, 0x010F, 0x0000 }, /* R4427  - Write Sequencer 331 */
1301         [4428] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4428  - Write Sequencer 332 */
1302         [4429] = { 0x00FF, 0x00FF, 0x0000 }, /* R4429  - Write Sequencer 333 */
1303         [4430] = { 0x070F, 0x070F, 0x0000 }, /* R4430  - Write Sequencer 334 */
1304         [4431] = { 0x010F, 0x010F, 0x0000 }, /* R4431  - Write Sequencer 335 */
1305         [4432] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4432  - Write Sequencer 336 */
1306         [4433] = { 0x00FF, 0x00FF, 0x0000 }, /* R4433  - Write Sequencer 337 */
1307         [4434] = { 0x070F, 0x070F, 0x0000 }, /* R4434  - Write Sequencer 338 */
1308         [4435] = { 0x010F, 0x010F, 0x0000 }, /* R4435  - Write Sequencer 339 */
1309         [4436] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4436  - Write Sequencer 340 */
1310         [4437] = { 0x00FF, 0x00FF, 0x0000 }, /* R4437  - Write Sequencer 341 */
1311         [4438] = { 0x070F, 0x070F, 0x0000 }, /* R4438  - Write Sequencer 342 */
1312         [4439] = { 0x010F, 0x010F, 0x0000 }, /* R4439  - Write Sequencer 343 */
1313         [4440] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4440  - Write Sequencer 344 */
1314         [4441] = { 0x00FF, 0x00FF, 0x0000 }, /* R4441  - Write Sequencer 345 */
1315         [4442] = { 0x070F, 0x070F, 0x0000 }, /* R4442  - Write Sequencer 346 */
1316         [4443] = { 0x010F, 0x010F, 0x0000 }, /* R4443  - Write Sequencer 347 */
1317         [4444] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4444  - Write Sequencer 348 */
1318         [4445] = { 0x00FF, 0x00FF, 0x0000 }, /* R4445  - Write Sequencer 349 */
1319         [4446] = { 0x070F, 0x070F, 0x0000 }, /* R4446  - Write Sequencer 350 */
1320         [4447] = { 0x010F, 0x010F, 0x0000 }, /* R4447  - Write Sequencer 351 */
1321         [4448] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4448  - Write Sequencer 352 */
1322         [4449] = { 0x00FF, 0x00FF, 0x0000 }, /* R4449  - Write Sequencer 353 */
1323         [4450] = { 0x070F, 0x070F, 0x0000 }, /* R4450  - Write Sequencer 354 */
1324         [4451] = { 0x010F, 0x010F, 0x0000 }, /* R4451  - Write Sequencer 355 */
1325         [4452] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4452  - Write Sequencer 356 */
1326         [4453] = { 0x00FF, 0x00FF, 0x0000 }, /* R4453  - Write Sequencer 357 */
1327         [4454] = { 0x070F, 0x070F, 0x0000 }, /* R4454  - Write Sequencer 358 */
1328         [4455] = { 0x010F, 0x010F, 0x0000 }, /* R4455  - Write Sequencer 359 */
1329         [4456] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4456  - Write Sequencer 360 */
1330         [4457] = { 0x00FF, 0x00FF, 0x0000 }, /* R4457  - Write Sequencer 361 */
1331         [4458] = { 0x070F, 0x070F, 0x0000 }, /* R4458  - Write Sequencer 362 */
1332         [4459] = { 0x010F, 0x010F, 0x0000 }, /* R4459  - Write Sequencer 363 */
1333         [4460] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4460  - Write Sequencer 364 */
1334         [4461] = { 0x00FF, 0x00FF, 0x0000 }, /* R4461  - Write Sequencer 365 */
1335         [4462] = { 0x070F, 0x070F, 0x0000 }, /* R4462  - Write Sequencer 366 */
1336         [4463] = { 0x010F, 0x010F, 0x0000 }, /* R4463  - Write Sequencer 367 */
1337         [4464] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4464  - Write Sequencer 368 */
1338         [4465] = { 0x00FF, 0x00FF, 0x0000 }, /* R4465  - Write Sequencer 369 */
1339         [4466] = { 0x070F, 0x070F, 0x0000 }, /* R4466  - Write Sequencer 370 */
1340         [4467] = { 0x010F, 0x010F, 0x0000 }, /* R4467  - Write Sequencer 371 */
1341         [4468] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4468  - Write Sequencer 372 */
1342         [4469] = { 0x00FF, 0x00FF, 0x0000 }, /* R4469  - Write Sequencer 373 */
1343         [4470] = { 0x070F, 0x070F, 0x0000 }, /* R4470  - Write Sequencer 374 */
1344         [4471] = { 0x010F, 0x010F, 0x0000 }, /* R4471  - Write Sequencer 375 */
1345         [4472] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4472  - Write Sequencer 376 */
1346         [4473] = { 0x00FF, 0x00FF, 0x0000 }, /* R4473  - Write Sequencer 377 */
1347         [4474] = { 0x070F, 0x070F, 0x0000 }, /* R4474  - Write Sequencer 378 */
1348         [4475] = { 0x010F, 0x010F, 0x0000 }, /* R4475  - Write Sequencer 379 */
1349         [4476] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4476  - Write Sequencer 380 */
1350         [4477] = { 0x00FF, 0x00FF, 0x0000 }, /* R4477  - Write Sequencer 381 */
1351         [4478] = { 0x070F, 0x070F, 0x0000 }, /* R4478  - Write Sequencer 382 */
1352         [4479] = { 0x010F, 0x010F, 0x0000 }, /* R4479  - Write Sequencer 383 */
1353         [4480] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4480  - Write Sequencer 384 */
1354         [4481] = { 0x00FF, 0x00FF, 0x0000 }, /* R4481  - Write Sequencer 385 */
1355         [4482] = { 0x070F, 0x070F, 0x0000 }, /* R4482  - Write Sequencer 386 */
1356         [4483] = { 0x010F, 0x010F, 0x0000 }, /* R4483  - Write Sequencer 387 */
1357         [4484] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4484  - Write Sequencer 388 */
1358         [4485] = { 0x00FF, 0x00FF, 0x0000 }, /* R4485  - Write Sequencer 389 */
1359         [4486] = { 0x070F, 0x070F, 0x0000 }, /* R4486  - Write Sequencer 390 */
1360         [4487] = { 0x010F, 0x010F, 0x0000 }, /* R4487  - Write Sequencer 391 */
1361         [4488] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4488  - Write Sequencer 392 */
1362         [4489] = { 0x00FF, 0x00FF, 0x0000 }, /* R4489  - Write Sequencer 393 */
1363         [4490] = { 0x070F, 0x070F, 0x0000 }, /* R4490  - Write Sequencer 394 */
1364         [4491] = { 0x010F, 0x010F, 0x0000 }, /* R4491  - Write Sequencer 395 */
1365         [4492] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4492  - Write Sequencer 396 */
1366         [4493] = { 0x00FF, 0x00FF, 0x0000 }, /* R4493  - Write Sequencer 397 */
1367         [4494] = { 0x070F, 0x070F, 0x0000 }, /* R4494  - Write Sequencer 398 */
1368         [4495] = { 0x010F, 0x010F, 0x0000 }, /* R4495  - Write Sequencer 399 */
1369         [4496] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4496  - Write Sequencer 400 */
1370         [4497] = { 0x00FF, 0x00FF, 0x0000 }, /* R4497  - Write Sequencer 401 */
1371         [4498] = { 0x070F, 0x070F, 0x0000 }, /* R4498  - Write Sequencer 402 */
1372         [4499] = { 0x010F, 0x010F, 0x0000 }, /* R4499  - Write Sequencer 403 */
1373         [4500] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4500  - Write Sequencer 404 */
1374         [4501] = { 0x00FF, 0x00FF, 0x0000 }, /* R4501  - Write Sequencer 405 */
1375         [4502] = { 0x070F, 0x070F, 0x0000 }, /* R4502  - Write Sequencer 406 */
1376         [4503] = { 0x010F, 0x010F, 0x0000 }, /* R4503  - Write Sequencer 407 */
1377         [4504] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4504  - Write Sequencer 408 */
1378         [4505] = { 0x00FF, 0x00FF, 0x0000 }, /* R4505  - Write Sequencer 409 */
1379         [4506] = { 0x070F, 0x070F, 0x0000 }, /* R4506  - Write Sequencer 410 */
1380         [4507] = { 0x010F, 0x010F, 0x0000 }, /* R4507  - Write Sequencer 411 */
1381         [4508] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4508  - Write Sequencer 412 */
1382         [4509] = { 0x00FF, 0x00FF, 0x0000 }, /* R4509  - Write Sequencer 413 */
1383         [4510] = { 0x070F, 0x070F, 0x0000 }, /* R4510  - Write Sequencer 414 */
1384         [4511] = { 0x010F, 0x010F, 0x0000 }, /* R4511  - Write Sequencer 415 */
1385         [4512] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4512  - Write Sequencer 416 */
1386         [4513] = { 0x00FF, 0x00FF, 0x0000 }, /* R4513  - Write Sequencer 417 */
1387         [4514] = { 0x070F, 0x070F, 0x0000 }, /* R4514  - Write Sequencer 418 */
1388         [4515] = { 0x010F, 0x010F, 0x0000 }, /* R4515  - Write Sequencer 419 */
1389         [4516] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4516  - Write Sequencer 420 */
1390         [4517] = { 0x00FF, 0x00FF, 0x0000 }, /* R4517  - Write Sequencer 421 */
1391         [4518] = { 0x070F, 0x070F, 0x0000 }, /* R4518  - Write Sequencer 422 */
1392         [4519] = { 0x010F, 0x010F, 0x0000 }, /* R4519  - Write Sequencer 423 */
1393         [4520] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4520  - Write Sequencer 424 */
1394         [4521] = { 0x00FF, 0x00FF, 0x0000 }, /* R4521  - Write Sequencer 425 */
1395         [4522] = { 0x070F, 0x070F, 0x0000 }, /* R4522  - Write Sequencer 426 */
1396         [4523] = { 0x010F, 0x010F, 0x0000 }, /* R4523  - Write Sequencer 427 */
1397         [4524] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4524  - Write Sequencer 428 */
1398         [4525] = { 0x00FF, 0x00FF, 0x0000 }, /* R4525  - Write Sequencer 429 */
1399         [4526] = { 0x070F, 0x070F, 0x0000 }, /* R4526  - Write Sequencer 430 */
1400         [4527] = { 0x010F, 0x010F, 0x0000 }, /* R4527  - Write Sequencer 431 */
1401         [4528] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4528  - Write Sequencer 432 */
1402         [4529] = { 0x00FF, 0x00FF, 0x0000 }, /* R4529  - Write Sequencer 433 */
1403         [4530] = { 0x070F, 0x070F, 0x0000 }, /* R4530  - Write Sequencer 434 */
1404         [4531] = { 0x010F, 0x010F, 0x0000 }, /* R4531  - Write Sequencer 435 */
1405         [4532] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4532  - Write Sequencer 436 */
1406         [4533] = { 0x00FF, 0x00FF, 0x0000 }, /* R4533  - Write Sequencer 437 */
1407         [4534] = { 0x070F, 0x070F, 0x0000 }, /* R4534  - Write Sequencer 438 */
1408         [4535] = { 0x010F, 0x010F, 0x0000 }, /* R4535  - Write Sequencer 439 */
1409         [4536] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4536  - Write Sequencer 440 */
1410         [4537] = { 0x00FF, 0x00FF, 0x0000 }, /* R4537  - Write Sequencer 441 */
1411         [4538] = { 0x070F, 0x070F, 0x0000 }, /* R4538  - Write Sequencer 442 */
1412         [4539] = { 0x010F, 0x010F, 0x0000 }, /* R4539  - Write Sequencer 443 */
1413         [4540] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4540  - Write Sequencer 444 */
1414         [4541] = { 0x00FF, 0x00FF, 0x0000 }, /* R4541  - Write Sequencer 445 */
1415         [4542] = { 0x070F, 0x070F, 0x0000 }, /* R4542  - Write Sequencer 446 */
1416         [4543] = { 0x010F, 0x010F, 0x0000 }, /* R4543  - Write Sequencer 447 */
1417         [4544] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4544  - Write Sequencer 448 */
1418         [4545] = { 0x00FF, 0x00FF, 0x0000 }, /* R4545  - Write Sequencer 449 */
1419         [4546] = { 0x070F, 0x070F, 0x0000 }, /* R4546  - Write Sequencer 450 */
1420         [4547] = { 0x010F, 0x010F, 0x0000 }, /* R4547  - Write Sequencer 451 */
1421         [4548] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4548  - Write Sequencer 452 */
1422         [4549] = { 0x00FF, 0x00FF, 0x0000 }, /* R4549  - Write Sequencer 453 */
1423         [4550] = { 0x070F, 0x070F, 0x0000 }, /* R4550  - Write Sequencer 454 */
1424         [4551] = { 0x010F, 0x010F, 0x0000 }, /* R4551  - Write Sequencer 455 */
1425         [4552] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4552  - Write Sequencer 456 */
1426         [4553] = { 0x00FF, 0x00FF, 0x0000 }, /* R4553  - Write Sequencer 457 */
1427         [4554] = { 0x070F, 0x070F, 0x0000 }, /* R4554  - Write Sequencer 458 */
1428         [4555] = { 0x010F, 0x010F, 0x0000 }, /* R4555  - Write Sequencer 459 */
1429         [4556] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4556  - Write Sequencer 460 */
1430         [4557] = { 0x00FF, 0x00FF, 0x0000 }, /* R4557  - Write Sequencer 461 */
1431         [4558] = { 0x070F, 0x070F, 0x0000 }, /* R4558  - Write Sequencer 462 */
1432         [4559] = { 0x010F, 0x010F, 0x0000 }, /* R4559  - Write Sequencer 463 */
1433         [4560] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4560  - Write Sequencer 464 */
1434         [4561] = { 0x00FF, 0x00FF, 0x0000 }, /* R4561  - Write Sequencer 465 */
1435         [4562] = { 0x070F, 0x070F, 0x0000 }, /* R4562  - Write Sequencer 466 */
1436         [4563] = { 0x010F, 0x010F, 0x0000 }, /* R4563  - Write Sequencer 467 */
1437         [4564] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4564  - Write Sequencer 468 */
1438         [4565] = { 0x00FF, 0x00FF, 0x0000 }, /* R4565  - Write Sequencer 469 */
1439         [4566] = { 0x070F, 0x070F, 0x0000 }, /* R4566  - Write Sequencer 470 */
1440         [4567] = { 0x010F, 0x010F, 0x0000 }, /* R4567  - Write Sequencer 471 */
1441         [4568] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4568  - Write Sequencer 472 */
1442         [4569] = { 0x00FF, 0x00FF, 0x0000 }, /* R4569  - Write Sequencer 473 */
1443         [4570] = { 0x070F, 0x070F, 0x0000 }, /* R4570  - Write Sequencer 474 */
1444         [4571] = { 0x010F, 0x010F, 0x0000 }, /* R4571  - Write Sequencer 475 */
1445         [4572] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4572  - Write Sequencer 476 */
1446         [4573] = { 0x00FF, 0x00FF, 0x0000 }, /* R4573  - Write Sequencer 477 */
1447         [4574] = { 0x070F, 0x070F, 0x0000 }, /* R4574  - Write Sequencer 478 */
1448         [4575] = { 0x010F, 0x010F, 0x0000 }, /* R4575  - Write Sequencer 479 */
1449         [4576] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4576  - Write Sequencer 480 */
1450         [4577] = { 0x00FF, 0x00FF, 0x0000 }, /* R4577  - Write Sequencer 481 */
1451         [4578] = { 0x070F, 0x070F, 0x0000 }, /* R4578  - Write Sequencer 482 */
1452         [4579] = { 0x010F, 0x010F, 0x0000 }, /* R4579  - Write Sequencer 483 */
1453         [4580] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4580  - Write Sequencer 484 */
1454         [4581] = { 0x00FF, 0x00FF, 0x0000 }, /* R4581  - Write Sequencer 485 */
1455         [4582] = { 0x070F, 0x070F, 0x0000 }, /* R4582  - Write Sequencer 486 */
1456         [4583] = { 0x010F, 0x010F, 0x0000 }, /* R4583  - Write Sequencer 487 */
1457         [4584] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4584  - Write Sequencer 488 */
1458         [4585] = { 0x00FF, 0x00FF, 0x0000 }, /* R4585  - Write Sequencer 489 */
1459         [4586] = { 0x070F, 0x070F, 0x0000 }, /* R4586  - Write Sequencer 490 */
1460         [4587] = { 0x010F, 0x010F, 0x0000 }, /* R4587  - Write Sequencer 491 */
1461         [4588] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4588  - Write Sequencer 492 */
1462         [4589] = { 0x00FF, 0x00FF, 0x0000 }, /* R4589  - Write Sequencer 493 */
1463         [4590] = { 0x070F, 0x070F, 0x0000 }, /* R4590  - Write Sequencer 494 */
1464         [4591] = { 0x010F, 0x010F, 0x0000 }, /* R4591  - Write Sequencer 495 */
1465         [4592] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4592  - Write Sequencer 496 */
1466         [4593] = { 0x00FF, 0x00FF, 0x0000 }, /* R4593  - Write Sequencer 497 */
1467         [4594] = { 0x070F, 0x070F, 0x0000 }, /* R4594  - Write Sequencer 498 */
1468         [4595] = { 0x010F, 0x010F, 0x0000 }, /* R4595  - Write Sequencer 499 */
1469         [4596] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4596  - Write Sequencer 500 */
1470         [4597] = { 0x00FF, 0x00FF, 0x0000 }, /* R4597  - Write Sequencer 501 */
1471         [4598] = { 0x070F, 0x070F, 0x0000 }, /* R4598  - Write Sequencer 502 */
1472         [4599] = { 0x010F, 0x010F, 0x0000 }, /* R4599  - Write Sequencer 503 */
1473         [4600] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4600  - Write Sequencer 504 */
1474         [4601] = { 0x00FF, 0x00FF, 0x0000 }, /* R4601  - Write Sequencer 505 */
1475         [4602] = { 0x070F, 0x070F, 0x0000 }, /* R4602  - Write Sequencer 506 */
1476         [4603] = { 0x010F, 0x010F, 0x0000 }, /* R4603  - Write Sequencer 507 */
1477         [4604] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4604  - Write Sequencer 508 */
1478         [4605] = { 0x00FF, 0x00FF, 0x0000 }, /* R4605  - Write Sequencer 509 */
1479         [4606] = { 0x070F, 0x070F, 0x0000 }, /* R4606  - Write Sequencer 510 */
1480         [4607] = { 0x010F, 0x010F, 0x0000 }, /* R4607  - Write Sequencer 511 */
1481         [8192] = { 0x03FF, 0x03FF, 0x0000 }, /* R8192  - DSP2 Instruction RAM 0 */
1482         [9216] = { 0x003F, 0x003F, 0x0000 }, /* R9216  - DSP2 Address RAM 2 */
1483         [9217] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9217  - DSP2 Address RAM 1 */
1484         [9218] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9218  - DSP2 Address RAM 0 */
1485         [12288] = { 0x00FF, 0x00FF, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
1486         [12289] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
1487         [13312] = { 0x00FF, 0x00FF, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
1488         [13313] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
1489         [14336] = { 0x00FF, 0x00FF, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
1490         [14337] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
1491         [15360] = { 0x07FF, 0x07FF, 0x0000 }, /* R15360 - DSP2 Coeff RAM 0 */
1492         [16384] = { 0x00FF, 0x00FF, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
1493         [16385] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
1494         [16386] = { 0x00FF, 0x00FF, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
1495         [16387] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
1496         [16388] = { 0x00FF, 0x00FF, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
1497         [16389] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
1498         [16896] = { 0x00FF, 0x00FF, 0x0000 }, /* R16896 - HDBASS_AI_1 */
1499         [16897] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16897 - HDBASS_AI_0 */
1500         [16898] = { 0x00FF, 0x00FF, 0x0000 }, /* R16898 - HDBASS_AR_1 */
1501         [16899] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16899 - HDBASS_AR_0 */
1502         [16900] = { 0x00FF, 0x00FF, 0x0000 }, /* R16900 - HDBASS_B_1 */
1503         [16901] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16901 - HDBASS_B_0 */
1504         [16902] = { 0x00FF, 0x00FF, 0x0000 }, /* R16902 - HDBASS_K_1 */
1505         [16903] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16903 - HDBASS_K_0 */
1506         [16904] = { 0x00FF, 0x00FF, 0x0000 }, /* R16904 - HDBASS_N1_1 */
1507         [16905] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16905 - HDBASS_N1_0 */
1508         [16906] = { 0x00FF, 0x00FF, 0x0000 }, /* R16906 - HDBASS_N2_1 */
1509         [16907] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16907 - HDBASS_N2_0 */
1510         [16908] = { 0x00FF, 0x00FF, 0x0000 }, /* R16908 - HDBASS_N3_1 */
1511         [16909] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16909 - HDBASS_N3_0 */
1512         [16910] = { 0x00FF, 0x00FF, 0x0000 }, /* R16910 - HDBASS_N4_1 */
1513         [16911] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16911 - HDBASS_N4_0 */
1514         [16912] = { 0x00FF, 0x00FF, 0x0000 }, /* R16912 - HDBASS_N5_1 */
1515         [16913] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16913 - HDBASS_N5_0 */
1516         [16914] = { 0x00FF, 0x00FF, 0x0000 }, /* R16914 - HDBASS_X1_1 */
1517         [16915] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16915 - HDBASS_X1_0 */
1518         [16916] = { 0x00FF, 0x00FF, 0x0000 }, /* R16916 - HDBASS_X2_1 */
1519         [16917] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16917 - HDBASS_X2_0 */
1520         [16918] = { 0x00FF, 0x00FF, 0x0000 }, /* R16918 - HDBASS_X3_1 */
1521         [16919] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16919 - HDBASS_X3_0 */
1522         [16920] = { 0x00FF, 0x00FF, 0x0000 }, /* R16920 - HDBASS_ATK_1 */
1523         [16921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
1524         [16922] = { 0x00FF, 0x00FF, 0x0000 }, /* R16922 - HDBASS_DCY_1 */
1525         [16923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
1526         [16924] = { 0x00FF, 0x00FF, 0x0000 }, /* R16924 - HDBASS_PG_1 */
1527         [16925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16925 - HDBASS_PG_0 */
1528         [17408] = { 0x00FF, 0x00FF, 0x0000 }, /* R17408 - HPF_C_1 */
1529         [17409] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17409 - HPF_C_0 */
1530         [17920] = { 0x00FF, 0x00FF, 0x0000 }, /* R17920 - ADCL_RETUNE_C1_1 */
1531         [17921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17921 - ADCL_RETUNE_C1_0 */
1532         [17922] = { 0x00FF, 0x00FF, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
1533         [17923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
1534         [17924] = { 0x00FF, 0x00FF, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
1535         [17925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
1536         [17926] = { 0x00FF, 0x00FF, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
1537         [17927] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
1538         [17928] = { 0x00FF, 0x00FF, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
1539         [17929] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
1540         [17930] = { 0x00FF, 0x00FF, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
1541         [17931] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
1542         [17932] = { 0x00FF, 0x00FF, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
1543         [17933] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
1544         [17934] = { 0x00FF, 0x00FF, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
1545         [17935] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
1546         [17936] = { 0x00FF, 0x00FF, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
1547         [17937] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
1548         [17938] = { 0x00FF, 0x00FF, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
1549         [17939] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
1550         [17940] = { 0x00FF, 0x00FF, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
1551         [17941] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
1552         [17942] = { 0x00FF, 0x00FF, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
1553         [17943] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
1554         [17944] = { 0x00FF, 0x00FF, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
1555         [17945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
1556         [17946] = { 0x00FF, 0x00FF, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
1557         [17947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
1558         [17948] = { 0x00FF, 0x00FF, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
1559         [17949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
1560         [17950] = { 0x00FF, 0x00FF, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
1561         [17951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
1562         [17952] = { 0x00FF, 0x00FF, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
1563         [17953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
1564         [17954] = { 0x00FF, 0x00FF, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
1565         [17955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
1566         [17956] = { 0x00FF, 0x00FF, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
1567         [17957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
1568         [17958] = { 0x00FF, 0x00FF, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
1569         [17959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
1570         [17960] = { 0x00FF, 0x00FF, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
1571         [17961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
1572         [17962] = { 0x00FF, 0x00FF, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
1573         [17963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
1574         [17964] = { 0x00FF, 0x00FF, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
1575         [17965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
1576         [17966] = { 0x00FF, 0x00FF, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
1577         [17967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
1578         [17968] = { 0x00FF, 0x00FF, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
1579         [17969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
1580         [17970] = { 0x00FF, 0x00FF, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
1581         [17971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
1582         [17972] = { 0x00FF, 0x00FF, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
1583         [17973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
1584         [17974] = { 0x00FF, 0x00FF, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
1585         [17975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
1586         [17976] = { 0x00FF, 0x00FF, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
1587         [17977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
1588         [17978] = { 0x00FF, 0x00FF, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
1589         [17979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
1590         [17980] = { 0x00FF, 0x00FF, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
1591         [17981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
1592         [17982] = { 0x00FF, 0x00FF, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
1593         [17983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
1594         [18432] = { 0x00FF, 0x00FF, 0x0000 }, /* R18432 - RETUNEADC_PG2_1 */
1595         [18433] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
1596         [18434] = { 0x00FF, 0x00FF, 0x0000 }, /* R18434 - RETUNEADC_PG_1 */
1597         [18435] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
1598         [18944] = { 0x00FF, 0x00FF, 0x0000 }, /* R18944 - ADCR_RETUNE_C1_1 */
1599         [18945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18945 - ADCR_RETUNE_C1_0 */
1600         [18946] = { 0x00FF, 0x00FF, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
1601         [18947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
1602         [18948] = { 0x00FF, 0x00FF, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
1603         [18949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
1604         [18950] = { 0x00FF, 0x00FF, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
1605         [18951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
1606         [18952] = { 0x00FF, 0x00FF, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
1607         [18953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
1608         [18954] = { 0x00FF, 0x00FF, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
1609         [18955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
1610         [18956] = { 0x00FF, 0x00FF, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
1611         [18957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
1612         [18958] = { 0x00FF, 0x00FF, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
1613         [18959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
1614         [18960] = { 0x00FF, 0x00FF, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
1615         [18961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
1616         [18962] = { 0x00FF, 0x00FF, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
1617         [18963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
1618         [18964] = { 0x00FF, 0x00FF, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
1619         [18965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
1620         [18966] = { 0x00FF, 0x00FF, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
1621         [18967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
1622         [18968] = { 0x00FF, 0x00FF, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
1623         [18969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
1624         [18970] = { 0x00FF, 0x00FF, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
1625         [18971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
1626         [18972] = { 0x00FF, 0x00FF, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
1627         [18973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
1628         [18974] = { 0x00FF, 0x00FF, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
1629         [18975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
1630         [18976] = { 0x00FF, 0x00FF, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
1631         [18977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
1632         [18978] = { 0x00FF, 0x00FF, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
1633         [18979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
1634         [18980] = { 0x00FF, 0x00FF, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
1635         [18981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
1636         [18982] = { 0x00FF, 0x00FF, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
1637         [18983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
1638         [18984] = { 0x00FF, 0x00FF, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
1639         [18985] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
1640         [18986] = { 0x00FF, 0x00FF, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
1641         [18987] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
1642         [18988] = { 0x00FF, 0x00FF, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
1643         [18989] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
1644         [18990] = { 0x00FF, 0x00FF, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
1645         [18991] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
1646         [18992] = { 0x00FF, 0x00FF, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
1647         [18993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
1648         [18994] = { 0x00FF, 0x00FF, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
1649         [18995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
1650         [18996] = { 0x00FF, 0x00FF, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
1651         [18997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
1652         [18998] = { 0x00FF, 0x00FF, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
1653         [18999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
1654         [19000] = { 0x00FF, 0x00FF, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
1655         [19001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
1656         [19002] = { 0x00FF, 0x00FF, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
1657         [19003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
1658         [19004] = { 0x00FF, 0x00FF, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
1659         [19005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
1660         [19006] = { 0x00FF, 0x00FF, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
1661         [19007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
1662         [19456] = { 0x00FF, 0x00FF, 0x0000 }, /* R19456 - DACL_RETUNE_C1_1 */
1663         [19457] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19457 - DACL_RETUNE_C1_0 */
1664         [19458] = { 0x00FF, 0x00FF, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
1665         [19459] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
1666         [19460] = { 0x00FF, 0x00FF, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
1667         [19461] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
1668         [19462] = { 0x00FF, 0x00FF, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
1669         [19463] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
1670         [19464] = { 0x00FF, 0x00FF, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
1671         [19465] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
1672         [19466] = { 0x00FF, 0x00FF, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
1673         [19467] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
1674         [19468] = { 0x00FF, 0x00FF, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
1675         [19469] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
1676         [19470] = { 0x00FF, 0x00FF, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
1677         [19471] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
1678         [19472] = { 0x00FF, 0x00FF, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
1679         [19473] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
1680         [19474] = { 0x00FF, 0x00FF, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
1681         [19475] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
1682         [19476] = { 0x00FF, 0x00FF, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
1683         [19477] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
1684         [19478] = { 0x00FF, 0x00FF, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
1685         [19479] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
1686         [19480] = { 0x00FF, 0x00FF, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
1687         [19481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
1688         [19482] = { 0x00FF, 0x00FF, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
1689         [19483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
1690         [19484] = { 0x00FF, 0x00FF, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
1691         [19485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
1692         [19486] = { 0x00FF, 0x00FF, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
1693         [19487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
1694         [19488] = { 0x00FF, 0x00FF, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
1695         [19489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
1696         [19490] = { 0x00FF, 0x00FF, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
1697         [19491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
1698         [19492] = { 0x00FF, 0x00FF, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
1699         [19493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
1700         [19494] = { 0x00FF, 0x00FF, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
1701         [19495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
1702         [19496] = { 0x00FF, 0x00FF, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
1703         [19497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
1704         [19498] = { 0x00FF, 0x00FF, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
1705         [19499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
1706         [19500] = { 0x00FF, 0x00FF, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
1707         [19501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
1708         [19502] = { 0x00FF, 0x00FF, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
1709         [19503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
1710         [19504] = { 0x00FF, 0x00FF, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
1711         [19505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
1712         [19506] = { 0x00FF, 0x00FF, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
1713         [19507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
1714         [19508] = { 0x00FF, 0x00FF, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
1715         [19509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
1716         [19510] = { 0x00FF, 0x00FF, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
1717         [19511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
1718         [19512] = { 0x00FF, 0x00FF, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
1719         [19513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
1720         [19514] = { 0x00FF, 0x00FF, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
1721         [19515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
1722         [19516] = { 0x00FF, 0x00FF, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
1723         [19517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
1724         [19518] = { 0x00FF, 0x00FF, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
1725         [19519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
1726         [19968] = { 0x00FF, 0x00FF, 0x0000 }, /* R19968 - RETUNEDAC_PG2_1 */
1727         [19969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
1728         [19970] = { 0x00FF, 0x00FF, 0x0000 }, /* R19970 - RETUNEDAC_PG_1 */
1729         [19971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
1730         [20480] = { 0x00FF, 0x00FF, 0x0000 }, /* R20480 - DACR_RETUNE_C1_1 */
1731         [20481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20481 - DACR_RETUNE_C1_0 */
1732         [20482] = { 0x00FF, 0x00FF, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
1733         [20483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
1734         [20484] = { 0x00FF, 0x00FF, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
1735         [20485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
1736         [20486] = { 0x00FF, 0x00FF, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
1737         [20487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
1738         [20488] = { 0x00FF, 0x00FF, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
1739         [20489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
1740         [20490] = { 0x00FF, 0x00FF, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
1741         [20491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
1742         [20492] = { 0x00FF, 0x00FF, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
1743         [20493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
1744         [20494] = { 0x00FF, 0x00FF, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
1745         [20495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
1746         [20496] = { 0x00FF, 0x00FF, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
1747         [20497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
1748         [20498] = { 0x00FF, 0x00FF, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
1749         [20499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
1750         [20500] = { 0x00FF, 0x00FF, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
1751         [20501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
1752         [20502] = { 0x00FF, 0x00FF, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
1753         [20503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
1754         [20504] = { 0x00FF, 0x00FF, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
1755         [20505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
1756         [20506] = { 0x00FF, 0x00FF, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
1757         [20507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
1758         [20508] = { 0x00FF, 0x00FF, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
1759         [20509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
1760         [20510] = { 0x00FF, 0x00FF, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
1761         [20511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
1762         [20512] = { 0x00FF, 0x00FF, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
1763         [20513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
1764         [20514] = { 0x00FF, 0x00FF, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
1765         [20515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
1766         [20516] = { 0x00FF, 0x00FF, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
1767         [20517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
1768         [20518] = { 0x00FF, 0x00FF, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
1769         [20519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
1770         [20520] = { 0x00FF, 0x00FF, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
1771         [20521] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
1772         [20522] = { 0x00FF, 0x00FF, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
1773         [20523] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
1774         [20524] = { 0x00FF, 0x00FF, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
1775         [20525] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
1776         [20526] = { 0x00FF, 0x00FF, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
1777         [20527] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
1778         [20528] = { 0x00FF, 0x00FF, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
1779         [20529] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
1780         [20530] = { 0x00FF, 0x00FF, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
1781         [20531] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
1782         [20532] = { 0x00FF, 0x00FF, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
1783         [20533] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
1784         [20534] = { 0x00FF, 0x00FF, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
1785         [20535] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
1786         [20536] = { 0x00FF, 0x00FF, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
1787         [20537] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
1788         [20538] = { 0x00FF, 0x00FF, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
1789         [20539] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
1790         [20540] = { 0x00FF, 0x00FF, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
1791         [20541] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
1792         [20542] = { 0x00FF, 0x00FF, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
1793         [20543] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
1794         [20992] = { 0x00FF, 0x00FF, 0x0000 }, /* R20992 - VSS_XHD2_1 */
1795         [20993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20993 - VSS_XHD2_0 */
1796         [20994] = { 0x00FF, 0x00FF, 0x0000 }, /* R20994 - VSS_XHD3_1 */
1797         [20995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20995 - VSS_XHD3_0 */
1798         [20996] = { 0x00FF, 0x00FF, 0x0000 }, /* R20996 - VSS_XHN1_1 */
1799         [20997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20997 - VSS_XHN1_0 */
1800         [20998] = { 0x00FF, 0x00FF, 0x0000 }, /* R20998 - VSS_XHN2_1 */
1801         [20999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20999 - VSS_XHN2_0 */
1802         [21000] = { 0x00FF, 0x00FF, 0x0000 }, /* R21000 - VSS_XHN3_1 */
1803         [21001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21001 - VSS_XHN3_0 */
1804         [21002] = { 0x00FF, 0x00FF, 0x0000 }, /* R21002 - VSS_XLA_1 */
1805         [21003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21003 - VSS_XLA_0 */
1806         [21004] = { 0x00FF, 0x00FF, 0x0000 }, /* R21004 - VSS_XLB_1 */
1807         [21005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21005 - VSS_XLB_0 */
1808         [21006] = { 0x00FF, 0x00FF, 0x0000 }, /* R21006 - VSS_XLG_1 */
1809         [21007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21007 - VSS_XLG_0 */
1810         [21008] = { 0x00FF, 0x00FF, 0x0000 }, /* R21008 - VSS_PG2_1 */
1811         [21009] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21009 - VSS_PG2_0 */
1812         [21010] = { 0x00FF, 0x00FF, 0x0000 }, /* R21010 - VSS_PG_1 */
1813         [21011] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21011 - VSS_PG_0 */
1814         [21012] = { 0x00FF, 0x00FF, 0x0000 }, /* R21012 - VSS_XTD1_1 */
1815         [21013] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21013 - VSS_XTD1_0 */
1816         [21014] = { 0x00FF, 0x00FF, 0x0000 }, /* R21014 - VSS_XTD2_1 */
1817         [21015] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21015 - VSS_XTD2_0 */
1818         [21016] = { 0x00FF, 0x00FF, 0x0000 }, /* R21016 - VSS_XTD3_1 */
1819         [21017] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21017 - VSS_XTD3_0 */
1820         [21018] = { 0x00FF, 0x00FF, 0x0000 }, /* R21018 - VSS_XTD4_1 */
1821         [21019] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21019 - VSS_XTD4_0 */
1822         [21020] = { 0x00FF, 0x00FF, 0x0000 }, /* R21020 - VSS_XTD5_1 */
1823         [21021] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21021 - VSS_XTD5_0 */
1824         [21022] = { 0x00FF, 0x00FF, 0x0000 }, /* R21022 - VSS_XTD6_1 */
1825         [21023] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21023 - VSS_XTD6_0 */
1826         [21024] = { 0x00FF, 0x00FF, 0x0000 }, /* R21024 - VSS_XTD7_1 */
1827         [21025] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21025 - VSS_XTD7_0 */
1828         [21026] = { 0x00FF, 0x00FF, 0x0000 }, /* R21026 - VSS_XTD8_1 */
1829         [21027] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21027 - VSS_XTD8_0 */
1830         [21028] = { 0x00FF, 0x00FF, 0x0000 }, /* R21028 - VSS_XTD9_1 */
1831         [21029] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21029 - VSS_XTD9_0 */
1832         [21030] = { 0x00FF, 0x00FF, 0x0000 }, /* R21030 - VSS_XTD10_1 */
1833         [21031] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21031 - VSS_XTD10_0 */
1834         [21032] = { 0x00FF, 0x00FF, 0x0000 }, /* R21032 - VSS_XTD11_1 */
1835         [21033] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21033 - VSS_XTD11_0 */
1836         [21034] = { 0x00FF, 0x00FF, 0x0000 }, /* R21034 - VSS_XTD12_1 */
1837         [21035] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21035 - VSS_XTD12_0 */
1838         [21036] = { 0x00FF, 0x00FF, 0x0000 }, /* R21036 - VSS_XTD13_1 */
1839         [21037] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21037 - VSS_XTD13_0 */
1840         [21038] = { 0x00FF, 0x00FF, 0x0000 }, /* R21038 - VSS_XTD14_1 */
1841         [21039] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21039 - VSS_XTD14_0 */
1842         [21040] = { 0x00FF, 0x00FF, 0x0000 }, /* R21040 - VSS_XTD15_1 */
1843         [21041] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21041 - VSS_XTD15_0 */
1844         [21042] = { 0x00FF, 0x00FF, 0x0000 }, /* R21042 - VSS_XTD16_1 */
1845         [21043] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21043 - VSS_XTD16_0 */
1846         [21044] = { 0x00FF, 0x00FF, 0x0000 }, /* R21044 - VSS_XTD17_1 */
1847         [21045] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21045 - VSS_XTD17_0 */
1848         [21046] = { 0x00FF, 0x00FF, 0x0000 }, /* R21046 - VSS_XTD18_1 */
1849         [21047] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21047 - VSS_XTD18_0 */
1850         [21048] = { 0x00FF, 0x00FF, 0x0000 }, /* R21048 - VSS_XTD19_1 */
1851         [21049] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21049 - VSS_XTD19_0 */
1852         [21050] = { 0x00FF, 0x00FF, 0x0000 }, /* R21050 - VSS_XTD20_1 */
1853         [21051] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21051 - VSS_XTD20_0 */
1854         [21052] = { 0x00FF, 0x00FF, 0x0000 }, /* R21052 - VSS_XTD21_1 */
1855         [21053] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21053 - VSS_XTD21_0 */
1856         [21054] = { 0x00FF, 0x00FF, 0x0000 }, /* R21054 - VSS_XTD22_1 */
1857         [21055] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21055 - VSS_XTD22_0 */
1858         [21056] = { 0x00FF, 0x00FF, 0x0000 }, /* R21056 - VSS_XTD23_1 */
1859         [21057] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21057 - VSS_XTD23_0 */
1860         [21058] = { 0x00FF, 0x00FF, 0x0000 }, /* R21058 - VSS_XTD24_1 */
1861         [21059] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21059 - VSS_XTD24_0 */
1862         [21060] = { 0x00FF, 0x00FF, 0x0000 }, /* R21060 - VSS_XTD25_1 */
1863         [21061] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21061 - VSS_XTD25_0 */
1864         [21062] = { 0x00FF, 0x00FF, 0x0000 }, /* R21062 - VSS_XTD26_1 */
1865         [21063] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21063 - VSS_XTD26_0 */
1866         [21064] = { 0x00FF, 0x00FF, 0x0000 }, /* R21064 - VSS_XTD27_1 */
1867         [21065] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21065 - VSS_XTD27_0 */
1868         [21066] = { 0x00FF, 0x00FF, 0x0000 }, /* R21066 - VSS_XTD28_1 */
1869         [21067] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21067 - VSS_XTD28_0 */
1870         [21068] = { 0x00FF, 0x00FF, 0x0000 }, /* R21068 - VSS_XTD29_1 */
1871         [21069] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21069 - VSS_XTD29_0 */
1872         [21070] = { 0x00FF, 0x00FF, 0x0000 }, /* R21070 - VSS_XTD30_1 */
1873         [21071] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21071 - VSS_XTD30_0 */
1874         [21072] = { 0x00FF, 0x00FF, 0x0000 }, /* R21072 - VSS_XTD31_1 */
1875         [21073] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21073 - VSS_XTD31_0 */
1876         [21074] = { 0x00FF, 0x00FF, 0x0000 }, /* R21074 - VSS_XTD32_1 */
1877         [21075] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21075 - VSS_XTD32_0 */
1878         [21076] = { 0x00FF, 0x00FF, 0x0000 }, /* R21076 - VSS_XTS1_1 */
1879         [21077] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21077 - VSS_XTS1_0 */
1880         [21078] = { 0x00FF, 0x00FF, 0x0000 }, /* R21078 - VSS_XTS2_1 */
1881         [21079] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21079 - VSS_XTS2_0 */
1882         [21080] = { 0x00FF, 0x00FF, 0x0000 }, /* R21080 - VSS_XTS3_1 */
1883         [21081] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21081 - VSS_XTS3_0 */
1884         [21082] = { 0x00FF, 0x00FF, 0x0000 }, /* R21082 - VSS_XTS4_1 */
1885         [21083] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21083 - VSS_XTS4_0 */
1886         [21084] = { 0x00FF, 0x00FF, 0x0000 }, /* R21084 - VSS_XTS5_1 */
1887         [21085] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21085 - VSS_XTS5_0 */
1888         [21086] = { 0x00FF, 0x00FF, 0x0000 }, /* R21086 - VSS_XTS6_1 */
1889         [21087] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21087 - VSS_XTS6_0 */
1890         [21088] = { 0x00FF, 0x00FF, 0x0000 }, /* R21088 - VSS_XTS7_1 */
1891         [21089] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21089 - VSS_XTS7_0 */
1892         [21090] = { 0x00FF, 0x00FF, 0x0000 }, /* R21090 - VSS_XTS8_1 */
1893         [21091] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21091 - VSS_XTS8_0 */
1894         [21092] = { 0x00FF, 0x00FF, 0x0000 }, /* R21092 - VSS_XTS9_1 */
1895         [21093] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21093 - VSS_XTS9_0 */
1896         [21094] = { 0x00FF, 0x00FF, 0x0000 }, /* R21094 - VSS_XTS10_1 */
1897         [21095] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21095 - VSS_XTS10_0 */
1898         [21096] = { 0x00FF, 0x00FF, 0x0000 }, /* R21096 - VSS_XTS11_1 */
1899         [21097] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21097 - VSS_XTS11_0 */
1900         [21098] = { 0x00FF, 0x00FF, 0x0000 }, /* R21098 - VSS_XTS12_1 */
1901         [21099] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21099 - VSS_XTS12_0 */
1902         [21100] = { 0x00FF, 0x00FF, 0x0000 }, /* R21100 - VSS_XTS13_1 */
1903         [21101] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21101 - VSS_XTS13_0 */
1904         [21102] = { 0x00FF, 0x00FF, 0x0000 }, /* R21102 - VSS_XTS14_1 */
1905         [21103] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21103 - VSS_XTS14_0 */
1906         [21104] = { 0x00FF, 0x00FF, 0x0000 }, /* R21104 - VSS_XTS15_1 */
1907         [21105] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21105 - VSS_XTS15_0 */
1908         [21106] = { 0x00FF, 0x00FF, 0x0000 }, /* R21106 - VSS_XTS16_1 */
1909         [21107] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21107 - VSS_XTS16_0 */
1910         [21108] = { 0x00FF, 0x00FF, 0x0000 }, /* R21108 - VSS_XTS17_1 */
1911         [21109] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21109 - VSS_XTS17_0 */
1912         [21110] = { 0x00FF, 0x00FF, 0x0000 }, /* R21110 - VSS_XTS18_1 */
1913         [21111] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21111 - VSS_XTS18_0 */
1914         [21112] = { 0x00FF, 0x00FF, 0x0000 }, /* R21112 - VSS_XTS19_1 */
1915         [21113] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21113 - VSS_XTS19_0 */
1916         [21114] = { 0x00FF, 0x00FF, 0x0000 }, /* R21114 - VSS_XTS20_1 */
1917         [21115] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21115 - VSS_XTS20_0 */
1918         [21116] = { 0x00FF, 0x00FF, 0x0000 }, /* R21116 - VSS_XTS21_1 */
1919         [21117] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21117 - VSS_XTS21_0 */
1920         [21118] = { 0x00FF, 0x00FF, 0x0000 }, /* R21118 - VSS_XTS22_1 */
1921         [21119] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21119 - VSS_XTS22_0 */
1922         [21120] = { 0x00FF, 0x00FF, 0x0000 }, /* R21120 - VSS_XTS23_1 */
1923         [21121] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21121 - VSS_XTS23_0 */
1924         [21122] = { 0x00FF, 0x00FF, 0x0000 }, /* R21122 - VSS_XTS24_1 */
1925         [21123] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21123 - VSS_XTS24_0 */
1926         [21124] = { 0x00FF, 0x00FF, 0x0000 }, /* R21124 - VSS_XTS25_1 */
1927         [21125] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21125 - VSS_XTS25_0 */
1928         [21126] = { 0x00FF, 0x00FF, 0x0000 }, /* R21126 - VSS_XTS26_1 */
1929         [21127] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21127 - VSS_XTS26_0 */
1930         [21128] = { 0x00FF, 0x00FF, 0x0000 }, /* R21128 - VSS_XTS27_1 */
1931         [21129] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21129 - VSS_XTS27_0 */
1932         [21130] = { 0x00FF, 0x00FF, 0x0000 }, /* R21130 - VSS_XTS28_1 */
1933         [21131] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21131 - VSS_XTS28_0 */
1934         [21132] = { 0x00FF, 0x00FF, 0x0000 }, /* R21132 - VSS_XTS29_1 */
1935         [21133] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21133 - VSS_XTS29_0 */
1936         [21134] = { 0x00FF, 0x00FF, 0x0000 }, /* R21134 - VSS_XTS30_1 */
1937         [21135] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21135 - VSS_XTS30_0 */
1938         [21136] = { 0x00FF, 0x00FF, 0x0000 }, /* R21136 - VSS_XTS31_1 */
1939         [21137] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21137 - VSS_XTS31_0 */
1940         [21138] = { 0x00FF, 0x00FF, 0x0000 }, /* R21138 - VSS_XTS32_1 */
1941         [21139] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21139 - VSS_XTS32_0 */
1942 };
1943
1944 static int wm8962_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
1945 {
1946         if (wm8962_reg_access[reg].vol)
1947                 return 1;
1948         else
1949                 return 0;
1950 }
1951
1952 static int wm8962_readable_register(struct snd_soc_codec *codec, unsigned int reg)
1953 {
1954         if (wm8962_reg_access[reg].read)
1955                 return 1;
1956         else
1957                 return 0;
1958 }
1959
1960 static int wm8962_reset(struct snd_soc_codec *codec)
1961 {
1962         return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
1963 }
1964
1965 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1966 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1967 static const unsigned int mixinpga_tlv[] = {
1968         TLV_DB_RANGE_HEAD(7),
1969         0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1970         2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1971         3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1972         5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1973         6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1974 };
1975 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1976 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1977 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1978 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1979 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1980 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1981 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1982 static const unsigned int classd_tlv[] = {
1983         TLV_DB_RANGE_HEAD(7),
1984         0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1985         7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1986 };
1987 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1988
1989 /* The VU bits for the headphones are in a different register to the mute
1990  * bits and only take effect on the PGA if it is actually powered.
1991  */
1992 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1993                             struct snd_ctl_elem_value *ucontrol)
1994 {
1995         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1996         u16 *reg_cache = codec->reg_cache;
1997         int ret;
1998
1999         /* Apply the update (if any) */
2000         ret = snd_soc_put_volsw(kcontrol, ucontrol);
2001         if (ret == 0)
2002                 return 0;
2003
2004         /* If the left PGA is enabled hit that VU bit... */
2005         if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
2006                 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
2007                                      reg_cache[WM8962_HPOUTL_VOLUME]);
2008
2009         /* ...otherwise the right.  The VU is stereo. */
2010         if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
2011                 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
2012                                      reg_cache[WM8962_HPOUTR_VOLUME]);
2013
2014         return 0;
2015 }
2016
2017 /* The VU bits for the speakers are in a different register to the mute
2018  * bits and only take effect on the PGA if it is actually powered.
2019  */
2020 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
2021                             struct snd_ctl_elem_value *ucontrol)
2022 {
2023         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2024         u16 *reg_cache = codec->reg_cache;
2025         int ret;
2026
2027         /* Apply the update (if any) */
2028         ret = snd_soc_put_volsw(kcontrol, ucontrol);
2029         if (ret == 0)
2030                 return 0;
2031
2032         /* If the left PGA is enabled hit that VU bit... */
2033         if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
2034                 return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
2035                                      reg_cache[WM8962_SPKOUTL_VOLUME]);
2036
2037         /* ...otherwise the right.  The VU is stereo. */
2038         if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
2039                 return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
2040                                      reg_cache[WM8962_SPKOUTR_VOLUME]);
2041
2042         return 0;
2043 }
2044
2045 static const char *cap_hpf_mode_text[] = {
2046         "Hi-fi", "Application"
2047 };
2048
2049 static const struct soc_enum cap_hpf_mode =
2050         SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
2051
2052 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
2053 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
2054
2055 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
2056                mixin_tlv),
2057 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
2058                mixinpga_tlv),
2059 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
2060                mixin_tlv),
2061
2062 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
2063                mixin_tlv),
2064 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
2065                mixinpga_tlv),
2066 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
2067                mixin_tlv),
2068
2069 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
2070                  WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
2071 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
2072                  WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
2073 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
2074              WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
2075 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
2076              WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
2077 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
2078 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
2079 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
2080
2081 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
2082                  WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
2083
2084 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
2085                  WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
2086 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
2087
2088 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
2089            5, 1, 0),
2090
2091 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
2092
2093 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
2094                  WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
2095 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
2096                snd_soc_get_volsw, wm8962_put_hp_sw),
2097 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
2098              7, 1, 0),
2099 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
2100                hp_tlv),
2101
2102 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
2103              WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
2104
2105 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
2106                3, 7, 0, bypass_tlv),
2107 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
2108                0, 7, 0, bypass_tlv),
2109 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
2110                7, 1, 1, inmix_tlv),
2111 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
2112                6, 1, 1, inmix_tlv),
2113
2114 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
2115                3, 7, 0, bypass_tlv),
2116 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
2117                0, 7, 0, bypass_tlv),
2118 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
2119                7, 1, 1, inmix_tlv),
2120 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
2121                6, 1, 1, inmix_tlv),
2122
2123 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
2124                classd_tlv),
2125
2126 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
2127 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
2128                  WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
2129 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
2130                  WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
2131 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
2132                  WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
2133 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
2134                  WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
2135 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
2136                  WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
2137 };
2138
2139 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
2140 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
2141 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
2142                snd_soc_get_volsw, wm8962_put_spk_sw),
2143 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
2144
2145 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
2146 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
2147                3, 7, 0, bypass_tlv),
2148 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
2149                0, 7, 0, bypass_tlv),
2150 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
2151                7, 1, 1, inmix_tlv),
2152 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
2153                6, 1, 1, inmix_tlv),
2154 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
2155                7, 1, 0, inmix_tlv),
2156 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
2157                6, 1, 0, inmix_tlv),
2158 };
2159
2160 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
2161 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
2162                  WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
2163 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
2164                snd_soc_get_volsw, wm8962_put_spk_sw),
2165 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
2166              7, 1, 0),
2167
2168 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
2169              WM8962_SPEAKER_MIXER_4, 8, 1, 1),
2170
2171 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
2172                3, 7, 0, bypass_tlv),
2173 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
2174                0, 7, 0, bypass_tlv),
2175 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
2176                7, 1, 1, inmix_tlv),
2177 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
2178                6, 1, 1, inmix_tlv),
2179 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
2180                7, 1, 0, inmix_tlv),
2181 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
2182                6, 1, 0, inmix_tlv),
2183
2184 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
2185                3, 7, 0, bypass_tlv),
2186 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
2187                0, 7, 0, bypass_tlv),
2188 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
2189                7, 1, 1, inmix_tlv),
2190 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
2191                6, 1, 1, inmix_tlv),
2192 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
2193                5, 1, 0, inmix_tlv),
2194 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
2195                4, 1, 0, inmix_tlv),
2196 };
2197
2198 static int sysclk_event(struct snd_soc_dapm_widget *w,
2199                         struct snd_kcontrol *kcontrol, int event)
2200 {
2201         struct snd_soc_codec *codec = w->codec;
2202         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2203         unsigned long timeout;
2204         int src;
2205         int fll;
2206
2207         src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
2208
2209         switch (src) {
2210         case 0:      /* MCLK */
2211                 fll = 0;
2212                 break;
2213         case 0x200:  /* FLL */
2214                 fll = 1;
2215                 break;
2216         default:
2217                 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
2218                 return -EINVAL;
2219         }
2220
2221         switch (event) {
2222         case SND_SOC_DAPM_PRE_PMU:
2223                 if (fll) {
2224                         try_wait_for_completion(&wm8962->fll_lock);
2225
2226                         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2227                                             WM8962_FLL_ENA, WM8962_FLL_ENA);
2228                         if (wm8962->irq) {
2229                                 timeout = msecs_to_jiffies(5);
2230                                 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2231                                                                       timeout);
2232
2233                                 if (timeout == 0)
2234                                         dev_err(codec->dev,
2235                                                 "Timed out starting FLL\n");
2236                         }
2237                 }
2238                 break;
2239
2240         case SND_SOC_DAPM_POST_PMD:
2241                 if (fll)
2242                         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2243                                             WM8962_FLL_ENA, 0);
2244                 break;
2245
2246         default:
2247                 BUG();
2248                 return -EINVAL;
2249         }
2250
2251         return 0;
2252 }
2253
2254 static int cp_event(struct snd_soc_dapm_widget *w,
2255                     struct snd_kcontrol *kcontrol, int event)
2256 {
2257         switch (event) {
2258         case SND_SOC_DAPM_POST_PMU:
2259                 msleep(5);
2260                 break;
2261
2262         default:
2263                 BUG();
2264                 return -EINVAL;
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int hp_event(struct snd_soc_dapm_widget *w,
2271                     struct snd_kcontrol *kcontrol, int event)
2272 {
2273         struct snd_soc_codec *codec = w->codec;
2274         int timeout;
2275         int reg;
2276         int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
2277                         WM8962_DCS_STARTUP_DONE_HP1R);
2278
2279         switch (event) {
2280         case SND_SOC_DAPM_POST_PMU:
2281                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
2282                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
2283                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
2284                 udelay(20);
2285
2286                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
2287                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
2288                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
2289
2290                 /* Start the DC servo */
2291                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
2292                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
2293                                     WM8962_HP1L_DCS_STARTUP |
2294                                     WM8962_HP1R_DCS_STARTUP,
2295                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
2296                                     WM8962_HP1L_DCS_STARTUP |
2297                                     WM8962_HP1R_DCS_STARTUP);
2298
2299                 /* Wait for it to complete, should be well under 100ms */
2300                 timeout = 0;
2301                 do {
2302                         msleep(1);
2303                         reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
2304                         if (reg < 0) {
2305                                 dev_err(codec->dev,
2306                                         "Failed to read DCS status: %d\n",
2307                                         reg);
2308                                 continue;
2309                         }
2310                         dev_dbg(codec->dev, "DCS status: %x\n", reg);
2311                 } while (++timeout < 200 && (reg & expected) != expected);
2312
2313                 if ((reg & expected) != expected)
2314                         dev_err(codec->dev, "DC servo timed out\n");
2315                 else
2316                         dev_dbg(codec->dev, "DC servo complete after %dms\n",
2317                                 timeout);
2318
2319                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
2320                                     WM8962_HP1L_ENA_OUTP |
2321                                     WM8962_HP1R_ENA_OUTP,
2322                                     WM8962_HP1L_ENA_OUTP |
2323                                     WM8962_HP1R_ENA_OUTP);
2324                 udelay(20);
2325
2326                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
2327                                     WM8962_HP1L_RMV_SHORT |
2328                                     WM8962_HP1R_RMV_SHORT,
2329                                     WM8962_HP1L_RMV_SHORT |
2330                                     WM8962_HP1R_RMV_SHORT);
2331                 break;
2332
2333         case SND_SOC_DAPM_PRE_PMD:
2334                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
2335                                     WM8962_HP1L_RMV_SHORT |
2336                                     WM8962_HP1R_RMV_SHORT, 0);
2337
2338                 udelay(20);
2339
2340                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
2341                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
2342                                     WM8962_HP1L_DCS_STARTUP |
2343                                     WM8962_HP1R_DCS_STARTUP,
2344                                     0);
2345
2346                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
2347                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
2348                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
2349                                     WM8962_HP1L_ENA_OUTP |
2350                                     WM8962_HP1R_ENA_OUTP, 0);
2351
2352                 break;
2353
2354         default:
2355                 BUG();
2356                 return -EINVAL;
2357
2358         }
2359
2360         return 0;
2361 }
2362
2363 /* VU bits for the output PGAs only take effect while the PGA is powered */
2364 static int out_pga_event(struct snd_soc_dapm_widget *w,
2365                          struct snd_kcontrol *kcontrol, int event)
2366 {
2367         struct snd_soc_codec *codec = w->codec;
2368         u16 *reg_cache = codec->reg_cache;
2369         int reg;
2370
2371         switch (w->shift) {
2372         case WM8962_HPOUTR_PGA_ENA_SHIFT:
2373                 reg = WM8962_HPOUTR_VOLUME;
2374                 break;
2375         case WM8962_HPOUTL_PGA_ENA_SHIFT:
2376                 reg = WM8962_HPOUTL_VOLUME;
2377                 break;
2378         case WM8962_SPKOUTR_PGA_ENA_SHIFT:
2379                 reg = WM8962_SPKOUTR_VOLUME;
2380                 break;
2381         case WM8962_SPKOUTL_PGA_ENA_SHIFT:
2382                 reg = WM8962_SPKOUTL_VOLUME;
2383                 break;
2384         default:
2385                 BUG();
2386                 return -EINVAL;
2387         }
2388
2389         switch (event) {
2390         case SND_SOC_DAPM_POST_PMU:
2391                 return snd_soc_write(codec, reg, reg_cache[reg]);
2392         default:
2393                 BUG();
2394                 return -EINVAL;
2395         }
2396 }
2397
2398 static const char *st_text[] = { "None", "Right", "Left" };
2399
2400 static const struct soc_enum str_enum =
2401         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2402
2403 static const struct snd_kcontrol_new str_mux =
2404         SOC_DAPM_ENUM("Right Sidetone", str_enum);
2405
2406 static const struct soc_enum stl_enum =
2407         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2408
2409 static const struct snd_kcontrol_new stl_mux =
2410         SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2411
2412 static const char *outmux_text[] = { "DAC", "Mixer" };
2413
2414 static const struct soc_enum spkoutr_enum =
2415         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2416
2417 static const struct snd_kcontrol_new spkoutr_mux =
2418         SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2419
2420 static const struct soc_enum spkoutl_enum =
2421         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2422
2423 static const struct snd_kcontrol_new spkoutl_mux =
2424         SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2425
2426 static const struct soc_enum hpoutr_enum =
2427         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2428
2429 static const struct snd_kcontrol_new hpoutr_mux =
2430         SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2431
2432 static const struct soc_enum hpoutl_enum =
2433         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2434
2435 static const struct snd_kcontrol_new hpoutl_mux =
2436         SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2437
2438 static const struct snd_kcontrol_new inpgal[] = {
2439 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2440 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2441 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2442 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2443 };
2444
2445 static const struct snd_kcontrol_new inpgar[] = {
2446 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2447 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2448 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2449 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2450 };
2451
2452 static const struct snd_kcontrol_new mixinl[] = {
2453 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2454 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2455 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2456 };
2457
2458 static const struct snd_kcontrol_new mixinr[] = {
2459 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2460 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2461 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2462 };
2463
2464 static const struct snd_kcontrol_new hpmixl[] = {
2465 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2466 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2467 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2468 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2469 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2470 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2471 };
2472
2473 static const struct snd_kcontrol_new hpmixr[] = {
2474 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2475 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2476 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2477 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2478 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2479 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2480 };
2481
2482 static const struct snd_kcontrol_new spkmixl[] = {
2483 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2484 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2485 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2486 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2487 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2488 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2489 };
2490
2491 static const struct snd_kcontrol_new spkmixr[] = {
2492 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2493 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2494 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2495 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2496 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2497 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2498 };
2499
2500 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2501 SND_SOC_DAPM_INPUT("IN1L"),
2502 SND_SOC_DAPM_INPUT("IN1R"),
2503 SND_SOC_DAPM_INPUT("IN2L"),
2504 SND_SOC_DAPM_INPUT("IN2R"),
2505 SND_SOC_DAPM_INPUT("IN3L"),
2506 SND_SOC_DAPM_INPUT("IN3R"),
2507 SND_SOC_DAPM_INPUT("IN4L"),
2508 SND_SOC_DAPM_INPUT("IN4R"),
2509 SND_SOC_DAPM_INPUT("Beep"),
2510 SND_SOC_DAPM_INPUT("DMICDAT"),
2511
2512 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
2513
2514 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2515 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
2516                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2517 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2518                     SND_SOC_DAPM_POST_PMU),
2519 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2520
2521 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2522                    inpgal, ARRAY_SIZE(inpgal)),
2523 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2524                    inpgar, ARRAY_SIZE(inpgar)),
2525 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2526                    mixinl, ARRAY_SIZE(mixinl)),
2527 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2528                    mixinr, ARRAY_SIZE(mixinr)),
2529
2530 SND_SOC_DAPM_AIF_IN("DMIC", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2531
2532 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2533 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2534
2535 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2536 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2537
2538 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2539 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2540
2541 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2542 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2543
2544 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2545                    hpmixl, ARRAY_SIZE(hpmixl)),
2546 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2547                    hpmixr, ARRAY_SIZE(hpmixr)),
2548
2549 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2550                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2551 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2552                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2553
2554 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2555                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2556
2557 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2558 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2559 };
2560
2561 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2562 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2563                    spkmixl, ARRAY_SIZE(spkmixl)),
2564 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2565                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2566 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2567 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2568 };
2569
2570 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2571 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2572                    spkmixl, ARRAY_SIZE(spkmixl)),
2573 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2574                    spkmixr, ARRAY_SIZE(spkmixr)),
2575
2576 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2577                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2578 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2579                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2580
2581 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2583
2584 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2585 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2586 };
2587
2588 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2589         { "INPGAL", "IN1L Switch", "IN1L" },
2590         { "INPGAL", "IN2L Switch", "IN2L" },
2591         { "INPGAL", "IN3L Switch", "IN3L" },
2592         { "INPGAL", "IN4L Switch", "IN4L" },
2593
2594         { "INPGAR", "IN1R Switch", "IN1R" },
2595         { "INPGAR", "IN2R Switch", "IN2R" },
2596         { "INPGAR", "IN3R Switch", "IN3R" },
2597         { "INPGAR", "IN4R Switch", "IN4R" },
2598
2599         { "MIXINL", "IN2L Switch", "IN2L" },
2600         { "MIXINL", "IN3L Switch", "IN3L" },
2601         { "MIXINL", "PGA Switch", "INPGAL" },
2602
2603         { "MIXINR", "IN2R Switch", "IN2R" },
2604         { "MIXINR", "IN3R Switch", "IN3R" },
2605         { "MIXINR", "PGA Switch", "INPGAR" },
2606
2607         { "MICBIAS", NULL, "SYSCLK" },
2608
2609         { "DMIC", NULL, "DMICDAT" },
2610
2611         { "ADCL", NULL, "SYSCLK" },
2612         { "ADCL", NULL, "TOCLK" },
2613         { "ADCL", NULL, "MIXINL" },
2614         { "ADCL", NULL, "DMIC" },
2615
2616         { "ADCR", NULL, "SYSCLK" },
2617         { "ADCR", NULL, "TOCLK" },
2618         { "ADCR", NULL, "MIXINR" },
2619         { "ADCR", NULL, "DMIC" },
2620
2621         { "STL", "Left", "ADCL" },
2622         { "STL", "Right", "ADCR" },
2623
2624         { "STR", "Left", "ADCL" },
2625         { "STR", "Right", "ADCR" },
2626
2627         { "DACL", NULL, "SYSCLK" },
2628         { "DACL", NULL, "TOCLK" },
2629         { "DACL", NULL, "Beep" },
2630         { "DACL", NULL, "STL" },
2631
2632         { "DACR", NULL, "SYSCLK" },
2633         { "DACR", NULL, "TOCLK" },
2634         { "DACR", NULL, "Beep" },
2635         { "DACR", NULL, "STR" },
2636
2637         { "HPMIXL", "IN4L Switch", "IN4L" },
2638         { "HPMIXL", "IN4R Switch", "IN4R" },
2639         { "HPMIXL", "DACL Switch", "DACL" },
2640         { "HPMIXL", "DACR Switch", "DACR" },
2641         { "HPMIXL", "MIXINL Switch", "MIXINL" },
2642         { "HPMIXL", "MIXINR Switch", "MIXINR" },
2643
2644         { "HPMIXR", "IN4L Switch", "IN4L" },
2645         { "HPMIXR", "IN4R Switch", "IN4R" },
2646         { "HPMIXR", "DACL Switch", "DACL" },
2647         { "HPMIXR", "DACR Switch", "DACR" },
2648         { "HPMIXR", "MIXINL Switch", "MIXINL" },
2649         { "HPMIXR", "MIXINR Switch", "MIXINR" },
2650
2651         { "Left Bypass", NULL, "HPMIXL" },
2652         { "Left Bypass", NULL, "Class G" },
2653
2654         { "Right Bypass", NULL, "HPMIXR" },
2655         { "Right Bypass", NULL, "Class G" },
2656
2657         { "HPOUTL PGA", "Mixer", "Left Bypass" },
2658         { "HPOUTL PGA", "DAC", "DACL" },
2659
2660         { "HPOUTR PGA", "Mixer", "Right Bypass" },
2661         { "HPOUTR PGA", "DAC", "DACR" },
2662
2663         { "HPOUT", NULL, "HPOUTL PGA" },
2664         { "HPOUT", NULL, "HPOUTR PGA" },
2665         { "HPOUT", NULL, "Charge Pump" },
2666         { "HPOUT", NULL, "SYSCLK" },
2667         { "HPOUT", NULL, "TOCLK" },
2668
2669         { "HPOUTL", NULL, "HPOUT" },
2670         { "HPOUTR", NULL, "HPOUT" },
2671 };
2672
2673 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2674         { "Speaker Mixer", "IN4L Switch", "IN4L" },
2675         { "Speaker Mixer", "IN4R Switch", "IN4R" },
2676         { "Speaker Mixer", "DACL Switch", "DACL" },
2677         { "Speaker Mixer", "DACR Switch", "DACR" },
2678         { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2679         { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2680
2681         { "Speaker PGA", "Mixer", "Speaker Mixer" },
2682         { "Speaker PGA", "DAC", "DACL" },
2683
2684         { "Speaker Output", NULL, "Speaker PGA" },
2685         { "Speaker Output", NULL, "SYSCLK" },
2686         { "Speaker Output", NULL, "TOCLK" },
2687
2688         { "SPKOUT", NULL, "Speaker Output" },
2689 };
2690
2691 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2692         { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2693         { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2694         { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2695         { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2696         { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2697         { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2698
2699         { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2700         { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2701         { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2702         { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2703         { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2704         { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2705
2706         { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2707         { "SPKOUTL PGA", "DAC", "DACL" },
2708
2709         { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2710         { "SPKOUTR PGA", "DAC", "DACR" },
2711
2712         { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2713         { "SPKOUTL Output", NULL, "SYSCLK" },
2714         { "SPKOUTL Output", NULL, "TOCLK" },
2715
2716         { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2717         { "SPKOUTR Output", NULL, "SYSCLK" },
2718         { "SPKOUTR Output", NULL, "TOCLK" },
2719
2720         { "SPKOUTL", NULL, "SPKOUTL Output" },
2721         { "SPKOUTR", NULL, "SPKOUTR Output" },
2722 };
2723
2724 static int wm8962_add_widgets(struct snd_soc_codec *codec)
2725 {
2726         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
2727         struct snd_soc_dapm_context *dapm = &codec->dapm;
2728
2729         snd_soc_add_controls(codec, wm8962_snd_controls,
2730                              ARRAY_SIZE(wm8962_snd_controls));
2731         if (pdata && pdata->spk_mono)
2732                 snd_soc_add_controls(codec, wm8962_spk_mono_controls,
2733                                      ARRAY_SIZE(wm8962_spk_mono_controls));
2734         else
2735                 snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
2736                                      ARRAY_SIZE(wm8962_spk_stereo_controls));
2737
2738
2739         snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2740                                   ARRAY_SIZE(wm8962_dapm_widgets));
2741         if (pdata && pdata->spk_mono)
2742                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2743                                           ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2744         else
2745                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2746                                           ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2747
2748         snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2749                                 ARRAY_SIZE(wm8962_intercon));
2750         if (pdata && pdata->spk_mono)
2751                 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2752                                         ARRAY_SIZE(wm8962_spk_mono_intercon));
2753         else
2754                 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2755                                         ARRAY_SIZE(wm8962_spk_stereo_intercon));
2756
2757
2758         snd_soc_dapm_disable_pin(dapm, "Beep");
2759
2760         return 0;
2761 }
2762
2763 static void wm8962_sync_cache(struct snd_soc_codec *codec)
2764 {
2765         u16 *reg_cache = codec->reg_cache;
2766         int i;
2767
2768         if (!codec->cache_sync)
2769                 return;
2770
2771         dev_dbg(codec->dev, "Syncing cache\n");
2772
2773         codec->cache_only = 0;
2774
2775         /* Sync back cached values if they're different from the
2776          * hardware default.
2777          */
2778         for (i = 1; i < codec->driver->reg_cache_size; i++) {
2779                 if (i == WM8962_SOFTWARE_RESET)
2780                         continue;
2781                 if (reg_cache[i] == wm8962_reg[i])
2782                         continue;
2783
2784                 snd_soc_write(codec, i, reg_cache[i]);
2785         }
2786
2787         codec->cache_sync = 0;
2788 }
2789
2790 /* -1 for reserved values */
2791 static const int bclk_divs[] = {
2792         1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2793 };
2794
2795 static const int sysclk_rates[] = {
2796         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
2797 };
2798
2799 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2800 {
2801         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2802         int dspclk, i;
2803         int clocking2 = 0;
2804         int clocking4 = 0;
2805         int aif2 = 0;
2806
2807         if (!wm8962->sysclk_rate) {
2808                 dev_dbg(codec->dev, "No SYSCLK configured\n");
2809                 return;
2810         }
2811
2812         if (!wm8962->bclk || !wm8962->lrclk) {
2813                 dev_dbg(codec->dev, "No audio clocks configured\n");
2814                 return;
2815         }
2816
2817         for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2818                 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2819                         clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2820                         break;
2821                 }
2822         }
2823
2824         if (i == ARRAY_SIZE(sysclk_rates)) {
2825                 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2826                         wm8962->sysclk_rate / wm8962->lrclk);
2827                 return;
2828         }
2829
2830         snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2831                             WM8962_SYSCLK_RATE_MASK, clocking4);
2832
2833         dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2834         if (dspclk < 0) {
2835                 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2836                 return;
2837         }
2838
2839         dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2840         switch (dspclk) {
2841         case 0:
2842                 dspclk = wm8962->sysclk_rate;
2843                 break;
2844         case 1:
2845                 dspclk = wm8962->sysclk_rate / 2;
2846                 break;
2847         case 2:
2848                 dspclk = wm8962->sysclk_rate / 4;
2849                 break;
2850         default:
2851                 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2852                 dspclk = wm8962->sysclk;
2853         }
2854
2855         dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2856
2857         /* We're expecting an exact match */
2858         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2859                 if (bclk_divs[i] < 0)
2860                         continue;
2861
2862                 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2863                         dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2864                                 bclk_divs[i], wm8962->bclk);
2865                         clocking2 |= i;
2866                         break;
2867                 }
2868         }
2869         if (i == ARRAY_SIZE(bclk_divs)) {
2870                 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2871                         dspclk / wm8962->bclk);
2872                 return;
2873         }
2874
2875         aif2 |= wm8962->bclk / wm8962->lrclk;
2876         dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2877                 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2878
2879         snd_soc_update_bits(codec, WM8962_CLOCKING2,
2880                             WM8962_BCLK_DIV_MASK, clocking2);
2881         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2882                             WM8962_AIF_RATE_MASK, aif2);
2883 }
2884
2885 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2886                                  enum snd_soc_bias_level level)
2887 {
2888         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2889         int ret;
2890
2891         if (level == codec->dapm.bias_level)
2892                 return 0;
2893
2894         switch (level) {
2895         case SND_SOC_BIAS_ON:
2896                 break;
2897
2898         case SND_SOC_BIAS_PREPARE:
2899                 /* VMID 2*50k */
2900                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2901                                     WM8962_VMID_SEL_MASK, 0x80);
2902
2903                 wm8962_configure_bclk(codec);
2904                 break;
2905
2906         case SND_SOC_BIAS_STANDBY:
2907                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2908                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
2909                                                     wm8962->supplies);
2910                         if (ret != 0) {
2911                                 dev_err(codec->dev,
2912                                         "Failed to enable supplies: %d\n",
2913                                         ret);
2914                                 return ret;
2915                         }
2916
2917                         wm8962_sync_cache(codec);
2918
2919                         snd_soc_update_bits(codec, WM8962_ANTI_POP,
2920                                             WM8962_STARTUP_BIAS_ENA |
2921                                             WM8962_VMID_BUF_ENA,
2922                                             WM8962_STARTUP_BIAS_ENA |
2923                                             WM8962_VMID_BUF_ENA);
2924
2925                         /* Bias enable at 2*50k for ramp */
2926                         snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2927                                             WM8962_VMID_SEL_MASK |
2928                                             WM8962_BIAS_ENA,
2929                                             WM8962_BIAS_ENA | 0x180);
2930
2931                         msleep(5);
2932                 }
2933
2934                 /* VMID 2*250k */
2935                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2936                                     WM8962_VMID_SEL_MASK, 0x100);
2937                 break;
2938
2939         case SND_SOC_BIAS_OFF:
2940                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2941                                     WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
2942
2943                 snd_soc_update_bits(codec, WM8962_ANTI_POP,
2944                                     WM8962_STARTUP_BIAS_ENA |
2945                                     WM8962_VMID_BUF_ENA, 0);
2946
2947                 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
2948                                        wm8962->supplies);
2949                 break;
2950         }
2951         codec->dapm.bias_level = level;
2952         return 0;
2953 }
2954
2955 static const struct {
2956         int rate;
2957         int reg;
2958 } sr_vals[] = {
2959         { 48000, 0 },
2960         { 44100, 0 },
2961         { 32000, 1 },
2962         { 22050, 2 },
2963         { 24000, 2 },
2964         { 16000, 3 },
2965         { 11025, 4 },
2966         { 12000, 4 },
2967         { 8000,  5 },
2968         { 88200, 6 },
2969         { 96000, 6 },
2970 };
2971
2972 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2973                             struct snd_pcm_hw_params *params,
2974                             struct snd_soc_dai *dai)
2975 {
2976         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2977         struct snd_soc_codec *codec = rtd->codec;
2978         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2979         int i;
2980         int aif0 = 0;
2981         int adctl3 = 0;
2982
2983         wm8962->bclk = snd_soc_params_to_bclk(params);
2984         wm8962->lrclk = params_rate(params);
2985
2986         for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2987                 if (sr_vals[i].rate == wm8962->lrclk) {
2988                         adctl3 |= sr_vals[i].reg;
2989                         break;
2990                 }
2991         }
2992         if (i == ARRAY_SIZE(sr_vals)) {
2993                 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2994                 return -EINVAL;
2995         }
2996
2997         if (wm8962->lrclk % 8000 == 0)
2998                 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2999
3000         switch (params_format(params)) {
3001         case SNDRV_PCM_FORMAT_S16_LE:
3002                 break;
3003         case SNDRV_PCM_FORMAT_S20_3LE:
3004                 aif0 |= 0x40;
3005                 break;
3006         case SNDRV_PCM_FORMAT_S24_LE:
3007                 aif0 |= 0x80;
3008                 break;
3009         case SNDRV_PCM_FORMAT_S32_LE:
3010                 aif0 |= 0xc0;
3011                 break;
3012         default:
3013                 return -EINVAL;
3014         }
3015
3016         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
3017                             WM8962_WL_MASK, aif0);
3018         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
3019                             WM8962_SAMPLE_RATE_INT_MODE |
3020                             WM8962_SAMPLE_RATE_MASK, adctl3);
3021
3022         wm8962_configure_bclk(codec);
3023
3024         return 0;
3025 }
3026
3027 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
3028                                  unsigned int freq, int dir)
3029 {
3030         struct snd_soc_codec *codec = dai->codec;
3031         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3032         int src;
3033
3034         switch (clk_id) {
3035         case WM8962_SYSCLK_MCLK:
3036                 wm8962->sysclk = WM8962_SYSCLK_MCLK;
3037                 src = 0;
3038                 break;
3039         case WM8962_SYSCLK_FLL:
3040                 wm8962->sysclk = WM8962_SYSCLK_FLL;
3041                 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
3042                 break;
3043         default:
3044                 return -EINVAL;
3045         }
3046
3047         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
3048                             src);
3049
3050         wm8962->sysclk_rate = freq;
3051
3052         return 0;
3053 }
3054
3055 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3056 {
3057         struct snd_soc_codec *codec = dai->codec;
3058         int aif0 = 0;
3059
3060         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3061         case SND_SOC_DAIFMT_DSP_A:
3062                 aif0 |= WM8962_LRCLK_INV;
3063         case SND_SOC_DAIFMT_DSP_B:
3064                 aif0 |= 3;
3065
3066                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3067                 case SND_SOC_DAIFMT_NB_NF:
3068                 case SND_SOC_DAIFMT_IB_NF:
3069                         break;
3070                 default:
3071                         return -EINVAL;
3072                 }
3073                 break;
3074
3075         case SND_SOC_DAIFMT_RIGHT_J:
3076                 break;
3077         case SND_SOC_DAIFMT_LEFT_J:
3078                 aif0 |= 1;
3079                 break;
3080         case SND_SOC_DAIFMT_I2S:
3081                 aif0 |= 2;
3082                 break;
3083         default:
3084                 return -EINVAL;
3085         }
3086
3087         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3088         case SND_SOC_DAIFMT_NB_NF:
3089                 break;
3090         case SND_SOC_DAIFMT_IB_NF:
3091                 aif0 |= WM8962_BCLK_INV;
3092                 break;
3093         case SND_SOC_DAIFMT_NB_IF:
3094                 aif0 |= WM8962_LRCLK_INV;
3095                 break;
3096         case SND_SOC_DAIFMT_IB_IF:
3097                 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
3098                 break;
3099         default:
3100                 return -EINVAL;
3101         }
3102
3103         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3104         case SND_SOC_DAIFMT_CBM_CFM:
3105                 aif0 |= WM8962_MSTR;
3106                 break;
3107         case SND_SOC_DAIFMT_CBS_CFS:
3108                 break;
3109         default:
3110                 return -EINVAL;
3111         }
3112
3113         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
3114                             WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
3115                             WM8962_LRCLK_INV, aif0);
3116
3117         return 0;
3118 }
3119
3120 struct _fll_div {
3121         u16 fll_fratio;
3122         u16 fll_outdiv;
3123         u16 fll_refclk_div;
3124         u16 n;
3125         u16 theta;
3126         u16 lambda;
3127 };
3128
3129 /* The size in bits of the FLL divide multiplied by 10
3130  * to allow rounding later */
3131 #define FIXED_FLL_SIZE ((1 << 16) * 10)
3132
3133 static struct {
3134         unsigned int min;
3135         unsigned int max;
3136         u16 fll_fratio;
3137         int ratio;
3138 } fll_fratios[] = {
3139         {       0,    64000, 4, 16 },
3140         {   64000,   128000, 3,  8 },
3141         {  128000,   256000, 2,  4 },
3142         {  256000,  1000000, 1,  2 },
3143         { 1000000, 13500000, 0,  1 },
3144 };
3145
3146 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
3147                        unsigned int Fout)
3148 {
3149         unsigned int target;
3150         unsigned int div;
3151         unsigned int fratio, gcd_fll;
3152         int i;
3153
3154         /* Fref must be <=13.5MHz */
3155         div = 1;
3156         fll_div->fll_refclk_div = 0;
3157         while ((Fref / div) > 13500000) {
3158                 div *= 2;
3159                 fll_div->fll_refclk_div++;
3160
3161                 if (div > 4) {
3162                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
3163                                Fref);
3164                         return -EINVAL;
3165                 }
3166         }
3167
3168         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
3169
3170         /* Apply the division for our remaining calculations */
3171         Fref /= div;
3172
3173         /* Fvco should be 90-100MHz; don't check the upper bound */
3174         div = 2;
3175         while (Fout * div < 90000000) {
3176                 div++;
3177                 if (div > 64) {
3178                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
3179                                Fout);
3180                         return -EINVAL;
3181                 }
3182         }
3183         target = Fout * div;
3184         fll_div->fll_outdiv = div - 1;
3185
3186         pr_debug("FLL Fvco=%dHz\n", target);
3187
3188         /* Find an appropriate FLL_FRATIO and factor it out of the target */
3189         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
3190                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
3191                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
3192                         fratio = fll_fratios[i].ratio;
3193                         break;
3194                 }
3195         }
3196         if (i == ARRAY_SIZE(fll_fratios)) {
3197                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
3198                 return -EINVAL;
3199         }
3200
3201         fll_div->n = target / (fratio * Fref);
3202
3203         if (target % Fref == 0) {
3204                 fll_div->theta = 0;
3205                 fll_div->lambda = 0;
3206         } else {
3207                 gcd_fll = gcd(target, fratio * Fref);
3208
3209                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
3210                         / gcd_fll;
3211                 fll_div->lambda = (fratio * Fref) / gcd_fll;
3212         }
3213
3214         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
3215                  fll_div->n, fll_div->theta, fll_div->lambda);
3216         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
3217                  fll_div->fll_fratio, fll_div->fll_outdiv,
3218                  fll_div->fll_refclk_div);
3219
3220         return 0;
3221 }
3222
3223 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
3224                           unsigned int Fref, unsigned int Fout)
3225 {
3226         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3227         struct _fll_div fll_div;
3228         unsigned long timeout;
3229         int ret;
3230         int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
3231
3232         /* Any change? */
3233         if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
3234             Fout == wm8962->fll_fout)
3235                 return 0;
3236
3237         if (Fout == 0) {
3238                 dev_dbg(codec->dev, "FLL disabled\n");
3239
3240                 wm8962->fll_fref = 0;
3241                 wm8962->fll_fout = 0;
3242
3243                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
3244                                     WM8962_FLL_ENA, 0);
3245
3246                 return 0;
3247         }
3248
3249         ret = fll_factors(&fll_div, Fref, Fout);
3250         if (ret != 0)
3251                 return ret;
3252
3253         switch (fll_id) {
3254         case WM8962_FLL_MCLK:
3255         case WM8962_FLL_BCLK:
3256         case WM8962_FLL_OSC:
3257                 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
3258                 break;
3259         case WM8962_FLL_INT:
3260                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
3261                                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
3262                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
3263                                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
3264                 break;
3265         default:
3266                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
3267                 return -EINVAL;
3268         }
3269
3270         if (fll_div.theta || fll_div.lambda)
3271                 fll1 |= WM8962_FLL_FRAC;
3272
3273         /* Stop the FLL while we reconfigure */
3274         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
3275
3276         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
3277                             WM8962_FLL_OUTDIV_MASK |
3278                             WM8962_FLL_REFCLK_DIV_MASK,
3279                             (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
3280                             (fll_div.fll_refclk_div));
3281
3282         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
3283                             WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
3284
3285         snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
3286         snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
3287         snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
3288
3289         try_wait_for_completion(&wm8962->fll_lock);
3290
3291         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
3292                             WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
3293                             WM8962_FLL_ENA, fll1);
3294
3295         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
3296
3297         ret = 0;
3298
3299         if (fll1 & WM8962_FLL_ENA) {
3300                 /* This should be a massive overestimate but go even
3301                  * higher if we'll error out
3302                  */
3303                 if (wm8962->irq)
3304                         timeout = msecs_to_jiffies(5);
3305                 else
3306                         timeout = msecs_to_jiffies(1);
3307
3308                 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
3309                                                       timeout);
3310
3311                 if (timeout == 0 && wm8962->irq) {
3312                         dev_err(codec->dev, "FLL lock timed out");
3313                         ret = -ETIMEDOUT;
3314                 }
3315         }
3316
3317         wm8962->fll_fref = Fref;
3318         wm8962->fll_fout = Fout;
3319         wm8962->fll_src = source;
3320
3321         return ret;
3322 }
3323
3324 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
3325 {
3326         struct snd_soc_codec *codec = dai->codec;
3327         int val;
3328
3329         if (mute)
3330                 val = WM8962_DAC_MUTE;
3331         else
3332                 val = 0;
3333
3334         return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
3335                                    WM8962_DAC_MUTE, val);
3336 }
3337
3338 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
3339
3340 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3341                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3342
3343 static struct snd_soc_dai_ops wm8962_dai_ops = {
3344         .hw_params = wm8962_hw_params,
3345         .set_sysclk = wm8962_set_dai_sysclk,
3346         .set_fmt = wm8962_set_dai_fmt,
3347         .digital_mute = wm8962_mute,
3348 };
3349
3350 static struct snd_soc_dai_driver wm8962_dai = {
3351         .name = "wm8962",
3352         .playback = {
3353                 .stream_name = "Playback",
3354                 .channels_min = 2,
3355                 .channels_max = 2,
3356                 .rates = WM8962_RATES,
3357                 .formats = WM8962_FORMATS,
3358         },
3359         .capture = {
3360                 .stream_name = "Capture",
3361                 .channels_min = 2,
3362                 .channels_max = 2,
3363                 .rates = WM8962_RATES,
3364                 .formats = WM8962_FORMATS,
3365         },
3366         .ops = &wm8962_dai_ops,
3367         .symmetric_rates = 1,
3368 };
3369
3370 static void wm8962_mic_work(struct work_struct *work)
3371 {
3372         struct wm8962_priv *wm8962 = container_of(work,
3373                                                   struct wm8962_priv,
3374                                                   mic_work.work);
3375         struct snd_soc_codec *codec = wm8962->codec;
3376         int status = 0;
3377         int irq_pol = 0;
3378         int reg;
3379
3380         reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
3381
3382         if (reg & WM8962_MICDET_STS) {
3383                 status |= SND_JACK_MICROPHONE;
3384                 irq_pol |= WM8962_MICD_IRQ_POL;
3385         }
3386
3387         if (reg & WM8962_MICSHORT_STS) {
3388                 status |= SND_JACK_BTN_0;
3389                 irq_pol |= WM8962_MICSCD_IRQ_POL;
3390         }
3391
3392         snd_soc_jack_report(wm8962->jack, status,
3393                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3394
3395         snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
3396                             WM8962_MICSCD_IRQ_POL |
3397                             WM8962_MICD_IRQ_POL, irq_pol);
3398 }
3399
3400 static irqreturn_t wm8962_irq(int irq, void *data)
3401 {
3402         struct snd_soc_codec *codec = data;
3403         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3404         int mask;
3405         int active;
3406
3407         mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2_MASK);
3408
3409         active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
3410         active &= ~mask;
3411
3412         /* Acknowledge the interrupts */
3413         snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
3414
3415         if (active & WM8962_FLL_LOCK_EINT) {
3416                 dev_dbg(codec->dev, "FLL locked\n");
3417                 complete(&wm8962->fll_lock);
3418         }
3419
3420         if (active & WM8962_FIFOS_ERR_EINT)
3421                 dev_err(codec->dev, "FIFO error\n");
3422
3423         if (active & WM8962_TEMP_SHUT_EINT)
3424                 dev_crit(codec->dev, "Thermal shutdown\n");
3425
3426         if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3427                 dev_dbg(codec->dev, "Microphone event detected\n");
3428
3429 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3430                 trace_snd_soc_jack_irq(dev_name(codec->dev));
3431 #endif
3432
3433                 pm_wakeup_event(codec->dev, 300);
3434
3435                 schedule_delayed_work(&wm8962->mic_work,
3436                                       msecs_to_jiffies(250));
3437         }
3438
3439         return IRQ_HANDLED;
3440 }
3441
3442 /**
3443  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3444  *
3445  * @codec:  WM8962 codec
3446  * @jack:   jack to report detection events on
3447  *
3448  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3449  * being used to bring out signals to the processor then only platform
3450  * data configuration is needed for WM8962 and processor GPIOs should
3451  * be configured using snd_soc_jack_add_gpios() instead.
3452  *
3453  * If no jack is supplied detection will be disabled.
3454  */
3455 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3456 {
3457         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3458         int irq_mask, enable;
3459
3460         wm8962->jack = jack;
3461         if (jack) {
3462                 irq_mask = 0;
3463                 enable = WM8962_MICDET_ENA;
3464         } else {
3465                 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3466                 enable = 0;
3467         }
3468
3469         snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3470                             WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3471         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3472                             WM8962_MICDET_ENA, enable);
3473
3474         /* Send an initial empty report */
3475         snd_soc_jack_report(wm8962->jack, 0,
3476                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3477
3478         return 0;
3479 }
3480 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3481
3482 #ifdef CONFIG_PM
3483 static int wm8962_resume(struct snd_soc_codec *codec)
3484 {
3485         u16 *reg_cache = codec->reg_cache;
3486         int i;
3487
3488         /* Restore the registers */
3489         for (i = 1; i < codec->driver->reg_cache_size; i++) {
3490                 switch (i) {
3491                 case WM8962_SOFTWARE_RESET:
3492                         continue;
3493                 default:
3494                         break;
3495                 }
3496
3497                 if (reg_cache[i] != wm8962_reg[i])
3498                         snd_soc_write(codec, i, reg_cache[i]);
3499         }
3500
3501         return 0;
3502 }
3503 #else
3504 #define wm8962_resume NULL
3505 #endif
3506
3507 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3508 static int beep_rates[] = {
3509         500, 1000, 2000, 4000,
3510 };
3511
3512 static void wm8962_beep_work(struct work_struct *work)
3513 {
3514         struct wm8962_priv *wm8962 =
3515                 container_of(work, struct wm8962_priv, beep_work);
3516         struct snd_soc_codec *codec = wm8962->codec;
3517         struct snd_soc_dapm_context *dapm = &codec->dapm;
3518         int i;
3519         int reg = 0;
3520         int best = 0;
3521
3522         if (wm8962->beep_rate) {
3523                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3524                         if (abs(wm8962->beep_rate - beep_rates[i]) <
3525                             abs(wm8962->beep_rate - beep_rates[best]))
3526                                 best = i;
3527                 }
3528
3529                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3530                         beep_rates[best], wm8962->beep_rate);
3531
3532                 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3533
3534                 snd_soc_dapm_enable_pin(dapm, "Beep");
3535         } else {
3536                 dev_dbg(codec->dev, "Disabling beep\n");
3537                 snd_soc_dapm_disable_pin(dapm, "Beep");
3538         }
3539
3540         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3541                             WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3542
3543         snd_soc_dapm_sync(dapm);
3544 }
3545
3546 /* For usability define a way of injecting beep events for the device -
3547  * many systems will not have a keyboard.
3548  */
3549 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3550                              unsigned int code, int hz)
3551 {
3552         struct snd_soc_codec *codec = input_get_drvdata(dev);
3553         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3554
3555         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3556
3557         switch (code) {
3558         case SND_BELL:
3559                 if (hz)
3560                         hz = 1000;
3561         case SND_TONE:
3562                 break;
3563         default:
3564                 return -1;
3565         }
3566
3567         /* Kick the beep from a workqueue */
3568         wm8962->beep_rate = hz;
3569         schedule_work(&wm8962->beep_work);
3570         return 0;
3571 }
3572
3573 static ssize_t wm8962_beep_set(struct device *dev,
3574                                struct device_attribute *attr,
3575                                const char *buf, size_t count)
3576 {
3577         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3578         long int time;
3579         int ret;
3580
3581         ret = strict_strtol(buf, 10, &time);
3582         if (ret != 0)
3583                 return ret;
3584
3585         input_event(wm8962->beep, EV_SND, SND_TONE, time);
3586
3587         return count;
3588 }
3589
3590 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3591
3592 static void wm8962_init_beep(struct snd_soc_codec *codec)
3593 {
3594         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3595         int ret;
3596
3597         wm8962->beep = input_allocate_device();
3598         if (!wm8962->beep) {
3599                 dev_err(codec->dev, "Failed to allocate beep device\n");
3600                 return;
3601         }
3602
3603         INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3604         wm8962->beep_rate = 0;
3605
3606         wm8962->beep->name = "WM8962 Beep Generator";
3607         wm8962->beep->phys = dev_name(codec->dev);
3608         wm8962->beep->id.bustype = BUS_I2C;
3609
3610         wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3611         wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3612         wm8962->beep->event = wm8962_beep_event;
3613         wm8962->beep->dev.parent = codec->dev;
3614         input_set_drvdata(wm8962->beep, codec);
3615
3616         ret = input_register_device(wm8962->beep);
3617         if (ret != 0) {
3618                 input_free_device(wm8962->beep);
3619                 wm8962->beep = NULL;
3620                 dev_err(codec->dev, "Failed to register beep device\n");
3621         }
3622
3623         ret = device_create_file(codec->dev, &dev_attr_beep);
3624         if (ret != 0) {
3625                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3626                         ret);
3627         }
3628 }
3629
3630 static void wm8962_free_beep(struct snd_soc_codec *codec)
3631 {
3632         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3633
3634         device_remove_file(codec->dev, &dev_attr_beep);
3635         input_unregister_device(wm8962->beep);
3636         cancel_work_sync(&wm8962->beep_work);
3637         wm8962->beep = NULL;
3638
3639         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3640 }
3641 #else
3642 static void wm8962_init_beep(struct snd_soc_codec *codec)
3643 {
3644 }
3645
3646 static void wm8962_free_beep(struct snd_soc_codec *codec)
3647 {
3648 }
3649 #endif
3650
3651 static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3652 {
3653         int mask = 0;
3654         int val = 0;
3655
3656         /* Some of the GPIOs are behind MFP configuration and need to
3657          * be put into GPIO mode. */
3658         switch (gpio) {
3659         case 2:
3660                 mask = WM8962_CLKOUT2_SEL_MASK;
3661                 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3662                 break;
3663         case 3:
3664                 mask = WM8962_CLKOUT3_SEL_MASK;
3665                 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3666                 break;
3667         default:
3668                 break;
3669         }
3670
3671         if (mask)
3672                 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3673                                     mask, val);
3674 }
3675
3676 #ifdef CONFIG_GPIOLIB
3677 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3678 {
3679         return container_of(chip, struct wm8962_priv, gpio_chip);
3680 }
3681
3682 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3683 {
3684         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3685         struct snd_soc_codec *codec = wm8962->codec;
3686
3687         /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3688          * we export linear numbers and error out if the unsupported
3689          * ones are requsted.
3690          */
3691         switch (offset + 1) {
3692         case 2:
3693         case 3:
3694         case 5:
3695         case 6:
3696                 break;
3697         default:
3698                 return -EINVAL;
3699         }
3700
3701         wm8962_set_gpio_mode(codec, offset + 1);
3702
3703         return 0;
3704 }
3705
3706 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3707 {
3708         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3709         struct snd_soc_codec *codec = wm8962->codec;
3710
3711         snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3712                             WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3713 }
3714
3715 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3716                                      unsigned offset, int value)
3717 {
3718         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3719         struct snd_soc_codec *codec = wm8962->codec;
3720         int val;
3721
3722         /* Force function 1 (logic output) */
3723         val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3724
3725         return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3726                                    WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3727 }
3728
3729 static struct gpio_chip wm8962_template_chip = {
3730         .label                  = "wm8962",
3731         .owner                  = THIS_MODULE,
3732         .request                = wm8962_gpio_request,
3733         .direction_output       = wm8962_gpio_direction_out,
3734         .set                    = wm8962_gpio_set,
3735         .can_sleep              = 1,
3736 };
3737
3738 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3739 {
3740         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3741         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3742         int ret;
3743
3744         wm8962->gpio_chip = wm8962_template_chip;
3745         wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3746         wm8962->gpio_chip.dev = codec->dev;
3747
3748         if (pdata && pdata->gpio_base)
3749                 wm8962->gpio_chip.base = pdata->gpio_base;
3750         else
3751                 wm8962->gpio_chip.base = -1;
3752
3753         ret = gpiochip_add(&wm8962->gpio_chip);
3754         if (ret != 0)
3755                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3756 }
3757
3758 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3759 {
3760         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3761         int ret;
3762
3763         ret = gpiochip_remove(&wm8962->gpio_chip);
3764         if (ret != 0)
3765                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3766 }
3767 #else
3768 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3769 {
3770 }
3771
3772 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3773 {
3774 }
3775 #endif
3776
3777 static int wm8962_probe(struct snd_soc_codec *codec)
3778 {
3779         int ret;
3780         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3781         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3782         u16 *reg_cache = codec->reg_cache;
3783         int i, trigger, irq_pol;
3784         bool dmicclk, dmicdat;
3785
3786         wm8962->codec = codec;
3787         INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3788         init_completion(&wm8962->fll_lock);
3789
3790         codec->cache_sync = 1;
3791         codec->dapm.idle_bias_off = 1;
3792
3793         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
3794         if (ret != 0) {
3795                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3796                 goto err;
3797         }
3798
3799         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3800                 wm8962->supplies[i].supply = wm8962_supply_names[i];
3801
3802         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
3803                                  wm8962->supplies);
3804         if (ret != 0) {
3805                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
3806                 goto err;
3807         }
3808
3809         wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3810         wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3811         wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3812         wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3813         wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3814         wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3815         wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3816         wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3817
3818         /* This should really be moved into the regulator core */
3819         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3820                 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3821                                                   &wm8962->disable_nb[i]);
3822                 if (ret != 0) {
3823                         dev_err(codec->dev,
3824                                 "Failed to register regulator notifier: %d\n",
3825                                 ret);
3826                 }
3827         }
3828
3829         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3830                                     wm8962->supplies);
3831         if (ret != 0) {
3832                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
3833                 goto err_get;
3834         }
3835
3836         ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
3837         if (ret < 0) {
3838                 dev_err(codec->dev, "Failed to read ID register\n");
3839                 goto err_enable;
3840         }
3841         if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
3842                 dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
3843                         ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
3844                 ret = -EINVAL;
3845                 goto err_enable;
3846         }
3847
3848         ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
3849         if (ret < 0) {
3850                 dev_err(codec->dev, "Failed to read device revision: %d\n",
3851                         ret);
3852                 goto err_enable;
3853         }
3854
3855         dev_info(codec->dev, "customer id %x revision %c\n",
3856                  (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3857                  ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3858                  + 'A');
3859
3860         ret = wm8962_reset(codec);
3861         if (ret < 0) {
3862                 dev_err(codec->dev, "Failed to issue reset\n");
3863                 goto err_enable;
3864         }
3865
3866         /* SYSCLK defaults to on; make sure it is off so we can safely
3867          * write to registers if the device is declocked.
3868          */
3869         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3870
3871         /* Ensure we have soft control over all registers */
3872         snd_soc_update_bits(codec, WM8962_CLOCKING2,
3873                             WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3874
3875         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3876
3877         if (pdata) {
3878                 /* Apply static configuration for GPIOs */
3879                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
3880                         if (pdata->gpio_init[i]) {
3881                                 wm8962_set_gpio_mode(codec, i + 1);
3882                                 snd_soc_write(codec, 0x200 + i,
3883                                               pdata->gpio_init[i] & 0xffff);
3884                         }
3885
3886                 /* Put the speakers into mono mode? */
3887                 if (pdata->spk_mono)
3888                         reg_cache[WM8962_CLASS_D_CONTROL_2]
3889                                 |= WM8962_SPK_MONO;
3890
3891                 /* Micbias setup, detection enable and detection
3892                  * threasholds. */
3893                 if (pdata->mic_cfg)
3894                         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3895                                             WM8962_MICDET_ENA |
3896                                             WM8962_MICDET_THR_MASK |
3897                                             WM8962_MICSHORT_THR_MASK |
3898                                             WM8962_MICBIAS_LVL,
3899                                             pdata->mic_cfg);
3900         }
3901
3902         /* Latch volume update bits */
3903         snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3904                             WM8962_IN_VU, WM8962_IN_VU);
3905         snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3906                             WM8962_IN_VU, WM8962_IN_VU);
3907         snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3908                             WM8962_ADC_VU, WM8962_ADC_VU);
3909         snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3910                             WM8962_ADC_VU, WM8962_ADC_VU);
3911         snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3912                             WM8962_DAC_VU, WM8962_DAC_VU);
3913         snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3914                             WM8962_DAC_VU, WM8962_DAC_VU);
3915         snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3916                             WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3917         snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3918                             WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3919         snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3920                             WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3921         snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3922                             WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3923
3924         /* Stereo control for EQ */
3925         snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3926
3927         wm8962_add_widgets(codec);
3928
3929         /* Save boards having to disable DMIC when not in use */
3930         dmicclk = false;
3931         dmicdat = false;
3932         for (i = 0; i < WM8962_MAX_GPIO; i++) {
3933                 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3934                         & WM8962_GP2_FN_MASK) {
3935                 case WM8962_GPIO_FN_DMICCLK:
3936                         dmicclk = true;
3937                         break;
3938                 case WM8962_GPIO_FN_DMICDAT:
3939                         dmicdat = true;
3940                         break;
3941                 default:
3942                         break;
3943                 }
3944         }
3945         if (!dmicclk || !dmicdat) {
3946                 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3947                 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3948         }
3949         if (dmicclk != dmicdat)
3950                 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3951
3952         wm8962_init_beep(codec);
3953         wm8962_init_gpio(codec);
3954
3955         if (wm8962->irq) {
3956                 if (pdata && pdata->irq_active_low) {
3957                         trigger = IRQF_TRIGGER_LOW;
3958                         irq_pol = WM8962_IRQ_POL;
3959                 } else {
3960                         trigger = IRQF_TRIGGER_HIGH;
3961                         irq_pol = 0;
3962                 }
3963
3964                 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3965                                     WM8962_IRQ_POL, irq_pol);
3966
3967                 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
3968                                            trigger | IRQF_ONESHOT,
3969                                            "wm8962", codec);
3970                 if (ret != 0) {
3971                         dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
3972                                 wm8962->irq, ret);
3973                         wm8962->irq = 0;
3974                         /* Non-fatal */
3975                 } else {
3976                         /* Enable some IRQs by default */
3977                         snd_soc_update_bits(codec,
3978                                             WM8962_INTERRUPT_STATUS_2_MASK,
3979                                             WM8962_FLL_LOCK_EINT |
3980                                             WM8962_TEMP_SHUT_EINT |
3981                                             WM8962_FIFOS_ERR_EINT, 0);
3982                 }
3983         }
3984
3985         return 0;
3986
3987 err_enable:
3988         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3989 err_get:
3990         regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3991 err:
3992         return ret;
3993 }
3994
3995 static int wm8962_remove(struct snd_soc_codec *codec)
3996 {
3997         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3998         int i;
3999
4000         if (wm8962->irq)
4001                 free_irq(wm8962->irq, codec);
4002
4003         cancel_delayed_work_sync(&wm8962->mic_work);
4004
4005         wm8962_free_gpio(codec);
4006         wm8962_free_beep(codec);
4007         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
4008                 regulator_unregister_notifier(wm8962->supplies[i].consumer,
4009                                               &wm8962->disable_nb[i]);
4010         regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
4011
4012         return 0;
4013 }
4014
4015 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
4016         .probe =        wm8962_probe,
4017         .remove =       wm8962_remove,
4018         .resume =       wm8962_resume,
4019         .set_bias_level = wm8962_set_bias_level,
4020         .reg_cache_size = WM8962_MAX_REGISTER + 1,
4021         .reg_word_size = sizeof(u16),
4022         .reg_cache_default = wm8962_reg,
4023         .volatile_register = wm8962_volatile_register,
4024         .readable_register = wm8962_readable_register,
4025         .set_pll = wm8962_set_fll,
4026 };
4027
4028 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4029 static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
4030                                       const struct i2c_device_id *id)
4031 {
4032         struct wm8962_priv *wm8962;
4033         int ret;
4034
4035         wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
4036         if (wm8962 == NULL)
4037                 return -ENOMEM;
4038
4039         i2c_set_clientdata(i2c, wm8962);
4040
4041         wm8962->irq = i2c->irq;
4042
4043         ret = snd_soc_register_codec(&i2c->dev,
4044                                      &soc_codec_dev_wm8962, &wm8962_dai, 1);
4045         if (ret < 0)
4046                 kfree(wm8962);
4047
4048         return ret;
4049 }
4050
4051 static __devexit int wm8962_i2c_remove(struct i2c_client *client)
4052 {
4053         snd_soc_unregister_codec(&client->dev);
4054         kfree(i2c_get_clientdata(client));
4055         return 0;
4056 }
4057
4058 static const struct i2c_device_id wm8962_i2c_id[] = {
4059         { "wm8962", 0 },
4060         { }
4061 };
4062 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
4063
4064 static struct i2c_driver wm8962_i2c_driver = {
4065         .driver = {
4066                 .name = "wm8962",
4067                 .owner = THIS_MODULE,
4068         },
4069         .probe =    wm8962_i2c_probe,
4070         .remove =   __devexit_p(wm8962_i2c_remove),
4071         .id_table = wm8962_i2c_id,
4072 };
4073 #endif
4074
4075 static int __init wm8962_modinit(void)
4076 {
4077         int ret;
4078 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4079         ret = i2c_add_driver(&wm8962_i2c_driver);
4080         if (ret != 0) {
4081                 printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
4082                        ret);
4083         }
4084 #endif
4085         return 0;
4086 }
4087 module_init(wm8962_modinit);
4088
4089 static void __exit wm8962_exit(void)
4090 {
4091 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4092         i2c_del_driver(&wm8962_i2c_driver);
4093 #endif
4094 }
4095 module_exit(wm8962_exit);
4096
4097 MODULE_DESCRIPTION("ASoC WM8962 driver");
4098 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4099 MODULE_LICENSE("GPL");