sound/soc/codecs/wm8978.c

   1 /*
   2  * wm8978.c  --  WM8978 ALSA SoC Audio Codec driver
   3  *
   4  * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   5  * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
   6  * Copyright 2006-2009 Wolfson Microelectronics PLC.
   7  * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/pm.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30 #include <asm/div64.h>
  31
  32 #include "wm8978.h"
  33
  34 static struct snd_soc_codec *wm8978_codec;
  35
  36 /* wm8978 register cache. Note that register 0 is not included in the cache. */
  37 static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
  38         0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
  39         0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */
  40         0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */
  41         0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */
  42         0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */
  43         0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */
  44         0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */
  45         0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */
  46         0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */
  47         0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */
  48         0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */
  49         0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */
  50         0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */
  51         0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */
  52         0x0001, 0x0001,                 /* 0x38...0x3b */
  53 };
  54
  55 /* codec private data */
  56 struct wm8978_priv {
  57         struct snd_soc_codec codec;
  58         unsigned int f_pllout;
  59         unsigned int f_mclk;
  60         unsigned int f_256fs;
  61         unsigned int f_opclk;
  62         int mclk_idx;
  63         enum wm8978_sysclk_src sysclk;
  64         u16 reg_cache[WM8978_CACHEREGNUM];
  65 };
  66
  67 static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
  68 static const char *wm8978_eqmode[] = {"Capture", "Playback"};
  69 static const char *wm8978_bw[] = {"Narrow", "Wide"};
  70 static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
  71 static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
  72 static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
  73 static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
  74 static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
  75 static const char *wm8978_alc3[] = {"ALC", "Limiter"};
  76 static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
  77
  78 static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
  79                                   wm8978_companding);
  80 static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
  81                                   wm8978_companding);
  82 static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
  83 static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
  84 static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
  85 static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
  86 static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
  87 static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
  88 static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
  89 static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
  90 static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
  91 static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
  92 static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
  93
  94 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
  95 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  96 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
  97 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
  98 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
  99
 100 static const struct snd_kcontrol_new wm8978_snd_controls[] = {
 101
 102         SOC_SINGLE("Digital Loopback Switch",
 103                 WM8978_COMPANDING_CONTROL, 0, 1, 0),
 104
 105         SOC_ENUM("ADC Companding", adc_compand),
 106         SOC_ENUM("DAC Companding", dac_compand),
 107
 108         SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
 109
 110         SOC_DOUBLE_R_TLV("PCM Volume",
 111                 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
 112                 0, 255, 0, digital_tlv),
 113
 114         SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
 115         SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
 116         SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
 117
 118         SOC_DOUBLE_R_TLV("ADC Volume",
 119                 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
 120                 0, 255, 0, digital_tlv),
 121
 122         SOC_ENUM("Equaliser Function", eqmode),
 123         SOC_ENUM("EQ1 Cut Off", eq1),
 124         SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1,  0, 24, 1, eq_tlv),
 125
 126         SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw),
 127         SOC_ENUM("EQ2 Cut Off", eq2),
 128         SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2,  0, 24, 1, eq_tlv),
 129
 130         SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw),
 131         SOC_ENUM("EQ3 Cut Off", eq3),
 132         SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3,  0, 24, 1, eq_tlv),
 133
 134         SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw),
 135         SOC_ENUM("EQ4 Cut Off", eq4),
 136         SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4,  0, 24, 1, eq_tlv),
 137
 138         SOC_ENUM("EQ5 Cut Off", eq5),
 139         SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
 140
 141         SOC_SINGLE("DAC Playback Limiter Switch",
 142                 WM8978_DAC_LIMITER_1, 8, 1, 0),
 143         SOC_SINGLE("DAC Playback Limiter Decay",
 144                 WM8978_DAC_LIMITER_1, 4, 15, 0),
 145         SOC_SINGLE("DAC Playback Limiter Attack",
 146                 WM8978_DAC_LIMITER_1, 0, 15, 0),
 147
 148         SOC_SINGLE("DAC Playback Limiter Threshold",
 149                 WM8978_DAC_LIMITER_2, 4, 7, 0),
 150         SOC_SINGLE("DAC Playback Limiter Boost",
 151                 WM8978_DAC_LIMITER_2, 0, 15, 0),
 152
 153         SOC_ENUM("ALC Enable Switch", alc1),
 154         SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
 155         SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
 156
 157         SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 7, 0),
 158         SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
 159
 160         SOC_ENUM("ALC Capture Mode", alc3),
 161         SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 15, 0),
 162         SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 15, 0),
 163
 164         SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
 165         SOC_SINGLE("ALC Capture Noise Gate Threshold",
 166                 WM8978_NOISE_GATE, 0, 7, 0),
 167
 168         SOC_DOUBLE_R("Capture PGA ZC Switch",
 169                 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
 170                 7, 1, 0),
 171
 172         /* OUT1 - Headphones */
 173         SOC_DOUBLE_R("Headphone Playback ZC Switch",
 174                 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
 175
 176         SOC_DOUBLE_R_TLV("Headphone Playback Volume",
 177                 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
 178                 0, 63, 0, spk_tlv),
 179
 180         /* OUT2 - Speakers */
 181         SOC_DOUBLE_R("Speaker Playback ZC Switch",
 182                 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
 183
 184         SOC_DOUBLE_R_TLV("Speaker Playback Volume",
 185                 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
 186                 0, 63, 0, spk_tlv),
 187
 188         /* OUT3/4 - Line Output */
 189         SOC_DOUBLE_R("Line Playback Switch",
 190                 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
 191
 192         /* Mixer #3: Boost (Input) mixer */
 193         SOC_DOUBLE_R("PGA Boost (+20dB)",
 194                 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
 195                 8, 1, 0),
 196         SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
 197                 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
 198                 4, 7, 0, boost_tlv),
 199         SOC_DOUBLE_R_TLV("Aux Boost Volume",
 200                 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
 201                 0, 7, 0, boost_tlv),
 202
 203         /* Input PGA volume */
 204         SOC_DOUBLE_R_TLV("Input PGA Volume",
 205                 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
 206                 0, 63, 0, inpga_tlv),
 207
 208         /* Headphone */
 209         SOC_DOUBLE_R("Headphone Switch",
 210                 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
 211
 212         /* Speaker */
 213         SOC_DOUBLE_R("Speaker Switch",
 214                 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
 215
 216         /* DAC / ADC oversampling */
 217         SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0),
 218         SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0),
 219 };
 220
 221 /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
 222 static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
 223         SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
 224         SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
 225         SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
 226 };
 227
 228 static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
 229         SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
 230         SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
 231         SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
 232 };
 233
 234 /* OUT3/OUT4 Mixer not implemented */
 235
 236 /* Mixer #2: Input PGA Mute */
 237 static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
 238         SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
 239         SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
 240         SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
 241 };
 242 static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
 243         SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
 244         SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
 245         SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
 246 };
 247
 248 static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
 249         SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
 250                          WM8978_POWER_MANAGEMENT_3, 0, 0),
 251         SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
 252                          WM8978_POWER_MANAGEMENT_3, 1, 0),
 253         SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
 254                          WM8978_POWER_MANAGEMENT_2, 0, 0),
 255         SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
 256                          WM8978_POWER_MANAGEMENT_2, 1, 0),
 257
 258         /* Mixer #1: OUT1,2 */
 259         SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
 260                         2, 0, wm8978_left_out_mixer),
 261         SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
 262                         3, 0, wm8978_right_out_mixer),
 263
 264         SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
 265                         2, 0, wm8978_left_input_mixer),
 266         SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
 267                         3, 0, wm8978_right_input_mixer),
 268
 269         SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
 270                          4, 0, NULL, 0),
 271         SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
 272                          5, 0, NULL, 0),
 273
 274         SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
 275                          6, 1, NULL, 0),
 276         SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
 277                          6, 1, NULL, 0),
 278
 279         SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
 280                          7, 0, NULL, 0),
 281         SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
 282                          8, 0, NULL, 0),
 283
 284         SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
 285                          6, 0, NULL, 0),
 286         SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
 287                          5, 0, NULL, 0),
 288
 289         SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
 290                            8, 0, NULL, 0),
 291
 292         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
 293
 294         SND_SOC_DAPM_INPUT("LMICN"),
 295         SND_SOC_DAPM_INPUT("LMICP"),
 296         SND_SOC_DAPM_INPUT("RMICN"),
 297         SND_SOC_DAPM_INPUT("RMICP"),
 298         SND_SOC_DAPM_INPUT("LAUX"),
 299         SND_SOC_DAPM_INPUT("RAUX"),
 300         SND_SOC_DAPM_INPUT("L2"),
 301         SND_SOC_DAPM_INPUT("R2"),
 302         SND_SOC_DAPM_OUTPUT("LHP"),
 303         SND_SOC_DAPM_OUTPUT("RHP"),
 304         SND_SOC_DAPM_OUTPUT("LSPK"),
 305         SND_SOC_DAPM_OUTPUT("RSPK"),
 306 };
 307
 308 static const struct snd_soc_dapm_route audio_map[] = {
 309         /* Output mixer */
 310         {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
 311         {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
 312         {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
 313
 314         {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
 315         {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
 316         {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
 317
 318         /* Outputs */
 319         {"Right Headphone Out", NULL, "Right Output Mixer"},
 320         {"RHP", NULL, "Right Headphone Out"},
 321
 322         {"Left Headphone Out", NULL, "Left Output Mixer"},
 323         {"LHP", NULL, "Left Headphone Out"},
 324
 325         {"Right Speaker Out", NULL, "Right Output Mixer"},
 326         {"RSPK", NULL, "Right Speaker Out"},
 327
 328         {"Left Speaker Out", NULL, "Left Output Mixer"},
 329         {"LSPK", NULL, "Left Speaker Out"},
 330
 331         /* Boost Mixer */
 332         {"Right ADC", NULL, "Right Boost Mixer"},
 333
 334         {"Right Boost Mixer", NULL, "RAUX"},
 335         {"Right Boost Mixer", NULL, "Right Capture PGA"},
 336         {"Right Boost Mixer", NULL, "R2"},
 337
 338         {"Left ADC", NULL, "Left Boost Mixer"},
 339
 340         {"Left Boost Mixer", NULL, "LAUX"},
 341         {"Left Boost Mixer", NULL, "Left Capture PGA"},
 342         {"Left Boost Mixer", NULL, "L2"},
 343
 344         /* Input PGA */
 345         {"Right Capture PGA", NULL, "Right Input Mixer"},
 346         {"Left Capture PGA", NULL, "Left Input Mixer"},
 347
 348         {"Right Input Mixer", "R2 Switch", "R2"},
 349         {"Right Input Mixer", "MicN Switch", "RMICN"},
 350         {"Right Input Mixer", "MicP Switch", "RMICP"},
 351
 352         {"Left Input Mixer", "L2 Switch", "L2"},
 353         {"Left Input Mixer", "MicN Switch", "LMICN"},
 354         {"Left Input Mixer", "MicP Switch", "LMICP"},
 355 };
 356
 357 static int wm8978_add_widgets(struct snd_soc_codec *codec)
 358 {
 359         snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets,
 360                                   ARRAY_SIZE(wm8978_dapm_widgets));
 361
 362         /* set up the WM8978 audio map */
 363         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 364
 365         return 0;
 366 }
 367
 368 /* PLL divisors */
 369 struct wm8978_pll_div {
 370         u32 k;
 371         u8 n;
 372         u8 div2;
 373 };
 374
 375 #define FIXED_PLL_SIZE (1 << 24)
 376
 377 static void pll_factors(struct wm8978_pll_div *pll_div, unsigned int target,
 378                         unsigned int source)
 379 {
 380         u64 k_part;
 381         unsigned int k, n_div, n_mod;
 382
 383         n_div = target / source;
 384         if (n_div < 6) {
 385                 source >>= 1;
 386                 pll_div->div2 = 1;
 387                 n_div = target / source;
 388         } else {
 389                 pll_div->div2 = 0;
 390         }
 391
 392         if (n_div < 6 || n_div > 12)
 393                 dev_warn(wm8978_codec->dev,
 394                          "WM8978 N value exceeds recommended range! N = %u\n",
 395                          n_div);
 396
 397         pll_div->n = n_div;
 398         n_mod = target - source * n_div;
 399         k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
 400
 401         do_div(k_part, source);
 402
 403         k = k_part & 0xFFFFFFFF;
 404
 405         pll_div->k = k;
 406 }
 407
 408 /* MCLK dividers */
 409 static const int mclk_numerator[]       = {1, 3, 2, 3, 4, 6, 8, 12};
 410 static const int mclk_denominator[]     = {1, 2, 1, 1, 1, 1, 1, 1};
 411
 412 /*
 413  * find index >= idx, such that, for a given f_out,
 414  * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
 415  * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
 416  * generalised for f_opclk with suitable coefficient arrays, but currently
 417  * the OPCLK divisor is calculated directly, not iteratively.
 418  */
 419 static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
 420                             unsigned int *f_pllout)
 421 {
 422         int i;
 423
 424         for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
 425                 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
 426                         mclk_denominator[i];
 427                 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
 428                         *f_pllout = f_pllout_x4 / 4;
 429                         return i;
 430                 }
 431         }
 432
 433         return -EINVAL;
 434 }
 435
 436 /*
 437  * Calculate internal frequencies and dividers, according to Figure 40
 438  * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
 439  */
 440 static int wm8978_configure_pll(struct snd_soc_codec *codec)
 441 {
 442         struct wm8978_priv *wm8978 = codec->private_data;
 443         struct wm8978_pll_div pll_div;
 444         unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
 445                 f_256fs = wm8978->f_256fs;
 446         unsigned int f2;
 447
 448         if (!f_mclk)
 449                 return -EINVAL;
 450
 451         if (f_opclk) {
 452                 unsigned int opclk_div;
 453                 /* Cannot set up MCLK divider now, do later */
 454                 wm8978->mclk_idx = -1;
 455
 456                 /*
 457                  * The user needs OPCLK. Choose OPCLKDIV to put
 458                  * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
 459                  * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
 460                  * prescale = 1, or prescale = 2. Prescale is calculated inside
 461                  * pll_factors(). We have to select f_PLLOUT, such that
 462                  * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
 463                  * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
 464                  */
 465                 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
 466                         return -EINVAL;
 467
 468                 if (4 * f_opclk < 3 * f_mclk)
 469                         /* Have to use OPCLKDIV */
 470                         opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
 471                 else
 472                         opclk_div = 1;
 473
 474                 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
 475
 476                 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
 477                                     (opclk_div - 1) << 4);
 478
 479                 wm8978->f_pllout = f_opclk * opclk_div;
 480         } else if (f_256fs) {
 481                 /*
 482                  * Not using OPCLK, but PLL is used for the codec, choose R:
 483                  * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
 484                  * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
 485                  * prescale = 1, or prescale = 2. Prescale is calculated inside
 486                  * pll_factors(). We have to select f_PLLOUT, such that
 487                  * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
 488                  * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
 489                  * must be 3.781MHz <= f_MCLK <= 32.768MHz
 490                  */
 491                 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
 492                 if (idx < 0)
 493                         return idx;
 494
 495                 wm8978->mclk_idx = idx;
 496
 497                 /* GPIO1 into default mode as input - before configuring PLL */
 498                 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
 499         } else {
 500                 return -EINVAL;
 501         }
 502
 503         f2 = wm8978->f_pllout * 4;
 504
 505         dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
 506                 wm8978->f_mclk, wm8978->f_pllout);
 507
 508         pll_factors(&pll_div, f2, wm8978->f_mclk);
 509
 510         dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
 511                 __func__, pll_div.n, pll_div.k, pll_div.div2);
 512
 513         /* Turn PLL off for configuration... */
 514         snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
 515
 516         snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
 517         snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
 518         snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
 519         snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
 520
 521         /* ...and on again */
 522         snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
 523
 524         if (f_opclk)
 525                 /* Output PLL (OPCLK) to GPIO1 */
 526                 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
 527
 528         return 0;
 529 }
 530
 531 /*
 532  * Configure WM8978 clock dividers.
 533  */
 534 static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 535                                  int div_id, int div)
 536 {
 537         struct snd_soc_codec *codec = codec_dai->codec;
 538         struct wm8978_priv *wm8978 = codec->private_data;
 539         int ret = 0;
 540
 541         switch (div_id) {
 542         case WM8978_OPCLKRATE:
 543                 wm8978->f_opclk = div;
 544
 545                 if (wm8978->f_mclk)
 546                         /*
 547                          * We know the MCLK frequency, the user has requested
 548                          * OPCLK, configure the PLL based on that and start it
 549                          * and OPCLK immediately. We will configure PLL to match
 550                          * user-requested OPCLK frquency as good as possible.
 551                          * In fact, it is likely, that matching the sampling
 552                          * rate, when it becomes known, is more important, and
 553                          * we will not be reconfiguring PLL then, because we
 554                          * must not interrupt OPCLK. But it should be fine,
 555                          * because typically the user will request OPCLK to run
 556                          * at 256fs or 512fs, and for these cases we will also
 557                          * find an exact MCLK divider configuration - it will
 558                          * be equal to or double the OPCLK divisor.
 559                          */
 560                         ret = wm8978_configure_pll(codec);
 561                 break;
 562         case WM8978_BCLKDIV:
 563                 if (div & ~0x1c)
 564                         return -EINVAL;
 565                 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
 566                 break;
 567         default:
 568                 return -EINVAL;
 569         }
 570
 571         dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
 572
 573         return ret;
 574 }
 575
 576 /*
 577  * @freq:       when .set_pll() us not used, freq is codec MCLK input frequency
 578  */
 579 static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
 580                                  unsigned int freq, int dir)
 581 {
 582         struct snd_soc_codec *codec = codec_dai->codec;
 583         struct wm8978_priv *wm8978 = codec->private_data;
 584         int ret = 0;
 585
 586         dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
 587
 588         if (freq) {
 589                 wm8978->f_mclk = freq;
 590
 591                 /* Even if MCLK is used for system clock, might have to drive OPCLK */
 592                 if (wm8978->f_opclk)
 593                         ret = wm8978_configure_pll(codec);
 594
 595                 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params()  */
 596
 597                 if (!ret)
 598                         wm8978->sysclk = clk_id;
 599         }
 600
 601         if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
 602                 /* Clock CODEC directly from MCLK */
 603                 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
 604
 605                 /* GPIO1 into default mode as input - before configuring PLL */
 606                 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
 607
 608                 /* Turn off PLL */
 609                 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
 610                 wm8978->sysclk = WM8978_MCLK;
 611                 wm8978->f_pllout = 0;
 612                 wm8978->f_opclk = 0;
 613         }
 614
 615         return ret;
 616 }
 617
 618 /*
 619  * Set ADC and Voice DAC format.
 620  */
 621 static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 622 {
 623         struct snd_soc_codec *codec = codec_dai->codec;
 624         /*
 625          * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
 626          * Data Format mask = 0x18: all will be calculated anew
 627          */
 628         u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
 629         u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
 630
 631         dev_dbg(codec->dev, "%s\n", __func__);
 632
 633         /* set master/slave audio interface */
 634         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 635         case SND_SOC_DAIFMT_CBM_CFM:
 636                 clk |= 1;
 637                 break;
 638         case SND_SOC_DAIFMT_CBS_CFS:
 639                 clk &= ~1;
 640                 break;
 641         default:
 642                 return -EINVAL;
 643         }
 644
 645         /* interface format */
 646         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 647         case SND_SOC_DAIFMT_I2S:
 648                 iface |= 0x10;
 649                 break;
 650         case SND_SOC_DAIFMT_RIGHT_J:
 651                 break;
 652         case SND_SOC_DAIFMT_LEFT_J:
 653                 iface |= 0x8;
 654                 break;
 655         case SND_SOC_DAIFMT_DSP_A:
 656                 iface |= 0x18;
 657                 break;
 658         default:
 659                 return -EINVAL;
 660         }
 661
 662         /* clock inversion */
 663         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 664         case SND_SOC_DAIFMT_NB_NF:
 665                 break;
 666         case SND_SOC_DAIFMT_IB_IF:
 667                 iface |= 0x180;
 668                 break;
 669         case SND_SOC_DAIFMT_IB_NF:
 670                 iface |= 0x100;
 671                 break;
 672         case SND_SOC_DAIFMT_NB_IF:
 673                 iface |= 0x80;
 674                 break;
 675         default:
 676                 return -EINVAL;
 677         }
 678
 679         snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
 680         snd_soc_write(codec, WM8978_CLOCKING, clk);
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * Set PCM DAI bit size and sample rate.
 687  */
 688 static int wm8978_hw_params(struct snd_pcm_substream *substream,
 689                             struct snd_pcm_hw_params *params,
 690                             struct snd_soc_dai *dai)
 691 {
 692         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 693         struct snd_soc_device *socdev = rtd->socdev;
 694         struct snd_soc_codec *codec = socdev->card->codec;
 695         struct wm8978_priv *wm8978 = codec->private_data;
 696         /* Word length mask = 0x60 */
 697         u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
 698         /* Sampling rate mask = 0xe (for filters) */
 699         u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
 700         u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
 701         enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
 702                 WM8978_PLL : WM8978_MCLK;
 703         unsigned int f_sel, diff, diff_best = INT_MAX;
 704         int i, best = 0;
 705
 706         if (!wm8978->f_mclk)
 707                 return -EINVAL;
 708
 709         /* bit size */
 710         switch (params_format(params)) {
 711         case SNDRV_PCM_FORMAT_S16_LE:
 712                 break;
 713         case SNDRV_PCM_FORMAT_S20_3LE:
 714                 iface_ctl |= 0x20;
 715                 break;
 716         case SNDRV_PCM_FORMAT_S24_LE:
 717                 iface_ctl |= 0x40;
 718                 break;
 719         case SNDRV_PCM_FORMAT_S32_LE:
 720                 iface_ctl |= 0x60;
 721                 break;
 722         }
 723
 724         /* filter coefficient */
 725         switch (params_rate(params)) {
 726         case 8000:
 727                 add_ctl |= 0x5 << 1;
 728                 break;
 729         case 11025:
 730                 add_ctl |= 0x4 << 1;
 731                 break;
 732         case 16000:
 733                 add_ctl |= 0x3 << 1;
 734                 break;
 735         case 22050:
 736                 add_ctl |= 0x2 << 1;
 737                 break;
 738         case 32000:
 739                 add_ctl |= 0x1 << 1;
 740                 break;
 741         case 44100:
 742         case 48000:
 743                 break;
 744         }
 745
 746         /* Sampling rate is known now, can configure the MCLK divider */
 747         wm8978->f_256fs = params_rate(params) * 256;
 748
 749         if (wm8978->sysclk == WM8978_MCLK) {
 750                 wm8978->mclk_idx = -1;
 751                 f_sel = wm8978->f_mclk;
 752         } else {
 753                 if (!wm8978->f_pllout) {
 754                         /* We only enter here, if OPCLK is not used */
 755                         int ret = wm8978_configure_pll(codec);
 756                         if (ret < 0)
 757                                 return ret;
 758                 }
 759                 f_sel = wm8978->f_pllout;
 760         }
 761
 762         if (wm8978->mclk_idx < 0) {
 763                 /* Either MCLK is used directly, or OPCLK is used */
 764                 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
 765                         return -EINVAL;
 766
 767                 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
 768                         diff = abs(wm8978->f_256fs * 3 -
 769                                    f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
 770
 771                         if (diff < diff_best) {
 772                                 diff_best = diff;
 773                                 best = i;
 774                         }
 775
 776                         if (!diff)
 777                                 break;
 778                 }
 779         } else {
 780                 /* OPCLK not used, codec driven by PLL */
 781                 best = wm8978->mclk_idx;
 782                 diff = 0;
 783         }
 784
 785         if (diff)
 786                 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
 787                         f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
 788                         wm8978->sysclk == WM8978_MCLK ?
 789                         ", consider using PLL" : "");
 790
 791         dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__,
 792                 params_format(params), params_rate(params), best);
 793
 794         /* MCLK divisor mask = 0xe0 */
 795         snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
 796
 797         snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
 798         snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
 799
 800         if (wm8978->sysclk != current_clk_id) {
 801                 if (wm8978->sysclk == WM8978_PLL)
 802                         /* Run CODEC from PLL instead of MCLK */
 803                         snd_soc_update_bits(codec, WM8978_CLOCKING,
 804                                             0x100, 0x100);
 805                 else
 806                         /* Clock CODEC directly from MCLK */
 807                         snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int wm8978_mute(struct snd_soc_dai *dai, int mute)
 814 {
 815         struct snd_soc_codec *codec = dai->codec;
 816
 817         dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
 818
 819         if (mute)
 820                 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
 821         else
 822                 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
 823
 824         return 0;
 825 }
 826
 827 static int wm8978_set_bias_level(struct snd_soc_codec *codec,
 828                                  enum snd_soc_bias_level level)
 829 {
 830         u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
 831
 832         switch (level) {
 833         case SND_SOC_BIAS_ON:
 834         case SND_SOC_BIAS_PREPARE:
 835                 power1 |= 1;  /* VMID 75k */
 836                 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
 837                 break;
 838         case SND_SOC_BIAS_STANDBY:
 839                 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
 840                 power1 |= 0xc;
 841
 842                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 843                         /* Initial cap charge at VMID 5k */
 844                         snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
 845                                       power1 | 0x3);
 846                         mdelay(100);
 847                 }
 848
 849                 power1 |= 0x2;  /* VMID 500k */
 850                 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
 851                 break;
 852         case SND_SOC_BIAS_OFF:
 853                 /* Preserve PLL - OPCLK may be used by someone */
 854                 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
 855                 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
 856                 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
 857                 break;
 858         }
 859
 860         dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
 861
 862         codec->bias_level = level;
 863         return 0;
 864 }
 865
 866 #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 867         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 868
 869 static struct snd_soc_dai_ops wm8978_dai_ops = {
 870         .hw_params      = wm8978_hw_params,
 871         .digital_mute   = wm8978_mute,
 872         .set_fmt        = wm8978_set_dai_fmt,
 873         .set_clkdiv     = wm8978_set_dai_clkdiv,
 874         .set_sysclk     = wm8978_set_dai_sysclk,
 875 };
 876
 877 /* Also supports 12kHz */
 878 struct snd_soc_dai wm8978_dai = {
 879         .name = "WM8978 HiFi",
 880         .id = 1,
 881         .playback = {
 882                 .stream_name = "Playback",
 883                 .channels_min = 1,
 884                 .channels_max = 2,
 885                 .rates = SNDRV_PCM_RATE_8000_48000,
 886                 .formats = WM8978_FORMATS,
 887         },
 888         .capture = {
 889                 .stream_name = "Capture",
 890                 .channels_min = 1,
 891                 .channels_max = 2,
 892                 .rates = SNDRV_PCM_RATE_8000_48000,
 893                 .formats = WM8978_FORMATS,
 894         },
 895         .ops = &wm8978_dai_ops,
 896 };
 897 EXPORT_SYMBOL_GPL(wm8978_dai);
 898
 899 static int wm8978_suspend(struct platform_device *pdev, pm_message_t state)
 900 {
 901         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 902         struct snd_soc_codec *codec = socdev->card->codec;
 903
 904         wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
 905         /* Also switch PLL off */
 906         snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
 907
 908         return 0;
 909 }
 910
 911 static int wm8978_resume(struct platform_device *pdev)
 912 {
 913         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 914         struct snd_soc_codec *codec = socdev->card->codec;
 915         struct wm8978_priv *wm8978 = codec->private_data;
 916         int i;
 917         u16 *cache = codec->reg_cache;
 918
 919         /* Sync reg_cache with the hardware */
 920         for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) {
 921                 if (i == WM8978_RESET)
 922                         continue;
 923                 if (cache[i] != wm8978_reg[i])
 924                         snd_soc_write(codec, i, cache[i]);
 925         }
 926
 927         wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 928
 929         if (wm8978->f_pllout)
 930                 /* Switch PLL on */
 931                 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
 932
 933         return 0;
 934 }
 935
 936 static int wm8978_probe(struct platform_device *pdev)
 937 {
 938         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 939         struct snd_soc_codec *codec;
 940         int ret = 0;
 941
 942         if (wm8978_codec == NULL) {
 943                 dev_err(&pdev->dev, "Codec device not registered\n");
 944                 return -ENODEV;
 945         }
 946
 947         socdev->card->codec = wm8978_codec;
 948         codec = wm8978_codec;
 949
 950         /* register pcms */
 951         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
 952         if (ret < 0) {
 953                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
 954                 goto pcm_err;
 955         }
 956
 957         snd_soc_add_controls(codec, wm8978_snd_controls,
 958                              ARRAY_SIZE(wm8978_snd_controls));
 959         wm8978_add_widgets(codec);
 960
 961 pcm_err:
 962         return ret;
 963 }
 964
 965 /* power down chip */
 966 static int wm8978_remove(struct platform_device *pdev)
 967 {
 968         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 969
 970         snd_soc_free_pcms(socdev);
 971         snd_soc_dapm_free(socdev);
 972
 973         return 0;
 974 }
 975
 976 struct snd_soc_codec_device soc_codec_dev_wm8978 = {
 977         .probe          = wm8978_probe,
 978         .remove         = wm8978_remove,
 979         .suspend        = wm8978_suspend,
 980         .resume         = wm8978_resume,
 981 };
 982 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8978);
 983
 984 /*
 985  * These registers contain an "update" bit - bit 8. This means, for example,
 986  * that one can write new DAC digital volume for both channels, but only when
 987  * the update bit is set, will also the volume be updated - simultaneously for
 988  * both channels.
 989  */
 990 static const int update_reg[] = {
 991         WM8978_LEFT_DAC_DIGITAL_VOLUME,
 992         WM8978_RIGHT_DAC_DIGITAL_VOLUME,
 993         WM8978_LEFT_ADC_DIGITAL_VOLUME,
 994         WM8978_RIGHT_ADC_DIGITAL_VOLUME,
 995         WM8978_LEFT_INP_PGA_CONTROL,
 996         WM8978_RIGHT_INP_PGA_CONTROL,
 997         WM8978_LOUT1_HP_CONTROL,
 998         WM8978_ROUT1_HP_CONTROL,
 999         WM8978_LOUT2_SPK_CONTROL,
1000         WM8978_ROUT2_SPK_CONTROL,
1001 };
1002
1003 static __devinit int wm8978_register(struct wm8978_priv *wm8978)
1004 {
1005         int ret, i;
1006         struct snd_soc_codec *codec = &wm8978->codec;
1007
1008         if (wm8978_codec) {
1009                 dev_err(codec->dev, "Another WM8978 is registered\n");
1010                 return -EINVAL;
1011         }
1012
1013         /*
1014          * Set default system clock to PLL, it is more precise, this is also the
1015          * default hardware setting
1016          */
1017         wm8978->sysclk = WM8978_PLL;
1018
1019         mutex_init(&codec->mutex);
1020         INIT_LIST_HEAD(&codec->dapm_widgets);
1021         INIT_LIST_HEAD(&codec->dapm_paths);
1022
1023         codec->private_data = wm8978;
1024         codec->name = "WM8978";
1025         codec->owner = THIS_MODULE;
1026         codec->bias_level = SND_SOC_BIAS_OFF;
1027         codec->set_bias_level = wm8978_set_bias_level;
1028         codec->dai = &wm8978_dai;
1029         codec->num_dai = 1;
1030         codec->reg_cache_size = WM8978_CACHEREGNUM;
1031         codec->reg_cache = &wm8978->reg_cache;
1032
1033         ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
1034         if (ret < 0) {
1035                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1036                 goto err;
1037         }
1038
1039         memcpy(codec->reg_cache, wm8978_reg, sizeof(wm8978_reg));
1040
1041         /*
1042          * Set the update bit in all registers, that have one. This way all
1043          * writes to those registers will also cause the update bit to be
1044          * written.
1045          */
1046         for (i = 0; i < ARRAY_SIZE(update_reg); i++)
1047                 ((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100;
1048
1049         /* Reset the codec */
1050         ret = snd_soc_write(codec, WM8978_RESET, 0);
1051         if (ret < 0) {
1052                 dev_err(codec->dev, "Failed to issue reset\n");
1053                 goto err;
1054         }
1055
1056         wm8978_dai.dev = codec->dev;
1057
1058         wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1059
1060         wm8978_codec = codec;
1061
1062         ret = snd_soc_register_codec(codec);
1063         if (ret != 0) {
1064                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1065                 goto err;
1066         }
1067
1068         ret = snd_soc_register_dai(&wm8978_dai);
1069         if (ret != 0) {
1070                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1071                 goto err_codec;
1072         }
1073
1074         return 0;
1075
1076 err_codec:
1077         snd_soc_unregister_codec(codec);
1078 err:
1079         kfree(wm8978);
1080         return ret;
1081 }
1082
1083 static __devexit void wm8978_unregister(struct wm8978_priv *wm8978)
1084 {
1085         wm8978_set_bias_level(&wm8978->codec, SND_SOC_BIAS_OFF);
1086         snd_soc_unregister_dai(&wm8978_dai);
1087         snd_soc_unregister_codec(&wm8978->codec);
1088         kfree(wm8978);
1089         wm8978_codec = NULL;
1090 }
1091
1092 static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
1093                                       const struct i2c_device_id *id)
1094 {
1095         struct wm8978_priv *wm8978;
1096         struct snd_soc_codec *codec;
1097
1098         wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL);
1099         if (wm8978 == NULL)
1100                 return -ENOMEM;
1101
1102         codec = &wm8978->codec;
1103         codec->hw_write = (hw_write_t)i2c_master_send;
1104
1105         i2c_set_clientdata(i2c, wm8978);
1106         codec->control_data = i2c;
1107
1108         codec->dev = &i2c->dev;
1109
1110         return wm8978_register(wm8978);
1111 }
1112
1113 static __devexit int wm8978_i2c_remove(struct i2c_client *client)
1114 {
1115         struct wm8978_priv *wm8978 = i2c_get_clientdata(client);
1116         wm8978_unregister(wm8978);
1117         return 0;
1118 }
1119
1120 static const struct i2c_device_id wm8978_i2c_id[] = {
1121         { "wm8978", 0 },
1122         { }
1123 };
1124 MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
1125
1126 static struct i2c_driver wm8978_i2c_driver = {
1127         .driver = {
1128                 .name = "WM8978",
1129                 .owner = THIS_MODULE,
1130         },
1131         .probe =    wm8978_i2c_probe,
1132         .remove =   __devexit_p(wm8978_i2c_remove),
1133         .id_table = wm8978_i2c_id,
1134 };
1135
1136 static int __init wm8978_modinit(void)
1137 {
1138         return i2c_add_driver(&wm8978_i2c_driver);
1139 }
1140 module_init(wm8978_modinit);
1141
1142 static void __exit wm8978_exit(void)
1143 {
1144         i2c_del_driver(&wm8978_i2c_driver);
1145 }
1146 module_exit(wm8978_exit);
1147
1148 MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1149 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1150 MODULE_LICENSE("GPL");