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ASoC: wm8994: Actively discharge VMID when not in use
[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
48
49 static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
82 const struct wm8958_micd_rate *rates;
83 int num_rates;
84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
107 best = 0;
108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
110 continue;
111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
113 best = i;
114 else if (rates[best].idle != idle)
115 best = i;
116 }
117
118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124 }
125
126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127 {
128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
169
170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177 }
178
179 static int configure_clock(struct snd_soc_codec *codec)
180 {
181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
182 int change, new;
183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
197 return 0;
198 }
199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
209
210 wm8958_micd_set_rate(codec);
211
212 return 0;
213 }
214
215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217 {
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228 }
229
230 static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232 };
233
234 static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
237 static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239 };
240
241 static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244 static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247 static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
257
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266 {
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286 }
287
288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289 {
290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308 }
309
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name)
312 {
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320 }
321
322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324 {
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342 }
343
344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346 {
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354 }
355
356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357 {
358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411 }
412
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name)
415 {
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423 }
424
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445 }
446
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449 {
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457 }
458
459 static const char *aif_chan_src_text[] = {
460 "Left", "Right"
461 };
462
463 static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466 static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469 static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472 static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
475 static const struct soc_enum aif1dacl_src =
476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
477
478 static const struct soc_enum aif1dacr_src =
479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
480
481 static const struct soc_enum aif2dacl_src =
482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
483
484 static const struct soc_enum aif2dacr_src =
485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
486
487 static const char *osr_text[] = {
488 "Low Power", "High Performance",
489 };
490
491 static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494 static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
512
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
517
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
564 SOC_ENUM("ADC OSR", adc_osr),
565 SOC_ENUM("DAC OSR", dac_osr),
566
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
590 8, 1, 0),
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
596 10, 15, 0, wm8994_3d_tlv),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
598 8, 1, 0),
599 };
600
601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634 };
635
636 static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638 };
639
640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648 static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
654
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
675 };
676
677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682 };
683
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686 {
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (wm8994->active_refcount)
690 mode = WM1811_JACKDET_MODE_AUDIO;
691
692 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
693 WM1811_JACKDET_MODE_MASK, mode);
694
695 if (mode == WM1811_JACKDET_MODE_MIC)
696 msleep(2);
697 }
698
699 static void active_reference(struct snd_soc_codec *codec)
700 {
701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702
703 mutex_lock(&wm8994->accdet_lock);
704
705 wm8994->active_refcount++;
706
707 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
708 wm8994->active_refcount);
709
710 if (wm8994->active_refcount == 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994->jackdet && wm8994->jack_cb) {
713 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
714 WM1811_JACKDET_MODE_MASK,
715 WM1811_JACKDET_MODE_AUDIO);
716 msleep(2);
717 }
718 }
719
720 mutex_unlock(&wm8994->accdet_lock);
721 }
722
723 static void active_dereference(struct snd_soc_codec *codec)
724 {
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726 u16 mode;
727
728 mutex_lock(&wm8994->accdet_lock);
729
730 wm8994->active_refcount--;
731
732 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
733 wm8994->active_refcount);
734
735 if (wm8994->active_refcount == 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994->jackdet && wm8994->jack_cb) {
738 if (wm8994->jack_mic || wm8994->mic_detecting)
739 mode = WM1811_JACKDET_MODE_MIC;
740 else
741 mode = WM1811_JACKDET_MODE_JACK;
742
743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
744 WM1811_JACKDET_MODE_MASK,
745 mode);
746 }
747 }
748
749 mutex_unlock(&wm8994->accdet_lock);
750 }
751
752 static int clk_sys_event(struct snd_soc_dapm_widget *w,
753 struct snd_kcontrol *kcontrol, int event)
754 {
755 struct snd_soc_codec *codec = w->codec;
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 return configure_clock(codec);
760
761 case SND_SOC_DAPM_POST_PMD:
762 configure_clock(codec);
763 break;
764 }
765
766 return 0;
767 }
768
769 static void vmid_reference(struct snd_soc_codec *codec)
770 {
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
773 pm_runtime_get_sync(codec->dev);
774
775 wm8994->vmid_refcount++;
776
777 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
778 wm8994->vmid_refcount);
779
780 if (wm8994->vmid_refcount == 1) {
781 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
782 WM8994_LINEOUT_VMID_BUF_ENA |
783 WM8994_LINEOUT1_DISCH |
784 WM8994_LINEOUT2_DISCH,
785 WM8994_LINEOUT_VMID_BUF_ENA);
786
787 /* Startup bias, VMID ramp & buffer */
788 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
789 WM8994_BIAS_SRC |
790 WM8994_VMID_DISCH |
791 WM8994_STARTUP_BIAS_ENA |
792 WM8994_VMID_BUF_ENA |
793 WM8994_VMID_RAMP_MASK,
794 WM8994_BIAS_SRC |
795 WM8994_STARTUP_BIAS_ENA |
796 WM8994_VMID_BUF_ENA |
797 (0x3 << WM8994_VMID_RAMP_SHIFT));
798
799 wm_hubs_vmid_ena(codec);
800
801 /* Main bias enable, VMID=2x40k */
802 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803 WM8994_BIAS_ENA |
804 WM8994_VMID_SEL_MASK,
805 WM8994_BIAS_ENA | 0x2);
806
807 msleep(50);
808
809 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810 WM8994_VMID_RAMP_MASK | WM8994_BIAS_SRC,
811 0);
812 }
813 }
814
815 static void vmid_dereference(struct snd_soc_codec *codec)
816 {
817 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
818
819 wm8994->vmid_refcount--;
820
821 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
822 wm8994->vmid_refcount);
823
824 if (wm8994->vmid_refcount == 0) {
825 /* Switch over to startup biases */
826 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
827 WM8994_BIAS_SRC |
828 WM8994_STARTUP_BIAS_ENA |
829 WM8994_VMID_BUF_ENA |
830 WM8994_VMID_RAMP_MASK,
831 WM8994_BIAS_SRC |
832 WM8994_STARTUP_BIAS_ENA |
833 WM8994_VMID_BUF_ENA |
834 (1 << WM8994_VMID_RAMP_SHIFT));
835
836 /* Disable main biases */
837 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
838 WM8994_BIAS_ENA |
839 WM8994_VMID_SEL_MASK, 0);
840
841 /* Discharge VMID */
842 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
843 WM8994_VMID_DISCH, WM8994_VMID_DISCH);
844
845 /* Discharge line */
846 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
847 WM8994_LINEOUT1_DISCH |
848 WM8994_LINEOUT2_DISCH,
849 WM8994_LINEOUT1_DISCH |
850 WM8994_LINEOUT2_DISCH);
851
852 msleep(5);
853
854 /* Switch off startup biases */
855 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
856 WM8994_BIAS_SRC |
857 WM8994_STARTUP_BIAS_ENA |
858 WM8994_VMID_BUF_ENA |
859 WM8994_VMID_RAMP_MASK, 0);
860 }
861
862 pm_runtime_put(codec->dev);
863 }
864
865 static int vmid_event(struct snd_soc_dapm_widget *w,
866 struct snd_kcontrol *kcontrol, int event)
867 {
868 struct snd_soc_codec *codec = w->codec;
869
870 switch (event) {
871 case SND_SOC_DAPM_PRE_PMU:
872 vmid_reference(codec);
873 break;
874
875 case SND_SOC_DAPM_POST_PMD:
876 vmid_dereference(codec);
877 break;
878 }
879
880 return 0;
881 }
882
883 static void wm8994_update_class_w(struct snd_soc_codec *codec)
884 {
885 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
886 int enable = 1;
887 int source = 0; /* GCC flow analysis can't track enable */
888 int reg, reg_r;
889
890 /* Only support direct DAC->headphone paths */
891 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
892 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
893 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
894 enable = 0;
895 }
896
897 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
898 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
899 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
900 enable = 0;
901 }
902
903 /* We also need the same setting for L/R and only one path */
904 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
905 switch (reg) {
906 case WM8994_AIF2DACL_TO_DAC1L:
907 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
908 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
909 break;
910 case WM8994_AIF1DAC2L_TO_DAC1L:
911 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
912 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
913 break;
914 case WM8994_AIF1DAC1L_TO_DAC1L:
915 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
916 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
917 break;
918 default:
919 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
920 enable = 0;
921 break;
922 }
923
924 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
925 if (reg_r != reg) {
926 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
927 enable = 0;
928 }
929
930 if (enable) {
931 dev_dbg(codec->dev, "Class W enabled\n");
932 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
933 WM8994_CP_DYN_PWR |
934 WM8994_CP_DYN_SRC_SEL_MASK,
935 source | WM8994_CP_DYN_PWR);
936 wm8994->hubs.class_w = true;
937
938 } else {
939 dev_dbg(codec->dev, "Class W disabled\n");
940 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
941 WM8994_CP_DYN_PWR, 0);
942 wm8994->hubs.class_w = false;
943 }
944 }
945
946 static int late_enable_ev(struct snd_soc_dapm_widget *w,
947 struct snd_kcontrol *kcontrol, int event)
948 {
949 struct snd_soc_codec *codec = w->codec;
950 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
951
952 switch (event) {
953 case SND_SOC_DAPM_PRE_PMU:
954 if (wm8994->aif1clk_enable) {
955 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
956 WM8994_AIF1CLK_ENA_MASK,
957 WM8994_AIF1CLK_ENA);
958 wm8994->aif1clk_enable = 0;
959 }
960 if (wm8994->aif2clk_enable) {
961 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
962 WM8994_AIF2CLK_ENA_MASK,
963 WM8994_AIF2CLK_ENA);
964 wm8994->aif2clk_enable = 0;
965 }
966 break;
967 }
968
969 /* We may also have postponed startup of DSP, handle that. */
970 wm8958_aif_ev(w, kcontrol, event);
971
972 return 0;
973 }
974
975 static int late_disable_ev(struct snd_soc_dapm_widget *w,
976 struct snd_kcontrol *kcontrol, int event)
977 {
978 struct snd_soc_codec *codec = w->codec;
979 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
980
981 switch (event) {
982 case SND_SOC_DAPM_POST_PMD:
983 if (wm8994->aif1clk_disable) {
984 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
985 WM8994_AIF1CLK_ENA_MASK, 0);
986 wm8994->aif1clk_disable = 0;
987 }
988 if (wm8994->aif2clk_disable) {
989 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
990 WM8994_AIF2CLK_ENA_MASK, 0);
991 wm8994->aif2clk_disable = 0;
992 }
993 break;
994 }
995
996 return 0;
997 }
998
999 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1000 struct snd_kcontrol *kcontrol, int event)
1001 {
1002 struct snd_soc_codec *codec = w->codec;
1003 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1004
1005 switch (event) {
1006 case SND_SOC_DAPM_PRE_PMU:
1007 wm8994->aif1clk_enable = 1;
1008 break;
1009 case SND_SOC_DAPM_POST_PMD:
1010 wm8994->aif1clk_disable = 1;
1011 break;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1018 struct snd_kcontrol *kcontrol, int event)
1019 {
1020 struct snd_soc_codec *codec = w->codec;
1021 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1022
1023 switch (event) {
1024 case SND_SOC_DAPM_PRE_PMU:
1025 wm8994->aif2clk_enable = 1;
1026 break;
1027 case SND_SOC_DAPM_POST_PMD:
1028 wm8994->aif2clk_disable = 1;
1029 break;
1030 }
1031
1032 return 0;
1033 }
1034
1035 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *kcontrol, int event)
1037 {
1038 late_enable_ev(w, kcontrol, event);
1039 return 0;
1040 }
1041
1042 static int micbias_ev(struct snd_soc_dapm_widget *w,
1043 struct snd_kcontrol *kcontrol, int event)
1044 {
1045 late_enable_ev(w, kcontrol, event);
1046 return 0;
1047 }
1048
1049 static int dac_ev(struct snd_soc_dapm_widget *w,
1050 struct snd_kcontrol *kcontrol, int event)
1051 {
1052 struct snd_soc_codec *codec = w->codec;
1053 unsigned int mask = 1 << w->shift;
1054
1055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1056 mask, mask);
1057 return 0;
1058 }
1059
1060 static const char *hp_mux_text[] = {
1061 "Mixer",
1062 "DAC",
1063 };
1064
1065 #define WM8994_HP_ENUM(xname, xenum) \
1066 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1067 .info = snd_soc_info_enum_double, \
1068 .get = snd_soc_dapm_get_enum_double, \
1069 .put = wm8994_put_hp_enum, \
1070 .private_value = (unsigned long)&xenum }
1071
1072 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1073 struct snd_ctl_elem_value *ucontrol)
1074 {
1075 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1076 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1077 struct snd_soc_codec *codec = w->codec;
1078 int ret;
1079
1080 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1081
1082 wm8994_update_class_w(codec);
1083
1084 return ret;
1085 }
1086
1087 static const struct soc_enum hpl_enum =
1088 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1089
1090 static const struct snd_kcontrol_new hpl_mux =
1091 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1092
1093 static const struct soc_enum hpr_enum =
1094 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1095
1096 static const struct snd_kcontrol_new hpr_mux =
1097 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1098
1099 static const char *adc_mux_text[] = {
1100 "ADC",
1101 "DMIC",
1102 };
1103
1104 static const struct soc_enum adc_enum =
1105 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1106
1107 static const struct snd_kcontrol_new adcl_mux =
1108 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1109
1110 static const struct snd_kcontrol_new adcr_mux =
1111 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1112
1113 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1114 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1115 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1116 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1117 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1118 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1119 };
1120
1121 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1122 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1123 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1124 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1125 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1126 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1127 };
1128
1129 /* Debugging; dump chip status after DAPM transitions */
1130 static int post_ev(struct snd_soc_dapm_widget *w,
1131 struct snd_kcontrol *kcontrol, int event)
1132 {
1133 struct snd_soc_codec *codec = w->codec;
1134 dev_dbg(codec->dev, "SRC status: %x\n",
1135 snd_soc_read(codec,
1136 WM8994_RATE_STATUS));
1137 return 0;
1138 }
1139
1140 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1141 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1142 1, 1, 0),
1143 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1144 0, 1, 0),
1145 };
1146
1147 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1148 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1149 1, 1, 0),
1150 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1151 0, 1, 0),
1152 };
1153
1154 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1155 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1156 1, 1, 0),
1157 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1158 0, 1, 0),
1159 };
1160
1161 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1162 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1163 1, 1, 0),
1164 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1165 0, 1, 0),
1166 };
1167
1168 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1169 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1170 5, 1, 0),
1171 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1172 4, 1, 0),
1173 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1174 2, 1, 0),
1175 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1176 1, 1, 0),
1177 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1178 0, 1, 0),
1179 };
1180
1181 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1182 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1183 5, 1, 0),
1184 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1185 4, 1, 0),
1186 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1187 2, 1, 0),
1188 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1189 1, 1, 0),
1190 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1191 0, 1, 0),
1192 };
1193
1194 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1195 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1196 .info = snd_soc_info_volsw, \
1197 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1198 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1199
1200 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1201 struct snd_ctl_elem_value *ucontrol)
1202 {
1203 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1204 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1205 struct snd_soc_codec *codec = w->codec;
1206 int ret;
1207
1208 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1209
1210 wm8994_update_class_w(codec);
1211
1212 return ret;
1213 }
1214
1215 static const struct snd_kcontrol_new dac1l_mix[] = {
1216 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1217 5, 1, 0),
1218 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1219 4, 1, 0),
1220 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1221 2, 1, 0),
1222 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1223 1, 1, 0),
1224 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1225 0, 1, 0),
1226 };
1227
1228 static const struct snd_kcontrol_new dac1r_mix[] = {
1229 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1230 5, 1, 0),
1231 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1232 4, 1, 0),
1233 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1234 2, 1, 0),
1235 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1236 1, 1, 0),
1237 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1238 0, 1, 0),
1239 };
1240
1241 static const char *sidetone_text[] = {
1242 "ADC/DMIC1", "DMIC2",
1243 };
1244
1245 static const struct soc_enum sidetone1_enum =
1246 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1247
1248 static const struct snd_kcontrol_new sidetone1_mux =
1249 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1250
1251 static const struct soc_enum sidetone2_enum =
1252 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1253
1254 static const struct snd_kcontrol_new sidetone2_mux =
1255 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1256
1257 static const char *aif1dac_text[] = {
1258 "AIF1DACDAT", "AIF3DACDAT",
1259 };
1260
1261 static const struct soc_enum aif1dac_enum =
1262 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1263
1264 static const struct snd_kcontrol_new aif1dac_mux =
1265 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1266
1267 static const char *aif2dac_text[] = {
1268 "AIF2DACDAT", "AIF3DACDAT",
1269 };
1270
1271 static const struct soc_enum aif2dac_enum =
1272 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1273
1274 static const struct snd_kcontrol_new aif2dac_mux =
1275 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1276
1277 static const char *aif2adc_text[] = {
1278 "AIF2ADCDAT", "AIF3DACDAT",
1279 };
1280
1281 static const struct soc_enum aif2adc_enum =
1282 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1283
1284 static const struct snd_kcontrol_new aif2adc_mux =
1285 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1286
1287 static const char *aif3adc_text[] = {
1288 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1289 };
1290
1291 static const struct soc_enum wm8994_aif3adc_enum =
1292 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1293
1294 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1295 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1296
1297 static const struct soc_enum wm8958_aif3adc_enum =
1298 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1299
1300 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1301 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1302
1303 static const char *mono_pcm_out_text[] = {
1304 "None", "AIF2ADCL", "AIF2ADCR",
1305 };
1306
1307 static const struct soc_enum mono_pcm_out_enum =
1308 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1309
1310 static const struct snd_kcontrol_new mono_pcm_out_mux =
1311 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1312
1313 static const char *aif2dac_src_text[] = {
1314 "AIF2", "AIF3",
1315 };
1316
1317 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1318 static const struct soc_enum aif2dacl_src_enum =
1319 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1320
1321 static const struct snd_kcontrol_new aif2dacl_src_mux =
1322 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1323
1324 static const struct soc_enum aif2dacr_src_enum =
1325 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1326
1327 static const struct snd_kcontrol_new aif2dacr_src_mux =
1328 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1329
1330 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1331 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1332 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1333 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1334 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1335
1336 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1337 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1339 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1340 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1341 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1342 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1343 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1344 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1345 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1346
1347 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1348 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1349 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1350 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1351 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1352 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1353 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1354 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1355 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1356 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1357
1358 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1359 };
1360
1361 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1362 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1363 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1364 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1365 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1366 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1367 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1368 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1369 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1370 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1371 };
1372
1373 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1374 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1375 dac_ev, SND_SOC_DAPM_PRE_PMU),
1376 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1377 dac_ev, SND_SOC_DAPM_PRE_PMU),
1378 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1379 dac_ev, SND_SOC_DAPM_PRE_PMU),
1380 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1381 dac_ev, SND_SOC_DAPM_PRE_PMU),
1382 };
1383
1384 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1385 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1386 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1387 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1388 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1389 };
1390
1391 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1392 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1393 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1394 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1395 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1396 };
1397
1398 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1399 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1400 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1401 };
1402
1403 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1404 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1405 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1406 SND_SOC_DAPM_INPUT("Clock"),
1407
1408 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1409 SND_SOC_DAPM_PRE_PMU),
1410 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1412
1413 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1414 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1415
1416 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1417 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1418 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1419
1420 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1421 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1422 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1423 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1424 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1425 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1426 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1427 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1428 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1429 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1430
1431 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1432 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1433 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1434 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1435 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1436 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1437 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1438 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1439 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1440 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1441
1442 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1443 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1444 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1445 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1446
1447 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1448 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1449 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1450 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1451
1452 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1453 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1454 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1455 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1456
1457 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1458 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1459
1460 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1461 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1462 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1463 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1464
1465 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1466 WM8994_POWER_MANAGEMENT_4, 13, 0),
1467 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1468 WM8994_POWER_MANAGEMENT_4, 12, 0),
1469 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1470 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1471 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1473 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1475
1476 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1477 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1478 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1479 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1480
1481 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1482 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1483 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1484
1485 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1486 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1487
1488 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1489
1490 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1491 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1492 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1493 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1494
1495 /* Power is done with the muxes since the ADC power also controls the
1496 * downsampling chain, the chip will automatically manage the analogue
1497 * specific portions.
1498 */
1499 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1500 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1501
1502 SND_SOC_DAPM_POST("Debug log", post_ev),
1503 };
1504
1505 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1506 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1507 };
1508
1509 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1510 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1511 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1512 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1513 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1514 };
1515
1516 static const struct snd_soc_dapm_route intercon[] = {
1517 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1518 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1519
1520 { "DSP1CLK", NULL, "CLK_SYS" },
1521 { "DSP2CLK", NULL, "CLK_SYS" },
1522 { "DSPINTCLK", NULL, "CLK_SYS" },
1523
1524 { "AIF1ADC1L", NULL, "AIF1CLK" },
1525 { "AIF1ADC1L", NULL, "DSP1CLK" },
1526 { "AIF1ADC1R", NULL, "AIF1CLK" },
1527 { "AIF1ADC1R", NULL, "DSP1CLK" },
1528 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1529
1530 { "AIF1DAC1L", NULL, "AIF1CLK" },
1531 { "AIF1DAC1L", NULL, "DSP1CLK" },
1532 { "AIF1DAC1R", NULL, "AIF1CLK" },
1533 { "AIF1DAC1R", NULL, "DSP1CLK" },
1534 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1535
1536 { "AIF1ADC2L", NULL, "AIF1CLK" },
1537 { "AIF1ADC2L", NULL, "DSP1CLK" },
1538 { "AIF1ADC2R", NULL, "AIF1CLK" },
1539 { "AIF1ADC2R", NULL, "DSP1CLK" },
1540 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1541
1542 { "AIF1DAC2L", NULL, "AIF1CLK" },
1543 { "AIF1DAC2L", NULL, "DSP1CLK" },
1544 { "AIF1DAC2R", NULL, "AIF1CLK" },
1545 { "AIF1DAC2R", NULL, "DSP1CLK" },
1546 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1547
1548 { "AIF2ADCL", NULL, "AIF2CLK" },
1549 { "AIF2ADCL", NULL, "DSP2CLK" },
1550 { "AIF2ADCR", NULL, "AIF2CLK" },
1551 { "AIF2ADCR", NULL, "DSP2CLK" },
1552 { "AIF2ADCR", NULL, "DSPINTCLK" },
1553
1554 { "AIF2DACL", NULL, "AIF2CLK" },
1555 { "AIF2DACL", NULL, "DSP2CLK" },
1556 { "AIF2DACR", NULL, "AIF2CLK" },
1557 { "AIF2DACR", NULL, "DSP2CLK" },
1558 { "AIF2DACR", NULL, "DSPINTCLK" },
1559
1560 { "DMIC1L", NULL, "DMIC1DAT" },
1561 { "DMIC1L", NULL, "CLK_SYS" },
1562 { "DMIC1R", NULL, "DMIC1DAT" },
1563 { "DMIC1R", NULL, "CLK_SYS" },
1564 { "DMIC2L", NULL, "DMIC2DAT" },
1565 { "DMIC2L", NULL, "CLK_SYS" },
1566 { "DMIC2R", NULL, "DMIC2DAT" },
1567 { "DMIC2R", NULL, "CLK_SYS" },
1568
1569 { "ADCL", NULL, "AIF1CLK" },
1570 { "ADCL", NULL, "DSP1CLK" },
1571 { "ADCL", NULL, "DSPINTCLK" },
1572
1573 { "ADCR", NULL, "AIF1CLK" },
1574 { "ADCR", NULL, "DSP1CLK" },
1575 { "ADCR", NULL, "DSPINTCLK" },
1576
1577 { "ADCL Mux", "ADC", "ADCL" },
1578 { "ADCL Mux", "DMIC", "DMIC1L" },
1579 { "ADCR Mux", "ADC", "ADCR" },
1580 { "ADCR Mux", "DMIC", "DMIC1R" },
1581
1582 { "DAC1L", NULL, "AIF1CLK" },
1583 { "DAC1L", NULL, "DSP1CLK" },
1584 { "DAC1L", NULL, "DSPINTCLK" },
1585
1586 { "DAC1R", NULL, "AIF1CLK" },
1587 { "DAC1R", NULL, "DSP1CLK" },
1588 { "DAC1R", NULL, "DSPINTCLK" },
1589
1590 { "DAC2L", NULL, "AIF2CLK" },
1591 { "DAC2L", NULL, "DSP2CLK" },
1592 { "DAC2L", NULL, "DSPINTCLK" },
1593
1594 { "DAC2R", NULL, "AIF2DACR" },
1595 { "DAC2R", NULL, "AIF2CLK" },
1596 { "DAC2R", NULL, "DSP2CLK" },
1597 { "DAC2R", NULL, "DSPINTCLK" },
1598
1599 { "TOCLK", NULL, "CLK_SYS" },
1600
1601 /* AIF1 outputs */
1602 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1603 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1604 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1605
1606 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1607 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1608 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1609
1610 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1611 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1612 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1613
1614 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1615 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1616 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1617
1618 /* Pin level routing for AIF3 */
1619 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1620 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1621 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1622 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1623
1624 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1625 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1626 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1627 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1628 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1629 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1630 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1631
1632 /* DAC1 inputs */
1633 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1634 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1635 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1636 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1637 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1638
1639 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1640 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1641 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1642 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1643 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1644
1645 /* DAC2/AIF2 outputs */
1646 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1647 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1648 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1649 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1650 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1651 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1652
1653 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1654 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1655 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1656 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1657 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1658 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1659
1660 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1661 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1662 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1663 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1664
1665 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1666
1667 /* AIF3 output */
1668 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1669 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1670 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1671 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1672 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1673 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1674 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1675 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1676
1677 /* Sidetone */
1678 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1679 { "Left Sidetone", "DMIC2", "DMIC2L" },
1680 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1681 { "Right Sidetone", "DMIC2", "DMIC2R" },
1682
1683 /* Output stages */
1684 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1685 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1686
1687 { "SPKL", "DAC1 Switch", "DAC1L" },
1688 { "SPKL", "DAC2 Switch", "DAC2L" },
1689
1690 { "SPKR", "DAC1 Switch", "DAC1R" },
1691 { "SPKR", "DAC2 Switch", "DAC2R" },
1692
1693 { "Left Headphone Mux", "DAC", "DAC1L" },
1694 { "Right Headphone Mux", "DAC", "DAC1R" },
1695 };
1696
1697 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1698 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1699 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1700 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1701 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1702 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1703 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1704 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1705 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1706 };
1707
1708 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1709 { "DAC1L", NULL, "DAC1L Mixer" },
1710 { "DAC1R", NULL, "DAC1R Mixer" },
1711 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1712 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1713 };
1714
1715 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1716 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1717 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1718 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1719 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1720 { "MICBIAS1", NULL, "CLK_SYS" },
1721 { "MICBIAS1", NULL, "MICBIAS Supply" },
1722 { "MICBIAS2", NULL, "CLK_SYS" },
1723 { "MICBIAS2", NULL, "MICBIAS Supply" },
1724 };
1725
1726 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1727 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1728 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1729 { "MICBIAS1", NULL, "VMID" },
1730 { "MICBIAS2", NULL, "VMID" },
1731 };
1732
1733 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1734 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1735 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1736
1737 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1738 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1739 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1740 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1741
1742 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1743 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1744
1745 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1746 };
1747
1748 /* The size in bits of the FLL divide multiplied by 10
1749 * to allow rounding later */
1750 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1751
1752 struct fll_div {
1753 u16 outdiv;
1754 u16 n;
1755 u16 k;
1756 u16 clk_ref_div;
1757 u16 fll_fratio;
1758 };
1759
1760 static int wm8994_get_fll_config(struct fll_div *fll,
1761 int freq_in, int freq_out)
1762 {
1763 u64 Kpart;
1764 unsigned int K, Ndiv, Nmod;
1765
1766 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1767
1768 /* Scale the input frequency down to <= 13.5MHz */
1769 fll->clk_ref_div = 0;
1770 while (freq_in > 13500000) {
1771 fll->clk_ref_div++;
1772 freq_in /= 2;
1773
1774 if (fll->clk_ref_div > 3)
1775 return -EINVAL;
1776 }
1777 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1778
1779 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1780 fll->outdiv = 3;
1781 while (freq_out * (fll->outdiv + 1) < 90000000) {
1782 fll->outdiv++;
1783 if (fll->outdiv > 63)
1784 return -EINVAL;
1785 }
1786 freq_out *= fll->outdiv + 1;
1787 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1788
1789 if (freq_in > 1000000) {
1790 fll->fll_fratio = 0;
1791 } else if (freq_in > 256000) {
1792 fll->fll_fratio = 1;
1793 freq_in *= 2;
1794 } else if (freq_in > 128000) {
1795 fll->fll_fratio = 2;
1796 freq_in *= 4;
1797 } else if (freq_in > 64000) {
1798 fll->fll_fratio = 3;
1799 freq_in *= 8;
1800 } else {
1801 fll->fll_fratio = 4;
1802 freq_in *= 16;
1803 }
1804 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1805
1806 /* Now, calculate N.K */
1807 Ndiv = freq_out / freq_in;
1808
1809 fll->n = Ndiv;
1810 Nmod = freq_out % freq_in;
1811 pr_debug("Nmod=%d\n", Nmod);
1812
1813 /* Calculate fractional part - scale up so we can round. */
1814 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1815
1816 do_div(Kpart, freq_in);
1817
1818 K = Kpart & 0xFFFFFFFF;
1819
1820 if ((K % 10) >= 5)
1821 K += 5;
1822
1823 /* Move down to proper range now rounding is done */
1824 fll->k = K / 10;
1825
1826 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1827
1828 return 0;
1829 }
1830
1831 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1832 unsigned int freq_in, unsigned int freq_out)
1833 {
1834 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1835 struct wm8994 *control = wm8994->wm8994;
1836 int reg_offset, ret;
1837 struct fll_div fll;
1838 u16 reg, aif1, aif2;
1839 unsigned long timeout;
1840 bool was_enabled;
1841
1842 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1843 & WM8994_AIF1CLK_ENA;
1844
1845 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1846 & WM8994_AIF2CLK_ENA;
1847
1848 switch (id) {
1849 case WM8994_FLL1:
1850 reg_offset = 0;
1851 id = 0;
1852 break;
1853 case WM8994_FLL2:
1854 reg_offset = 0x20;
1855 id = 1;
1856 break;
1857 default:
1858 return -EINVAL;
1859 }
1860
1861 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1862 was_enabled = reg & WM8994_FLL1_ENA;
1863
1864 switch (src) {
1865 case 0:
1866 /* Allow no source specification when stopping */
1867 if (freq_out)
1868 return -EINVAL;
1869 src = wm8994->fll[id].src;
1870 break;
1871 case WM8994_FLL_SRC_MCLK1:
1872 case WM8994_FLL_SRC_MCLK2:
1873 case WM8994_FLL_SRC_LRCLK:
1874 case WM8994_FLL_SRC_BCLK:
1875 break;
1876 default:
1877 return -EINVAL;
1878 }
1879
1880 /* Are we changing anything? */
1881 if (wm8994->fll[id].src == src &&
1882 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1883 return 0;
1884
1885 /* If we're stopping the FLL redo the old config - no
1886 * registers will actually be written but we avoid GCC flow
1887 * analysis bugs spewing warnings.
1888 */
1889 if (freq_out)
1890 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1891 else
1892 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1893 wm8994->fll[id].out);
1894 if (ret < 0)
1895 return ret;
1896
1897 /* Gate the AIF clocks while we reclock */
1898 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1899 WM8994_AIF1CLK_ENA, 0);
1900 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1901 WM8994_AIF2CLK_ENA, 0);
1902
1903 /* We always need to disable the FLL while reconfiguring */
1904 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1905 WM8994_FLL1_ENA, 0);
1906
1907 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1908 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1909 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1910 WM8994_FLL1_OUTDIV_MASK |
1911 WM8994_FLL1_FRATIO_MASK, reg);
1912
1913 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1914
1915 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1916 WM8994_FLL1_N_MASK,
1917 fll.n << WM8994_FLL1_N_SHIFT);
1918
1919 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1920 WM8994_FLL1_REFCLK_DIV_MASK |
1921 WM8994_FLL1_REFCLK_SRC_MASK,
1922 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1923 (src - 1));
1924
1925 /* Clear any pending completion from a previous failure */
1926 try_wait_for_completion(&wm8994->fll_locked[id]);
1927
1928 /* Enable (with fractional mode if required) */
1929 if (freq_out) {
1930 /* Enable VMID if we need it */
1931 if (!was_enabled) {
1932 active_reference(codec);
1933
1934 switch (control->type) {
1935 case WM8994:
1936 vmid_reference(codec);
1937 break;
1938 case WM8958:
1939 if (wm8994->revision < 1)
1940 vmid_reference(codec);
1941 break;
1942 default:
1943 break;
1944 }
1945 }
1946
1947 if (fll.k)
1948 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1949 else
1950 reg = WM8994_FLL1_ENA;
1951 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1952 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1953 reg);
1954
1955 if (wm8994->fll_locked_irq) {
1956 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1957 msecs_to_jiffies(10));
1958 if (timeout == 0)
1959 dev_warn(codec->dev,
1960 "Timed out waiting for FLL lock\n");
1961 } else {
1962 msleep(5);
1963 }
1964 } else {
1965 if (was_enabled) {
1966 switch (control->type) {
1967 case WM8994:
1968 vmid_dereference(codec);
1969 break;
1970 case WM8958:
1971 if (wm8994->revision < 1)
1972 vmid_dereference(codec);
1973 break;
1974 default:
1975 break;
1976 }
1977
1978 active_dereference(codec);
1979 }
1980 }
1981
1982 wm8994->fll[id].in = freq_in;
1983 wm8994->fll[id].out = freq_out;
1984 wm8994->fll[id].src = src;
1985
1986 /* Enable any gated AIF clocks */
1987 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1988 WM8994_AIF1CLK_ENA, aif1);
1989 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1990 WM8994_AIF2CLK_ENA, aif2);
1991
1992 configure_clock(codec);
1993
1994 return 0;
1995 }
1996
1997 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1998 {
1999 struct completion *completion = data;
2000
2001 complete(completion);
2002
2003 return IRQ_HANDLED;
2004 }
2005
2006 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2007
2008 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2009 unsigned int freq_in, unsigned int freq_out)
2010 {
2011 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2012 }
2013
2014 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2015 int clk_id, unsigned int freq, int dir)
2016 {
2017 struct snd_soc_codec *codec = dai->codec;
2018 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2019 int i;
2020
2021 switch (dai->id) {
2022 case 1:
2023 case 2:
2024 break;
2025
2026 default:
2027 /* AIF3 shares clocking with AIF1/2 */
2028 return -EINVAL;
2029 }
2030
2031 switch (clk_id) {
2032 case WM8994_SYSCLK_MCLK1:
2033 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2034 wm8994->mclk[0] = freq;
2035 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2036 dai->id, freq);
2037 break;
2038
2039 case WM8994_SYSCLK_MCLK2:
2040 /* TODO: Set GPIO AF */
2041 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2042 wm8994->mclk[1] = freq;
2043 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2044 dai->id, freq);
2045 break;
2046
2047 case WM8994_SYSCLK_FLL1:
2048 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2049 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2050 break;
2051
2052 case WM8994_SYSCLK_FLL2:
2053 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2054 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2055 break;
2056
2057 case WM8994_SYSCLK_OPCLK:
2058 /* Special case - a division (times 10) is given and
2059 * no effect on main clocking.
2060 */
2061 if (freq) {
2062 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2063 if (opclk_divs[i] == freq)
2064 break;
2065 if (i == ARRAY_SIZE(opclk_divs))
2066 return -EINVAL;
2067 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2068 WM8994_OPCLK_DIV_MASK, i);
2069 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2070 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2071 } else {
2072 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2073 WM8994_OPCLK_ENA, 0);
2074 }
2075
2076 default:
2077 return -EINVAL;
2078 }
2079
2080 configure_clock(codec);
2081
2082 return 0;
2083 }
2084
2085 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2086 enum snd_soc_bias_level level)
2087 {
2088 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2089 struct wm8994 *control = wm8994->wm8994;
2090
2091 wm_hubs_set_bias_level(codec, level);
2092
2093 switch (level) {
2094 case SND_SOC_BIAS_ON:
2095 break;
2096
2097 case SND_SOC_BIAS_PREPARE:
2098 /* MICBIAS into regulating mode */
2099 switch (control->type) {
2100 case WM8958:
2101 case WM1811:
2102 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2103 WM8958_MICB1_MODE, 0);
2104 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2105 WM8958_MICB2_MODE, 0);
2106 break;
2107 default:
2108 break;
2109 }
2110
2111 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2112 active_reference(codec);
2113 break;
2114
2115 case SND_SOC_BIAS_STANDBY:
2116 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2117 switch (control->type) {
2118 case WM8994:
2119 if (wm8994->revision < 4) {
2120 /* Tweak DC servo and DSP
2121 * configuration for improved
2122 * performance. */
2123 snd_soc_write(codec, 0x102, 0x3);
2124 snd_soc_write(codec, 0x56, 0x3);
2125 snd_soc_write(codec, 0x817, 0);
2126 snd_soc_write(codec, 0x102, 0);
2127 }
2128 break;
2129
2130 case WM8958:
2131 if (wm8994->revision == 0) {
2132 /* Optimise performance for rev A */
2133 snd_soc_write(codec, 0x102, 0x3);
2134 snd_soc_write(codec, 0xcb, 0x81);
2135 snd_soc_write(codec, 0x817, 0);
2136 snd_soc_write(codec, 0x102, 0);
2137
2138 snd_soc_update_bits(codec,
2139 WM8958_CHARGE_PUMP_2,
2140 WM8958_CP_DISCH,
2141 WM8958_CP_DISCH);
2142 }
2143 break;
2144
2145 case WM1811:
2146 if (wm8994->revision < 2) {
2147 snd_soc_write(codec, 0x102, 0x3);
2148 snd_soc_write(codec, 0x5d, 0x7e);
2149 snd_soc_write(codec, 0x5e, 0x0);
2150 snd_soc_write(codec, 0x102, 0x0);
2151 }
2152 break;
2153 }
2154
2155 /* Discharge LINEOUT1 & 2 */
2156 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2157 WM8994_LINEOUT1_DISCH |
2158 WM8994_LINEOUT2_DISCH,
2159 WM8994_LINEOUT1_DISCH |
2160 WM8994_LINEOUT2_DISCH);
2161 }
2162
2163 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2164 active_dereference(codec);
2165
2166 /* MICBIAS into bypass mode on newer devices */
2167 switch (control->type) {
2168 case WM8958:
2169 case WM1811:
2170 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2171 WM8958_MICB1_MODE,
2172 WM8958_MICB1_MODE);
2173 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2174 WM8958_MICB2_MODE,
2175 WM8958_MICB2_MODE);
2176 break;
2177 default:
2178 break;
2179 }
2180 break;
2181
2182 case SND_SOC_BIAS_OFF:
2183 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2184 wm8994->cur_fw = NULL;
2185 break;
2186 }
2187
2188 codec->dapm.bias_level = level;
2189
2190 return 0;
2191 }
2192
2193 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2194 {
2195 struct snd_soc_codec *codec = dai->codec;
2196 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2197 struct wm8994 *control = wm8994->wm8994;
2198 int ms_reg;
2199 int aif1_reg;
2200 int ms = 0;
2201 int aif1 = 0;
2202
2203 switch (dai->id) {
2204 case 1:
2205 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2206 aif1_reg = WM8994_AIF1_CONTROL_1;
2207 break;
2208 case 2:
2209 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2210 aif1_reg = WM8994_AIF2_CONTROL_1;
2211 break;
2212 default:
2213 return -EINVAL;
2214 }
2215
2216 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2217 case SND_SOC_DAIFMT_CBS_CFS:
2218 break;
2219 case SND_SOC_DAIFMT_CBM_CFM:
2220 ms = WM8994_AIF1_MSTR;
2221 break;
2222 default:
2223 return -EINVAL;
2224 }
2225
2226 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2227 case SND_SOC_DAIFMT_DSP_B:
2228 aif1 |= WM8994_AIF1_LRCLK_INV;
2229 case SND_SOC_DAIFMT_DSP_A:
2230 aif1 |= 0x18;
2231 break;
2232 case SND_SOC_DAIFMT_I2S:
2233 aif1 |= 0x10;
2234 break;
2235 case SND_SOC_DAIFMT_RIGHT_J:
2236 break;
2237 case SND_SOC_DAIFMT_LEFT_J:
2238 aif1 |= 0x8;
2239 break;
2240 default:
2241 return -EINVAL;
2242 }
2243
2244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2245 case SND_SOC_DAIFMT_DSP_A:
2246 case SND_SOC_DAIFMT_DSP_B:
2247 /* frame inversion not valid for DSP modes */
2248 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2249 case SND_SOC_DAIFMT_NB_NF:
2250 break;
2251 case SND_SOC_DAIFMT_IB_NF:
2252 aif1 |= WM8994_AIF1_BCLK_INV;
2253 break;
2254 default:
2255 return -EINVAL;
2256 }
2257 break;
2258
2259 case SND_SOC_DAIFMT_I2S:
2260 case SND_SOC_DAIFMT_RIGHT_J:
2261 case SND_SOC_DAIFMT_LEFT_J:
2262 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2263 case SND_SOC_DAIFMT_NB_NF:
2264 break;
2265 case SND_SOC_DAIFMT_IB_IF:
2266 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2267 break;
2268 case SND_SOC_DAIFMT_IB_NF:
2269 aif1 |= WM8994_AIF1_BCLK_INV;
2270 break;
2271 case SND_SOC_DAIFMT_NB_IF:
2272 aif1 |= WM8994_AIF1_LRCLK_INV;
2273 break;
2274 default:
2275 return -EINVAL;
2276 }
2277 break;
2278 default:
2279 return -EINVAL;
2280 }
2281
2282 /* The AIF2 format configuration needs to be mirrored to AIF3
2283 * on WM8958 if it's in use so just do it all the time. */
2284 switch (control->type) {
2285 case WM1811:
2286 case WM8958:
2287 if (dai->id == 2)
2288 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2289 WM8994_AIF1_LRCLK_INV |
2290 WM8958_AIF3_FMT_MASK, aif1);
2291 break;
2292
2293 default:
2294 break;
2295 }
2296
2297 snd_soc_update_bits(codec, aif1_reg,
2298 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2299 WM8994_AIF1_FMT_MASK,
2300 aif1);
2301 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2302 ms);
2303
2304 return 0;
2305 }
2306
2307 static struct {
2308 int val, rate;
2309 } srs[] = {
2310 { 0, 8000 },
2311 { 1, 11025 },
2312 { 2, 12000 },
2313 { 3, 16000 },
2314 { 4, 22050 },
2315 { 5, 24000 },
2316 { 6, 32000 },
2317 { 7, 44100 },
2318 { 8, 48000 },
2319 { 9, 88200 },
2320 { 10, 96000 },
2321 };
2322
2323 static int fs_ratios[] = {
2324 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2325 };
2326
2327 static int bclk_divs[] = {
2328 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2329 640, 880, 960, 1280, 1760, 1920
2330 };
2331
2332 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2333 struct snd_pcm_hw_params *params,
2334 struct snd_soc_dai *dai)
2335 {
2336 struct snd_soc_codec *codec = dai->codec;
2337 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2338 int aif1_reg;
2339 int aif2_reg;
2340 int bclk_reg;
2341 int lrclk_reg;
2342 int rate_reg;
2343 int aif1 = 0;
2344 int aif2 = 0;
2345 int bclk = 0;
2346 int lrclk = 0;
2347 int rate_val = 0;
2348 int id = dai->id - 1;
2349
2350 int i, cur_val, best_val, bclk_rate, best;
2351
2352 switch (dai->id) {
2353 case 1:
2354 aif1_reg = WM8994_AIF1_CONTROL_1;
2355 aif2_reg = WM8994_AIF1_CONTROL_2;
2356 bclk_reg = WM8994_AIF1_BCLK;
2357 rate_reg = WM8994_AIF1_RATE;
2358 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2359 wm8994->lrclk_shared[0]) {
2360 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2361 } else {
2362 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2363 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2364 }
2365 break;
2366 case 2:
2367 aif1_reg = WM8994_AIF2_CONTROL_1;
2368 aif2_reg = WM8994_AIF2_CONTROL_2;
2369 bclk_reg = WM8994_AIF2_BCLK;
2370 rate_reg = WM8994_AIF2_RATE;
2371 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2372 wm8994->lrclk_shared[1]) {
2373 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2374 } else {
2375 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2376 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2377 }
2378 break;
2379 default:
2380 return -EINVAL;
2381 }
2382
2383 bclk_rate = params_rate(params) * 2;
2384 switch (params_format(params)) {
2385 case SNDRV_PCM_FORMAT_S16_LE:
2386 bclk_rate *= 16;
2387 break;
2388 case SNDRV_PCM_FORMAT_S20_3LE:
2389 bclk_rate *= 20;
2390 aif1 |= 0x20;
2391 break;
2392 case SNDRV_PCM_FORMAT_S24_LE:
2393 bclk_rate *= 24;
2394 aif1 |= 0x40;
2395 break;
2396 case SNDRV_PCM_FORMAT_S32_LE:
2397 bclk_rate *= 32;
2398 aif1 |= 0x60;
2399 break;
2400 default:
2401 return -EINVAL;
2402 }
2403
2404 /* Try to find an appropriate sample rate; look for an exact match. */
2405 for (i = 0; i < ARRAY_SIZE(srs); i++)
2406 if (srs[i].rate == params_rate(params))
2407 break;
2408 if (i == ARRAY_SIZE(srs))
2409 return -EINVAL;
2410 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2411
2412 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2413 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2414 dai->id, wm8994->aifclk[id], bclk_rate);
2415
2416 if (params_channels(params) == 1 &&
2417 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2418 aif2 |= WM8994_AIF1_MONO;
2419
2420 if (wm8994->aifclk[id] == 0) {
2421 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2422 return -EINVAL;
2423 }
2424
2425 /* AIFCLK/fs ratio; look for a close match in either direction */
2426 best = 0;
2427 best_val = abs((fs_ratios[0] * params_rate(params))
2428 - wm8994->aifclk[id]);
2429 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2430 cur_val = abs((fs_ratios[i] * params_rate(params))
2431 - wm8994->aifclk[id]);
2432 if (cur_val >= best_val)
2433 continue;
2434 best = i;
2435 best_val = cur_val;
2436 }
2437 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2438 dai->id, fs_ratios[best]);
2439 rate_val |= best;
2440
2441 /* We may not get quite the right frequency if using
2442 * approximate clocks so look for the closest match that is
2443 * higher than the target (we need to ensure that there enough
2444 * BCLKs to clock out the samples).
2445 */
2446 best = 0;
2447 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2448 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2449 if (cur_val < 0) /* BCLK table is sorted */
2450 break;
2451 best = i;
2452 }
2453 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2454 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2455 bclk_divs[best], bclk_rate);
2456 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2457
2458 lrclk = bclk_rate / params_rate(params);
2459 if (!lrclk) {
2460 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2461 bclk_rate);
2462 return -EINVAL;
2463 }
2464 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2465 lrclk, bclk_rate / lrclk);
2466
2467 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2468 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2469 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2470 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2471 lrclk);
2472 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2473 WM8994_AIF1CLK_RATE_MASK, rate_val);
2474
2475 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2476 switch (dai->id) {
2477 case 1:
2478 wm8994->dac_rates[0] = params_rate(params);
2479 wm8994_set_retune_mobile(codec, 0);
2480 wm8994_set_retune_mobile(codec, 1);
2481 break;
2482 case 2:
2483 wm8994->dac_rates[1] = params_rate(params);
2484 wm8994_set_retune_mobile(codec, 2);
2485 break;
2486 }
2487 }
2488
2489 return 0;
2490 }
2491
2492 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2493 struct snd_pcm_hw_params *params,
2494 struct snd_soc_dai *dai)
2495 {
2496 struct snd_soc_codec *codec = dai->codec;
2497 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2498 struct wm8994 *control = wm8994->wm8994;
2499 int aif1_reg;
2500 int aif1 = 0;
2501
2502 switch (dai->id) {
2503 case 3:
2504 switch (control->type) {
2505 case WM1811:
2506 case WM8958:
2507 aif1_reg = WM8958_AIF3_CONTROL_1;
2508 break;
2509 default:
2510 return 0;
2511 }
2512 default:
2513 return 0;
2514 }
2515
2516 switch (params_format(params)) {
2517 case SNDRV_PCM_FORMAT_S16_LE:
2518 break;
2519 case SNDRV_PCM_FORMAT_S20_3LE:
2520 aif1 |= 0x20;
2521 break;
2522 case SNDRV_PCM_FORMAT_S24_LE:
2523 aif1 |= 0x40;
2524 break;
2525 case SNDRV_PCM_FORMAT_S32_LE:
2526 aif1 |= 0x60;
2527 break;
2528 default:
2529 return -EINVAL;
2530 }
2531
2532 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2533 }
2534
2535 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2536 struct snd_soc_dai *dai)
2537 {
2538 struct snd_soc_codec *codec = dai->codec;
2539 int rate_reg = 0;
2540
2541 switch (dai->id) {
2542 case 1:
2543 rate_reg = WM8994_AIF1_RATE;
2544 break;
2545 case 2:
2546 rate_reg = WM8994_AIF2_RATE;
2547 break;
2548 default:
2549 break;
2550 }
2551
2552 /* If the DAI is idle then configure the divider tree for the
2553 * lowest output rate to save a little power if the clock is
2554 * still active (eg, because it is system clock).
2555 */
2556 if (rate_reg && !dai->playback_active && !dai->capture_active)
2557 snd_soc_update_bits(codec, rate_reg,
2558 WM8994_AIF1_SR_MASK |
2559 WM8994_AIF1CLK_RATE_MASK, 0x9);
2560 }
2561
2562 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2563 {
2564 struct snd_soc_codec *codec = codec_dai->codec;
2565 int mute_reg;
2566 int reg;
2567
2568 switch (codec_dai->id) {
2569 case 1:
2570 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2571 break;
2572 case 2:
2573 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2574 break;
2575 default:
2576 return -EINVAL;
2577 }
2578
2579 if (mute)
2580 reg = WM8994_AIF1DAC1_MUTE;
2581 else
2582 reg = 0;
2583
2584 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2585
2586 return 0;
2587 }
2588
2589 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2590 {
2591 struct snd_soc_codec *codec = codec_dai->codec;
2592 int reg, val, mask;
2593
2594 switch (codec_dai->id) {
2595 case 1:
2596 reg = WM8994_AIF1_MASTER_SLAVE;
2597 mask = WM8994_AIF1_TRI;
2598 break;
2599 case 2:
2600 reg = WM8994_AIF2_MASTER_SLAVE;
2601 mask = WM8994_AIF2_TRI;
2602 break;
2603 case 3:
2604 reg = WM8994_POWER_MANAGEMENT_6;
2605 mask = WM8994_AIF3_TRI;
2606 break;
2607 default:
2608 return -EINVAL;
2609 }
2610
2611 if (tristate)
2612 val = mask;
2613 else
2614 val = 0;
2615
2616 return snd_soc_update_bits(codec, reg, mask, val);
2617 }
2618
2619 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2620 {
2621 struct snd_soc_codec *codec = dai->codec;
2622
2623 /* Disable the pulls on the AIF if we're using it to save power. */
2624 snd_soc_update_bits(codec, WM8994_GPIO_3,
2625 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2626 snd_soc_update_bits(codec, WM8994_GPIO_4,
2627 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2628 snd_soc_update_bits(codec, WM8994_GPIO_5,
2629 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2630
2631 return 0;
2632 }
2633
2634 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2635
2636 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2637 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2638
2639 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2640 .set_sysclk = wm8994_set_dai_sysclk,
2641 .set_fmt = wm8994_set_dai_fmt,
2642 .hw_params = wm8994_hw_params,
2643 .shutdown = wm8994_aif_shutdown,
2644 .digital_mute = wm8994_aif_mute,
2645 .set_pll = wm8994_set_fll,
2646 .set_tristate = wm8994_set_tristate,
2647 };
2648
2649 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2650 .set_sysclk = wm8994_set_dai_sysclk,
2651 .set_fmt = wm8994_set_dai_fmt,
2652 .hw_params = wm8994_hw_params,
2653 .shutdown = wm8994_aif_shutdown,
2654 .digital_mute = wm8994_aif_mute,
2655 .set_pll = wm8994_set_fll,
2656 .set_tristate = wm8994_set_tristate,
2657 };
2658
2659 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2660 .hw_params = wm8994_aif3_hw_params,
2661 .set_tristate = wm8994_set_tristate,
2662 };
2663
2664 static struct snd_soc_dai_driver wm8994_dai[] = {
2665 {
2666 .name = "wm8994-aif1",
2667 .id = 1,
2668 .playback = {
2669 .stream_name = "AIF1 Playback",
2670 .channels_min = 1,
2671 .channels_max = 2,
2672 .rates = WM8994_RATES,
2673 .formats = WM8994_FORMATS,
2674 .sig_bits = 24,
2675 },
2676 .capture = {
2677 .stream_name = "AIF1 Capture",
2678 .channels_min = 1,
2679 .channels_max = 2,
2680 .rates = WM8994_RATES,
2681 .formats = WM8994_FORMATS,
2682 .sig_bits = 24,
2683 },
2684 .ops = &wm8994_aif1_dai_ops,
2685 },
2686 {
2687 .name = "wm8994-aif2",
2688 .id = 2,
2689 .playback = {
2690 .stream_name = "AIF2 Playback",
2691 .channels_min = 1,
2692 .channels_max = 2,
2693 .rates = WM8994_RATES,
2694 .formats = WM8994_FORMATS,
2695 .sig_bits = 24,
2696 },
2697 .capture = {
2698 .stream_name = "AIF2 Capture",
2699 .channels_min = 1,
2700 .channels_max = 2,
2701 .rates = WM8994_RATES,
2702 .formats = WM8994_FORMATS,
2703 .sig_bits = 24,
2704 },
2705 .probe = wm8994_aif2_probe,
2706 .ops = &wm8994_aif2_dai_ops,
2707 },
2708 {
2709 .name = "wm8994-aif3",
2710 .id = 3,
2711 .playback = {
2712 .stream_name = "AIF3 Playback",
2713 .channels_min = 1,
2714 .channels_max = 2,
2715 .rates = WM8994_RATES,
2716 .formats = WM8994_FORMATS,
2717 .sig_bits = 24,
2718 },
2719 .capture = {
2720 .stream_name = "AIF3 Capture",
2721 .channels_min = 1,
2722 .channels_max = 2,
2723 .rates = WM8994_RATES,
2724 .formats = WM8994_FORMATS,
2725 .sig_bits = 24,
2726 },
2727 .ops = &wm8994_aif3_dai_ops,
2728 }
2729 };
2730
2731 #ifdef CONFIG_PM
2732 static int wm8994_suspend(struct snd_soc_codec *codec)
2733 {
2734 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2735 struct wm8994 *control = wm8994->wm8994;
2736 int i, ret;
2737
2738 switch (control->type) {
2739 case WM8994:
2740 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2741 break;
2742 case WM1811:
2743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2744 WM1811_JACKDET_MODE_MASK, 0);
2745 /* Fall through */
2746 case WM8958:
2747 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2748 WM8958_MICD_ENA, 0);
2749 break;
2750 }
2751
2752 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2753 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2754 sizeof(struct wm8994_fll_config));
2755 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2756 if (ret < 0)
2757 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2758 i + 1, ret);
2759 }
2760
2761 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2762
2763 return 0;
2764 }
2765
2766 static int wm8994_resume(struct snd_soc_codec *codec)
2767 {
2768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2769 struct wm8994 *control = wm8994->wm8994;
2770 int i, ret;
2771 unsigned int val, mask;
2772
2773 if (wm8994->revision < 4) {
2774 /* force a HW read */
2775 ret = regmap_read(control->regmap,
2776 WM8994_POWER_MANAGEMENT_5, &val);
2777
2778 /* modify the cache only */
2779 codec->cache_only = 1;
2780 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2781 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2782 val &= mask;
2783 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2784 mask, val);
2785 codec->cache_only = 0;
2786 }
2787
2788 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2789 if (!wm8994->fll_suspend[i].out)
2790 continue;
2791
2792 ret = _wm8994_set_fll(codec, i + 1,
2793 wm8994->fll_suspend[i].src,
2794 wm8994->fll_suspend[i].in,
2795 wm8994->fll_suspend[i].out);
2796 if (ret < 0)
2797 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2798 i + 1, ret);
2799 }
2800
2801 switch (control->type) {
2802 case WM8994:
2803 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2804 snd_soc_update_bits(codec, WM8994_MICBIAS,
2805 WM8994_MICD_ENA, WM8994_MICD_ENA);
2806 break;
2807 case WM1811:
2808 if (wm8994->jackdet && wm8994->jack_cb) {
2809 /* Restart from idle */
2810 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2811 WM1811_JACKDET_MODE_MASK,
2812 WM1811_JACKDET_MODE_JACK);
2813 break;
2814 }
2815 case WM8958:
2816 if (wm8994->jack_cb)
2817 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2818 WM8958_MICD_ENA, WM8958_MICD_ENA);
2819 break;
2820 }
2821
2822 return 0;
2823 }
2824 #else
2825 #define wm8994_suspend NULL
2826 #define wm8994_resume NULL
2827 #endif
2828
2829 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2830 {
2831 struct snd_soc_codec *codec = wm8994->codec;
2832 struct wm8994_pdata *pdata = wm8994->pdata;
2833 struct snd_kcontrol_new controls[] = {
2834 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2835 wm8994->retune_mobile_enum,
2836 wm8994_get_retune_mobile_enum,
2837 wm8994_put_retune_mobile_enum),
2838 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2839 wm8994->retune_mobile_enum,
2840 wm8994_get_retune_mobile_enum,
2841 wm8994_put_retune_mobile_enum),
2842 SOC_ENUM_EXT("AIF2 EQ Mode",
2843 wm8994->retune_mobile_enum,
2844 wm8994_get_retune_mobile_enum,
2845 wm8994_put_retune_mobile_enum),
2846 };
2847 int ret, i, j;
2848 const char **t;
2849
2850 /* We need an array of texts for the enum API but the number
2851 * of texts is likely to be less than the number of
2852 * configurations due to the sample rate dependency of the
2853 * configurations. */
2854 wm8994->num_retune_mobile_texts = 0;
2855 wm8994->retune_mobile_texts = NULL;
2856 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2857 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2858 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2859 wm8994->retune_mobile_texts[j]) == 0)
2860 break;
2861 }
2862
2863 if (j != wm8994->num_retune_mobile_texts)
2864 continue;
2865
2866 /* Expand the array... */
2867 t = krealloc(wm8994->retune_mobile_texts,
2868 sizeof(char *) *
2869 (wm8994->num_retune_mobile_texts + 1),
2870 GFP_KERNEL);
2871 if (t == NULL)
2872 continue;
2873
2874 /* ...store the new entry... */
2875 t[wm8994->num_retune_mobile_texts] =
2876 pdata->retune_mobile_cfgs[i].name;
2877
2878 /* ...and remember the new version. */
2879 wm8994->num_retune_mobile_texts++;
2880 wm8994->retune_mobile_texts = t;
2881 }
2882
2883 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2884 wm8994->num_retune_mobile_texts);
2885
2886 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2887 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2888
2889 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2890 ARRAY_SIZE(controls));
2891 if (ret != 0)
2892 dev_err(wm8994->codec->dev,
2893 "Failed to add ReTune Mobile controls: %d\n", ret);
2894 }
2895
2896 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2897 {
2898 struct snd_soc_codec *codec = wm8994->codec;
2899 struct wm8994_pdata *pdata = wm8994->pdata;
2900 int ret, i;
2901
2902 if (!pdata)
2903 return;
2904
2905 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2906 pdata->lineout2_diff,
2907 pdata->lineout1fb,
2908 pdata->lineout2fb,
2909 pdata->jd_scthr,
2910 pdata->jd_thr,
2911 pdata->micbias1_lvl,
2912 pdata->micbias2_lvl);
2913
2914 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2915
2916 if (pdata->num_drc_cfgs) {
2917 struct snd_kcontrol_new controls[] = {
2918 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2919 wm8994_get_drc_enum, wm8994_put_drc_enum),
2920 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2921 wm8994_get_drc_enum, wm8994_put_drc_enum),
2922 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2923 wm8994_get_drc_enum, wm8994_put_drc_enum),
2924 };
2925
2926 /* We need an array of texts for the enum API */
2927 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2928 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
2929 if (!wm8994->drc_texts) {
2930 dev_err(wm8994->codec->dev,
2931 "Failed to allocate %d DRC config texts\n",
2932 pdata->num_drc_cfgs);
2933 return;
2934 }
2935
2936 for (i = 0; i < pdata->num_drc_cfgs; i++)
2937 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2938
2939 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2940 wm8994->drc_enum.texts = wm8994->drc_texts;
2941
2942 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2943 ARRAY_SIZE(controls));
2944 if (ret != 0)
2945 dev_err(wm8994->codec->dev,
2946 "Failed to add DRC mode controls: %d\n", ret);
2947
2948 for (i = 0; i < WM8994_NUM_DRC; i++)
2949 wm8994_set_drc(codec, i);
2950 }
2951
2952 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2953 pdata->num_retune_mobile_cfgs);
2954
2955 if (pdata->num_retune_mobile_cfgs)
2956 wm8994_handle_retune_mobile_pdata(wm8994);
2957 else
2958 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
2959 ARRAY_SIZE(wm8994_eq_controls));
2960
2961 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2962 if (pdata->micbias[i]) {
2963 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2964 pdata->micbias[i] & 0xffff);
2965 }
2966 }
2967 }
2968
2969 /**
2970 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2971 *
2972 * @codec: WM8994 codec
2973 * @jack: jack to report detection events on
2974 * @micbias: microphone bias to detect on
2975 *
2976 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2977 * being used to bring out signals to the processor then only platform
2978 * data configuration is needed for WM8994 and processor GPIOs should
2979 * be configured using snd_soc_jack_add_gpios() instead.
2980 *
2981 * Configuration of detection levels is available via the micbias1_lvl
2982 * and micbias2_lvl platform data members.
2983 */
2984 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2985 int micbias)
2986 {
2987 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2988 struct wm8994_micdet *micdet;
2989 struct wm8994 *control = wm8994->wm8994;
2990 int reg, ret;
2991
2992 if (control->type != WM8994) {
2993 dev_warn(codec->dev, "Not a WM8994\n");
2994 return -EINVAL;
2995 }
2996
2997 switch (micbias) {
2998 case 1:
2999 micdet = &wm8994->micdet[0];
3000 if (jack)
3001 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3002 "MICBIAS1");
3003 else
3004 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3005 "MICBIAS1");
3006 break;
3007 case 2:
3008 micdet = &wm8994->micdet[1];
3009 if (jack)
3010 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3011 "MICBIAS1");
3012 else
3013 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3014 "MICBIAS1");
3015 break;
3016 default:
3017 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3018 return -EINVAL;
3019 }
3020
3021 if (ret != 0)
3022 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3023 micbias, ret);
3024
3025 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3026 micbias, jack);
3027
3028 /* Store the configuration */
3029 micdet->jack = jack;
3030 micdet->detecting = true;
3031
3032 /* If either of the jacks is set up then enable detection */
3033 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3034 reg = WM8994_MICD_ENA;
3035 else
3036 reg = 0;
3037
3038 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3039
3040 snd_soc_dapm_sync(&codec->dapm);
3041
3042 return 0;
3043 }
3044 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3045
3046 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3047 {
3048 struct wm8994_priv *priv = data;
3049 struct snd_soc_codec *codec = priv->codec;
3050 int reg;
3051 int report;
3052
3053 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3054 trace_snd_soc_jack_irq(dev_name(codec->dev));
3055 #endif
3056
3057 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3058 if (reg < 0) {
3059 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3060 reg);
3061 return IRQ_HANDLED;
3062 }
3063
3064 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3065
3066 report = 0;
3067 if (reg & WM8994_MIC1_DET_STS) {
3068 if (priv->micdet[0].detecting)
3069 report = SND_JACK_HEADSET;
3070 }
3071 if (reg & WM8994_MIC1_SHRT_STS) {
3072 if (priv->micdet[0].detecting)
3073 report = SND_JACK_HEADPHONE;
3074 else
3075 report |= SND_JACK_BTN_0;
3076 }
3077 if (report)
3078 priv->micdet[0].detecting = false;
3079 else
3080 priv->micdet[0].detecting = true;
3081
3082 snd_soc_jack_report(priv->micdet[0].jack, report,
3083 SND_JACK_HEADSET | SND_JACK_BTN_0);
3084
3085 report = 0;
3086 if (reg & WM8994_MIC2_DET_STS) {
3087 if (priv->micdet[1].detecting)
3088 report = SND_JACK_HEADSET;
3089 }
3090 if (reg & WM8994_MIC2_SHRT_STS) {
3091 if (priv->micdet[1].detecting)
3092 report = SND_JACK_HEADPHONE;
3093 else
3094 report |= SND_JACK_BTN_0;
3095 }
3096 if (report)
3097 priv->micdet[1].detecting = false;
3098 else
3099 priv->micdet[1].detecting = true;
3100
3101 snd_soc_jack_report(priv->micdet[1].jack, report,
3102 SND_JACK_HEADSET | SND_JACK_BTN_0);
3103
3104 return IRQ_HANDLED;
3105 }
3106
3107 /* Default microphone detection handler for WM8958 - the user can
3108 * override this if they wish.
3109 */
3110 static void wm8958_default_micdet(u16 status, void *data)
3111 {
3112 struct snd_soc_codec *codec = data;
3113 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3114 int report;
3115
3116 dev_dbg(codec->dev, "MICDET %x\n", status);
3117
3118 /* Either nothing present or just starting detection */
3119 if (!(status & WM8958_MICD_STS)) {
3120 if (!wm8994->jackdet) {
3121 /* If nothing present then clear our statuses */
3122 dev_dbg(codec->dev, "Detected open circuit\n");
3123 wm8994->jack_mic = false;
3124 wm8994->mic_detecting = true;
3125
3126 wm8958_micd_set_rate(codec);
3127
3128 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3129 wm8994->btn_mask |
3130 SND_JACK_HEADSET);
3131 }
3132 return;
3133 }
3134
3135 /* If the measurement is showing a high impedence we've got a
3136 * microphone.
3137 */
3138 if (wm8994->mic_detecting && (status & 0x600)) {
3139 dev_dbg(codec->dev, "Detected microphone\n");
3140
3141 wm8994->mic_detecting = false;
3142 wm8994->jack_mic = true;
3143
3144 wm8958_micd_set_rate(codec);
3145
3146 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3147 SND_JACK_HEADSET);
3148 }
3149
3150
3151 if (wm8994->mic_detecting && status & 0xfc) {
3152 dev_dbg(codec->dev, "Detected headphone\n");
3153 wm8994->mic_detecting = false;
3154
3155 wm8958_micd_set_rate(codec);
3156
3157 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3158 SND_JACK_HEADSET);
3159
3160 /* If we have jackdet that will detect removal */
3161 if (wm8994->jackdet) {
3162 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3163 WM8958_MICD_ENA, 0);
3164
3165 wm1811_jackdet_set_mode(codec,
3166 WM1811_JACKDET_MODE_JACK);
3167 }
3168 }
3169
3170 /* Report short circuit as a button */
3171 if (wm8994->jack_mic) {
3172 report = 0;
3173 if (status & 0x4)
3174 report |= SND_JACK_BTN_0;
3175
3176 if (status & 0x8)
3177 report |= SND_JACK_BTN_1;
3178
3179 if (status & 0x10)
3180 report |= SND_JACK_BTN_2;
3181
3182 if (status & 0x20)
3183 report |= SND_JACK_BTN_3;
3184
3185 if (status & 0x40)
3186 report |= SND_JACK_BTN_4;
3187
3188 if (status & 0x80)
3189 report |= SND_JACK_BTN_5;
3190
3191 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3192 wm8994->btn_mask);
3193 }
3194 }
3195
3196 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3197 {
3198 struct wm8994_priv *wm8994 = data;
3199 struct snd_soc_codec *codec = wm8994->codec;
3200 int reg;
3201
3202 mutex_lock(&wm8994->accdet_lock);
3203
3204 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3205 if (reg < 0) {
3206 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3207 mutex_unlock(&wm8994->accdet_lock);
3208 return IRQ_NONE;
3209 }
3210
3211 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3212
3213 if (reg & WM1811_JACKDET_LVL) {
3214 dev_dbg(codec->dev, "Jack detected\n");
3215
3216 snd_soc_jack_report(wm8994->micdet[0].jack,
3217 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3218
3219 /*
3220 * Start off measument of microphone impedence to find
3221 * out what's actually there.
3222 */
3223 wm8994->mic_detecting = true;
3224 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3225 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3226 WM8958_MICD_ENA, WM8958_MICD_ENA);
3227 } else {
3228 dev_dbg(codec->dev, "Jack not detected\n");
3229
3230 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3231 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3232 wm8994->btn_mask);
3233
3234 wm8994->mic_detecting = false;
3235 wm8994->jack_mic = false;
3236 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3237 WM8958_MICD_ENA, 0);
3238 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3239 }
3240
3241 mutex_unlock(&wm8994->accdet_lock);
3242
3243 return IRQ_HANDLED;
3244 }
3245
3246 /**
3247 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3248 *
3249 * @codec: WM8958 codec
3250 * @jack: jack to report detection events on
3251 *
3252 * Enable microphone detection functionality for the WM8958. By
3253 * default simple detection which supports the detection of up to 6
3254 * buttons plus video and microphone functionality is supported.
3255 *
3256 * The WM8958 has an advanced jack detection facility which is able to
3257 * support complex accessory detection, especially when used in
3258 * conjunction with external circuitry. In order to provide maximum
3259 * flexiblity a callback is provided which allows a completely custom
3260 * detection algorithm.
3261 */
3262 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3263 wm8958_micdet_cb cb, void *cb_data)
3264 {
3265 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3266 struct wm8994 *control = wm8994->wm8994;
3267 u16 micd_lvl_sel;
3268
3269 switch (control->type) {
3270 case WM1811:
3271 case WM8958:
3272 break;
3273 default:
3274 return -EINVAL;
3275 }
3276
3277 if (jack) {
3278 if (!cb) {
3279 dev_dbg(codec->dev, "Using default micdet callback\n");
3280 cb = wm8958_default_micdet;
3281 cb_data = codec;
3282 }
3283
3284 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3285
3286 wm8994->micdet[0].jack = jack;
3287 wm8994->jack_cb = cb;
3288 wm8994->jack_cb_data = cb_data;
3289
3290 wm8994->mic_detecting = true;
3291 wm8994->jack_mic = false;
3292
3293 wm8958_micd_set_rate(codec);
3294
3295 /* Detect microphones and short circuits by default */
3296 if (wm8994->pdata->micd_lvl_sel)
3297 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3298 else
3299 micd_lvl_sel = 0x41;
3300
3301 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3302 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3303 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3304
3305 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3306 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3307
3308 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3309
3310 /*
3311 * If we can use jack detection start off with that,
3312 * otherwise jump straight to microphone detection.
3313 */
3314 if (wm8994->jackdet) {
3315 snd_soc_update_bits(codec, WM8994_LDO_1,
3316 WM8994_LDO1_DISCH, 0);
3317 wm1811_jackdet_set_mode(codec,
3318 WM1811_JACKDET_MODE_JACK);
3319 } else {
3320 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3321 WM8958_MICD_ENA, WM8958_MICD_ENA);
3322 }
3323
3324 } else {
3325 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3326 WM8958_MICD_ENA, 0);
3327 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3328 }
3329
3330 return 0;
3331 }
3332 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3333
3334 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3335 {
3336 struct wm8994_priv *wm8994 = data;
3337 struct snd_soc_codec *codec = wm8994->codec;
3338 int reg, count;
3339
3340 mutex_lock(&wm8994->accdet_lock);
3341
3342 /*
3343 * Jack detection may have detected a removal simulataneously
3344 * with an update of the MICDET status; if so it will have
3345 * stopped detection and we can ignore this interrupt.
3346 */
3347 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3348 mutex_unlock(&wm8994->accdet_lock);
3349 return IRQ_HANDLED;
3350 }
3351
3352 /* We may occasionally read a detection without an impedence
3353 * range being provided - if that happens loop again.
3354 */
3355 count = 10;
3356 do {
3357 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3358 if (reg < 0) {
3359 mutex_unlock(&wm8994->accdet_lock);
3360 dev_err(codec->dev,
3361 "Failed to read mic detect status: %d\n",
3362 reg);
3363 return IRQ_NONE;
3364 }
3365
3366 if (!(reg & WM8958_MICD_VALID)) {
3367 dev_dbg(codec->dev, "Mic detect data not valid\n");
3368 goto out;
3369 }
3370
3371 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3372 break;
3373
3374 msleep(1);
3375 } while (count--);
3376
3377 if (count == 0)
3378 dev_warn(codec->dev, "No impedence range reported for jack\n");
3379
3380 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3381 trace_snd_soc_jack_irq(dev_name(codec->dev));
3382 #endif
3383
3384 if (wm8994->jack_cb)
3385 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3386 else
3387 dev_warn(codec->dev, "Accessory detection with no callback\n");
3388
3389 out:
3390 mutex_unlock(&wm8994->accdet_lock);
3391
3392 return IRQ_HANDLED;
3393 }
3394
3395 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3396 {
3397 struct snd_soc_codec *codec = data;
3398
3399 dev_err(codec->dev, "FIFO error\n");
3400
3401 return IRQ_HANDLED;
3402 }
3403
3404 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3405 {
3406 struct snd_soc_codec *codec = data;
3407
3408 dev_err(codec->dev, "Thermal warning\n");
3409
3410 return IRQ_HANDLED;
3411 }
3412
3413 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3414 {
3415 struct snd_soc_codec *codec = data;
3416
3417 dev_crit(codec->dev, "Thermal shutdown\n");
3418
3419 return IRQ_HANDLED;
3420 }
3421
3422 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3423 {
3424 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3425 struct wm8994_priv *wm8994;
3426 struct snd_soc_dapm_context *dapm = &codec->dapm;
3427 unsigned int reg;
3428 int ret, i;
3429
3430 codec->control_data = control->regmap;
3431
3432 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3433 GFP_KERNEL);
3434 if (wm8994 == NULL)
3435 return -ENOMEM;
3436 snd_soc_codec_set_drvdata(codec, wm8994);
3437
3438 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3439
3440 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3441 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3442 wm8994->codec = codec;
3443
3444 mutex_init(&wm8994->accdet_lock);
3445
3446 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3447 init_completion(&wm8994->fll_locked[i]);
3448
3449 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3450 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3451 else if (wm8994->pdata && wm8994->pdata->irq_base)
3452 wm8994->micdet_irq = wm8994->pdata->irq_base +
3453 WM8994_IRQ_MIC1_DET;
3454
3455 pm_runtime_enable(codec->dev);
3456 pm_runtime_idle(codec->dev);
3457
3458 /* By default use idle_bias_off, will override for WM8994 */
3459 codec->dapm.idle_bias_off = 1;
3460
3461 /* Set revision-specific configuration */
3462 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3463 switch (control->type) {
3464 case WM8994:
3465 /* Single ended line outputs should have VMID on. */
3466 if (!wm8994->pdata->lineout1_diff ||
3467 !wm8994->pdata->lineout2_diff)
3468 codec->dapm.idle_bias_off = 0;
3469
3470 switch (wm8994->revision) {
3471 case 2:
3472 case 3:
3473 wm8994->hubs.dcs_codes_l = -5;
3474 wm8994->hubs.dcs_codes_r = -5;
3475 wm8994->hubs.hp_startup_mode = 1;
3476 wm8994->hubs.dcs_readback_mode = 1;
3477 wm8994->hubs.series_startup = 1;
3478 break;
3479 default:
3480 wm8994->hubs.dcs_readback_mode = 2;
3481 break;
3482 }
3483 break;
3484
3485 case WM8958:
3486 wm8994->hubs.dcs_readback_mode = 1;
3487 break;
3488
3489 case WM1811:
3490 wm8994->hubs.dcs_readback_mode = 2;
3491 wm8994->hubs.no_series_update = 1;
3492
3493 switch (wm8994->revision) {
3494 case 0:
3495 case 1:
3496 case 2:
3497 case 3:
3498 wm8994->hubs.dcs_codes_l = -9;
3499 wm8994->hubs.dcs_codes_r = -5;
3500 break;
3501 default:
3502 break;
3503 }
3504
3505 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3506 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3507 break;
3508
3509 default:
3510 break;
3511 }
3512
3513 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3514 wm8994_fifo_error, "FIFO error", codec);
3515 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3516 wm8994_temp_warn, "Thermal warning", codec);
3517 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3518 wm8994_temp_shut, "Thermal shutdown", codec);
3519
3520 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3521 wm_hubs_dcs_done, "DC servo done",
3522 &wm8994->hubs);
3523 if (ret == 0)
3524 wm8994->hubs.dcs_done_irq = true;
3525
3526 switch (control->type) {
3527 case WM8994:
3528 if (wm8994->micdet_irq) {
3529 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3530 wm8994_mic_irq,
3531 IRQF_TRIGGER_RISING,
3532 "Mic1 detect",
3533 wm8994);
3534 if (ret != 0)
3535 dev_warn(codec->dev,
3536 "Failed to request Mic1 detect IRQ: %d\n",
3537 ret);
3538 }
3539
3540 ret = wm8994_request_irq(wm8994->wm8994,
3541 WM8994_IRQ_MIC1_SHRT,
3542 wm8994_mic_irq, "Mic 1 short",
3543 wm8994);
3544 if (ret != 0)
3545 dev_warn(codec->dev,
3546 "Failed to request Mic1 short IRQ: %d\n",
3547 ret);
3548
3549 ret = wm8994_request_irq(wm8994->wm8994,
3550 WM8994_IRQ_MIC2_DET,
3551 wm8994_mic_irq, "Mic 2 detect",
3552 wm8994);
3553 if (ret != 0)
3554 dev_warn(codec->dev,
3555 "Failed to request Mic2 detect IRQ: %d\n",
3556 ret);
3557
3558 ret = wm8994_request_irq(wm8994->wm8994,
3559 WM8994_IRQ_MIC2_SHRT,
3560 wm8994_mic_irq, "Mic 2 short",
3561 wm8994);
3562 if (ret != 0)
3563 dev_warn(codec->dev,
3564 "Failed to request Mic2 short IRQ: %d\n",
3565 ret);
3566 break;
3567
3568 case WM8958:
3569 case WM1811:
3570 if (wm8994->micdet_irq) {
3571 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3572 wm8958_mic_irq,
3573 IRQF_TRIGGER_RISING,
3574 "Mic detect",
3575 wm8994);
3576 if (ret != 0)
3577 dev_warn(codec->dev,
3578 "Failed to request Mic detect IRQ: %d\n",
3579 ret);
3580 }
3581 }
3582
3583 switch (control->type) {
3584 case WM1811:
3585 if (wm8994->revision > 1) {
3586 ret = wm8994_request_irq(wm8994->wm8994,
3587 WM8994_IRQ_GPIO(6),
3588 wm1811_jackdet_irq, "JACKDET",
3589 wm8994);
3590 if (ret == 0)
3591 wm8994->jackdet = true;
3592 }
3593 break;
3594 default:
3595 break;
3596 }
3597
3598 wm8994->fll_locked_irq = true;
3599 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3600 ret = wm8994_request_irq(wm8994->wm8994,
3601 WM8994_IRQ_FLL1_LOCK + i,
3602 wm8994_fll_locked_irq, "FLL lock",
3603 &wm8994->fll_locked[i]);
3604 if (ret != 0)
3605 wm8994->fll_locked_irq = false;
3606 }
3607
3608 /* Make sure we can read from the GPIOs if they're inputs */
3609 pm_runtime_get_sync(codec->dev);
3610
3611 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3612 * configured on init - if a system wants to do this dynamically
3613 * at runtime we can deal with that then.
3614 */
3615 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3616 if (ret < 0) {
3617 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3618 goto err_irq;
3619 }
3620 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3621 wm8994->lrclk_shared[0] = 1;
3622 wm8994_dai[0].symmetric_rates = 1;
3623 } else {
3624 wm8994->lrclk_shared[0] = 0;
3625 }
3626
3627 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3628 if (ret < 0) {
3629 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3630 goto err_irq;
3631 }
3632 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3633 wm8994->lrclk_shared[1] = 1;
3634 wm8994_dai[1].symmetric_rates = 1;
3635 } else {
3636 wm8994->lrclk_shared[1] = 0;
3637 }
3638
3639 pm_runtime_put(codec->dev);
3640
3641 /* Latch volume updates (right only; we always do left then right). */
3642 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3643 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3644 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3645 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3646 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3647 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3648 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3649 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3650 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3651 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3652 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3653 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3654 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3655 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3656 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3657 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3658 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3659 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3660 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3661 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3662 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3663 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3664 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3665 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3666 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3667 WM8994_DAC1_VU, WM8994_DAC1_VU);
3668 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3669 WM8994_DAC1_VU, WM8994_DAC1_VU);
3670 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3671 WM8994_DAC2_VU, WM8994_DAC2_VU);
3672 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3673 WM8994_DAC2_VU, WM8994_DAC2_VU);
3674
3675 /* Set the low bit of the 3D stereo depth so TLV matches */
3676 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3677 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3678 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3679 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3680 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3681 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3682 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3683 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3684 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3685
3686 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3687 * use this; it only affects behaviour on idle TDM clock
3688 * cycles. */
3689 switch (control->type) {
3690 case WM8994:
3691 case WM8958:
3692 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3693 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3694 break;
3695 default:
3696 break;
3697 }
3698
3699 /* Put MICBIAS into bypass mode by default on newer devices */
3700 switch (control->type) {
3701 case WM8958:
3702 case WM1811:
3703 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3704 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3705 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3706 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3707 break;
3708 default:
3709 break;
3710 }
3711
3712 wm8994_update_class_w(codec);
3713
3714 wm8994_handle_pdata(wm8994);
3715
3716 wm_hubs_add_analogue_controls(codec);
3717 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3718 ARRAY_SIZE(wm8994_snd_controls));
3719 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3720 ARRAY_SIZE(wm8994_dapm_widgets));
3721
3722 switch (control->type) {
3723 case WM8994:
3724 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3725 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3726 if (wm8994->revision < 4) {
3727 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3728 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3729 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3730 ARRAY_SIZE(wm8994_adc_revd_widgets));
3731 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3732 ARRAY_SIZE(wm8994_dac_revd_widgets));
3733 } else {
3734 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3735 ARRAY_SIZE(wm8994_lateclk_widgets));
3736 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3737 ARRAY_SIZE(wm8994_adc_widgets));
3738 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3739 ARRAY_SIZE(wm8994_dac_widgets));
3740 }
3741 break;
3742 case WM8958:
3743 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3744 ARRAY_SIZE(wm8958_snd_controls));
3745 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3746 ARRAY_SIZE(wm8958_dapm_widgets));
3747 if (wm8994->revision < 1) {
3748 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3749 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3750 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3751 ARRAY_SIZE(wm8994_adc_revd_widgets));
3752 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3753 ARRAY_SIZE(wm8994_dac_revd_widgets));
3754 } else {
3755 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3756 ARRAY_SIZE(wm8994_lateclk_widgets));
3757 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3758 ARRAY_SIZE(wm8994_adc_widgets));
3759 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3760 ARRAY_SIZE(wm8994_dac_widgets));
3761 }
3762 break;
3763
3764 case WM1811:
3765 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3766 ARRAY_SIZE(wm8958_snd_controls));
3767 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3768 ARRAY_SIZE(wm8958_dapm_widgets));
3769 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3770 ARRAY_SIZE(wm8994_lateclk_widgets));
3771 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3772 ARRAY_SIZE(wm8994_adc_widgets));
3773 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3774 ARRAY_SIZE(wm8994_dac_widgets));
3775 break;
3776 }
3777
3778
3779 wm_hubs_add_analogue_routes(codec, 0, 0);
3780 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3781
3782 switch (control->type) {
3783 case WM8994:
3784 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3785 ARRAY_SIZE(wm8994_intercon));
3786
3787 if (wm8994->revision < 4) {
3788 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3789 ARRAY_SIZE(wm8994_revd_intercon));
3790 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3791 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3792 } else {
3793 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3794 ARRAY_SIZE(wm8994_lateclk_intercon));
3795 }
3796 break;
3797 case WM8958:
3798 if (wm8994->revision < 1) {
3799 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3800 ARRAY_SIZE(wm8994_revd_intercon));
3801 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3802 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3803 } else {
3804 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3805 ARRAY_SIZE(wm8994_lateclk_intercon));
3806 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3807 ARRAY_SIZE(wm8958_intercon));
3808 }
3809
3810 wm8958_dsp2_init(codec);
3811 break;
3812 case WM1811:
3813 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3814 ARRAY_SIZE(wm8994_lateclk_intercon));
3815 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3816 ARRAY_SIZE(wm8958_intercon));
3817 break;
3818 }
3819
3820 return 0;
3821
3822 err_irq:
3823 if (wm8994->jackdet)
3824 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3825 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3826 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3827 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3828 if (wm8994->micdet_irq)
3829 free_irq(wm8994->micdet_irq, wm8994);
3830 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3831 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3832 &wm8994->fll_locked[i]);
3833 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3834 &wm8994->hubs);
3835 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3836 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3837 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3838
3839 return ret;
3840 }
3841
3842 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3843 {
3844 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3845 struct wm8994 *control = wm8994->wm8994;
3846 int i;
3847
3848 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3849
3850 pm_runtime_disable(codec->dev);
3851
3852 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3853 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3854 &wm8994->fll_locked[i]);
3855
3856 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3857 &wm8994->hubs);
3858 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3859 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3860 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3861
3862 if (wm8994->jackdet)
3863 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3864
3865 switch (control->type) {
3866 case WM8994:
3867 if (wm8994->micdet_irq)
3868 free_irq(wm8994->micdet_irq, wm8994);
3869 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3870 wm8994);
3871 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3872 wm8994);
3873 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3874 wm8994);
3875 break;
3876
3877 case WM1811:
3878 case WM8958:
3879 if (wm8994->micdet_irq)
3880 free_irq(wm8994->micdet_irq, wm8994);
3881 break;
3882 }
3883 if (wm8994->mbc)
3884 release_firmware(wm8994->mbc);
3885 if (wm8994->mbc_vss)
3886 release_firmware(wm8994->mbc_vss);
3887 if (wm8994->enh_eq)
3888 release_firmware(wm8994->enh_eq);
3889 kfree(wm8994->retune_mobile_texts);
3890
3891 return 0;
3892 }
3893
3894 static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3895 unsigned int reg)
3896 {
3897 return true;
3898 }
3899
3900 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3901 .probe = wm8994_codec_probe,
3902 .remove = wm8994_codec_remove,
3903 .suspend = wm8994_suspend,
3904 .resume = wm8994_resume,
3905 .set_bias_level = wm8994_set_bias_level,
3906 .reg_cache_size = WM8994_MAX_REGISTER,
3907 .volatile_register = wm8994_soc_volatile,
3908 };
3909
3910 static int __devinit wm8994_probe(struct platform_device *pdev)
3911 {
3912 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3913 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3914 }
3915
3916 static int __devexit wm8994_remove(struct platform_device *pdev)
3917 {
3918 snd_soc_unregister_codec(&pdev->dev);
3919 return 0;
3920 }
3921
3922 static struct platform_driver wm8994_codec_driver = {
3923 .driver = {
3924 .name = "wm8994-codec",
3925 .owner = THIS_MODULE,
3926 },
3927 .probe = wm8994_probe,
3928 .remove = __devexit_p(wm8994_remove),
3929 };
3930
3931 module_platform_driver(wm8994_codec_driver);
3932
3933 MODULE_DESCRIPTION("ASoC WM8994 driver");
3934 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3935 MODULE_LICENSE("GPL");
3936 MODULE_ALIAS("platform:wm8994-codec");
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