2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
50 static int wm8994_drc_base
[] = {
56 static int wm8994_retune_mobile_base
[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1
,
58 WM8994_AIF1_DAC2_EQ_GAINS_1
,
59 WM8994_AIF2_EQ_GAINS_1
,
62 struct wm8994_micdet
{
63 struct snd_soc_jack
*jack
;
68 /* codec private data */
70 struct wm_hubs_data hubs
;
71 enum snd_soc_control_type control_type
;
73 struct snd_soc_codec
*codec
;
78 struct fll_config fll
[2], fll_suspend
[2];
85 /* Platform dependant DRC configuration */
86 const char **drc_texts
;
87 int drc_cfg
[WM8994_NUM_DRC
];
88 struct soc_enum drc_enum
;
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts
;
92 const char **retune_mobile_texts
;
93 int retune_mobile_cfg
[WM8994_NUM_EQ
];
94 struct soc_enum retune_mobile_enum
;
96 /* Platform dependant MBC configuration */
98 const char **mbc_texts
;
99 struct soc_enum mbc_enum
;
101 struct wm8994_micdet micdet
[2];
103 wm8958_micdet_cb jack_cb
;
109 struct wm8994_pdata
*pdata
;
111 unsigned int aif1clk_enable
:1;
112 unsigned int aif2clk_enable
:1;
114 unsigned int aif1clk_disable
:1;
115 unsigned int aif2clk_disable
:1;
118 static int wm8994_readable(unsigned int reg
)
132 case WM8994_INTERRUPT_STATUS_1
:
133 case WM8994_INTERRUPT_STATUS_2
:
134 case WM8994_INTERRUPT_RAW_STATUS_2
:
140 if (reg
>= WM8994_CACHE_SIZE
)
142 return wm8994_access_masks
[reg
].readable
!= 0;
145 static int wm8994_volatile(unsigned int reg
)
147 if (reg
>= WM8994_CACHE_SIZE
)
151 case WM8994_SOFTWARE_RESET
:
152 case WM8994_CHIP_REVISION
:
153 case WM8994_DC_SERVO_1
:
154 case WM8994_DC_SERVO_READBACK
:
155 case WM8994_RATE_STATUS
:
158 case WM8958_DSP2_EXECCONTROL
:
159 case WM8958_MIC_DETECT_3
:
166 static int wm8994_write(struct snd_soc_codec
*codec
, unsigned int reg
,
171 BUG_ON(reg
> WM8994_MAX_REGISTER
);
173 if (!wm8994_volatile(reg
)) {
174 ret
= snd_soc_cache_write(codec
, reg
, value
);
176 dev_err(codec
->dev
, "Cache write to %x failed: %d\n",
180 return wm8994_reg_write(codec
->control_data
, reg
, value
);
183 static unsigned int wm8994_read(struct snd_soc_codec
*codec
,
189 BUG_ON(reg
> WM8994_MAX_REGISTER
);
191 if (!wm8994_volatile(reg
) && wm8994_readable(reg
) &&
192 reg
< codec
->driver
->reg_cache_size
) {
193 ret
= snd_soc_cache_read(codec
, reg
, &val
);
197 dev_err(codec
->dev
, "Cache read from %x failed: %d\n",
201 return wm8994_reg_read(codec
->control_data
, reg
);
204 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
206 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
216 switch (wm8994
->sysclk
[aif
]) {
217 case WM8994_SYSCLK_MCLK1
:
218 rate
= wm8994
->mclk
[0];
221 case WM8994_SYSCLK_MCLK2
:
223 rate
= wm8994
->mclk
[1];
226 case WM8994_SYSCLK_FLL1
:
228 rate
= wm8994
->fll
[0].out
;
231 case WM8994_SYSCLK_FLL2
:
233 rate
= wm8994
->fll
[1].out
;
240 if (rate
>= 13500000) {
242 reg1
|= WM8994_AIF1CLK_DIV
;
244 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
248 if (rate
&& rate
< 3000000)
249 dev_warn(codec
->dev
, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
252 wm8994
->aifclk
[aif
] = rate
;
254 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
255 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
261 static int configure_clock(struct snd_soc_codec
*codec
)
263 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
266 /* Bring up the AIF clocks first */
267 configure_aif_clock(codec
, 0);
268 configure_aif_clock(codec
, 1);
270 /* Then switch CLK_SYS over to the higher of them; a change
271 * can only happen as a result of a clocking change which can
272 * only be made outside of DAPM so we can safely redo the
276 /* If they're equal it doesn't matter which is used */
277 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1])
280 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
281 new = WM8994_SYSCLK_SRC
;
285 old
= snd_soc_read(codec
, WM8994_CLOCKING_1
) & WM8994_SYSCLK_SRC
;
287 /* If there's no change then we're done. */
291 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
, WM8994_SYSCLK_SRC
, new);
293 snd_soc_dapm_sync(&codec
->dapm
);
298 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
299 struct snd_soc_dapm_widget
*sink
)
301 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
304 /* Check what we're currently using for CLK_SYS */
305 if (reg
& WM8994_SYSCLK_SRC
)
310 return strcmp(source
->name
, clk
) == 0;
313 static const char *sidetone_hpf_text
[] = {
314 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
317 static const struct soc_enum sidetone_hpf
=
318 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
320 static const char *adc_hpf_text
[] = {
321 "HiFi", "Voice 1", "Voice 2", "Voice 3"
324 static const struct soc_enum aif1adc1_hpf
=
325 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
327 static const struct soc_enum aif1adc2_hpf
=
328 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
330 static const struct soc_enum aif2adc_hpf
=
331 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
333 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
334 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
335 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
336 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
337 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
339 #define WM8994_DRC_SWITCH(xname, reg, shift) \
340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
341 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
342 .put = wm8994_put_drc_sw, \
343 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
345 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
346 struct snd_ctl_elem_value
*ucontrol
)
348 struct soc_mixer_control
*mc
=
349 (struct soc_mixer_control
*)kcontrol
->private_value
;
350 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
353 /* Can't enable both ADC and DAC paths simultaneously */
354 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
355 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
356 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
358 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
360 ret
= snd_soc_read(codec
, mc
->reg
);
366 return snd_soc_put_volsw(kcontrol
, ucontrol
);
369 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
371 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
372 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
373 int base
= wm8994_drc_base
[drc
];
374 int cfg
= wm8994
->drc_cfg
[drc
];
377 /* Save any enables; the configuration should clear them. */
378 save
= snd_soc_read(codec
, base
);
379 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
380 WM8994_AIF1ADC1R_DRC_ENA
;
382 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
383 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
384 pdata
->drc_cfgs
[cfg
].regs
[i
]);
386 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
387 WM8994_AIF1ADC1L_DRC_ENA
|
388 WM8994_AIF1ADC1R_DRC_ENA
, save
);
391 /* Icky as hell but saves code duplication */
392 static int wm8994_get_drc(const char *name
)
394 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
396 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
398 if (strcmp(name
, "AIF2DRC Mode") == 0)
403 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
404 struct snd_ctl_elem_value
*ucontrol
)
406 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
407 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
408 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
409 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
410 int value
= ucontrol
->value
.integer
.value
[0];
415 if (value
>= pdata
->num_drc_cfgs
)
418 wm8994
->drc_cfg
[drc
] = value
;
420 wm8994_set_drc(codec
, drc
);
425 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
426 struct snd_ctl_elem_value
*ucontrol
)
428 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
429 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
430 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
432 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
437 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
439 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
440 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
441 int base
= wm8994_retune_mobile_base
[block
];
442 int iface
, best
, best_val
, save
, i
, cfg
;
444 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
459 /* Find the version of the currently selected configuration
460 * with the nearest sample rate. */
461 cfg
= wm8994
->retune_mobile_cfg
[block
];
464 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
465 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
466 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
467 abs(pdata
->retune_mobile_cfgs
[i
].rate
468 - wm8994
->dac_rates
[iface
]) < best_val
) {
470 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
471 - wm8994
->dac_rates
[iface
]);
475 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
477 pdata
->retune_mobile_cfgs
[best
].name
,
478 pdata
->retune_mobile_cfgs
[best
].rate
,
479 wm8994
->dac_rates
[iface
]);
481 /* The EQ will be disabled while reconfiguring it, remember the
482 * current configuration.
484 save
= snd_soc_read(codec
, base
);
485 save
&= WM8994_AIF1DAC1_EQ_ENA
;
487 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
488 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
489 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
491 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
494 /* Icky as hell but saves code duplication */
495 static int wm8994_get_retune_mobile_block(const char *name
)
497 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
499 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
501 if (strcmp(name
, "AIF2 EQ Mode") == 0)
506 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
507 struct snd_ctl_elem_value
*ucontrol
)
509 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
510 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
511 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
512 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
513 int value
= ucontrol
->value
.integer
.value
[0];
518 if (value
>= pdata
->num_retune_mobile_cfgs
)
521 wm8994
->retune_mobile_cfg
[block
] = value
;
523 wm8994_set_retune_mobile(codec
, block
);
528 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
529 struct snd_ctl_elem_value
*ucontrol
)
531 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
532 struct wm8994_priv
*wm8994
=snd_soc_codec_get_drvdata(codec
);
533 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
535 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
540 static const char *aif_chan_src_text
[] = {
544 static const struct soc_enum aif1adcl_src
=
545 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
547 static const struct soc_enum aif1adcr_src
=
548 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
550 static const struct soc_enum aif2adcl_src
=
551 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
553 static const struct soc_enum aif2adcr_src
=
554 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
556 static const struct soc_enum aif1dacl_src
=
557 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
559 static const struct soc_enum aif1dacr_src
=
560 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
562 static const struct soc_enum aif2dacl_src
=
563 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
565 static const struct soc_enum aif2dacr_src
=
566 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
568 static const char *osr_text
[] = {
569 "Low Power", "High Performance",
572 static const struct soc_enum dac_osr
=
573 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
575 static const struct soc_enum adc_osr
=
576 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
578 static void wm8958_mbc_apply(struct snd_soc_codec
*codec
, int mbc
, int start
)
580 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
581 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
582 int pwr_reg
= snd_soc_read(codec
, WM8994_POWER_MANAGEMENT_5
);
583 int ena
, reg
, aif
, i
;
587 pwr_reg
&= (WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
);
591 pwr_reg
&= (WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
);
595 pwr_reg
&= (WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
);
603 /* We can only enable the MBC if the AIF is enabled and we
604 * want it to be enabled. */
605 ena
= pwr_reg
&& wm8994
->mbc_ena
[mbc
];
607 reg
= snd_soc_read(codec
, WM8958_DSP2_PROGRAM
);
609 dev_dbg(codec
->dev
, "MBC %d startup: %d, power: %x, DSP: %x\n",
610 mbc
, start
, pwr_reg
, reg
);
613 /* If the DSP is already running then noop */
614 if (reg
& WM8958_DSP2_ENA
)
617 /* Switch the clock over to the appropriate AIF */
618 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
619 WM8958_DSP2CLK_SRC
| WM8958_DSP2CLK_ENA
,
620 aif
<< WM8958_DSP2CLK_SRC_SHIFT
|
623 snd_soc_update_bits(codec
, WM8958_DSP2_PROGRAM
,
624 WM8958_DSP2_ENA
, WM8958_DSP2_ENA
);
626 /* If we've got user supplied MBC settings use them */
627 if (pdata
&& pdata
->num_mbc_cfgs
) {
628 struct wm8958_mbc_cfg
*cfg
629 = &pdata
->mbc_cfgs
[wm8994
->mbc_cfg
];
631 for (i
= 0; i
< ARRAY_SIZE(cfg
->coeff_regs
); i
++)
632 snd_soc_write(codec
, i
+ WM8958_MBC_BAND_1_K_1
,
635 for (i
= 0; i
< ARRAY_SIZE(cfg
->cutoff_regs
); i
++)
637 i
+ WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1
,
638 cfg
->cutoff_regs
[i
]);
642 snd_soc_write(codec
, WM8958_DSP2_EXECCONTROL
,
646 snd_soc_update_bits(codec
, WM8958_DSP2_CONFIG
,
647 WM8958_MBC_ENA
| WM8958_MBC_SEL_MASK
,
648 mbc
<< WM8958_MBC_SEL_SHIFT
|
651 /* If the DSP is already stopped then noop */
652 if (!(reg
& WM8958_DSP2_ENA
))
655 snd_soc_update_bits(codec
, WM8958_DSP2_CONFIG
,
657 snd_soc_update_bits(codec
, WM8958_DSP2_PROGRAM
,
659 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
660 WM8958_DSP2CLK_ENA
, 0);
664 static int wm8958_aif_ev(struct snd_soc_dapm_widget
*w
,
665 struct snd_kcontrol
*kcontrol
, int event
)
667 struct snd_soc_codec
*codec
= w
->codec
;
689 case SND_SOC_DAPM_POST_PMU
:
690 wm8958_mbc_apply(codec
, mbc
, 1);
692 case SND_SOC_DAPM_POST_PMD
:
693 wm8958_mbc_apply(codec
, mbc
, 0);
700 static int wm8958_put_mbc_enum(struct snd_kcontrol
*kcontrol
,
701 struct snd_ctl_elem_value
*ucontrol
)
703 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
704 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
705 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
706 int value
= ucontrol
->value
.integer
.value
[0];
709 /* Don't allow on the fly reconfiguration */
710 reg
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
711 if (reg
< 0 || reg
& WM8958_DSP2CLK_ENA
)
714 if (value
>= pdata
->num_mbc_cfgs
)
717 wm8994
->mbc_cfg
= value
;
722 static int wm8958_get_mbc_enum(struct snd_kcontrol
*kcontrol
,
723 struct snd_ctl_elem_value
*ucontrol
)
725 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
726 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
728 ucontrol
->value
.enumerated
.item
[0] = wm8994
->mbc_cfg
;
733 static int wm8958_mbc_info(struct snd_kcontrol
*kcontrol
,
734 struct snd_ctl_elem_info
*uinfo
)
736 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
738 uinfo
->value
.integer
.min
= 0;
739 uinfo
->value
.integer
.max
= 1;
743 static int wm8958_mbc_get(struct snd_kcontrol
*kcontrol
,
744 struct snd_ctl_elem_value
*ucontrol
)
746 int mbc
= kcontrol
->private_value
;
747 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
748 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
750 ucontrol
->value
.integer
.value
[0] = wm8994
->mbc_ena
[mbc
];
755 static int wm8958_mbc_put(struct snd_kcontrol
*kcontrol
,
756 struct snd_ctl_elem_value
*ucontrol
)
758 int mbc
= kcontrol
->private_value
;
760 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
761 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
763 if (ucontrol
->value
.integer
.value
[0] > 1)
766 for (i
= 0; i
< ARRAY_SIZE(wm8994
->mbc_ena
); i
++) {
767 if (mbc
!= i
&& wm8994
->mbc_ena
[i
]) {
768 dev_dbg(codec
->dev
, "MBC %d active already\n", mbc
);
773 wm8994
->mbc_ena
[mbc
] = ucontrol
->value
.integer
.value
[0];
775 wm8958_mbc_apply(codec
, mbc
, wm8994
->mbc_ena
[mbc
]);
780 #define WM8958_MBC_SWITCH(xname, xval) {\
781 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
782 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
783 .info = wm8958_mbc_info, \
784 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
785 .private_value = xval }
787 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
788 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
789 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
790 1, 119, 0, digital_tlv
),
791 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
792 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
793 1, 119, 0, digital_tlv
),
794 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
795 WM8994_AIF2_ADC_RIGHT_VOLUME
,
796 1, 119, 0, digital_tlv
),
798 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
799 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
800 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
801 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
803 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
804 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
805 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
806 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
808 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
809 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
810 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
811 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
812 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
813 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
815 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
816 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
818 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
819 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
820 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
822 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
823 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
824 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
826 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
827 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
828 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
830 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
831 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
832 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
834 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
836 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
838 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
840 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
842 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
843 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
845 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
846 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
848 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
849 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
851 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
852 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
854 SOC_ENUM("ADC OSR", adc_osr
),
855 SOC_ENUM("DAC OSR", dac_osr
),
857 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
858 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
859 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
860 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
862 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
863 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
864 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
865 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
867 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
868 6, 1, 1, wm_hubs_spkmix_tlv
),
869 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
870 2, 1, 1, wm_hubs_spkmix_tlv
),
872 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
873 6, 1, 1, wm_hubs_spkmix_tlv
),
874 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
875 2, 1, 1, wm_hubs_spkmix_tlv
),
877 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
878 10, 15, 0, wm8994_3d_tlv
),
879 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
881 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
882 10, 15, 0, wm8994_3d_tlv
),
883 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
885 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
886 10, 15, 0, wm8994_3d_tlv
),
887 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
891 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
892 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
894 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
896 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
898 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
900 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
903 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
905 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
907 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
909 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
911 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
914 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
916 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
918 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
920 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
922 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
926 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
927 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
928 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
929 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
930 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
933 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
934 struct snd_kcontrol
*kcontrol
, int event
)
936 struct snd_soc_codec
*codec
= w
->codec
;
939 case SND_SOC_DAPM_PRE_PMU
:
940 return configure_clock(codec
);
942 case SND_SOC_DAPM_POST_PMD
:
943 configure_clock(codec
);
950 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
952 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
954 int source
= 0; /* GCC flow analysis can't track enable */
957 /* Only support direct DAC->headphone paths */
958 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
959 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
960 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
964 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
965 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
966 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
970 /* We also need the same setting for L/R and only one path */
971 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
973 case WM8994_AIF2DACL_TO_DAC1L
:
974 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
975 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
977 case WM8994_AIF1DAC2L_TO_DAC1L
:
978 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
979 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
981 case WM8994_AIF1DAC1L_TO_DAC1L
:
982 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
983 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
986 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
991 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
993 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
998 dev_dbg(codec
->dev
, "Class W enabled\n");
999 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1001 WM8994_CP_DYN_SRC_SEL_MASK
,
1002 source
| WM8994_CP_DYN_PWR
);
1003 wm8994
->hubs
.class_w
= true;
1006 dev_dbg(codec
->dev
, "Class W disabled\n");
1007 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1008 WM8994_CP_DYN_PWR
, 0);
1009 wm8994
->hubs
.class_w
= false;
1013 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1014 struct snd_kcontrol
*kcontrol
, int event
)
1016 struct snd_soc_codec
*codec
= w
->codec
;
1017 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1020 case SND_SOC_DAPM_PRE_PMU
:
1021 if (wm8994
->aif1clk_enable
) {
1022 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1023 WM8994_AIF1CLK_ENA_MASK
,
1024 WM8994_AIF1CLK_ENA
);
1025 wm8994
->aif1clk_enable
= 0;
1027 if (wm8994
->aif2clk_enable
) {
1028 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1029 WM8994_AIF2CLK_ENA_MASK
,
1030 WM8994_AIF2CLK_ENA
);
1031 wm8994
->aif2clk_enable
= 0;
1039 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1040 struct snd_kcontrol
*kcontrol
, int event
)
1042 struct snd_soc_codec
*codec
= w
->codec
;
1043 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1046 case SND_SOC_DAPM_POST_PMD
:
1047 if (wm8994
->aif1clk_disable
) {
1048 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1049 WM8994_AIF1CLK_ENA_MASK
, 0);
1050 wm8994
->aif1clk_disable
= 0;
1052 if (wm8994
->aif2clk_disable
) {
1053 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1054 WM8994_AIF2CLK_ENA_MASK
, 0);
1055 wm8994
->aif2clk_disable
= 0;
1063 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1064 struct snd_kcontrol
*kcontrol
, int event
)
1066 struct snd_soc_codec
*codec
= w
->codec
;
1067 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1070 case SND_SOC_DAPM_PRE_PMU
:
1071 wm8994
->aif1clk_enable
= 1;
1073 case SND_SOC_DAPM_POST_PMD
:
1074 wm8994
->aif1clk_disable
= 1;
1081 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1082 struct snd_kcontrol
*kcontrol
, int event
)
1084 struct snd_soc_codec
*codec
= w
->codec
;
1085 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1088 case SND_SOC_DAPM_PRE_PMU
:
1089 wm8994
->aif2clk_enable
= 1;
1091 case SND_SOC_DAPM_POST_PMD
:
1092 wm8994
->aif2clk_disable
= 1;
1099 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1100 struct snd_kcontrol
*kcontrol
, int event
)
1102 late_enable_ev(w
, kcontrol
, event
);
1106 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1107 struct snd_kcontrol
*kcontrol
, int event
)
1109 struct snd_soc_codec
*codec
= w
->codec
;
1110 unsigned int mask
= 1 << w
->shift
;
1112 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1117 static const char *hp_mux_text
[] = {
1122 #define WM8994_HP_ENUM(xname, xenum) \
1123 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1124 .info = snd_soc_info_enum_double, \
1125 .get = snd_soc_dapm_get_enum_double, \
1126 .put = wm8994_put_hp_enum, \
1127 .private_value = (unsigned long)&xenum }
1129 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
1130 struct snd_ctl_elem_value
*ucontrol
)
1132 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
1133 struct snd_soc_codec
*codec
= w
->codec
;
1136 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
1138 wm8994_update_class_w(codec
);
1143 static const struct soc_enum hpl_enum
=
1144 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
1146 static const struct snd_kcontrol_new hpl_mux
=
1147 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
1149 static const struct soc_enum hpr_enum
=
1150 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
1152 static const struct snd_kcontrol_new hpr_mux
=
1153 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
1155 static const char *adc_mux_text
[] = {
1160 static const struct soc_enum adc_enum
=
1161 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1163 static const struct snd_kcontrol_new adcl_mux
=
1164 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1166 static const struct snd_kcontrol_new adcr_mux
=
1167 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1169 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1170 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1171 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1172 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1173 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1174 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1177 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1178 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1179 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1180 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1181 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1182 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1185 /* Debugging; dump chip status after DAPM transitions */
1186 static int post_ev(struct snd_soc_dapm_widget
*w
,
1187 struct snd_kcontrol
*kcontrol
, int event
)
1189 struct snd_soc_codec
*codec
= w
->codec
;
1190 dev_dbg(codec
->dev
, "SRC status: %x\n",
1192 WM8994_RATE_STATUS
));
1196 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1197 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1199 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1203 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1204 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1206 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1210 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1211 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1213 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1217 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1218 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1220 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1224 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1225 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1227 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1229 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1231 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1233 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1237 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1238 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1240 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1242 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1244 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1246 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1250 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1251 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1252 .info = snd_soc_info_volsw, \
1253 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1254 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1256 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1257 struct snd_ctl_elem_value
*ucontrol
)
1259 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
1260 struct snd_soc_codec
*codec
= w
->codec
;
1263 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1265 wm8994_update_class_w(codec
);
1270 static const struct snd_kcontrol_new dac1l_mix
[] = {
1271 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1273 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1275 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1277 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1279 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1283 static const struct snd_kcontrol_new dac1r_mix
[] = {
1284 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1286 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1288 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1290 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1292 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1296 static const char *sidetone_text
[] = {
1297 "ADC/DMIC1", "DMIC2",
1300 static const struct soc_enum sidetone1_enum
=
1301 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1303 static const struct snd_kcontrol_new sidetone1_mux
=
1304 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1306 static const struct soc_enum sidetone2_enum
=
1307 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1309 static const struct snd_kcontrol_new sidetone2_mux
=
1310 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1312 static const char *aif1dac_text
[] = {
1313 "AIF1DACDAT", "AIF3DACDAT",
1316 static const struct soc_enum aif1dac_enum
=
1317 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1319 static const struct snd_kcontrol_new aif1dac_mux
=
1320 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1322 static const char *aif2dac_text
[] = {
1323 "AIF2DACDAT", "AIF3DACDAT",
1326 static const struct soc_enum aif2dac_enum
=
1327 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1329 static const struct snd_kcontrol_new aif2dac_mux
=
1330 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1332 static const char *aif2adc_text
[] = {
1333 "AIF2ADCDAT", "AIF3DACDAT",
1336 static const struct soc_enum aif2adc_enum
=
1337 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1339 static const struct snd_kcontrol_new aif2adc_mux
=
1340 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1342 static const char *aif3adc_text
[] = {
1343 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1346 static const struct soc_enum wm8994_aif3adc_enum
=
1347 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1349 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1350 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1352 static const struct soc_enum wm8958_aif3adc_enum
=
1353 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1355 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1356 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1358 static const char *mono_pcm_out_text
[] = {
1359 "None", "AIF2ADCL", "AIF2ADCR",
1362 static const struct soc_enum mono_pcm_out_enum
=
1363 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1365 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1366 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1368 static const char *aif2dac_src_text
[] = {
1372 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1373 static const struct soc_enum aif2dacl_src_enum
=
1374 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1376 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1377 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1379 static const struct soc_enum aif2dacr_src_enum
=
1380 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1382 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1383 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1385 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1386 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_ev
,
1387 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1388 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_ev
,
1389 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1391 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1392 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1393 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1394 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1395 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1396 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1397 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1398 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1400 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1403 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1404 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
1405 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0)
1408 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1409 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1410 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1411 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1412 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1413 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1414 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1415 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1416 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1419 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1420 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1421 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1422 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1423 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1426 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1427 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1428 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1429 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1430 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1433 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1434 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1435 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1438 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1439 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1440 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1441 SND_SOC_DAPM_INPUT("Clock"),
1443 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1444 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1446 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
1447 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
1448 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
1450 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1451 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
1452 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1453 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
1454 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1455 WM8994_POWER_MANAGEMENT_5
, 9, 0, wm8958_aif_ev
,
1456 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1457 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1458 WM8994_POWER_MANAGEMENT_5
, 8, 0, wm8958_aif_ev
,
1459 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1461 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1462 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
1463 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1464 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
1465 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1466 WM8994_POWER_MANAGEMENT_5
, 11, 0, wm8958_aif_ev
,
1467 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1468 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1469 WM8994_POWER_MANAGEMENT_5
, 10, 0, wm8958_aif_ev
,
1470 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1472 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1473 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1474 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1475 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1477 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1478 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1479 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1480 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1482 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1483 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1484 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1485 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1487 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1488 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1490 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1491 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1492 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1493 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1495 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1496 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1497 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1498 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1499 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1500 WM8994_POWER_MANAGEMENT_5
, 13, 0, wm8958_aif_ev
,
1501 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1502 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1503 WM8994_POWER_MANAGEMENT_5
, 12, 0, wm8958_aif_ev
,
1504 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1506 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1507 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1508 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
1509 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1511 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1512 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1513 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1515 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1516 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1518 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1520 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1521 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1522 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1523 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1525 /* Power is done with the muxes since the ADC power also controls the
1526 * downsampling chain, the chip will automatically manage the analogue
1527 * specific portions.
1529 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1530 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1532 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1533 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1535 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1536 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1537 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1538 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1540 SND_SOC_DAPM_POST("Debug log", post_ev
),
1543 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1544 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1547 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1548 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1549 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1550 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1551 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1554 static const struct snd_soc_dapm_route intercon
[] = {
1555 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1556 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1558 { "DSP1CLK", NULL
, "CLK_SYS" },
1559 { "DSP2CLK", NULL
, "CLK_SYS" },
1560 { "DSPINTCLK", NULL
, "CLK_SYS" },
1562 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1563 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1564 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1565 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1566 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1568 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1569 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1570 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1571 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1572 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1574 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1575 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1576 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1577 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1578 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1580 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1581 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1582 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1583 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1584 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1586 { "AIF2ADCL", NULL
, "AIF2CLK" },
1587 { "AIF2ADCL", NULL
, "DSP2CLK" },
1588 { "AIF2ADCR", NULL
, "AIF2CLK" },
1589 { "AIF2ADCR", NULL
, "DSP2CLK" },
1590 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1592 { "AIF2DACL", NULL
, "AIF2CLK" },
1593 { "AIF2DACL", NULL
, "DSP2CLK" },
1594 { "AIF2DACR", NULL
, "AIF2CLK" },
1595 { "AIF2DACR", NULL
, "DSP2CLK" },
1596 { "AIF2DACR", NULL
, "DSPINTCLK" },
1598 { "DMIC1L", NULL
, "DMIC1DAT" },
1599 { "DMIC1L", NULL
, "CLK_SYS" },
1600 { "DMIC1R", NULL
, "DMIC1DAT" },
1601 { "DMIC1R", NULL
, "CLK_SYS" },
1602 { "DMIC2L", NULL
, "DMIC2DAT" },
1603 { "DMIC2L", NULL
, "CLK_SYS" },
1604 { "DMIC2R", NULL
, "DMIC2DAT" },
1605 { "DMIC2R", NULL
, "CLK_SYS" },
1607 { "ADCL", NULL
, "AIF1CLK" },
1608 { "ADCL", NULL
, "DSP1CLK" },
1609 { "ADCL", NULL
, "DSPINTCLK" },
1611 { "ADCR", NULL
, "AIF1CLK" },
1612 { "ADCR", NULL
, "DSP1CLK" },
1613 { "ADCR", NULL
, "DSPINTCLK" },
1615 { "ADCL Mux", "ADC", "ADCL" },
1616 { "ADCL Mux", "DMIC", "DMIC1L" },
1617 { "ADCR Mux", "ADC", "ADCR" },
1618 { "ADCR Mux", "DMIC", "DMIC1R" },
1620 { "DAC1L", NULL
, "AIF1CLK" },
1621 { "DAC1L", NULL
, "DSP1CLK" },
1622 { "DAC1L", NULL
, "DSPINTCLK" },
1624 { "DAC1R", NULL
, "AIF1CLK" },
1625 { "DAC1R", NULL
, "DSP1CLK" },
1626 { "DAC1R", NULL
, "DSPINTCLK" },
1628 { "DAC2L", NULL
, "AIF2CLK" },
1629 { "DAC2L", NULL
, "DSP2CLK" },
1630 { "DAC2L", NULL
, "DSPINTCLK" },
1632 { "DAC2R", NULL
, "AIF2DACR" },
1633 { "DAC2R", NULL
, "AIF2CLK" },
1634 { "DAC2R", NULL
, "DSP2CLK" },
1635 { "DAC2R", NULL
, "DSPINTCLK" },
1637 { "TOCLK", NULL
, "CLK_SYS" },
1640 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1641 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1642 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1644 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1645 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1646 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1648 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1649 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1650 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1652 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1653 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1654 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1656 /* Pin level routing for AIF3 */
1657 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1658 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1659 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1660 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1662 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1663 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1664 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1665 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1666 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1667 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1668 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1671 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1672 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1673 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1674 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1675 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1677 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1678 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1679 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1680 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1681 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1683 /* DAC2/AIF2 outputs */
1684 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1685 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1686 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1687 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1688 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1689 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1691 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1692 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1693 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1694 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1695 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1696 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1698 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1699 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1700 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1701 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1703 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1706 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1707 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1708 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1709 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1710 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1711 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1712 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1713 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1716 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1717 { "Left Sidetone", "DMIC2", "DMIC2L" },
1718 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1719 { "Right Sidetone", "DMIC2", "DMIC2R" },
1722 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1723 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1725 { "SPKL", "DAC1 Switch", "DAC1L" },
1726 { "SPKL", "DAC2 Switch", "DAC2L" },
1728 { "SPKR", "DAC1 Switch", "DAC1R" },
1729 { "SPKR", "DAC2 Switch", "DAC2R" },
1731 { "Left Headphone Mux", "DAC", "DAC1L" },
1732 { "Right Headphone Mux", "DAC", "DAC1R" },
1735 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1736 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1737 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1738 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1739 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1740 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1741 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1742 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1743 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1746 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1747 { "DAC1L", NULL
, "DAC1L Mixer" },
1748 { "DAC1R", NULL
, "DAC1R Mixer" },
1749 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1750 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1753 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1754 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1755 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1756 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1757 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1760 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1761 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1762 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1765 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1766 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1767 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1769 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1770 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1771 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1772 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1774 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1775 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1777 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1780 /* The size in bits of the FLL divide multiplied by 10
1781 * to allow rounding later */
1782 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1792 static int wm8994_get_fll_config(struct fll_div
*fll
,
1793 int freq_in
, int freq_out
)
1796 unsigned int K
, Ndiv
, Nmod
;
1798 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1800 /* Scale the input frequency down to <= 13.5MHz */
1801 fll
->clk_ref_div
= 0;
1802 while (freq_in
> 13500000) {
1806 if (fll
->clk_ref_div
> 3)
1809 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1811 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1813 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1815 if (fll
->outdiv
> 63)
1818 freq_out
*= fll
->outdiv
+ 1;
1819 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1821 if (freq_in
> 1000000) {
1822 fll
->fll_fratio
= 0;
1823 } else if (freq_in
> 256000) {
1824 fll
->fll_fratio
= 1;
1826 } else if (freq_in
> 128000) {
1827 fll
->fll_fratio
= 2;
1829 } else if (freq_in
> 64000) {
1830 fll
->fll_fratio
= 3;
1833 fll
->fll_fratio
= 4;
1836 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1838 /* Now, calculate N.K */
1839 Ndiv
= freq_out
/ freq_in
;
1842 Nmod
= freq_out
% freq_in
;
1843 pr_debug("Nmod=%d\n", Nmod
);
1845 /* Calculate fractional part - scale up so we can round. */
1846 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1848 do_div(Kpart
, freq_in
);
1850 K
= Kpart
& 0xFFFFFFFF;
1855 /* Move down to proper range now rounding is done */
1858 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1863 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1864 unsigned int freq_in
, unsigned int freq_out
)
1866 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1867 int reg_offset
, ret
;
1869 u16 reg
, aif1
, aif2
;
1871 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1872 & WM8994_AIF1CLK_ENA
;
1874 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1875 & WM8994_AIF2CLK_ENA
;
1892 /* Allow no source specification when stopping */
1895 src
= wm8994
->fll
[id
].src
;
1897 case WM8994_FLL_SRC_MCLK1
:
1898 case WM8994_FLL_SRC_MCLK2
:
1899 case WM8994_FLL_SRC_LRCLK
:
1900 case WM8994_FLL_SRC_BCLK
:
1906 /* Are we changing anything? */
1907 if (wm8994
->fll
[id
].src
== src
&&
1908 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1911 /* If we're stopping the FLL redo the old config - no
1912 * registers will actually be written but we avoid GCC flow
1913 * analysis bugs spewing warnings.
1916 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1918 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1919 wm8994
->fll
[id
].out
);
1923 /* Gate the AIF clocks while we reclock */
1924 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1925 WM8994_AIF1CLK_ENA
, 0);
1926 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1927 WM8994_AIF2CLK_ENA
, 0);
1929 /* We always need to disable the FLL while reconfiguring */
1930 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1931 WM8994_FLL1_ENA
, 0);
1933 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1934 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1935 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1936 WM8994_FLL1_OUTDIV_MASK
|
1937 WM8994_FLL1_FRATIO_MASK
, reg
);
1939 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1941 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1943 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1945 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1946 WM8994_FLL1_REFCLK_DIV_MASK
|
1947 WM8994_FLL1_REFCLK_SRC_MASK
,
1948 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
1951 /* Enable (with fractional mode if required) */
1954 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
1956 reg
= WM8994_FLL1_ENA
;
1957 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1958 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
1962 wm8994
->fll
[id
].in
= freq_in
;
1963 wm8994
->fll
[id
].out
= freq_out
;
1964 wm8994
->fll
[id
].src
= src
;
1966 /* Enable any gated AIF clocks */
1967 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1968 WM8994_AIF1CLK_ENA
, aif1
);
1969 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1970 WM8994_AIF2CLK_ENA
, aif2
);
1972 configure_clock(codec
);
1978 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1980 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
1981 unsigned int freq_in
, unsigned int freq_out
)
1983 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
1986 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
1987 int clk_id
, unsigned int freq
, int dir
)
1989 struct snd_soc_codec
*codec
= dai
->codec
;
1990 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1999 /* AIF3 shares clocking with AIF1/2 */
2004 case WM8994_SYSCLK_MCLK1
:
2005 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2006 wm8994
->mclk
[0] = freq
;
2007 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2011 case WM8994_SYSCLK_MCLK2
:
2012 /* TODO: Set GPIO AF */
2013 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2014 wm8994
->mclk
[1] = freq
;
2015 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2019 case WM8994_SYSCLK_FLL1
:
2020 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2021 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2024 case WM8994_SYSCLK_FLL2
:
2025 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2026 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2029 case WM8994_SYSCLK_OPCLK
:
2030 /* Special case - a division (times 10) is given and
2031 * no effect on main clocking.
2034 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2035 if (opclk_divs
[i
] == freq
)
2037 if (i
== ARRAY_SIZE(opclk_divs
))
2039 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2040 WM8994_OPCLK_DIV_MASK
, i
);
2041 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2042 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2044 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2045 WM8994_OPCLK_ENA
, 0);
2052 configure_clock(codec
);
2057 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2058 enum snd_soc_bias_level level
)
2060 struct wm8994
*control
= codec
->control_data
;
2061 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2064 case SND_SOC_BIAS_ON
:
2067 case SND_SOC_BIAS_PREPARE
:
2069 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
2070 WM8994_VMID_SEL_MASK
, 0x2);
2073 case SND_SOC_BIAS_STANDBY
:
2074 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2075 pm_runtime_get_sync(codec
->dev
);
2077 switch (control
->type
) {
2079 if (wm8994
->revision
< 4) {
2080 /* Tweak DC servo and DSP
2081 * configuration for improved
2083 snd_soc_write(codec
, 0x102, 0x3);
2084 snd_soc_write(codec
, 0x56, 0x3);
2085 snd_soc_write(codec
, 0x817, 0);
2086 snd_soc_write(codec
, 0x102, 0);
2091 if (wm8994
->revision
== 0) {
2092 /* Optimise performance for rev A */
2093 snd_soc_write(codec
, 0x102, 0x3);
2094 snd_soc_write(codec
, 0xcb, 0x81);
2095 snd_soc_write(codec
, 0x817, 0);
2096 snd_soc_write(codec
, 0x102, 0);
2098 snd_soc_update_bits(codec
,
2099 WM8958_CHARGE_PUMP_2
,
2106 /* Discharge LINEOUT1 & 2 */
2107 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2108 WM8994_LINEOUT1_DISCH
|
2109 WM8994_LINEOUT2_DISCH
,
2110 WM8994_LINEOUT1_DISCH
|
2111 WM8994_LINEOUT2_DISCH
);
2113 /* Startup bias, VMID ramp & buffer */
2114 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2115 WM8994_STARTUP_BIAS_ENA
|
2116 WM8994_VMID_BUF_ENA
|
2117 WM8994_VMID_RAMP_MASK
,
2118 WM8994_STARTUP_BIAS_ENA
|
2119 WM8994_VMID_BUF_ENA
|
2120 (0x11 << WM8994_VMID_RAMP_SHIFT
));
2122 /* Main bias enable, VMID=2x40k */
2123 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
2125 WM8994_VMID_SEL_MASK
,
2126 WM8994_BIAS_ENA
| 0x2);
2132 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
2133 WM8994_VMID_SEL_MASK
, 0x4);
2137 case SND_SOC_BIAS_OFF
:
2138 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
) {
2139 /* Switch over to startup biases */
2140 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2142 WM8994_STARTUP_BIAS_ENA
|
2143 WM8994_VMID_BUF_ENA
|
2144 WM8994_VMID_RAMP_MASK
,
2146 WM8994_STARTUP_BIAS_ENA
|
2147 WM8994_VMID_BUF_ENA
|
2148 (1 << WM8994_VMID_RAMP_SHIFT
));
2150 /* Disable main biases */
2151 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
2153 WM8994_VMID_SEL_MASK
, 0);
2155 /* Discharge line */
2156 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2157 WM8994_LINEOUT1_DISCH
|
2158 WM8994_LINEOUT2_DISCH
,
2159 WM8994_LINEOUT1_DISCH
|
2160 WM8994_LINEOUT2_DISCH
);
2164 /* Switch off startup biases */
2165 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2167 WM8994_STARTUP_BIAS_ENA
|
2168 WM8994_VMID_BUF_ENA
|
2169 WM8994_VMID_RAMP_MASK
, 0);
2171 pm_runtime_put(codec
->dev
);
2175 codec
->dapm
.bias_level
= level
;
2179 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2181 struct snd_soc_codec
*codec
= dai
->codec
;
2182 struct wm8994
*control
= codec
->control_data
;
2190 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2191 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2194 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2195 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2201 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2202 case SND_SOC_DAIFMT_CBS_CFS
:
2204 case SND_SOC_DAIFMT_CBM_CFM
:
2205 ms
= WM8994_AIF1_MSTR
;
2211 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2212 case SND_SOC_DAIFMT_DSP_B
:
2213 aif1
|= WM8994_AIF1_LRCLK_INV
;
2214 case SND_SOC_DAIFMT_DSP_A
:
2217 case SND_SOC_DAIFMT_I2S
:
2220 case SND_SOC_DAIFMT_RIGHT_J
:
2222 case SND_SOC_DAIFMT_LEFT_J
:
2229 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2230 case SND_SOC_DAIFMT_DSP_A
:
2231 case SND_SOC_DAIFMT_DSP_B
:
2232 /* frame inversion not valid for DSP modes */
2233 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2234 case SND_SOC_DAIFMT_NB_NF
:
2236 case SND_SOC_DAIFMT_IB_NF
:
2237 aif1
|= WM8994_AIF1_BCLK_INV
;
2244 case SND_SOC_DAIFMT_I2S
:
2245 case SND_SOC_DAIFMT_RIGHT_J
:
2246 case SND_SOC_DAIFMT_LEFT_J
:
2247 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2248 case SND_SOC_DAIFMT_NB_NF
:
2250 case SND_SOC_DAIFMT_IB_IF
:
2251 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2253 case SND_SOC_DAIFMT_IB_NF
:
2254 aif1
|= WM8994_AIF1_BCLK_INV
;
2256 case SND_SOC_DAIFMT_NB_IF
:
2257 aif1
|= WM8994_AIF1_LRCLK_INV
;
2267 /* The AIF2 format configuration needs to be mirrored to AIF3
2268 * on WM8958 if it's in use so just do it all the time. */
2269 if (control
->type
== WM8958
&& dai
->id
== 2)
2270 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2271 WM8994_AIF1_LRCLK_INV
|
2272 WM8958_AIF3_FMT_MASK
, aif1
);
2274 snd_soc_update_bits(codec
, aif1_reg
,
2275 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2276 WM8994_AIF1_FMT_MASK
,
2278 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2300 static int fs_ratios
[] = {
2301 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2304 static int bclk_divs
[] = {
2305 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2306 640, 880, 960, 1280, 1760, 1920
2309 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2310 struct snd_pcm_hw_params
*params
,
2311 struct snd_soc_dai
*dai
)
2313 struct snd_soc_codec
*codec
= dai
->codec
;
2314 struct wm8994
*control
= codec
->control_data
;
2315 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2326 int id
= dai
->id
- 1;
2328 int i
, cur_val
, best_val
, bclk_rate
, best
;
2332 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2333 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2334 bclk_reg
= WM8994_AIF1_BCLK
;
2335 rate_reg
= WM8994_AIF1_RATE
;
2336 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2337 wm8994
->lrclk_shared
[0]) {
2338 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2340 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2341 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2345 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2346 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2347 bclk_reg
= WM8994_AIF2_BCLK
;
2348 rate_reg
= WM8994_AIF2_RATE
;
2349 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2350 wm8994
->lrclk_shared
[1]) {
2351 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2353 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2354 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2358 switch (control
->type
) {
2360 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2369 bclk_rate
= params_rate(params
) * 2;
2370 switch (params_format(params
)) {
2371 case SNDRV_PCM_FORMAT_S16_LE
:
2374 case SNDRV_PCM_FORMAT_S20_3LE
:
2378 case SNDRV_PCM_FORMAT_S24_LE
:
2382 case SNDRV_PCM_FORMAT_S32_LE
:
2390 /* Try to find an appropriate sample rate; look for an exact match. */
2391 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2392 if (srs
[i
].rate
== params_rate(params
))
2394 if (i
== ARRAY_SIZE(srs
))
2396 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2398 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2399 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2400 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2402 if (params_channels(params
) == 1 &&
2403 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2404 aif2
|= WM8994_AIF1_MONO
;
2406 if (wm8994
->aifclk
[id
] == 0) {
2407 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2411 /* AIFCLK/fs ratio; look for a close match in either direction */
2413 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2414 - wm8994
->aifclk
[id
]);
2415 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2416 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2417 - wm8994
->aifclk
[id
]);
2418 if (cur_val
>= best_val
)
2423 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2424 dai
->id
, fs_ratios
[best
]);
2427 /* We may not get quite the right frequency if using
2428 * approximate clocks so look for the closest match that is
2429 * higher than the target (we need to ensure that there enough
2430 * BCLKs to clock out the samples).
2433 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2434 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2435 if (cur_val
< 0) /* BCLK table is sorted */
2439 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2440 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2441 bclk_divs
[best
], bclk_rate
);
2442 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2444 lrclk
= bclk_rate
/ params_rate(params
);
2445 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2446 lrclk
, bclk_rate
/ lrclk
);
2448 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2449 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2450 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2451 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2453 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2454 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2456 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2459 wm8994
->dac_rates
[0] = params_rate(params
);
2460 wm8994_set_retune_mobile(codec
, 0);
2461 wm8994_set_retune_mobile(codec
, 1);
2464 wm8994
->dac_rates
[1] = params_rate(params
);
2465 wm8994_set_retune_mobile(codec
, 2);
2473 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2474 struct snd_pcm_hw_params
*params
,
2475 struct snd_soc_dai
*dai
)
2477 struct snd_soc_codec
*codec
= dai
->codec
;
2478 struct wm8994
*control
= codec
->control_data
;
2484 switch (control
->type
) {
2486 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2495 switch (params_format(params
)) {
2496 case SNDRV_PCM_FORMAT_S16_LE
:
2498 case SNDRV_PCM_FORMAT_S20_3LE
:
2501 case SNDRV_PCM_FORMAT_S24_LE
:
2504 case SNDRV_PCM_FORMAT_S32_LE
:
2511 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2514 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2516 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2520 switch (codec_dai
->id
) {
2522 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2525 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2532 reg
= WM8994_AIF1DAC1_MUTE
;
2536 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2541 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2543 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2546 switch (codec_dai
->id
) {
2548 reg
= WM8994_AIF1_MASTER_SLAVE
;
2549 mask
= WM8994_AIF1_TRI
;
2552 reg
= WM8994_AIF2_MASTER_SLAVE
;
2553 mask
= WM8994_AIF2_TRI
;
2556 reg
= WM8994_POWER_MANAGEMENT_6
;
2557 mask
= WM8994_AIF3_TRI
;
2568 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2571 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2573 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2574 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2576 static struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2577 .set_sysclk
= wm8994_set_dai_sysclk
,
2578 .set_fmt
= wm8994_set_dai_fmt
,
2579 .hw_params
= wm8994_hw_params
,
2580 .digital_mute
= wm8994_aif_mute
,
2581 .set_pll
= wm8994_set_fll
,
2582 .set_tristate
= wm8994_set_tristate
,
2585 static struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2586 .set_sysclk
= wm8994_set_dai_sysclk
,
2587 .set_fmt
= wm8994_set_dai_fmt
,
2588 .hw_params
= wm8994_hw_params
,
2589 .digital_mute
= wm8994_aif_mute
,
2590 .set_pll
= wm8994_set_fll
,
2591 .set_tristate
= wm8994_set_tristate
,
2594 static struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2595 .hw_params
= wm8994_aif3_hw_params
,
2596 .set_tristate
= wm8994_set_tristate
,
2599 static struct snd_soc_dai_driver wm8994_dai
[] = {
2601 .name
= "wm8994-aif1",
2604 .stream_name
= "AIF1 Playback",
2607 .rates
= WM8994_RATES
,
2608 .formats
= WM8994_FORMATS
,
2611 .stream_name
= "AIF1 Capture",
2614 .rates
= WM8994_RATES
,
2615 .formats
= WM8994_FORMATS
,
2617 .ops
= &wm8994_aif1_dai_ops
,
2620 .name
= "wm8994-aif2",
2623 .stream_name
= "AIF2 Playback",
2626 .rates
= WM8994_RATES
,
2627 .formats
= WM8994_FORMATS
,
2630 .stream_name
= "AIF2 Capture",
2633 .rates
= WM8994_RATES
,
2634 .formats
= WM8994_FORMATS
,
2636 .ops
= &wm8994_aif2_dai_ops
,
2639 .name
= "wm8994-aif3",
2642 .stream_name
= "AIF3 Playback",
2645 .rates
= WM8994_RATES
,
2646 .formats
= WM8994_FORMATS
,
2649 .stream_name
= "AIF3 Capture",
2652 .rates
= WM8994_RATES
,
2653 .formats
= WM8994_FORMATS
,
2655 .ops
= &wm8994_aif3_dai_ops
,
2660 static int wm8994_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
2662 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2665 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2666 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2667 sizeof(struct fll_config
));
2668 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2670 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2674 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2679 static int wm8994_resume(struct snd_soc_codec
*codec
)
2681 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2683 unsigned int val
, mask
;
2685 if (wm8994
->revision
< 4) {
2686 /* force a HW read */
2687 val
= wm8994_reg_read(codec
->control_data
,
2688 WM8994_POWER_MANAGEMENT_5
);
2690 /* modify the cache only */
2691 codec
->cache_only
= 1;
2692 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
2693 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
2695 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
2697 codec
->cache_only
= 0;
2700 /* Restore the registers */
2701 ret
= snd_soc_cache_sync(codec
);
2703 dev_err(codec
->dev
, "Failed to sync cache: %d\n", ret
);
2705 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2707 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2708 if (!wm8994
->fll_suspend
[i
].out
)
2711 ret
= _wm8994_set_fll(codec
, i
+ 1,
2712 wm8994
->fll_suspend
[i
].src
,
2713 wm8994
->fll_suspend
[i
].in
,
2714 wm8994
->fll_suspend
[i
].out
);
2716 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2723 #define wm8994_suspend NULL
2724 #define wm8994_resume NULL
2727 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2729 struct snd_soc_codec
*codec
= wm8994
->codec
;
2730 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2731 struct snd_kcontrol_new controls
[] = {
2732 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2733 wm8994
->retune_mobile_enum
,
2734 wm8994_get_retune_mobile_enum
,
2735 wm8994_put_retune_mobile_enum
),
2736 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2737 wm8994
->retune_mobile_enum
,
2738 wm8994_get_retune_mobile_enum
,
2739 wm8994_put_retune_mobile_enum
),
2740 SOC_ENUM_EXT("AIF2 EQ Mode",
2741 wm8994
->retune_mobile_enum
,
2742 wm8994_get_retune_mobile_enum
,
2743 wm8994_put_retune_mobile_enum
),
2748 /* We need an array of texts for the enum API but the number
2749 * of texts is likely to be less than the number of
2750 * configurations due to the sample rate dependency of the
2751 * configurations. */
2752 wm8994
->num_retune_mobile_texts
= 0;
2753 wm8994
->retune_mobile_texts
= NULL
;
2754 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2755 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2756 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2757 wm8994
->retune_mobile_texts
[j
]) == 0)
2761 if (j
!= wm8994
->num_retune_mobile_texts
)
2764 /* Expand the array... */
2765 t
= krealloc(wm8994
->retune_mobile_texts
,
2767 (wm8994
->num_retune_mobile_texts
+ 1),
2772 /* ...store the new entry... */
2773 t
[wm8994
->num_retune_mobile_texts
] =
2774 pdata
->retune_mobile_cfgs
[i
].name
;
2776 /* ...and remember the new version. */
2777 wm8994
->num_retune_mobile_texts
++;
2778 wm8994
->retune_mobile_texts
= t
;
2781 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2782 wm8994
->num_retune_mobile_texts
);
2784 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2785 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2787 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2788 ARRAY_SIZE(controls
));
2790 dev_err(wm8994
->codec
->dev
,
2791 "Failed to add ReTune Mobile controls: %d\n", ret
);
2794 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2796 struct snd_soc_codec
*codec
= wm8994
->codec
;
2797 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2803 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2804 pdata
->lineout2_diff
,
2809 pdata
->micbias1_lvl
,
2810 pdata
->micbias2_lvl
);
2812 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2814 if (pdata
->num_drc_cfgs
) {
2815 struct snd_kcontrol_new controls
[] = {
2816 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2817 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2818 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
2819 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2820 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
2821 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2824 /* We need an array of texts for the enum API */
2825 wm8994
->drc_texts
= kmalloc(sizeof(char *)
2826 * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2827 if (!wm8994
->drc_texts
) {
2828 dev_err(wm8994
->codec
->dev
,
2829 "Failed to allocate %d DRC config texts\n",
2830 pdata
->num_drc_cfgs
);
2834 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2835 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2837 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2838 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
2840 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2841 ARRAY_SIZE(controls
));
2843 dev_err(wm8994
->codec
->dev
,
2844 "Failed to add DRC mode controls: %d\n", ret
);
2846 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
2847 wm8994_set_drc(codec
, i
);
2850 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2851 pdata
->num_retune_mobile_cfgs
);
2853 if (pdata
->num_mbc_cfgs
) {
2854 struct snd_kcontrol_new control
[] = {
2855 SOC_ENUM_EXT("MBC Mode", wm8994
->mbc_enum
,
2856 wm8958_get_mbc_enum
, wm8958_put_mbc_enum
),
2859 /* We need an array of texts for the enum API */
2860 wm8994
->mbc_texts
= kmalloc(sizeof(char *)
2861 * pdata
->num_mbc_cfgs
, GFP_KERNEL
);
2862 if (!wm8994
->mbc_texts
) {
2863 dev_err(wm8994
->codec
->dev
,
2864 "Failed to allocate %d MBC config texts\n",
2865 pdata
->num_mbc_cfgs
);
2869 for (i
= 0; i
< pdata
->num_mbc_cfgs
; i
++)
2870 wm8994
->mbc_texts
[i
] = pdata
->mbc_cfgs
[i
].name
;
2872 wm8994
->mbc_enum
.max
= pdata
->num_mbc_cfgs
;
2873 wm8994
->mbc_enum
.texts
= wm8994
->mbc_texts
;
2875 ret
= snd_soc_add_controls(wm8994
->codec
, control
, 1);
2877 dev_err(wm8994
->codec
->dev
,
2878 "Failed to add MBC mode controls: %d\n", ret
);
2881 if (pdata
->num_retune_mobile_cfgs
)
2882 wm8994_handle_retune_mobile_pdata(wm8994
);
2884 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
2885 ARRAY_SIZE(wm8994_eq_controls
));
2889 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2891 * @codec: WM8994 codec
2892 * @jack: jack to report detection events on
2893 * @micbias: microphone bias to detect on
2894 * @det: value to report for presence detection
2895 * @shrt: value to report for short detection
2897 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2898 * being used to bring out signals to the processor then only platform
2899 * data configuration is needed for WM8994 and processor GPIOs should
2900 * be configured using snd_soc_jack_add_gpios() instead.
2902 * Configuration of detection levels is available via the micbias1_lvl
2903 * and micbias2_lvl platform data members.
2905 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2906 int micbias
, int det
, int shrt
)
2908 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2909 struct wm8994_micdet
*micdet
;
2910 struct wm8994
*control
= codec
->control_data
;
2913 if (control
->type
!= WM8994
)
2918 micdet
= &wm8994
->micdet
[0];
2921 micdet
= &wm8994
->micdet
[1];
2927 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
2928 micbias
, det
, shrt
);
2930 /* Store the configuration */
2931 micdet
->jack
= jack
;
2933 micdet
->shrt
= shrt
;
2935 /* If either of the jacks is set up then enable detection */
2936 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2937 reg
= WM8994_MICD_ENA
;
2941 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
2945 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
2947 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
2949 struct wm8994_priv
*priv
= data
;
2950 struct snd_soc_codec
*codec
= priv
->codec
;
2954 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2955 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
2958 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
2960 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
2965 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
2968 if (reg
& WM8994_MIC1_DET_STS
)
2969 report
|= priv
->micdet
[0].det
;
2970 if (reg
& WM8994_MIC1_SHRT_STS
)
2971 report
|= priv
->micdet
[0].shrt
;
2972 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
2973 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
2976 if (reg
& WM8994_MIC2_DET_STS
)
2977 report
|= priv
->micdet
[1].det
;
2978 if (reg
& WM8994_MIC2_SHRT_STS
)
2979 report
|= priv
->micdet
[1].shrt
;
2980 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
2981 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
2986 /* Default microphone detection handler for WM8958 - the user can
2987 * override this if they wish.
2989 static void wm8958_default_micdet(u16 status
, void *data
)
2991 struct snd_soc_codec
*codec
= data
;
2992 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2995 /* If nothing present then clear our statuses */
2996 if (!(status
& WM8958_MICD_STS
)) {
2997 wm8994
->jack_is_video
= false;
2998 wm8994
->jack_is_mic
= false;
3002 /* Assume anything over 475 ohms is a microphone and remember
3003 * that we've seen one (since buttons override it) */
3005 wm8994
->jack_is_mic
= true;
3006 if (wm8994
->jack_is_mic
)
3007 report
|= SND_JACK_MICROPHONE
;
3009 /* Video has an impedence of approximately 75 ohms; assume
3010 * this isn't used as a button and remember it since buttons
3013 wm8994
->jack_is_video
= true;
3014 if (wm8994
->jack_is_video
)
3015 report
|= SND_JACK_VIDEOOUT
;
3017 /* Everything else is buttons; just assign slots */
3019 report
|= SND_JACK_BTN_0
;
3021 report
|= SND_JACK_BTN_1
;
3023 report
|= SND_JACK_BTN_2
;
3025 report
|= SND_JACK_BTN_3
;
3027 report
|= SND_JACK_BTN_4
;
3029 report
|= SND_JACK_BTN_5
;
3032 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3033 SND_JACK_BTN_0
| SND_JACK_BTN_1
| SND_JACK_BTN_2
|
3034 SND_JACK_BTN_3
| SND_JACK_BTN_4
| SND_JACK_BTN_5
|
3035 SND_JACK_MICROPHONE
| SND_JACK_VIDEOOUT
);
3039 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3041 * @codec: WM8958 codec
3042 * @jack: jack to report detection events on
3044 * Enable microphone detection functionality for the WM8958. By
3045 * default simple detection which supports the detection of up to 6
3046 * buttons plus video and microphone functionality is supported.
3048 * The WM8958 has an advanced jack detection facility which is able to
3049 * support complex accessory detection, especially when used in
3050 * conjunction with external circuitry. In order to provide maximum
3051 * flexiblity a callback is provided which allows a completely custom
3052 * detection algorithm.
3054 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3055 wm8958_micdet_cb cb
, void *cb_data
)
3057 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3058 struct wm8994
*control
= codec
->control_data
;
3060 if (control
->type
!= WM8958
)
3065 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3066 cb
= wm8958_default_micdet
;
3070 wm8994
->micdet
[0].jack
= jack
;
3071 wm8994
->jack_cb
= cb
;
3072 wm8994
->jack_cb_data
= cb_data
;
3074 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3075 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3077 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3078 WM8958_MICD_ENA
, 0);
3083 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3085 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3087 struct wm8994_priv
*wm8994
= data
;
3088 struct snd_soc_codec
*codec
= wm8994
->codec
;
3091 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3093 dev_err(codec
->dev
, "Failed to read mic detect status: %d\n",
3098 if (!(reg
& WM8958_MICD_VALID
)) {
3099 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3103 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3104 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3107 if (wm8994
->jack_cb
)
3108 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3110 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3116 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3118 struct wm8994
*control
;
3119 struct wm8994_priv
*wm8994
;
3120 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3123 codec
->control_data
= dev_get_drvdata(codec
->dev
->parent
);
3124 control
= codec
->control_data
;
3126 wm8994
= kzalloc(sizeof(struct wm8994_priv
), GFP_KERNEL
);
3129 snd_soc_codec_set_drvdata(codec
, wm8994
);
3131 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
3132 wm8994
->codec
= codec
;
3134 pm_runtime_enable(codec
->dev
);
3135 pm_runtime_resume(codec
->dev
);
3137 /* Read our current status back from the chip - we don't want to
3138 * reset as this may interfere with the GPIO or LDO operation. */
3139 for (i
= 0; i
< WM8994_CACHE_SIZE
; i
++) {
3140 if (!wm8994_readable(i
) || wm8994_volatile(i
))
3143 ret
= wm8994_reg_read(codec
->control_data
, i
);
3147 ret
= snd_soc_cache_write(codec
, i
, ret
);
3150 "Failed to initialise cache for 0x%x: %d\n",
3156 /* Set revision-specific configuration */
3157 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3158 switch (control
->type
) {
3160 switch (wm8994
->revision
) {
3163 wm8994
->hubs
.dcs_codes
= -5;
3164 wm8994
->hubs
.hp_startup_mode
= 1;
3165 wm8994
->hubs
.dcs_readback_mode
= 1;
3168 wm8994
->hubs
.dcs_readback_mode
= 1;
3173 wm8994
->hubs
.dcs_readback_mode
= 1;
3180 switch (control
->type
) {
3182 ret
= wm8994_request_irq(codec
->control_data
,
3183 WM8994_IRQ_MIC1_DET
,
3184 wm8994_mic_irq
, "Mic 1 detect",
3187 dev_warn(codec
->dev
,
3188 "Failed to request Mic1 detect IRQ: %d\n",
3191 ret
= wm8994_request_irq(codec
->control_data
,
3192 WM8994_IRQ_MIC1_SHRT
,
3193 wm8994_mic_irq
, "Mic 1 short",
3196 dev_warn(codec
->dev
,
3197 "Failed to request Mic1 short IRQ: %d\n",
3200 ret
= wm8994_request_irq(codec
->control_data
,
3201 WM8994_IRQ_MIC2_DET
,
3202 wm8994_mic_irq
, "Mic 2 detect",
3205 dev_warn(codec
->dev
,
3206 "Failed to request Mic2 detect IRQ: %d\n",
3209 ret
= wm8994_request_irq(codec
->control_data
,
3210 WM8994_IRQ_MIC2_SHRT
,
3211 wm8994_mic_irq
, "Mic 2 short",
3214 dev_warn(codec
->dev
,
3215 "Failed to request Mic2 short IRQ: %d\n",
3220 ret
= wm8994_request_irq(codec
->control_data
,
3221 WM8994_IRQ_MIC1_DET
,
3222 wm8958_mic_irq
, "Mic detect",
3225 dev_warn(codec
->dev
,
3226 "Failed to request Mic detect IRQ: %d\n",
3231 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3232 * configured on init - if a system wants to do this dynamically
3233 * at runtime we can deal with that then.
3235 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_1
);
3237 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3240 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3241 wm8994
->lrclk_shared
[0] = 1;
3242 wm8994_dai
[0].symmetric_rates
= 1;
3244 wm8994
->lrclk_shared
[0] = 0;
3247 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_6
);
3249 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3252 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3253 wm8994
->lrclk_shared
[1] = 1;
3254 wm8994_dai
[1].symmetric_rates
= 1;
3256 wm8994
->lrclk_shared
[1] = 0;
3259 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
3261 /* Latch volume updates (right only; we always do left then right). */
3262 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
3263 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3264 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
3265 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3266 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
3267 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3268 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
3269 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3270 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
3271 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3272 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3273 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3274 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3275 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3276 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3277 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3279 /* Set the low bit of the 3D stereo depth so TLV matches */
3280 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3281 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3282 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3283 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3284 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3285 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3286 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3287 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3288 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3290 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3291 * behaviour on idle TDM clock cycles. */
3292 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3293 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3295 wm8994_update_class_w(codec
);
3297 wm8994_handle_pdata(wm8994
);
3299 wm_hubs_add_analogue_controls(codec
);
3300 snd_soc_add_controls(codec
, wm8994_snd_controls
,
3301 ARRAY_SIZE(wm8994_snd_controls
));
3302 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3303 ARRAY_SIZE(wm8994_dapm_widgets
));
3305 switch (control
->type
) {
3307 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3308 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3309 if (wm8994
->revision
< 4) {
3310 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3311 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3312 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3313 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3314 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3315 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3317 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3318 ARRAY_SIZE(wm8994_lateclk_widgets
));
3319 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3320 ARRAY_SIZE(wm8994_adc_widgets
));
3321 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3322 ARRAY_SIZE(wm8994_dac_widgets
));
3326 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3327 ARRAY_SIZE(wm8958_snd_controls
));
3328 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3329 ARRAY_SIZE(wm8994_lateclk_widgets
));
3330 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3331 ARRAY_SIZE(wm8994_adc_widgets
));
3332 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3333 ARRAY_SIZE(wm8994_dac_widgets
));
3334 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3335 ARRAY_SIZE(wm8958_dapm_widgets
));
3340 wm_hubs_add_analogue_routes(codec
, 0, 0);
3341 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
3343 switch (control
->type
) {
3345 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
3346 ARRAY_SIZE(wm8994_intercon
));
3348 if (wm8994
->revision
< 4) {
3349 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3350 ARRAY_SIZE(wm8994_revd_intercon
));
3351 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3352 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3354 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3355 ARRAY_SIZE(wm8994_lateclk_intercon
));
3359 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3360 ARRAY_SIZE(wm8994_lateclk_intercon
));
3361 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3362 ARRAY_SIZE(wm8958_intercon
));
3369 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
3370 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
, wm8994
);
3371 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
3372 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
, wm8994
);
3378 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
3380 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3381 struct wm8994
*control
= codec
->control_data
;
3383 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3385 pm_runtime_disable(codec
->dev
);
3387 switch (control
->type
) {
3389 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
,
3391 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
,
3393 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
,
3395 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
,
3400 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
,
3404 kfree(wm8994
->retune_mobile_texts
);
3405 kfree(wm8994
->drc_texts
);
3411 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
3412 .probe
= wm8994_codec_probe
,
3413 .remove
= wm8994_codec_remove
,
3414 .suspend
= wm8994_suspend
,
3415 .resume
= wm8994_resume
,
3416 .read
= wm8994_read
,
3417 .write
= wm8994_write
,
3418 .readable_register
= wm8994_readable
,
3419 .volatile_register
= wm8994_volatile
,
3420 .set_bias_level
= wm8994_set_bias_level
,
3422 .reg_cache_size
= WM8994_CACHE_SIZE
,
3423 .reg_cache_default
= wm8994_reg_defaults
,
3425 .compress_type
= SND_SOC_RBTREE_COMPRESSION
,
3428 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
3430 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
3431 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
3434 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
3436 snd_soc_unregister_codec(&pdev
->dev
);
3440 static struct platform_driver wm8994_codec_driver
= {
3442 .name
= "wm8994-codec",
3443 .owner
= THIS_MODULE
,
3445 .probe
= wm8994_probe
,
3446 .remove
= __devexit_p(wm8994_remove
),
3449 static __init
int wm8994_init(void)
3451 return platform_driver_register(&wm8994_codec_driver
);
3453 module_init(wm8994_init
);
3455 static __exit
void wm8994_exit(void)
3457 platform_driver_unregister(&wm8994_codec_driver
);
3459 module_exit(wm8994_exit
);
3462 MODULE_DESCRIPTION("ASoC WM8994 driver");
3463 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3464 MODULE_LICENSE("GPL");
3465 MODULE_ALIAS("platform:wm8994-codec");