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ASoC: wm8994: Add clock bindings to the device tree
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
33
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
38
39 #include "wm8994.h"
40 #include "wm_hubs.h"
41
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
49
50 static struct {
51 unsigned int reg;
52 unsigned int mask;
53 } wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81 };
82
83 static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87 };
88
89 static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93 };
94
95 static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
100 };
101
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
107 };
108
109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110 {
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
137 best = 0;
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
140 continue;
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
143 best = i;
144 else if (rates[best].idle != idle)
145 best = i;
146 }
147
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150
151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158 }
159
160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161 {
162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
203
204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211 }
212
213 static int configure_clock(struct snd_soc_codec *codec)
214 {
215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216 int change, new;
217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
231 return 0;
232 }
233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
243
244 wm8958_micd_set_rate(codec);
245
246 return 0;
247 }
248
249 static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251 {
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262 }
263
264 static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266 };
267
268 static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270
271 static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273 };
274
275 static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277
278 static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280
281 static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283
284 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
289 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
291
292 #define WM8994_DRC_SWITCH(xname, reg, shift) \
293 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294 snd_soc_get_volsw, wm8994_put_drc_sw)
295
296 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298 {
299 struct soc_mixer_control *mc =
300 (struct soc_mixer_control *)kcontrol->private_value;
301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
302 int mask, ret;
303
304 /* Can't enable both ADC and DAC paths simultaneously */
305 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307 WM8994_AIF1ADC1R_DRC_ENA_MASK;
308 else
309 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310
311 ret = snd_soc_read(codec, mc->reg);
312 if (ret < 0)
313 return ret;
314 if (ret & mask)
315 return -EINVAL;
316
317 return snd_soc_put_volsw(kcontrol, ucontrol);
318 }
319
320 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321 {
322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
323 struct wm8994 *control = wm8994->wm8994;
324 struct wm8994_pdata *pdata = &control->pdata;
325 int base = wm8994_drc_base[drc];
326 int cfg = wm8994->drc_cfg[drc];
327 int save, i;
328
329 /* Save any enables; the configuration should clear them. */
330 save = snd_soc_read(codec, base);
331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332 WM8994_AIF1ADC1R_DRC_ENA;
333
334 for (i = 0; i < WM8994_DRC_REGS; i++)
335 snd_soc_update_bits(codec, base + i, 0xffff,
336 pdata->drc_cfgs[cfg].regs[i]);
337
338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339 WM8994_AIF1ADC1L_DRC_ENA |
340 WM8994_AIF1ADC1R_DRC_ENA, save);
341 }
342
343 /* Icky as hell but saves code duplication */
344 static int wm8994_get_drc(const char *name)
345 {
346 if (strcmp(name, "AIF1DRC1 Mode") == 0)
347 return 0;
348 if (strcmp(name, "AIF1DRC2 Mode") == 0)
349 return 1;
350 if (strcmp(name, "AIF2DRC Mode") == 0)
351 return 2;
352 return -EINVAL;
353 }
354
355 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357 {
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
360 struct wm8994 *control = wm8994->wm8994;
361 struct wm8994_pdata *pdata = &control->pdata;
362 int drc = wm8994_get_drc(kcontrol->id.name);
363 int value = ucontrol->value.integer.value[0];
364
365 if (drc < 0)
366 return drc;
367
368 if (value >= pdata->num_drc_cfgs)
369 return -EINVAL;
370
371 wm8994->drc_cfg[drc] = value;
372
373 wm8994_set_drc(codec, drc);
374
375 return 0;
376 }
377
378 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380 {
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
383 int drc = wm8994_get_drc(kcontrol->id.name);
384
385 if (drc < 0)
386 return drc;
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390 }
391
392 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393 {
394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
438 * current configuration.
439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448 }
449
450 /* Icky as hell but saves code duplication */
451 static int wm8994_get_retune_mobile_block(const char *name)
452 {
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460 }
461
462 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464 {
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483 }
484
485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487 {
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 if (block < 0)
493 return block;
494
495 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496
497 return 0;
498 }
499
500 static const char *aif_chan_src_text[] = {
501 "Left", "Right"
502 };
503
504 static const struct soc_enum aif1adcl_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
506
507 static const struct soc_enum aif1adcr_src =
508 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
509
510 static const struct soc_enum aif2adcl_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
512
513 static const struct soc_enum aif2adcr_src =
514 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
515
516 static const struct soc_enum aif1dacl_src =
517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
518
519 static const struct soc_enum aif1dacr_src =
520 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
521
522 static const struct soc_enum aif2dacl_src =
523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
524
525 static const struct soc_enum aif2dacr_src =
526 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
527
528 static const char *osr_text[] = {
529 "Low Power", "High Performance",
530 };
531
532 static const struct soc_enum dac_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
534
535 static const struct soc_enum adc_osr =
536 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
537
538 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540 WM8994_AIF1_ADC1_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543 WM8994_AIF1_ADC2_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546 WM8994_AIF2_ADC_RIGHT_VOLUME,
547 1, 119, 0, digital_tlv),
548
549 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
551 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
553
554 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
556 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
558
559 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565
566 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568
569 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572
573 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576
577 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580
581 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584
585 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590 5, 12, 0, st_tlv),
591 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592 0, 12, 0, st_tlv),
593 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595
596 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598
599 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601
602 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604
605 SOC_ENUM("ADC OSR", adc_osr),
606 SOC_ENUM("DAC OSR", dac_osr),
607
608 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612
613 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617
618 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619 6, 1, 1, wm_hubs_spkmix_tlv),
620 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621 2, 1, 1, wm_hubs_spkmix_tlv),
622
623 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624 6, 1, 1, wm_hubs_spkmix_tlv),
625 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626 2, 1, 1, wm_hubs_spkmix_tlv),
627
628 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
630 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
631 8, 1, 0),
632 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633 10, 15, 0, wm8994_3d_tlv),
634 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635 8, 1, 0),
636 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
637 10, 15, 0, wm8994_3d_tlv),
638 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
639 8, 1, 0),
640 };
641
642 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644 eq_tlv),
645 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646 eq_tlv),
647 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648 eq_tlv),
649 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650 eq_tlv),
651 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652 eq_tlv),
653
654 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655 eq_tlv),
656 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657 eq_tlv),
658 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659 eq_tlv),
660 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661 eq_tlv),
662 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663 eq_tlv),
664
665 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666 eq_tlv),
667 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668 eq_tlv),
669 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670 eq_tlv),
671 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672 eq_tlv),
673 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674 eq_tlv),
675 };
676
677 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680 WM8994_AIF1ADC1R_DRC_ENA),
681 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683 WM8994_AIF1ADC2R_DRC_ENA),
684 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686 WM8994_AIF2ADCR_DRC_ENA),
687 };
688
689 static const char *wm8958_ng_text[] = {
690 "30ms", "125ms", "250ms", "500ms",
691 };
692
693 static const struct soc_enum wm8958_aif1dac1_ng_hold =
694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
695 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
696
697 static const struct soc_enum wm8958_aif1dac2_ng_hold =
698 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
699 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
700
701 static const struct soc_enum wm8958_aif2dac_ng_hold =
702 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
703 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
704
705 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
706 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
707
708 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
709 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
710 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
711 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
712 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
713 7, 1, ng_tlv),
714
715 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
716 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
717 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
718 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
719 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
720 7, 1, ng_tlv),
721
722 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
723 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
724 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
725 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
726 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
727 7, 1, ng_tlv),
728 };
729
730 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
731 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
732 mixin_boost_tlv),
733 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
734 mixin_boost_tlv),
735 };
736
737 /* We run all mode setting through a function to enforce audio mode */
738 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
739 {
740 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
741
742 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
743 return;
744
745 if (wm8994->active_refcount)
746 mode = WM1811_JACKDET_MODE_AUDIO;
747
748 if (mode == wm8994->jackdet_mode)
749 return;
750
751 wm8994->jackdet_mode = mode;
752
753 /* Always use audio mode to detect while the system is active */
754 if (mode != WM1811_JACKDET_MODE_NONE)
755 mode = WM1811_JACKDET_MODE_AUDIO;
756
757 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
758 WM1811_JACKDET_MODE_MASK, mode);
759 }
760
761 static void active_reference(struct snd_soc_codec *codec)
762 {
763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
764
765 mutex_lock(&wm8994->accdet_lock);
766
767 wm8994->active_refcount++;
768
769 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
770 wm8994->active_refcount);
771
772 /* If we're using jack detection go into audio mode */
773 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
774
775 mutex_unlock(&wm8994->accdet_lock);
776 }
777
778 static void active_dereference(struct snd_soc_codec *codec)
779 {
780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
781 u16 mode;
782
783 mutex_lock(&wm8994->accdet_lock);
784
785 wm8994->active_refcount--;
786
787 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
788 wm8994->active_refcount);
789
790 if (wm8994->active_refcount == 0) {
791 /* Go into appropriate detection only mode */
792 if (wm8994->jack_mic || wm8994->mic_detecting)
793 mode = WM1811_JACKDET_MODE_MIC;
794 else
795 mode = WM1811_JACKDET_MODE_JACK;
796
797 wm1811_jackdet_set_mode(codec, mode);
798 }
799
800 mutex_unlock(&wm8994->accdet_lock);
801 }
802
803 static int clk_sys_event(struct snd_soc_dapm_widget *w,
804 struct snd_kcontrol *kcontrol, int event)
805 {
806 struct snd_soc_codec *codec = w->codec;
807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
808
809 switch (event) {
810 case SND_SOC_DAPM_PRE_PMU:
811 return configure_clock(codec);
812
813 case SND_SOC_DAPM_POST_PMU:
814 /*
815 * JACKDET won't run until we start the clock and it
816 * only reports deltas, make sure we notify the state
817 * up the stack on startup. Use a *very* generous
818 * timeout for paranoia, there's no urgency and we
819 * don't want false reports.
820 */
821 if (wm8994->jackdet && !wm8994->clk_has_run) {
822 queue_delayed_work(system_power_efficient_wq,
823 &wm8994->jackdet_bootstrap,
824 msecs_to_jiffies(1000));
825 wm8994->clk_has_run = true;
826 }
827 break;
828
829 case SND_SOC_DAPM_POST_PMD:
830 configure_clock(codec);
831 break;
832 }
833
834 return 0;
835 }
836
837 static void vmid_reference(struct snd_soc_codec *codec)
838 {
839 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
840
841 pm_runtime_get_sync(codec->dev);
842
843 wm8994->vmid_refcount++;
844
845 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
846 wm8994->vmid_refcount);
847
848 if (wm8994->vmid_refcount == 1) {
849 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
850 WM8994_LINEOUT1_DISCH |
851 WM8994_LINEOUT2_DISCH, 0);
852
853 wm_hubs_vmid_ena(codec);
854
855 switch (wm8994->vmid_mode) {
856 default:
857 WARN_ON(NULL == "Invalid VMID mode");
858 case WM8994_VMID_NORMAL:
859 /* Startup bias, VMID ramp & buffer */
860 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
861 WM8994_BIAS_SRC |
862 WM8994_VMID_DISCH |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
865 WM8994_VMID_RAMP_MASK,
866 WM8994_BIAS_SRC |
867 WM8994_STARTUP_BIAS_ENA |
868 WM8994_VMID_BUF_ENA |
869 (0x2 << WM8994_VMID_RAMP_SHIFT));
870
871 /* Main bias enable, VMID=2x40k */
872 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
873 WM8994_BIAS_ENA |
874 WM8994_VMID_SEL_MASK,
875 WM8994_BIAS_ENA | 0x2);
876
877 msleep(300);
878
879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
880 WM8994_VMID_RAMP_MASK |
881 WM8994_BIAS_SRC,
882 0);
883 break;
884
885 case WM8994_VMID_FORCE:
886 /* Startup bias, slow VMID ramp & buffer */
887 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
888 WM8994_BIAS_SRC |
889 WM8994_VMID_DISCH |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 WM8994_VMID_RAMP_MASK,
893 WM8994_BIAS_SRC |
894 WM8994_STARTUP_BIAS_ENA |
895 WM8994_VMID_BUF_ENA |
896 (0x2 << WM8994_VMID_RAMP_SHIFT));
897
898 /* Main bias enable, VMID=2x40k */
899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
900 WM8994_BIAS_ENA |
901 WM8994_VMID_SEL_MASK,
902 WM8994_BIAS_ENA | 0x2);
903
904 msleep(400);
905
906 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907 WM8994_VMID_RAMP_MASK |
908 WM8994_BIAS_SRC,
909 0);
910 break;
911 }
912 }
913 }
914
915 static void vmid_dereference(struct snd_soc_codec *codec)
916 {
917 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
918
919 wm8994->vmid_refcount--;
920
921 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
922 wm8994->vmid_refcount);
923
924 if (wm8994->vmid_refcount == 0) {
925 if (wm8994->hubs.lineout1_se)
926 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
927 WM8994_LINEOUT1N_ENA |
928 WM8994_LINEOUT1P_ENA,
929 WM8994_LINEOUT1N_ENA |
930 WM8994_LINEOUT1P_ENA);
931
932 if (wm8994->hubs.lineout2_se)
933 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
934 WM8994_LINEOUT2N_ENA |
935 WM8994_LINEOUT2P_ENA,
936 WM8994_LINEOUT2N_ENA |
937 WM8994_LINEOUT2P_ENA);
938
939 /* Start discharging VMID */
940 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
941 WM8994_BIAS_SRC |
942 WM8994_VMID_DISCH,
943 WM8994_BIAS_SRC |
944 WM8994_VMID_DISCH);
945
946 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
947 WM8994_VMID_SEL_MASK, 0);
948
949 msleep(400);
950
951 /* Active discharge */
952 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
953 WM8994_LINEOUT1_DISCH |
954 WM8994_LINEOUT2_DISCH,
955 WM8994_LINEOUT1_DISCH |
956 WM8994_LINEOUT2_DISCH);
957
958 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
959 WM8994_LINEOUT1N_ENA |
960 WM8994_LINEOUT1P_ENA |
961 WM8994_LINEOUT2N_ENA |
962 WM8994_LINEOUT2P_ENA, 0);
963
964 /* Switch off startup biases */
965 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
966 WM8994_BIAS_SRC |
967 WM8994_STARTUP_BIAS_ENA |
968 WM8994_VMID_BUF_ENA |
969 WM8994_VMID_RAMP_MASK, 0);
970
971 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
972 WM8994_VMID_SEL_MASK, 0);
973 }
974
975 pm_runtime_put(codec->dev);
976 }
977
978 static int vmid_event(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol, int event)
980 {
981 struct snd_soc_codec *codec = w->codec;
982
983 switch (event) {
984 case SND_SOC_DAPM_PRE_PMU:
985 vmid_reference(codec);
986 break;
987
988 case SND_SOC_DAPM_POST_PMD:
989 vmid_dereference(codec);
990 break;
991 }
992
993 return 0;
994 }
995
996 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
997 {
998 int source = 0; /* GCC flow analysis can't track enable */
999 int reg, reg_r;
1000
1001 /* We also need the same AIF source for L/R and only one path */
1002 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1003 switch (reg) {
1004 case WM8994_AIF2DACL_TO_DAC1L:
1005 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1006 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC2L_TO_DAC1L:
1009 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1010 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 case WM8994_AIF1DAC1L_TO_DAC1L:
1013 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1014 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1015 break;
1016 default:
1017 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1018 return false;
1019 }
1020
1021 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1022 if (reg_r != reg) {
1023 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1024 return false;
1025 }
1026
1027 /* Set the source up */
1028 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1029 WM8994_CP_DYN_SRC_SEL_MASK, source);
1030
1031 return true;
1032 }
1033
1034 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1035 struct snd_kcontrol *kcontrol, int event)
1036 {
1037 struct snd_soc_codec *codec = w->codec;
1038 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1039 struct wm8994 *control = wm8994->wm8994;
1040 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1041 int i;
1042 int dac;
1043 int adc;
1044 int val;
1045
1046 switch (control->type) {
1047 case WM8994:
1048 case WM8958:
1049 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1050 break;
1051 default:
1052 break;
1053 }
1054
1055 switch (event) {
1056 case SND_SOC_DAPM_PRE_PMU:
1057 /* Don't enable timeslot 2 if not in use */
1058 if (wm8994->channels[0] <= 2)
1059 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1060
1061 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1062 if ((val & WM8994_AIF1ADCL_SRC) &&
1063 (val & WM8994_AIF1ADCR_SRC))
1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1065 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1066 !(val & WM8994_AIF1ADCR_SRC))
1067 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1068 else
1069 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1070 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1071
1072 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1073 if ((val & WM8994_AIF1DACL_SRC) &&
1074 (val & WM8994_AIF1DACR_SRC))
1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1076 else if (!(val & WM8994_AIF1DACL_SRC) &&
1077 !(val & WM8994_AIF1DACR_SRC))
1078 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1079 else
1080 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1081 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1082
1083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1084 mask, adc);
1085 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1086 mask, dac);
1087 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1088 WM8994_AIF1DSPCLK_ENA |
1089 WM8994_SYSDSPCLK_ENA,
1090 WM8994_AIF1DSPCLK_ENA |
1091 WM8994_SYSDSPCLK_ENA);
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1093 WM8994_AIF1ADC1R_ENA |
1094 WM8994_AIF1ADC1L_ENA |
1095 WM8994_AIF1ADC2R_ENA |
1096 WM8994_AIF1ADC2L_ENA);
1097 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1098 WM8994_AIF1DAC1R_ENA |
1099 WM8994_AIF1DAC1L_ENA |
1100 WM8994_AIF1DAC2R_ENA |
1101 WM8994_AIF1DAC2L_ENA);
1102 break;
1103
1104 case SND_SOC_DAPM_POST_PMU:
1105 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1106 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1107 snd_soc_read(codec,
1108 wm8994_vu_bits[i].reg));
1109 break;
1110
1111 case SND_SOC_DAPM_PRE_PMD:
1112 case SND_SOC_DAPM_POST_PMD:
1113 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1114 mask, 0);
1115 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1116 mask, 0);
1117
1118 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1119 if (val & WM8994_AIF2DSPCLK_ENA)
1120 val = WM8994_SYSDSPCLK_ENA;
1121 else
1122 val = 0;
1123 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1124 WM8994_SYSDSPCLK_ENA |
1125 WM8994_AIF1DSPCLK_ENA, val);
1126 break;
1127 }
1128
1129 return 0;
1130 }
1131
1132 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1133 struct snd_kcontrol *kcontrol, int event)
1134 {
1135 struct snd_soc_codec *codec = w->codec;
1136 int i;
1137 int dac;
1138 int adc;
1139 int val;
1140
1141 switch (event) {
1142 case SND_SOC_DAPM_PRE_PMU:
1143 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1144 if ((val & WM8994_AIF2ADCL_SRC) &&
1145 (val & WM8994_AIF2ADCR_SRC))
1146 adc = WM8994_AIF2ADCR_ENA;
1147 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1148 !(val & WM8994_AIF2ADCR_SRC))
1149 adc = WM8994_AIF2ADCL_ENA;
1150 else
1151 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1152
1153
1154 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1155 if ((val & WM8994_AIF2DACL_SRC) &&
1156 (val & WM8994_AIF2DACR_SRC))
1157 dac = WM8994_AIF2DACR_ENA;
1158 else if (!(val & WM8994_AIF2DACL_SRC) &&
1159 !(val & WM8994_AIF2DACR_SRC))
1160 dac = WM8994_AIF2DACL_ENA;
1161 else
1162 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1163
1164 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1165 WM8994_AIF2ADCL_ENA |
1166 WM8994_AIF2ADCR_ENA, adc);
1167 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1168 WM8994_AIF2DACL_ENA |
1169 WM8994_AIF2DACR_ENA, dac);
1170 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1171 WM8994_AIF2DSPCLK_ENA |
1172 WM8994_SYSDSPCLK_ENA,
1173 WM8994_AIF2DSPCLK_ENA |
1174 WM8994_SYSDSPCLK_ENA);
1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1176 WM8994_AIF2ADCL_ENA |
1177 WM8994_AIF2ADCR_ENA,
1178 WM8994_AIF2ADCL_ENA |
1179 WM8994_AIF2ADCR_ENA);
1180 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1181 WM8994_AIF2DACL_ENA |
1182 WM8994_AIF2DACR_ENA,
1183 WM8994_AIF2DACL_ENA |
1184 WM8994_AIF2DACR_ENA);
1185 break;
1186
1187 case SND_SOC_DAPM_POST_PMU:
1188 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1189 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1190 snd_soc_read(codec,
1191 wm8994_vu_bits[i].reg));
1192 break;
1193
1194 case SND_SOC_DAPM_PRE_PMD:
1195 case SND_SOC_DAPM_POST_PMD:
1196 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1197 WM8994_AIF2DACL_ENA |
1198 WM8994_AIF2DACR_ENA, 0);
1199 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1200 WM8994_AIF2ADCL_ENA |
1201 WM8994_AIF2ADCR_ENA, 0);
1202
1203 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1204 if (val & WM8994_AIF1DSPCLK_ENA)
1205 val = WM8994_SYSDSPCLK_ENA;
1206 else
1207 val = 0;
1208 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1209 WM8994_SYSDSPCLK_ENA |
1210 WM8994_AIF2DSPCLK_ENA, val);
1211 break;
1212 }
1213
1214 return 0;
1215 }
1216
1217 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1218 struct snd_kcontrol *kcontrol, int event)
1219 {
1220 struct snd_soc_codec *codec = w->codec;
1221 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1222
1223 switch (event) {
1224 case SND_SOC_DAPM_PRE_PMU:
1225 wm8994->aif1clk_enable = 1;
1226 break;
1227 case SND_SOC_DAPM_POST_PMD:
1228 wm8994->aif1clk_disable = 1;
1229 break;
1230 }
1231
1232 return 0;
1233 }
1234
1235 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1236 struct snd_kcontrol *kcontrol, int event)
1237 {
1238 struct snd_soc_codec *codec = w->codec;
1239 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1240
1241 switch (event) {
1242 case SND_SOC_DAPM_PRE_PMU:
1243 wm8994->aif2clk_enable = 1;
1244 break;
1245 case SND_SOC_DAPM_POST_PMD:
1246 wm8994->aif2clk_disable = 1;
1247 break;
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1254 struct snd_kcontrol *kcontrol, int event)
1255 {
1256 struct snd_soc_codec *codec = w->codec;
1257 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1258
1259 switch (event) {
1260 case SND_SOC_DAPM_PRE_PMU:
1261 if (wm8994->aif1clk_enable) {
1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1263 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1264 WM8994_AIF1CLK_ENA_MASK,
1265 WM8994_AIF1CLK_ENA);
1266 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1267 wm8994->aif1clk_enable = 0;
1268 }
1269 if (wm8994->aif2clk_enable) {
1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1271 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1272 WM8994_AIF2CLK_ENA_MASK,
1273 WM8994_AIF2CLK_ENA);
1274 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1275 wm8994->aif2clk_enable = 0;
1276 }
1277 break;
1278 }
1279
1280 /* We may also have postponed startup of DSP, handle that. */
1281 wm8958_aif_ev(w, kcontrol, event);
1282
1283 return 0;
1284 }
1285
1286 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1287 struct snd_kcontrol *kcontrol, int event)
1288 {
1289 struct snd_soc_codec *codec = w->codec;
1290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1291
1292 switch (event) {
1293 case SND_SOC_DAPM_POST_PMD:
1294 if (wm8994->aif1clk_disable) {
1295 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1296 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1297 WM8994_AIF1CLK_ENA_MASK, 0);
1298 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1299 wm8994->aif1clk_disable = 0;
1300 }
1301 if (wm8994->aif2clk_disable) {
1302 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1303 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1304 WM8994_AIF2CLK_ENA_MASK, 0);
1305 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1306 wm8994->aif2clk_disable = 0;
1307 }
1308 break;
1309 }
1310
1311 return 0;
1312 }
1313
1314 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1315 struct snd_kcontrol *kcontrol, int event)
1316 {
1317 late_enable_ev(w, kcontrol, event);
1318 return 0;
1319 }
1320
1321 static int micbias_ev(struct snd_soc_dapm_widget *w,
1322 struct snd_kcontrol *kcontrol, int event)
1323 {
1324 late_enable_ev(w, kcontrol, event);
1325 return 0;
1326 }
1327
1328 static int dac_ev(struct snd_soc_dapm_widget *w,
1329 struct snd_kcontrol *kcontrol, int event)
1330 {
1331 struct snd_soc_codec *codec = w->codec;
1332 unsigned int mask = 1 << w->shift;
1333
1334 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1335 mask, mask);
1336 return 0;
1337 }
1338
1339 static const char *adc_mux_text[] = {
1340 "ADC",
1341 "DMIC",
1342 };
1343
1344 static const struct soc_enum adc_enum =
1345 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1346
1347 static const struct snd_kcontrol_new adcl_mux =
1348 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1349
1350 static const struct snd_kcontrol_new adcr_mux =
1351 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1352
1353 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1354 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1355 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1356 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1357 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1358 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1359 };
1360
1361 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1362 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1363 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1364 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1365 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1366 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1367 };
1368
1369 /* Debugging; dump chip status after DAPM transitions */
1370 static int post_ev(struct snd_soc_dapm_widget *w,
1371 struct snd_kcontrol *kcontrol, int event)
1372 {
1373 struct snd_soc_codec *codec = w->codec;
1374 dev_dbg(codec->dev, "SRC status: %x\n",
1375 snd_soc_read(codec,
1376 WM8994_RATE_STATUS));
1377 return 0;
1378 }
1379
1380 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1381 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1382 1, 1, 0),
1383 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1384 0, 1, 0),
1385 };
1386
1387 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1388 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1389 1, 1, 0),
1390 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1391 0, 1, 0),
1392 };
1393
1394 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1395 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1396 1, 1, 0),
1397 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1398 0, 1, 0),
1399 };
1400
1401 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1402 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1403 1, 1, 0),
1404 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1405 0, 1, 0),
1406 };
1407
1408 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1409 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410 5, 1, 0),
1411 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 4, 1, 0),
1413 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 2, 1, 0),
1415 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416 1, 1, 0),
1417 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418 0, 1, 0),
1419 };
1420
1421 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1422 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423 5, 1, 0),
1424 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 4, 1, 0),
1426 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 2, 1, 0),
1428 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429 1, 1, 0),
1430 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431 0, 1, 0),
1432 };
1433
1434 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1435 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1436 snd_soc_get_volsw, wm8994_put_class_w)
1437
1438 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1439 struct snd_ctl_elem_value *ucontrol)
1440 {
1441 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1442 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1443 struct snd_soc_codec *codec = w->codec;
1444 int ret;
1445
1446 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1447
1448 wm_hubs_update_class_w(codec);
1449
1450 return ret;
1451 }
1452
1453 static const struct snd_kcontrol_new dac1l_mix[] = {
1454 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 5, 1, 0),
1456 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457 4, 1, 0),
1458 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 2, 1, 0),
1460 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 1, 1, 0),
1462 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463 0, 1, 0),
1464 };
1465
1466 static const struct snd_kcontrol_new dac1r_mix[] = {
1467 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 5, 1, 0),
1469 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470 4, 1, 0),
1471 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 2, 1, 0),
1473 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 1, 1, 0),
1475 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476 0, 1, 0),
1477 };
1478
1479 static const char *sidetone_text[] = {
1480 "ADC/DMIC1", "DMIC2",
1481 };
1482
1483 static const struct soc_enum sidetone1_enum =
1484 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1485
1486 static const struct snd_kcontrol_new sidetone1_mux =
1487 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1488
1489 static const struct soc_enum sidetone2_enum =
1490 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1491
1492 static const struct snd_kcontrol_new sidetone2_mux =
1493 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1494
1495 static const char *aif1dac_text[] = {
1496 "AIF1DACDAT", "AIF3DACDAT",
1497 };
1498
1499 static const char *loopback_text[] = {
1500 "None", "ADCDAT",
1501 };
1502
1503 static const struct soc_enum aif1_loopback_enum =
1504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, WM8994_AIF1_LOOPBACK_SHIFT, 2,
1505 loopback_text);
1506
1507 static const struct snd_kcontrol_new aif1_loopback =
1508 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1509
1510 static const struct soc_enum aif2_loopback_enum =
1511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, WM8994_AIF2_LOOPBACK_SHIFT, 2,
1512 loopback_text);
1513
1514 static const struct snd_kcontrol_new aif2_loopback =
1515 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1516
1517 static const struct soc_enum aif1dac_enum =
1518 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1519
1520 static const struct snd_kcontrol_new aif1dac_mux =
1521 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1522
1523 static const char *aif2dac_text[] = {
1524 "AIF2DACDAT", "AIF3DACDAT",
1525 };
1526
1527 static const struct soc_enum aif2dac_enum =
1528 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1529
1530 static const struct snd_kcontrol_new aif2dac_mux =
1531 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1532
1533 static const char *aif2adc_text[] = {
1534 "AIF2ADCDAT", "AIF3DACDAT",
1535 };
1536
1537 static const struct soc_enum aif2adc_enum =
1538 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1539
1540 static const struct snd_kcontrol_new aif2adc_mux =
1541 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1542
1543 static const char *aif3adc_text[] = {
1544 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1545 };
1546
1547 static const struct soc_enum wm8994_aif3adc_enum =
1548 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1549
1550 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1551 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1552
1553 static const struct soc_enum wm8958_aif3adc_enum =
1554 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1555
1556 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1557 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1558
1559 static const char *mono_pcm_out_text[] = {
1560 "None", "AIF2ADCL", "AIF2ADCR",
1561 };
1562
1563 static const struct soc_enum mono_pcm_out_enum =
1564 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1565
1566 static const struct snd_kcontrol_new mono_pcm_out_mux =
1567 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1568
1569 static const char *aif2dac_src_text[] = {
1570 "AIF2", "AIF3",
1571 };
1572
1573 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1574 static const struct soc_enum aif2dacl_src_enum =
1575 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1576
1577 static const struct snd_kcontrol_new aif2dacl_src_mux =
1578 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1579
1580 static const struct soc_enum aif2dacr_src_enum =
1581 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1582
1583 static const struct snd_kcontrol_new aif2dacr_src_mux =
1584 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1585
1586 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1587 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1588 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1589 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1590 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1591
1592 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1593 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1594 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1595 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1597 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1598 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1599 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1601 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1602
1603 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1604 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1605 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1606 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1607 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1609 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1610 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1611 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1612 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1613
1614 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1615 };
1616
1617 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1618 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1619 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1620 SND_SOC_DAPM_PRE_PMD),
1621 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1623 SND_SOC_DAPM_PRE_PMD),
1624 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1625 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1626 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1627 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1628 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1629 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1630 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1631 };
1632
1633 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1634 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1635 dac_ev, SND_SOC_DAPM_PRE_PMU),
1636 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1637 dac_ev, SND_SOC_DAPM_PRE_PMU),
1638 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1639 dac_ev, SND_SOC_DAPM_PRE_PMU),
1640 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1641 dac_ev, SND_SOC_DAPM_PRE_PMU),
1642 };
1643
1644 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1645 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1646 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1647 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1648 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1649 };
1650
1651 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1652 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1653 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1654 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1655 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1656 };
1657
1658 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1659 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1660 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1661 };
1662
1663 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1664 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1665 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1666 SND_SOC_DAPM_INPUT("Clock"),
1667
1668 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1669 SND_SOC_DAPM_PRE_PMU),
1670 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1671 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1672
1673 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1675 SND_SOC_DAPM_PRE_PMD),
1676
1677 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1678 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1679 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1680
1681 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1682 0, SND_SOC_NOPM, 9, 0),
1683 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1684 0, SND_SOC_NOPM, 8, 0),
1685 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1686 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1687 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1688 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1689 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1690 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1691
1692 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1693 0, SND_SOC_NOPM, 11, 0),
1694 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1695 0, SND_SOC_NOPM, 10, 0),
1696 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1697 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1698 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1699 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1700 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1701 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1702
1703 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1704 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1705 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1706 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1707
1708 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1710 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1711 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1712
1713 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1714 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1715 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1716 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1717
1718 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1719 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1720
1721 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1722 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1723 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1724 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1725
1726 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1727 SND_SOC_NOPM, 13, 0),
1728 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1729 SND_SOC_NOPM, 12, 0),
1730 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1731 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1732 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1733 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1734 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1735 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1736
1737 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1738 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1739 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1740 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741
1742 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1743 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1744 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1745
1746 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1747 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1748
1749 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1750
1751 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1752 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1753 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1754 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1755
1756 /* Power is done with the muxes since the ADC power also controls the
1757 * downsampling chain, the chip will automatically manage the analogue
1758 * specific portions.
1759 */
1760 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1761 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1762
1763 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1764 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1765
1766 SND_SOC_DAPM_POST("Debug log", post_ev),
1767 };
1768
1769 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1770 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1771 };
1772
1773 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1774 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1775 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1776 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1777 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1778 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1779 };
1780
1781 static const struct snd_soc_dapm_route intercon[] = {
1782 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1783 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1784
1785 { "DSP1CLK", NULL, "CLK_SYS" },
1786 { "DSP2CLK", NULL, "CLK_SYS" },
1787 { "DSPINTCLK", NULL, "CLK_SYS" },
1788
1789 { "AIF1ADC1L", NULL, "AIF1CLK" },
1790 { "AIF1ADC1L", NULL, "DSP1CLK" },
1791 { "AIF1ADC1R", NULL, "AIF1CLK" },
1792 { "AIF1ADC1R", NULL, "DSP1CLK" },
1793 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1794
1795 { "AIF1DAC1L", NULL, "AIF1CLK" },
1796 { "AIF1DAC1L", NULL, "DSP1CLK" },
1797 { "AIF1DAC1R", NULL, "AIF1CLK" },
1798 { "AIF1DAC1R", NULL, "DSP1CLK" },
1799 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1800
1801 { "AIF1ADC2L", NULL, "AIF1CLK" },
1802 { "AIF1ADC2L", NULL, "DSP1CLK" },
1803 { "AIF1ADC2R", NULL, "AIF1CLK" },
1804 { "AIF1ADC2R", NULL, "DSP1CLK" },
1805 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1806
1807 { "AIF1DAC2L", NULL, "AIF1CLK" },
1808 { "AIF1DAC2L", NULL, "DSP1CLK" },
1809 { "AIF1DAC2R", NULL, "AIF1CLK" },
1810 { "AIF1DAC2R", NULL, "DSP1CLK" },
1811 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1812
1813 { "AIF2ADCL", NULL, "AIF2CLK" },
1814 { "AIF2ADCL", NULL, "DSP2CLK" },
1815 { "AIF2ADCR", NULL, "AIF2CLK" },
1816 { "AIF2ADCR", NULL, "DSP2CLK" },
1817 { "AIF2ADCR", NULL, "DSPINTCLK" },
1818
1819 { "AIF2DACL", NULL, "AIF2CLK" },
1820 { "AIF2DACL", NULL, "DSP2CLK" },
1821 { "AIF2DACR", NULL, "AIF2CLK" },
1822 { "AIF2DACR", NULL, "DSP2CLK" },
1823 { "AIF2DACR", NULL, "DSPINTCLK" },
1824
1825 { "DMIC1L", NULL, "DMIC1DAT" },
1826 { "DMIC1L", NULL, "CLK_SYS" },
1827 { "DMIC1R", NULL, "DMIC1DAT" },
1828 { "DMIC1R", NULL, "CLK_SYS" },
1829 { "DMIC2L", NULL, "DMIC2DAT" },
1830 { "DMIC2L", NULL, "CLK_SYS" },
1831 { "DMIC2R", NULL, "DMIC2DAT" },
1832 { "DMIC2R", NULL, "CLK_SYS" },
1833
1834 { "ADCL", NULL, "AIF1CLK" },
1835 { "ADCL", NULL, "DSP1CLK" },
1836 { "ADCL", NULL, "DSPINTCLK" },
1837
1838 { "ADCR", NULL, "AIF1CLK" },
1839 { "ADCR", NULL, "DSP1CLK" },
1840 { "ADCR", NULL, "DSPINTCLK" },
1841
1842 { "ADCL Mux", "ADC", "ADCL" },
1843 { "ADCL Mux", "DMIC", "DMIC1L" },
1844 { "ADCR Mux", "ADC", "ADCR" },
1845 { "ADCR Mux", "DMIC", "DMIC1R" },
1846
1847 { "DAC1L", NULL, "AIF1CLK" },
1848 { "DAC1L", NULL, "DSP1CLK" },
1849 { "DAC1L", NULL, "DSPINTCLK" },
1850
1851 { "DAC1R", NULL, "AIF1CLK" },
1852 { "DAC1R", NULL, "DSP1CLK" },
1853 { "DAC1R", NULL, "DSPINTCLK" },
1854
1855 { "DAC2L", NULL, "AIF2CLK" },
1856 { "DAC2L", NULL, "DSP2CLK" },
1857 { "DAC2L", NULL, "DSPINTCLK" },
1858
1859 { "DAC2R", NULL, "AIF2DACR" },
1860 { "DAC2R", NULL, "AIF2CLK" },
1861 { "DAC2R", NULL, "DSP2CLK" },
1862 { "DAC2R", NULL, "DSPINTCLK" },
1863
1864 { "TOCLK", NULL, "CLK_SYS" },
1865
1866 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1867 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1868 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1869
1870 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1871 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1872 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1873
1874 /* AIF1 outputs */
1875 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1876 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1877 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1878
1879 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1880 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1881 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1882
1883 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1884 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1885 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1886
1887 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1888 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1889 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1890
1891 /* Pin level routing for AIF3 */
1892 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1893 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1894 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1895 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1896
1897 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1898 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1899 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1900 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1901 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1902 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1903 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1904
1905 /* DAC1 inputs */
1906 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1907 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1908 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1909 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1910 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1911
1912 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1913 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1914 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1915 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1916 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1917
1918 /* DAC2/AIF2 outputs */
1919 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1920 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1921 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1922 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1923 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1924 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1925
1926 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1927 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1928 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1929 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1930 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1931 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1932
1933 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1934 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1935 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1936 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1937
1938 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1939
1940 /* AIF3 output */
1941 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1942 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1943 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1944 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1945 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1946 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1947 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1948 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1949
1950 /* Loopback */
1951 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1952 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1953 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1954 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1955
1956 /* Sidetone */
1957 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1958 { "Left Sidetone", "DMIC2", "DMIC2L" },
1959 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1960 { "Right Sidetone", "DMIC2", "DMIC2R" },
1961
1962 /* Output stages */
1963 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1964 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1965
1966 { "SPKL", "DAC1 Switch", "DAC1L" },
1967 { "SPKL", "DAC2 Switch", "DAC2L" },
1968
1969 { "SPKR", "DAC1 Switch", "DAC1R" },
1970 { "SPKR", "DAC2 Switch", "DAC2R" },
1971
1972 { "Left Headphone Mux", "DAC", "DAC1L" },
1973 { "Right Headphone Mux", "DAC", "DAC1R" },
1974 };
1975
1976 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1977 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1978 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1979 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1980 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1981 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1982 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1983 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1984 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1985 };
1986
1987 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1988 { "DAC1L", NULL, "DAC1L Mixer" },
1989 { "DAC1R", NULL, "DAC1R Mixer" },
1990 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1991 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1992 };
1993
1994 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1995 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1996 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1997 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1998 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1999 { "MICBIAS1", NULL, "CLK_SYS" },
2000 { "MICBIAS1", NULL, "MICBIAS Supply" },
2001 { "MICBIAS2", NULL, "CLK_SYS" },
2002 { "MICBIAS2", NULL, "MICBIAS Supply" },
2003 };
2004
2005 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2006 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2007 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2008 { "MICBIAS1", NULL, "VMID" },
2009 { "MICBIAS2", NULL, "VMID" },
2010 };
2011
2012 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2013 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2014 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2015
2016 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2017 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2018 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2019 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2020
2021 { "AIF3DACDAT", NULL, "AIF3" },
2022 { "AIF3ADCDAT", NULL, "AIF3" },
2023
2024 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2025 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2026
2027 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2028 };
2029
2030 /* The size in bits of the FLL divide multiplied by 10
2031 * to allow rounding later */
2032 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2033
2034 struct fll_div {
2035 u16 outdiv;
2036 u16 n;
2037 u16 k;
2038 u16 lambda;
2039 u16 clk_ref_div;
2040 u16 fll_fratio;
2041 };
2042
2043 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2044 int freq_in, int freq_out)
2045 {
2046 u64 Kpart;
2047 unsigned int K, Ndiv, Nmod, gcd_fll;
2048
2049 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2050
2051 /* Scale the input frequency down to <= 13.5MHz */
2052 fll->clk_ref_div = 0;
2053 while (freq_in > 13500000) {
2054 fll->clk_ref_div++;
2055 freq_in /= 2;
2056
2057 if (fll->clk_ref_div > 3)
2058 return -EINVAL;
2059 }
2060 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2061
2062 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2063 fll->outdiv = 3;
2064 while (freq_out * (fll->outdiv + 1) < 90000000) {
2065 fll->outdiv++;
2066 if (fll->outdiv > 63)
2067 return -EINVAL;
2068 }
2069 freq_out *= fll->outdiv + 1;
2070 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2071
2072 if (freq_in > 1000000) {
2073 fll->fll_fratio = 0;
2074 } else if (freq_in > 256000) {
2075 fll->fll_fratio = 1;
2076 freq_in *= 2;
2077 } else if (freq_in > 128000) {
2078 fll->fll_fratio = 2;
2079 freq_in *= 4;
2080 } else if (freq_in > 64000) {
2081 fll->fll_fratio = 3;
2082 freq_in *= 8;
2083 } else {
2084 fll->fll_fratio = 4;
2085 freq_in *= 16;
2086 }
2087 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2088
2089 /* Now, calculate N.K */
2090 Ndiv = freq_out / freq_in;
2091
2092 fll->n = Ndiv;
2093 Nmod = freq_out % freq_in;
2094 pr_debug("Nmod=%d\n", Nmod);
2095
2096 switch (control->type) {
2097 case WM8994:
2098 /* Calculate fractional part - scale up so we can round. */
2099 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2100
2101 do_div(Kpart, freq_in);
2102
2103 K = Kpart & 0xFFFFFFFF;
2104
2105 if ((K % 10) >= 5)
2106 K += 5;
2107
2108 /* Move down to proper range now rounding is done */
2109 fll->k = K / 10;
2110 fll->lambda = 0;
2111
2112 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2113 break;
2114
2115 default:
2116 gcd_fll = gcd(freq_out, freq_in);
2117
2118 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2119 fll->lambda = freq_in / gcd_fll;
2120
2121 }
2122
2123 return 0;
2124 }
2125
2126 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2127 unsigned int freq_in, unsigned int freq_out)
2128 {
2129 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2130 struct wm8994 *control = wm8994->wm8994;
2131 int reg_offset, ret;
2132 struct fll_div fll;
2133 u16 reg, clk1, aif_reg, aif_src;
2134 unsigned long timeout;
2135 bool was_enabled;
2136
2137 switch (id) {
2138 case WM8994_FLL1:
2139 reg_offset = 0;
2140 id = 0;
2141 aif_src = 0x10;
2142 break;
2143 case WM8994_FLL2:
2144 reg_offset = 0x20;
2145 id = 1;
2146 aif_src = 0x18;
2147 break;
2148 default:
2149 return -EINVAL;
2150 }
2151
2152 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2153 was_enabled = reg & WM8994_FLL1_ENA;
2154
2155 switch (src) {
2156 case 0:
2157 /* Allow no source specification when stopping */
2158 if (freq_out)
2159 return -EINVAL;
2160 src = wm8994->fll[id].src;
2161 break;
2162 case WM8994_FLL_SRC_MCLK1:
2163 case WM8994_FLL_SRC_MCLK2:
2164 case WM8994_FLL_SRC_LRCLK:
2165 case WM8994_FLL_SRC_BCLK:
2166 break;
2167 case WM8994_FLL_SRC_INTERNAL:
2168 freq_in = 12000000;
2169 freq_out = 12000000;
2170 break;
2171 default:
2172 return -EINVAL;
2173 }
2174
2175 /* Are we changing anything? */
2176 if (wm8994->fll[id].src == src &&
2177 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2178 return 0;
2179
2180 /* If we're stopping the FLL redo the old config - no
2181 * registers will actually be written but we avoid GCC flow
2182 * analysis bugs spewing warnings.
2183 */
2184 if (freq_out)
2185 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2186 else
2187 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2188 wm8994->fll[id].out);
2189 if (ret < 0)
2190 return ret;
2191
2192 /* Make sure that we're not providing SYSCLK right now */
2193 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2194 if (clk1 & WM8994_SYSCLK_SRC)
2195 aif_reg = WM8994_AIF2_CLOCKING_1;
2196 else
2197 aif_reg = WM8994_AIF1_CLOCKING_1;
2198 reg = snd_soc_read(codec, aif_reg);
2199
2200 if ((reg & WM8994_AIF1CLK_ENA) &&
2201 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2202 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2203 id + 1);
2204 return -EBUSY;
2205 }
2206
2207 /* We always need to disable the FLL while reconfiguring */
2208 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2209 WM8994_FLL1_ENA, 0);
2210
2211 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2212 freq_in == freq_out && freq_out) {
2213 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2214 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2215 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2216 goto out;
2217 }
2218
2219 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2220 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2221 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2222 WM8994_FLL1_OUTDIV_MASK |
2223 WM8994_FLL1_FRATIO_MASK, reg);
2224
2225 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2226 WM8994_FLL1_K_MASK, fll.k);
2227
2228 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2229 WM8994_FLL1_N_MASK,
2230 fll.n << WM8994_FLL1_N_SHIFT);
2231
2232 if (fll.lambda) {
2233 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2234 WM8958_FLL1_LAMBDA_MASK,
2235 fll.lambda);
2236 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2237 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2238 } else {
2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2240 WM8958_FLL1_EFS_ENA, 0);
2241 }
2242
2243 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2244 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2245 WM8994_FLL1_REFCLK_DIV_MASK |
2246 WM8994_FLL1_REFCLK_SRC_MASK,
2247 ((src == WM8994_FLL_SRC_INTERNAL)
2248 << WM8994_FLL1_FRC_NCO_SHIFT) |
2249 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2250 (src - 1));
2251
2252 /* Clear any pending completion from a previous failure */
2253 try_wait_for_completion(&wm8994->fll_locked[id]);
2254
2255 /* Enable (with fractional mode if required) */
2256 if (freq_out) {
2257 /* Enable VMID if we need it */
2258 if (!was_enabled) {
2259 active_reference(codec);
2260
2261 switch (control->type) {
2262 case WM8994:
2263 vmid_reference(codec);
2264 break;
2265 case WM8958:
2266 if (control->revision < 1)
2267 vmid_reference(codec);
2268 break;
2269 default:
2270 break;
2271 }
2272 }
2273
2274 reg = WM8994_FLL1_ENA;
2275
2276 if (fll.k)
2277 reg |= WM8994_FLL1_FRAC;
2278 if (src == WM8994_FLL_SRC_INTERNAL)
2279 reg |= WM8994_FLL1_OSC_ENA;
2280
2281 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2282 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2283 WM8994_FLL1_FRAC, reg);
2284
2285 if (wm8994->fll_locked_irq) {
2286 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2287 msecs_to_jiffies(10));
2288 if (timeout == 0)
2289 dev_warn(codec->dev,
2290 "Timed out waiting for FLL lock\n");
2291 } else {
2292 msleep(5);
2293 }
2294 } else {
2295 if (was_enabled) {
2296 switch (control->type) {
2297 case WM8994:
2298 vmid_dereference(codec);
2299 break;
2300 case WM8958:
2301 if (control->revision < 1)
2302 vmid_dereference(codec);
2303 break;
2304 default:
2305 break;
2306 }
2307
2308 active_dereference(codec);
2309 }
2310 }
2311
2312 out:
2313 wm8994->fll[id].in = freq_in;
2314 wm8994->fll[id].out = freq_out;
2315 wm8994->fll[id].src = src;
2316
2317 configure_clock(codec);
2318
2319 /*
2320 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2321 * for detection.
2322 */
2323 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2324 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2325
2326 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2327 & WM8994_AIF1CLK_RATE_MASK;
2328 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2329 & WM8994_AIF1CLK_RATE_MASK;
2330
2331 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2332 WM8994_AIF1CLK_RATE_MASK, 0x1);
2333 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2334 WM8994_AIF2CLK_RATE_MASK, 0x1);
2335 } else if (wm8994->aifdiv[0]) {
2336 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2337 WM8994_AIF1CLK_RATE_MASK,
2338 wm8994->aifdiv[0]);
2339 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2340 WM8994_AIF2CLK_RATE_MASK,
2341 wm8994->aifdiv[1]);
2342
2343 wm8994->aifdiv[0] = 0;
2344 wm8994->aifdiv[1] = 0;
2345 }
2346
2347 return 0;
2348 }
2349
2350 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2351 {
2352 struct completion *completion = data;
2353
2354 complete(completion);
2355
2356 return IRQ_HANDLED;
2357 }
2358
2359 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2360
2361 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2362 unsigned int freq_in, unsigned int freq_out)
2363 {
2364 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2365 }
2366
2367 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2368 int clk_id, unsigned int freq, int dir)
2369 {
2370 struct snd_soc_codec *codec = dai->codec;
2371 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2372 int i;
2373
2374 switch (dai->id) {
2375 case 1:
2376 case 2:
2377 break;
2378
2379 default:
2380 /* AIF3 shares clocking with AIF1/2 */
2381 return -EINVAL;
2382 }
2383
2384 switch (clk_id) {
2385 case WM8994_SYSCLK_MCLK1:
2386 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2387 wm8994->mclk[0] = freq;
2388 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2389 dai->id, freq);
2390 break;
2391
2392 case WM8994_SYSCLK_MCLK2:
2393 /* TODO: Set GPIO AF */
2394 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2395 wm8994->mclk[1] = freq;
2396 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2397 dai->id, freq);
2398 break;
2399
2400 case WM8994_SYSCLK_FLL1:
2401 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2402 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2403 break;
2404
2405 case WM8994_SYSCLK_FLL2:
2406 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2407 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2408 break;
2409
2410 case WM8994_SYSCLK_OPCLK:
2411 /* Special case - a division (times 10) is given and
2412 * no effect on main clocking.
2413 */
2414 if (freq) {
2415 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2416 if (opclk_divs[i] == freq)
2417 break;
2418 if (i == ARRAY_SIZE(opclk_divs))
2419 return -EINVAL;
2420 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2421 WM8994_OPCLK_DIV_MASK, i);
2422 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2423 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2424 } else {
2425 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2426 WM8994_OPCLK_ENA, 0);
2427 }
2428
2429 default:
2430 return -EINVAL;
2431 }
2432
2433 configure_clock(codec);
2434
2435 /*
2436 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2437 * for detection.
2438 */
2439 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2440 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2441
2442 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2443 & WM8994_AIF1CLK_RATE_MASK;
2444 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2445 & WM8994_AIF1CLK_RATE_MASK;
2446
2447 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2448 WM8994_AIF1CLK_RATE_MASK, 0x1);
2449 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2450 WM8994_AIF2CLK_RATE_MASK, 0x1);
2451 } else if (wm8994->aifdiv[0]) {
2452 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2453 WM8994_AIF1CLK_RATE_MASK,
2454 wm8994->aifdiv[0]);
2455 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2456 WM8994_AIF2CLK_RATE_MASK,
2457 wm8994->aifdiv[1]);
2458
2459 wm8994->aifdiv[0] = 0;
2460 wm8994->aifdiv[1] = 0;
2461 }
2462
2463 return 0;
2464 }
2465
2466 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2467 enum snd_soc_bias_level level)
2468 {
2469 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2470 struct wm8994 *control = wm8994->wm8994;
2471
2472 wm_hubs_set_bias_level(codec, level);
2473
2474 switch (level) {
2475 case SND_SOC_BIAS_ON:
2476 break;
2477
2478 case SND_SOC_BIAS_PREPARE:
2479 /* MICBIAS into regulating mode */
2480 switch (control->type) {
2481 case WM8958:
2482 case WM1811:
2483 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2484 WM8958_MICB1_MODE, 0);
2485 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2486 WM8958_MICB2_MODE, 0);
2487 break;
2488 default:
2489 break;
2490 }
2491
2492 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2493 active_reference(codec);
2494 break;
2495
2496 case SND_SOC_BIAS_STANDBY:
2497 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2498 switch (control->type) {
2499 case WM8958:
2500 if (control->revision == 0) {
2501 /* Optimise performance for rev A */
2502 snd_soc_update_bits(codec,
2503 WM8958_CHARGE_PUMP_2,
2504 WM8958_CP_DISCH,
2505 WM8958_CP_DISCH);
2506 }
2507 break;
2508
2509 default:
2510 break;
2511 }
2512
2513 /* Discharge LINEOUT1 & 2 */
2514 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2515 WM8994_LINEOUT1_DISCH |
2516 WM8994_LINEOUT2_DISCH,
2517 WM8994_LINEOUT1_DISCH |
2518 WM8994_LINEOUT2_DISCH);
2519 }
2520
2521 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2522 active_dereference(codec);
2523
2524 /* MICBIAS into bypass mode on newer devices */
2525 switch (control->type) {
2526 case WM8958:
2527 case WM1811:
2528 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2529 WM8958_MICB1_MODE,
2530 WM8958_MICB1_MODE);
2531 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2532 WM8958_MICB2_MODE,
2533 WM8958_MICB2_MODE);
2534 break;
2535 default:
2536 break;
2537 }
2538 break;
2539
2540 case SND_SOC_BIAS_OFF:
2541 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2542 wm8994->cur_fw = NULL;
2543 break;
2544 }
2545
2546 codec->dapm.bias_level = level;
2547
2548 return 0;
2549 }
2550
2551 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2552 {
2553 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2554
2555 switch (mode) {
2556 case WM8994_VMID_NORMAL:
2557 if (wm8994->hubs.lineout1_se) {
2558 snd_soc_dapm_disable_pin(&codec->dapm,
2559 "LINEOUT1N Driver");
2560 snd_soc_dapm_disable_pin(&codec->dapm,
2561 "LINEOUT1P Driver");
2562 }
2563 if (wm8994->hubs.lineout2_se) {
2564 snd_soc_dapm_disable_pin(&codec->dapm,
2565 "LINEOUT2N Driver");
2566 snd_soc_dapm_disable_pin(&codec->dapm,
2567 "LINEOUT2P Driver");
2568 }
2569
2570 /* Do the sync with the old mode to allow it to clean up */
2571 snd_soc_dapm_sync(&codec->dapm);
2572 wm8994->vmid_mode = mode;
2573 break;
2574
2575 case WM8994_VMID_FORCE:
2576 if (wm8994->hubs.lineout1_se) {
2577 snd_soc_dapm_force_enable_pin(&codec->dapm,
2578 "LINEOUT1N Driver");
2579 snd_soc_dapm_force_enable_pin(&codec->dapm,
2580 "LINEOUT1P Driver");
2581 }
2582 if (wm8994->hubs.lineout2_se) {
2583 snd_soc_dapm_force_enable_pin(&codec->dapm,
2584 "LINEOUT2N Driver");
2585 snd_soc_dapm_force_enable_pin(&codec->dapm,
2586 "LINEOUT2P Driver");
2587 }
2588
2589 wm8994->vmid_mode = mode;
2590 snd_soc_dapm_sync(&codec->dapm);
2591 break;
2592
2593 default:
2594 return -EINVAL;
2595 }
2596
2597 return 0;
2598 }
2599
2600 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2601 {
2602 struct snd_soc_codec *codec = dai->codec;
2603 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2604 struct wm8994 *control = wm8994->wm8994;
2605 int ms_reg;
2606 int aif1_reg;
2607 int dac_reg;
2608 int adc_reg;
2609 int ms = 0;
2610 int aif1 = 0;
2611 int lrclk = 0;
2612
2613 switch (dai->id) {
2614 case 1:
2615 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2616 aif1_reg = WM8994_AIF1_CONTROL_1;
2617 dac_reg = WM8994_AIF1DAC_LRCLK;
2618 adc_reg = WM8994_AIF1ADC_LRCLK;
2619 break;
2620 case 2:
2621 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2622 aif1_reg = WM8994_AIF2_CONTROL_1;
2623 dac_reg = WM8994_AIF1DAC_LRCLK;
2624 adc_reg = WM8994_AIF1ADC_LRCLK;
2625 break;
2626 default:
2627 return -EINVAL;
2628 }
2629
2630 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2631 case SND_SOC_DAIFMT_CBS_CFS:
2632 break;
2633 case SND_SOC_DAIFMT_CBM_CFM:
2634 ms = WM8994_AIF1_MSTR;
2635 break;
2636 default:
2637 return -EINVAL;
2638 }
2639
2640 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2641 case SND_SOC_DAIFMT_DSP_B:
2642 aif1 |= WM8994_AIF1_LRCLK_INV;
2643 lrclk |= WM8958_AIF1_LRCLK_INV;
2644 case SND_SOC_DAIFMT_DSP_A:
2645 aif1 |= 0x18;
2646 break;
2647 case SND_SOC_DAIFMT_I2S:
2648 aif1 |= 0x10;
2649 break;
2650 case SND_SOC_DAIFMT_RIGHT_J:
2651 break;
2652 case SND_SOC_DAIFMT_LEFT_J:
2653 aif1 |= 0x8;
2654 break;
2655 default:
2656 return -EINVAL;
2657 }
2658
2659 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2660 case SND_SOC_DAIFMT_DSP_A:
2661 case SND_SOC_DAIFMT_DSP_B:
2662 /* frame inversion not valid for DSP modes */
2663 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2664 case SND_SOC_DAIFMT_NB_NF:
2665 break;
2666 case SND_SOC_DAIFMT_IB_NF:
2667 aif1 |= WM8994_AIF1_BCLK_INV;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672 break;
2673
2674 case SND_SOC_DAIFMT_I2S:
2675 case SND_SOC_DAIFMT_RIGHT_J:
2676 case SND_SOC_DAIFMT_LEFT_J:
2677 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2678 case SND_SOC_DAIFMT_NB_NF:
2679 break;
2680 case SND_SOC_DAIFMT_IB_IF:
2681 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2682 lrclk |= WM8958_AIF1_LRCLK_INV;
2683 break;
2684 case SND_SOC_DAIFMT_IB_NF:
2685 aif1 |= WM8994_AIF1_BCLK_INV;
2686 break;
2687 case SND_SOC_DAIFMT_NB_IF:
2688 aif1 |= WM8994_AIF1_LRCLK_INV;
2689 lrclk |= WM8958_AIF1_LRCLK_INV;
2690 break;
2691 default:
2692 return -EINVAL;
2693 }
2694 break;
2695 default:
2696 return -EINVAL;
2697 }
2698
2699 /* The AIF2 format configuration needs to be mirrored to AIF3
2700 * on WM8958 if it's in use so just do it all the time. */
2701 switch (control->type) {
2702 case WM1811:
2703 case WM8958:
2704 if (dai->id == 2)
2705 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2706 WM8994_AIF1_LRCLK_INV |
2707 WM8958_AIF3_FMT_MASK, aif1);
2708 break;
2709
2710 default:
2711 break;
2712 }
2713
2714 snd_soc_update_bits(codec, aif1_reg,
2715 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2716 WM8994_AIF1_FMT_MASK,
2717 aif1);
2718 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2719 ms);
2720 snd_soc_update_bits(codec, dac_reg,
2721 WM8958_AIF1_LRCLK_INV, lrclk);
2722 snd_soc_update_bits(codec, adc_reg,
2723 WM8958_AIF1_LRCLK_INV, lrclk);
2724
2725 return 0;
2726 }
2727
2728 static struct {
2729 int val, rate;
2730 } srs[] = {
2731 { 0, 8000 },
2732 { 1, 11025 },
2733 { 2, 12000 },
2734 { 3, 16000 },
2735 { 4, 22050 },
2736 { 5, 24000 },
2737 { 6, 32000 },
2738 { 7, 44100 },
2739 { 8, 48000 },
2740 { 9, 88200 },
2741 { 10, 96000 },
2742 };
2743
2744 static int fs_ratios[] = {
2745 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2746 };
2747
2748 static int bclk_divs[] = {
2749 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2750 640, 880, 960, 1280, 1760, 1920
2751 };
2752
2753 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2754 struct snd_pcm_hw_params *params,
2755 struct snd_soc_dai *dai)
2756 {
2757 struct snd_soc_codec *codec = dai->codec;
2758 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2759 struct wm8994 *control = wm8994->wm8994;
2760 struct wm8994_pdata *pdata = &control->pdata;
2761 int aif1_reg;
2762 int aif2_reg;
2763 int bclk_reg;
2764 int lrclk_reg;
2765 int rate_reg;
2766 int aif1 = 0;
2767 int aif2 = 0;
2768 int bclk = 0;
2769 int lrclk = 0;
2770 int rate_val = 0;
2771 int id = dai->id - 1;
2772
2773 int i, cur_val, best_val, bclk_rate, best;
2774
2775 switch (dai->id) {
2776 case 1:
2777 aif1_reg = WM8994_AIF1_CONTROL_1;
2778 aif2_reg = WM8994_AIF1_CONTROL_2;
2779 bclk_reg = WM8994_AIF1_BCLK;
2780 rate_reg = WM8994_AIF1_RATE;
2781 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2782 wm8994->lrclk_shared[0]) {
2783 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2784 } else {
2785 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2786 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2787 }
2788 break;
2789 case 2:
2790 aif1_reg = WM8994_AIF2_CONTROL_1;
2791 aif2_reg = WM8994_AIF2_CONTROL_2;
2792 bclk_reg = WM8994_AIF2_BCLK;
2793 rate_reg = WM8994_AIF2_RATE;
2794 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2795 wm8994->lrclk_shared[1]) {
2796 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2797 } else {
2798 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2799 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2800 }
2801 break;
2802 default:
2803 return -EINVAL;
2804 }
2805
2806 bclk_rate = params_rate(params);
2807 switch (params_format(params)) {
2808 case SNDRV_PCM_FORMAT_S16_LE:
2809 bclk_rate *= 16;
2810 break;
2811 case SNDRV_PCM_FORMAT_S20_3LE:
2812 bclk_rate *= 20;
2813 aif1 |= 0x20;
2814 break;
2815 case SNDRV_PCM_FORMAT_S24_LE:
2816 bclk_rate *= 24;
2817 aif1 |= 0x40;
2818 break;
2819 case SNDRV_PCM_FORMAT_S32_LE:
2820 bclk_rate *= 32;
2821 aif1 |= 0x60;
2822 break;
2823 default:
2824 return -EINVAL;
2825 }
2826
2827 wm8994->channels[id] = params_channels(params);
2828 if (pdata->max_channels_clocked[id] &&
2829 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2830 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2831 pdata->max_channels_clocked[id], wm8994->channels[id]);
2832 wm8994->channels[id] = pdata->max_channels_clocked[id];
2833 }
2834
2835 switch (wm8994->channels[id]) {
2836 case 1:
2837 case 2:
2838 bclk_rate *= 2;
2839 break;
2840 default:
2841 bclk_rate *= 4;
2842 break;
2843 }
2844
2845 /* Try to find an appropriate sample rate; look for an exact match. */
2846 for (i = 0; i < ARRAY_SIZE(srs); i++)
2847 if (srs[i].rate == params_rate(params))
2848 break;
2849 if (i == ARRAY_SIZE(srs))
2850 return -EINVAL;
2851 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2852
2853 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2854 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2855 dai->id, wm8994->aifclk[id], bclk_rate);
2856
2857 if (wm8994->channels[id] == 1 &&
2858 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2859 aif2 |= WM8994_AIF1_MONO;
2860
2861 if (wm8994->aifclk[id] == 0) {
2862 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2863 return -EINVAL;
2864 }
2865
2866 /* AIFCLK/fs ratio; look for a close match in either direction */
2867 best = 0;
2868 best_val = abs((fs_ratios[0] * params_rate(params))
2869 - wm8994->aifclk[id]);
2870 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2871 cur_val = abs((fs_ratios[i] * params_rate(params))
2872 - wm8994->aifclk[id]);
2873 if (cur_val >= best_val)
2874 continue;
2875 best = i;
2876 best_val = cur_val;
2877 }
2878 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2879 dai->id, fs_ratios[best]);
2880 rate_val |= best;
2881
2882 /* We may not get quite the right frequency if using
2883 * approximate clocks so look for the closest match that is
2884 * higher than the target (we need to ensure that there enough
2885 * BCLKs to clock out the samples).
2886 */
2887 best = 0;
2888 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2889 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2890 if (cur_val < 0) /* BCLK table is sorted */
2891 break;
2892 best = i;
2893 }
2894 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2895 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2896 bclk_divs[best], bclk_rate);
2897 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2898
2899 lrclk = bclk_rate / params_rate(params);
2900 if (!lrclk) {
2901 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2902 bclk_rate);
2903 return -EINVAL;
2904 }
2905 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2906 lrclk, bclk_rate / lrclk);
2907
2908 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2909 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2910 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2911 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2912 lrclk);
2913 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2914 WM8994_AIF1CLK_RATE_MASK, rate_val);
2915
2916 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2917 switch (dai->id) {
2918 case 1:
2919 wm8994->dac_rates[0] = params_rate(params);
2920 wm8994_set_retune_mobile(codec, 0);
2921 wm8994_set_retune_mobile(codec, 1);
2922 break;
2923 case 2:
2924 wm8994->dac_rates[1] = params_rate(params);
2925 wm8994_set_retune_mobile(codec, 2);
2926 break;
2927 }
2928 }
2929
2930 return 0;
2931 }
2932
2933 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2934 struct snd_pcm_hw_params *params,
2935 struct snd_soc_dai *dai)
2936 {
2937 struct snd_soc_codec *codec = dai->codec;
2938 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2939 struct wm8994 *control = wm8994->wm8994;
2940 int aif1_reg;
2941 int aif1 = 0;
2942
2943 switch (dai->id) {
2944 case 3:
2945 switch (control->type) {
2946 case WM1811:
2947 case WM8958:
2948 aif1_reg = WM8958_AIF3_CONTROL_1;
2949 break;
2950 default:
2951 return 0;
2952 }
2953 break;
2954 default:
2955 return 0;
2956 }
2957
2958 switch (params_format(params)) {
2959 case SNDRV_PCM_FORMAT_S16_LE:
2960 break;
2961 case SNDRV_PCM_FORMAT_S20_3LE:
2962 aif1 |= 0x20;
2963 break;
2964 case SNDRV_PCM_FORMAT_S24_LE:
2965 aif1 |= 0x40;
2966 break;
2967 case SNDRV_PCM_FORMAT_S32_LE:
2968 aif1 |= 0x60;
2969 break;
2970 default:
2971 return -EINVAL;
2972 }
2973
2974 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2975 }
2976
2977 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2978 {
2979 struct snd_soc_codec *codec = codec_dai->codec;
2980 int mute_reg;
2981 int reg;
2982
2983 switch (codec_dai->id) {
2984 case 1:
2985 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2986 break;
2987 case 2:
2988 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2989 break;
2990 default:
2991 return -EINVAL;
2992 }
2993
2994 if (mute)
2995 reg = WM8994_AIF1DAC1_MUTE;
2996 else
2997 reg = 0;
2998
2999 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3000
3001 return 0;
3002 }
3003
3004 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3005 {
3006 struct snd_soc_codec *codec = codec_dai->codec;
3007 int reg, val, mask;
3008
3009 switch (codec_dai->id) {
3010 case 1:
3011 reg = WM8994_AIF1_MASTER_SLAVE;
3012 mask = WM8994_AIF1_TRI;
3013 break;
3014 case 2:
3015 reg = WM8994_AIF2_MASTER_SLAVE;
3016 mask = WM8994_AIF2_TRI;
3017 break;
3018 default:
3019 return -EINVAL;
3020 }
3021
3022 if (tristate)
3023 val = mask;
3024 else
3025 val = 0;
3026
3027 return snd_soc_update_bits(codec, reg, mask, val);
3028 }
3029
3030 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3031 {
3032 struct snd_soc_codec *codec = dai->codec;
3033
3034 /* Disable the pulls on the AIF if we're using it to save power. */
3035 snd_soc_update_bits(codec, WM8994_GPIO_3,
3036 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3037 snd_soc_update_bits(codec, WM8994_GPIO_4,
3038 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3039 snd_soc_update_bits(codec, WM8994_GPIO_5,
3040 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3041
3042 return 0;
3043 }
3044
3045 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3046
3047 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3048 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3049
3050 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3051 .set_sysclk = wm8994_set_dai_sysclk,
3052 .set_fmt = wm8994_set_dai_fmt,
3053 .hw_params = wm8994_hw_params,
3054 .digital_mute = wm8994_aif_mute,
3055 .set_pll = wm8994_set_fll,
3056 .set_tristate = wm8994_set_tristate,
3057 };
3058
3059 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3060 .set_sysclk = wm8994_set_dai_sysclk,
3061 .set_fmt = wm8994_set_dai_fmt,
3062 .hw_params = wm8994_hw_params,
3063 .digital_mute = wm8994_aif_mute,
3064 .set_pll = wm8994_set_fll,
3065 .set_tristate = wm8994_set_tristate,
3066 };
3067
3068 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3069 .hw_params = wm8994_aif3_hw_params,
3070 };
3071
3072 static struct snd_soc_dai_driver wm8994_dai[] = {
3073 {
3074 .name = "wm8994-aif1",
3075 .id = 1,
3076 .playback = {
3077 .stream_name = "AIF1 Playback",
3078 .channels_min = 1,
3079 .channels_max = 2,
3080 .rates = WM8994_RATES,
3081 .formats = WM8994_FORMATS,
3082 .sig_bits = 24,
3083 },
3084 .capture = {
3085 .stream_name = "AIF1 Capture",
3086 .channels_min = 1,
3087 .channels_max = 2,
3088 .rates = WM8994_RATES,
3089 .formats = WM8994_FORMATS,
3090 .sig_bits = 24,
3091 },
3092 .ops = &wm8994_aif1_dai_ops,
3093 },
3094 {
3095 .name = "wm8994-aif2",
3096 .id = 2,
3097 .playback = {
3098 .stream_name = "AIF2 Playback",
3099 .channels_min = 1,
3100 .channels_max = 2,
3101 .rates = WM8994_RATES,
3102 .formats = WM8994_FORMATS,
3103 .sig_bits = 24,
3104 },
3105 .capture = {
3106 .stream_name = "AIF2 Capture",
3107 .channels_min = 1,
3108 .channels_max = 2,
3109 .rates = WM8994_RATES,
3110 .formats = WM8994_FORMATS,
3111 .sig_bits = 24,
3112 },
3113 .probe = wm8994_aif2_probe,
3114 .ops = &wm8994_aif2_dai_ops,
3115 },
3116 {
3117 .name = "wm8994-aif3",
3118 .id = 3,
3119 .playback = {
3120 .stream_name = "AIF3 Playback",
3121 .channels_min = 1,
3122 .channels_max = 2,
3123 .rates = WM8994_RATES,
3124 .formats = WM8994_FORMATS,
3125 .sig_bits = 24,
3126 },
3127 .capture = {
3128 .stream_name = "AIF3 Capture",
3129 .channels_min = 1,
3130 .channels_max = 2,
3131 .rates = WM8994_RATES,
3132 .formats = WM8994_FORMATS,
3133 .sig_bits = 24,
3134 },
3135 .ops = &wm8994_aif3_dai_ops,
3136 }
3137 };
3138
3139 #ifdef CONFIG_PM
3140 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3141 {
3142 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3143 int i, ret;
3144
3145 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3146 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3147 sizeof(struct wm8994_fll_config));
3148 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3149 if (ret < 0)
3150 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3151 i + 1, ret);
3152 }
3153
3154 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3155
3156 return 0;
3157 }
3158
3159 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3160 {
3161 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3162 int i, ret;
3163
3164 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3165 if (!wm8994->fll_suspend[i].out)
3166 continue;
3167
3168 ret = _wm8994_set_fll(codec, i + 1,
3169 wm8994->fll_suspend[i].src,
3170 wm8994->fll_suspend[i].in,
3171 wm8994->fll_suspend[i].out);
3172 if (ret < 0)
3173 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3174 i + 1, ret);
3175 }
3176
3177 return 0;
3178 }
3179 #else
3180 #define wm8994_codec_suspend NULL
3181 #define wm8994_codec_resume NULL
3182 #endif
3183
3184 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3185 {
3186 struct snd_soc_codec *codec = wm8994->hubs.codec;
3187 struct wm8994 *control = wm8994->wm8994;
3188 struct wm8994_pdata *pdata = &control->pdata;
3189 struct snd_kcontrol_new controls[] = {
3190 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3191 wm8994->retune_mobile_enum,
3192 wm8994_get_retune_mobile_enum,
3193 wm8994_put_retune_mobile_enum),
3194 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3195 wm8994->retune_mobile_enum,
3196 wm8994_get_retune_mobile_enum,
3197 wm8994_put_retune_mobile_enum),
3198 SOC_ENUM_EXT("AIF2 EQ Mode",
3199 wm8994->retune_mobile_enum,
3200 wm8994_get_retune_mobile_enum,
3201 wm8994_put_retune_mobile_enum),
3202 };
3203 int ret, i, j;
3204 const char **t;
3205
3206 /* We need an array of texts for the enum API but the number
3207 * of texts is likely to be less than the number of
3208 * configurations due to the sample rate dependency of the
3209 * configurations. */
3210 wm8994->num_retune_mobile_texts = 0;
3211 wm8994->retune_mobile_texts = NULL;
3212 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3213 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3214 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3215 wm8994->retune_mobile_texts[j]) == 0)
3216 break;
3217 }
3218
3219 if (j != wm8994->num_retune_mobile_texts)
3220 continue;
3221
3222 /* Expand the array... */
3223 t = krealloc(wm8994->retune_mobile_texts,
3224 sizeof(char *) *
3225 (wm8994->num_retune_mobile_texts + 1),
3226 GFP_KERNEL);
3227 if (t == NULL)
3228 continue;
3229
3230 /* ...store the new entry... */
3231 t[wm8994->num_retune_mobile_texts] =
3232 pdata->retune_mobile_cfgs[i].name;
3233
3234 /* ...and remember the new version. */
3235 wm8994->num_retune_mobile_texts++;
3236 wm8994->retune_mobile_texts = t;
3237 }
3238
3239 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3240 wm8994->num_retune_mobile_texts);
3241
3242 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3243 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3244
3245 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3246 ARRAY_SIZE(controls));
3247 if (ret != 0)
3248 dev_err(wm8994->hubs.codec->dev,
3249 "Failed to add ReTune Mobile controls: %d\n", ret);
3250 }
3251
3252 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3253 {
3254 struct snd_soc_codec *codec = wm8994->hubs.codec;
3255 struct wm8994 *control = wm8994->wm8994;
3256 struct wm8994_pdata *pdata = &control->pdata;
3257 int ret, i;
3258
3259 if (!pdata)
3260 return;
3261
3262 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3263 pdata->lineout2_diff,
3264 pdata->lineout1fb,
3265 pdata->lineout2fb,
3266 pdata->jd_scthr,
3267 pdata->jd_thr,
3268 pdata->micb1_delay,
3269 pdata->micb2_delay,
3270 pdata->micbias1_lvl,
3271 pdata->micbias2_lvl);
3272
3273 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3274
3275 if (pdata->num_drc_cfgs) {
3276 struct snd_kcontrol_new controls[] = {
3277 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3278 wm8994_get_drc_enum, wm8994_put_drc_enum),
3279 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3280 wm8994_get_drc_enum, wm8994_put_drc_enum),
3281 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3282 wm8994_get_drc_enum, wm8994_put_drc_enum),
3283 };
3284
3285 /* We need an array of texts for the enum API */
3286 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3287 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3288 if (!wm8994->drc_texts) {
3289 dev_err(wm8994->hubs.codec->dev,
3290 "Failed to allocate %d DRC config texts\n",
3291 pdata->num_drc_cfgs);
3292 return;
3293 }
3294
3295 for (i = 0; i < pdata->num_drc_cfgs; i++)
3296 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3297
3298 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3299 wm8994->drc_enum.texts = wm8994->drc_texts;
3300
3301 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3302 ARRAY_SIZE(controls));
3303 for (i = 0; i < WM8994_NUM_DRC; i++)
3304 wm8994_set_drc(codec, i);
3305 } else {
3306 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3307 wm8994_drc_controls,
3308 ARRAY_SIZE(wm8994_drc_controls));
3309 }
3310
3311 if (ret != 0)
3312 dev_err(wm8994->hubs.codec->dev,
3313 "Failed to add DRC mode controls: %d\n", ret);
3314
3315
3316 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3317 pdata->num_retune_mobile_cfgs);
3318
3319 if (pdata->num_retune_mobile_cfgs)
3320 wm8994_handle_retune_mobile_pdata(wm8994);
3321 else
3322 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3323 ARRAY_SIZE(wm8994_eq_controls));
3324
3325 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3326 if (pdata->micbias[i]) {
3327 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3328 pdata->micbias[i] & 0xffff);
3329 }
3330 }
3331 }
3332
3333 /**
3334 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3335 *
3336 * @codec: WM8994 codec
3337 * @jack: jack to report detection events on
3338 * @micbias: microphone bias to detect on
3339 *
3340 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3341 * being used to bring out signals to the processor then only platform
3342 * data configuration is needed for WM8994 and processor GPIOs should
3343 * be configured using snd_soc_jack_add_gpios() instead.
3344 *
3345 * Configuration of detection levels is available via the micbias1_lvl
3346 * and micbias2_lvl platform data members.
3347 */
3348 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3349 int micbias)
3350 {
3351 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3352 struct wm8994_micdet *micdet;
3353 struct wm8994 *control = wm8994->wm8994;
3354 int reg, ret;
3355
3356 if (control->type != WM8994) {
3357 dev_warn(codec->dev, "Not a WM8994\n");
3358 return -EINVAL;
3359 }
3360
3361 switch (micbias) {
3362 case 1:
3363 micdet = &wm8994->micdet[0];
3364 if (jack)
3365 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3366 "MICBIAS1");
3367 else
3368 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3369 "MICBIAS1");
3370 break;
3371 case 2:
3372 micdet = &wm8994->micdet[1];
3373 if (jack)
3374 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3375 "MICBIAS1");
3376 else
3377 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3378 "MICBIAS1");
3379 break;
3380 default:
3381 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3382 return -EINVAL;
3383 }
3384
3385 if (ret != 0)
3386 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3387 micbias, ret);
3388
3389 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3390 micbias, jack);
3391
3392 /* Store the configuration */
3393 micdet->jack = jack;
3394 micdet->detecting = true;
3395
3396 /* If either of the jacks is set up then enable detection */
3397 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3398 reg = WM8994_MICD_ENA;
3399 else
3400 reg = 0;
3401
3402 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3403
3404 /* enable MICDET and MICSHRT deboune */
3405 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3406 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3407 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3408 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3409
3410 snd_soc_dapm_sync(&codec->dapm);
3411
3412 return 0;
3413 }
3414 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3415
3416 static void wm8994_mic_work(struct work_struct *work)
3417 {
3418 struct wm8994_priv *priv = container_of(work,
3419 struct wm8994_priv,
3420 mic_work.work);
3421 struct regmap *regmap = priv->wm8994->regmap;
3422 struct device *dev = priv->wm8994->dev;
3423 unsigned int reg;
3424 int ret;
3425 int report;
3426
3427 pm_runtime_get_sync(dev);
3428
3429 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3430 if (ret < 0) {
3431 dev_err(dev, "Failed to read microphone status: %d\n",
3432 ret);
3433 pm_runtime_put(dev);
3434 return;
3435 }
3436
3437 dev_dbg(dev, "Microphone status: %x\n", reg);
3438
3439 report = 0;
3440 if (reg & WM8994_MIC1_DET_STS) {
3441 if (priv->micdet[0].detecting)
3442 report = SND_JACK_HEADSET;
3443 }
3444 if (reg & WM8994_MIC1_SHRT_STS) {
3445 if (priv->micdet[0].detecting)
3446 report = SND_JACK_HEADPHONE;
3447 else
3448 report |= SND_JACK_BTN_0;
3449 }
3450 if (report)
3451 priv->micdet[0].detecting = false;
3452 else
3453 priv->micdet[0].detecting = true;
3454
3455 snd_soc_jack_report(priv->micdet[0].jack, report,
3456 SND_JACK_HEADSET | SND_JACK_BTN_0);
3457
3458 report = 0;
3459 if (reg & WM8994_MIC2_DET_STS) {
3460 if (priv->micdet[1].detecting)
3461 report = SND_JACK_HEADSET;
3462 }
3463 if (reg & WM8994_MIC2_SHRT_STS) {
3464 if (priv->micdet[1].detecting)
3465 report = SND_JACK_HEADPHONE;
3466 else
3467 report |= SND_JACK_BTN_0;
3468 }
3469 if (report)
3470 priv->micdet[1].detecting = false;
3471 else
3472 priv->micdet[1].detecting = true;
3473
3474 snd_soc_jack_report(priv->micdet[1].jack, report,
3475 SND_JACK_HEADSET | SND_JACK_BTN_0);
3476
3477 pm_runtime_put(dev);
3478 }
3479
3480 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3481 {
3482 struct wm8994_priv *priv = data;
3483 struct snd_soc_codec *codec = priv->hubs.codec;
3484
3485 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3486 trace_snd_soc_jack_irq(dev_name(codec->dev));
3487 #endif
3488
3489 pm_wakeup_event(codec->dev, 300);
3490
3491 queue_delayed_work(system_power_efficient_wq,
3492 &priv->mic_work, msecs_to_jiffies(250));
3493
3494 return IRQ_HANDLED;
3495 }
3496
3497 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3498 {
3499 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3500
3501 if (!wm8994->jackdet)
3502 return;
3503
3504 mutex_lock(&wm8994->accdet_lock);
3505
3506 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3507
3508 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3509
3510 mutex_unlock(&wm8994->accdet_lock);
3511
3512 if (wm8994->wm8994->pdata.jd_ext_cap)
3513 snd_soc_dapm_disable_pin(&codec->dapm,
3514 "MICBIAS2");
3515 }
3516
3517 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3518 {
3519 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3520 int report;
3521
3522 report = 0;
3523 if (status & 0x4)
3524 report |= SND_JACK_BTN_0;
3525
3526 if (status & 0x8)
3527 report |= SND_JACK_BTN_1;
3528
3529 if (status & 0x10)
3530 report |= SND_JACK_BTN_2;
3531
3532 if (status & 0x20)
3533 report |= SND_JACK_BTN_3;
3534
3535 if (status & 0x40)
3536 report |= SND_JACK_BTN_4;
3537
3538 if (status & 0x80)
3539 report |= SND_JACK_BTN_5;
3540
3541 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3542 wm8994->btn_mask);
3543 }
3544
3545 static void wm8958_open_circuit_work(struct work_struct *work)
3546 {
3547 struct wm8994_priv *wm8994 = container_of(work,
3548 struct wm8994_priv,
3549 open_circuit_work.work);
3550 struct device *dev = wm8994->wm8994->dev;
3551
3552 wm1811_micd_stop(wm8994->hubs.codec);
3553
3554 mutex_lock(&wm8994->accdet_lock);
3555
3556 dev_dbg(dev, "Reporting open circuit\n");
3557
3558 wm8994->jack_mic = false;
3559 wm8994->mic_detecting = true;
3560
3561 wm8958_micd_set_rate(wm8994->hubs.codec);
3562
3563 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3564 wm8994->btn_mask |
3565 SND_JACK_HEADSET);
3566
3567 mutex_unlock(&wm8994->accdet_lock);
3568 }
3569
3570 static void wm8958_mic_id(void *data, u16 status)
3571 {
3572 struct snd_soc_codec *codec = data;
3573 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3574
3575 /* Either nothing present or just starting detection */
3576 if (!(status & WM8958_MICD_STS)) {
3577 /* If nothing present then clear our statuses */
3578 dev_dbg(codec->dev, "Detected open circuit\n");
3579
3580 queue_delayed_work(system_power_efficient_wq,
3581 &wm8994->open_circuit_work,
3582 msecs_to_jiffies(2500));
3583 return;
3584 }
3585
3586 /* If the measurement is showing a high impedence we've got a
3587 * microphone.
3588 */
3589 if (status & 0x600) {
3590 dev_dbg(codec->dev, "Detected microphone\n");
3591
3592 wm8994->mic_detecting = false;
3593 wm8994->jack_mic = true;
3594
3595 wm8958_micd_set_rate(codec);
3596
3597 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3598 SND_JACK_HEADSET);
3599 }
3600
3601
3602 if (status & 0xfc) {
3603 dev_dbg(codec->dev, "Detected headphone\n");
3604 wm8994->mic_detecting = false;
3605
3606 wm8958_micd_set_rate(codec);
3607
3608 /* If we have jackdet that will detect removal */
3609 wm1811_micd_stop(codec);
3610
3611 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3612 SND_JACK_HEADSET);
3613 }
3614 }
3615
3616 /* Deferred mic detection to allow for extra settling time */
3617 static void wm1811_mic_work(struct work_struct *work)
3618 {
3619 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3620 mic_work.work);
3621 struct wm8994 *control = wm8994->wm8994;
3622 struct snd_soc_codec *codec = wm8994->hubs.codec;
3623
3624 pm_runtime_get_sync(codec->dev);
3625
3626 /* If required for an external cap force MICBIAS on */
3627 if (control->pdata.jd_ext_cap) {
3628 snd_soc_dapm_force_enable_pin(&codec->dapm,
3629 "MICBIAS2");
3630 snd_soc_dapm_sync(&codec->dapm);
3631 }
3632
3633 mutex_lock(&wm8994->accdet_lock);
3634
3635 dev_dbg(codec->dev, "Starting mic detection\n");
3636
3637 /* Use a user-supplied callback if we have one */
3638 if (wm8994->micd_cb) {
3639 wm8994->micd_cb(wm8994->micd_cb_data);
3640 } else {
3641 /*
3642 * Start off measument of microphone impedence to find out
3643 * what's actually there.
3644 */
3645 wm8994->mic_detecting = true;
3646 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3647
3648 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3649 WM8958_MICD_ENA, WM8958_MICD_ENA);
3650 }
3651
3652 mutex_unlock(&wm8994->accdet_lock);
3653
3654 pm_runtime_put(codec->dev);
3655 }
3656
3657 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3658 {
3659 struct wm8994_priv *wm8994 = data;
3660 struct wm8994 *control = wm8994->wm8994;
3661 struct snd_soc_codec *codec = wm8994->hubs.codec;
3662 int reg, delay;
3663 bool present;
3664
3665 pm_runtime_get_sync(codec->dev);
3666
3667 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3668
3669 mutex_lock(&wm8994->accdet_lock);
3670
3671 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3672 if (reg < 0) {
3673 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3674 mutex_unlock(&wm8994->accdet_lock);
3675 pm_runtime_put(codec->dev);
3676 return IRQ_NONE;
3677 }
3678
3679 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3680
3681 present = reg & WM1811_JACKDET_LVL;
3682
3683 if (present) {
3684 dev_dbg(codec->dev, "Jack detected\n");
3685
3686 wm8958_micd_set_rate(codec);
3687
3688 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3689 WM8958_MICB2_DISCH, 0);
3690
3691 /* Disable debounce while inserted */
3692 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3693 WM1811_JACKDET_DB, 0);
3694
3695 delay = control->pdata.micdet_delay;
3696 queue_delayed_work(system_power_efficient_wq,
3697 &wm8994->mic_work,
3698 msecs_to_jiffies(delay));
3699 } else {
3700 dev_dbg(codec->dev, "Jack not detected\n");
3701
3702 cancel_delayed_work_sync(&wm8994->mic_work);
3703
3704 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3705 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3706
3707 /* Enable debounce while removed */
3708 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3709 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3710
3711 wm8994->mic_detecting = false;
3712 wm8994->jack_mic = false;
3713 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3714 WM8958_MICD_ENA, 0);
3715 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3716 }
3717
3718 mutex_unlock(&wm8994->accdet_lock);
3719
3720 /* Turn off MICBIAS if it was on for an external cap */
3721 if (control->pdata.jd_ext_cap && !present)
3722 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3723
3724 if (present)
3725 snd_soc_jack_report(wm8994->micdet[0].jack,
3726 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3727 else
3728 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3729 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3730 wm8994->btn_mask);
3731
3732 /* Since we only report deltas force an update, ensures we
3733 * avoid bootstrapping issues with the core. */
3734 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3735
3736 pm_runtime_put(codec->dev);
3737 return IRQ_HANDLED;
3738 }
3739
3740 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3741 {
3742 struct wm8994_priv *wm8994 = container_of(work,
3743 struct wm8994_priv,
3744 jackdet_bootstrap.work);
3745 wm1811_jackdet_irq(0, wm8994);
3746 }
3747
3748 /**
3749 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3750 *
3751 * @codec: WM8958 codec
3752 * @jack: jack to report detection events on
3753 *
3754 * Enable microphone detection functionality for the WM8958. By
3755 * default simple detection which supports the detection of up to 6
3756 * buttons plus video and microphone functionality is supported.
3757 *
3758 * The WM8958 has an advanced jack detection facility which is able to
3759 * support complex accessory detection, especially when used in
3760 * conjunction with external circuitry. In order to provide maximum
3761 * flexiblity a callback is provided which allows a completely custom
3762 * detection algorithm.
3763 */
3764 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3765 wm1811_micdet_cb det_cb, void *det_cb_data,
3766 wm1811_mic_id_cb id_cb, void *id_cb_data)
3767 {
3768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3769 struct wm8994 *control = wm8994->wm8994;
3770 u16 micd_lvl_sel;
3771
3772 switch (control->type) {
3773 case WM1811:
3774 case WM8958:
3775 break;
3776 default:
3777 return -EINVAL;
3778 }
3779
3780 if (jack) {
3781 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3782 snd_soc_dapm_sync(&codec->dapm);
3783
3784 wm8994->micdet[0].jack = jack;
3785
3786 if (det_cb) {
3787 wm8994->micd_cb = det_cb;
3788 wm8994->micd_cb_data = det_cb_data;
3789 } else {
3790 wm8994->mic_detecting = true;
3791 wm8994->jack_mic = false;
3792 }
3793
3794 if (id_cb) {
3795 wm8994->mic_id_cb = id_cb;
3796 wm8994->mic_id_cb_data = id_cb_data;
3797 } else {
3798 wm8994->mic_id_cb = wm8958_mic_id;
3799 wm8994->mic_id_cb_data = codec;
3800 }
3801
3802 wm8958_micd_set_rate(codec);
3803
3804 /* Detect microphones and short circuits by default */
3805 if (control->pdata.micd_lvl_sel)
3806 micd_lvl_sel = control->pdata.micd_lvl_sel;
3807 else
3808 micd_lvl_sel = 0x41;
3809
3810 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3811 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3812 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3813
3814 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3815 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3816
3817 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3818
3819 /*
3820 * If we can use jack detection start off with that,
3821 * otherwise jump straight to microphone detection.
3822 */
3823 if (wm8994->jackdet) {
3824 /* Disable debounce for the initial detect */
3825 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3826 WM1811_JACKDET_DB, 0);
3827
3828 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3829 WM8958_MICB2_DISCH,
3830 WM8958_MICB2_DISCH);
3831 snd_soc_update_bits(codec, WM8994_LDO_1,
3832 WM8994_LDO1_DISCH, 0);
3833 wm1811_jackdet_set_mode(codec,
3834 WM1811_JACKDET_MODE_JACK);
3835 } else {
3836 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3837 WM8958_MICD_ENA, WM8958_MICD_ENA);
3838 }
3839
3840 } else {
3841 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3842 WM8958_MICD_ENA, 0);
3843 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3844 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3845 snd_soc_dapm_sync(&codec->dapm);
3846 }
3847
3848 return 0;
3849 }
3850 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3851
3852 static void wm8958_mic_work(struct work_struct *work)
3853 {
3854 struct wm8994_priv *wm8994 = container_of(work,
3855 struct wm8994_priv,
3856 mic_complete_work.work);
3857 struct snd_soc_codec *codec = wm8994->hubs.codec;
3858
3859 dev_crit(codec->dev, "MIC WORK %x\n", wm8994->mic_status);
3860
3861 pm_runtime_get_sync(codec->dev);
3862
3863 mutex_lock(&wm8994->accdet_lock);
3864
3865 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3866
3867 mutex_unlock(&wm8994->accdet_lock);
3868
3869 pm_runtime_put(codec->dev);
3870
3871 dev_crit(codec->dev, "MIC WORK %x DONE\n", wm8994->mic_status);
3872 }
3873
3874 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3875 {
3876 struct wm8994_priv *wm8994 = data;
3877 struct snd_soc_codec *codec = wm8994->hubs.codec;
3878 int reg, count, ret, id_delay;
3879
3880 /*
3881 * Jack detection may have detected a removal simulataneously
3882 * with an update of the MICDET status; if so it will have
3883 * stopped detection and we can ignore this interrupt.
3884 */
3885 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3886 return IRQ_HANDLED;
3887
3888 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3889 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3890
3891 pm_runtime_get_sync(codec->dev);
3892
3893 /* We may occasionally read a detection without an impedence
3894 * range being provided - if that happens loop again.
3895 */
3896 count = 10;
3897 do {
3898 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3899 if (reg < 0) {
3900 dev_err(codec->dev,
3901 "Failed to read mic detect status: %d\n",
3902 reg);
3903 pm_runtime_put(codec->dev);
3904 return IRQ_NONE;
3905 }
3906
3907 if (!(reg & WM8958_MICD_VALID)) {
3908 dev_dbg(codec->dev, "Mic detect data not valid\n");
3909 goto out;
3910 }
3911
3912 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3913 break;
3914
3915 msleep(1);
3916 } while (count--);
3917
3918 if (count == 0)
3919 dev_warn(codec->dev, "No impedance range reported for jack\n");
3920
3921 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3922 trace_snd_soc_jack_irq(dev_name(codec->dev));
3923 #endif
3924
3925 /* Avoid a transient report when the accessory is being removed */
3926 if (wm8994->jackdet) {
3927 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3928 if (ret < 0) {
3929 dev_err(codec->dev, "Failed to read jack status: %d\n",
3930 ret);
3931 } else if (!(ret & WM1811_JACKDET_LVL)) {
3932 dev_dbg(codec->dev, "Ignoring removed jack\n");
3933 goto out;
3934 }
3935 } else if (!(reg & WM8958_MICD_STS)) {
3936 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3937 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3938 wm8994->btn_mask);
3939 wm8994->mic_detecting = true;
3940 goto out;
3941 }
3942
3943 wm8994->mic_status = reg;
3944 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3945
3946 if (wm8994->mic_detecting)
3947 queue_delayed_work(system_power_efficient_wq,
3948 &wm8994->mic_complete_work,
3949 msecs_to_jiffies(id_delay));
3950 else
3951 wm8958_button_det(codec, reg);
3952
3953 out:
3954 pm_runtime_put(codec->dev);
3955 return IRQ_HANDLED;
3956 }
3957
3958 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3959 {
3960 struct snd_soc_codec *codec = data;
3961
3962 dev_err(codec->dev, "FIFO error\n");
3963
3964 return IRQ_HANDLED;
3965 }
3966
3967 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3968 {
3969 struct snd_soc_codec *codec = data;
3970
3971 dev_err(codec->dev, "Thermal warning\n");
3972
3973 return IRQ_HANDLED;
3974 }
3975
3976 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3977 {
3978 struct snd_soc_codec *codec = data;
3979
3980 dev_crit(codec->dev, "Thermal shutdown\n");
3981
3982 return IRQ_HANDLED;
3983 }
3984
3985 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3986 {
3987 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3988 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3989 struct snd_soc_dapm_context *dapm = &codec->dapm;
3990 unsigned int reg;
3991 int ret, i;
3992
3993 wm8994->hubs.codec = codec;
3994 codec->control_data = control->regmap;
3995
3996 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3997
3998 mutex_init(&wm8994->accdet_lock);
3999 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4000 wm1811_jackdet_bootstrap);
4001 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4002 wm8958_open_circuit_work);
4003
4004 switch (control->type) {
4005 case WM8994:
4006 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4007 break;
4008 case WM1811:
4009 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4010 break;
4011 default:
4012 break;
4013 }
4014
4015 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4016
4017 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4018 init_completion(&wm8994->fll_locked[i]);
4019
4020 wm8994->micdet_irq = control->pdata.micdet_irq;
4021
4022 /* By default use idle_bias_off, will override for WM8994 */
4023 codec->dapm.idle_bias_off = 1;
4024
4025 /* Set revision-specific configuration */
4026 switch (control->type) {
4027 case WM8994:
4028 /* Single ended line outputs should have VMID on. */
4029 if (!control->pdata.lineout1_diff ||
4030 !control->pdata.lineout2_diff)
4031 codec->dapm.idle_bias_off = 0;
4032
4033 switch (control->revision) {
4034 case 2:
4035 case 3:
4036 wm8994->hubs.dcs_codes_l = -5;
4037 wm8994->hubs.dcs_codes_r = -5;
4038 wm8994->hubs.hp_startup_mode = 1;
4039 wm8994->hubs.dcs_readback_mode = 1;
4040 wm8994->hubs.series_startup = 1;
4041 break;
4042 default:
4043 wm8994->hubs.dcs_readback_mode = 2;
4044 break;
4045 }
4046 break;
4047
4048 case WM8958:
4049 wm8994->hubs.dcs_readback_mode = 1;
4050 wm8994->hubs.hp_startup_mode = 1;
4051
4052 switch (control->revision) {
4053 case 0:
4054 break;
4055 default:
4056 wm8994->fll_byp = true;
4057 break;
4058 }
4059 break;
4060
4061 case WM1811:
4062 wm8994->hubs.dcs_readback_mode = 2;
4063 wm8994->hubs.no_series_update = 1;
4064 wm8994->hubs.hp_startup_mode = 1;
4065 wm8994->hubs.no_cache_dac_hp_direct = true;
4066 wm8994->fll_byp = true;
4067
4068 wm8994->hubs.dcs_codes_l = -9;
4069 wm8994->hubs.dcs_codes_r = -7;
4070
4071 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4072 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4073 break;
4074
4075 default:
4076 break;
4077 }
4078
4079 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4080 wm8994_fifo_error, "FIFO error", codec);
4081 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4082 wm8994_temp_warn, "Thermal warning", codec);
4083 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4084 wm8994_temp_shut, "Thermal shutdown", codec);
4085
4086 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4087 wm_hubs_dcs_done, "DC servo done",
4088 &wm8994->hubs);
4089 if (ret == 0)
4090 wm8994->hubs.dcs_done_irq = true;
4091
4092 switch (control->type) {
4093 case WM8994:
4094 if (wm8994->micdet_irq) {
4095 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4096 wm8994_mic_irq,
4097 IRQF_TRIGGER_RISING,
4098 "Mic1 detect",
4099 wm8994);
4100 if (ret != 0)
4101 dev_warn(codec->dev,
4102 "Failed to request Mic1 detect IRQ: %d\n",
4103 ret);
4104 }
4105
4106 ret = wm8994_request_irq(wm8994->wm8994,
4107 WM8994_IRQ_MIC1_SHRT,
4108 wm8994_mic_irq, "Mic 1 short",
4109 wm8994);
4110 if (ret != 0)
4111 dev_warn(codec->dev,
4112 "Failed to request Mic1 short IRQ: %d\n",
4113 ret);
4114
4115 ret = wm8994_request_irq(wm8994->wm8994,
4116 WM8994_IRQ_MIC2_DET,
4117 wm8994_mic_irq, "Mic 2 detect",
4118 wm8994);
4119 if (ret != 0)
4120 dev_warn(codec->dev,
4121 "Failed to request Mic2 detect IRQ: %d\n",
4122 ret);
4123
4124 ret = wm8994_request_irq(wm8994->wm8994,
4125 WM8994_IRQ_MIC2_SHRT,
4126 wm8994_mic_irq, "Mic 2 short",
4127 wm8994);
4128 if (ret != 0)
4129 dev_warn(codec->dev,
4130 "Failed to request Mic2 short IRQ: %d\n",
4131 ret);
4132 break;
4133
4134 case WM8958:
4135 case WM1811:
4136 if (wm8994->micdet_irq) {
4137 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4138 wm8958_mic_irq,
4139 IRQF_TRIGGER_RISING,
4140 "Mic detect",
4141 wm8994);
4142 if (ret != 0)
4143 dev_warn(codec->dev,
4144 "Failed to request Mic detect IRQ: %d\n",
4145 ret);
4146 } else {
4147 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4148 wm8958_mic_irq, "Mic detect",
4149 wm8994);
4150 }
4151 }
4152
4153 switch (control->type) {
4154 case WM1811:
4155 if (control->cust_id > 1 || control->revision > 1) {
4156 ret = wm8994_request_irq(wm8994->wm8994,
4157 WM8994_IRQ_GPIO(6),
4158 wm1811_jackdet_irq, "JACKDET",
4159 wm8994);
4160 if (ret == 0)
4161 wm8994->jackdet = true;
4162 }
4163 break;
4164 default:
4165 break;
4166 }
4167
4168 wm8994->fll_locked_irq = true;
4169 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4170 ret = wm8994_request_irq(wm8994->wm8994,
4171 WM8994_IRQ_FLL1_LOCK + i,
4172 wm8994_fll_locked_irq, "FLL lock",
4173 &wm8994->fll_locked[i]);
4174 if (ret != 0)
4175 wm8994->fll_locked_irq = false;
4176 }
4177
4178 /* Make sure we can read from the GPIOs if they're inputs */
4179 pm_runtime_get_sync(codec->dev);
4180
4181 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4182 * configured on init - if a system wants to do this dynamically
4183 * at runtime we can deal with that then.
4184 */
4185 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4186 if (ret < 0) {
4187 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4188 goto err_irq;
4189 }
4190 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4191 wm8994->lrclk_shared[0] = 1;
4192 wm8994_dai[0].symmetric_rates = 1;
4193 } else {
4194 wm8994->lrclk_shared[0] = 0;
4195 }
4196
4197 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4198 if (ret < 0) {
4199 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4200 goto err_irq;
4201 }
4202 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4203 wm8994->lrclk_shared[1] = 1;
4204 wm8994_dai[1].symmetric_rates = 1;
4205 } else {
4206 wm8994->lrclk_shared[1] = 0;
4207 }
4208
4209 pm_runtime_put(codec->dev);
4210
4211 /* Latch volume update bits */
4212 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4213 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4214 wm8994_vu_bits[i].mask,
4215 wm8994_vu_bits[i].mask);
4216
4217 /* Set the low bit of the 3D stereo depth so TLV matches */
4218 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4219 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4220 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4221 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4222 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4223 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4224 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4225 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4226 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4227
4228 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4229 * use this; it only affects behaviour on idle TDM clock
4230 * cycles. */
4231 switch (control->type) {
4232 case WM8994:
4233 case WM8958:
4234 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4235 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4236 break;
4237 default:
4238 break;
4239 }
4240
4241 /* Put MICBIAS into bypass mode by default on newer devices */
4242 switch (control->type) {
4243 case WM8958:
4244 case WM1811:
4245 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4246 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4247 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4248 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4249 break;
4250 default:
4251 break;
4252 }
4253
4254 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4255 wm_hubs_update_class_w(codec);
4256
4257 wm8994_handle_pdata(wm8994);
4258
4259 wm_hubs_add_analogue_controls(codec);
4260 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4261 ARRAY_SIZE(wm8994_snd_controls));
4262 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4263 ARRAY_SIZE(wm8994_dapm_widgets));
4264
4265 switch (control->type) {
4266 case WM8994:
4267 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4268 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4269 if (control->revision < 4) {
4270 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4271 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4272 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4273 ARRAY_SIZE(wm8994_adc_revd_widgets));
4274 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4275 ARRAY_SIZE(wm8994_dac_revd_widgets));
4276 } else {
4277 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4278 ARRAY_SIZE(wm8994_lateclk_widgets));
4279 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4280 ARRAY_SIZE(wm8994_adc_widgets));
4281 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4282 ARRAY_SIZE(wm8994_dac_widgets));
4283 }
4284 break;
4285 case WM8958:
4286 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4287 ARRAY_SIZE(wm8958_snd_controls));
4288 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4289 ARRAY_SIZE(wm8958_dapm_widgets));
4290 if (control->revision < 1) {
4291 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4292 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4293 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4294 ARRAY_SIZE(wm8994_adc_revd_widgets));
4295 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4296 ARRAY_SIZE(wm8994_dac_revd_widgets));
4297 } else {
4298 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4299 ARRAY_SIZE(wm8994_lateclk_widgets));
4300 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4301 ARRAY_SIZE(wm8994_adc_widgets));
4302 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4303 ARRAY_SIZE(wm8994_dac_widgets));
4304 }
4305 break;
4306
4307 case WM1811:
4308 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4309 ARRAY_SIZE(wm8958_snd_controls));
4310 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4311 ARRAY_SIZE(wm8958_dapm_widgets));
4312 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4313 ARRAY_SIZE(wm8994_lateclk_widgets));
4314 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4315 ARRAY_SIZE(wm8994_adc_widgets));
4316 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4317 ARRAY_SIZE(wm8994_dac_widgets));
4318 break;
4319 }
4320
4321 wm_hubs_add_analogue_routes(codec, 0, 0);
4322 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4323
4324 switch (control->type) {
4325 case WM8994:
4326 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4327 ARRAY_SIZE(wm8994_intercon));
4328
4329 if (control->revision < 4) {
4330 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4331 ARRAY_SIZE(wm8994_revd_intercon));
4332 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4333 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4334 } else {
4335 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4336 ARRAY_SIZE(wm8994_lateclk_intercon));
4337 }
4338 break;
4339 case WM8958:
4340 if (control->revision < 1) {
4341 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4342 ARRAY_SIZE(wm8994_intercon));
4343 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4344 ARRAY_SIZE(wm8994_revd_intercon));
4345 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4346 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4347 } else {
4348 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4349 ARRAY_SIZE(wm8994_lateclk_intercon));
4350 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4351 ARRAY_SIZE(wm8958_intercon));
4352 }
4353
4354 wm8958_dsp2_init(codec);
4355 break;
4356 case WM1811:
4357 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4358 ARRAY_SIZE(wm8994_lateclk_intercon));
4359 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4360 ARRAY_SIZE(wm8958_intercon));
4361 break;
4362 }
4363
4364 return 0;
4365
4366 err_irq:
4367 if (wm8994->jackdet)
4368 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4369 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4370 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4371 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4372 if (wm8994->micdet_irq)
4373 free_irq(wm8994->micdet_irq, wm8994);
4374 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4376 &wm8994->fll_locked[i]);
4377 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4378 &wm8994->hubs);
4379 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4380 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4381 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4382
4383 return ret;
4384 }
4385
4386 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4387 {
4388 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4389 struct wm8994 *control = wm8994->wm8994;
4390 int i;
4391
4392 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4393
4394 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4395 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4396 &wm8994->fll_locked[i]);
4397
4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4399 &wm8994->hubs);
4400 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4401 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4402 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4403
4404 if (wm8994->jackdet)
4405 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4406
4407 switch (control->type) {
4408 case WM8994:
4409 if (wm8994->micdet_irq)
4410 free_irq(wm8994->micdet_irq, wm8994);
4411 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4412 wm8994);
4413 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4414 wm8994);
4415 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4416 wm8994);
4417 break;
4418
4419 case WM1811:
4420 case WM8958:
4421 if (wm8994->micdet_irq)
4422 free_irq(wm8994->micdet_irq, wm8994);
4423 break;
4424 }
4425 release_firmware(wm8994->mbc);
4426 release_firmware(wm8994->mbc_vss);
4427 release_firmware(wm8994->enh_eq);
4428 kfree(wm8994->retune_mobile_texts);
4429 return 0;
4430 }
4431
4432 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4433 .probe = wm8994_codec_probe,
4434 .remove = wm8994_codec_remove,
4435 .suspend = wm8994_codec_suspend,
4436 .resume = wm8994_codec_resume,
4437 .set_bias_level = wm8994_set_bias_level,
4438 };
4439
4440 static int wm8994_probe(struct platform_device *pdev)
4441 {
4442 struct wm8994_priv *wm8994;
4443
4444 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4445 GFP_KERNEL);
4446 if (wm8994 == NULL)
4447 return -ENOMEM;
4448 platform_set_drvdata(pdev, wm8994);
4449
4450 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4451
4452 pm_runtime_enable(&pdev->dev);
4453 pm_runtime_idle(&pdev->dev);
4454
4455 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4456 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4457 }
4458
4459 static int wm8994_remove(struct platform_device *pdev)
4460 {
4461 snd_soc_unregister_codec(&pdev->dev);
4462 pm_runtime_disable(&pdev->dev);
4463
4464 return 0;
4465 }
4466
4467 #ifdef CONFIG_PM_SLEEP
4468 static int wm8994_suspend(struct device *dev)
4469 {
4470 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4471
4472 /* Drop down to power saving mode when system is suspended */
4473 if (wm8994->jackdet && !wm8994->active_refcount)
4474 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4475 WM1811_JACKDET_MODE_MASK,
4476 wm8994->jackdet_mode);
4477
4478 return 0;
4479 }
4480
4481 static int wm8994_resume(struct device *dev)
4482 {
4483 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4484
4485 if (wm8994->jackdet && wm8994->jackdet_mode)
4486 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4487 WM1811_JACKDET_MODE_MASK,
4488 WM1811_JACKDET_MODE_AUDIO);
4489
4490 return 0;
4491 }
4492 #endif
4493
4494 static const struct dev_pm_ops wm8994_pm_ops = {
4495 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4496 };
4497
4498 static struct platform_driver wm8994_codec_driver = {
4499 .driver = {
4500 .name = "wm8994-codec",
4501 .owner = THIS_MODULE,
4502 .pm = &wm8994_pm_ops,
4503 },
4504 .probe = wm8994_probe,
4505 .remove = wm8994_remove,
4506 };
4507
4508 module_platform_driver(wm8994_codec_driver);
4509
4510 MODULE_DESCRIPTION("ASoC WM8994 driver");
4511 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4512 MODULE_LICENSE("GPL");
4513 MODULE_ALIAS("platform:wm8994-codec");
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