2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
49 static int wm8994_drc_base
[] = {
55 static int wm8994_retune_mobile_base
[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1
,
57 WM8994_AIF1_DAC2_EQ_GAINS_1
,
58 WM8994_AIF2_EQ_GAINS_1
,
61 static void wm8958_default_micdet(u16 status
, void *data
);
63 static const struct wm8958_micd_rate micdet_rates
[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
70 static const struct wm8958_micd_rate jackdet_rates
[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
77 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
79 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
80 int best
, i
, sysclk
, val
;
82 const struct wm8958_micd_rate
*rates
;
85 if (wm8994
->jack_cb
!= wm8958_default_micdet
)
88 idle
= !wm8994
->jack_mic
;
90 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
91 if (sysclk
& WM8994_SYSCLK_SRC
)
92 sysclk
= wm8994
->aifclk
[1];
94 sysclk
= wm8994
->aifclk
[0];
96 if (wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) {
97 rates
= wm8994
->pdata
->micd_rates
;
98 num_rates
= wm8994
->pdata
->num_micd_rates
;
99 } else if (wm8994
->jackdet
) {
100 rates
= jackdet_rates
;
101 num_rates
= ARRAY_SIZE(jackdet_rates
);
103 rates
= micdet_rates
;
104 num_rates
= ARRAY_SIZE(micdet_rates
);
108 for (i
= 0; i
< num_rates
; i
++) {
109 if (rates
[i
].idle
!= idle
)
111 if (abs(rates
[i
].sysclk
- sysclk
) <
112 abs(rates
[best
].sysclk
- sysclk
))
114 else if (rates
[best
].idle
!= idle
)
118 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
121 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
122 WM8958_MICD_BIAS_STARTTIME_MASK
|
123 WM8958_MICD_RATE_MASK
, val
);
126 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
128 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
138 switch (wm8994
->sysclk
[aif
]) {
139 case WM8994_SYSCLK_MCLK1
:
140 rate
= wm8994
->mclk
[0];
143 case WM8994_SYSCLK_MCLK2
:
145 rate
= wm8994
->mclk
[1];
148 case WM8994_SYSCLK_FLL1
:
150 rate
= wm8994
->fll
[0].out
;
153 case WM8994_SYSCLK_FLL2
:
155 rate
= wm8994
->fll
[1].out
;
162 if (rate
>= 13500000) {
164 reg1
|= WM8994_AIF1CLK_DIV
;
166 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
170 wm8994
->aifclk
[aif
] = rate
;
172 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
173 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
179 static int configure_clock(struct snd_soc_codec
*codec
)
181 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec
, 0);
186 configure_aif_clock(codec
, 1);
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
194 /* If they're equal it doesn't matter which is used */
195 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
196 wm8958_micd_set_rate(codec
);
200 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
201 new = WM8994_SYSCLK_SRC
;
205 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
206 WM8994_SYSCLK_SRC
, new);
208 snd_soc_dapm_sync(&codec
->dapm
);
210 wm8958_micd_set_rate(codec
);
215 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
216 struct snd_soc_dapm_widget
*sink
)
218 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
221 /* Check what we're currently using for CLK_SYS */
222 if (reg
& WM8994_SYSCLK_SRC
)
227 return strcmp(source
->name
, clk
) == 0;
230 static const char *sidetone_hpf_text
[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
234 static const struct soc_enum sidetone_hpf
=
235 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
237 static const char *adc_hpf_text
[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
241 static const struct soc_enum aif1adc1_hpf
=
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
244 static const struct soc_enum aif1adc2_hpf
=
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
247 static const struct soc_enum aif2adc_hpf
=
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
250 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
264 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
265 struct snd_ctl_elem_value
*ucontrol
)
267 struct soc_mixer_control
*mc
=
268 (struct soc_mixer_control
*)kcontrol
->private_value
;
269 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
274 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
275 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
277 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
279 ret
= snd_soc_read(codec
, mc
->reg
);
285 return snd_soc_put_volsw(kcontrol
, ucontrol
);
288 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
290 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
291 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
292 int base
= wm8994_drc_base
[drc
];
293 int cfg
= wm8994
->drc_cfg
[drc
];
296 /* Save any enables; the configuration should clear them. */
297 save
= snd_soc_read(codec
, base
);
298 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
299 WM8994_AIF1ADC1R_DRC_ENA
;
301 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
302 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
303 pdata
->drc_cfgs
[cfg
].regs
[i
]);
305 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
306 WM8994_AIF1ADC1L_DRC_ENA
|
307 WM8994_AIF1ADC1R_DRC_ENA
, save
);
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name
)
313 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
315 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
317 if (strcmp(name
, "AIF2DRC Mode") == 0)
322 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
323 struct snd_ctl_elem_value
*ucontrol
)
325 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
326 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
327 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
328 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
329 int value
= ucontrol
->value
.integer
.value
[0];
334 if (value
>= pdata
->num_drc_cfgs
)
337 wm8994
->drc_cfg
[drc
] = value
;
339 wm8994_set_drc(codec
, drc
);
344 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
345 struct snd_ctl_elem_value
*ucontrol
)
347 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
348 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
349 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
351 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
356 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
358 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
359 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
360 int base
= wm8994_retune_mobile_base
[block
];
361 int iface
, best
, best_val
, save
, i
, cfg
;
363 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg
= wm8994
->retune_mobile_cfg
[block
];
383 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
384 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
385 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
386 abs(pdata
->retune_mobile_cfgs
[i
].rate
387 - wm8994
->dac_rates
[iface
]) < best_val
) {
389 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
390 - wm8994
->dac_rates
[iface
]);
394 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
396 pdata
->retune_mobile_cfgs
[best
].name
,
397 pdata
->retune_mobile_cfgs
[best
].rate
,
398 wm8994
->dac_rates
[iface
]);
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
403 save
= snd_soc_read(codec
, base
);
404 save
&= WM8994_AIF1DAC1_EQ_ENA
;
406 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
407 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
408 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
410 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name
)
416 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
418 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
420 if (strcmp(name
, "AIF2 EQ Mode") == 0)
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
426 struct snd_ctl_elem_value
*ucontrol
)
428 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
429 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
430 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
431 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
432 int value
= ucontrol
->value
.integer
.value
[0];
437 if (value
>= pdata
->num_retune_mobile_cfgs
)
440 wm8994
->retune_mobile_cfg
[block
] = value
;
442 wm8994_set_retune_mobile(codec
, block
);
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
448 struct snd_ctl_elem_value
*ucontrol
)
450 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
451 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
452 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
454 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
459 static const char *aif_chan_src_text
[] = {
463 static const struct soc_enum aif1adcl_src
=
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
466 static const struct soc_enum aif1adcr_src
=
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
469 static const struct soc_enum aif2adcl_src
=
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
472 static const struct soc_enum aif2adcr_src
=
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
475 static const struct soc_enum aif1dacl_src
=
476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
478 static const struct soc_enum aif1dacr_src
=
479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
481 static const struct soc_enum aif2dacl_src
=
482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
484 static const struct soc_enum aif2dacr_src
=
485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
487 static const char *osr_text
[] = {
488 "Low Power", "High Performance",
491 static const struct soc_enum dac_osr
=
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
494 static const struct soc_enum adc_osr
=
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
497 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
500 1, 119, 0, digital_tlv
),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
503 1, 119, 0, digital_tlv
),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
505 WM8994_AIF2_ADC_RIGHT_VOLUME
,
506 1, 119, 0, digital_tlv
),
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
523 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
564 SOC_ENUM("ADC OSR", adc_osr
),
565 SOC_ENUM("DAC OSR", dac_osr
),
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
568 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
570 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
573 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
575 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
578 6, 1, 1, wm_hubs_spkmix_tlv
),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
580 2, 1, 1, wm_hubs_spkmix_tlv
),
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
583 6, 1, 1, wm_hubs_spkmix_tlv
),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
585 2, 1, 1, wm_hubs_spkmix_tlv
),
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
588 10, 15, 0, wm8994_3d_tlv
),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
592 10, 15, 0, wm8994_3d_tlv
),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
596 10, 15, 0, wm8994_3d_tlv
),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
601 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
636 static const char *wm8958_ng_text
[] = {
637 "30ms", "125ms", "250ms", "500ms",
640 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
642 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
644 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
646 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
648 static const struct soc_enum wm8958_aif2dac_ng_hold
=
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
650 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
652 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
670 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
677 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
687 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
689 if (wm8994
->active_refcount
)
690 mode
= WM1811_JACKDET_MODE_AUDIO
;
692 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
693 WM1811_JACKDET_MODE_MASK
, mode
);
695 if (mode
== WM1811_JACKDET_MODE_MIC
)
699 static void active_reference(struct snd_soc_codec
*codec
)
701 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
703 mutex_lock(&wm8994
->accdet_lock
);
705 wm8994
->active_refcount
++;
707 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
708 wm8994
->active_refcount
);
710 if (wm8994
->active_refcount
== 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
713 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
714 WM1811_JACKDET_MODE_MASK
,
715 WM1811_JACKDET_MODE_AUDIO
);
720 mutex_unlock(&wm8994
->accdet_lock
);
723 static void active_dereference(struct snd_soc_codec
*codec
)
725 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
728 mutex_lock(&wm8994
->accdet_lock
);
730 wm8994
->active_refcount
--;
732 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
733 wm8994
->active_refcount
);
735 if (wm8994
->active_refcount
== 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
738 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
739 mode
= WM1811_JACKDET_MODE_MIC
;
741 mode
= WM1811_JACKDET_MODE_JACK
;
743 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
744 WM1811_JACKDET_MODE_MASK
,
749 mutex_unlock(&wm8994
->accdet_lock
);
752 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
753 struct snd_kcontrol
*kcontrol
, int event
)
755 struct snd_soc_codec
*codec
= w
->codec
;
758 case SND_SOC_DAPM_PRE_PMU
:
759 return configure_clock(codec
);
761 case SND_SOC_DAPM_POST_PMD
:
762 configure_clock(codec
);
769 static void vmid_reference(struct snd_soc_codec
*codec
)
771 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
773 pm_runtime_get_sync(codec
->dev
);
775 wm8994
->vmid_refcount
++;
777 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
778 wm8994
->vmid_refcount
);
780 if (wm8994
->vmid_refcount
== 1) {
781 /* Startup bias, VMID ramp & buffer */
782 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
783 WM8994_STARTUP_BIAS_ENA
|
784 WM8994_VMID_BUF_ENA
|
785 WM8994_VMID_RAMP_MASK
,
786 WM8994_STARTUP_BIAS_ENA
|
787 WM8994_VMID_BUF_ENA
|
788 (0x3 << WM8994_VMID_RAMP_SHIFT
));
790 /* Remove discharge for line out */
791 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
792 WM8994_LINEOUT1_DISCH
|
793 WM8994_LINEOUT2_DISCH
, 0);
795 /* Main bias enable, VMID=2x40k */
796 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
798 WM8994_VMID_SEL_MASK
,
799 WM8994_BIAS_ENA
| 0x2);
805 static void vmid_dereference(struct snd_soc_codec
*codec
)
807 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
809 wm8994
->vmid_refcount
--;
811 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
812 wm8994
->vmid_refcount
);
814 if (wm8994
->vmid_refcount
== 0) {
815 /* Switch over to startup biases */
816 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
818 WM8994_STARTUP_BIAS_ENA
|
819 WM8994_VMID_BUF_ENA
|
820 WM8994_VMID_RAMP_MASK
,
822 WM8994_STARTUP_BIAS_ENA
|
823 WM8994_VMID_BUF_ENA
|
824 (1 << WM8994_VMID_RAMP_SHIFT
));
826 /* Disable main biases */
827 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
829 WM8994_VMID_SEL_MASK
, 0);
832 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
833 WM8994_LINEOUT1_DISCH
|
834 WM8994_LINEOUT2_DISCH
,
835 WM8994_LINEOUT1_DISCH
|
836 WM8994_LINEOUT2_DISCH
);
840 /* Switch off startup biases */
841 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
843 WM8994_STARTUP_BIAS_ENA
|
844 WM8994_VMID_BUF_ENA
|
845 WM8994_VMID_RAMP_MASK
, 0);
848 pm_runtime_put(codec
->dev
);
851 static int vmid_event(struct snd_soc_dapm_widget
*w
,
852 struct snd_kcontrol
*kcontrol
, int event
)
854 struct snd_soc_codec
*codec
= w
->codec
;
857 case SND_SOC_DAPM_PRE_PMU
:
858 vmid_reference(codec
);
861 case SND_SOC_DAPM_POST_PMD
:
862 vmid_dereference(codec
);
869 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
871 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
873 int source
= 0; /* GCC flow analysis can't track enable */
876 /* Only support direct DAC->headphone paths */
877 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
878 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
879 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
883 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
884 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
885 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
889 /* We also need the same setting for L/R and only one path */
890 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
892 case WM8994_AIF2DACL_TO_DAC1L
:
893 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
894 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
896 case WM8994_AIF1DAC2L_TO_DAC1L
:
897 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
898 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
900 case WM8994_AIF1DAC1L_TO_DAC1L
:
901 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
902 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
905 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
910 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
912 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
917 dev_dbg(codec
->dev
, "Class W enabled\n");
918 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
920 WM8994_CP_DYN_SRC_SEL_MASK
,
921 source
| WM8994_CP_DYN_PWR
);
922 wm8994
->hubs
.class_w
= true;
925 dev_dbg(codec
->dev
, "Class W disabled\n");
926 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
927 WM8994_CP_DYN_PWR
, 0);
928 wm8994
->hubs
.class_w
= false;
932 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
933 struct snd_kcontrol
*kcontrol
, int event
)
935 struct snd_soc_codec
*codec
= w
->codec
;
936 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
939 case SND_SOC_DAPM_PRE_PMU
:
940 if (wm8994
->aif1clk_enable
) {
941 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
942 WM8994_AIF1CLK_ENA_MASK
,
944 wm8994
->aif1clk_enable
= 0;
946 if (wm8994
->aif2clk_enable
) {
947 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
948 WM8994_AIF2CLK_ENA_MASK
,
950 wm8994
->aif2clk_enable
= 0;
955 /* We may also have postponed startup of DSP, handle that. */
956 wm8958_aif_ev(w
, kcontrol
, event
);
961 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
962 struct snd_kcontrol
*kcontrol
, int event
)
964 struct snd_soc_codec
*codec
= w
->codec
;
965 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
968 case SND_SOC_DAPM_POST_PMD
:
969 if (wm8994
->aif1clk_disable
) {
970 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
971 WM8994_AIF1CLK_ENA_MASK
, 0);
972 wm8994
->aif1clk_disable
= 0;
974 if (wm8994
->aif2clk_disable
) {
975 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
976 WM8994_AIF2CLK_ENA_MASK
, 0);
977 wm8994
->aif2clk_disable
= 0;
985 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
986 struct snd_kcontrol
*kcontrol
, int event
)
988 struct snd_soc_codec
*codec
= w
->codec
;
989 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
992 case SND_SOC_DAPM_PRE_PMU
:
993 wm8994
->aif1clk_enable
= 1;
995 case SND_SOC_DAPM_POST_PMD
:
996 wm8994
->aif1clk_disable
= 1;
1003 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1004 struct snd_kcontrol
*kcontrol
, int event
)
1006 struct snd_soc_codec
*codec
= w
->codec
;
1007 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1010 case SND_SOC_DAPM_PRE_PMU
:
1011 wm8994
->aif2clk_enable
= 1;
1013 case SND_SOC_DAPM_POST_PMD
:
1014 wm8994
->aif2clk_disable
= 1;
1021 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1022 struct snd_kcontrol
*kcontrol
, int event
)
1024 late_enable_ev(w
, kcontrol
, event
);
1028 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1029 struct snd_kcontrol
*kcontrol
, int event
)
1031 late_enable_ev(w
, kcontrol
, event
);
1035 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1036 struct snd_kcontrol
*kcontrol
, int event
)
1038 struct snd_soc_codec
*codec
= w
->codec
;
1039 unsigned int mask
= 1 << w
->shift
;
1041 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1046 static const char *hp_mux_text
[] = {
1051 #define WM8994_HP_ENUM(xname, xenum) \
1052 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1053 .info = snd_soc_info_enum_double, \
1054 .get = snd_soc_dapm_get_enum_double, \
1055 .put = wm8994_put_hp_enum, \
1056 .private_value = (unsigned long)&xenum }
1058 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
1059 struct snd_ctl_elem_value
*ucontrol
)
1061 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1062 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1063 struct snd_soc_codec
*codec
= w
->codec
;
1066 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
1068 wm8994_update_class_w(codec
);
1073 static const struct soc_enum hpl_enum
=
1074 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
1076 static const struct snd_kcontrol_new hpl_mux
=
1077 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
1079 static const struct soc_enum hpr_enum
=
1080 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
1082 static const struct snd_kcontrol_new hpr_mux
=
1083 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
1085 static const char *adc_mux_text
[] = {
1090 static const struct soc_enum adc_enum
=
1091 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1093 static const struct snd_kcontrol_new adcl_mux
=
1094 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1096 static const struct snd_kcontrol_new adcr_mux
=
1097 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1099 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1100 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1101 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1102 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1103 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1104 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1107 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1108 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1109 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1110 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1111 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1112 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1115 /* Debugging; dump chip status after DAPM transitions */
1116 static int post_ev(struct snd_soc_dapm_widget
*w
,
1117 struct snd_kcontrol
*kcontrol
, int event
)
1119 struct snd_soc_codec
*codec
= w
->codec
;
1120 dev_dbg(codec
->dev
, "SRC status: %x\n",
1122 WM8994_RATE_STATUS
));
1126 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1127 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1129 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1133 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1134 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1136 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1140 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1141 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1143 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1147 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1148 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1150 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1154 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1155 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1157 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1159 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1161 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1163 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1167 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1168 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1170 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1172 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1174 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1176 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1180 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1181 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1182 .info = snd_soc_info_volsw, \
1183 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1184 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1186 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1187 struct snd_ctl_elem_value
*ucontrol
)
1189 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1190 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1191 struct snd_soc_codec
*codec
= w
->codec
;
1194 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1196 wm8994_update_class_w(codec
);
1201 static const struct snd_kcontrol_new dac1l_mix
[] = {
1202 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1204 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1206 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1208 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1210 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1214 static const struct snd_kcontrol_new dac1r_mix
[] = {
1215 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1217 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1219 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1221 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1223 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1227 static const char *sidetone_text
[] = {
1228 "ADC/DMIC1", "DMIC2",
1231 static const struct soc_enum sidetone1_enum
=
1232 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1234 static const struct snd_kcontrol_new sidetone1_mux
=
1235 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1237 static const struct soc_enum sidetone2_enum
=
1238 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1240 static const struct snd_kcontrol_new sidetone2_mux
=
1241 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1243 static const char *aif1dac_text
[] = {
1244 "AIF1DACDAT", "AIF3DACDAT",
1247 static const struct soc_enum aif1dac_enum
=
1248 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1250 static const struct snd_kcontrol_new aif1dac_mux
=
1251 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1253 static const char *aif2dac_text
[] = {
1254 "AIF2DACDAT", "AIF3DACDAT",
1257 static const struct soc_enum aif2dac_enum
=
1258 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1260 static const struct snd_kcontrol_new aif2dac_mux
=
1261 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1263 static const char *aif2adc_text
[] = {
1264 "AIF2ADCDAT", "AIF3DACDAT",
1267 static const struct soc_enum aif2adc_enum
=
1268 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1270 static const struct snd_kcontrol_new aif2adc_mux
=
1271 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1273 static const char *aif3adc_text
[] = {
1274 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1277 static const struct soc_enum wm8994_aif3adc_enum
=
1278 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1280 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1281 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1283 static const struct soc_enum wm8958_aif3adc_enum
=
1284 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1286 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1287 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1289 static const char *mono_pcm_out_text
[] = {
1290 "None", "AIF2ADCL", "AIF2ADCR",
1293 static const struct soc_enum mono_pcm_out_enum
=
1294 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1296 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1297 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1299 static const char *aif2dac_src_text
[] = {
1303 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1304 static const struct soc_enum aif2dacl_src_enum
=
1305 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1307 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1308 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1310 static const struct soc_enum aif2dacr_src_enum
=
1311 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1313 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1314 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1316 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1317 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_ev
,
1318 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1319 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_ev
,
1320 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1322 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1323 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1324 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1325 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1326 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1327 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1328 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1329 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1330 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1331 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1333 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1334 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1335 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1336 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1337 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1338 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1339 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
,
1340 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1341 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
,
1342 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1344 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1347 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1348 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
1349 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0),
1350 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1351 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1352 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1353 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1354 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1355 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1356 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1359 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1360 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1361 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1362 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1363 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1364 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1365 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1366 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1367 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1370 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1371 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1372 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1373 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1374 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1377 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1378 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1379 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1380 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1381 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1384 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1385 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1386 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1389 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1390 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1391 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1392 SND_SOC_DAPM_INPUT("Clock"),
1394 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1395 SND_SOC_DAPM_PRE_PMU
),
1396 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1397 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1399 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1400 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1402 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
1403 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
1404 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
1406 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1407 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
1408 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1409 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
1410 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1411 WM8994_POWER_MANAGEMENT_5
, 9, 0, wm8958_aif_ev
,
1412 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1413 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1414 WM8994_POWER_MANAGEMENT_5
, 8, 0, wm8958_aif_ev
,
1415 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1417 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1418 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
1419 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1420 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
1421 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1422 WM8994_POWER_MANAGEMENT_5
, 11, 0, wm8958_aif_ev
,
1423 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1424 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1425 WM8994_POWER_MANAGEMENT_5
, 10, 0, wm8958_aif_ev
,
1426 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1428 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1429 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1430 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1431 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1433 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1434 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1435 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1436 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1438 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1439 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1440 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1441 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1443 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1444 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1446 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1447 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1448 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1449 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1451 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1452 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1453 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1454 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1455 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1456 WM8994_POWER_MANAGEMENT_5
, 13, 0, wm8958_aif_ev
,
1457 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1458 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1459 WM8994_POWER_MANAGEMENT_5
, 12, 0, wm8958_aif_ev
,
1460 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1462 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1463 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1464 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
1465 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1467 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1468 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1469 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1471 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1472 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1474 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1476 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1477 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1478 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1479 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1481 /* Power is done with the muxes since the ADC power also controls the
1482 * downsampling chain, the chip will automatically manage the analogue
1483 * specific portions.
1485 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1486 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1488 SND_SOC_DAPM_POST("Debug log", post_ev
),
1491 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1492 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1495 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1496 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1497 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1498 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1499 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1502 static const struct snd_soc_dapm_route intercon
[] = {
1503 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1504 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1506 { "DSP1CLK", NULL
, "CLK_SYS" },
1507 { "DSP2CLK", NULL
, "CLK_SYS" },
1508 { "DSPINTCLK", NULL
, "CLK_SYS" },
1510 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1511 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1512 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1513 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1514 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1516 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1517 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1518 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1519 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1520 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1522 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1523 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1524 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1525 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1526 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1528 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1529 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1530 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1531 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1532 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1534 { "AIF2ADCL", NULL
, "AIF2CLK" },
1535 { "AIF2ADCL", NULL
, "DSP2CLK" },
1536 { "AIF2ADCR", NULL
, "AIF2CLK" },
1537 { "AIF2ADCR", NULL
, "DSP2CLK" },
1538 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1540 { "AIF2DACL", NULL
, "AIF2CLK" },
1541 { "AIF2DACL", NULL
, "DSP2CLK" },
1542 { "AIF2DACR", NULL
, "AIF2CLK" },
1543 { "AIF2DACR", NULL
, "DSP2CLK" },
1544 { "AIF2DACR", NULL
, "DSPINTCLK" },
1546 { "DMIC1L", NULL
, "DMIC1DAT" },
1547 { "DMIC1L", NULL
, "CLK_SYS" },
1548 { "DMIC1R", NULL
, "DMIC1DAT" },
1549 { "DMIC1R", NULL
, "CLK_SYS" },
1550 { "DMIC2L", NULL
, "DMIC2DAT" },
1551 { "DMIC2L", NULL
, "CLK_SYS" },
1552 { "DMIC2R", NULL
, "DMIC2DAT" },
1553 { "DMIC2R", NULL
, "CLK_SYS" },
1555 { "ADCL", NULL
, "AIF1CLK" },
1556 { "ADCL", NULL
, "DSP1CLK" },
1557 { "ADCL", NULL
, "DSPINTCLK" },
1559 { "ADCR", NULL
, "AIF1CLK" },
1560 { "ADCR", NULL
, "DSP1CLK" },
1561 { "ADCR", NULL
, "DSPINTCLK" },
1563 { "ADCL Mux", "ADC", "ADCL" },
1564 { "ADCL Mux", "DMIC", "DMIC1L" },
1565 { "ADCR Mux", "ADC", "ADCR" },
1566 { "ADCR Mux", "DMIC", "DMIC1R" },
1568 { "DAC1L", NULL
, "AIF1CLK" },
1569 { "DAC1L", NULL
, "DSP1CLK" },
1570 { "DAC1L", NULL
, "DSPINTCLK" },
1572 { "DAC1R", NULL
, "AIF1CLK" },
1573 { "DAC1R", NULL
, "DSP1CLK" },
1574 { "DAC1R", NULL
, "DSPINTCLK" },
1576 { "DAC2L", NULL
, "AIF2CLK" },
1577 { "DAC2L", NULL
, "DSP2CLK" },
1578 { "DAC2L", NULL
, "DSPINTCLK" },
1580 { "DAC2R", NULL
, "AIF2DACR" },
1581 { "DAC2R", NULL
, "AIF2CLK" },
1582 { "DAC2R", NULL
, "DSP2CLK" },
1583 { "DAC2R", NULL
, "DSPINTCLK" },
1585 { "TOCLK", NULL
, "CLK_SYS" },
1588 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1589 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1590 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1592 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1593 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1594 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1596 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1597 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1598 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1600 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1601 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1602 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1604 /* Pin level routing for AIF3 */
1605 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1606 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1607 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1608 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1610 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1611 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1612 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1613 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1614 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1615 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1616 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1619 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1620 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1621 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1622 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1623 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1625 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1626 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1627 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1628 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1629 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1631 /* DAC2/AIF2 outputs */
1632 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1633 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1634 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1635 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1636 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1637 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1639 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1640 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1641 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1642 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1643 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1644 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1646 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1647 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1648 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1649 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1651 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1654 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1655 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1656 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1657 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1658 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1659 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1660 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1661 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1664 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1665 { "Left Sidetone", "DMIC2", "DMIC2L" },
1666 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1667 { "Right Sidetone", "DMIC2", "DMIC2R" },
1670 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1671 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1673 { "SPKL", "DAC1 Switch", "DAC1L" },
1674 { "SPKL", "DAC2 Switch", "DAC2L" },
1676 { "SPKR", "DAC1 Switch", "DAC1R" },
1677 { "SPKR", "DAC2 Switch", "DAC2R" },
1679 { "Left Headphone Mux", "DAC", "DAC1L" },
1680 { "Right Headphone Mux", "DAC", "DAC1R" },
1683 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1684 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1685 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1686 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1687 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1688 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1689 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1690 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1691 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1694 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1695 { "DAC1L", NULL
, "DAC1L Mixer" },
1696 { "DAC1R", NULL
, "DAC1R Mixer" },
1697 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1698 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1701 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1702 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1703 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1704 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1705 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1706 { "MICBIAS1", NULL
, "CLK_SYS" },
1707 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1708 { "MICBIAS2", NULL
, "CLK_SYS" },
1709 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1712 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1713 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1714 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1715 { "MICBIAS1", NULL
, "VMID" },
1716 { "MICBIAS2", NULL
, "VMID" },
1719 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1720 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1721 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1723 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1724 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1725 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1726 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1728 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1729 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1731 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1734 /* The size in bits of the FLL divide multiplied by 10
1735 * to allow rounding later */
1736 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1746 static int wm8994_get_fll_config(struct fll_div
*fll
,
1747 int freq_in
, int freq_out
)
1750 unsigned int K
, Ndiv
, Nmod
;
1752 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1754 /* Scale the input frequency down to <= 13.5MHz */
1755 fll
->clk_ref_div
= 0;
1756 while (freq_in
> 13500000) {
1760 if (fll
->clk_ref_div
> 3)
1763 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1765 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1767 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1769 if (fll
->outdiv
> 63)
1772 freq_out
*= fll
->outdiv
+ 1;
1773 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1775 if (freq_in
> 1000000) {
1776 fll
->fll_fratio
= 0;
1777 } else if (freq_in
> 256000) {
1778 fll
->fll_fratio
= 1;
1780 } else if (freq_in
> 128000) {
1781 fll
->fll_fratio
= 2;
1783 } else if (freq_in
> 64000) {
1784 fll
->fll_fratio
= 3;
1787 fll
->fll_fratio
= 4;
1790 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1792 /* Now, calculate N.K */
1793 Ndiv
= freq_out
/ freq_in
;
1796 Nmod
= freq_out
% freq_in
;
1797 pr_debug("Nmod=%d\n", Nmod
);
1799 /* Calculate fractional part - scale up so we can round. */
1800 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1802 do_div(Kpart
, freq_in
);
1804 K
= Kpart
& 0xFFFFFFFF;
1809 /* Move down to proper range now rounding is done */
1812 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1817 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1818 unsigned int freq_in
, unsigned int freq_out
)
1820 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1821 struct wm8994
*control
= wm8994
->wm8994
;
1822 int reg_offset
, ret
;
1824 u16 reg
, aif1
, aif2
;
1825 unsigned long timeout
;
1828 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1829 & WM8994_AIF1CLK_ENA
;
1831 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1832 & WM8994_AIF2CLK_ENA
;
1847 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
1848 was_enabled
= reg
& WM8994_FLL1_ENA
;
1852 /* Allow no source specification when stopping */
1855 src
= wm8994
->fll
[id
].src
;
1857 case WM8994_FLL_SRC_MCLK1
:
1858 case WM8994_FLL_SRC_MCLK2
:
1859 case WM8994_FLL_SRC_LRCLK
:
1860 case WM8994_FLL_SRC_BCLK
:
1866 /* Are we changing anything? */
1867 if (wm8994
->fll
[id
].src
== src
&&
1868 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1871 /* If we're stopping the FLL redo the old config - no
1872 * registers will actually be written but we avoid GCC flow
1873 * analysis bugs spewing warnings.
1876 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1878 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1879 wm8994
->fll
[id
].out
);
1883 /* Gate the AIF clocks while we reclock */
1884 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1885 WM8994_AIF1CLK_ENA
, 0);
1886 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1887 WM8994_AIF2CLK_ENA
, 0);
1889 /* We always need to disable the FLL while reconfiguring */
1890 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1891 WM8994_FLL1_ENA
, 0);
1893 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1894 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1895 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1896 WM8994_FLL1_OUTDIV_MASK
|
1897 WM8994_FLL1_FRATIO_MASK
, reg
);
1899 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1901 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1903 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1905 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1906 WM8994_FLL1_REFCLK_DIV_MASK
|
1907 WM8994_FLL1_REFCLK_SRC_MASK
,
1908 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
1911 /* Clear any pending completion from a previous failure */
1912 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
1914 /* Enable (with fractional mode if required) */
1916 /* Enable VMID if we need it */
1918 active_reference(codec
);
1920 switch (control
->type
) {
1922 vmid_reference(codec
);
1925 if (wm8994
->revision
< 1)
1926 vmid_reference(codec
);
1934 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
1936 reg
= WM8994_FLL1_ENA
;
1937 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1938 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
1941 if (wm8994
->fll_locked_irq
) {
1942 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
1943 msecs_to_jiffies(10));
1945 dev_warn(codec
->dev
,
1946 "Timed out waiting for FLL lock\n");
1952 switch (control
->type
) {
1954 vmid_dereference(codec
);
1957 if (wm8994
->revision
< 1)
1958 vmid_dereference(codec
);
1964 active_dereference(codec
);
1968 wm8994
->fll
[id
].in
= freq_in
;
1969 wm8994
->fll
[id
].out
= freq_out
;
1970 wm8994
->fll
[id
].src
= src
;
1972 /* Enable any gated AIF clocks */
1973 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1974 WM8994_AIF1CLK_ENA
, aif1
);
1975 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1976 WM8994_AIF2CLK_ENA
, aif2
);
1978 configure_clock(codec
);
1983 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
1985 struct completion
*completion
= data
;
1987 complete(completion
);
1992 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1994 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
1995 unsigned int freq_in
, unsigned int freq_out
)
1997 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2000 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2001 int clk_id
, unsigned int freq
, int dir
)
2003 struct snd_soc_codec
*codec
= dai
->codec
;
2004 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2013 /* AIF3 shares clocking with AIF1/2 */
2018 case WM8994_SYSCLK_MCLK1
:
2019 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2020 wm8994
->mclk
[0] = freq
;
2021 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2025 case WM8994_SYSCLK_MCLK2
:
2026 /* TODO: Set GPIO AF */
2027 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2028 wm8994
->mclk
[1] = freq
;
2029 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2033 case WM8994_SYSCLK_FLL1
:
2034 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2035 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2038 case WM8994_SYSCLK_FLL2
:
2039 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2040 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2043 case WM8994_SYSCLK_OPCLK
:
2044 /* Special case - a division (times 10) is given and
2045 * no effect on main clocking.
2048 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2049 if (opclk_divs
[i
] == freq
)
2051 if (i
== ARRAY_SIZE(opclk_divs
))
2053 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2054 WM8994_OPCLK_DIV_MASK
, i
);
2055 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2056 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2058 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2059 WM8994_OPCLK_ENA
, 0);
2066 configure_clock(codec
);
2071 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2072 enum snd_soc_bias_level level
)
2074 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2075 struct wm8994
*control
= wm8994
->wm8994
;
2078 case SND_SOC_BIAS_ON
:
2081 case SND_SOC_BIAS_PREPARE
:
2082 /* MICBIAS into regulating mode */
2083 switch (control
->type
) {
2086 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2087 WM8958_MICB1_MODE
, 0);
2088 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2089 WM8958_MICB2_MODE
, 0);
2095 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2096 active_reference(codec
);
2099 case SND_SOC_BIAS_STANDBY
:
2100 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2101 switch (control
->type
) {
2103 if (wm8994
->revision
< 4) {
2104 /* Tweak DC servo and DSP
2105 * configuration for improved
2107 snd_soc_write(codec
, 0x102, 0x3);
2108 snd_soc_write(codec
, 0x56, 0x3);
2109 snd_soc_write(codec
, 0x817, 0);
2110 snd_soc_write(codec
, 0x102, 0);
2115 if (wm8994
->revision
== 0) {
2116 /* Optimise performance for rev A */
2117 snd_soc_write(codec
, 0x102, 0x3);
2118 snd_soc_write(codec
, 0xcb, 0x81);
2119 snd_soc_write(codec
, 0x817, 0);
2120 snd_soc_write(codec
, 0x102, 0);
2122 snd_soc_update_bits(codec
,
2123 WM8958_CHARGE_PUMP_2
,
2130 if (wm8994
->revision
< 2) {
2131 snd_soc_write(codec
, 0x102, 0x3);
2132 snd_soc_write(codec
, 0x5d, 0x7e);
2133 snd_soc_write(codec
, 0x5e, 0x0);
2134 snd_soc_write(codec
, 0x102, 0x0);
2139 /* Discharge LINEOUT1 & 2 */
2140 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2141 WM8994_LINEOUT1_DISCH
|
2142 WM8994_LINEOUT2_DISCH
,
2143 WM8994_LINEOUT1_DISCH
|
2144 WM8994_LINEOUT2_DISCH
);
2147 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2148 active_dereference(codec
);
2150 /* MICBIAS into bypass mode on newer devices */
2151 switch (control
->type
) {
2154 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2157 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2166 case SND_SOC_BIAS_OFF
:
2167 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2168 wm8994
->cur_fw
= NULL
;
2171 codec
->dapm
.bias_level
= level
;
2176 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2178 struct snd_soc_codec
*codec
= dai
->codec
;
2179 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2180 struct wm8994
*control
= wm8994
->wm8994
;
2188 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2189 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2192 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2193 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2199 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2200 case SND_SOC_DAIFMT_CBS_CFS
:
2202 case SND_SOC_DAIFMT_CBM_CFM
:
2203 ms
= WM8994_AIF1_MSTR
;
2209 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2210 case SND_SOC_DAIFMT_DSP_B
:
2211 aif1
|= WM8994_AIF1_LRCLK_INV
;
2212 case SND_SOC_DAIFMT_DSP_A
:
2215 case SND_SOC_DAIFMT_I2S
:
2218 case SND_SOC_DAIFMT_RIGHT_J
:
2220 case SND_SOC_DAIFMT_LEFT_J
:
2227 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2228 case SND_SOC_DAIFMT_DSP_A
:
2229 case SND_SOC_DAIFMT_DSP_B
:
2230 /* frame inversion not valid for DSP modes */
2231 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2232 case SND_SOC_DAIFMT_NB_NF
:
2234 case SND_SOC_DAIFMT_IB_NF
:
2235 aif1
|= WM8994_AIF1_BCLK_INV
;
2242 case SND_SOC_DAIFMT_I2S
:
2243 case SND_SOC_DAIFMT_RIGHT_J
:
2244 case SND_SOC_DAIFMT_LEFT_J
:
2245 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2246 case SND_SOC_DAIFMT_NB_NF
:
2248 case SND_SOC_DAIFMT_IB_IF
:
2249 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2251 case SND_SOC_DAIFMT_IB_NF
:
2252 aif1
|= WM8994_AIF1_BCLK_INV
;
2254 case SND_SOC_DAIFMT_NB_IF
:
2255 aif1
|= WM8994_AIF1_LRCLK_INV
;
2265 /* The AIF2 format configuration needs to be mirrored to AIF3
2266 * on WM8958 if it's in use so just do it all the time. */
2267 switch (control
->type
) {
2271 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2272 WM8994_AIF1_LRCLK_INV
|
2273 WM8958_AIF3_FMT_MASK
, aif1
);
2280 snd_soc_update_bits(codec
, aif1_reg
,
2281 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2282 WM8994_AIF1_FMT_MASK
,
2284 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2306 static int fs_ratios
[] = {
2307 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2310 static int bclk_divs
[] = {
2311 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2312 640, 880, 960, 1280, 1760, 1920
2315 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2316 struct snd_pcm_hw_params
*params
,
2317 struct snd_soc_dai
*dai
)
2319 struct snd_soc_codec
*codec
= dai
->codec
;
2320 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2331 int id
= dai
->id
- 1;
2333 int i
, cur_val
, best_val
, bclk_rate
, best
;
2337 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2338 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2339 bclk_reg
= WM8994_AIF1_BCLK
;
2340 rate_reg
= WM8994_AIF1_RATE
;
2341 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2342 wm8994
->lrclk_shared
[0]) {
2343 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2345 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2346 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2350 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2351 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2352 bclk_reg
= WM8994_AIF2_BCLK
;
2353 rate_reg
= WM8994_AIF2_RATE
;
2354 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2355 wm8994
->lrclk_shared
[1]) {
2356 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2358 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2359 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2366 bclk_rate
= params_rate(params
) * 2;
2367 switch (params_format(params
)) {
2368 case SNDRV_PCM_FORMAT_S16_LE
:
2371 case SNDRV_PCM_FORMAT_S20_3LE
:
2375 case SNDRV_PCM_FORMAT_S24_LE
:
2379 case SNDRV_PCM_FORMAT_S32_LE
:
2387 /* Try to find an appropriate sample rate; look for an exact match. */
2388 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2389 if (srs
[i
].rate
== params_rate(params
))
2391 if (i
== ARRAY_SIZE(srs
))
2393 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2395 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2396 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2397 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2399 if (params_channels(params
) == 1 &&
2400 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2401 aif2
|= WM8994_AIF1_MONO
;
2403 if (wm8994
->aifclk
[id
] == 0) {
2404 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2408 /* AIFCLK/fs ratio; look for a close match in either direction */
2410 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2411 - wm8994
->aifclk
[id
]);
2412 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2413 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2414 - wm8994
->aifclk
[id
]);
2415 if (cur_val
>= best_val
)
2420 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2421 dai
->id
, fs_ratios
[best
]);
2424 /* We may not get quite the right frequency if using
2425 * approximate clocks so look for the closest match that is
2426 * higher than the target (we need to ensure that there enough
2427 * BCLKs to clock out the samples).
2430 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2431 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2432 if (cur_val
< 0) /* BCLK table is sorted */
2436 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2437 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2438 bclk_divs
[best
], bclk_rate
);
2439 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2441 lrclk
= bclk_rate
/ params_rate(params
);
2443 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2447 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2448 lrclk
, bclk_rate
/ lrclk
);
2450 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2451 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2452 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2453 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2455 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2456 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2458 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2461 wm8994
->dac_rates
[0] = params_rate(params
);
2462 wm8994_set_retune_mobile(codec
, 0);
2463 wm8994_set_retune_mobile(codec
, 1);
2466 wm8994
->dac_rates
[1] = params_rate(params
);
2467 wm8994_set_retune_mobile(codec
, 2);
2475 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2476 struct snd_pcm_hw_params
*params
,
2477 struct snd_soc_dai
*dai
)
2479 struct snd_soc_codec
*codec
= dai
->codec
;
2480 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2481 struct wm8994
*control
= wm8994
->wm8994
;
2487 switch (control
->type
) {
2490 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2499 switch (params_format(params
)) {
2500 case SNDRV_PCM_FORMAT_S16_LE
:
2502 case SNDRV_PCM_FORMAT_S20_3LE
:
2505 case SNDRV_PCM_FORMAT_S24_LE
:
2508 case SNDRV_PCM_FORMAT_S32_LE
:
2515 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2518 static void wm8994_aif_shutdown(struct snd_pcm_substream
*substream
,
2519 struct snd_soc_dai
*dai
)
2521 struct snd_soc_codec
*codec
= dai
->codec
;
2526 rate_reg
= WM8994_AIF1_RATE
;
2529 rate_reg
= WM8994_AIF2_RATE
;
2535 /* If the DAI is idle then configure the divider tree for the
2536 * lowest output rate to save a little power if the clock is
2537 * still active (eg, because it is system clock).
2539 if (rate_reg
&& !dai
->playback_active
&& !dai
->capture_active
)
2540 snd_soc_update_bits(codec
, rate_reg
,
2541 WM8994_AIF1_SR_MASK
|
2542 WM8994_AIF1CLK_RATE_MASK
, 0x9);
2545 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2547 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2551 switch (codec_dai
->id
) {
2553 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2556 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2563 reg
= WM8994_AIF1DAC1_MUTE
;
2567 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2572 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2574 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2577 switch (codec_dai
->id
) {
2579 reg
= WM8994_AIF1_MASTER_SLAVE
;
2580 mask
= WM8994_AIF1_TRI
;
2583 reg
= WM8994_AIF2_MASTER_SLAVE
;
2584 mask
= WM8994_AIF2_TRI
;
2587 reg
= WM8994_POWER_MANAGEMENT_6
;
2588 mask
= WM8994_AIF3_TRI
;
2599 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2602 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2604 struct snd_soc_codec
*codec
= dai
->codec
;
2606 /* Disable the pulls on the AIF if we're using it to save power. */
2607 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2608 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2609 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2610 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2611 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2612 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2617 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2619 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2620 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2622 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2623 .set_sysclk
= wm8994_set_dai_sysclk
,
2624 .set_fmt
= wm8994_set_dai_fmt
,
2625 .hw_params
= wm8994_hw_params
,
2626 .shutdown
= wm8994_aif_shutdown
,
2627 .digital_mute
= wm8994_aif_mute
,
2628 .set_pll
= wm8994_set_fll
,
2629 .set_tristate
= wm8994_set_tristate
,
2632 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2633 .set_sysclk
= wm8994_set_dai_sysclk
,
2634 .set_fmt
= wm8994_set_dai_fmt
,
2635 .hw_params
= wm8994_hw_params
,
2636 .shutdown
= wm8994_aif_shutdown
,
2637 .digital_mute
= wm8994_aif_mute
,
2638 .set_pll
= wm8994_set_fll
,
2639 .set_tristate
= wm8994_set_tristate
,
2642 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2643 .hw_params
= wm8994_aif3_hw_params
,
2644 .set_tristate
= wm8994_set_tristate
,
2647 static struct snd_soc_dai_driver wm8994_dai
[] = {
2649 .name
= "wm8994-aif1",
2652 .stream_name
= "AIF1 Playback",
2655 .rates
= WM8994_RATES
,
2656 .formats
= WM8994_FORMATS
,
2659 .stream_name
= "AIF1 Capture",
2662 .rates
= WM8994_RATES
,
2663 .formats
= WM8994_FORMATS
,
2665 .ops
= &wm8994_aif1_dai_ops
,
2668 .name
= "wm8994-aif2",
2671 .stream_name
= "AIF2 Playback",
2674 .rates
= WM8994_RATES
,
2675 .formats
= WM8994_FORMATS
,
2678 .stream_name
= "AIF2 Capture",
2681 .rates
= WM8994_RATES
,
2682 .formats
= WM8994_FORMATS
,
2684 .probe
= wm8994_aif2_probe
,
2685 .ops
= &wm8994_aif2_dai_ops
,
2688 .name
= "wm8994-aif3",
2691 .stream_name
= "AIF3 Playback",
2694 .rates
= WM8994_RATES
,
2695 .formats
= WM8994_FORMATS
,
2698 .stream_name
= "AIF3 Capture",
2701 .rates
= WM8994_RATES
,
2702 .formats
= WM8994_FORMATS
,
2704 .ops
= &wm8994_aif3_dai_ops
,
2709 static int wm8994_suspend(struct snd_soc_codec
*codec
)
2711 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2712 struct wm8994
*control
= wm8994
->wm8994
;
2715 switch (control
->type
) {
2717 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, 0);
2720 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2721 WM1811_JACKDET_MODE_MASK
, 0);
2724 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2725 WM8958_MICD_ENA
, 0);
2729 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2730 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2731 sizeof(struct wm8994_fll_config
));
2732 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2734 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2738 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2743 static int wm8994_resume(struct snd_soc_codec
*codec
)
2745 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2746 struct wm8994
*control
= wm8994
->wm8994
;
2748 unsigned int val
, mask
;
2750 if (wm8994
->revision
< 4) {
2751 /* force a HW read */
2752 ret
= regmap_read(control
->regmap
,
2753 WM8994_POWER_MANAGEMENT_5
, &val
);
2755 /* modify the cache only */
2756 codec
->cache_only
= 1;
2757 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
2758 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
2760 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
2762 codec
->cache_only
= 0;
2765 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2767 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2768 if (!wm8994
->fll_suspend
[i
].out
)
2771 ret
= _wm8994_set_fll(codec
, i
+ 1,
2772 wm8994
->fll_suspend
[i
].src
,
2773 wm8994
->fll_suspend
[i
].in
,
2774 wm8994
->fll_suspend
[i
].out
);
2776 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2780 switch (control
->type
) {
2782 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2783 snd_soc_update_bits(codec
, WM8994_MICBIAS
,
2784 WM8994_MICD_ENA
, WM8994_MICD_ENA
);
2787 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
2788 /* Restart from idle */
2789 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2790 WM1811_JACKDET_MODE_MASK
,
2791 WM1811_JACKDET_MODE_JACK
);
2795 if (wm8994
->jack_cb
)
2796 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2797 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
2804 #define wm8994_suspend NULL
2805 #define wm8994_resume NULL
2808 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2810 struct snd_soc_codec
*codec
= wm8994
->codec
;
2811 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2812 struct snd_kcontrol_new controls
[] = {
2813 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2814 wm8994
->retune_mobile_enum
,
2815 wm8994_get_retune_mobile_enum
,
2816 wm8994_put_retune_mobile_enum
),
2817 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2818 wm8994
->retune_mobile_enum
,
2819 wm8994_get_retune_mobile_enum
,
2820 wm8994_put_retune_mobile_enum
),
2821 SOC_ENUM_EXT("AIF2 EQ Mode",
2822 wm8994
->retune_mobile_enum
,
2823 wm8994_get_retune_mobile_enum
,
2824 wm8994_put_retune_mobile_enum
),
2829 /* We need an array of texts for the enum API but the number
2830 * of texts is likely to be less than the number of
2831 * configurations due to the sample rate dependency of the
2832 * configurations. */
2833 wm8994
->num_retune_mobile_texts
= 0;
2834 wm8994
->retune_mobile_texts
= NULL
;
2835 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2836 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2837 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2838 wm8994
->retune_mobile_texts
[j
]) == 0)
2842 if (j
!= wm8994
->num_retune_mobile_texts
)
2845 /* Expand the array... */
2846 t
= krealloc(wm8994
->retune_mobile_texts
,
2848 (wm8994
->num_retune_mobile_texts
+ 1),
2853 /* ...store the new entry... */
2854 t
[wm8994
->num_retune_mobile_texts
] =
2855 pdata
->retune_mobile_cfgs
[i
].name
;
2857 /* ...and remember the new version. */
2858 wm8994
->num_retune_mobile_texts
++;
2859 wm8994
->retune_mobile_texts
= t
;
2862 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2863 wm8994
->num_retune_mobile_texts
);
2865 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2866 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2868 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2869 ARRAY_SIZE(controls
));
2871 dev_err(wm8994
->codec
->dev
,
2872 "Failed to add ReTune Mobile controls: %d\n", ret
);
2875 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2877 struct snd_soc_codec
*codec
= wm8994
->codec
;
2878 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2884 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2885 pdata
->lineout2_diff
,
2890 pdata
->micbias1_lvl
,
2891 pdata
->micbias2_lvl
);
2893 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2895 if (pdata
->num_drc_cfgs
) {
2896 struct snd_kcontrol_new controls
[] = {
2897 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2898 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2899 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
2900 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2901 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
2902 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2905 /* We need an array of texts for the enum API */
2906 wm8994
->drc_texts
= devm_kzalloc(wm8994
->codec
->dev
,
2907 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2908 if (!wm8994
->drc_texts
) {
2909 dev_err(wm8994
->codec
->dev
,
2910 "Failed to allocate %d DRC config texts\n",
2911 pdata
->num_drc_cfgs
);
2915 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2916 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2918 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2919 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
2921 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2922 ARRAY_SIZE(controls
));
2924 dev_err(wm8994
->codec
->dev
,
2925 "Failed to add DRC mode controls: %d\n", ret
);
2927 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
2928 wm8994_set_drc(codec
, i
);
2931 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2932 pdata
->num_retune_mobile_cfgs
);
2934 if (pdata
->num_retune_mobile_cfgs
)
2935 wm8994_handle_retune_mobile_pdata(wm8994
);
2937 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
2938 ARRAY_SIZE(wm8994_eq_controls
));
2940 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
2941 if (pdata
->micbias
[i
]) {
2942 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
2943 pdata
->micbias
[i
] & 0xffff);
2949 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2951 * @codec: WM8994 codec
2952 * @jack: jack to report detection events on
2953 * @micbias: microphone bias to detect on
2954 * @det: value to report for presence detection
2955 * @shrt: value to report for short detection
2957 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2958 * being used to bring out signals to the processor then only platform
2959 * data configuration is needed for WM8994 and processor GPIOs should
2960 * be configured using snd_soc_jack_add_gpios() instead.
2962 * Configuration of detection levels is available via the micbias1_lvl
2963 * and micbias2_lvl platform data members.
2965 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2966 int micbias
, int det
, int shrt
)
2968 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2969 struct wm8994_micdet
*micdet
;
2970 struct wm8994
*control
= wm8994
->wm8994
;
2973 if (control
->type
!= WM8994
)
2978 micdet
= &wm8994
->micdet
[0];
2981 micdet
= &wm8994
->micdet
[1];
2987 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
2988 micbias
, det
, shrt
);
2990 /* Store the configuration */
2991 micdet
->jack
= jack
;
2993 micdet
->shrt
= shrt
;
2995 /* If either of the jacks is set up then enable detection */
2996 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2997 reg
= WM8994_MICD_ENA
;
3001 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3005 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3007 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3009 struct wm8994_priv
*priv
= data
;
3010 struct snd_soc_codec
*codec
= priv
->codec
;
3014 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3015 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3018 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
3020 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
3025 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
3028 if (reg
& WM8994_MIC1_DET_STS
)
3029 report
|= priv
->micdet
[0].det
;
3030 if (reg
& WM8994_MIC1_SHRT_STS
)
3031 report
|= priv
->micdet
[0].shrt
;
3032 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3033 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
3036 if (reg
& WM8994_MIC2_DET_STS
)
3037 report
|= priv
->micdet
[1].det
;
3038 if (reg
& WM8994_MIC2_SHRT_STS
)
3039 report
|= priv
->micdet
[1].shrt
;
3040 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3041 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
3046 /* Default microphone detection handler for WM8958 - the user can
3047 * override this if they wish.
3049 static void wm8958_default_micdet(u16 status
, void *data
)
3051 struct snd_soc_codec
*codec
= data
;
3052 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3055 dev_dbg(codec
->dev
, "MICDET %x\n", status
);
3057 /* Either nothing present or just starting detection */
3058 if (!(status
& WM8958_MICD_STS
)) {
3059 if (!wm8994
->jackdet
) {
3060 /* If nothing present then clear our statuses */
3061 dev_dbg(codec
->dev
, "Detected open circuit\n");
3062 wm8994
->jack_mic
= false;
3063 wm8994
->mic_detecting
= true;
3065 wm8958_micd_set_rate(codec
);
3067 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3074 /* If the measurement is showing a high impedence we've got a
3077 if (wm8994
->mic_detecting
&& (status
& 0x600)) {
3078 dev_dbg(codec
->dev
, "Detected microphone\n");
3080 wm8994
->mic_detecting
= false;
3081 wm8994
->jack_mic
= true;
3083 wm8958_micd_set_rate(codec
);
3085 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3090 if (wm8994
->mic_detecting
&& status
& 0x4) {
3091 dev_dbg(codec
->dev
, "Detected headphone\n");
3092 wm8994
->mic_detecting
= false;
3094 wm8958_micd_set_rate(codec
);
3096 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3099 /* If we have jackdet that will detect removal */
3100 if (wm8994
->jackdet
) {
3101 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3102 WM8958_MICD_ENA
, 0);
3104 wm1811_jackdet_set_mode(codec
,
3105 WM1811_JACKDET_MODE_JACK
);
3109 /* Report short circuit as a button */
3110 if (wm8994
->jack_mic
) {
3113 report
|= SND_JACK_BTN_0
;
3116 report
|= SND_JACK_BTN_1
;
3119 report
|= SND_JACK_BTN_2
;
3122 report
|= SND_JACK_BTN_3
;
3125 report
|= SND_JACK_BTN_4
;
3128 report
|= SND_JACK_BTN_5
;
3130 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3135 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3137 struct wm8994_priv
*wm8994
= data
;
3138 struct snd_soc_codec
*codec
= wm8994
->codec
;
3141 mutex_lock(&wm8994
->accdet_lock
);
3143 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3145 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3146 mutex_unlock(&wm8994
->accdet_lock
);
3150 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3152 if (reg
& WM1811_JACKDET_LVL
) {
3153 dev_dbg(codec
->dev
, "Jack detected\n");
3155 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3156 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3159 * Start off measument of microphone impedence to find
3160 * out what's actually there.
3162 wm8994
->mic_detecting
= true;
3163 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3164 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3165 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3167 dev_dbg(codec
->dev
, "Jack not detected\n");
3169 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3170 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3173 wm8994
->mic_detecting
= false;
3174 wm8994
->jack_mic
= false;
3175 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3176 WM8958_MICD_ENA
, 0);
3177 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3180 mutex_unlock(&wm8994
->accdet_lock
);
3186 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3188 * @codec: WM8958 codec
3189 * @jack: jack to report detection events on
3191 * Enable microphone detection functionality for the WM8958. By
3192 * default simple detection which supports the detection of up to 6
3193 * buttons plus video and microphone functionality is supported.
3195 * The WM8958 has an advanced jack detection facility which is able to
3196 * support complex accessory detection, especially when used in
3197 * conjunction with external circuitry. In order to provide maximum
3198 * flexiblity a callback is provided which allows a completely custom
3199 * detection algorithm.
3201 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3202 wm8958_micdet_cb cb
, void *cb_data
)
3204 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3205 struct wm8994
*control
= wm8994
->wm8994
;
3208 switch (control
->type
) {
3218 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3219 cb
= wm8958_default_micdet
;
3223 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3225 wm8994
->micdet
[0].jack
= jack
;
3226 wm8994
->jack_cb
= cb
;
3227 wm8994
->jack_cb_data
= cb_data
;
3229 wm8994
->mic_detecting
= true;
3230 wm8994
->jack_mic
= false;
3232 wm8958_micd_set_rate(codec
);
3234 /* Detect microphones and short circuits by default */
3235 if (wm8994
->pdata
->micd_lvl_sel
)
3236 micd_lvl_sel
= wm8994
->pdata
->micd_lvl_sel
;
3238 micd_lvl_sel
= 0x41;
3240 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3241 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3242 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3244 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3245 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3247 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3250 * If we can use jack detection start off with that,
3251 * otherwise jump straight to microphone detection.
3253 if (wm8994
->jackdet
) {
3254 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3255 WM8994_LDO1_DISCH
, 0);
3256 wm1811_jackdet_set_mode(codec
,
3257 WM1811_JACKDET_MODE_JACK
);
3259 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3260 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3264 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3265 WM8958_MICD_ENA
, 0);
3266 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3271 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3273 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3275 struct wm8994_priv
*wm8994
= data
;
3276 struct snd_soc_codec
*codec
= wm8994
->codec
;
3279 mutex_lock(&wm8994
->accdet_lock
);
3282 * Jack detection may have detected a removal simulataneously
3283 * with an update of the MICDET status; if so it will have
3284 * stopped detection and we can ignore this interrupt.
3286 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
)) {
3287 mutex_unlock(&wm8994
->accdet_lock
);
3291 /* We may occasionally read a detection without an impedence
3292 * range being provided - if that happens loop again.
3296 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3298 mutex_unlock(&wm8994
->accdet_lock
);
3300 "Failed to read mic detect status: %d\n",
3305 if (!(reg
& WM8958_MICD_VALID
)) {
3306 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3310 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3317 dev_warn(codec
->dev
, "No impedence range reported for jack\n");
3319 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3320 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3323 if (wm8994
->jack_cb
)
3324 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3326 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3329 mutex_unlock(&wm8994
->accdet_lock
);
3334 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3336 struct snd_soc_codec
*codec
= data
;
3338 dev_err(codec
->dev
, "FIFO error\n");
3343 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3345 struct snd_soc_codec
*codec
= data
;
3347 dev_err(codec
->dev
, "Thermal warning\n");
3352 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3354 struct snd_soc_codec
*codec
= data
;
3356 dev_crit(codec
->dev
, "Thermal shutdown\n");
3361 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3363 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3364 struct wm8994_priv
*wm8994
;
3365 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3369 codec
->control_data
= control
->regmap
;
3371 wm8994
= devm_kzalloc(codec
->dev
, sizeof(struct wm8994_priv
),
3375 snd_soc_codec_set_drvdata(codec
, wm8994
);
3377 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3379 wm8994
->wm8994
= dev_get_drvdata(codec
->dev
->parent
);
3380 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
3381 wm8994
->codec
= codec
;
3383 mutex_init(&wm8994
->accdet_lock
);
3385 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3386 init_completion(&wm8994
->fll_locked
[i
]);
3388 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
3389 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
3390 else if (wm8994
->pdata
&& wm8994
->pdata
->irq_base
)
3391 wm8994
->micdet_irq
= wm8994
->pdata
->irq_base
+
3392 WM8994_IRQ_MIC1_DET
;
3394 pm_runtime_enable(codec
->dev
);
3395 pm_runtime_resume(codec
->dev
);
3397 /* Set revision-specific configuration */
3398 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3399 switch (control
->type
) {
3401 switch (wm8994
->revision
) {
3404 wm8994
->hubs
.dcs_codes_l
= -5;
3405 wm8994
->hubs
.dcs_codes_r
= -5;
3406 wm8994
->hubs
.hp_startup_mode
= 1;
3407 wm8994
->hubs
.dcs_readback_mode
= 1;
3408 wm8994
->hubs
.series_startup
= 1;
3411 wm8994
->hubs
.dcs_readback_mode
= 2;
3417 wm8994
->hubs
.dcs_readback_mode
= 1;
3421 wm8994
->hubs
.dcs_readback_mode
= 2;
3422 wm8994
->hubs
.no_series_update
= 1;
3424 switch (wm8994
->revision
) {
3429 wm8994
->hubs
.dcs_codes_l
= -9;
3430 wm8994
->hubs
.dcs_codes_r
= -5;
3436 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3437 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3444 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3445 wm8994_fifo_error
, "FIFO error", codec
);
3446 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3447 wm8994_temp_warn
, "Thermal warning", codec
);
3448 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3449 wm8994_temp_shut
, "Thermal shutdown", codec
);
3451 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3452 wm_hubs_dcs_done
, "DC servo done",
3455 wm8994
->hubs
.dcs_done_irq
= true;
3457 switch (control
->type
) {
3459 if (wm8994
->micdet_irq
) {
3460 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3462 IRQF_TRIGGER_RISING
,
3466 dev_warn(codec
->dev
,
3467 "Failed to request Mic1 detect IRQ: %d\n",
3471 ret
= wm8994_request_irq(wm8994
->wm8994
,
3472 WM8994_IRQ_MIC1_SHRT
,
3473 wm8994_mic_irq
, "Mic 1 short",
3476 dev_warn(codec
->dev
,
3477 "Failed to request Mic1 short IRQ: %d\n",
3480 ret
= wm8994_request_irq(wm8994
->wm8994
,
3481 WM8994_IRQ_MIC2_DET
,
3482 wm8994_mic_irq
, "Mic 2 detect",
3485 dev_warn(codec
->dev
,
3486 "Failed to request Mic2 detect IRQ: %d\n",
3489 ret
= wm8994_request_irq(wm8994
->wm8994
,
3490 WM8994_IRQ_MIC2_SHRT
,
3491 wm8994_mic_irq
, "Mic 2 short",
3494 dev_warn(codec
->dev
,
3495 "Failed to request Mic2 short IRQ: %d\n",
3501 if (wm8994
->micdet_irq
) {
3502 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3504 IRQF_TRIGGER_RISING
,
3508 dev_warn(codec
->dev
,
3509 "Failed to request Mic detect IRQ: %d\n",
3514 switch (control
->type
) {
3516 if (wm8994
->revision
> 1) {
3517 ret
= wm8994_request_irq(wm8994
->wm8994
,
3519 wm1811_jackdet_irq
, "JACKDET",
3522 wm8994
->jackdet
= true;
3529 wm8994
->fll_locked_irq
= true;
3530 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
3531 ret
= wm8994_request_irq(wm8994
->wm8994
,
3532 WM8994_IRQ_FLL1_LOCK
+ i
,
3533 wm8994_fll_locked_irq
, "FLL lock",
3534 &wm8994
->fll_locked
[i
]);
3536 wm8994
->fll_locked_irq
= false;
3539 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3540 * configured on init - if a system wants to do this dynamically
3541 * at runtime we can deal with that then.
3543 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
3545 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3548 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3549 wm8994
->lrclk_shared
[0] = 1;
3550 wm8994_dai
[0].symmetric_rates
= 1;
3552 wm8994
->lrclk_shared
[0] = 0;
3555 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
3557 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3560 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3561 wm8994
->lrclk_shared
[1] = 1;
3562 wm8994_dai
[1].symmetric_rates
= 1;
3564 wm8994
->lrclk_shared
[1] = 0;
3567 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
3569 /* Latch volume updates (right only; we always do left then right). */
3570 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_LEFT_VOLUME
,
3571 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3572 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
3573 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3574 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_LEFT_VOLUME
,
3575 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3576 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
3577 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3578 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_LEFT_VOLUME
,
3579 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3580 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
3581 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3582 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_LEFT_VOLUME
,
3583 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3584 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
3585 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3586 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_LEFT_VOLUME
,
3587 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3588 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
3589 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3590 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_LEFT_VOLUME
,
3591 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3592 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3593 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3594 snd_soc_update_bits(codec
, WM8994_DAC1_LEFT_VOLUME
,
3595 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3596 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3597 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3598 snd_soc_update_bits(codec
, WM8994_DAC2_LEFT_VOLUME
,
3599 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3600 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3601 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3603 /* Set the low bit of the 3D stereo depth so TLV matches */
3604 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3605 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3606 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3607 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3608 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3609 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3610 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3611 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3612 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3614 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3615 * use this; it only affects behaviour on idle TDM clock
3617 switch (control
->type
) {
3620 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3621 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3627 /* Put MICBIAS into bypass mode by default on newer devices */
3628 switch (control
->type
) {
3631 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
3632 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
3633 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3634 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
3640 wm8994_update_class_w(codec
);
3642 wm8994_handle_pdata(wm8994
);
3644 wm_hubs_add_analogue_controls(codec
);
3645 snd_soc_add_controls(codec
, wm8994_snd_controls
,
3646 ARRAY_SIZE(wm8994_snd_controls
));
3647 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3648 ARRAY_SIZE(wm8994_dapm_widgets
));
3650 switch (control
->type
) {
3652 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3653 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3654 if (wm8994
->revision
< 4) {
3655 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3656 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3657 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3658 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3659 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3660 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3662 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3663 ARRAY_SIZE(wm8994_lateclk_widgets
));
3664 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3665 ARRAY_SIZE(wm8994_adc_widgets
));
3666 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3667 ARRAY_SIZE(wm8994_dac_widgets
));
3671 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3672 ARRAY_SIZE(wm8958_snd_controls
));
3673 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3674 ARRAY_SIZE(wm8958_dapm_widgets
));
3675 if (wm8994
->revision
< 1) {
3676 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3677 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3678 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3679 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3680 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3681 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3683 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3684 ARRAY_SIZE(wm8994_lateclk_widgets
));
3685 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3686 ARRAY_SIZE(wm8994_adc_widgets
));
3687 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3688 ARRAY_SIZE(wm8994_dac_widgets
));
3693 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3694 ARRAY_SIZE(wm8958_snd_controls
));
3695 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3696 ARRAY_SIZE(wm8958_dapm_widgets
));
3697 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3698 ARRAY_SIZE(wm8994_lateclk_widgets
));
3699 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3700 ARRAY_SIZE(wm8994_adc_widgets
));
3701 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3702 ARRAY_SIZE(wm8994_dac_widgets
));
3707 wm_hubs_add_analogue_routes(codec
, 0, 0);
3708 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
3710 switch (control
->type
) {
3712 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
3713 ARRAY_SIZE(wm8994_intercon
));
3715 if (wm8994
->revision
< 4) {
3716 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3717 ARRAY_SIZE(wm8994_revd_intercon
));
3718 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3719 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3721 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3722 ARRAY_SIZE(wm8994_lateclk_intercon
));
3726 if (wm8994
->revision
< 1) {
3727 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3728 ARRAY_SIZE(wm8994_revd_intercon
));
3729 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3730 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3732 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3733 ARRAY_SIZE(wm8994_lateclk_intercon
));
3734 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3735 ARRAY_SIZE(wm8958_intercon
));
3738 wm8958_dsp2_init(codec
);
3741 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3742 ARRAY_SIZE(wm8994_lateclk_intercon
));
3743 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3744 ARRAY_SIZE(wm8958_intercon
));
3751 if (wm8994
->jackdet
)
3752 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
3753 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
3754 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
3755 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
3756 if (wm8994
->micdet_irq
)
3757 free_irq(wm8994
->micdet_irq
, wm8994
);
3758 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3759 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
3760 &wm8994
->fll_locked
[i
]);
3761 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3763 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
3764 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
3765 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
3770 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
3772 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3773 struct wm8994
*control
= wm8994
->wm8994
;
3776 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3778 pm_runtime_disable(codec
->dev
);
3780 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3781 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
3782 &wm8994
->fll_locked
[i
]);
3784 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3786 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
3787 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
3788 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
3790 if (wm8994
->jackdet
)
3791 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
3793 switch (control
->type
) {
3795 if (wm8994
->micdet_irq
)
3796 free_irq(wm8994
->micdet_irq
, wm8994
);
3797 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
3799 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
3801 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
3807 if (wm8994
->micdet_irq
)
3808 free_irq(wm8994
->micdet_irq
, wm8994
);
3812 release_firmware(wm8994
->mbc
);
3813 if (wm8994
->mbc_vss
)
3814 release_firmware(wm8994
->mbc_vss
);
3816 release_firmware(wm8994
->enh_eq
);
3817 kfree(wm8994
->retune_mobile_texts
);
3822 static int wm8994_soc_volatile(struct snd_soc_codec
*codec
,
3828 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
3829 .probe
= wm8994_codec_probe
,
3830 .remove
= wm8994_codec_remove
,
3831 .suspend
= wm8994_suspend
,
3832 .resume
= wm8994_resume
,
3833 .set_bias_level
= wm8994_set_bias_level
,
3834 .reg_cache_size
= WM8994_MAX_REGISTER
,
3835 .volatile_register
= wm8994_soc_volatile
,
3838 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
3840 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
3841 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
3844 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
3846 snd_soc_unregister_codec(&pdev
->dev
);
3850 static struct platform_driver wm8994_codec_driver
= {
3852 .name
= "wm8994-codec",
3853 .owner
= THIS_MODULE
,
3855 .probe
= wm8994_probe
,
3856 .remove
= __devexit_p(wm8994_remove
),
3859 module_platform_driver(wm8994_codec_driver
);
3861 MODULE_DESCRIPTION("ASoC WM8994 driver");
3862 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3863 MODULE_LICENSE("GPL");
3864 MODULE_ALIAS("platform:wm8994-codec");