2 * wm8996.c - WM8996 audio codec interface
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
19 #include <linux/gcd.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
34 #include <sound/wm8996.h>
44 #define WM8996_NUM_SUPPLIES 3
45 static const char *wm8996_supply_names
[WM8996_NUM_SUPPLIES
] = {
52 struct snd_soc_codec
*codec
;
63 struct completion fll_lock
;
66 struct completion dcs_done
;
71 struct regulator_bulk_data supplies
[WM8996_NUM_SUPPLIES
];
72 struct notifier_block disable_nb
[WM8996_NUM_SUPPLIES
];
73 struct regulator
*cpvdd
;
76 struct wm8996_pdata pdata
;
78 int rx_rate
[WM8996_AIFS
];
79 int bclk_rate
[WM8996_AIFS
];
81 /* Platform dependant ReTune mobile configuration */
82 int num_retune_mobile_texts
;
83 const char **retune_mobile_texts
;
84 int retune_mobile_cfg
[2];
85 struct soc_enum retune_mobile_enum
;
87 struct snd_soc_jack
*jack
;
90 wm8996_polarity_fn polarity_cb
;
93 struct gpio_chip gpio_chip
;
97 /* We can't use the same notifier block for more than one supply and
98 * there's no way I can see to get from a callback to the caller
99 * except container_of().
101 #define WM8996_REGULATOR_EVENT(n) \
102 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
103 unsigned long event, void *data) \
105 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
107 if (event & REGULATOR_EVENT_DISABLE) { \
108 wm8996->codec->cache_sync = 1; \
113 WM8996_REGULATOR_EVENT(0)
114 WM8996_REGULATOR_EVENT(1)
115 WM8996_REGULATOR_EVENT(2)
117 static const u16 wm8996_reg
[WM8996_MAX_REGISTER
] = {
118 [WM8996_SOFTWARE_RESET
] = 0x8996,
119 [WM8996_POWER_MANAGEMENT_7
] = 0x10,
120 [WM8996_DAC1_HPOUT1_VOLUME
] = 0x88,
121 [WM8996_DAC2_HPOUT2_VOLUME
] = 0x88,
122 [WM8996_DAC1_LEFT_VOLUME
] = 0x2c0,
123 [WM8996_DAC1_RIGHT_VOLUME
] = 0x2c0,
124 [WM8996_DAC2_LEFT_VOLUME
] = 0x2c0,
125 [WM8996_DAC2_RIGHT_VOLUME
] = 0x2c0,
126 [WM8996_OUTPUT1_LEFT_VOLUME
] = 0x80,
127 [WM8996_OUTPUT1_RIGHT_VOLUME
] = 0x80,
128 [WM8996_OUTPUT2_LEFT_VOLUME
] = 0x80,
129 [WM8996_OUTPUT2_RIGHT_VOLUME
] = 0x80,
130 [WM8996_MICBIAS_1
] = 0x39,
131 [WM8996_MICBIAS_2
] = 0x39,
132 [WM8996_LDO_1
] = 0x3,
133 [WM8996_LDO_2
] = 0x13,
134 [WM8996_ACCESSORY_DETECT_MODE_1
] = 0x4,
135 [WM8996_HEADPHONE_DETECT_1
] = 0x20,
136 [WM8996_MIC_DETECT_1
] = 0x7600,
137 [WM8996_MIC_DETECT_2
] = 0xbf,
138 [WM8996_CHARGE_PUMP_1
] = 0x1f25,
139 [WM8996_CHARGE_PUMP_2
] = 0xab19,
140 [WM8996_DC_SERVO_5
] = 0x2a2a,
141 [WM8996_CONTROL_INTERFACE_1
] = 0x8004,
142 [WM8996_CLOCKING_1
] = 0x10,
143 [WM8996_AIF_RATE
] = 0x83,
144 [WM8996_FLL_CONTROL_4
] = 0x5dc0,
145 [WM8996_FLL_CONTROL_5
] = 0xc84,
146 [WM8996_FLL_EFS_2
] = 0x2,
147 [WM8996_AIF1_TX_LRCLK_1
] = 0x80,
148 [WM8996_AIF1_TX_LRCLK_2
] = 0x8,
149 [WM8996_AIF1_RX_LRCLK_1
] = 0x80,
150 [WM8996_AIF1TX_DATA_CONFIGURATION_1
] = 0x1818,
151 [WM8996_AIF1RX_DATA_CONFIGURATION
] = 0x1818,
152 [WM8996_AIF1TX_TEST
] = 0x7,
153 [WM8996_AIF2_TX_LRCLK_1
] = 0x80,
154 [WM8996_AIF2_TX_LRCLK_2
] = 0x8,
155 [WM8996_AIF2_RX_LRCLK_1
] = 0x80,
156 [WM8996_AIF2TX_DATA_CONFIGURATION_1
] = 0x1818,
157 [WM8996_AIF2RX_DATA_CONFIGURATION
] = 0x1818,
158 [WM8996_AIF2TX_TEST
] = 0x1,
159 [WM8996_DSP1_TX_LEFT_VOLUME
] = 0xc0,
160 [WM8996_DSP1_TX_RIGHT_VOLUME
] = 0xc0,
161 [WM8996_DSP1_RX_LEFT_VOLUME
] = 0xc0,
162 [WM8996_DSP1_RX_RIGHT_VOLUME
] = 0xc0,
163 [WM8996_DSP1_TX_FILTERS
] = 0x2000,
164 [WM8996_DSP1_RX_FILTERS_1
] = 0x200,
165 [WM8996_DSP1_RX_FILTERS_2
] = 0x10,
166 [WM8996_DSP1_DRC_1
] = 0x98,
167 [WM8996_DSP1_DRC_2
] = 0x845,
168 [WM8996_DSP1_RX_EQ_GAINS_1
] = 0x6318,
169 [WM8996_DSP1_RX_EQ_GAINS_2
] = 0x6300,
170 [WM8996_DSP1_RX_EQ_BAND_1_A
] = 0xfca,
171 [WM8996_DSP1_RX_EQ_BAND_1_B
] = 0x400,
172 [WM8996_DSP1_RX_EQ_BAND_1_PG
] = 0xd8,
173 [WM8996_DSP1_RX_EQ_BAND_2_A
] = 0x1eb5,
174 [WM8996_DSP1_RX_EQ_BAND_2_B
] = 0xf145,
175 [WM8996_DSP1_RX_EQ_BAND_2_C
] = 0xb75,
176 [WM8996_DSP1_RX_EQ_BAND_2_PG
] = 0x1c5,
177 [WM8996_DSP1_RX_EQ_BAND_3_A
] = 0x1c58,
178 [WM8996_DSP1_RX_EQ_BAND_3_B
] = 0xf373,
179 [WM8996_DSP1_RX_EQ_BAND_3_C
] = 0xa54,
180 [WM8996_DSP1_RX_EQ_BAND_3_PG
] = 0x558,
181 [WM8996_DSP1_RX_EQ_BAND_4_A
] = 0x168e,
182 [WM8996_DSP1_RX_EQ_BAND_4_B
] = 0xf829,
183 [WM8996_DSP1_RX_EQ_BAND_4_C
] = 0x7ad,
184 [WM8996_DSP1_RX_EQ_BAND_4_PG
] = 0x1103,
185 [WM8996_DSP1_RX_EQ_BAND_5_A
] = 0x564,
186 [WM8996_DSP1_RX_EQ_BAND_5_B
] = 0x559,
187 [WM8996_DSP1_RX_EQ_BAND_5_PG
] = 0x4000,
188 [WM8996_DSP2_TX_LEFT_VOLUME
] = 0xc0,
189 [WM8996_DSP2_TX_RIGHT_VOLUME
] = 0xc0,
190 [WM8996_DSP2_RX_LEFT_VOLUME
] = 0xc0,
191 [WM8996_DSP2_RX_RIGHT_VOLUME
] = 0xc0,
192 [WM8996_DSP2_TX_FILTERS
] = 0x2000,
193 [WM8996_DSP2_RX_FILTERS_1
] = 0x200,
194 [WM8996_DSP2_RX_FILTERS_2
] = 0x10,
195 [WM8996_DSP2_DRC_1
] = 0x98,
196 [WM8996_DSP2_DRC_2
] = 0x845,
197 [WM8996_DSP2_RX_EQ_GAINS_1
] = 0x6318,
198 [WM8996_DSP2_RX_EQ_GAINS_2
] = 0x6300,
199 [WM8996_DSP2_RX_EQ_BAND_1_A
] = 0xfca,
200 [WM8996_DSP2_RX_EQ_BAND_1_B
] = 0x400,
201 [WM8996_DSP2_RX_EQ_BAND_1_PG
] = 0xd8,
202 [WM8996_DSP2_RX_EQ_BAND_2_A
] = 0x1eb5,
203 [WM8996_DSP2_RX_EQ_BAND_2_B
] = 0xf145,
204 [WM8996_DSP2_RX_EQ_BAND_2_C
] = 0xb75,
205 [WM8996_DSP2_RX_EQ_BAND_2_PG
] = 0x1c5,
206 [WM8996_DSP2_RX_EQ_BAND_3_A
] = 0x1c58,
207 [WM8996_DSP2_RX_EQ_BAND_3_B
] = 0xf373,
208 [WM8996_DSP2_RX_EQ_BAND_3_C
] = 0xa54,
209 [WM8996_DSP2_RX_EQ_BAND_3_PG
] = 0x558,
210 [WM8996_DSP2_RX_EQ_BAND_4_A
] = 0x168e,
211 [WM8996_DSP2_RX_EQ_BAND_4_B
] = 0xf829,
212 [WM8996_DSP2_RX_EQ_BAND_4_C
] = 0x7ad,
213 [WM8996_DSP2_RX_EQ_BAND_4_PG
] = 0x1103,
214 [WM8996_DSP2_RX_EQ_BAND_5_A
] = 0x564,
215 [WM8996_DSP2_RX_EQ_BAND_5_B
] = 0x559,
216 [WM8996_DSP2_RX_EQ_BAND_5_PG
] = 0x4000,
217 [WM8996_OVERSAMPLING
] = 0xd,
218 [WM8996_SIDETONE
] = 0x1040,
219 [WM8996_GPIO_1
] = 0xa101,
220 [WM8996_GPIO_2
] = 0xa101,
221 [WM8996_GPIO_3
] = 0xa101,
222 [WM8996_GPIO_4
] = 0xa101,
223 [WM8996_GPIO_5
] = 0xa101,
224 [WM8996_PULL_CONTROL_2
] = 0x140,
225 [WM8996_INTERRUPT_STATUS_1_MASK
] = 0x1f,
226 [WM8996_INTERRUPT_STATUS_2_MASK
] = 0x1ecf,
227 [WM8996_RIGHT_PDM_SPEAKER
] = 0x1,
228 [WM8996_PDM_SPEAKER_MUTE_SEQUENCE
] = 0x69,
229 [WM8996_PDM_SPEAKER_VOLUME
] = 0x66,
230 [WM8996_WRITE_SEQUENCER_0
] = 0x1,
231 [WM8996_WRITE_SEQUENCER_1
] = 0x1,
232 [WM8996_WRITE_SEQUENCER_3
] = 0x6,
233 [WM8996_WRITE_SEQUENCER_4
] = 0x40,
234 [WM8996_WRITE_SEQUENCER_5
] = 0x1,
235 [WM8996_WRITE_SEQUENCER_6
] = 0xf,
236 [WM8996_WRITE_SEQUENCER_7
] = 0x6,
237 [WM8996_WRITE_SEQUENCER_8
] = 0x1,
238 [WM8996_WRITE_SEQUENCER_9
] = 0x3,
239 [WM8996_WRITE_SEQUENCER_10
] = 0x104,
240 [WM8996_WRITE_SEQUENCER_12
] = 0x60,
241 [WM8996_WRITE_SEQUENCER_13
] = 0x11,
242 [WM8996_WRITE_SEQUENCER_14
] = 0x401,
243 [WM8996_WRITE_SEQUENCER_16
] = 0x50,
244 [WM8996_WRITE_SEQUENCER_17
] = 0x3,
245 [WM8996_WRITE_SEQUENCER_18
] = 0x100,
246 [WM8996_WRITE_SEQUENCER_20
] = 0x51,
247 [WM8996_WRITE_SEQUENCER_21
] = 0x3,
248 [WM8996_WRITE_SEQUENCER_22
] = 0x104,
249 [WM8996_WRITE_SEQUENCER_23
] = 0xa,
250 [WM8996_WRITE_SEQUENCER_24
] = 0x60,
251 [WM8996_WRITE_SEQUENCER_25
] = 0x3b,
252 [WM8996_WRITE_SEQUENCER_26
] = 0x502,
253 [WM8996_WRITE_SEQUENCER_27
] = 0x100,
254 [WM8996_WRITE_SEQUENCER_28
] = 0x2fff,
255 [WM8996_WRITE_SEQUENCER_32
] = 0x2fff,
256 [WM8996_WRITE_SEQUENCER_36
] = 0x2fff,
257 [WM8996_WRITE_SEQUENCER_40
] = 0x2fff,
258 [WM8996_WRITE_SEQUENCER_44
] = 0x2fff,
259 [WM8996_WRITE_SEQUENCER_48
] = 0x2fff,
260 [WM8996_WRITE_SEQUENCER_52
] = 0x2fff,
261 [WM8996_WRITE_SEQUENCER_56
] = 0x2fff,
262 [WM8996_WRITE_SEQUENCER_60
] = 0x2fff,
263 [WM8996_WRITE_SEQUENCER_64
] = 0x1,
264 [WM8996_WRITE_SEQUENCER_65
] = 0x1,
265 [WM8996_WRITE_SEQUENCER_67
] = 0x6,
266 [WM8996_WRITE_SEQUENCER_68
] = 0x40,
267 [WM8996_WRITE_SEQUENCER_69
] = 0x1,
268 [WM8996_WRITE_SEQUENCER_70
] = 0xf,
269 [WM8996_WRITE_SEQUENCER_71
] = 0x6,
270 [WM8996_WRITE_SEQUENCER_72
] = 0x1,
271 [WM8996_WRITE_SEQUENCER_73
] = 0x3,
272 [WM8996_WRITE_SEQUENCER_74
] = 0x104,
273 [WM8996_WRITE_SEQUENCER_76
] = 0x60,
274 [WM8996_WRITE_SEQUENCER_77
] = 0x11,
275 [WM8996_WRITE_SEQUENCER_78
] = 0x401,
276 [WM8996_WRITE_SEQUENCER_80
] = 0x50,
277 [WM8996_WRITE_SEQUENCER_81
] = 0x3,
278 [WM8996_WRITE_SEQUENCER_82
] = 0x100,
279 [WM8996_WRITE_SEQUENCER_84
] = 0x60,
280 [WM8996_WRITE_SEQUENCER_85
] = 0x3b,
281 [WM8996_WRITE_SEQUENCER_86
] = 0x502,
282 [WM8996_WRITE_SEQUENCER_87
] = 0x100,
283 [WM8996_WRITE_SEQUENCER_88
] = 0x2fff,
284 [WM8996_WRITE_SEQUENCER_92
] = 0x2fff,
285 [WM8996_WRITE_SEQUENCER_96
] = 0x2fff,
286 [WM8996_WRITE_SEQUENCER_100
] = 0x2fff,
287 [WM8996_WRITE_SEQUENCER_104
] = 0x2fff,
288 [WM8996_WRITE_SEQUENCER_108
] = 0x2fff,
289 [WM8996_WRITE_SEQUENCER_112
] = 0x2fff,
290 [WM8996_WRITE_SEQUENCER_116
] = 0x2fff,
291 [WM8996_WRITE_SEQUENCER_120
] = 0x2fff,
292 [WM8996_WRITE_SEQUENCER_124
] = 0x2fff,
293 [WM8996_WRITE_SEQUENCER_128
] = 0x1,
294 [WM8996_WRITE_SEQUENCER_129
] = 0x1,
295 [WM8996_WRITE_SEQUENCER_131
] = 0x6,
296 [WM8996_WRITE_SEQUENCER_132
] = 0x40,
297 [WM8996_WRITE_SEQUENCER_133
] = 0x1,
298 [WM8996_WRITE_SEQUENCER_134
] = 0xf,
299 [WM8996_WRITE_SEQUENCER_135
] = 0x6,
300 [WM8996_WRITE_SEQUENCER_136
] = 0x1,
301 [WM8996_WRITE_SEQUENCER_137
] = 0x3,
302 [WM8996_WRITE_SEQUENCER_138
] = 0x106,
303 [WM8996_WRITE_SEQUENCER_140
] = 0x61,
304 [WM8996_WRITE_SEQUENCER_141
] = 0x11,
305 [WM8996_WRITE_SEQUENCER_142
] = 0x401,
306 [WM8996_WRITE_SEQUENCER_144
] = 0x50,
307 [WM8996_WRITE_SEQUENCER_145
] = 0x3,
308 [WM8996_WRITE_SEQUENCER_146
] = 0x102,
309 [WM8996_WRITE_SEQUENCER_148
] = 0x51,
310 [WM8996_WRITE_SEQUENCER_149
] = 0x3,
311 [WM8996_WRITE_SEQUENCER_150
] = 0x106,
312 [WM8996_WRITE_SEQUENCER_151
] = 0xa,
313 [WM8996_WRITE_SEQUENCER_152
] = 0x61,
314 [WM8996_WRITE_SEQUENCER_153
] = 0x3b,
315 [WM8996_WRITE_SEQUENCER_154
] = 0x502,
316 [WM8996_WRITE_SEQUENCER_155
] = 0x100,
317 [WM8996_WRITE_SEQUENCER_156
] = 0x2fff,
318 [WM8996_WRITE_SEQUENCER_160
] = 0x2fff,
319 [WM8996_WRITE_SEQUENCER_164
] = 0x2fff,
320 [WM8996_WRITE_SEQUENCER_168
] = 0x2fff,
321 [WM8996_WRITE_SEQUENCER_172
] = 0x2fff,
322 [WM8996_WRITE_SEQUENCER_176
] = 0x2fff,
323 [WM8996_WRITE_SEQUENCER_180
] = 0x2fff,
324 [WM8996_WRITE_SEQUENCER_184
] = 0x2fff,
325 [WM8996_WRITE_SEQUENCER_188
] = 0x2fff,
326 [WM8996_WRITE_SEQUENCER_192
] = 0x1,
327 [WM8996_WRITE_SEQUENCER_193
] = 0x1,
328 [WM8996_WRITE_SEQUENCER_195
] = 0x6,
329 [WM8996_WRITE_SEQUENCER_196
] = 0x40,
330 [WM8996_WRITE_SEQUENCER_197
] = 0x1,
331 [WM8996_WRITE_SEQUENCER_198
] = 0xf,
332 [WM8996_WRITE_SEQUENCER_199
] = 0x6,
333 [WM8996_WRITE_SEQUENCER_200
] = 0x1,
334 [WM8996_WRITE_SEQUENCER_201
] = 0x3,
335 [WM8996_WRITE_SEQUENCER_202
] = 0x106,
336 [WM8996_WRITE_SEQUENCER_204
] = 0x61,
337 [WM8996_WRITE_SEQUENCER_205
] = 0x11,
338 [WM8996_WRITE_SEQUENCER_206
] = 0x401,
339 [WM8996_WRITE_SEQUENCER_208
] = 0x50,
340 [WM8996_WRITE_SEQUENCER_209
] = 0x3,
341 [WM8996_WRITE_SEQUENCER_210
] = 0x102,
342 [WM8996_WRITE_SEQUENCER_212
] = 0x61,
343 [WM8996_WRITE_SEQUENCER_213
] = 0x3b,
344 [WM8996_WRITE_SEQUENCER_214
] = 0x502,
345 [WM8996_WRITE_SEQUENCER_215
] = 0x100,
346 [WM8996_WRITE_SEQUENCER_216
] = 0x2fff,
347 [WM8996_WRITE_SEQUENCER_220
] = 0x2fff,
348 [WM8996_WRITE_SEQUENCER_224
] = 0x2fff,
349 [WM8996_WRITE_SEQUENCER_228
] = 0x2fff,
350 [WM8996_WRITE_SEQUENCER_232
] = 0x2fff,
351 [WM8996_WRITE_SEQUENCER_236
] = 0x2fff,
352 [WM8996_WRITE_SEQUENCER_240
] = 0x2fff,
353 [WM8996_WRITE_SEQUENCER_244
] = 0x2fff,
354 [WM8996_WRITE_SEQUENCER_248
] = 0x2fff,
355 [WM8996_WRITE_SEQUENCER_252
] = 0x2fff,
356 [WM8996_WRITE_SEQUENCER_256
] = 0x60,
357 [WM8996_WRITE_SEQUENCER_258
] = 0x601,
358 [WM8996_WRITE_SEQUENCER_260
] = 0x50,
359 [WM8996_WRITE_SEQUENCER_262
] = 0x100,
360 [WM8996_WRITE_SEQUENCER_264
] = 0x1,
361 [WM8996_WRITE_SEQUENCER_266
] = 0x104,
362 [WM8996_WRITE_SEQUENCER_267
] = 0x100,
363 [WM8996_WRITE_SEQUENCER_268
] = 0x2fff,
364 [WM8996_WRITE_SEQUENCER_272
] = 0x2fff,
365 [WM8996_WRITE_SEQUENCER_276
] = 0x2fff,
366 [WM8996_WRITE_SEQUENCER_280
] = 0x2fff,
367 [WM8996_WRITE_SEQUENCER_284
] = 0x2fff,
368 [WM8996_WRITE_SEQUENCER_288
] = 0x2fff,
369 [WM8996_WRITE_SEQUENCER_292
] = 0x2fff,
370 [WM8996_WRITE_SEQUENCER_296
] = 0x2fff,
371 [WM8996_WRITE_SEQUENCER_300
] = 0x2fff,
372 [WM8996_WRITE_SEQUENCER_304
] = 0x2fff,
373 [WM8996_WRITE_SEQUENCER_308
] = 0x2fff,
374 [WM8996_WRITE_SEQUENCER_312
] = 0x2fff,
375 [WM8996_WRITE_SEQUENCER_316
] = 0x2fff,
376 [WM8996_WRITE_SEQUENCER_320
] = 0x61,
377 [WM8996_WRITE_SEQUENCER_322
] = 0x601,
378 [WM8996_WRITE_SEQUENCER_324
] = 0x50,
379 [WM8996_WRITE_SEQUENCER_326
] = 0x102,
380 [WM8996_WRITE_SEQUENCER_328
] = 0x1,
381 [WM8996_WRITE_SEQUENCER_330
] = 0x106,
382 [WM8996_WRITE_SEQUENCER_331
] = 0x100,
383 [WM8996_WRITE_SEQUENCER_332
] = 0x2fff,
384 [WM8996_WRITE_SEQUENCER_336
] = 0x2fff,
385 [WM8996_WRITE_SEQUENCER_340
] = 0x2fff,
386 [WM8996_WRITE_SEQUENCER_344
] = 0x2fff,
387 [WM8996_WRITE_SEQUENCER_348
] = 0x2fff,
388 [WM8996_WRITE_SEQUENCER_352
] = 0x2fff,
389 [WM8996_WRITE_SEQUENCER_356
] = 0x2fff,
390 [WM8996_WRITE_SEQUENCER_360
] = 0x2fff,
391 [WM8996_WRITE_SEQUENCER_364
] = 0x2fff,
392 [WM8996_WRITE_SEQUENCER_368
] = 0x2fff,
393 [WM8996_WRITE_SEQUENCER_372
] = 0x2fff,
394 [WM8996_WRITE_SEQUENCER_376
] = 0x2fff,
395 [WM8996_WRITE_SEQUENCER_380
] = 0x2fff,
396 [WM8996_WRITE_SEQUENCER_384
] = 0x60,
397 [WM8996_WRITE_SEQUENCER_386
] = 0x601,
398 [WM8996_WRITE_SEQUENCER_388
] = 0x61,
399 [WM8996_WRITE_SEQUENCER_390
] = 0x601,
400 [WM8996_WRITE_SEQUENCER_392
] = 0x50,
401 [WM8996_WRITE_SEQUENCER_394
] = 0x300,
402 [WM8996_WRITE_SEQUENCER_396
] = 0x1,
403 [WM8996_WRITE_SEQUENCER_398
] = 0x304,
404 [WM8996_WRITE_SEQUENCER_400
] = 0x40,
405 [WM8996_WRITE_SEQUENCER_402
] = 0xf,
406 [WM8996_WRITE_SEQUENCER_404
] = 0x1,
407 [WM8996_WRITE_SEQUENCER_407
] = 0x100,
410 static const DECLARE_TLV_DB_SCALE(inpga_tlv
, 0, 100, 0);
411 static const DECLARE_TLV_DB_SCALE(sidetone_tlv
, -3600, 150, 0);
412 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
413 static const DECLARE_TLV_DB_SCALE(out_digital_tlv
, -1200, 150, 0);
414 static const DECLARE_TLV_DB_SCALE(out_tlv
, -900, 75, 0);
415 static const DECLARE_TLV_DB_SCALE(spk_tlv
, -900, 150, 0);
416 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
417 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv
, -1600, 183, 1);
419 static const char *sidetone_hpf_text
[] = {
420 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
423 static const struct soc_enum sidetone_hpf
=
424 SOC_ENUM_SINGLE(WM8996_SIDETONE
, 7, 7, sidetone_hpf_text
);
426 static const char *hpf_mode_text
[] = {
427 "HiFi", "Custom", "Voice"
430 static const struct soc_enum dsp1tx_hpf_mode
=
431 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS
, 3, 3, hpf_mode_text
);
433 static const struct soc_enum dsp2tx_hpf_mode
=
434 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS
, 3, 3, hpf_mode_text
);
436 static const char *hpf_cutoff_text
[] = {
437 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
440 static const struct soc_enum dsp1tx_hpf_cutoff
=
441 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS
, 0, 7, hpf_cutoff_text
);
443 static const struct soc_enum dsp2tx_hpf_cutoff
=
444 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS
, 0, 7, hpf_cutoff_text
);
446 static void wm8996_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
448 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
449 struct wm8996_pdata
*pdata
= &wm8996
->pdata
;
450 int base
, best
, best_val
, save
, i
, cfg
, iface
;
452 if (!wm8996
->num_retune_mobile_texts
)
457 base
= WM8996_DSP1_RX_EQ_GAINS_1
;
458 if (snd_soc_read(codec
, WM8996_POWER_MANAGEMENT_8
) &
465 base
= WM8996_DSP1_RX_EQ_GAINS_2
;
466 if (snd_soc_read(codec
, WM8996_POWER_MANAGEMENT_8
) &
476 /* Find the version of the currently selected configuration
477 * with the nearest sample rate. */
478 cfg
= wm8996
->retune_mobile_cfg
[block
];
481 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
482 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
483 wm8996
->retune_mobile_texts
[cfg
]) == 0 &&
484 abs(pdata
->retune_mobile_cfgs
[i
].rate
485 - wm8996
->rx_rate
[iface
]) < best_val
) {
487 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
488 - wm8996
->rx_rate
[iface
]);
492 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
494 pdata
->retune_mobile_cfgs
[best
].name
,
495 pdata
->retune_mobile_cfgs
[best
].rate
,
496 wm8996
->rx_rate
[iface
]);
498 /* The EQ will be disabled while reconfiguring it, remember the
499 * current configuration.
501 save
= snd_soc_read(codec
, base
);
502 save
&= WM8996_DSP1RX_EQ_ENA
;
504 for (i
= 0; i
< ARRAY_SIZE(pdata
->retune_mobile_cfgs
[best
].regs
); i
++)
505 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
506 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
508 snd_soc_update_bits(codec
, base
, WM8996_DSP1RX_EQ_ENA
, save
);
511 /* Icky as hell but saves code duplication */
512 static int wm8996_get_retune_mobile_block(const char *name
)
514 if (strcmp(name
, "DSP1 EQ Mode") == 0)
516 if (strcmp(name
, "DSP2 EQ Mode") == 0)
521 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
522 struct snd_ctl_elem_value
*ucontrol
)
524 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
525 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
526 struct wm8996_pdata
*pdata
= &wm8996
->pdata
;
527 int block
= wm8996_get_retune_mobile_block(kcontrol
->id
.name
);
528 int value
= ucontrol
->value
.integer
.value
[0];
533 if (value
>= pdata
->num_retune_mobile_cfgs
)
536 wm8996
->retune_mobile_cfg
[block
] = value
;
538 wm8996_set_retune_mobile(codec
, block
);
543 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
544 struct snd_ctl_elem_value
*ucontrol
)
546 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
547 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
548 int block
= wm8996_get_retune_mobile_block(kcontrol
->id
.name
);
550 ucontrol
->value
.enumerated
.item
[0] = wm8996
->retune_mobile_cfg
[block
];
555 static const struct snd_kcontrol_new wm8996_snd_controls
[] = {
556 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME
,
557 WM8996_RIGHT_LINE_INPUT_VOLUME
, 0, 31, 0, inpga_tlv
),
558 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME
,
559 WM8996_RIGHT_LINE_INPUT_VOLUME
, 5, 1, 0),
561 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES
,
562 0, 5, 24, 0, sidetone_tlv
),
563 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES
,
564 0, 5, 24, 0, sidetone_tlv
),
565 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE
, 12, 1, 0),
566 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf
),
567 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE
, 6, 1, 0),
569 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME
,
570 WM8996_DSP1_TX_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
571 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME
,
572 WM8996_DSP2_TX_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
574 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS
,
576 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS
, 12, 11, 1, 0),
577 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode
),
578 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff
),
580 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS
,
582 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS
, 12, 11, 1, 0),
583 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode
),
584 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff
),
586 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME
,
587 WM8996_DSP1_RX_RIGHT_VOLUME
, 1, 112, 0, digital_tlv
),
588 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1
, 9, 1, 1),
590 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME
,
591 WM8996_DSP2_RX_RIGHT_VOLUME
, 1, 112, 0, digital_tlv
),
592 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1
, 9, 1, 1),
594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME
,
595 WM8996_DAC1_RIGHT_VOLUME
, 1, 112, 0, digital_tlv
),
596 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME
,
597 WM8996_DAC1_RIGHT_VOLUME
, 9, 1, 1),
599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME
,
600 WM8996_DAC2_RIGHT_VOLUME
, 1, 112, 0, digital_tlv
),
601 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME
,
602 WM8996_DAC2_RIGHT_VOLUME
, 9, 1, 1),
604 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING
, 3, 1, 0),
605 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING
, 2, 1, 0),
606 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING
, 1, 1, 0),
607 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING
, 0, 1, 0),
609 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE
, 1, 1, 0),
610 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE
, 0, 1, 0),
612 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2
, 8, 1, 0),
613 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2
, 8, 1, 0),
615 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2
, 10, 15,
616 0, threedstereo_tlv
),
617 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2
, 10, 15,
618 0, threedstereo_tlv
),
620 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME
, 0, 4,
621 8, 0, out_digital_tlv
),
622 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME
, 0, 4,
623 8, 0, out_digital_tlv
),
625 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME
,
626 WM8996_OUTPUT1_RIGHT_VOLUME
, 0, 12, 0, out_tlv
),
627 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME
,
628 WM8996_OUTPUT1_RIGHT_VOLUME
, 7, 1, 0),
630 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME
,
631 WM8996_OUTPUT2_RIGHT_VOLUME
, 0, 12, 0, out_tlv
),
632 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME
,
633 WM8996_OUTPUT2_RIGHT_VOLUME
, 7, 1, 0),
635 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME
, 0, 4, 8, 0,
637 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER
,
638 WM8996_RIGHT_PDM_SPEAKER
, 3, 1, 1),
639 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER
,
640 WM8996_RIGHT_PDM_SPEAKER
, 2, 1, 0),
642 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1
, 0, 1, 0),
643 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1
, 0, 1, 0),
646 static const struct snd_kcontrol_new wm8996_eq_controls
[] = {
647 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1
, 11, 31, 0,
649 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1
, 6, 31, 0,
651 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1
, 1, 31, 0,
653 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2
, 11, 31, 0,
655 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2
, 6, 31, 0,
658 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1
, 11, 31, 0,
660 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1
, 6, 31, 0,
662 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1
, 1, 31, 0,
664 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2
, 11, 31, 0,
666 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2
, 6, 31, 0,
670 static void wm8996_bg_enable(struct snd_soc_codec
*codec
)
672 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
675 if (wm8996
->bg_ena
== 1) {
676 snd_soc_update_bits(codec
, WM8996_POWER_MANAGEMENT_1
,
677 WM8996_BG_ENA
, WM8996_BG_ENA
);
682 static void wm8996_bg_disable(struct snd_soc_codec
*codec
)
684 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
688 snd_soc_update_bits(codec
, WM8996_POWER_MANAGEMENT_1
,
692 static int bg_event(struct snd_soc_dapm_widget
*w
,
693 struct snd_kcontrol
*kcontrol
, int event
)
695 struct snd_soc_codec
*codec
= w
->codec
;
699 case SND_SOC_DAPM_PRE_PMU
:
700 wm8996_bg_enable(codec
);
702 case SND_SOC_DAPM_POST_PMD
:
703 wm8996_bg_disable(codec
);
713 static int cp_event(struct snd_soc_dapm_widget
*w
,
714 struct snd_kcontrol
*kcontrol
, int event
)
716 struct snd_soc_codec
*codec
= w
->codec
;
717 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
721 case SND_SOC_DAPM_PRE_PMU
:
722 ret
= regulator_enable(wm8996
->cpvdd
);
724 dev_err(codec
->dev
, "Failed to enable CPVDD: %d\n",
727 case SND_SOC_DAPM_POST_PMU
:
730 case SND_SOC_DAPM_POST_PMD
:
731 regulator_disable_deferred(wm8996
->cpvdd
, 20);
741 static int rmv_short_event(struct snd_soc_dapm_widget
*w
,
742 struct snd_kcontrol
*kcontrol
, int event
)
744 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(w
->codec
);
746 /* Record which outputs we enabled */
748 case SND_SOC_DAPM_PRE_PMD
:
749 wm8996
->hpout_pending
&= ~w
->shift
;
751 case SND_SOC_DAPM_PRE_PMU
:
752 wm8996
->hpout_pending
|= w
->shift
;
762 static void wait_for_dc_servo(struct snd_soc_codec
*codec
, u16 mask
)
764 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
765 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
767 unsigned long timeout
= 200;
769 snd_soc_write(codec
, WM8996_DC_SERVO_2
, mask
);
771 /* Use the interrupt if possible */
774 timeout
= wait_for_completion_timeout(&wm8996
->dcs_done
,
775 msecs_to_jiffies(200));
777 dev_err(codec
->dev
, "DC servo timed out\n");
784 ret
= snd_soc_read(codec
, WM8996_DC_SERVO_2
);
785 dev_dbg(codec
->dev
, "DC servo state: %x\n", ret
);
786 } while (timeout
&& ret
& mask
);
789 dev_err(codec
->dev
, "DC servo timed out for %x\n", mask
);
791 dev_dbg(codec
->dev
, "DC servo complete for %x\n", mask
);
794 static void wm8996_seq_notifier(struct snd_soc_dapm_context
*dapm
,
795 enum snd_soc_dapm_type event
, int subseq
)
797 struct snd_soc_codec
*codec
= container_of(dapm
,
798 struct snd_soc_codec
, dapm
);
799 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
802 /* Complete any pending DC servo starts */
803 if (wm8996
->dcs_pending
) {
804 dev_dbg(codec
->dev
, "Starting DC servo for %x\n",
805 wm8996
->dcs_pending
);
807 /* Trigger a startup sequence */
808 wait_for_dc_servo(codec
, wm8996
->dcs_pending
809 << WM8996_DCS_TRIG_STARTUP_0_SHIFT
);
811 wm8996
->dcs_pending
= 0;
814 if (wm8996
->hpout_pending
!= wm8996
->hpout_ena
) {
815 dev_dbg(codec
->dev
, "Applying RMV_SHORTs %x->%x\n",
816 wm8996
->hpout_ena
, wm8996
->hpout_pending
);
820 if (wm8996
->hpout_pending
& HPOUT1L
) {
821 val
|= WM8996_HPOUT1L_RMV_SHORT
;
822 mask
|= WM8996_HPOUT1L_RMV_SHORT
;
824 mask
|= WM8996_HPOUT1L_RMV_SHORT
|
825 WM8996_HPOUT1L_OUTP
|
829 if (wm8996
->hpout_pending
& HPOUT1R
) {
830 val
|= WM8996_HPOUT1R_RMV_SHORT
;
831 mask
|= WM8996_HPOUT1R_RMV_SHORT
;
833 mask
|= WM8996_HPOUT1R_RMV_SHORT
|
834 WM8996_HPOUT1R_OUTP
|
838 snd_soc_update_bits(codec
, WM8996_ANALOGUE_HP_1
, mask
, val
);
842 if (wm8996
->hpout_pending
& HPOUT2L
) {
843 val
|= WM8996_HPOUT2L_RMV_SHORT
;
844 mask
|= WM8996_HPOUT2L_RMV_SHORT
;
846 mask
|= WM8996_HPOUT2L_RMV_SHORT
|
847 WM8996_HPOUT2L_OUTP
|
851 if (wm8996
->hpout_pending
& HPOUT2R
) {
852 val
|= WM8996_HPOUT2R_RMV_SHORT
;
853 mask
|= WM8996_HPOUT2R_RMV_SHORT
;
855 mask
|= WM8996_HPOUT2R_RMV_SHORT
|
856 WM8996_HPOUT2R_OUTP
|
860 snd_soc_update_bits(codec
, WM8996_ANALOGUE_HP_2
, mask
, val
);
862 wm8996
->hpout_ena
= wm8996
->hpout_pending
;
866 static int dcs_start(struct snd_soc_dapm_widget
*w
,
867 struct snd_kcontrol
*kcontrol
, int event
)
869 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(w
->codec
);
872 case SND_SOC_DAPM_POST_PMU
:
873 wm8996
->dcs_pending
|= 1 << w
->shift
;
883 static const char *sidetone_text
[] = {
887 static const struct soc_enum left_sidetone_enum
=
888 SOC_ENUM_SINGLE(WM8996_SIDETONE
, 0, 2, sidetone_text
);
890 static const struct snd_kcontrol_new left_sidetone
=
891 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum
);
893 static const struct soc_enum right_sidetone_enum
=
894 SOC_ENUM_SINGLE(WM8996_SIDETONE
, 1, 2, sidetone_text
);
896 static const struct snd_kcontrol_new right_sidetone
=
897 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum
);
899 static const char *spk_text
[] = {
900 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
903 static const struct soc_enum spkl_enum
=
904 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER
, 0, 4, spk_text
);
906 static const struct snd_kcontrol_new spkl_mux
=
907 SOC_DAPM_ENUM("SPKL", spkl_enum
);
909 static const struct soc_enum spkr_enum
=
910 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER
, 0, 4, spk_text
);
912 static const struct snd_kcontrol_new spkr_mux
=
913 SOC_DAPM_ENUM("SPKR", spkr_enum
);
915 static const char *dsp1rx_text
[] = {
919 static const struct soc_enum dsp1rx_enum
=
920 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8
, 0, 2, dsp1rx_text
);
922 static const struct snd_kcontrol_new dsp1rx
=
923 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum
);
925 static const char *dsp2rx_text
[] = {
929 static const struct soc_enum dsp2rx_enum
=
930 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8
, 4, 2, dsp2rx_text
);
932 static const struct snd_kcontrol_new dsp2rx
=
933 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum
);
935 static const char *aif2tx_text
[] = {
936 "DSP2", "DSP1", "AIF1"
939 static const struct soc_enum aif2tx_enum
=
940 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8
, 6, 3, aif2tx_text
);
942 static const struct snd_kcontrol_new aif2tx
=
943 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum
);
945 static const char *inmux_text
[] = {
946 "ADC", "DMIC1", "DMIC2"
949 static const struct soc_enum in1_enum
=
950 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7
, 0, 3, inmux_text
);
952 static const struct snd_kcontrol_new in1_mux
=
953 SOC_DAPM_ENUM("IN1 Mux", in1_enum
);
955 static const struct soc_enum in2_enum
=
956 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7
, 4, 3, inmux_text
);
958 static const struct snd_kcontrol_new in2_mux
=
959 SOC_DAPM_ENUM("IN2 Mux", in2_enum
);
961 static const struct snd_kcontrol_new dac2r_mix
[] = {
962 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING
,
964 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING
,
966 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING
, 1, 1, 0),
967 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING
, 0, 1, 0),
970 static const struct snd_kcontrol_new dac2l_mix
[] = {
971 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING
,
973 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING
,
975 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING
, 1, 1, 0),
976 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING
, 0, 1, 0),
979 static const struct snd_kcontrol_new dac1r_mix
[] = {
980 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING
,
982 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING
,
984 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING
, 1, 1, 0),
985 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING
, 0, 1, 0),
988 static const struct snd_kcontrol_new dac1l_mix
[] = {
989 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING
,
991 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING
,
993 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING
, 1, 1, 0),
994 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING
, 0, 1, 0),
997 static const struct snd_kcontrol_new dsp1txl
[] = {
998 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING
,
1000 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING
,
1004 static const struct snd_kcontrol_new dsp1txr
[] = {
1005 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING
,
1007 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING
,
1011 static const struct snd_kcontrol_new dsp2txl
[] = {
1012 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING
,
1014 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING
,
1018 static const struct snd_kcontrol_new dsp2txr
[] = {
1019 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING
,
1021 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING
,
1026 static const struct snd_soc_dapm_widget wm8996_dapm_widgets
[] = {
1027 SND_SOC_DAPM_INPUT("IN1LN"),
1028 SND_SOC_DAPM_INPUT("IN1LP"),
1029 SND_SOC_DAPM_INPUT("IN1RN"),
1030 SND_SOC_DAPM_INPUT("IN1RP"),
1032 SND_SOC_DAPM_INPUT("IN2LN"),
1033 SND_SOC_DAPM_INPUT("IN2LP"),
1034 SND_SOC_DAPM_INPUT("IN2RN"),
1035 SND_SOC_DAPM_INPUT("IN2RP"),
1037 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1038 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1040 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1
, 0, 0, NULL
, 0),
1041 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1
, 1, 0, NULL
, 0),
1042 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1
, 2, 0, NULL
, 0),
1043 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1
, 15, 0, cp_event
,
1044 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1045 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM
, 0, 0, bg_event
,
1046 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1047 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2
, 1, 0, NULL
, 0),
1048 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1
, 4, 1, NULL
, 0),
1049 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2
, 4, 1, NULL
, 0),
1050 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1
, 9, 0),
1051 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1
, 8, 0),
1053 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2
, 5, 0, NULL
, 0),
1054 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2
, 4, 0, NULL
, 0),
1056 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7
, 2, 0, &in1_mux
),
1057 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7
, 3, 0, &in1_mux
),
1058 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7
, 6, 0, &in2_mux
),
1059 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7
, 7, 0, &in2_mux
),
1061 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7
, 9, 0, NULL
, 0),
1062 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7
, 8, 0, NULL
, 0),
1064 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8996_POWER_MANAGEMENT_3
, 5, 0),
1065 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8996_POWER_MANAGEMENT_3
, 4, 0),
1066 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8996_POWER_MANAGEMENT_3
, 3, 0),
1067 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8996_POWER_MANAGEMENT_3
, 2, 0),
1069 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8996_POWER_MANAGEMENT_3
, 1, 0),
1070 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8996_POWER_MANAGEMENT_3
, 0, 0),
1072 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &left_sidetone
),
1073 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &right_sidetone
),
1075 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL
, 0, WM8996_POWER_MANAGEMENT_3
, 11, 0),
1076 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL
, 1, WM8996_POWER_MANAGEMENT_3
, 10, 0),
1077 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL
, 0, WM8996_POWER_MANAGEMENT_3
, 9, 0),
1078 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL
, 1, WM8996_POWER_MANAGEMENT_3
, 8, 0),
1080 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5
, 11, 0,
1081 dsp2txl
, ARRAY_SIZE(dsp2txl
)),
1082 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5
, 10, 0,
1083 dsp2txr
, ARRAY_SIZE(dsp2txr
)),
1084 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5
, 9, 0,
1085 dsp1txl
, ARRAY_SIZE(dsp1txl
)),
1086 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5
, 8, 0,
1087 dsp1txr
, ARRAY_SIZE(dsp1txr
)),
1089 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1090 dac2l_mix
, ARRAY_SIZE(dac2l_mix
)),
1091 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1092 dac2r_mix
, ARRAY_SIZE(dac2r_mix
)),
1093 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1094 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1095 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1096 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1098 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8996_POWER_MANAGEMENT_5
, 3, 0),
1099 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8996_POWER_MANAGEMENT_5
, 2, 0),
1100 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8996_POWER_MANAGEMENT_5
, 1, 0),
1101 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8996_POWER_MANAGEMENT_5
, 0, 0),
1103 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
1104 WM8996_POWER_MANAGEMENT_4
, 9, 0),
1105 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
1106 WM8996_POWER_MANAGEMENT_4
, 8, 0),
1108 SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 0,
1109 WM8996_POWER_MANAGEMENT_6
, 9, 0),
1110 SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 1,
1111 WM8996_POWER_MANAGEMENT_6
, 8, 0),
1113 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1114 WM8996_POWER_MANAGEMENT_4
, 5, 0),
1115 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1116 WM8996_POWER_MANAGEMENT_4
, 4, 0),
1117 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1118 WM8996_POWER_MANAGEMENT_4
, 3, 0),
1119 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1120 WM8996_POWER_MANAGEMENT_4
, 2, 0),
1121 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1122 WM8996_POWER_MANAGEMENT_4
, 1, 0),
1123 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1124 WM8996_POWER_MANAGEMENT_4
, 0, 0),
1126 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1127 WM8996_POWER_MANAGEMENT_6
, 5, 0),
1128 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1129 WM8996_POWER_MANAGEMENT_6
, 4, 0),
1130 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1131 WM8996_POWER_MANAGEMENT_6
, 3, 0),
1132 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1133 WM8996_POWER_MANAGEMENT_6
, 2, 0),
1134 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1135 WM8996_POWER_MANAGEMENT_6
, 1, 0),
1136 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1137 WM8996_POWER_MANAGEMENT_6
, 0, 0),
1139 /* We route as stereo pairs so define some dummy widgets to squash
1140 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1141 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1142 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1143 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1144 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1145 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1147 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM
, 0, 0, &dsp1rx
),
1148 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM
, 0, 0, &dsp2rx
),
1149 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM
, 0, 0, &aif2tx
),
1151 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM
, 0, 0, &spkl_mux
),
1152 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM
, 0, 0, &spkr_mux
),
1153 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER
, 4, 0, NULL
, 0),
1154 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER
, 4, 0, NULL
, 0),
1156 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1
, 7, 0, NULL
, 0),
1157 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2
, 5, 0, NULL
, 0),
1158 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1
, 2, 0, dcs_start
,
1159 SND_SOC_DAPM_POST_PMU
),
1160 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2
, 6, 0, NULL
, 0),
1161 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM
, HPOUT2L
, 0,
1163 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_PRE_PMD
),
1165 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1
, 6, 0,NULL
, 0),
1166 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2
, 1, 0, NULL
, 0),
1167 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1
, 3, 0, dcs_start
,
1168 SND_SOC_DAPM_POST_PMU
),
1169 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2
, 2, 0, NULL
, 0),
1170 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM
, HPOUT2R
, 0,
1172 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_PRE_PMD
),
1174 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1
, 5, 0, NULL
, 0),
1175 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1
, 5, 0, NULL
, 0),
1176 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1
, 0, 0, dcs_start
,
1177 SND_SOC_DAPM_POST_PMU
),
1178 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1
, 6, 0, NULL
, 0),
1179 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM
, HPOUT1L
, 0,
1181 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_PRE_PMD
),
1183 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1
, 4, 0, NULL
, 0),
1184 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1
, 1, 0, NULL
, 0),
1185 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1
, 1, 0, dcs_start
,
1186 SND_SOC_DAPM_POST_PMU
),
1187 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1
, 2, 0, NULL
, 0),
1188 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM
, HPOUT1R
, 0,
1190 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_PRE_PMD
),
1192 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1193 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1194 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1195 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1196 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1199 static const struct snd_soc_dapm_route wm8996_dapm_routes
[] = {
1200 { "AIFCLK", NULL
, "SYSCLK" },
1201 { "SYSDSPCLK", NULL
, "SYSCLK" },
1202 { "Charge Pump", NULL
, "SYSCLK" },
1204 { "MICB1", NULL
, "LDO2" },
1205 { "MICB1", NULL
, "MICB1 Audio" },
1206 { "MICB1", NULL
, "Bandgap" },
1207 { "MICB2", NULL
, "LDO2" },
1208 { "MICB2", NULL
, "MICB2 Audio" },
1209 { "MICB2", NULL
, "Bandgap" },
1211 { "IN1L PGA", NULL
, "IN2LN" },
1212 { "IN1L PGA", NULL
, "IN2LP" },
1213 { "IN1L PGA", NULL
, "IN1LN" },
1214 { "IN1L PGA", NULL
, "IN1LP" },
1215 { "IN1L PGA", NULL
, "Bandgap" },
1217 { "IN1R PGA", NULL
, "IN2RN" },
1218 { "IN1R PGA", NULL
, "IN2RP" },
1219 { "IN1R PGA", NULL
, "IN1RN" },
1220 { "IN1R PGA", NULL
, "IN1RP" },
1221 { "IN1R PGA", NULL
, "Bandgap" },
1223 { "ADCL", NULL
, "IN1L PGA" },
1225 { "ADCR", NULL
, "IN1R PGA" },
1227 { "DMIC1L", NULL
, "DMIC1DAT" },
1228 { "DMIC1R", NULL
, "DMIC1DAT" },
1229 { "DMIC2L", NULL
, "DMIC2DAT" },
1230 { "DMIC2R", NULL
, "DMIC2DAT" },
1232 { "DMIC2L", NULL
, "DMIC2" },
1233 { "DMIC2R", NULL
, "DMIC2" },
1234 { "DMIC1L", NULL
, "DMIC1" },
1235 { "DMIC1R", NULL
, "DMIC1" },
1237 { "IN1L Mux", "ADC", "ADCL" },
1238 { "IN1L Mux", "DMIC1", "DMIC1L" },
1239 { "IN1L Mux", "DMIC2", "DMIC2L" },
1241 { "IN1R Mux", "ADC", "ADCR" },
1242 { "IN1R Mux", "DMIC1", "DMIC1R" },
1243 { "IN1R Mux", "DMIC2", "DMIC2R" },
1245 { "IN2L Mux", "ADC", "ADCL" },
1246 { "IN2L Mux", "DMIC1", "DMIC1L" },
1247 { "IN2L Mux", "DMIC2", "DMIC2L" },
1249 { "IN2R Mux", "ADC", "ADCR" },
1250 { "IN2R Mux", "DMIC1", "DMIC1R" },
1251 { "IN2R Mux", "DMIC2", "DMIC2R" },
1253 { "Left Sidetone", "IN1", "IN1L Mux" },
1254 { "Left Sidetone", "IN2", "IN2L Mux" },
1256 { "Right Sidetone", "IN1", "IN1R Mux" },
1257 { "Right Sidetone", "IN2", "IN2R Mux" },
1259 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1260 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1262 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1263 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1265 { "AIF1TX0", NULL
, "DSP1TXL" },
1266 { "AIF1TX1", NULL
, "DSP1TXR" },
1267 { "AIF1TX2", NULL
, "DSP2TXL" },
1268 { "AIF1TX3", NULL
, "DSP2TXR" },
1269 { "AIF1TX4", NULL
, "AIF2RX0" },
1270 { "AIF1TX5", NULL
, "AIF2RX1" },
1272 { "AIF1RX0", NULL
, "AIFCLK" },
1273 { "AIF1RX1", NULL
, "AIFCLK" },
1274 { "AIF1RX2", NULL
, "AIFCLK" },
1275 { "AIF1RX3", NULL
, "AIFCLK" },
1276 { "AIF1RX4", NULL
, "AIFCLK" },
1277 { "AIF1RX5", NULL
, "AIFCLK" },
1279 { "AIF2RX0", NULL
, "AIFCLK" },
1280 { "AIF2RX1", NULL
, "AIFCLK" },
1282 { "AIF1TX0", NULL
, "AIFCLK" },
1283 { "AIF1TX1", NULL
, "AIFCLK" },
1284 { "AIF1TX2", NULL
, "AIFCLK" },
1285 { "AIF1TX3", NULL
, "AIFCLK" },
1286 { "AIF1TX4", NULL
, "AIFCLK" },
1287 { "AIF1TX5", NULL
, "AIFCLK" },
1289 { "AIF2TX0", NULL
, "AIFCLK" },
1290 { "AIF2TX1", NULL
, "AIFCLK" },
1292 { "DSP1RXL", NULL
, "SYSDSPCLK" },
1293 { "DSP1RXR", NULL
, "SYSDSPCLK" },
1294 { "DSP2RXL", NULL
, "SYSDSPCLK" },
1295 { "DSP2RXR", NULL
, "SYSDSPCLK" },
1296 { "DSP1TXL", NULL
, "SYSDSPCLK" },
1297 { "DSP1TXR", NULL
, "SYSDSPCLK" },
1298 { "DSP2TXL", NULL
, "SYSDSPCLK" },
1299 { "DSP2TXR", NULL
, "SYSDSPCLK" },
1301 { "AIF1RXA", NULL
, "AIF1RX0" },
1302 { "AIF1RXA", NULL
, "AIF1RX1" },
1303 { "AIF1RXB", NULL
, "AIF1RX2" },
1304 { "AIF1RXB", NULL
, "AIF1RX3" },
1305 { "AIF1RXC", NULL
, "AIF1RX4" },
1306 { "AIF1RXC", NULL
, "AIF1RX5" },
1308 { "AIF2RX", NULL
, "AIF2RX0" },
1309 { "AIF2RX", NULL
, "AIF2RX1" },
1311 { "AIF2TX", "DSP2", "DSP2TX" },
1312 { "AIF2TX", "DSP1", "DSP1RX" },
1313 { "AIF2TX", "AIF1", "AIF1RXC" },
1315 { "DSP1RXL", NULL
, "DSP1RX" },
1316 { "DSP1RXR", NULL
, "DSP1RX" },
1317 { "DSP2RXL", NULL
, "DSP2RX" },
1318 { "DSP2RXR", NULL
, "DSP2RX" },
1320 { "DSP2TX", NULL
, "DSP2TXL" },
1321 { "DSP2TX", NULL
, "DSP2TXR" },
1323 { "DSP1RX", "AIF1", "AIF1RXA" },
1324 { "DSP1RX", "AIF2", "AIF2RX" },
1326 { "DSP2RX", "AIF1", "AIF1RXB" },
1327 { "DSP2RX", "AIF2", "AIF2RX" },
1329 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1330 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1331 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1332 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1334 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1335 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1336 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1337 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1339 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1340 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1341 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1342 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1344 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1345 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1346 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1347 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1349 { "DAC1L", NULL
, "DAC1L Mixer" },
1350 { "DAC1R", NULL
, "DAC1R Mixer" },
1351 { "DAC2L", NULL
, "DAC2L Mixer" },
1352 { "DAC2R", NULL
, "DAC2R Mixer" },
1354 { "HPOUT2L PGA", NULL
, "Charge Pump" },
1355 { "HPOUT2L PGA", NULL
, "Bandgap" },
1356 { "HPOUT2L PGA", NULL
, "DAC2L" },
1357 { "HPOUT2L_DLY", NULL
, "HPOUT2L PGA" },
1358 { "HPOUT2L_DCS", NULL
, "HPOUT2L_DLY" },
1359 { "HPOUT2L_OUTP", NULL
, "HPOUT2L_DCS" },
1360 { "HPOUT2L_RMV_SHORT", NULL
, "HPOUT2L_OUTP" },
1362 { "HPOUT2R PGA", NULL
, "Charge Pump" },
1363 { "HPOUT2R PGA", NULL
, "Bandgap" },
1364 { "HPOUT2R PGA", NULL
, "DAC2R" },
1365 { "HPOUT2R_DLY", NULL
, "HPOUT2R PGA" },
1366 { "HPOUT2R_DCS", NULL
, "HPOUT2R_DLY" },
1367 { "HPOUT2R_OUTP", NULL
, "HPOUT2R_DCS" },
1368 { "HPOUT2R_RMV_SHORT", NULL
, "HPOUT2R_OUTP" },
1370 { "HPOUT1L PGA", NULL
, "Charge Pump" },
1371 { "HPOUT1L PGA", NULL
, "Bandgap" },
1372 { "HPOUT1L PGA", NULL
, "DAC1L" },
1373 { "HPOUT1L_DLY", NULL
, "HPOUT1L PGA" },
1374 { "HPOUT1L_DCS", NULL
, "HPOUT1L_DLY" },
1375 { "HPOUT1L_OUTP", NULL
, "HPOUT1L_DCS" },
1376 { "HPOUT1L_RMV_SHORT", NULL
, "HPOUT1L_OUTP" },
1378 { "HPOUT1R PGA", NULL
, "Charge Pump" },
1379 { "HPOUT1R PGA", NULL
, "Bandgap" },
1380 { "HPOUT1R PGA", NULL
, "DAC1R" },
1381 { "HPOUT1R_DLY", NULL
, "HPOUT1R PGA" },
1382 { "HPOUT1R_DCS", NULL
, "HPOUT1R_DLY" },
1383 { "HPOUT1R_OUTP", NULL
, "HPOUT1R_DCS" },
1384 { "HPOUT1R_RMV_SHORT", NULL
, "HPOUT1R_OUTP" },
1386 { "HPOUT2L", NULL
, "HPOUT2L_RMV_SHORT" },
1387 { "HPOUT2R", NULL
, "HPOUT2R_RMV_SHORT" },
1388 { "HPOUT1L", NULL
, "HPOUT1L_RMV_SHORT" },
1389 { "HPOUT1R", NULL
, "HPOUT1R_RMV_SHORT" },
1391 { "SPKL", "DAC1L", "DAC1L" },
1392 { "SPKL", "DAC1R", "DAC1R" },
1393 { "SPKL", "DAC2L", "DAC2L" },
1394 { "SPKL", "DAC2R", "DAC2R" },
1396 { "SPKR", "DAC1L", "DAC1L" },
1397 { "SPKR", "DAC1R", "DAC1R" },
1398 { "SPKR", "DAC2L", "DAC2L" },
1399 { "SPKR", "DAC2R", "DAC2R" },
1401 { "SPKL PGA", NULL
, "SPKL" },
1402 { "SPKR PGA", NULL
, "SPKR" },
1404 { "SPKDAT", NULL
, "SPKL PGA" },
1405 { "SPKDAT", NULL
, "SPKR PGA" },
1408 static int wm8996_readable_register(struct snd_soc_codec
*codec
,
1411 /* Due to the sparseness of the register map the compiler
1412 * output from an explicit switch statement ends up being much
1413 * more efficient than a table.
1416 case WM8996_SOFTWARE_RESET
:
1417 case WM8996_POWER_MANAGEMENT_1
:
1418 case WM8996_POWER_MANAGEMENT_2
:
1419 case WM8996_POWER_MANAGEMENT_3
:
1420 case WM8996_POWER_MANAGEMENT_4
:
1421 case WM8996_POWER_MANAGEMENT_5
:
1422 case WM8996_POWER_MANAGEMENT_6
:
1423 case WM8996_POWER_MANAGEMENT_7
:
1424 case WM8996_POWER_MANAGEMENT_8
:
1425 case WM8996_LEFT_LINE_INPUT_VOLUME
:
1426 case WM8996_RIGHT_LINE_INPUT_VOLUME
:
1427 case WM8996_LINE_INPUT_CONTROL
:
1428 case WM8996_DAC1_HPOUT1_VOLUME
:
1429 case WM8996_DAC2_HPOUT2_VOLUME
:
1430 case WM8996_DAC1_LEFT_VOLUME
:
1431 case WM8996_DAC1_RIGHT_VOLUME
:
1432 case WM8996_DAC2_LEFT_VOLUME
:
1433 case WM8996_DAC2_RIGHT_VOLUME
:
1434 case WM8996_OUTPUT1_LEFT_VOLUME
:
1435 case WM8996_OUTPUT1_RIGHT_VOLUME
:
1436 case WM8996_OUTPUT2_LEFT_VOLUME
:
1437 case WM8996_OUTPUT2_RIGHT_VOLUME
:
1438 case WM8996_MICBIAS_1
:
1439 case WM8996_MICBIAS_2
:
1442 case WM8996_ACCESSORY_DETECT_MODE_1
:
1443 case WM8996_ACCESSORY_DETECT_MODE_2
:
1444 case WM8996_HEADPHONE_DETECT_1
:
1445 case WM8996_HEADPHONE_DETECT_2
:
1446 case WM8996_MIC_DETECT_1
:
1447 case WM8996_MIC_DETECT_2
:
1448 case WM8996_MIC_DETECT_3
:
1449 case WM8996_CHARGE_PUMP_1
:
1450 case WM8996_CHARGE_PUMP_2
:
1451 case WM8996_DC_SERVO_1
:
1452 case WM8996_DC_SERVO_2
:
1453 case WM8996_DC_SERVO_3
:
1454 case WM8996_DC_SERVO_5
:
1455 case WM8996_DC_SERVO_6
:
1456 case WM8996_DC_SERVO_7
:
1457 case WM8996_DC_SERVO_READBACK_0
:
1458 case WM8996_ANALOGUE_HP_1
:
1459 case WM8996_ANALOGUE_HP_2
:
1460 case WM8996_CHIP_REVISION
:
1461 case WM8996_CONTROL_INTERFACE_1
:
1462 case WM8996_WRITE_SEQUENCER_CTRL_1
:
1463 case WM8996_WRITE_SEQUENCER_CTRL_2
:
1464 case WM8996_AIF_CLOCKING_1
:
1465 case WM8996_AIF_CLOCKING_2
:
1466 case WM8996_CLOCKING_1
:
1467 case WM8996_CLOCKING_2
:
1468 case WM8996_AIF_RATE
:
1469 case WM8996_FLL_CONTROL_1
:
1470 case WM8996_FLL_CONTROL_2
:
1471 case WM8996_FLL_CONTROL_3
:
1472 case WM8996_FLL_CONTROL_4
:
1473 case WM8996_FLL_CONTROL_5
:
1474 case WM8996_FLL_CONTROL_6
:
1475 case WM8996_FLL_EFS_1
:
1476 case WM8996_FLL_EFS_2
:
1477 case WM8996_AIF1_CONTROL
:
1478 case WM8996_AIF1_BCLK
:
1479 case WM8996_AIF1_TX_LRCLK_1
:
1480 case WM8996_AIF1_TX_LRCLK_2
:
1481 case WM8996_AIF1_RX_LRCLK_1
:
1482 case WM8996_AIF1_RX_LRCLK_2
:
1483 case WM8996_AIF1TX_DATA_CONFIGURATION_1
:
1484 case WM8996_AIF1TX_DATA_CONFIGURATION_2
:
1485 case WM8996_AIF1RX_DATA_CONFIGURATION
:
1486 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION
:
1487 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION
:
1488 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION
:
1489 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION
:
1490 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION
:
1491 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION
:
1492 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION
:
1493 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION
:
1494 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION
:
1495 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION
:
1496 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION
:
1497 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION
:
1498 case WM8996_AIF1RX_MONO_CONFIGURATION
:
1499 case WM8996_AIF1TX_TEST
:
1500 case WM8996_AIF2_CONTROL
:
1501 case WM8996_AIF2_BCLK
:
1502 case WM8996_AIF2_TX_LRCLK_1
:
1503 case WM8996_AIF2_TX_LRCLK_2
:
1504 case WM8996_AIF2_RX_LRCLK_1
:
1505 case WM8996_AIF2_RX_LRCLK_2
:
1506 case WM8996_AIF2TX_DATA_CONFIGURATION_1
:
1507 case WM8996_AIF2TX_DATA_CONFIGURATION_2
:
1508 case WM8996_AIF2RX_DATA_CONFIGURATION
:
1509 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION
:
1510 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION
:
1511 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION
:
1512 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION
:
1513 case WM8996_AIF2RX_MONO_CONFIGURATION
:
1514 case WM8996_AIF2TX_TEST
:
1515 case WM8996_DSP1_TX_LEFT_VOLUME
:
1516 case WM8996_DSP1_TX_RIGHT_VOLUME
:
1517 case WM8996_DSP1_RX_LEFT_VOLUME
:
1518 case WM8996_DSP1_RX_RIGHT_VOLUME
:
1519 case WM8996_DSP1_TX_FILTERS
:
1520 case WM8996_DSP1_RX_FILTERS_1
:
1521 case WM8996_DSP1_RX_FILTERS_2
:
1522 case WM8996_DSP1_DRC_1
:
1523 case WM8996_DSP1_DRC_2
:
1524 case WM8996_DSP1_DRC_3
:
1525 case WM8996_DSP1_DRC_4
:
1526 case WM8996_DSP1_DRC_5
:
1527 case WM8996_DSP1_RX_EQ_GAINS_1
:
1528 case WM8996_DSP1_RX_EQ_GAINS_2
:
1529 case WM8996_DSP1_RX_EQ_BAND_1_A
:
1530 case WM8996_DSP1_RX_EQ_BAND_1_B
:
1531 case WM8996_DSP1_RX_EQ_BAND_1_PG
:
1532 case WM8996_DSP1_RX_EQ_BAND_2_A
:
1533 case WM8996_DSP1_RX_EQ_BAND_2_B
:
1534 case WM8996_DSP1_RX_EQ_BAND_2_C
:
1535 case WM8996_DSP1_RX_EQ_BAND_2_PG
:
1536 case WM8996_DSP1_RX_EQ_BAND_3_A
:
1537 case WM8996_DSP1_RX_EQ_BAND_3_B
:
1538 case WM8996_DSP1_RX_EQ_BAND_3_C
:
1539 case WM8996_DSP1_RX_EQ_BAND_3_PG
:
1540 case WM8996_DSP1_RX_EQ_BAND_4_A
:
1541 case WM8996_DSP1_RX_EQ_BAND_4_B
:
1542 case WM8996_DSP1_RX_EQ_BAND_4_C
:
1543 case WM8996_DSP1_RX_EQ_BAND_4_PG
:
1544 case WM8996_DSP1_RX_EQ_BAND_5_A
:
1545 case WM8996_DSP1_RX_EQ_BAND_5_B
:
1546 case WM8996_DSP1_RX_EQ_BAND_5_PG
:
1547 case WM8996_DSP2_TX_LEFT_VOLUME
:
1548 case WM8996_DSP2_TX_RIGHT_VOLUME
:
1549 case WM8996_DSP2_RX_LEFT_VOLUME
:
1550 case WM8996_DSP2_RX_RIGHT_VOLUME
:
1551 case WM8996_DSP2_TX_FILTERS
:
1552 case WM8996_DSP2_RX_FILTERS_1
:
1553 case WM8996_DSP2_RX_FILTERS_2
:
1554 case WM8996_DSP2_DRC_1
:
1555 case WM8996_DSP2_DRC_2
:
1556 case WM8996_DSP2_DRC_3
:
1557 case WM8996_DSP2_DRC_4
:
1558 case WM8996_DSP2_DRC_5
:
1559 case WM8996_DSP2_RX_EQ_GAINS_1
:
1560 case WM8996_DSP2_RX_EQ_GAINS_2
:
1561 case WM8996_DSP2_RX_EQ_BAND_1_A
:
1562 case WM8996_DSP2_RX_EQ_BAND_1_B
:
1563 case WM8996_DSP2_RX_EQ_BAND_1_PG
:
1564 case WM8996_DSP2_RX_EQ_BAND_2_A
:
1565 case WM8996_DSP2_RX_EQ_BAND_2_B
:
1566 case WM8996_DSP2_RX_EQ_BAND_2_C
:
1567 case WM8996_DSP2_RX_EQ_BAND_2_PG
:
1568 case WM8996_DSP2_RX_EQ_BAND_3_A
:
1569 case WM8996_DSP2_RX_EQ_BAND_3_B
:
1570 case WM8996_DSP2_RX_EQ_BAND_3_C
:
1571 case WM8996_DSP2_RX_EQ_BAND_3_PG
:
1572 case WM8996_DSP2_RX_EQ_BAND_4_A
:
1573 case WM8996_DSP2_RX_EQ_BAND_4_B
:
1574 case WM8996_DSP2_RX_EQ_BAND_4_C
:
1575 case WM8996_DSP2_RX_EQ_BAND_4_PG
:
1576 case WM8996_DSP2_RX_EQ_BAND_5_A
:
1577 case WM8996_DSP2_RX_EQ_BAND_5_B
:
1578 case WM8996_DSP2_RX_EQ_BAND_5_PG
:
1579 case WM8996_DAC1_MIXER_VOLUMES
:
1580 case WM8996_DAC1_LEFT_MIXER_ROUTING
:
1581 case WM8996_DAC1_RIGHT_MIXER_ROUTING
:
1582 case WM8996_DAC2_MIXER_VOLUMES
:
1583 case WM8996_DAC2_LEFT_MIXER_ROUTING
:
1584 case WM8996_DAC2_RIGHT_MIXER_ROUTING
:
1585 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING
:
1586 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING
:
1587 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING
:
1588 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING
:
1589 case WM8996_DSP_TX_MIXER_SELECT
:
1590 case WM8996_DAC_SOFTMUTE
:
1591 case WM8996_OVERSAMPLING
:
1592 case WM8996_SIDETONE
:
1598 case WM8996_PULL_CONTROL_1
:
1599 case WM8996_PULL_CONTROL_2
:
1600 case WM8996_INTERRUPT_STATUS_1
:
1601 case WM8996_INTERRUPT_STATUS_2
:
1602 case WM8996_INTERRUPT_RAW_STATUS_2
:
1603 case WM8996_INTERRUPT_STATUS_1_MASK
:
1604 case WM8996_INTERRUPT_STATUS_2_MASK
:
1605 case WM8996_INTERRUPT_CONTROL
:
1606 case WM8996_LEFT_PDM_SPEAKER
:
1607 case WM8996_RIGHT_PDM_SPEAKER
:
1608 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE
:
1609 case WM8996_PDM_SPEAKER_VOLUME
:
1616 static int wm8996_volatile_register(struct snd_soc_codec
*codec
,
1620 case WM8996_SOFTWARE_RESET
:
1621 case WM8996_CHIP_REVISION
:
1624 case WM8996_INTERRUPT_STATUS_1
:
1625 case WM8996_INTERRUPT_STATUS_2
:
1626 case WM8996_INTERRUPT_RAW_STATUS_2
:
1627 case WM8996_DC_SERVO_READBACK_0
:
1628 case WM8996_DC_SERVO_2
:
1629 case WM8996_DC_SERVO_6
:
1630 case WM8996_DC_SERVO_7
:
1631 case WM8996_FLL_CONTROL_6
:
1632 case WM8996_MIC_DETECT_3
:
1633 case WM8996_HEADPHONE_DETECT_1
:
1634 case WM8996_HEADPHONE_DETECT_2
:
1641 static int wm8996_reset(struct snd_soc_codec
*codec
)
1643 return snd_soc_write(codec
, WM8996_SOFTWARE_RESET
, 0x8915);
1646 static const int bclk_divs
[] = {
1647 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1650 static void wm8996_update_bclk(struct snd_soc_codec
*codec
)
1652 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
1653 int aif
, best
, cur_val
, bclk_rate
, bclk_reg
, i
;
1655 /* Don't bother if we're in a low frequency idle mode that
1656 * can't support audio.
1658 if (wm8996
->sysclk
< 64000)
1661 for (aif
= 0; aif
< WM8996_AIFS
; aif
++) {
1664 bclk_reg
= WM8996_AIF1_BCLK
;
1667 bclk_reg
= WM8996_AIF2_BCLK
;
1671 bclk_rate
= wm8996
->bclk_rate
[aif
];
1673 /* Pick a divisor for BCLK as close as we can get to ideal */
1675 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1676 cur_val
= (wm8996
->sysclk
/ bclk_divs
[i
]) - bclk_rate
;
1677 if (cur_val
< 0) /* BCLK table is sorted */
1681 bclk_rate
= wm8996
->sysclk
/ bclk_divs
[best
];
1682 dev_dbg(codec
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1683 bclk_divs
[best
], bclk_rate
);
1685 snd_soc_update_bits(codec
, bclk_reg
,
1686 WM8996_AIF1_BCLK_DIV_MASK
, best
);
1690 static int wm8996_set_bias_level(struct snd_soc_codec
*codec
,
1691 enum snd_soc_bias_level level
)
1693 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
1697 case SND_SOC_BIAS_ON
:
1698 case SND_SOC_BIAS_PREPARE
:
1701 case SND_SOC_BIAS_STANDBY
:
1702 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1703 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8996
->supplies
),
1707 "Failed to enable supplies: %d\n",
1712 if (wm8996
->pdata
.ldo_ena
>= 0) {
1713 gpio_set_value_cansleep(wm8996
->pdata
.ldo_ena
,
1718 codec
->cache_only
= false;
1719 snd_soc_cache_sync(codec
);
1723 case SND_SOC_BIAS_OFF
:
1724 codec
->cache_only
= true;
1725 if (wm8996
->pdata
.ldo_ena
>= 0)
1726 gpio_set_value_cansleep(wm8996
->pdata
.ldo_ena
, 0);
1727 regulator_bulk_disable(ARRAY_SIZE(wm8996
->supplies
),
1732 codec
->dapm
.bias_level
= level
;
1737 static int wm8996_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1739 struct snd_soc_codec
*codec
= dai
->codec
;
1744 int aifctrl_reg
, bclk_reg
, lrclk_tx_reg
, lrclk_rx_reg
;
1748 aifctrl_reg
= WM8996_AIF1_CONTROL
;
1749 bclk_reg
= WM8996_AIF1_BCLK
;
1750 lrclk_tx_reg
= WM8996_AIF1_TX_LRCLK_2
;
1751 lrclk_rx_reg
= WM8996_AIF1_RX_LRCLK_2
;
1754 aifctrl_reg
= WM8996_AIF2_CONTROL
;
1755 bclk_reg
= WM8996_AIF2_BCLK
;
1756 lrclk_tx_reg
= WM8996_AIF2_TX_LRCLK_2
;
1757 lrclk_rx_reg
= WM8996_AIF2_RX_LRCLK_2
;
1764 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1765 case SND_SOC_DAIFMT_NB_NF
:
1767 case SND_SOC_DAIFMT_IB_NF
:
1768 bclk
|= WM8996_AIF1_BCLK_INV
;
1770 case SND_SOC_DAIFMT_NB_IF
:
1771 lrclk_tx
|= WM8996_AIF1TX_LRCLK_INV
;
1772 lrclk_rx
|= WM8996_AIF1RX_LRCLK_INV
;
1774 case SND_SOC_DAIFMT_IB_IF
:
1775 bclk
|= WM8996_AIF1_BCLK_INV
;
1776 lrclk_tx
|= WM8996_AIF1TX_LRCLK_INV
;
1777 lrclk_rx
|= WM8996_AIF1RX_LRCLK_INV
;
1781 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1782 case SND_SOC_DAIFMT_CBS_CFS
:
1784 case SND_SOC_DAIFMT_CBS_CFM
:
1785 lrclk_tx
|= WM8996_AIF1TX_LRCLK_MSTR
;
1786 lrclk_rx
|= WM8996_AIF1RX_LRCLK_MSTR
;
1788 case SND_SOC_DAIFMT_CBM_CFS
:
1789 bclk
|= WM8996_AIF1_BCLK_MSTR
;
1791 case SND_SOC_DAIFMT_CBM_CFM
:
1792 bclk
|= WM8996_AIF1_BCLK_MSTR
;
1793 lrclk_tx
|= WM8996_AIF1TX_LRCLK_MSTR
;
1794 lrclk_rx
|= WM8996_AIF1RX_LRCLK_MSTR
;
1800 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1801 case SND_SOC_DAIFMT_DSP_A
:
1803 case SND_SOC_DAIFMT_DSP_B
:
1806 case SND_SOC_DAIFMT_I2S
:
1809 case SND_SOC_DAIFMT_LEFT_J
:
1816 snd_soc_update_bits(codec
, aifctrl_reg
, WM8996_AIF1_FMT_MASK
, aifctrl
);
1817 snd_soc_update_bits(codec
, bclk_reg
,
1818 WM8996_AIF1_BCLK_INV
| WM8996_AIF1_BCLK_MSTR
,
1820 snd_soc_update_bits(codec
, lrclk_tx_reg
,
1821 WM8996_AIF1TX_LRCLK_INV
|
1822 WM8996_AIF1TX_LRCLK_MSTR
,
1824 snd_soc_update_bits(codec
, lrclk_rx_reg
,
1825 WM8996_AIF1RX_LRCLK_INV
|
1826 WM8996_AIF1RX_LRCLK_MSTR
,
1832 static const int dsp_divs
[] = {
1833 48000, 32000, 16000, 8000
1836 static int wm8996_hw_params(struct snd_pcm_substream
*substream
,
1837 struct snd_pcm_hw_params
*params
,
1838 struct snd_soc_dai
*dai
)
1840 struct snd_soc_codec
*codec
= dai
->codec
;
1841 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
1842 int bits
, i
, bclk_rate
;
1846 int aifdata_reg
, lrclk_reg
, dsp_shift
;
1850 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
1851 (snd_soc_read(codec
, WM8996_GPIO_1
)) & WM8996_GP1_FN_MASK
) {
1852 aifdata_reg
= WM8996_AIF1RX_DATA_CONFIGURATION
;
1853 lrclk_reg
= WM8996_AIF1_RX_LRCLK_1
;
1855 aifdata_reg
= WM8996_AIF1TX_DATA_CONFIGURATION_1
;
1856 lrclk_reg
= WM8996_AIF1_TX_LRCLK_1
;
1861 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
1862 (snd_soc_read(codec
, WM8996_GPIO_2
)) & WM8996_GP2_FN_MASK
) {
1863 aifdata_reg
= WM8996_AIF2RX_DATA_CONFIGURATION
;
1864 lrclk_reg
= WM8996_AIF2_RX_LRCLK_1
;
1866 aifdata_reg
= WM8996_AIF2TX_DATA_CONFIGURATION_1
;
1867 lrclk_reg
= WM8996_AIF2_TX_LRCLK_1
;
1869 dsp_shift
= WM8996_DSP2_DIV_SHIFT
;
1876 bclk_rate
= snd_soc_params_to_bclk(params
);
1877 if (bclk_rate
< 0) {
1878 dev_err(codec
->dev
, "Unsupported BCLK rate: %d\n", bclk_rate
);
1882 wm8996
->bclk_rate
[dai
->id
] = bclk_rate
;
1883 wm8996
->rx_rate
[dai
->id
] = params_rate(params
);
1885 /* Needs looking at for TDM */
1886 bits
= snd_pcm_format_width(params_format(params
));
1889 aifdata
|= (bits
<< WM8996_AIF1TX_WL_SHIFT
) | bits
;
1891 for (i
= 0; i
< ARRAY_SIZE(dsp_divs
); i
++) {
1892 if (dsp_divs
[i
] == params_rate(params
))
1895 if (i
== ARRAY_SIZE(dsp_divs
)) {
1896 dev_err(codec
->dev
, "Unsupported sample rate %dHz\n",
1897 params_rate(params
));
1900 dsp
|= i
<< dsp_shift
;
1902 wm8996_update_bclk(codec
);
1904 lrclk
= bclk_rate
/ params_rate(params
);
1905 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1906 lrclk
, bclk_rate
/ lrclk
);
1908 snd_soc_update_bits(codec
, aifdata_reg
,
1909 WM8996_AIF1TX_WL_MASK
|
1910 WM8996_AIF1TX_SLOT_LEN_MASK
,
1912 snd_soc_update_bits(codec
, lrclk_reg
, WM8996_AIF1RX_RATE_MASK
,
1914 snd_soc_update_bits(codec
, WM8996_AIF_CLOCKING_2
,
1915 WM8996_DSP1_DIV_SHIFT
<< dsp_shift
, dsp
);
1920 static int wm8996_set_sysclk(struct snd_soc_dai
*dai
,
1921 int clk_id
, unsigned int freq
, int dir
)
1923 struct snd_soc_codec
*codec
= dai
->codec
;
1924 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
1930 if (freq
== wm8996
->sysclk
&& clk_id
== wm8996
->sysclk_src
)
1933 /* Disable SYSCLK while we reconfigure */
1934 old
= snd_soc_read(codec
, WM8996_AIF_CLOCKING_1
) & WM8996_SYSCLK_ENA
;
1935 snd_soc_update_bits(codec
, WM8996_AIF_CLOCKING_1
,
1936 WM8996_SYSCLK_ENA
, 0);
1939 case WM8996_SYSCLK_MCLK1
:
1940 wm8996
->sysclk
= freq
;
1943 case WM8996_SYSCLK_MCLK2
:
1944 wm8996
->sysclk
= freq
;
1947 case WM8996_SYSCLK_FLL
:
1948 wm8996
->sysclk
= freq
;
1952 dev_err(codec
->dev
, "Unsupported clock source %d\n", clk_id
);
1956 switch (wm8996
->sysclk
) {
1958 snd_soc_update_bits(codec
, WM8996_AIF_RATE
,
1959 WM8996_SYSCLK_RATE
, 0);
1962 ratediv
= WM8996_SYSCLK_DIV
;
1964 snd_soc_update_bits(codec
, WM8996_AIF_RATE
,
1965 WM8996_SYSCLK_RATE
, WM8996_SYSCLK_RATE
);
1969 lfclk
= WM8996_LFCLK_ENA
;
1972 dev_warn(codec
->dev
, "Unsupported clock rate %dHz\n",
1977 wm8996_update_bclk(codec
);
1979 snd_soc_update_bits(codec
, WM8996_AIF_CLOCKING_1
,
1980 WM8996_SYSCLK_SRC_MASK
| WM8996_SYSCLK_DIV_MASK
,
1981 src
<< WM8996_SYSCLK_SRC_SHIFT
| ratediv
);
1982 snd_soc_update_bits(codec
, WM8996_CLOCKING_1
, WM8996_LFCLK_ENA
, lfclk
);
1983 snd_soc_update_bits(codec
, WM8996_AIF_CLOCKING_1
,
1984 WM8996_SYSCLK_ENA
, old
);
1986 wm8996
->sysclk_src
= clk_id
;
2008 { 0, 64000, 4, 16 },
2009 { 64000, 128000, 3, 8 },
2010 { 128000, 256000, 2, 4 },
2011 { 256000, 1000000, 1, 2 },
2012 { 1000000, 13500000, 0, 1 },
2015 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
2018 unsigned int target
;
2020 unsigned int fratio
, gcd_fll
;
2023 /* Fref must be <=13.5MHz */
2025 fll_div
->fll_refclk_div
= 0;
2026 while ((Fref
/ div
) > 13500000) {
2028 fll_div
->fll_refclk_div
++;
2031 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2037 pr_debug("FLL Fref=%u Fout=%u\n", Fref
, Fout
);
2039 /* Apply the division for our remaining calculations */
2042 if (Fref
>= 3000000)
2043 fll_div
->fll_loop_gain
= 5;
2045 fll_div
->fll_loop_gain
= 0;
2048 fll_div
->fll_ref_freq
= 0;
2050 fll_div
->fll_ref_freq
= 1;
2052 /* Fvco should be 90-100MHz; don't check the upper bound */
2054 while (Fout
* div
< 90000000) {
2057 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2062 target
= Fout
* div
;
2063 fll_div
->fll_outdiv
= div
- 1;
2065 pr_debug("FLL Fvco=%dHz\n", target
);
2067 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2068 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
2069 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
2070 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
2071 fratio
= fll_fratios
[i
].ratio
;
2075 if (i
== ARRAY_SIZE(fll_fratios
)) {
2076 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
2080 fll_div
->n
= target
/ (fratio
* Fref
);
2082 if (target
% Fref
== 0) {
2084 fll_div
->lambda
= 0;
2086 gcd_fll
= gcd(target
, fratio
* Fref
);
2088 fll_div
->theta
= (target
- (fll_div
->n
* fratio
* Fref
))
2090 fll_div
->lambda
= (fratio
* Fref
) / gcd_fll
;
2093 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2094 fll_div
->n
, fll_div
->theta
, fll_div
->lambda
);
2095 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2096 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
2097 fll_div
->fll_refclk_div
);
2102 static int wm8996_set_fll(struct snd_soc_codec
*codec
, int fll_id
, int source
,
2103 unsigned int Fref
, unsigned int Fout
)
2105 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2106 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
2107 struct _fll_div fll_div
;
2108 unsigned long timeout
;
2109 int ret
, reg
, retry
;
2112 if (source
== wm8996
->fll_src
&& Fref
== wm8996
->fll_fref
&&
2113 Fout
== wm8996
->fll_fout
)
2117 dev_dbg(codec
->dev
, "FLL disabled\n");
2119 wm8996
->fll_fref
= 0;
2120 wm8996
->fll_fout
= 0;
2122 snd_soc_update_bits(codec
, WM8996_FLL_CONTROL_1
,
2125 wm8996_bg_disable(codec
);
2130 ret
= fll_factors(&fll_div
, Fref
, Fout
);
2135 case WM8996_FLL_MCLK1
:
2138 case WM8996_FLL_MCLK2
:
2141 case WM8996_FLL_DACLRCLK1
:
2144 case WM8996_FLL_BCLK1
:
2148 dev_err(codec
->dev
, "Unknown FLL source %d\n", ret
);
2152 reg
|= fll_div
.fll_refclk_div
<< WM8996_FLL_REFCLK_DIV_SHIFT
;
2153 reg
|= fll_div
.fll_ref_freq
<< WM8996_FLL_REF_FREQ_SHIFT
;
2155 snd_soc_update_bits(codec
, WM8996_FLL_CONTROL_5
,
2156 WM8996_FLL_REFCLK_DIV_MASK
| WM8996_FLL_REF_FREQ
|
2157 WM8996_FLL_REFCLK_SRC_MASK
, reg
);
2160 if (fll_div
.theta
|| fll_div
.lambda
)
2161 reg
|= WM8996_FLL_EFS_ENA
| (3 << WM8996_FLL_LFSR_SEL_SHIFT
);
2163 reg
|= 1 << WM8996_FLL_LFSR_SEL_SHIFT
;
2164 snd_soc_write(codec
, WM8996_FLL_EFS_2
, reg
);
2166 snd_soc_update_bits(codec
, WM8996_FLL_CONTROL_2
,
2167 WM8996_FLL_OUTDIV_MASK
|
2168 WM8996_FLL_FRATIO_MASK
,
2169 (fll_div
.fll_outdiv
<< WM8996_FLL_OUTDIV_SHIFT
) |
2170 (fll_div
.fll_fratio
));
2172 snd_soc_write(codec
, WM8996_FLL_CONTROL_3
, fll_div
.theta
);
2174 snd_soc_update_bits(codec
, WM8996_FLL_CONTROL_4
,
2175 WM8996_FLL_N_MASK
| WM8996_FLL_LOOP_GAIN_MASK
,
2176 (fll_div
.n
<< WM8996_FLL_N_SHIFT
) |
2177 fll_div
.fll_loop_gain
);
2179 snd_soc_write(codec
, WM8996_FLL_EFS_1
, fll_div
.lambda
);
2181 /* Enable the bandgap if it's not already enabled */
2182 ret
= snd_soc_read(codec
, WM8996_FLL_CONTROL_1
);
2183 if (!(ret
& WM8996_FLL_ENA
))
2184 wm8996_bg_enable(codec
);
2186 /* Clear any pending completions (eg, from failed startups) */
2187 try_wait_for_completion(&wm8996
->fll_lock
);
2189 snd_soc_update_bits(codec
, WM8996_FLL_CONTROL_1
,
2190 WM8996_FLL_ENA
, WM8996_FLL_ENA
);
2192 /* The FLL supports live reconfiguration - kick that in case we were
2195 snd_soc_write(codec
, WM8996_FLL_CONTROL_6
, WM8996_FLL_SWITCH_CLK
);
2197 /* Wait for the FLL to lock, using the interrupt if possible */
2199 timeout
= usecs_to_jiffies(300);
2201 timeout
= msecs_to_jiffies(2);
2203 /* Allow substantially longer if we've actually got the IRQ, poll
2204 * at a slightly higher rate if we don't.
2211 for (retry
= 0; retry
< 10; retry
++) {
2212 ret
= wait_for_completion_timeout(&wm8996
->fll_lock
,
2219 ret
= snd_soc_read(codec
, WM8996_INTERRUPT_RAW_STATUS_2
);
2220 if (ret
& WM8996_FLL_LOCK_STS
)
2224 dev_err(codec
->dev
, "Timed out waiting for FLL\n");
2228 dev_dbg(codec
->dev
, "FLL configured for %dHz->%dHz\n", Fref
, Fout
);
2230 wm8996
->fll_fref
= Fref
;
2231 wm8996
->fll_fout
= Fout
;
2232 wm8996
->fll_src
= source
;
2237 #ifdef CONFIG_GPIOLIB
2238 static inline struct wm8996_priv
*gpio_to_wm8996(struct gpio_chip
*chip
)
2240 return container_of(chip
, struct wm8996_priv
, gpio_chip
);
2243 static void wm8996_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
2245 struct wm8996_priv
*wm8996
= gpio_to_wm8996(chip
);
2246 struct snd_soc_codec
*codec
= wm8996
->codec
;
2248 snd_soc_update_bits(codec
, WM8996_GPIO_1
+ offset
,
2249 WM8996_GP1_LVL
, !!value
<< WM8996_GP1_LVL_SHIFT
);
2252 static int wm8996_gpio_direction_out(struct gpio_chip
*chip
,
2253 unsigned offset
, int value
)
2255 struct wm8996_priv
*wm8996
= gpio_to_wm8996(chip
);
2256 struct snd_soc_codec
*codec
= wm8996
->codec
;
2259 val
= (1 << WM8996_GP1_FN_SHIFT
) | (!!value
<< WM8996_GP1_LVL_SHIFT
);
2261 return snd_soc_update_bits(codec
, WM8996_GPIO_1
+ offset
,
2262 WM8996_GP1_FN_MASK
| WM8996_GP1_DIR
|
2263 WM8996_GP1_LVL
, val
);
2266 static int wm8996_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
2268 struct wm8996_priv
*wm8996
= gpio_to_wm8996(chip
);
2269 struct snd_soc_codec
*codec
= wm8996
->codec
;
2272 ret
= snd_soc_read(codec
, WM8996_GPIO_1
+ offset
);
2276 return (ret
& WM8996_GP1_LVL
) != 0;
2279 static int wm8996_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
2281 struct wm8996_priv
*wm8996
= gpio_to_wm8996(chip
);
2282 struct snd_soc_codec
*codec
= wm8996
->codec
;
2284 return snd_soc_update_bits(codec
, WM8996_GPIO_1
+ offset
,
2285 WM8996_GP1_FN_MASK
| WM8996_GP1_DIR
,
2286 (1 << WM8996_GP1_FN_SHIFT
) |
2287 (1 << WM8996_GP1_DIR_SHIFT
));
2290 static struct gpio_chip wm8996_template_chip
= {
2292 .owner
= THIS_MODULE
,
2293 .direction_output
= wm8996_gpio_direction_out
,
2294 .set
= wm8996_gpio_set
,
2295 .direction_input
= wm8996_gpio_direction_in
,
2296 .get
= wm8996_gpio_get
,
2300 static void wm8996_init_gpio(struct snd_soc_codec
*codec
)
2302 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2305 wm8996
->gpio_chip
= wm8996_template_chip
;
2306 wm8996
->gpio_chip
.ngpio
= 5;
2307 wm8996
->gpio_chip
.dev
= codec
->dev
;
2309 if (wm8996
->pdata
.gpio_base
)
2310 wm8996
->gpio_chip
.base
= wm8996
->pdata
.gpio_base
;
2312 wm8996
->gpio_chip
.base
= -1;
2314 ret
= gpiochip_add(&wm8996
->gpio_chip
);
2316 dev_err(codec
->dev
, "Failed to add GPIOs: %d\n", ret
);
2319 static void wm8996_free_gpio(struct snd_soc_codec
*codec
)
2321 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2324 ret
= gpiochip_remove(&wm8996
->gpio_chip
);
2326 dev_err(codec
->dev
, "Failed to remove GPIOs: %d\n", ret
);
2329 static void wm8996_init_gpio(struct snd_soc_codec
*codec
)
2333 static void wm8996_free_gpio(struct snd_soc_codec
*codec
)
2339 * wm8996_detect - Enable default WM8996 jack detection
2341 * The WM8996 has advanced accessory detection support for headsets.
2342 * This function provides a default implementation which integrates
2343 * the majority of this functionality with minimal user configuration.
2345 * This will detect headset, headphone and short circuit button and
2346 * will also detect inverted microphone ground connections and update
2347 * the polarity of the connections.
2349 int wm8996_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2350 wm8996_polarity_fn polarity_cb
)
2352 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2354 wm8996
->jack
= jack
;
2355 wm8996
->detecting
= true;
2356 wm8996
->polarity_cb
= polarity_cb
;
2358 if (wm8996
->polarity_cb
)
2359 wm8996
->polarity_cb(codec
, 0);
2361 /* Clear discarge to avoid noise during detection */
2362 snd_soc_update_bits(codec
, WM8996_MICBIAS_1
,
2363 WM8996_MICB1_DISCH
, 0);
2364 snd_soc_update_bits(codec
, WM8996_MICBIAS_2
,
2365 WM8996_MICB2_DISCH
, 0);
2367 /* LDO2 powers the microphones, SYSCLK clocks detection */
2368 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "LDO2");
2369 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "SYSCLK");
2371 /* We start off just enabling microphone detection - even a
2372 * plain headphone will trigger detection.
2374 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
,
2375 WM8996_MICD_ENA
, WM8996_MICD_ENA
);
2377 /* Slowest detection rate, gives debounce for initial detection */
2378 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
,
2379 WM8996_MICD_RATE_MASK
,
2380 WM8996_MICD_RATE_MASK
);
2382 /* Enable interrupts and we're off */
2383 snd_soc_update_bits(codec
, WM8996_INTERRUPT_STATUS_2_MASK
,
2384 WM8996_IM_MICD_EINT
| WM8996_HP_DONE_EINT
, 0);
2388 EXPORT_SYMBOL_GPL(wm8996_detect
);
2390 static void wm8996_hpdet_irq(struct snd_soc_codec
*codec
)
2392 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2393 int val
, reg
, report
;
2395 /* Assume headphone in error conditions; we need to report
2396 * something or we stall our state machine.
2398 report
= SND_JACK_HEADPHONE
;
2400 reg
= snd_soc_read(codec
, WM8996_HEADPHONE_DETECT_2
);
2402 dev_err(codec
->dev
, "Failed to read HPDET status\n");
2406 if (!(reg
& WM8996_HP_DONE
)) {
2407 dev_err(codec
->dev
, "Got HPDET IRQ but HPDET is busy\n");
2411 val
= reg
& WM8996_HP_LVL_MASK
;
2413 dev_dbg(codec
->dev
, "HPDET measured %d ohms\n", val
);
2415 /* If we've got high enough impedence then report as line,
2416 * otherwise assume headphone.
2419 report
= SND_JACK_LINEOUT
;
2421 report
= SND_JACK_HEADPHONE
;
2424 if (wm8996
->jack_mic
)
2425 report
|= SND_JACK_MICROPHONE
;
2427 snd_soc_jack_report(wm8996
->jack
, report
,
2428 SND_JACK_LINEOUT
| SND_JACK_HEADSET
);
2430 wm8996
->detecting
= false;
2432 /* If the output isn't running re-clamp it */
2433 if (!(snd_soc_read(codec
, WM8996_POWER_MANAGEMENT_1
) &
2434 (WM8996_HPOUT1L_ENA
| WM8996_HPOUT1R_RMV_SHORT
)))
2435 snd_soc_update_bits(codec
, WM8996_ANALOGUE_HP_1
,
2436 WM8996_HPOUT1L_RMV_SHORT
|
2437 WM8996_HPOUT1R_RMV_SHORT
, 0);
2439 /* Go back to looking at the microphone */
2440 snd_soc_update_bits(codec
, WM8996_ACCESSORY_DETECT_MODE_1
,
2441 WM8996_JD_MODE_MASK
, 0);
2442 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
, WM8996_MICD_ENA
,
2445 snd_soc_dapm_disable_pin(&codec
->dapm
, "Bandgap");
2446 snd_soc_dapm_sync(&codec
->dapm
);
2449 static void wm8996_hpdet_start(struct snd_soc_codec
*codec
)
2451 /* Unclamp the output, we can't measure while we're shorting it */
2452 snd_soc_update_bits(codec
, WM8996_ANALOGUE_HP_1
,
2453 WM8996_HPOUT1L_RMV_SHORT
|
2454 WM8996_HPOUT1R_RMV_SHORT
,
2455 WM8996_HPOUT1L_RMV_SHORT
|
2456 WM8996_HPOUT1R_RMV_SHORT
);
2458 /* We need bandgap for HPDET */
2459 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "Bandgap");
2460 snd_soc_dapm_sync(&codec
->dapm
);
2462 /* Go into headphone detect left mode */
2463 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
, WM8996_MICD_ENA
, 0);
2464 snd_soc_update_bits(codec
, WM8996_ACCESSORY_DETECT_MODE_1
,
2465 WM8996_JD_MODE_MASK
, 1);
2467 /* Trigger a measurement */
2468 snd_soc_update_bits(codec
, WM8996_HEADPHONE_DETECT_1
,
2469 WM8996_HP_POLL
, WM8996_HP_POLL
);
2472 static void wm8996_micd(struct snd_soc_codec
*codec
)
2474 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2477 val
= snd_soc_read(codec
, WM8996_MIC_DETECT_3
);
2479 dev_dbg(codec
->dev
, "Microphone event: %x\n", val
);
2481 if (!(val
& WM8996_MICD_VALID
)) {
2482 dev_warn(codec
->dev
, "Microphone detection state invalid\n");
2486 /* No accessory, reset everything and report removal */
2487 if (!(val
& WM8996_MICD_STS
)) {
2488 dev_dbg(codec
->dev
, "Jack removal detected\n");
2489 wm8996
->jack_mic
= false;
2490 wm8996
->detecting
= true;
2491 snd_soc_jack_report(wm8996
->jack
, 0,
2492 SND_JACK_LINEOUT
| SND_JACK_HEADSET
|
2495 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
,
2496 WM8996_MICD_RATE_MASK
,
2497 WM8996_MICD_RATE_MASK
);
2501 /* If the measurement is very high we've got a microphone,
2502 * either we just detected one or if we already reported then
2503 * we've got a button release event.
2506 if (wm8996
->detecting
) {
2507 dev_dbg(codec
->dev
, "Microphone detected\n");
2508 wm8996
->jack_mic
= true;
2509 wm8996_hpdet_start(codec
);
2511 /* Increase poll rate to give better responsiveness
2513 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
,
2514 WM8996_MICD_RATE_MASK
,
2515 5 << WM8996_MICD_RATE_SHIFT
);
2517 dev_dbg(codec
->dev
, "Mic button up\n");
2518 snd_soc_jack_report(wm8996
->jack
, 0, SND_JACK_BTN_0
);
2524 /* If we detected a lower impedence during initial startup
2525 * then we probably have the wrong polarity, flip it. Don't
2526 * do this for the lowest impedences to speed up detection of
2529 if (wm8996
->detecting
&& (val
& 0x3f0)) {
2530 reg
= snd_soc_read(codec
, WM8996_ACCESSORY_DETECT_MODE_2
);
2531 reg
^= WM8996_HPOUT1FB_SRC
| WM8996_MICD_SRC
|
2532 WM8996_MICD_BIAS_SRC
;
2533 snd_soc_update_bits(codec
, WM8996_ACCESSORY_DETECT_MODE_2
,
2534 WM8996_HPOUT1FB_SRC
| WM8996_MICD_SRC
|
2535 WM8996_MICD_BIAS_SRC
, reg
);
2537 if (wm8996
->polarity_cb
)
2538 wm8996
->polarity_cb(codec
,
2539 (reg
& WM8996_MICD_SRC
) != 0);
2541 dev_dbg(codec
->dev
, "Set microphone polarity to %d\n",
2542 (reg
& WM8996_MICD_SRC
) != 0);
2547 /* Don't distinguish between buttons, just report any low
2548 * impedence as BTN_0.
2551 if (wm8996
->jack_mic
) {
2552 dev_dbg(codec
->dev
, "Mic button detected\n");
2553 snd_soc_jack_report(wm8996
->jack
, SND_JACK_BTN_0
,
2555 } else if (wm8996
->detecting
) {
2556 dev_dbg(codec
->dev
, "Headphone detected\n");
2557 wm8996_hpdet_start(codec
);
2559 /* Increase the detection rate a bit for
2562 snd_soc_update_bits(codec
, WM8996_MIC_DETECT_1
,
2563 WM8996_MICD_RATE_MASK
,
2564 7 << WM8996_MICD_RATE_SHIFT
);
2569 static irqreturn_t
wm8996_irq(int irq
, void *data
)
2571 struct snd_soc_codec
*codec
= data
;
2572 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2575 irq_val
= snd_soc_read(codec
, WM8996_INTERRUPT_STATUS_2
);
2577 dev_err(codec
->dev
, "Failed to read IRQ status: %d\n",
2581 irq_val
&= ~snd_soc_read(codec
, WM8996_INTERRUPT_STATUS_2_MASK
);
2586 snd_soc_write(codec
, WM8996_INTERRUPT_STATUS_2
, irq_val
);
2588 if (irq_val
& (WM8996_DCS_DONE_01_EINT
| WM8996_DCS_DONE_23_EINT
)) {
2589 dev_dbg(codec
->dev
, "DC servo IRQ\n");
2590 complete(&wm8996
->dcs_done
);
2593 if (irq_val
& WM8996_FIFOS_ERR_EINT
)
2594 dev_err(codec
->dev
, "Digital core FIFO error\n");
2596 if (irq_val
& WM8996_FLL_LOCK_EINT
) {
2597 dev_dbg(codec
->dev
, "FLL locked\n");
2598 complete(&wm8996
->fll_lock
);
2601 if (irq_val
& WM8996_MICD_EINT
)
2604 if (irq_val
& WM8996_HP_DONE_EINT
)
2605 wm8996_hpdet_irq(codec
);
2610 static irqreturn_t
wm8996_edge_irq(int irq
, void *data
)
2612 irqreturn_t ret
= IRQ_NONE
;
2616 val
= wm8996_irq(irq
, data
);
2617 if (val
!= IRQ_NONE
)
2619 } while (val
!= IRQ_NONE
);
2624 static void wm8996_retune_mobile_pdata(struct snd_soc_codec
*codec
)
2626 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2627 struct wm8996_pdata
*pdata
= &wm8996
->pdata
;
2629 struct snd_kcontrol_new controls
[] = {
2630 SOC_ENUM_EXT("DSP1 EQ Mode",
2631 wm8996
->retune_mobile_enum
,
2632 wm8996_get_retune_mobile_enum
,
2633 wm8996_put_retune_mobile_enum
),
2634 SOC_ENUM_EXT("DSP2 EQ Mode",
2635 wm8996
->retune_mobile_enum
,
2636 wm8996_get_retune_mobile_enum
,
2637 wm8996_put_retune_mobile_enum
),
2642 /* We need an array of texts for the enum API but the number
2643 * of texts is likely to be less than the number of
2644 * configurations due to the sample rate dependency of the
2645 * configurations. */
2646 wm8996
->num_retune_mobile_texts
= 0;
2647 wm8996
->retune_mobile_texts
= NULL
;
2648 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2649 for (j
= 0; j
< wm8996
->num_retune_mobile_texts
; j
++) {
2650 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2651 wm8996
->retune_mobile_texts
[j
]) == 0)
2655 if (j
!= wm8996
->num_retune_mobile_texts
)
2658 /* Expand the array... */
2659 t
= krealloc(wm8996
->retune_mobile_texts
,
2661 (wm8996
->num_retune_mobile_texts
+ 1),
2666 /* ...store the new entry... */
2667 t
[wm8996
->num_retune_mobile_texts
] =
2668 pdata
->retune_mobile_cfgs
[i
].name
;
2670 /* ...and remember the new version. */
2671 wm8996
->num_retune_mobile_texts
++;
2672 wm8996
->retune_mobile_texts
= t
;
2675 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2676 wm8996
->num_retune_mobile_texts
);
2678 wm8996
->retune_mobile_enum
.max
= wm8996
->num_retune_mobile_texts
;
2679 wm8996
->retune_mobile_enum
.texts
= wm8996
->retune_mobile_texts
;
2681 ret
= snd_soc_add_controls(codec
, controls
, ARRAY_SIZE(controls
));
2684 "Failed to add ReTune Mobile controls: %d\n", ret
);
2687 static int wm8996_probe(struct snd_soc_codec
*codec
)
2690 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2691 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
2692 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
2695 wm8996
->codec
= codec
;
2697 init_completion(&wm8996
->dcs_done
);
2698 init_completion(&wm8996
->fll_lock
);
2700 dapm
->idle_bias_off
= true;
2701 dapm
->bias_level
= SND_SOC_BIAS_OFF
;
2703 ret
= snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_I2C
);
2705 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
2709 for (i
= 0; i
< ARRAY_SIZE(wm8996
->supplies
); i
++)
2710 wm8996
->supplies
[i
].supply
= wm8996_supply_names
[i
];
2712 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(wm8996
->supplies
),
2715 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
2719 wm8996
->disable_nb
[0].notifier_call
= wm8996_regulator_event_0
;
2720 wm8996
->disable_nb
[1].notifier_call
= wm8996_regulator_event_1
;
2721 wm8996
->disable_nb
[2].notifier_call
= wm8996_regulator_event_2
;
2723 wm8996
->cpvdd
= regulator_get(&i2c
->dev
, "CPVDD");
2724 if (IS_ERR(wm8996
->cpvdd
)) {
2725 ret
= PTR_ERR(wm8996
->cpvdd
);
2726 dev_err(&i2c
->dev
, "Failed to get CPVDD: %d\n", ret
);
2730 /* This should really be moved into the regulator core */
2731 for (i
= 0; i
< ARRAY_SIZE(wm8996
->supplies
); i
++) {
2732 ret
= regulator_register_notifier(wm8996
->supplies
[i
].consumer
,
2733 &wm8996
->disable_nb
[i
]);
2736 "Failed to register regulator notifier: %d\n",
2741 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8996
->supplies
),
2744 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
2748 if (wm8996
->pdata
.ldo_ena
>= 0) {
2749 gpio_set_value_cansleep(wm8996
->pdata
.ldo_ena
, 1);
2753 ret
= snd_soc_read(codec
, WM8996_SOFTWARE_RESET
);
2755 dev_err(codec
->dev
, "Failed to read ID register: %d\n", ret
);
2758 if (ret
!= 0x8915) {
2759 dev_err(codec
->dev
, "Device is not a WM8996, ID %x\n", ret
);
2764 ret
= snd_soc_read(codec
, WM8996_CHIP_REVISION
);
2766 dev_err(codec
->dev
, "Failed to read device revision: %d\n",
2771 dev_info(codec
->dev
, "revision %c\n",
2772 (ret
& WM8996_CHIP_REV_MASK
) + 'A');
2774 if (wm8996
->pdata
.ldo_ena
>= 0) {
2775 gpio_set_value_cansleep(wm8996
->pdata
.ldo_ena
, 0);
2777 ret
= wm8996_reset(codec
);
2779 dev_err(codec
->dev
, "Failed to issue reset\n");
2784 codec
->cache_only
= true;
2786 /* Apply platform data settings */
2787 snd_soc_update_bits(codec
, WM8996_LINE_INPUT_CONTROL
,
2788 WM8996_INL_MODE_MASK
| WM8996_INR_MODE_MASK
,
2789 wm8996
->pdata
.inl_mode
<< WM8996_INL_MODE_SHIFT
|
2790 wm8996
->pdata
.inr_mode
);
2792 for (i
= 0; i
< ARRAY_SIZE(wm8996
->pdata
.gpio_default
); i
++) {
2793 if (!wm8996
->pdata
.gpio_default
[i
])
2796 snd_soc_write(codec
, WM8996_GPIO_1
+ i
,
2797 wm8996
->pdata
.gpio_default
[i
] & 0xffff);
2800 if (wm8996
->pdata
.spkmute_seq
)
2801 snd_soc_update_bits(codec
, WM8996_PDM_SPEAKER_MUTE_SEQUENCE
,
2802 WM8996_SPK_MUTE_ENDIAN
|
2803 WM8996_SPK_MUTE_SEQ1_MASK
,
2804 wm8996
->pdata
.spkmute_seq
);
2806 snd_soc_update_bits(codec
, WM8996_ACCESSORY_DETECT_MODE_2
,
2807 WM8996_MICD_BIAS_SRC
| WM8996_HPOUT1FB_SRC
|
2808 WM8996_MICD_SRC
, wm8996
->pdata
.micdet_def
);
2810 /* Latch volume update bits */
2811 snd_soc_update_bits(codec
, WM8996_LEFT_LINE_INPUT_VOLUME
,
2812 WM8996_IN1_VU
, WM8996_IN1_VU
);
2813 snd_soc_update_bits(codec
, WM8996_RIGHT_LINE_INPUT_VOLUME
,
2814 WM8996_IN1_VU
, WM8996_IN1_VU
);
2816 snd_soc_update_bits(codec
, WM8996_DAC1_LEFT_VOLUME
,
2817 WM8996_DAC1_VU
, WM8996_DAC1_VU
);
2818 snd_soc_update_bits(codec
, WM8996_DAC1_RIGHT_VOLUME
,
2819 WM8996_DAC1_VU
, WM8996_DAC1_VU
);
2820 snd_soc_update_bits(codec
, WM8996_DAC2_LEFT_VOLUME
,
2821 WM8996_DAC2_VU
, WM8996_DAC2_VU
);
2822 snd_soc_update_bits(codec
, WM8996_DAC2_RIGHT_VOLUME
,
2823 WM8996_DAC2_VU
, WM8996_DAC2_VU
);
2825 snd_soc_update_bits(codec
, WM8996_OUTPUT1_LEFT_VOLUME
,
2826 WM8996_DAC1_VU
, WM8996_DAC1_VU
);
2827 snd_soc_update_bits(codec
, WM8996_OUTPUT1_RIGHT_VOLUME
,
2828 WM8996_DAC1_VU
, WM8996_DAC1_VU
);
2829 snd_soc_update_bits(codec
, WM8996_OUTPUT2_LEFT_VOLUME
,
2830 WM8996_DAC2_VU
, WM8996_DAC2_VU
);
2831 snd_soc_update_bits(codec
, WM8996_OUTPUT2_RIGHT_VOLUME
,
2832 WM8996_DAC2_VU
, WM8996_DAC2_VU
);
2834 snd_soc_update_bits(codec
, WM8996_DSP1_TX_LEFT_VOLUME
,
2835 WM8996_DSP1TX_VU
, WM8996_DSP1TX_VU
);
2836 snd_soc_update_bits(codec
, WM8996_DSP1_TX_RIGHT_VOLUME
,
2837 WM8996_DSP1TX_VU
, WM8996_DSP1TX_VU
);
2838 snd_soc_update_bits(codec
, WM8996_DSP2_TX_LEFT_VOLUME
,
2839 WM8996_DSP2TX_VU
, WM8996_DSP2TX_VU
);
2840 snd_soc_update_bits(codec
, WM8996_DSP2_TX_RIGHT_VOLUME
,
2841 WM8996_DSP2TX_VU
, WM8996_DSP2TX_VU
);
2843 snd_soc_update_bits(codec
, WM8996_DSP1_RX_LEFT_VOLUME
,
2844 WM8996_DSP1RX_VU
, WM8996_DSP1RX_VU
);
2845 snd_soc_update_bits(codec
, WM8996_DSP1_RX_RIGHT_VOLUME
,
2846 WM8996_DSP1RX_VU
, WM8996_DSP1RX_VU
);
2847 snd_soc_update_bits(codec
, WM8996_DSP2_RX_LEFT_VOLUME
,
2848 WM8996_DSP2RX_VU
, WM8996_DSP2RX_VU
);
2849 snd_soc_update_bits(codec
, WM8996_DSP2_RX_RIGHT_VOLUME
,
2850 WM8996_DSP2RX_VU
, WM8996_DSP2RX_VU
);
2852 /* No support currently for the underclocked TDM modes and
2853 * pick a default TDM layout with each channel pair working with
2855 snd_soc_update_bits(codec
, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION
,
2856 WM8996_AIF1RX_CHAN0_SLOTS_MASK
|
2857 WM8996_AIF1RX_CHAN0_START_SLOT_MASK
,
2858 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT
| 0);
2859 snd_soc_update_bits(codec
, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION
,
2860 WM8996_AIF1RX_CHAN1_SLOTS_MASK
|
2861 WM8996_AIF1RX_CHAN1_START_SLOT_MASK
,
2862 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT
| 1);
2863 snd_soc_update_bits(codec
, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION
,
2864 WM8996_AIF1RX_CHAN2_SLOTS_MASK
|
2865 WM8996_AIF1RX_CHAN2_START_SLOT_MASK
,
2866 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT
| 0);
2867 snd_soc_update_bits(codec
, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION
,
2868 WM8996_AIF1RX_CHAN3_SLOTS_MASK
|
2869 WM8996_AIF1RX_CHAN0_START_SLOT_MASK
,
2870 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT
| 1);
2871 snd_soc_update_bits(codec
, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION
,
2872 WM8996_AIF1RX_CHAN4_SLOTS_MASK
|
2873 WM8996_AIF1RX_CHAN0_START_SLOT_MASK
,
2874 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT
| 0);
2875 snd_soc_update_bits(codec
, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION
,
2876 WM8996_AIF1RX_CHAN5_SLOTS_MASK
|
2877 WM8996_AIF1RX_CHAN0_START_SLOT_MASK
,
2878 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT
| 1);
2880 snd_soc_update_bits(codec
, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION
,
2881 WM8996_AIF2RX_CHAN0_SLOTS_MASK
|
2882 WM8996_AIF2RX_CHAN0_START_SLOT_MASK
,
2883 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT
| 0);
2884 snd_soc_update_bits(codec
, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION
,
2885 WM8996_AIF2RX_CHAN1_SLOTS_MASK
|
2886 WM8996_AIF2RX_CHAN1_START_SLOT_MASK
,
2887 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT
| 1);
2889 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION
,
2890 WM8996_AIF1TX_CHAN0_SLOTS_MASK
|
2891 WM8996_AIF1TX_CHAN0_START_SLOT_MASK
,
2892 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT
| 0);
2893 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION
,
2894 WM8996_AIF1TX_CHAN1_SLOTS_MASK
|
2895 WM8996_AIF1TX_CHAN0_START_SLOT_MASK
,
2896 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT
| 1);
2897 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION
,
2898 WM8996_AIF1TX_CHAN2_SLOTS_MASK
|
2899 WM8996_AIF1TX_CHAN0_START_SLOT_MASK
,
2900 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT
| 0);
2901 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION
,
2902 WM8996_AIF1TX_CHAN3_SLOTS_MASK
|
2903 WM8996_AIF1TX_CHAN0_START_SLOT_MASK
,
2904 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT
| 1);
2905 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION
,
2906 WM8996_AIF1TX_CHAN4_SLOTS_MASK
|
2907 WM8996_AIF1TX_CHAN0_START_SLOT_MASK
,
2908 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT
| 0);
2909 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION
,
2910 WM8996_AIF1TX_CHAN5_SLOTS_MASK
|
2911 WM8996_AIF1TX_CHAN0_START_SLOT_MASK
,
2912 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT
| 1);
2914 snd_soc_update_bits(codec
, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION
,
2915 WM8996_AIF2TX_CHAN0_SLOTS_MASK
|
2916 WM8996_AIF2TX_CHAN0_START_SLOT_MASK
,
2917 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT
| 0);
2918 snd_soc_update_bits(codec
, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION
,
2919 WM8996_AIF2TX_CHAN1_SLOTS_MASK
|
2920 WM8996_AIF2TX_CHAN1_START_SLOT_MASK
,
2921 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT
| 1);
2923 if (wm8996
->pdata
.num_retune_mobile_cfgs
)
2924 wm8996_retune_mobile_pdata(codec
);
2926 snd_soc_add_controls(codec
, wm8996_eq_controls
,
2927 ARRAY_SIZE(wm8996_eq_controls
));
2929 /* If the TX LRCLK pins are not in LRCLK mode configure the
2930 * AIFs to source their clocks from the RX LRCLKs.
2932 if ((snd_soc_read(codec
, WM8996_GPIO_1
)))
2933 snd_soc_update_bits(codec
, WM8996_AIF1_TX_LRCLK_2
,
2934 WM8996_AIF1TX_LRCLK_MODE
,
2935 WM8996_AIF1TX_LRCLK_MODE
);
2937 if ((snd_soc_read(codec
, WM8996_GPIO_2
)))
2938 snd_soc_update_bits(codec
, WM8996_AIF2_TX_LRCLK_2
,
2939 WM8996_AIF2TX_LRCLK_MODE
,
2940 WM8996_AIF2TX_LRCLK_MODE
);
2942 regulator_bulk_disable(ARRAY_SIZE(wm8996
->supplies
), wm8996
->supplies
);
2944 wm8996_init_gpio(codec
);
2947 if (wm8996
->pdata
.irq_flags
)
2948 irq_flags
= wm8996
->pdata
.irq_flags
;
2950 irq_flags
= IRQF_TRIGGER_LOW
;
2952 irq_flags
|= IRQF_ONESHOT
;
2954 if (irq_flags
& (IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
))
2955 ret
= request_threaded_irq(i2c
->irq
, NULL
,
2957 irq_flags
, "wm8996", codec
);
2959 ret
= request_threaded_irq(i2c
->irq
, NULL
, wm8996_irq
,
2960 irq_flags
, "wm8996", codec
);
2963 /* Unmask the interrupt */
2964 snd_soc_update_bits(codec
, WM8996_INTERRUPT_CONTROL
,
2967 /* Enable error reporting and DC servo status */
2968 snd_soc_update_bits(codec
,
2969 WM8996_INTERRUPT_STATUS_2_MASK
,
2970 WM8996_IM_DCS_DONE_23_EINT
|
2971 WM8996_IM_DCS_DONE_01_EINT
|
2972 WM8996_IM_FLL_LOCK_EINT
|
2973 WM8996_IM_FIFOS_ERR_EINT
,
2976 dev_err(codec
->dev
, "Failed to request IRQ: %d\n",
2984 if (wm8996
->pdata
.ldo_ena
>= 0)
2985 gpio_set_value_cansleep(wm8996
->pdata
.ldo_ena
, 0);
2987 regulator_bulk_disable(ARRAY_SIZE(wm8996
->supplies
), wm8996
->supplies
);
2989 regulator_put(wm8996
->cpvdd
);
2991 regulator_bulk_free(ARRAY_SIZE(wm8996
->supplies
), wm8996
->supplies
);
2996 static int wm8996_remove(struct snd_soc_codec
*codec
)
2998 struct wm8996_priv
*wm8996
= snd_soc_codec_get_drvdata(codec
);
2999 struct i2c_client
*i2c
= to_i2c_client(codec
->dev
);
3002 snd_soc_update_bits(codec
, WM8996_INTERRUPT_CONTROL
,
3003 WM8996_IM_IRQ
, WM8996_IM_IRQ
);
3006 free_irq(i2c
->irq
, codec
);
3008 wm8996_free_gpio(codec
);
3010 for (i
= 0; i
< ARRAY_SIZE(wm8996
->supplies
); i
++)
3011 regulator_unregister_notifier(wm8996
->supplies
[i
].consumer
,
3012 &wm8996
->disable_nb
[i
]);
3013 regulator_put(wm8996
->cpvdd
);
3014 regulator_bulk_free(ARRAY_SIZE(wm8996
->supplies
), wm8996
->supplies
);
3019 static struct snd_soc_codec_driver soc_codec_dev_wm8996
= {
3020 .probe
= wm8996_probe
,
3021 .remove
= wm8996_remove
,
3022 .set_bias_level
= wm8996_set_bias_level
,
3023 .seq_notifier
= wm8996_seq_notifier
,
3024 .reg_cache_size
= WM8996_MAX_REGISTER
+ 1,
3025 .reg_word_size
= sizeof(u16
),
3026 .reg_cache_default
= wm8996_reg
,
3027 .volatile_register
= wm8996_volatile_register
,
3028 .readable_register
= wm8996_readable_register
,
3029 .compress_type
= SND_SOC_RBTREE_COMPRESSION
,
3030 .controls
= wm8996_snd_controls
,
3031 .num_controls
= ARRAY_SIZE(wm8996_snd_controls
),
3032 .dapm_widgets
= wm8996_dapm_widgets
,
3033 .num_dapm_widgets
= ARRAY_SIZE(wm8996_dapm_widgets
),
3034 .dapm_routes
= wm8996_dapm_routes
,
3035 .num_dapm_routes
= ARRAY_SIZE(wm8996_dapm_routes
),
3036 .set_pll
= wm8996_set_fll
,
3039 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3040 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3041 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3042 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3043 SNDRV_PCM_FMTBIT_S32_LE)
3045 static struct snd_soc_dai_ops wm8996_dai_ops
= {
3046 .set_fmt
= wm8996_set_fmt
,
3047 .hw_params
= wm8996_hw_params
,
3048 .set_sysclk
= wm8996_set_sysclk
,
3051 static struct snd_soc_dai_driver wm8996_dai
[] = {
3053 .name
= "wm8996-aif1",
3055 .stream_name
= "AIF1 Playback",
3058 .rates
= WM8996_RATES
,
3059 .formats
= WM8996_FORMATS
,
3062 .stream_name
= "AIF1 Capture",
3065 .rates
= WM8996_RATES
,
3066 .formats
= WM8996_FORMATS
,
3068 .ops
= &wm8996_dai_ops
,
3071 .name
= "wm8996-aif2",
3073 .stream_name
= "AIF2 Playback",
3076 .rates
= WM8996_RATES
,
3077 .formats
= WM8996_FORMATS
,
3080 .stream_name
= "AIF2 Capture",
3083 .rates
= WM8996_RATES
,
3084 .formats
= WM8996_FORMATS
,
3086 .ops
= &wm8996_dai_ops
,
3090 static __devinit
int wm8996_i2c_probe(struct i2c_client
*i2c
,
3091 const struct i2c_device_id
*id
)
3093 struct wm8996_priv
*wm8996
;
3096 wm8996
= kzalloc(sizeof(struct wm8996_priv
), GFP_KERNEL
);
3100 i2c_set_clientdata(i2c
, wm8996
);
3102 if (dev_get_platdata(&i2c
->dev
))
3103 memcpy(&wm8996
->pdata
, dev_get_platdata(&i2c
->dev
),
3104 sizeof(wm8996
->pdata
));
3106 if (wm8996
->pdata
.ldo_ena
> 0) {
3107 ret
= gpio_request_one(wm8996
->pdata
.ldo_ena
,
3108 GPIOF_OUT_INIT_LOW
, "WM8996 ENA");
3110 dev_err(&i2c
->dev
, "Failed to request GPIO %d: %d\n",
3111 wm8996
->pdata
.ldo_ena
, ret
);
3116 ret
= snd_soc_register_codec(&i2c
->dev
,
3117 &soc_codec_dev_wm8996
, wm8996_dai
,
3118 ARRAY_SIZE(wm8996_dai
));
3125 if (wm8996
->pdata
.ldo_ena
> 0)
3126 gpio_free(wm8996
->pdata
.ldo_ena
);
3133 static __devexit
int wm8996_i2c_remove(struct i2c_client
*client
)
3135 struct wm8996_priv
*wm8996
= i2c_get_clientdata(client
);
3137 snd_soc_unregister_codec(&client
->dev
);
3138 if (wm8996
->pdata
.ldo_ena
> 0)
3139 gpio_free(wm8996
->pdata
.ldo_ena
);
3140 kfree(i2c_get_clientdata(client
));
3144 static const struct i2c_device_id wm8996_i2c_id
[] = {
3148 MODULE_DEVICE_TABLE(i2c
, wm8996_i2c_id
);
3150 static struct i2c_driver wm8996_i2c_driver
= {
3153 .owner
= THIS_MODULE
,
3155 .probe
= wm8996_i2c_probe
,
3156 .remove
= __devexit_p(wm8996_i2c_remove
),
3157 .id_table
= wm8996_i2c_id
,
3160 static int __init
wm8996_modinit(void)
3164 ret
= i2c_add_driver(&wm8996_i2c_driver
);
3166 printk(KERN_ERR
"Failed to register WM8996 I2C driver: %d\n",
3172 module_init(wm8996_modinit
);
3174 static void __exit
wm8996_exit(void)
3176 i2c_del_driver(&wm8996_i2c_driver
);
3178 module_exit(wm8996_exit
);
3180 MODULE_DESCRIPTION("ASoC WM8996 driver");
3181 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3182 MODULE_LICENSE("GPL");
projects / mirror_ubuntu-zesty-kernel.git / blob