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[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / wm8996.c
1 /*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011-2 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <trace/events/asoc.h>
34
35 #include <sound/wm8996.h>
36 #include "wm8996.h"
37
38 #define WM8996_AIFS 2
39
40 #define HPOUT1L 1
41 #define HPOUT1R 2
42 #define HPOUT2L 4
43 #define HPOUT2R 8
44
45 #define WM8996_NUM_SUPPLIES 3
46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
47 "DBVDD",
48 "AVDD1",
49 "AVDD2",
50 };
51
52 struct wm8996_priv {
53 struct device *dev;
54 struct regmap *regmap;
55 struct snd_soc_codec *codec;
56
57 int ldo1ena;
58
59 int sysclk;
60 int sysclk_src;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct completion fll_lock;
67
68 u16 dcs_pending;
69 struct completion dcs_done;
70
71 u16 hpout_ena;
72 u16 hpout_pending;
73
74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
76 int bg_ena;
77
78 struct wm8996_pdata pdata;
79
80 int rx_rate[WM8996_AIFS];
81 int bclk_rate[WM8996_AIFS];
82
83 /* Platform dependant ReTune mobile configuration */
84 int num_retune_mobile_texts;
85 const char **retune_mobile_texts;
86 int retune_mobile_cfg[2];
87 struct soc_enum retune_mobile_enum;
88
89 struct snd_soc_jack *jack;
90 bool detecting;
91 bool jack_mic;
92 int jack_flips;
93 wm8996_polarity_fn polarity_cb;
94
95 #ifdef CONFIG_GPIOLIB
96 struct gpio_chip gpio_chip;
97 #endif
98 };
99
100 /* We can't use the same notifier block for more than one supply and
101 * there's no way I can see to get from a callback to the caller
102 * except container_of().
103 */
104 #define WM8996_REGULATOR_EVENT(n) \
105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
106 unsigned long event, void *data) \
107 { \
108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
109 disable_nb[n]); \
110 if (event & REGULATOR_EVENT_DISABLE) { \
111 regcache_mark_dirty(wm8996->regmap); \
112 } \
113 return 0; \
114 }
115
116 WM8996_REGULATOR_EVENT(0)
117 WM8996_REGULATOR_EVENT(1)
118 WM8996_REGULATOR_EVENT(2)
119
120 static struct reg_default wm8996_reg[] = {
121 { WM8996_POWER_MANAGEMENT_1, 0x0 },
122 { WM8996_POWER_MANAGEMENT_2, 0x0 },
123 { WM8996_POWER_MANAGEMENT_3, 0x0 },
124 { WM8996_POWER_MANAGEMENT_4, 0x0 },
125 { WM8996_POWER_MANAGEMENT_5, 0x0 },
126 { WM8996_POWER_MANAGEMENT_6, 0x0 },
127 { WM8996_POWER_MANAGEMENT_7, 0x10 },
128 { WM8996_POWER_MANAGEMENT_8, 0x0 },
129 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
130 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
131 { WM8996_LINE_INPUT_CONTROL, 0x0 },
132 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
133 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
134 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
135 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
136 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
137 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
138 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
139 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
140 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
141 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
142 { WM8996_MICBIAS_1, 0x39 },
143 { WM8996_MICBIAS_2, 0x39 },
144 { WM8996_LDO_1, 0x3 },
145 { WM8996_LDO_2, 0x13 },
146 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
147 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
148 { WM8996_HEADPHONE_DETECT_1, 0x20 },
149 { WM8996_HEADPHONE_DETECT_2, 0x0 },
150 { WM8996_MIC_DETECT_1, 0x7600 },
151 { WM8996_MIC_DETECT_2, 0xbf },
152 { WM8996_CHARGE_PUMP_1, 0x1f25 },
153 { WM8996_CHARGE_PUMP_2, 0xab19 },
154 { WM8996_DC_SERVO_1, 0x0 },
155 { WM8996_DC_SERVO_3, 0x0 },
156 { WM8996_DC_SERVO_5, 0x2a2a },
157 { WM8996_DC_SERVO_6, 0x0 },
158 { WM8996_DC_SERVO_7, 0x0 },
159 { WM8996_ANALOGUE_HP_1, 0x0 },
160 { WM8996_ANALOGUE_HP_2, 0x0 },
161 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
164 { WM8996_AIF_CLOCKING_1, 0x0 },
165 { WM8996_AIF_CLOCKING_2, 0x0 },
166 { WM8996_CLOCKING_1, 0x10 },
167 { WM8996_CLOCKING_2, 0x0 },
168 { WM8996_AIF_RATE, 0x83 },
169 { WM8996_FLL_CONTROL_1, 0x0 },
170 { WM8996_FLL_CONTROL_2, 0x0 },
171 { WM8996_FLL_CONTROL_3, 0x0 },
172 { WM8996_FLL_CONTROL_4, 0x5dc0 },
173 { WM8996_FLL_CONTROL_5, 0xc84 },
174 { WM8996_FLL_EFS_1, 0x0 },
175 { WM8996_FLL_EFS_2, 0x2 },
176 { WM8996_AIF1_CONTROL, 0x0 },
177 { WM8996_AIF1_BCLK, 0x0 },
178 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
179 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
180 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
181 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
198 { WM8996_AIF1TX_TEST, 0x7 },
199 { WM8996_AIF2_CONTROL, 0x0 },
200 { WM8996_AIF2_BCLK, 0x0 },
201 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
202 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
203 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
204 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
213 { WM8996_AIF2TX_TEST, 0x1 },
214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
218 { WM8996_DSP1_TX_FILTERS, 0x2000 },
219 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
220 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
221 { WM8996_DSP1_DRC_1, 0x98 },
222 { WM8996_DSP1_DRC_2, 0x845 },
223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
247 { WM8996_DSP2_TX_FILTERS, 0x2000 },
248 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
249 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
250 { WM8996_DSP2_DRC_1, 0x98 },
251 { WM8996_DSP2_DRC_2, 0x845 },
252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
283 { WM8996_DAC_SOFTMUTE, 0x0 },
284 { WM8996_OVERSAMPLING, 0xd },
285 { WM8996_SIDETONE, 0x1040 },
286 { WM8996_GPIO_1, 0xa101 },
287 { WM8996_GPIO_2, 0xa101 },
288 { WM8996_GPIO_3, 0xa101 },
289 { WM8996_GPIO_4, 0xa101 },
290 { WM8996_GPIO_5, 0xa101 },
291 { WM8996_PULL_CONTROL_1, 0x0 },
292 { WM8996_PULL_CONTROL_2, 0x140 },
293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
295 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
299 };
300
301 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
302 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
303 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
304 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
305 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
306 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
307 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
308 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
309
310 static const char *sidetone_hpf_text[] = {
311 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
312 };
313
314 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
315 WM8996_SIDETONE, 7, sidetone_hpf_text);
316
317 static const char *hpf_mode_text[] = {
318 "HiFi", "Custom", "Voice"
319 };
320
321 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
322 WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text);
323
324 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
325 WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text);
326
327 static const char *hpf_cutoff_text[] = {
328 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
329 };
330
331 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
332 WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text);
333
334 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
335 WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text);
336
337 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
338 {
339 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
340 struct wm8996_pdata *pdata = &wm8996->pdata;
341 int base, best, best_val, save, i, cfg, iface;
342
343 if (!wm8996->num_retune_mobile_texts)
344 return;
345
346 switch (block) {
347 case 0:
348 base = WM8996_DSP1_RX_EQ_GAINS_1;
349 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
350 WM8996_DSP1RX_SRC)
351 iface = 1;
352 else
353 iface = 0;
354 break;
355 case 1:
356 base = WM8996_DSP1_RX_EQ_GAINS_2;
357 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
358 WM8996_DSP2RX_SRC)
359 iface = 1;
360 else
361 iface = 0;
362 break;
363 default:
364 return;
365 }
366
367 /* Find the version of the currently selected configuration
368 * with the nearest sample rate. */
369 cfg = wm8996->retune_mobile_cfg[block];
370 best = 0;
371 best_val = INT_MAX;
372 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
373 if (strcmp(pdata->retune_mobile_cfgs[i].name,
374 wm8996->retune_mobile_texts[cfg]) == 0 &&
375 abs(pdata->retune_mobile_cfgs[i].rate
376 - wm8996->rx_rate[iface]) < best_val) {
377 best = i;
378 best_val = abs(pdata->retune_mobile_cfgs[i].rate
379 - wm8996->rx_rate[iface]);
380 }
381 }
382
383 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
384 block,
385 pdata->retune_mobile_cfgs[best].name,
386 pdata->retune_mobile_cfgs[best].rate,
387 wm8996->rx_rate[iface]);
388
389 /* The EQ will be disabled while reconfiguring it, remember the
390 * current configuration.
391 */
392 save = snd_soc_read(codec, base);
393 save &= WM8996_DSP1RX_EQ_ENA;
394
395 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
396 snd_soc_update_bits(codec, base + i, 0xffff,
397 pdata->retune_mobile_cfgs[best].regs[i]);
398
399 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
400 }
401
402 /* Icky as hell but saves code duplication */
403 static int wm8996_get_retune_mobile_block(const char *name)
404 {
405 if (strcmp(name, "DSP1 EQ Mode") == 0)
406 return 0;
407 if (strcmp(name, "DSP2 EQ Mode") == 0)
408 return 1;
409 return -EINVAL;
410 }
411
412 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
413 struct snd_ctl_elem_value *ucontrol)
414 {
415 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
416 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
417 struct wm8996_pdata *pdata = &wm8996->pdata;
418 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
419 int value = ucontrol->value.integer.value[0];
420
421 if (block < 0)
422 return block;
423
424 if (value >= pdata->num_retune_mobile_cfgs)
425 return -EINVAL;
426
427 wm8996->retune_mobile_cfg[block] = value;
428
429 wm8996_set_retune_mobile(codec, block);
430
431 return 0;
432 }
433
434 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
435 struct snd_ctl_elem_value *ucontrol)
436 {
437 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
438 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
439 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
440
441 if (block < 0)
442 return block;
443 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
444
445 return 0;
446 }
447
448 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
449 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
450 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
451 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
452 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
453
454 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
455 0, 5, 24, 0, sidetone_tlv),
456 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
457 0, 5, 24, 0, sidetone_tlv),
458 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
459 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
460 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
461
462 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
463 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
464 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
465 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
466
467 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
468 13, 1, 0),
469 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
470 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
471 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
472
473 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
474 13, 1, 0),
475 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
476 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
477 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
478
479 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
480 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
481 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
482
483 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
484 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
485 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
486
487 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
488 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
489 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
490 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
491
492 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
493 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
494 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
495 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
496
497 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
498 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
499 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
500 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
501
502 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
503 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
504
505 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
506 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
507
508 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
509 0, threedstereo_tlv),
510 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
511 0, threedstereo_tlv),
512
513 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
514 8, 0, out_digital_tlv),
515 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
516 8, 0, out_digital_tlv),
517
518 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
519 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
520 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
521 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
522
523 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
524 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
525 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
526 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
527
528 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
529 spk_tlv),
530 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
531 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
532 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
533 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
534
535 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
536 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
537
538 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
539 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
540 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
541 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
542 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
543 WM8996_DSP1TXR_DRC_ENA),
544
545 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
546 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
547 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
548 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
549 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
550 WM8996_DSP2TXR_DRC_ENA),
551 };
552
553 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
554 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
555 eq_tlv),
556 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
557 eq_tlv),
558 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
559 eq_tlv),
560 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
561 eq_tlv),
562 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
563 eq_tlv),
564
565 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
566 eq_tlv),
567 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
568 eq_tlv),
569 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
570 eq_tlv),
571 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
572 eq_tlv),
573 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
574 eq_tlv),
575 };
576
577 static void wm8996_bg_enable(struct snd_soc_codec *codec)
578 {
579 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
580
581 wm8996->bg_ena++;
582 if (wm8996->bg_ena == 1) {
583 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
584 WM8996_BG_ENA, WM8996_BG_ENA);
585 msleep(2);
586 }
587 }
588
589 static void wm8996_bg_disable(struct snd_soc_codec *codec)
590 {
591 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
592
593 wm8996->bg_ena--;
594 if (!wm8996->bg_ena)
595 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
596 WM8996_BG_ENA, 0);
597 }
598
599 static int bg_event(struct snd_soc_dapm_widget *w,
600 struct snd_kcontrol *kcontrol, int event)
601 {
602 struct snd_soc_codec *codec = w->codec;
603 int ret = 0;
604
605 switch (event) {
606 case SND_SOC_DAPM_PRE_PMU:
607 wm8996_bg_enable(codec);
608 break;
609 case SND_SOC_DAPM_POST_PMD:
610 wm8996_bg_disable(codec);
611 break;
612 default:
613 WARN(1, "Invalid event %d\n", event);
614 ret = -EINVAL;
615 }
616
617 return ret;
618 }
619
620 static int cp_event(struct snd_soc_dapm_widget *w,
621 struct snd_kcontrol *kcontrol, int event)
622 {
623 int ret = 0;
624
625 switch (event) {
626 case SND_SOC_DAPM_POST_PMU:
627 msleep(5);
628 break;
629 default:
630 WARN(1, "Invalid event %d\n", event);
631 ret = -EINVAL;
632 }
633
634 return 0;
635 }
636
637 static int rmv_short_event(struct snd_soc_dapm_widget *w,
638 struct snd_kcontrol *kcontrol, int event)
639 {
640 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
641
642 /* Record which outputs we enabled */
643 switch (event) {
644 case SND_SOC_DAPM_PRE_PMD:
645 wm8996->hpout_pending &= ~w->shift;
646 break;
647 case SND_SOC_DAPM_PRE_PMU:
648 wm8996->hpout_pending |= w->shift;
649 break;
650 default:
651 WARN(1, "Invalid event %d\n", event);
652 return -EINVAL;
653 }
654
655 return 0;
656 }
657
658 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
659 {
660 struct i2c_client *i2c = to_i2c_client(codec->dev);
661 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
662 int ret;
663 unsigned long timeout = 200;
664
665 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
666
667 /* Use the interrupt if possible */
668 do {
669 if (i2c->irq) {
670 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
671 msecs_to_jiffies(200));
672 if (timeout == 0)
673 dev_err(codec->dev, "DC servo timed out\n");
674
675 } else {
676 msleep(1);
677 timeout--;
678 }
679
680 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
681 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
682 } while (timeout && ret & mask);
683
684 if (timeout == 0)
685 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
686 else
687 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
688 }
689
690 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
691 enum snd_soc_dapm_type event, int subseq)
692 {
693 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
694 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
695 u16 val, mask;
696
697 /* Complete any pending DC servo starts */
698 if (wm8996->dcs_pending) {
699 dev_dbg(codec->dev, "Starting DC servo for %x\n",
700 wm8996->dcs_pending);
701
702 /* Trigger a startup sequence */
703 wait_for_dc_servo(codec, wm8996->dcs_pending
704 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
705
706 wm8996->dcs_pending = 0;
707 }
708
709 if (wm8996->hpout_pending != wm8996->hpout_ena) {
710 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
711 wm8996->hpout_ena, wm8996->hpout_pending);
712
713 val = 0;
714 mask = 0;
715 if (wm8996->hpout_pending & HPOUT1L) {
716 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
717 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
718 } else {
719 mask |= WM8996_HPOUT1L_RMV_SHORT |
720 WM8996_HPOUT1L_OUTP |
721 WM8996_HPOUT1L_DLY;
722 }
723
724 if (wm8996->hpout_pending & HPOUT1R) {
725 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
726 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
727 } else {
728 mask |= WM8996_HPOUT1R_RMV_SHORT |
729 WM8996_HPOUT1R_OUTP |
730 WM8996_HPOUT1R_DLY;
731 }
732
733 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
734
735 val = 0;
736 mask = 0;
737 if (wm8996->hpout_pending & HPOUT2L) {
738 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
739 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
740 } else {
741 mask |= WM8996_HPOUT2L_RMV_SHORT |
742 WM8996_HPOUT2L_OUTP |
743 WM8996_HPOUT2L_DLY;
744 }
745
746 if (wm8996->hpout_pending & HPOUT2R) {
747 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
748 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
749 } else {
750 mask |= WM8996_HPOUT2R_RMV_SHORT |
751 WM8996_HPOUT2R_OUTP |
752 WM8996_HPOUT2R_DLY;
753 }
754
755 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
756
757 wm8996->hpout_ena = wm8996->hpout_pending;
758 }
759 }
760
761 static int dcs_start(struct snd_soc_dapm_widget *w,
762 struct snd_kcontrol *kcontrol, int event)
763 {
764 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
765
766 switch (event) {
767 case SND_SOC_DAPM_POST_PMU:
768 wm8996->dcs_pending |= 1 << w->shift;
769 break;
770 default:
771 WARN(1, "Invalid event %d\n", event);
772 return -EINVAL;
773 }
774
775 return 0;
776 }
777
778 static const char *sidetone_text[] = {
779 "IN1", "IN2",
780 };
781
782 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum,
783 WM8996_SIDETONE, 0, sidetone_text);
784
785 static const struct snd_kcontrol_new left_sidetone =
786 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
787
788 static SOC_ENUM_SINGLE_DECL(right_sidetone_enum,
789 WM8996_SIDETONE, 1, sidetone_text);
790
791 static const struct snd_kcontrol_new right_sidetone =
792 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
793
794 static const char *spk_text[] = {
795 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
796 };
797
798 static SOC_ENUM_SINGLE_DECL(spkl_enum,
799 WM8996_LEFT_PDM_SPEAKER, 0, spk_text);
800
801 static const struct snd_kcontrol_new spkl_mux =
802 SOC_DAPM_ENUM("SPKL", spkl_enum);
803
804 static SOC_ENUM_SINGLE_DECL(spkr_enum,
805 WM8996_RIGHT_PDM_SPEAKER, 0, spk_text);
806
807 static const struct snd_kcontrol_new spkr_mux =
808 SOC_DAPM_ENUM("SPKR", spkr_enum);
809
810 static const char *dsp1rx_text[] = {
811 "AIF1", "AIF2"
812 };
813
814 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
815 WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text);
816
817 static const struct snd_kcontrol_new dsp1rx =
818 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
819
820 static const char *dsp2rx_text[] = {
821 "AIF2", "AIF1"
822 };
823
824 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
825 WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text);
826
827 static const struct snd_kcontrol_new dsp2rx =
828 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
829
830 static const char *aif2tx_text[] = {
831 "DSP2", "DSP1", "AIF1"
832 };
833
834 static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
835 WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text);
836
837 static const struct snd_kcontrol_new aif2tx =
838 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
839
840 static const char *inmux_text[] = {
841 "ADC", "DMIC1", "DMIC2"
842 };
843
844 static SOC_ENUM_SINGLE_DECL(in1_enum,
845 WM8996_POWER_MANAGEMENT_7, 0, inmux_text);
846
847 static const struct snd_kcontrol_new in1_mux =
848 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
849
850 static SOC_ENUM_SINGLE_DECL(in2_enum,
851 WM8996_POWER_MANAGEMENT_7, 4, inmux_text);
852
853 static const struct snd_kcontrol_new in2_mux =
854 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
855
856 static const struct snd_kcontrol_new dac2r_mix[] = {
857 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
858 5, 1, 0),
859 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
860 4, 1, 0),
861 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
862 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
863 };
864
865 static const struct snd_kcontrol_new dac2l_mix[] = {
866 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
867 5, 1, 0),
868 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
869 4, 1, 0),
870 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
871 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
872 };
873
874 static const struct snd_kcontrol_new dac1r_mix[] = {
875 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
876 5, 1, 0),
877 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
878 4, 1, 0),
879 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
880 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
881 };
882
883 static const struct snd_kcontrol_new dac1l_mix[] = {
884 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
885 5, 1, 0),
886 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
887 4, 1, 0),
888 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
889 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
890 };
891
892 static const struct snd_kcontrol_new dsp1txl[] = {
893 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
894 1, 1, 0),
895 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
896 0, 1, 0),
897 };
898
899 static const struct snd_kcontrol_new dsp1txr[] = {
900 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
901 1, 1, 0),
902 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
903 0, 1, 0),
904 };
905
906 static const struct snd_kcontrol_new dsp2txl[] = {
907 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
908 1, 1, 0),
909 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
910 0, 1, 0),
911 };
912
913 static const struct snd_kcontrol_new dsp2txr[] = {
914 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
915 1, 1, 0),
916 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
917 0, 1, 0),
918 };
919
920
921 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
922 SND_SOC_DAPM_INPUT("IN1LN"),
923 SND_SOC_DAPM_INPUT("IN1LP"),
924 SND_SOC_DAPM_INPUT("IN1RN"),
925 SND_SOC_DAPM_INPUT("IN1RP"),
926
927 SND_SOC_DAPM_INPUT("IN2LN"),
928 SND_SOC_DAPM_INPUT("IN2LP"),
929 SND_SOC_DAPM_INPUT("IN2RN"),
930 SND_SOC_DAPM_INPUT("IN2RP"),
931
932 SND_SOC_DAPM_INPUT("DMIC1DAT"),
933 SND_SOC_DAPM_INPUT("DMIC2DAT"),
934
935 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
936 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
937 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
938 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
939 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
940 SND_SOC_DAPM_POST_PMU),
941 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
942 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
943 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
944 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
945 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
946 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
947 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
948
949 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
950 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
951
952 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
953 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
954 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
955 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
956
957 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
958 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
959
960 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
961 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
962 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
963 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
964
965 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
966 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
967
968 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
969 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
970
971 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
972 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
973 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
974 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
975
976 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
977 dsp2txl, ARRAY_SIZE(dsp2txl)),
978 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
979 dsp2txr, ARRAY_SIZE(dsp2txr)),
980 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
981 dsp1txl, ARRAY_SIZE(dsp1txl)),
982 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
983 dsp1txr, ARRAY_SIZE(dsp1txr)),
984
985 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
986 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
987 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
988 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
989 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
990 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
991 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
992 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
993
994 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
995 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
996 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
997 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
998
999 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
1000 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
1001
1002 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
1003 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
1004
1005 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
1006 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
1007 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
1008 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
1009 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
1010 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
1011
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
1013 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
1014 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
1015 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
1016 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
1017 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
1018
1019 /* We route as stereo pairs so define some dummy widgets to squash
1020 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1021 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1022 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1023 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1024 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1025 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1026
1027 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1028 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1029 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1030
1031 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1032 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1033 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1034 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1035
1036 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1037 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1038 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1039 SND_SOC_DAPM_POST_PMU),
1040 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1041 rmv_short_event,
1042 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1043
1044 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1045 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1046 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1047 SND_SOC_DAPM_POST_PMU),
1048 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1049 rmv_short_event,
1050 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1051
1052 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1053 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1054 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1055 SND_SOC_DAPM_POST_PMU),
1056 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1057 rmv_short_event,
1058 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1059
1060 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1061 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1062 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1063 SND_SOC_DAPM_POST_PMU),
1064 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1065 rmv_short_event,
1066 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1067
1068 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1069 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1070 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1071 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1072 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1073 };
1074
1075 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1076 { "AIFCLK", NULL, "SYSCLK" },
1077 { "SYSDSPCLK", NULL, "SYSCLK" },
1078 { "Charge Pump", NULL, "SYSCLK" },
1079 { "Charge Pump", NULL, "CPVDD" },
1080
1081 { "MICB1", NULL, "LDO2" },
1082 { "MICB1", NULL, "MICB1 Audio" },
1083 { "MICB1", NULL, "Bandgap" },
1084 { "MICB2", NULL, "LDO2" },
1085 { "MICB2", NULL, "MICB2 Audio" },
1086 { "MICB2", NULL, "Bandgap" },
1087
1088 { "AIF1RX0", NULL, "AIF1 Playback" },
1089 { "AIF1RX1", NULL, "AIF1 Playback" },
1090 { "AIF1RX2", NULL, "AIF1 Playback" },
1091 { "AIF1RX3", NULL, "AIF1 Playback" },
1092 { "AIF1RX4", NULL, "AIF1 Playback" },
1093 { "AIF1RX5", NULL, "AIF1 Playback" },
1094
1095 { "AIF2RX0", NULL, "AIF2 Playback" },
1096 { "AIF2RX1", NULL, "AIF2 Playback" },
1097
1098 { "AIF1 Capture", NULL, "AIF1TX0" },
1099 { "AIF1 Capture", NULL, "AIF1TX1" },
1100 { "AIF1 Capture", NULL, "AIF1TX2" },
1101 { "AIF1 Capture", NULL, "AIF1TX3" },
1102 { "AIF1 Capture", NULL, "AIF1TX4" },
1103 { "AIF1 Capture", NULL, "AIF1TX5" },
1104
1105 { "AIF2 Capture", NULL, "AIF2TX0" },
1106 { "AIF2 Capture", NULL, "AIF2TX1" },
1107
1108 { "IN1L PGA", NULL, "IN2LN" },
1109 { "IN1L PGA", NULL, "IN2LP" },
1110 { "IN1L PGA", NULL, "IN1LN" },
1111 { "IN1L PGA", NULL, "IN1LP" },
1112 { "IN1L PGA", NULL, "Bandgap" },
1113
1114 { "IN1R PGA", NULL, "IN2RN" },
1115 { "IN1R PGA", NULL, "IN2RP" },
1116 { "IN1R PGA", NULL, "IN1RN" },
1117 { "IN1R PGA", NULL, "IN1RP" },
1118 { "IN1R PGA", NULL, "Bandgap" },
1119
1120 { "ADCL", NULL, "IN1L PGA" },
1121
1122 { "ADCR", NULL, "IN1R PGA" },
1123
1124 { "DMIC1L", NULL, "DMIC1DAT" },
1125 { "DMIC1R", NULL, "DMIC1DAT" },
1126 { "DMIC2L", NULL, "DMIC2DAT" },
1127 { "DMIC2R", NULL, "DMIC2DAT" },
1128
1129 { "DMIC2L", NULL, "DMIC2" },
1130 { "DMIC2R", NULL, "DMIC2" },
1131 { "DMIC1L", NULL, "DMIC1" },
1132 { "DMIC1R", NULL, "DMIC1" },
1133
1134 { "IN1L Mux", "ADC", "ADCL" },
1135 { "IN1L Mux", "DMIC1", "DMIC1L" },
1136 { "IN1L Mux", "DMIC2", "DMIC2L" },
1137
1138 { "IN1R Mux", "ADC", "ADCR" },
1139 { "IN1R Mux", "DMIC1", "DMIC1R" },
1140 { "IN1R Mux", "DMIC2", "DMIC2R" },
1141
1142 { "IN2L Mux", "ADC", "ADCL" },
1143 { "IN2L Mux", "DMIC1", "DMIC1L" },
1144 { "IN2L Mux", "DMIC2", "DMIC2L" },
1145
1146 { "IN2R Mux", "ADC", "ADCR" },
1147 { "IN2R Mux", "DMIC1", "DMIC1R" },
1148 { "IN2R Mux", "DMIC2", "DMIC2R" },
1149
1150 { "Left Sidetone", "IN1", "IN1L Mux" },
1151 { "Left Sidetone", "IN2", "IN2L Mux" },
1152
1153 { "Right Sidetone", "IN1", "IN1R Mux" },
1154 { "Right Sidetone", "IN2", "IN2R Mux" },
1155
1156 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1157 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1158
1159 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1160 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1161
1162 { "AIF1TX0", NULL, "DSP1TXL" },
1163 { "AIF1TX1", NULL, "DSP1TXR" },
1164 { "AIF1TX2", NULL, "DSP2TXL" },
1165 { "AIF1TX3", NULL, "DSP2TXR" },
1166 { "AIF1TX4", NULL, "AIF2RX0" },
1167 { "AIF1TX5", NULL, "AIF2RX1" },
1168
1169 { "AIF1RX0", NULL, "AIFCLK" },
1170 { "AIF1RX1", NULL, "AIFCLK" },
1171 { "AIF1RX2", NULL, "AIFCLK" },
1172 { "AIF1RX3", NULL, "AIFCLK" },
1173 { "AIF1RX4", NULL, "AIFCLK" },
1174 { "AIF1RX5", NULL, "AIFCLK" },
1175
1176 { "AIF2RX0", NULL, "AIFCLK" },
1177 { "AIF2RX1", NULL, "AIFCLK" },
1178
1179 { "AIF1TX0", NULL, "AIFCLK" },
1180 { "AIF1TX1", NULL, "AIFCLK" },
1181 { "AIF1TX2", NULL, "AIFCLK" },
1182 { "AIF1TX3", NULL, "AIFCLK" },
1183 { "AIF1TX4", NULL, "AIFCLK" },
1184 { "AIF1TX5", NULL, "AIFCLK" },
1185
1186 { "AIF2TX0", NULL, "AIFCLK" },
1187 { "AIF2TX1", NULL, "AIFCLK" },
1188
1189 { "DSP1RXL", NULL, "SYSDSPCLK" },
1190 { "DSP1RXR", NULL, "SYSDSPCLK" },
1191 { "DSP2RXL", NULL, "SYSDSPCLK" },
1192 { "DSP2RXR", NULL, "SYSDSPCLK" },
1193 { "DSP1TXL", NULL, "SYSDSPCLK" },
1194 { "DSP1TXR", NULL, "SYSDSPCLK" },
1195 { "DSP2TXL", NULL, "SYSDSPCLK" },
1196 { "DSP2TXR", NULL, "SYSDSPCLK" },
1197
1198 { "AIF1RXA", NULL, "AIF1RX0" },
1199 { "AIF1RXA", NULL, "AIF1RX1" },
1200 { "AIF1RXB", NULL, "AIF1RX2" },
1201 { "AIF1RXB", NULL, "AIF1RX3" },
1202 { "AIF1RXC", NULL, "AIF1RX4" },
1203 { "AIF1RXC", NULL, "AIF1RX5" },
1204
1205 { "AIF2RX", NULL, "AIF2RX0" },
1206 { "AIF2RX", NULL, "AIF2RX1" },
1207
1208 { "AIF2TX", "DSP2", "DSP2TX" },
1209 { "AIF2TX", "DSP1", "DSP1RX" },
1210 { "AIF2TX", "AIF1", "AIF1RXC" },
1211
1212 { "DSP1RXL", NULL, "DSP1RX" },
1213 { "DSP1RXR", NULL, "DSP1RX" },
1214 { "DSP2RXL", NULL, "DSP2RX" },
1215 { "DSP2RXR", NULL, "DSP2RX" },
1216
1217 { "DSP2TX", NULL, "DSP2TXL" },
1218 { "DSP2TX", NULL, "DSP2TXR" },
1219
1220 { "DSP1RX", "AIF1", "AIF1RXA" },
1221 { "DSP1RX", "AIF2", "AIF2RX" },
1222
1223 { "DSP2RX", "AIF1", "AIF1RXB" },
1224 { "DSP2RX", "AIF2", "AIF2RX" },
1225
1226 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1227 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1228 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1229 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1230
1231 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1232 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1233 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1234 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1235
1236 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1237 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1238 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1239 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1240
1241 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1242 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1243 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1244 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1245
1246 { "DAC1L", NULL, "DAC1L Mixer" },
1247 { "DAC1R", NULL, "DAC1R Mixer" },
1248 { "DAC2L", NULL, "DAC2L Mixer" },
1249 { "DAC2R", NULL, "DAC2R Mixer" },
1250
1251 { "HPOUT2L PGA", NULL, "Charge Pump" },
1252 { "HPOUT2L PGA", NULL, "Bandgap" },
1253 { "HPOUT2L PGA", NULL, "DAC2L" },
1254 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1255 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1256 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
1257
1258 { "HPOUT2R PGA", NULL, "Charge Pump" },
1259 { "HPOUT2R PGA", NULL, "Bandgap" },
1260 { "HPOUT2R PGA", NULL, "DAC2R" },
1261 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1262 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1263 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
1264
1265 { "HPOUT1L PGA", NULL, "Charge Pump" },
1266 { "HPOUT1L PGA", NULL, "Bandgap" },
1267 { "HPOUT1L PGA", NULL, "DAC1L" },
1268 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1269 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1270 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
1271
1272 { "HPOUT1R PGA", NULL, "Charge Pump" },
1273 { "HPOUT1R PGA", NULL, "Bandgap" },
1274 { "HPOUT1R PGA", NULL, "DAC1R" },
1275 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1276 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1277 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
1278
1279 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1280 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1281 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1282 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1283
1284 { "SPKL", "DAC1L", "DAC1L" },
1285 { "SPKL", "DAC1R", "DAC1R" },
1286 { "SPKL", "DAC2L", "DAC2L" },
1287 { "SPKL", "DAC2R", "DAC2R" },
1288
1289 { "SPKR", "DAC1L", "DAC1L" },
1290 { "SPKR", "DAC1R", "DAC1R" },
1291 { "SPKR", "DAC2L", "DAC2L" },
1292 { "SPKR", "DAC2R", "DAC2R" },
1293
1294 { "SPKL PGA", NULL, "SPKL" },
1295 { "SPKR PGA", NULL, "SPKR" },
1296
1297 { "SPKDAT", NULL, "SPKL PGA" },
1298 { "SPKDAT", NULL, "SPKR PGA" },
1299 };
1300
1301 static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1302 {
1303 /* Due to the sparseness of the register map the compiler
1304 * output from an explicit switch statement ends up being much
1305 * more efficient than a table.
1306 */
1307 switch (reg) {
1308 case WM8996_SOFTWARE_RESET:
1309 case WM8996_POWER_MANAGEMENT_1:
1310 case WM8996_POWER_MANAGEMENT_2:
1311 case WM8996_POWER_MANAGEMENT_3:
1312 case WM8996_POWER_MANAGEMENT_4:
1313 case WM8996_POWER_MANAGEMENT_5:
1314 case WM8996_POWER_MANAGEMENT_6:
1315 case WM8996_POWER_MANAGEMENT_7:
1316 case WM8996_POWER_MANAGEMENT_8:
1317 case WM8996_LEFT_LINE_INPUT_VOLUME:
1318 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1319 case WM8996_LINE_INPUT_CONTROL:
1320 case WM8996_DAC1_HPOUT1_VOLUME:
1321 case WM8996_DAC2_HPOUT2_VOLUME:
1322 case WM8996_DAC1_LEFT_VOLUME:
1323 case WM8996_DAC1_RIGHT_VOLUME:
1324 case WM8996_DAC2_LEFT_VOLUME:
1325 case WM8996_DAC2_RIGHT_VOLUME:
1326 case WM8996_OUTPUT1_LEFT_VOLUME:
1327 case WM8996_OUTPUT1_RIGHT_VOLUME:
1328 case WM8996_OUTPUT2_LEFT_VOLUME:
1329 case WM8996_OUTPUT2_RIGHT_VOLUME:
1330 case WM8996_MICBIAS_1:
1331 case WM8996_MICBIAS_2:
1332 case WM8996_LDO_1:
1333 case WM8996_LDO_2:
1334 case WM8996_ACCESSORY_DETECT_MODE_1:
1335 case WM8996_ACCESSORY_DETECT_MODE_2:
1336 case WM8996_HEADPHONE_DETECT_1:
1337 case WM8996_HEADPHONE_DETECT_2:
1338 case WM8996_MIC_DETECT_1:
1339 case WM8996_MIC_DETECT_2:
1340 case WM8996_MIC_DETECT_3:
1341 case WM8996_CHARGE_PUMP_1:
1342 case WM8996_CHARGE_PUMP_2:
1343 case WM8996_DC_SERVO_1:
1344 case WM8996_DC_SERVO_2:
1345 case WM8996_DC_SERVO_3:
1346 case WM8996_DC_SERVO_5:
1347 case WM8996_DC_SERVO_6:
1348 case WM8996_DC_SERVO_7:
1349 case WM8996_DC_SERVO_READBACK_0:
1350 case WM8996_ANALOGUE_HP_1:
1351 case WM8996_ANALOGUE_HP_2:
1352 case WM8996_CHIP_REVISION:
1353 case WM8996_CONTROL_INTERFACE_1:
1354 case WM8996_WRITE_SEQUENCER_CTRL_1:
1355 case WM8996_WRITE_SEQUENCER_CTRL_2:
1356 case WM8996_AIF_CLOCKING_1:
1357 case WM8996_AIF_CLOCKING_2:
1358 case WM8996_CLOCKING_1:
1359 case WM8996_CLOCKING_2:
1360 case WM8996_AIF_RATE:
1361 case WM8996_FLL_CONTROL_1:
1362 case WM8996_FLL_CONTROL_2:
1363 case WM8996_FLL_CONTROL_3:
1364 case WM8996_FLL_CONTROL_4:
1365 case WM8996_FLL_CONTROL_5:
1366 case WM8996_FLL_CONTROL_6:
1367 case WM8996_FLL_EFS_1:
1368 case WM8996_FLL_EFS_2:
1369 case WM8996_AIF1_CONTROL:
1370 case WM8996_AIF1_BCLK:
1371 case WM8996_AIF1_TX_LRCLK_1:
1372 case WM8996_AIF1_TX_LRCLK_2:
1373 case WM8996_AIF1_RX_LRCLK_1:
1374 case WM8996_AIF1_RX_LRCLK_2:
1375 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1376 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1377 case WM8996_AIF1RX_DATA_CONFIGURATION:
1378 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1379 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1380 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1381 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1382 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1383 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1384 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1385 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1386 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1387 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1388 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1389 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1390 case WM8996_AIF1RX_MONO_CONFIGURATION:
1391 case WM8996_AIF1TX_TEST:
1392 case WM8996_AIF2_CONTROL:
1393 case WM8996_AIF2_BCLK:
1394 case WM8996_AIF2_TX_LRCLK_1:
1395 case WM8996_AIF2_TX_LRCLK_2:
1396 case WM8996_AIF2_RX_LRCLK_1:
1397 case WM8996_AIF2_RX_LRCLK_2:
1398 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1399 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1400 case WM8996_AIF2RX_DATA_CONFIGURATION:
1401 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1402 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1403 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1404 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1405 case WM8996_AIF2RX_MONO_CONFIGURATION:
1406 case WM8996_AIF2TX_TEST:
1407 case WM8996_DSP1_TX_LEFT_VOLUME:
1408 case WM8996_DSP1_TX_RIGHT_VOLUME:
1409 case WM8996_DSP1_RX_LEFT_VOLUME:
1410 case WM8996_DSP1_RX_RIGHT_VOLUME:
1411 case WM8996_DSP1_TX_FILTERS:
1412 case WM8996_DSP1_RX_FILTERS_1:
1413 case WM8996_DSP1_RX_FILTERS_2:
1414 case WM8996_DSP1_DRC_1:
1415 case WM8996_DSP1_DRC_2:
1416 case WM8996_DSP1_DRC_3:
1417 case WM8996_DSP1_DRC_4:
1418 case WM8996_DSP1_DRC_5:
1419 case WM8996_DSP1_RX_EQ_GAINS_1:
1420 case WM8996_DSP1_RX_EQ_GAINS_2:
1421 case WM8996_DSP1_RX_EQ_BAND_1_A:
1422 case WM8996_DSP1_RX_EQ_BAND_1_B:
1423 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1424 case WM8996_DSP1_RX_EQ_BAND_2_A:
1425 case WM8996_DSP1_RX_EQ_BAND_2_B:
1426 case WM8996_DSP1_RX_EQ_BAND_2_C:
1427 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1428 case WM8996_DSP1_RX_EQ_BAND_3_A:
1429 case WM8996_DSP1_RX_EQ_BAND_3_B:
1430 case WM8996_DSP1_RX_EQ_BAND_3_C:
1431 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1432 case WM8996_DSP1_RX_EQ_BAND_4_A:
1433 case WM8996_DSP1_RX_EQ_BAND_4_B:
1434 case WM8996_DSP1_RX_EQ_BAND_4_C:
1435 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1436 case WM8996_DSP1_RX_EQ_BAND_5_A:
1437 case WM8996_DSP1_RX_EQ_BAND_5_B:
1438 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1439 case WM8996_DSP2_TX_LEFT_VOLUME:
1440 case WM8996_DSP2_TX_RIGHT_VOLUME:
1441 case WM8996_DSP2_RX_LEFT_VOLUME:
1442 case WM8996_DSP2_RX_RIGHT_VOLUME:
1443 case WM8996_DSP2_TX_FILTERS:
1444 case WM8996_DSP2_RX_FILTERS_1:
1445 case WM8996_DSP2_RX_FILTERS_2:
1446 case WM8996_DSP2_DRC_1:
1447 case WM8996_DSP2_DRC_2:
1448 case WM8996_DSP2_DRC_3:
1449 case WM8996_DSP2_DRC_4:
1450 case WM8996_DSP2_DRC_5:
1451 case WM8996_DSP2_RX_EQ_GAINS_1:
1452 case WM8996_DSP2_RX_EQ_GAINS_2:
1453 case WM8996_DSP2_RX_EQ_BAND_1_A:
1454 case WM8996_DSP2_RX_EQ_BAND_1_B:
1455 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1456 case WM8996_DSP2_RX_EQ_BAND_2_A:
1457 case WM8996_DSP2_RX_EQ_BAND_2_B:
1458 case WM8996_DSP2_RX_EQ_BAND_2_C:
1459 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1460 case WM8996_DSP2_RX_EQ_BAND_3_A:
1461 case WM8996_DSP2_RX_EQ_BAND_3_B:
1462 case WM8996_DSP2_RX_EQ_BAND_3_C:
1463 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1464 case WM8996_DSP2_RX_EQ_BAND_4_A:
1465 case WM8996_DSP2_RX_EQ_BAND_4_B:
1466 case WM8996_DSP2_RX_EQ_BAND_4_C:
1467 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1468 case WM8996_DSP2_RX_EQ_BAND_5_A:
1469 case WM8996_DSP2_RX_EQ_BAND_5_B:
1470 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1471 case WM8996_DAC1_MIXER_VOLUMES:
1472 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1473 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1474 case WM8996_DAC2_MIXER_VOLUMES:
1475 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1476 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1477 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1478 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1479 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1480 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1481 case WM8996_DSP_TX_MIXER_SELECT:
1482 case WM8996_DAC_SOFTMUTE:
1483 case WM8996_OVERSAMPLING:
1484 case WM8996_SIDETONE:
1485 case WM8996_GPIO_1:
1486 case WM8996_GPIO_2:
1487 case WM8996_GPIO_3:
1488 case WM8996_GPIO_4:
1489 case WM8996_GPIO_5:
1490 case WM8996_PULL_CONTROL_1:
1491 case WM8996_PULL_CONTROL_2:
1492 case WM8996_INTERRUPT_STATUS_1:
1493 case WM8996_INTERRUPT_STATUS_2:
1494 case WM8996_INTERRUPT_RAW_STATUS_2:
1495 case WM8996_INTERRUPT_STATUS_1_MASK:
1496 case WM8996_INTERRUPT_STATUS_2_MASK:
1497 case WM8996_INTERRUPT_CONTROL:
1498 case WM8996_LEFT_PDM_SPEAKER:
1499 case WM8996_RIGHT_PDM_SPEAKER:
1500 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1501 case WM8996_PDM_SPEAKER_VOLUME:
1502 return 1;
1503 default:
1504 return 0;
1505 }
1506 }
1507
1508 static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1509 {
1510 switch (reg) {
1511 case WM8996_SOFTWARE_RESET:
1512 case WM8996_CHIP_REVISION:
1513 case WM8996_LDO_1:
1514 case WM8996_LDO_2:
1515 case WM8996_INTERRUPT_STATUS_1:
1516 case WM8996_INTERRUPT_STATUS_2:
1517 case WM8996_INTERRUPT_RAW_STATUS_2:
1518 case WM8996_DC_SERVO_READBACK_0:
1519 case WM8996_DC_SERVO_2:
1520 case WM8996_DC_SERVO_6:
1521 case WM8996_DC_SERVO_7:
1522 case WM8996_FLL_CONTROL_6:
1523 case WM8996_MIC_DETECT_3:
1524 case WM8996_HEADPHONE_DETECT_1:
1525 case WM8996_HEADPHONE_DETECT_2:
1526 return 1;
1527 default:
1528 return 0;
1529 }
1530 }
1531
1532 static const int bclk_divs[] = {
1533 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1534 };
1535
1536 static void wm8996_update_bclk(struct snd_soc_codec *codec)
1537 {
1538 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1539 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1540
1541 /* Don't bother if we're in a low frequency idle mode that
1542 * can't support audio.
1543 */
1544 if (wm8996->sysclk < 64000)
1545 return;
1546
1547 for (aif = 0; aif < WM8996_AIFS; aif++) {
1548 switch (aif) {
1549 case 0:
1550 bclk_reg = WM8996_AIF1_BCLK;
1551 break;
1552 case 1:
1553 bclk_reg = WM8996_AIF2_BCLK;
1554 break;
1555 }
1556
1557 bclk_rate = wm8996->bclk_rate[aif];
1558
1559 /* Pick a divisor for BCLK as close as we can get to ideal */
1560 best = 0;
1561 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1562 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1563 if (cur_val < 0) /* BCLK table is sorted */
1564 break;
1565 best = i;
1566 }
1567 bclk_rate = wm8996->sysclk / bclk_divs[best];
1568 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1569 bclk_divs[best], bclk_rate);
1570
1571 snd_soc_update_bits(codec, bclk_reg,
1572 WM8996_AIF1_BCLK_DIV_MASK, best);
1573 }
1574 }
1575
1576 static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1577 enum snd_soc_bias_level level)
1578 {
1579 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1580 int ret;
1581
1582 switch (level) {
1583 case SND_SOC_BIAS_ON:
1584 break;
1585 case SND_SOC_BIAS_PREPARE:
1586 /* Put the MICBIASes into regulating mode */
1587 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1588 WM8996_MICB1_MODE, 0);
1589 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1590 WM8996_MICB2_MODE, 0);
1591 break;
1592
1593 case SND_SOC_BIAS_STANDBY:
1594 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1595 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1596 wm8996->supplies);
1597 if (ret != 0) {
1598 dev_err(codec->dev,
1599 "Failed to enable supplies: %d\n",
1600 ret);
1601 return ret;
1602 }
1603
1604 if (wm8996->pdata.ldo_ena >= 0) {
1605 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1606 1);
1607 msleep(5);
1608 }
1609
1610 regcache_cache_only(wm8996->regmap, false);
1611 regcache_sync(wm8996->regmap);
1612 }
1613
1614 /* Bypass the MICBIASes for lowest power */
1615 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1616 WM8996_MICB1_MODE, WM8996_MICB1_MODE);
1617 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1618 WM8996_MICB2_MODE, WM8996_MICB2_MODE);
1619 break;
1620
1621 case SND_SOC_BIAS_OFF:
1622 regcache_cache_only(wm8996->regmap, true);
1623 if (wm8996->pdata.ldo_ena >= 0) {
1624 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1625 regcache_cache_only(wm8996->regmap, true);
1626 }
1627 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1628 wm8996->supplies);
1629 break;
1630 }
1631
1632 codec->dapm.bias_level = level;
1633
1634 return 0;
1635 }
1636
1637 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1638 {
1639 struct snd_soc_codec *codec = dai->codec;
1640 int aifctrl = 0;
1641 int bclk = 0;
1642 int lrclk_tx = 0;
1643 int lrclk_rx = 0;
1644 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1645
1646 switch (dai->id) {
1647 case 0:
1648 aifctrl_reg = WM8996_AIF1_CONTROL;
1649 bclk_reg = WM8996_AIF1_BCLK;
1650 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1651 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1652 break;
1653 case 1:
1654 aifctrl_reg = WM8996_AIF2_CONTROL;
1655 bclk_reg = WM8996_AIF2_BCLK;
1656 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1657 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1658 break;
1659 default:
1660 WARN(1, "Invalid dai id %d\n", dai->id);
1661 return -EINVAL;
1662 }
1663
1664 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1665 case SND_SOC_DAIFMT_NB_NF:
1666 break;
1667 case SND_SOC_DAIFMT_IB_NF:
1668 bclk |= WM8996_AIF1_BCLK_INV;
1669 break;
1670 case SND_SOC_DAIFMT_NB_IF:
1671 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1672 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1673 break;
1674 case SND_SOC_DAIFMT_IB_IF:
1675 bclk |= WM8996_AIF1_BCLK_INV;
1676 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1677 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1678 break;
1679 }
1680
1681 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1682 case SND_SOC_DAIFMT_CBS_CFS:
1683 break;
1684 case SND_SOC_DAIFMT_CBS_CFM:
1685 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1686 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1687 break;
1688 case SND_SOC_DAIFMT_CBM_CFS:
1689 bclk |= WM8996_AIF1_BCLK_MSTR;
1690 break;
1691 case SND_SOC_DAIFMT_CBM_CFM:
1692 bclk |= WM8996_AIF1_BCLK_MSTR;
1693 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1694 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1695 break;
1696 default:
1697 return -EINVAL;
1698 }
1699
1700 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1701 case SND_SOC_DAIFMT_DSP_A:
1702 break;
1703 case SND_SOC_DAIFMT_DSP_B:
1704 aifctrl |= 1;
1705 break;
1706 case SND_SOC_DAIFMT_I2S:
1707 aifctrl |= 2;
1708 break;
1709 case SND_SOC_DAIFMT_LEFT_J:
1710 aifctrl |= 3;
1711 break;
1712 default:
1713 return -EINVAL;
1714 }
1715
1716 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1717 snd_soc_update_bits(codec, bclk_reg,
1718 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1719 bclk);
1720 snd_soc_update_bits(codec, lrclk_tx_reg,
1721 WM8996_AIF1TX_LRCLK_INV |
1722 WM8996_AIF1TX_LRCLK_MSTR,
1723 lrclk_tx);
1724 snd_soc_update_bits(codec, lrclk_rx_reg,
1725 WM8996_AIF1RX_LRCLK_INV |
1726 WM8996_AIF1RX_LRCLK_MSTR,
1727 lrclk_rx);
1728
1729 return 0;
1730 }
1731
1732 static const int dsp_divs[] = {
1733 48000, 32000, 16000, 8000
1734 };
1735
1736 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1737 struct snd_pcm_hw_params *params,
1738 struct snd_soc_dai *dai)
1739 {
1740 struct snd_soc_codec *codec = dai->codec;
1741 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1742 int bits, i, bclk_rate, best;
1743 int aifdata = 0;
1744 int lrclk = 0;
1745 int dsp = 0;
1746 int aifdata_reg, lrclk_reg, dsp_shift;
1747
1748 switch (dai->id) {
1749 case 0:
1750 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1751 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1752 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1753 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1754 } else {
1755 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1756 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1757 }
1758 dsp_shift = 0;
1759 break;
1760 case 1:
1761 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1762 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1763 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1764 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1765 } else {
1766 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1767 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1768 }
1769 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1770 break;
1771 default:
1772 WARN(1, "Invalid dai id %d\n", dai->id);
1773 return -EINVAL;
1774 }
1775
1776 bclk_rate = snd_soc_params_to_bclk(params);
1777 if (bclk_rate < 0) {
1778 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1779 return bclk_rate;
1780 }
1781
1782 wm8996->bclk_rate[dai->id] = bclk_rate;
1783 wm8996->rx_rate[dai->id] = params_rate(params);
1784
1785 /* Needs looking at for TDM */
1786 bits = snd_pcm_format_width(params_format(params));
1787 if (bits < 0)
1788 return bits;
1789 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1790
1791 best = 0;
1792 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1793 if (abs(dsp_divs[i] - params_rate(params)) <
1794 abs(dsp_divs[best] - params_rate(params)))
1795 best = i;
1796 }
1797 dsp |= i << dsp_shift;
1798
1799 wm8996_update_bclk(codec);
1800
1801 lrclk = bclk_rate / params_rate(params);
1802 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1803 lrclk, bclk_rate / lrclk);
1804
1805 snd_soc_update_bits(codec, aifdata_reg,
1806 WM8996_AIF1TX_WL_MASK |
1807 WM8996_AIF1TX_SLOT_LEN_MASK,
1808 aifdata);
1809 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1810 lrclk);
1811 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1812 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1813
1814 return 0;
1815 }
1816
1817 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1818 int clk_id, unsigned int freq, int dir)
1819 {
1820 struct snd_soc_codec *codec = dai->codec;
1821 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1822 int lfclk = 0;
1823 int ratediv = 0;
1824 int sync = WM8996_REG_SYNC;
1825 int src;
1826 int old;
1827
1828 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1829 return 0;
1830
1831 /* Disable SYSCLK while we reconfigure */
1832 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1833 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1834 WM8996_SYSCLK_ENA, 0);
1835
1836 switch (clk_id) {
1837 case WM8996_SYSCLK_MCLK1:
1838 wm8996->sysclk = freq;
1839 src = 0;
1840 break;
1841 case WM8996_SYSCLK_MCLK2:
1842 wm8996->sysclk = freq;
1843 src = 1;
1844 break;
1845 case WM8996_SYSCLK_FLL:
1846 wm8996->sysclk = freq;
1847 src = 2;
1848 break;
1849 default:
1850 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1851 return -EINVAL;
1852 }
1853
1854 switch (wm8996->sysclk) {
1855 case 5644800:
1856 case 6144000:
1857 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1858 WM8996_SYSCLK_RATE, 0);
1859 break;
1860 case 22579200:
1861 case 24576000:
1862 ratediv = WM8996_SYSCLK_DIV;
1863 wm8996->sysclk /= 2;
1864 case 11289600:
1865 case 12288000:
1866 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1867 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1868 break;
1869 case 32000:
1870 case 32768:
1871 lfclk = WM8996_LFCLK_ENA;
1872 sync = 0;
1873 break;
1874 default:
1875 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1876 wm8996->sysclk);
1877 return -EINVAL;
1878 }
1879
1880 wm8996_update_bclk(codec);
1881
1882 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1883 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1884 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1885 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1886 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
1887 WM8996_REG_SYNC, sync);
1888 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1889 WM8996_SYSCLK_ENA, old);
1890
1891 wm8996->sysclk_src = clk_id;
1892
1893 return 0;
1894 }
1895
1896 struct _fll_div {
1897 u16 fll_fratio;
1898 u16 fll_outdiv;
1899 u16 fll_refclk_div;
1900 u16 fll_loop_gain;
1901 u16 fll_ref_freq;
1902 u16 n;
1903 u16 theta;
1904 u16 lambda;
1905 };
1906
1907 static struct {
1908 unsigned int min;
1909 unsigned int max;
1910 u16 fll_fratio;
1911 int ratio;
1912 } fll_fratios[] = {
1913 { 0, 64000, 4, 16 },
1914 { 64000, 128000, 3, 8 },
1915 { 128000, 256000, 2, 4 },
1916 { 256000, 1000000, 1, 2 },
1917 { 1000000, 13500000, 0, 1 },
1918 };
1919
1920 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1921 unsigned int Fout)
1922 {
1923 unsigned int target;
1924 unsigned int div;
1925 unsigned int fratio, gcd_fll;
1926 int i;
1927
1928 /* Fref must be <=13.5MHz */
1929 div = 1;
1930 fll_div->fll_refclk_div = 0;
1931 while ((Fref / div) > 13500000) {
1932 div *= 2;
1933 fll_div->fll_refclk_div++;
1934
1935 if (div > 8) {
1936 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1937 Fref);
1938 return -EINVAL;
1939 }
1940 }
1941
1942 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1943
1944 /* Apply the division for our remaining calculations */
1945 Fref /= div;
1946
1947 if (Fref >= 3000000)
1948 fll_div->fll_loop_gain = 5;
1949 else
1950 fll_div->fll_loop_gain = 0;
1951
1952 if (Fref >= 48000)
1953 fll_div->fll_ref_freq = 0;
1954 else
1955 fll_div->fll_ref_freq = 1;
1956
1957 /* Fvco should be 90-100MHz; don't check the upper bound */
1958 div = 2;
1959 while (Fout * div < 90000000) {
1960 div++;
1961 if (div > 64) {
1962 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1963 Fout);
1964 return -EINVAL;
1965 }
1966 }
1967 target = Fout * div;
1968 fll_div->fll_outdiv = div - 1;
1969
1970 pr_debug("FLL Fvco=%dHz\n", target);
1971
1972 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1973 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1974 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1975 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1976 fratio = fll_fratios[i].ratio;
1977 break;
1978 }
1979 }
1980 if (i == ARRAY_SIZE(fll_fratios)) {
1981 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1982 return -EINVAL;
1983 }
1984
1985 fll_div->n = target / (fratio * Fref);
1986
1987 if (target % Fref == 0) {
1988 fll_div->theta = 0;
1989 fll_div->lambda = 0;
1990 } else {
1991 gcd_fll = gcd(target, fratio * Fref);
1992
1993 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1994 / gcd_fll;
1995 fll_div->lambda = (fratio * Fref) / gcd_fll;
1996 }
1997
1998 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1999 fll_div->n, fll_div->theta, fll_div->lambda);
2000 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2001 fll_div->fll_fratio, fll_div->fll_outdiv,
2002 fll_div->fll_refclk_div);
2003
2004 return 0;
2005 }
2006
2007 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2008 unsigned int Fref, unsigned int Fout)
2009 {
2010 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2011 struct i2c_client *i2c = to_i2c_client(codec->dev);
2012 struct _fll_div fll_div;
2013 unsigned long timeout;
2014 int ret, reg, retry;
2015
2016 /* Any change? */
2017 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2018 Fout == wm8996->fll_fout)
2019 return 0;
2020
2021 if (Fout == 0) {
2022 dev_dbg(codec->dev, "FLL disabled\n");
2023
2024 wm8996->fll_fref = 0;
2025 wm8996->fll_fout = 0;
2026
2027 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2028 WM8996_FLL_ENA, 0);
2029
2030 wm8996_bg_disable(codec);
2031
2032 return 0;
2033 }
2034
2035 ret = fll_factors(&fll_div, Fref, Fout);
2036 if (ret != 0)
2037 return ret;
2038
2039 switch (source) {
2040 case WM8996_FLL_MCLK1:
2041 reg = 0;
2042 break;
2043 case WM8996_FLL_MCLK2:
2044 reg = 1;
2045 break;
2046 case WM8996_FLL_DACLRCLK1:
2047 reg = 2;
2048 break;
2049 case WM8996_FLL_BCLK1:
2050 reg = 3;
2051 break;
2052 default:
2053 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2054 return -EINVAL;
2055 }
2056
2057 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2058 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2059
2060 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2061 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2062 WM8996_FLL_REFCLK_SRC_MASK, reg);
2063
2064 reg = 0;
2065 if (fll_div.theta || fll_div.lambda)
2066 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2067 else
2068 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2069 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2070
2071 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2072 WM8996_FLL_OUTDIV_MASK |
2073 WM8996_FLL_FRATIO_MASK,
2074 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2075 (fll_div.fll_fratio));
2076
2077 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2078
2079 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2080 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2081 (fll_div.n << WM8996_FLL_N_SHIFT) |
2082 fll_div.fll_loop_gain);
2083
2084 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2085
2086 /* Enable the bandgap if it's not already enabled */
2087 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2088 if (!(ret & WM8996_FLL_ENA))
2089 wm8996_bg_enable(codec);
2090
2091 /* Clear any pending completions (eg, from failed startups) */
2092 try_wait_for_completion(&wm8996->fll_lock);
2093
2094 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2095 WM8996_FLL_ENA, WM8996_FLL_ENA);
2096
2097 /* The FLL supports live reconfiguration - kick that in case we were
2098 * already enabled.
2099 */
2100 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2101
2102 /* Wait for the FLL to lock, using the interrupt if possible */
2103 if (Fref > 1000000)
2104 timeout = usecs_to_jiffies(300);
2105 else
2106 timeout = msecs_to_jiffies(2);
2107
2108 /* Allow substantially longer if we've actually got the IRQ, poll
2109 * at a slightly higher rate if we don't.
2110 */
2111 if (i2c->irq)
2112 timeout *= 10;
2113 else
2114 timeout /= 2;
2115
2116 for (retry = 0; retry < 10; retry++) {
2117 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2118 timeout);
2119 if (ret != 0) {
2120 WARN_ON(!i2c->irq);
2121 break;
2122 }
2123
2124 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2125 if (ret & WM8996_FLL_LOCK_STS)
2126 break;
2127 }
2128 if (retry == 10) {
2129 dev_err(codec->dev, "Timed out waiting for FLL\n");
2130 ret = -ETIMEDOUT;
2131 }
2132
2133 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2134
2135 wm8996->fll_fref = Fref;
2136 wm8996->fll_fout = Fout;
2137 wm8996->fll_src = source;
2138
2139 return ret;
2140 }
2141
2142 #ifdef CONFIG_GPIOLIB
2143 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2144 {
2145 return container_of(chip, struct wm8996_priv, gpio_chip);
2146 }
2147
2148 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2149 {
2150 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2151
2152 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2153 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2154 }
2155
2156 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2157 unsigned offset, int value)
2158 {
2159 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2160 int val;
2161
2162 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2163
2164 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2165 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2166 WM8996_GP1_LVL, val);
2167 }
2168
2169 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2170 {
2171 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2172 unsigned int reg;
2173 int ret;
2174
2175 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
2176 if (ret < 0)
2177 return ret;
2178
2179 return (reg & WM8996_GP1_LVL) != 0;
2180 }
2181
2182 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2183 {
2184 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2185
2186 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2187 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2188 (1 << WM8996_GP1_FN_SHIFT) |
2189 (1 << WM8996_GP1_DIR_SHIFT));
2190 }
2191
2192 static struct gpio_chip wm8996_template_chip = {
2193 .label = "wm8996",
2194 .owner = THIS_MODULE,
2195 .direction_output = wm8996_gpio_direction_out,
2196 .set = wm8996_gpio_set,
2197 .direction_input = wm8996_gpio_direction_in,
2198 .get = wm8996_gpio_get,
2199 .can_sleep = 1,
2200 };
2201
2202 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2203 {
2204 int ret;
2205
2206 wm8996->gpio_chip = wm8996_template_chip;
2207 wm8996->gpio_chip.ngpio = 5;
2208 wm8996->gpio_chip.dev = wm8996->dev;
2209
2210 if (wm8996->pdata.gpio_base)
2211 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2212 else
2213 wm8996->gpio_chip.base = -1;
2214
2215 ret = gpiochip_add(&wm8996->gpio_chip);
2216 if (ret != 0)
2217 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2218 }
2219
2220 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2221 {
2222 int ret;
2223
2224 ret = gpiochip_remove(&wm8996->gpio_chip);
2225 if (ret != 0)
2226 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
2227 }
2228 #else
2229 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2230 {
2231 }
2232
2233 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2234 {
2235 }
2236 #endif
2237
2238 /**
2239 * wm8996_detect - Enable default WM8996 jack detection
2240 *
2241 * The WM8996 has advanced accessory detection support for headsets.
2242 * This function provides a default implementation which integrates
2243 * the majority of this functionality with minimal user configuration.
2244 *
2245 * This will detect headset, headphone and short circuit button and
2246 * will also detect inverted microphone ground connections and update
2247 * the polarity of the connections.
2248 */
2249 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2250 wm8996_polarity_fn polarity_cb)
2251 {
2252 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2253 struct snd_soc_dapm_context *dapm = &codec->dapm;
2254
2255 wm8996->jack = jack;
2256 wm8996->detecting = true;
2257 wm8996->polarity_cb = polarity_cb;
2258 wm8996->jack_flips = 0;
2259
2260 if (wm8996->polarity_cb)
2261 wm8996->polarity_cb(codec, 0);
2262
2263 /* Clear discarge to avoid noise during detection */
2264 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2265 WM8996_MICB1_DISCH, 0);
2266 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2267 WM8996_MICB2_DISCH, 0);
2268
2269 /* LDO2 powers the microphones, SYSCLK clocks detection */
2270 snd_soc_dapm_mutex_lock(dapm);
2271
2272 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2273 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2274
2275 snd_soc_dapm_mutex_unlock(dapm);
2276
2277 /* We start off just enabling microphone detection - even a
2278 * plain headphone will trigger detection.
2279 */
2280 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2281 WM8996_MICD_ENA, WM8996_MICD_ENA);
2282
2283 /* Slowest detection rate, gives debounce for initial detection */
2284 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2285 WM8996_MICD_RATE_MASK,
2286 WM8996_MICD_RATE_MASK);
2287
2288 /* Enable interrupts and we're off */
2289 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2290 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2291
2292 return 0;
2293 }
2294 EXPORT_SYMBOL_GPL(wm8996_detect);
2295
2296 static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2297 {
2298 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2299 int val, reg, report;
2300
2301 /* Assume headphone in error conditions; we need to report
2302 * something or we stall our state machine.
2303 */
2304 report = SND_JACK_HEADPHONE;
2305
2306 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2307 if (reg < 0) {
2308 dev_err(codec->dev, "Failed to read HPDET status\n");
2309 goto out;
2310 }
2311
2312 if (!(reg & WM8996_HP_DONE)) {
2313 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2314 goto out;
2315 }
2316
2317 val = reg & WM8996_HP_LVL_MASK;
2318
2319 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2320
2321 /* If we've got high enough impedence then report as line,
2322 * otherwise assume headphone.
2323 */
2324 if (val >= 126)
2325 report = SND_JACK_LINEOUT;
2326 else
2327 report = SND_JACK_HEADPHONE;
2328
2329 out:
2330 if (wm8996->jack_mic)
2331 report |= SND_JACK_MICROPHONE;
2332
2333 snd_soc_jack_report(wm8996->jack, report,
2334 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2335
2336 wm8996->detecting = false;
2337
2338 /* If the output isn't running re-clamp it */
2339 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2340 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2341 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2342 WM8996_HPOUT1L_RMV_SHORT |
2343 WM8996_HPOUT1R_RMV_SHORT, 0);
2344
2345 /* Go back to looking at the microphone */
2346 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2347 WM8996_JD_MODE_MASK, 0);
2348 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2349 WM8996_MICD_ENA);
2350
2351 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2352 snd_soc_dapm_sync(&codec->dapm);
2353 }
2354
2355 static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2356 {
2357 /* Unclamp the output, we can't measure while we're shorting it */
2358 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2359 WM8996_HPOUT1L_RMV_SHORT |
2360 WM8996_HPOUT1R_RMV_SHORT,
2361 WM8996_HPOUT1L_RMV_SHORT |
2362 WM8996_HPOUT1R_RMV_SHORT);
2363
2364 /* We need bandgap for HPDET */
2365 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2366 snd_soc_dapm_sync(&codec->dapm);
2367
2368 /* Go into headphone detect left mode */
2369 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2370 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2371 WM8996_JD_MODE_MASK, 1);
2372
2373 /* Trigger a measurement */
2374 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2375 WM8996_HP_POLL, WM8996_HP_POLL);
2376 }
2377
2378 static void wm8996_report_headphone(struct snd_soc_codec *codec)
2379 {
2380 dev_dbg(codec->dev, "Headphone detected\n");
2381 wm8996_hpdet_start(codec);
2382
2383 /* Increase the detection rate a bit for responsiveness. */
2384 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2385 WM8996_MICD_RATE_MASK |
2386 WM8996_MICD_BIAS_STARTTIME_MASK,
2387 7 << WM8996_MICD_RATE_SHIFT |
2388 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2389 }
2390
2391 static void wm8996_micd(struct snd_soc_codec *codec)
2392 {
2393 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2394 int val, reg;
2395
2396 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2397
2398 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2399
2400 if (!(val & WM8996_MICD_VALID)) {
2401 dev_warn(codec->dev, "Microphone detection state invalid\n");
2402 return;
2403 }
2404
2405 /* No accessory, reset everything and report removal */
2406 if (!(val & WM8996_MICD_STS)) {
2407 dev_dbg(codec->dev, "Jack removal detected\n");
2408 wm8996->jack_mic = false;
2409 wm8996->detecting = true;
2410 wm8996->jack_flips = 0;
2411 snd_soc_jack_report(wm8996->jack, 0,
2412 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2413 SND_JACK_BTN_0);
2414
2415 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2416 WM8996_MICD_RATE_MASK |
2417 WM8996_MICD_BIAS_STARTTIME_MASK,
2418 WM8996_MICD_RATE_MASK |
2419 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2420 return;
2421 }
2422
2423 /* If the measurement is very high we've got a microphone,
2424 * either we just detected one or if we already reported then
2425 * we've got a button release event.
2426 */
2427 if (val & 0x400) {
2428 if (wm8996->detecting) {
2429 dev_dbg(codec->dev, "Microphone detected\n");
2430 wm8996->jack_mic = true;
2431 wm8996_hpdet_start(codec);
2432
2433 /* Increase poll rate to give better responsiveness
2434 * for buttons */
2435 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2436 WM8996_MICD_RATE_MASK |
2437 WM8996_MICD_BIAS_STARTTIME_MASK,
2438 5 << WM8996_MICD_RATE_SHIFT |
2439 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2440 } else {
2441 dev_dbg(codec->dev, "Mic button up\n");
2442 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2443 }
2444
2445 return;
2446 }
2447
2448 /* If we detected a lower impedence during initial startup
2449 * then we probably have the wrong polarity, flip it. Don't
2450 * do this for the lowest impedences to speed up detection of
2451 * plain headphones. If both polarities report a low
2452 * impedence then give up and report headphones.
2453 */
2454 if (wm8996->detecting && (val & 0x3f0)) {
2455 wm8996->jack_flips++;
2456
2457 if (wm8996->jack_flips > 1) {
2458 wm8996_report_headphone(codec);
2459 return;
2460 }
2461
2462 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2463 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2464 WM8996_MICD_BIAS_SRC;
2465 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2466 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2467 WM8996_MICD_BIAS_SRC, reg);
2468
2469 if (wm8996->polarity_cb)
2470 wm8996->polarity_cb(codec,
2471 (reg & WM8996_MICD_SRC) != 0);
2472
2473 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2474 (reg & WM8996_MICD_SRC) != 0);
2475
2476 return;
2477 }
2478
2479 /* Don't distinguish between buttons, just report any low
2480 * impedence as BTN_0.
2481 */
2482 if (val & 0x3fc) {
2483 if (wm8996->jack_mic) {
2484 dev_dbg(codec->dev, "Mic button detected\n");
2485 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2486 SND_JACK_BTN_0);
2487 } else if (wm8996->detecting) {
2488 wm8996_report_headphone(codec);
2489 }
2490 }
2491 }
2492
2493 static irqreturn_t wm8996_irq(int irq, void *data)
2494 {
2495 struct snd_soc_codec *codec = data;
2496 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2497 int irq_val;
2498
2499 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2500 if (irq_val < 0) {
2501 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2502 irq_val);
2503 return IRQ_NONE;
2504 }
2505 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2506
2507 if (!irq_val)
2508 return IRQ_NONE;
2509
2510 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2511
2512 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2513 dev_dbg(codec->dev, "DC servo IRQ\n");
2514 complete(&wm8996->dcs_done);
2515 }
2516
2517 if (irq_val & WM8996_FIFOS_ERR_EINT)
2518 dev_err(codec->dev, "Digital core FIFO error\n");
2519
2520 if (irq_val & WM8996_FLL_LOCK_EINT) {
2521 dev_dbg(codec->dev, "FLL locked\n");
2522 complete(&wm8996->fll_lock);
2523 }
2524
2525 if (irq_val & WM8996_MICD_EINT)
2526 wm8996_micd(codec);
2527
2528 if (irq_val & WM8996_HP_DONE_EINT)
2529 wm8996_hpdet_irq(codec);
2530
2531 return IRQ_HANDLED;
2532 }
2533
2534 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2535 {
2536 irqreturn_t ret = IRQ_NONE;
2537 irqreturn_t val;
2538
2539 do {
2540 val = wm8996_irq(irq, data);
2541 if (val != IRQ_NONE)
2542 ret = val;
2543 } while (val != IRQ_NONE);
2544
2545 return ret;
2546 }
2547
2548 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2549 {
2550 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2551 struct wm8996_pdata *pdata = &wm8996->pdata;
2552
2553 struct snd_kcontrol_new controls[] = {
2554 SOC_ENUM_EXT("DSP1 EQ Mode",
2555 wm8996->retune_mobile_enum,
2556 wm8996_get_retune_mobile_enum,
2557 wm8996_put_retune_mobile_enum),
2558 SOC_ENUM_EXT("DSP2 EQ Mode",
2559 wm8996->retune_mobile_enum,
2560 wm8996_get_retune_mobile_enum,
2561 wm8996_put_retune_mobile_enum),
2562 };
2563 int ret, i, j;
2564 const char **t;
2565
2566 /* We need an array of texts for the enum API but the number
2567 * of texts is likely to be less than the number of
2568 * configurations due to the sample rate dependency of the
2569 * configurations. */
2570 wm8996->num_retune_mobile_texts = 0;
2571 wm8996->retune_mobile_texts = NULL;
2572 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2573 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2574 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2575 wm8996->retune_mobile_texts[j]) == 0)
2576 break;
2577 }
2578
2579 if (j != wm8996->num_retune_mobile_texts)
2580 continue;
2581
2582 /* Expand the array... */
2583 t = krealloc(wm8996->retune_mobile_texts,
2584 sizeof(char *) *
2585 (wm8996->num_retune_mobile_texts + 1),
2586 GFP_KERNEL);
2587 if (t == NULL)
2588 continue;
2589
2590 /* ...store the new entry... */
2591 t[wm8996->num_retune_mobile_texts] =
2592 pdata->retune_mobile_cfgs[i].name;
2593
2594 /* ...and remember the new version. */
2595 wm8996->num_retune_mobile_texts++;
2596 wm8996->retune_mobile_texts = t;
2597 }
2598
2599 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2600 wm8996->num_retune_mobile_texts);
2601
2602 wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts;
2603 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2604
2605 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2606 if (ret != 0)
2607 dev_err(codec->dev,
2608 "Failed to add ReTune Mobile controls: %d\n", ret);
2609 }
2610
2611 static const struct regmap_config wm8996_regmap = {
2612 .reg_bits = 16,
2613 .val_bits = 16,
2614
2615 .max_register = WM8996_MAX_REGISTER,
2616 .reg_defaults = wm8996_reg,
2617 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2618 .volatile_reg = wm8996_volatile_register,
2619 .readable_reg = wm8996_readable_register,
2620 .cache_type = REGCACHE_RBTREE,
2621 };
2622
2623 static int wm8996_probe(struct snd_soc_codec *codec)
2624 {
2625 int ret;
2626 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2627 struct i2c_client *i2c = to_i2c_client(codec->dev);
2628 int irq_flags;
2629
2630 wm8996->codec = codec;
2631
2632 init_completion(&wm8996->dcs_done);
2633 init_completion(&wm8996->fll_lock);
2634
2635 if (wm8996->pdata.num_retune_mobile_cfgs)
2636 wm8996_retune_mobile_pdata(codec);
2637 else
2638 snd_soc_add_codec_controls(codec, wm8996_eq_controls,
2639 ARRAY_SIZE(wm8996_eq_controls));
2640
2641 if (i2c->irq) {
2642 if (wm8996->pdata.irq_flags)
2643 irq_flags = wm8996->pdata.irq_flags;
2644 else
2645 irq_flags = IRQF_TRIGGER_LOW;
2646
2647 irq_flags |= IRQF_ONESHOT;
2648
2649 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2650 ret = request_threaded_irq(i2c->irq, NULL,
2651 wm8996_edge_irq,
2652 irq_flags, "wm8996", codec);
2653 else
2654 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2655 irq_flags, "wm8996", codec);
2656
2657 if (ret == 0) {
2658 /* Unmask the interrupt */
2659 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2660 WM8996_IM_IRQ, 0);
2661
2662 /* Enable error reporting and DC servo status */
2663 snd_soc_update_bits(codec,
2664 WM8996_INTERRUPT_STATUS_2_MASK,
2665 WM8996_IM_DCS_DONE_23_EINT |
2666 WM8996_IM_DCS_DONE_01_EINT |
2667 WM8996_IM_FLL_LOCK_EINT |
2668 WM8996_IM_FIFOS_ERR_EINT,
2669 0);
2670 } else {
2671 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2672 ret);
2673 return ret;
2674 }
2675 }
2676
2677 return 0;
2678 }
2679
2680 static int wm8996_remove(struct snd_soc_codec *codec)
2681 {
2682 struct i2c_client *i2c = to_i2c_client(codec->dev);
2683
2684 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2685 WM8996_IM_IRQ, WM8996_IM_IRQ);
2686
2687 if (i2c->irq)
2688 free_irq(i2c->irq, codec);
2689
2690 return 0;
2691 }
2692
2693 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2694 .probe = wm8996_probe,
2695 .remove = wm8996_remove,
2696 .set_bias_level = wm8996_set_bias_level,
2697 .idle_bias_off = true,
2698 .seq_notifier = wm8996_seq_notifier,
2699 .controls = wm8996_snd_controls,
2700 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2701 .dapm_widgets = wm8996_dapm_widgets,
2702 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2703 .dapm_routes = wm8996_dapm_routes,
2704 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2705 .set_pll = wm8996_set_fll,
2706 };
2707
2708 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2709 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
2710 SNDRV_PCM_RATE_48000)
2711 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2712 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2713 SNDRV_PCM_FMTBIT_S32_LE)
2714
2715 static const struct snd_soc_dai_ops wm8996_dai_ops = {
2716 .set_fmt = wm8996_set_fmt,
2717 .hw_params = wm8996_hw_params,
2718 .set_sysclk = wm8996_set_sysclk,
2719 };
2720
2721 static struct snd_soc_dai_driver wm8996_dai[] = {
2722 {
2723 .name = "wm8996-aif1",
2724 .playback = {
2725 .stream_name = "AIF1 Playback",
2726 .channels_min = 1,
2727 .channels_max = 6,
2728 .rates = WM8996_RATES,
2729 .formats = WM8996_FORMATS,
2730 .sig_bits = 24,
2731 },
2732 .capture = {
2733 .stream_name = "AIF1 Capture",
2734 .channels_min = 1,
2735 .channels_max = 6,
2736 .rates = WM8996_RATES,
2737 .formats = WM8996_FORMATS,
2738 .sig_bits = 24,
2739 },
2740 .ops = &wm8996_dai_ops,
2741 },
2742 {
2743 .name = "wm8996-aif2",
2744 .playback = {
2745 .stream_name = "AIF2 Playback",
2746 .channels_min = 1,
2747 .channels_max = 2,
2748 .rates = WM8996_RATES,
2749 .formats = WM8996_FORMATS,
2750 .sig_bits = 24,
2751 },
2752 .capture = {
2753 .stream_name = "AIF2 Capture",
2754 .channels_min = 1,
2755 .channels_max = 2,
2756 .rates = WM8996_RATES,
2757 .formats = WM8996_FORMATS,
2758 .sig_bits = 24,
2759 },
2760 .ops = &wm8996_dai_ops,
2761 },
2762 };
2763
2764 static int wm8996_i2c_probe(struct i2c_client *i2c,
2765 const struct i2c_device_id *id)
2766 {
2767 struct wm8996_priv *wm8996;
2768 int ret, i;
2769 unsigned int reg;
2770
2771 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
2772 GFP_KERNEL);
2773 if (wm8996 == NULL)
2774 return -ENOMEM;
2775
2776 i2c_set_clientdata(i2c, wm8996);
2777 wm8996->dev = &i2c->dev;
2778
2779 if (dev_get_platdata(&i2c->dev))
2780 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2781 sizeof(wm8996->pdata));
2782
2783 if (wm8996->pdata.ldo_ena > 0) {
2784 ret = gpio_request_one(wm8996->pdata.ldo_ena,
2785 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2786 if (ret < 0) {
2787 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2788 wm8996->pdata.ldo_ena, ret);
2789 goto err;
2790 }
2791 }
2792
2793 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2794 wm8996->supplies[i].supply = wm8996_supply_names[i];
2795
2796 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
2797 wm8996->supplies);
2798 if (ret != 0) {
2799 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2800 goto err_gpio;
2801 }
2802
2803 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2804 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2805 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2806
2807 /* This should really be moved into the regulator core */
2808 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2809 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2810 &wm8996->disable_nb[i]);
2811 if (ret != 0) {
2812 dev_err(&i2c->dev,
2813 "Failed to register regulator notifier: %d\n",
2814 ret);
2815 }
2816 }
2817
2818 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2819 wm8996->supplies);
2820 if (ret != 0) {
2821 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2822 goto err_gpio;
2823 }
2824
2825 if (wm8996->pdata.ldo_ena > 0) {
2826 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2827 msleep(5);
2828 }
2829
2830 wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
2831 if (IS_ERR(wm8996->regmap)) {
2832 ret = PTR_ERR(wm8996->regmap);
2833 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
2834 goto err_enable;
2835 }
2836
2837 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
2838 if (ret < 0) {
2839 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2840 goto err_regmap;
2841 }
2842 if (reg != 0x8915) {
2843 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
2844 ret = -EINVAL;
2845 goto err_regmap;
2846 }
2847
2848 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
2849 if (ret < 0) {
2850 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2851 ret);
2852 goto err_regmap;
2853 }
2854
2855 dev_info(&i2c->dev, "revision %c\n",
2856 (reg & WM8996_CHIP_REV_MASK) + 'A');
2857
2858 if (wm8996->pdata.ldo_ena > 0) {
2859 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2860 regcache_cache_only(wm8996->regmap, true);
2861 } else {
2862 ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
2863 0x8915);
2864 if (ret != 0) {
2865 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2866 goto err_regmap;
2867 }
2868 }
2869
2870 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2871
2872 /* Apply platform data settings */
2873 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
2874 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2875 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2876 wm8996->pdata.inr_mode);
2877
2878 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2879 if (!wm8996->pdata.gpio_default[i])
2880 continue;
2881
2882 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
2883 wm8996->pdata.gpio_default[i] & 0xffff);
2884 }
2885
2886 if (wm8996->pdata.spkmute_seq)
2887 regmap_update_bits(wm8996->regmap,
2888 WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2889 WM8996_SPK_MUTE_ENDIAN |
2890 WM8996_SPK_MUTE_SEQ1_MASK,
2891 wm8996->pdata.spkmute_seq);
2892
2893 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
2894 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2895 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2896
2897 /* Latch volume update bits */
2898 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
2899 WM8996_IN1_VU, WM8996_IN1_VU);
2900 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
2901 WM8996_IN1_VU, WM8996_IN1_VU);
2902
2903 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
2904 WM8996_DAC1_VU, WM8996_DAC1_VU);
2905 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
2906 WM8996_DAC1_VU, WM8996_DAC1_VU);
2907 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
2908 WM8996_DAC2_VU, WM8996_DAC2_VU);
2909 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
2910 WM8996_DAC2_VU, WM8996_DAC2_VU);
2911
2912 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
2913 WM8996_DAC1_VU, WM8996_DAC1_VU);
2914 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
2915 WM8996_DAC1_VU, WM8996_DAC1_VU);
2916 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
2917 WM8996_DAC2_VU, WM8996_DAC2_VU);
2918 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
2919 WM8996_DAC2_VU, WM8996_DAC2_VU);
2920
2921 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
2922 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2923 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
2924 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2925 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
2926 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2927 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
2928 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2929
2930 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
2931 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2932 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
2933 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2934 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
2935 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2936 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
2937 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2938
2939 /* No support currently for the underclocked TDM modes and
2940 * pick a default TDM layout with each channel pair working with
2941 * slots 0 and 1. */
2942 regmap_update_bits(wm8996->regmap,
2943 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2944 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2945 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2946 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2947 regmap_update_bits(wm8996->regmap,
2948 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2949 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2950 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2951 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2952 regmap_update_bits(wm8996->regmap,
2953 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2954 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2955 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2956 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2957 regmap_update_bits(wm8996->regmap,
2958 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2959 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2960 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2961 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2962 regmap_update_bits(wm8996->regmap,
2963 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2964 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2965 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2966 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2967 regmap_update_bits(wm8996->regmap,
2968 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2969 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2970 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2971 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2972
2973 regmap_update_bits(wm8996->regmap,
2974 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2975 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2976 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2977 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2978 regmap_update_bits(wm8996->regmap,
2979 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2980 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2981 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2982 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2983
2984 regmap_update_bits(wm8996->regmap,
2985 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2986 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2987 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2988 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2989 regmap_update_bits(wm8996->regmap,
2990 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2991 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2992 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2993 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2994 regmap_update_bits(wm8996->regmap,
2995 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2996 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2997 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2998 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2999 regmap_update_bits(wm8996->regmap,
3000 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
3001 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
3002 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3003 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
3004 regmap_update_bits(wm8996->regmap,
3005 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
3006 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
3007 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3008 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
3009 regmap_update_bits(wm8996->regmap,
3010 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
3011 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3012 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3013 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3014
3015 regmap_update_bits(wm8996->regmap,
3016 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3017 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3018 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3019 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3020 regmap_update_bits(wm8996->regmap,
3021 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3022 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3023 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3024 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3025
3026 /* If the TX LRCLK pins are not in LRCLK mode configure the
3027 * AIFs to source their clocks from the RX LRCLKs.
3028 */
3029 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, &reg);
3030 if (ret != 0) {
3031 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
3032 goto err_regmap;
3033 }
3034
3035 if (reg & WM8996_GP1_FN_MASK)
3036 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
3037 WM8996_AIF1TX_LRCLK_MODE,
3038 WM8996_AIF1TX_LRCLK_MODE);
3039
3040 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, &reg);
3041 if (ret != 0) {
3042 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
3043 goto err_regmap;
3044 }
3045
3046 if (reg & WM8996_GP2_FN_MASK)
3047 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
3048 WM8996_AIF2TX_LRCLK_MODE,
3049 WM8996_AIF2TX_LRCLK_MODE);
3050
3051 wm8996_init_gpio(wm8996);
3052
3053 ret = snd_soc_register_codec(&i2c->dev,
3054 &soc_codec_dev_wm8996, wm8996_dai,
3055 ARRAY_SIZE(wm8996_dai));
3056 if (ret < 0)
3057 goto err_gpiolib;
3058
3059 return ret;
3060
3061 err_gpiolib:
3062 wm8996_free_gpio(wm8996);
3063 err_regmap:
3064 err_enable:
3065 if (wm8996->pdata.ldo_ena > 0)
3066 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3067 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3068 err_gpio:
3069 if (wm8996->pdata.ldo_ena > 0)
3070 gpio_free(wm8996->pdata.ldo_ena);
3071 err:
3072
3073 return ret;
3074 }
3075
3076 static int wm8996_i2c_remove(struct i2c_client *client)
3077 {
3078 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3079 int i;
3080
3081 snd_soc_unregister_codec(&client->dev);
3082 wm8996_free_gpio(wm8996);
3083 if (wm8996->pdata.ldo_ena > 0) {
3084 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3085 gpio_free(wm8996->pdata.ldo_ena);
3086 }
3087 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3088 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3089 &wm8996->disable_nb[i]);
3090
3091 return 0;
3092 }
3093
3094 static const struct i2c_device_id wm8996_i2c_id[] = {
3095 { "wm8996", 0 },
3096 { }
3097 };
3098 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3099
3100 static struct i2c_driver wm8996_i2c_driver = {
3101 .driver = {
3102 .name = "wm8996",
3103 .owner = THIS_MODULE,
3104 },
3105 .probe = wm8996_i2c_probe,
3106 .remove = wm8996_i2c_remove,
3107 .id_table = wm8996_i2c_id,
3108 };
3109
3110 module_i2c_driver(wm8996_i2c_driver);
3111
3112 MODULE_DESCRIPTION("ASoC WM8996 driver");
3113 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3114 MODULE_LICENSE("GPL");
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