1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm_adsp.c -- Wolfson ADSP support
5 * Copyright 2012 Wolfson Microelectronics plc
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
10 #include <linux/ctype.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/list.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/workqueue.h>
24 #include <linux/debugfs.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
37 #define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
39 #define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
41 #define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
43 #define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
46 #define compr_err(_obj, fmt, ...) \
47 adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
49 #define compr_dbg(_obj, fmt, ...) \
50 adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
53 #define ADSP1_CONTROL_1 0x00
54 #define ADSP1_CONTROL_2 0x02
55 #define ADSP1_CONTROL_3 0x03
56 #define ADSP1_CONTROL_4 0x04
57 #define ADSP1_CONTROL_5 0x06
58 #define ADSP1_CONTROL_6 0x07
59 #define ADSP1_CONTROL_7 0x08
60 #define ADSP1_CONTROL_8 0x09
61 #define ADSP1_CONTROL_9 0x0A
62 #define ADSP1_CONTROL_10 0x0B
63 #define ADSP1_CONTROL_11 0x0C
64 #define ADSP1_CONTROL_12 0x0D
65 #define ADSP1_CONTROL_13 0x0F
66 #define ADSP1_CONTROL_14 0x10
67 #define ADSP1_CONTROL_15 0x11
68 #define ADSP1_CONTROL_16 0x12
69 #define ADSP1_CONTROL_17 0x13
70 #define ADSP1_CONTROL_18 0x14
71 #define ADSP1_CONTROL_19 0x16
72 #define ADSP1_CONTROL_20 0x17
73 #define ADSP1_CONTROL_21 0x18
74 #define ADSP1_CONTROL_22 0x1A
75 #define ADSP1_CONTROL_23 0x1B
76 #define ADSP1_CONTROL_24 0x1C
77 #define ADSP1_CONTROL_25 0x1E
78 #define ADSP1_CONTROL_26 0x20
79 #define ADSP1_CONTROL_27 0x21
80 #define ADSP1_CONTROL_28 0x22
81 #define ADSP1_CONTROL_29 0x23
82 #define ADSP1_CONTROL_30 0x24
83 #define ADSP1_CONTROL_31 0x26
88 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
90 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
96 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
98 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
99 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
100 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
101 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
102 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
103 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
104 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
105 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
106 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
107 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
108 #define ADSP1_START 0x0001 /* DSP1_START */
109 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
110 #define ADSP1_START_SHIFT 0 /* DSP1_START */
111 #define ADSP1_START_WIDTH 1 /* DSP1_START */
116 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
117 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
118 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
120 #define ADSP2_CONTROL 0x0
121 #define ADSP2_CLOCKING 0x1
122 #define ADSP2V2_CLOCKING 0x2
123 #define ADSP2_STATUS1 0x4
124 #define ADSP2_WDMA_CONFIG_1 0x30
125 #define ADSP2_WDMA_CONFIG_2 0x31
126 #define ADSP2V2_WDMA_CONFIG_2 0x32
127 #define ADSP2_RDMA_CONFIG_1 0x34
129 #define ADSP2_SCRATCH0 0x40
130 #define ADSP2_SCRATCH1 0x41
131 #define ADSP2_SCRATCH2 0x42
132 #define ADSP2_SCRATCH3 0x43
134 #define ADSP2V2_SCRATCH0_1 0x40
135 #define ADSP2V2_SCRATCH2_3 0x42
141 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
142 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
143 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
144 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
145 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
146 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
147 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
148 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
149 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
150 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
151 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
152 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
153 #define ADSP2_START 0x0001 /* DSP1_START */
154 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
155 #define ADSP2_START_SHIFT 0 /* DSP1_START */
156 #define ADSP2_START_WIDTH 1 /* DSP1_START */
161 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
162 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
163 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
168 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
169 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
170 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
172 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
173 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
174 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
179 #define ADSP2_RAM_RDY 0x0001
180 #define ADSP2_RAM_RDY_MASK 0x0001
181 #define ADSP2_RAM_RDY_SHIFT 0
182 #define ADSP2_RAM_RDY_WIDTH 1
187 #define ADSP2_LOCK_CODE_0 0x5555
188 #define ADSP2_LOCK_CODE_1 0xAAAA
190 #define ADSP2_WATCHDOG 0x0A
191 #define ADSP2_BUS_ERR_ADDR 0x52
192 #define ADSP2_REGION_LOCK_STATUS 0x64
193 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
194 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
195 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
196 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
197 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
198 #define ADSP2_LOCK_REGION_CTRL 0x7A
199 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
201 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
202 #define ADSP2_SLAVE_ERR_MASK 0x4000
203 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
204 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
205 #define ADSP2_CTRL_ERR_EINT 0x0001
207 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
208 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
209 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
210 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
211 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
213 #define ADSP2_LOCK_REGION_SHIFT 16
215 #define ADSP_MAX_STD_CTRL_SIZE 512
217 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
218 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
219 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
220 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
223 * Event control messages
225 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
230 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040
231 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044
236 #define HALO_SCRATCH1 0x005c0
237 #define HALO_SCRATCH2 0x005c8
238 #define HALO_SCRATCH3 0x005d0
239 #define HALO_SCRATCH4 0x005d8
240 #define HALO_CCM_CORE_CONTROL 0x41000
241 #define HALO_CORE_SOFT_RESET 0x00010
242 #define HALO_WDT_CONTROL 0x47000
247 #define HALO_MPU_XMEM_ACCESS_0 0x43000
248 #define HALO_MPU_YMEM_ACCESS_0 0x43004
249 #define HALO_MPU_WINDOW_ACCESS_0 0x43008
250 #define HALO_MPU_XREG_ACCESS_0 0x4300C
251 #define HALO_MPU_YREG_ACCESS_0 0x43014
252 #define HALO_MPU_XMEM_ACCESS_1 0x43018
253 #define HALO_MPU_YMEM_ACCESS_1 0x4301C
254 #define HALO_MPU_WINDOW_ACCESS_1 0x43020
255 #define HALO_MPU_XREG_ACCESS_1 0x43024
256 #define HALO_MPU_YREG_ACCESS_1 0x4302C
257 #define HALO_MPU_XMEM_ACCESS_2 0x43030
258 #define HALO_MPU_YMEM_ACCESS_2 0x43034
259 #define HALO_MPU_WINDOW_ACCESS_2 0x43038
260 #define HALO_MPU_XREG_ACCESS_2 0x4303C
261 #define HALO_MPU_YREG_ACCESS_2 0x43044
262 #define HALO_MPU_XMEM_ACCESS_3 0x43048
263 #define HALO_MPU_YMEM_ACCESS_3 0x4304C
264 #define HALO_MPU_WINDOW_ACCESS_3 0x43050
265 #define HALO_MPU_XREG_ACCESS_3 0x43054
266 #define HALO_MPU_YREG_ACCESS_3 0x4305C
267 #define HALO_MPU_XM_VIO_ADDR 0x43100
268 #define HALO_MPU_XM_VIO_STATUS 0x43104
269 #define HALO_MPU_YM_VIO_ADDR 0x43108
270 #define HALO_MPU_YM_VIO_STATUS 0x4310C
271 #define HALO_MPU_PM_VIO_ADDR 0x43110
272 #define HALO_MPU_PM_VIO_STATUS 0x43114
273 #define HALO_MPU_LOCK_CONFIG 0x43140
276 * HALO_AHBM_WINDOW_DEBUG_1
278 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00
279 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8
280 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff
283 * HALO_CCM_CORE_CONTROL
285 #define HALO_CORE_EN 0x00000001
288 * HALO_CORE_SOFT_RESET
290 #define HALO_CORE_SOFT_RESET_MASK 0x00000001
295 #define HALO_WDT_EN_MASK 0x00000001
298 * HALO_MPU_?M_VIO_STATUS
300 #define HALO_MPU_VIO_STS_MASK 0x007e0000
301 #define HALO_MPU_VIO_STS_SHIFT 17
302 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000
303 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff
304 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0
306 static struct wm_adsp_ops wm_adsp1_ops
;
307 static struct wm_adsp_ops wm_adsp2_ops
[];
308 static struct wm_adsp_ops wm_halo_ops
;
311 struct list_head list
;
315 static struct wm_adsp_buf
*wm_adsp_buf_alloc(const void *src
, size_t len
,
316 struct list_head
*list
)
318 struct wm_adsp_buf
*buf
= kzalloc(sizeof(*buf
), GFP_KERNEL
);
323 buf
->buf
= vmalloc(len
);
328 memcpy(buf
->buf
, src
, len
);
331 list_add_tail(&buf
->list
, list
);
336 static void wm_adsp_buf_free(struct list_head
*list
)
338 while (!list_empty(list
)) {
339 struct wm_adsp_buf
*buf
= list_first_entry(list
,
342 list_del(&buf
->list
);
348 #define WM_ADSP_FW_MBC_VSS 0
349 #define WM_ADSP_FW_HIFI 1
350 #define WM_ADSP_FW_TX 2
351 #define WM_ADSP_FW_TX_SPK 3
352 #define WM_ADSP_FW_RX 4
353 #define WM_ADSP_FW_RX_ANC 5
354 #define WM_ADSP_FW_CTRL 6
355 #define WM_ADSP_FW_ASR 7
356 #define WM_ADSP_FW_TRACE 8
357 #define WM_ADSP_FW_SPK_PROT 9
358 #define WM_ADSP_FW_MISC 10
360 #define WM_ADSP_NUM_FW 11
362 static const char *wm_adsp_fw_text
[WM_ADSP_NUM_FW
] = {
363 [WM_ADSP_FW_MBC_VSS
] = "MBC/VSS",
364 [WM_ADSP_FW_HIFI
] = "MasterHiFi",
365 [WM_ADSP_FW_TX
] = "Tx",
366 [WM_ADSP_FW_TX_SPK
] = "Tx Speaker",
367 [WM_ADSP_FW_RX
] = "Rx",
368 [WM_ADSP_FW_RX_ANC
] = "Rx ANC",
369 [WM_ADSP_FW_CTRL
] = "Voice Ctrl",
370 [WM_ADSP_FW_ASR
] = "ASR Assist",
371 [WM_ADSP_FW_TRACE
] = "Dbg Trace",
372 [WM_ADSP_FW_SPK_PROT
] = "Protection",
373 [WM_ADSP_FW_MISC
] = "Misc",
376 struct wm_adsp_system_config_xm_hdr
{
382 __be32 dma_buffer_size
;
385 __be32 build_job_name
[3];
386 __be32 build_job_number
;
389 struct wm_halo_system_config_xm_hdr
{
390 __be32 halo_heartbeat
;
391 __be32 build_job_name
[3];
392 __be32 build_job_number
;
395 struct wm_adsp_alg_xm_struct
{
401 __be32 high_water_mark
;
402 __be32 low_water_mark
;
403 __be64 smoothed_power
;
406 struct wm_adsp_host_buf_coeff_v1
{
407 __be32 host_buf_ptr
; /* Host buffer pointer */
408 __be32 versions
; /* Version numbers */
409 __be32 name
[4]; /* The buffer name */
412 struct wm_adsp_buffer
{
413 __be32 buf1_base
; /* Base addr of first buffer area */
414 __be32 buf1_size
; /* Size of buf1 area in DSP words */
415 __be32 buf2_base
; /* Base addr of 2nd buffer area */
416 __be32 buf1_buf2_size
; /* Size of buf1+buf2 in DSP words */
417 __be32 buf3_base
; /* Base addr of buf3 area */
418 __be32 buf_total_size
; /* Size of buf1+buf2+buf3 in DSP words */
419 __be32 high_water_mark
; /* Point at which IRQ is asserted */
420 __be32 irq_count
; /* bits 1-31 count IRQ assertions */
421 __be32 irq_ack
; /* acked IRQ count, bit 0 enables IRQ */
422 __be32 next_write_index
; /* word index of next write */
423 __be32 next_read_index
; /* word index of next read */
424 __be32 error
; /* error if any */
425 __be32 oldest_block_index
; /* word index of oldest surviving */
426 __be32 requested_rewind
; /* how many blocks rewind was done */
427 __be32 reserved_space
; /* internal */
428 __be32 min_free
; /* min free space since stream start */
429 __be32 blocks_written
[2]; /* total blocks written (64 bit) */
430 __be32 words_written
[2]; /* total words written (64 bit) */
433 struct wm_adsp_compr
;
435 struct wm_adsp_compr_buf
{
436 struct list_head list
;
438 struct wm_adsp_compr
*compr
;
440 struct wm_adsp_buffer_region
*regions
;
447 int host_buf_mem_type
;
452 struct wm_adsp_compr
{
453 struct list_head list
;
455 struct wm_adsp_compr_buf
*buf
;
457 struct snd_compr_stream
*stream
;
458 struct snd_compressed_buffer size
;
461 unsigned int copied_total
;
463 unsigned int sample_rate
;
468 #define WM_ADSP_DATA_WORD_SIZE 3
470 #define WM_ADSP_MIN_FRAGMENTS 1
471 #define WM_ADSP_MAX_FRAGMENTS 256
472 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
473 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
475 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
477 #define HOST_BUFFER_FIELD(field) \
478 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
480 #define ALG_XM_FIELD(field) \
481 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
483 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1
485 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00
486 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8
488 static int wm_adsp_buffer_init(struct wm_adsp
*dsp
);
489 static int wm_adsp_buffer_free(struct wm_adsp
*dsp
);
491 struct wm_adsp_buffer_region
{
493 unsigned int cumulative_size
;
494 unsigned int mem_type
;
495 unsigned int base_addr
;
498 struct wm_adsp_buffer_region_def
{
499 unsigned int mem_type
;
500 unsigned int base_offset
;
501 unsigned int size_offset
;
504 static const struct wm_adsp_buffer_region_def default_regions
[] = {
506 .mem_type
= WMFW_ADSP2_XM
,
507 .base_offset
= HOST_BUFFER_FIELD(buf1_base
),
508 .size_offset
= HOST_BUFFER_FIELD(buf1_size
),
511 .mem_type
= WMFW_ADSP2_XM
,
512 .base_offset
= HOST_BUFFER_FIELD(buf2_base
),
513 .size_offset
= HOST_BUFFER_FIELD(buf1_buf2_size
),
516 .mem_type
= WMFW_ADSP2_YM
,
517 .base_offset
= HOST_BUFFER_FIELD(buf3_base
),
518 .size_offset
= HOST_BUFFER_FIELD(buf_total_size
),
522 struct wm_adsp_fw_caps
{
524 struct snd_codec_desc desc
;
526 const struct wm_adsp_buffer_region_def
*region_defs
;
529 static const struct wm_adsp_fw_caps ctrl_caps
[] = {
531 .id
= SND_AUDIOCODEC_BESPOKE
,
534 .sample_rates
= { 16000 },
535 .num_sample_rates
= 1,
536 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
538 .num_regions
= ARRAY_SIZE(default_regions
),
539 .region_defs
= default_regions
,
543 static const struct wm_adsp_fw_caps trace_caps
[] = {
545 .id
= SND_AUDIOCODEC_BESPOKE
,
549 4000, 8000, 11025, 12000, 16000, 22050,
550 24000, 32000, 44100, 48000, 64000, 88200,
551 96000, 176400, 192000
553 .num_sample_rates
= 15,
554 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
556 .num_regions
= ARRAY_SIZE(default_regions
),
557 .region_defs
= default_regions
,
561 static const struct {
565 const struct wm_adsp_fw_caps
*caps
;
567 } wm_adsp_fw
[WM_ADSP_NUM_FW
] = {
568 [WM_ADSP_FW_MBC_VSS
] = { .file
= "mbc-vss" },
569 [WM_ADSP_FW_HIFI
] = { .file
= "hifi" },
570 [WM_ADSP_FW_TX
] = { .file
= "tx" },
571 [WM_ADSP_FW_TX_SPK
] = { .file
= "tx-spk" },
572 [WM_ADSP_FW_RX
] = { .file
= "rx" },
573 [WM_ADSP_FW_RX_ANC
] = { .file
= "rx-anc" },
574 [WM_ADSP_FW_CTRL
] = {
576 .compr_direction
= SND_COMPRESS_CAPTURE
,
577 .num_caps
= ARRAY_SIZE(ctrl_caps
),
579 .voice_trigger
= true,
581 [WM_ADSP_FW_ASR
] = { .file
= "asr" },
582 [WM_ADSP_FW_TRACE
] = {
584 .compr_direction
= SND_COMPRESS_CAPTURE
,
585 .num_caps
= ARRAY_SIZE(trace_caps
),
588 [WM_ADSP_FW_SPK_PROT
] = { .file
= "spk-prot" },
589 [WM_ADSP_FW_MISC
] = { .file
= "misc" },
592 struct wm_coeff_ctl_ops
{
593 int (*xget
)(struct snd_kcontrol
*kcontrol
,
594 struct snd_ctl_elem_value
*ucontrol
);
595 int (*xput
)(struct snd_kcontrol
*kcontrol
,
596 struct snd_ctl_elem_value
*ucontrol
);
599 struct wm_coeff_ctl
{
602 struct wm_adsp_alg_region alg_region
;
603 struct wm_coeff_ctl_ops ops
;
605 unsigned int enabled
:1;
606 struct list_head list
;
611 struct soc_bytes_ext bytes_ext
;
616 static const char *wm_adsp_mem_region_name(unsigned int type
)
621 case WMFW_HALO_PM_PACKED
:
627 case WMFW_HALO_XM_PACKED
:
631 case WMFW_HALO_YM_PACKED
:
640 #ifdef CONFIG_DEBUG_FS
641 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp
*dsp
, const char *s
)
643 char *tmp
= kasprintf(GFP_KERNEL
, "%s\n", s
);
645 kfree(dsp
->wmfw_file_name
);
646 dsp
->wmfw_file_name
= tmp
;
649 static void wm_adsp_debugfs_save_binname(struct wm_adsp
*dsp
, const char *s
)
651 char *tmp
= kasprintf(GFP_KERNEL
, "%s\n", s
);
653 kfree(dsp
->bin_file_name
);
654 dsp
->bin_file_name
= tmp
;
657 static void wm_adsp_debugfs_clear(struct wm_adsp
*dsp
)
659 kfree(dsp
->wmfw_file_name
);
660 kfree(dsp
->bin_file_name
);
661 dsp
->wmfw_file_name
= NULL
;
662 dsp
->bin_file_name
= NULL
;
665 static ssize_t
wm_adsp_debugfs_wmfw_read(struct file
*file
,
666 char __user
*user_buf
,
667 size_t count
, loff_t
*ppos
)
669 struct wm_adsp
*dsp
= file
->private_data
;
672 mutex_lock(&dsp
->pwr_lock
);
674 if (!dsp
->wmfw_file_name
|| !dsp
->booted
)
677 ret
= simple_read_from_buffer(user_buf
, count
, ppos
,
679 strlen(dsp
->wmfw_file_name
));
681 mutex_unlock(&dsp
->pwr_lock
);
685 static ssize_t
wm_adsp_debugfs_bin_read(struct file
*file
,
686 char __user
*user_buf
,
687 size_t count
, loff_t
*ppos
)
689 struct wm_adsp
*dsp
= file
->private_data
;
692 mutex_lock(&dsp
->pwr_lock
);
694 if (!dsp
->bin_file_name
|| !dsp
->booted
)
697 ret
= simple_read_from_buffer(user_buf
, count
, ppos
,
699 strlen(dsp
->bin_file_name
));
701 mutex_unlock(&dsp
->pwr_lock
);
705 static const struct {
707 const struct file_operations fops
;
708 } wm_adsp_debugfs_fops
[] = {
710 .name
= "wmfw_file_name",
713 .read
= wm_adsp_debugfs_wmfw_read
,
717 .name
= "bin_file_name",
720 .read
= wm_adsp_debugfs_bin_read
,
725 static void wm_adsp2_init_debugfs(struct wm_adsp
*dsp
,
726 struct snd_soc_component
*component
)
728 struct dentry
*root
= NULL
;
731 root
= debugfs_create_dir(dsp
->name
, component
->debugfs_root
);
733 debugfs_create_bool("booted", 0444, root
, &dsp
->booted
);
734 debugfs_create_bool("running", 0444, root
, &dsp
->running
);
735 debugfs_create_x32("fw_id", 0444, root
, &dsp
->fw_id
);
736 debugfs_create_x32("fw_version", 0444, root
, &dsp
->fw_id_version
);
738 for (i
= 0; i
< ARRAY_SIZE(wm_adsp_debugfs_fops
); ++i
)
739 debugfs_create_file(wm_adsp_debugfs_fops
[i
].name
, 0444, root
,
740 dsp
, &wm_adsp_debugfs_fops
[i
].fops
);
742 dsp
->debugfs_root
= root
;
745 static void wm_adsp2_cleanup_debugfs(struct wm_adsp
*dsp
)
747 wm_adsp_debugfs_clear(dsp
);
748 debugfs_remove_recursive(dsp
->debugfs_root
);
751 static inline void wm_adsp2_init_debugfs(struct wm_adsp
*dsp
,
752 struct snd_soc_component
*component
)
756 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp
*dsp
)
760 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp
*dsp
,
765 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp
*dsp
,
770 static inline void wm_adsp_debugfs_clear(struct wm_adsp
*dsp
)
775 int wm_adsp_fw_get(struct snd_kcontrol
*kcontrol
,
776 struct snd_ctl_elem_value
*ucontrol
)
778 struct snd_soc_component
*component
= snd_soc_kcontrol_component(kcontrol
);
779 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
780 struct wm_adsp
*dsp
= snd_soc_component_get_drvdata(component
);
782 ucontrol
->value
.enumerated
.item
[0] = dsp
[e
->shift_l
].fw
;
786 EXPORT_SYMBOL_GPL(wm_adsp_fw_get
);
788 int wm_adsp_fw_put(struct snd_kcontrol
*kcontrol
,
789 struct snd_ctl_elem_value
*ucontrol
)
791 struct snd_soc_component
*component
= snd_soc_kcontrol_component(kcontrol
);
792 struct soc_enum
*e
= (struct soc_enum
*)kcontrol
->private_value
;
793 struct wm_adsp
*dsp
= snd_soc_component_get_drvdata(component
);
796 if (ucontrol
->value
.enumerated
.item
[0] == dsp
[e
->shift_l
].fw
)
799 if (ucontrol
->value
.enumerated
.item
[0] >= WM_ADSP_NUM_FW
)
802 mutex_lock(&dsp
[e
->shift_l
].pwr_lock
);
804 if (dsp
[e
->shift_l
].booted
|| !list_empty(&dsp
[e
->shift_l
].compr_list
))
807 dsp
[e
->shift_l
].fw
= ucontrol
->value
.enumerated
.item
[0];
809 mutex_unlock(&dsp
[e
->shift_l
].pwr_lock
);
813 EXPORT_SYMBOL_GPL(wm_adsp_fw_put
);
815 const struct soc_enum wm_adsp_fw_enum
[] = {
816 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
817 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
818 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
819 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
820 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
821 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
822 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text
), wm_adsp_fw_text
),
824 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum
);
826 static struct wm_adsp_region
const *wm_adsp_find_region(struct wm_adsp
*dsp
,
831 for (i
= 0; i
< dsp
->num_mems
; i
++)
832 if (dsp
->mem
[i
].type
== type
)
838 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region
const *mem
,
843 return mem
->base
+ (offset
* 3);
848 return mem
->base
+ (offset
* 2);
850 WARN(1, "Unknown memory region type");
855 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region
const *mem
,
861 return mem
->base
+ (offset
* 4);
862 case WMFW_HALO_XM_PACKED
:
863 case WMFW_HALO_YM_PACKED
:
864 return (mem
->base
+ (offset
* 3)) & ~0x3;
865 case WMFW_HALO_PM_PACKED
:
866 return mem
->base
+ (offset
* 5);
868 WARN(1, "Unknown memory region type");
873 static void wm_adsp_read_fw_status(struct wm_adsp
*dsp
,
874 int noffs
, unsigned int *offs
)
879 for (i
= 0; i
< noffs
; ++i
) {
880 ret
= regmap_read(dsp
->regmap
, dsp
->base
+ offs
[i
], &offs
[i
]);
882 adsp_err(dsp
, "Failed to read SCRATCH%u: %d\n", i
, ret
);
888 static void wm_adsp2_show_fw_status(struct wm_adsp
*dsp
)
890 unsigned int offs
[] = {
891 ADSP2_SCRATCH0
, ADSP2_SCRATCH1
, ADSP2_SCRATCH2
, ADSP2_SCRATCH3
,
894 wm_adsp_read_fw_status(dsp
, ARRAY_SIZE(offs
), offs
);
896 adsp_dbg(dsp
, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
897 offs
[0], offs
[1], offs
[2], offs
[3]);
900 static void wm_adsp2v2_show_fw_status(struct wm_adsp
*dsp
)
902 unsigned int offs
[] = { ADSP2V2_SCRATCH0_1
, ADSP2V2_SCRATCH2_3
};
904 wm_adsp_read_fw_status(dsp
, ARRAY_SIZE(offs
), offs
);
906 adsp_dbg(dsp
, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
907 offs
[0] & 0xFFFF, offs
[0] >> 16,
908 offs
[1] & 0xFFFF, offs
[1] >> 16);
911 static void wm_halo_show_fw_status(struct wm_adsp
*dsp
)
913 unsigned int offs
[] = {
914 HALO_SCRATCH1
, HALO_SCRATCH2
, HALO_SCRATCH3
, HALO_SCRATCH4
,
917 wm_adsp_read_fw_status(dsp
, ARRAY_SIZE(offs
), offs
);
919 adsp_dbg(dsp
, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
920 offs
[0], offs
[1], offs
[2], offs
[3]);
923 static inline struct wm_coeff_ctl
*bytes_ext_to_ctl(struct soc_bytes_ext
*ext
)
925 return container_of(ext
, struct wm_coeff_ctl
, bytes_ext
);
928 static int wm_coeff_base_reg(struct wm_coeff_ctl
*ctl
, unsigned int *reg
)
930 const struct wm_adsp_alg_region
*alg_region
= &ctl
->alg_region
;
931 struct wm_adsp
*dsp
= ctl
->dsp
;
932 const struct wm_adsp_region
*mem
;
934 mem
= wm_adsp_find_region(dsp
, alg_region
->type
);
936 adsp_err(dsp
, "No base for region %x\n",
941 *reg
= dsp
->ops
->region_to_reg(mem
, ctl
->alg_region
.base
+ ctl
->offset
);
946 static int wm_coeff_info(struct snd_kcontrol
*kctl
,
947 struct snd_ctl_elem_info
*uinfo
)
949 struct soc_bytes_ext
*bytes_ext
=
950 (struct soc_bytes_ext
*)kctl
->private_value
;
951 struct wm_coeff_ctl
*ctl
= bytes_ext_to_ctl(bytes_ext
);
954 case WMFW_CTL_TYPE_ACKED
:
955 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
956 uinfo
->value
.integer
.min
= WM_ADSP_ACKED_CTL_MIN_VALUE
;
957 uinfo
->value
.integer
.max
= WM_ADSP_ACKED_CTL_MAX_VALUE
;
958 uinfo
->value
.integer
.step
= 1;
962 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
963 uinfo
->count
= ctl
->len
;
970 static int wm_coeff_write_acked_control(struct wm_coeff_ctl
*ctl
,
971 unsigned int event_id
)
973 struct wm_adsp
*dsp
= ctl
->dsp
;
974 u32 val
= cpu_to_be32(event_id
);
978 ret
= wm_coeff_base_reg(ctl
, ®
);
982 adsp_dbg(dsp
, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
983 event_id
, ctl
->alg_region
.alg
,
984 wm_adsp_mem_region_name(ctl
->alg_region
.type
), ctl
->offset
);
986 ret
= regmap_raw_write(dsp
->regmap
, reg
, &val
, sizeof(val
));
988 adsp_err(dsp
, "Failed to write %x: %d\n", reg
, ret
);
993 * Poll for ack, we initially poll at ~1ms intervals for firmwares
994 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
995 * to ack instantly so we do the first 1ms delay before reading the
996 * control to avoid a pointless bus transaction
998 for (i
= 0; i
< WM_ADSP_ACKED_CTL_TIMEOUT_MS
;) {
1000 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS
- 1:
1001 usleep_range(1000, 2000);
1005 usleep_range(10000, 20000);
1010 ret
= regmap_raw_read(dsp
->regmap
, reg
, &val
, sizeof(val
));
1012 adsp_err(dsp
, "Failed to read %x: %d\n", reg
, ret
);
1017 adsp_dbg(dsp
, "Acked control ACKED at poll %u\n", i
);
1022 adsp_warn(dsp
, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
1023 reg
, ctl
->alg_region
.alg
,
1024 wm_adsp_mem_region_name(ctl
->alg_region
.type
),
1030 static int wm_coeff_write_control(struct wm_coeff_ctl
*ctl
,
1031 const void *buf
, size_t len
)
1033 struct wm_adsp
*dsp
= ctl
->dsp
;
1038 ret
= wm_coeff_base_reg(ctl
, ®
);
1042 scratch
= kmemdup(buf
, len
, GFP_KERNEL
| GFP_DMA
);
1046 ret
= regmap_raw_write(dsp
->regmap
, reg
, scratch
,
1049 adsp_err(dsp
, "Failed to write %zu bytes to %x: %d\n",
1054 adsp_dbg(dsp
, "Wrote %zu bytes to %x\n", len
, reg
);
1061 static int wm_coeff_put(struct snd_kcontrol
*kctl
,
1062 struct snd_ctl_elem_value
*ucontrol
)
1064 struct soc_bytes_ext
*bytes_ext
=
1065 (struct soc_bytes_ext
*)kctl
->private_value
;
1066 struct wm_coeff_ctl
*ctl
= bytes_ext_to_ctl(bytes_ext
);
1067 char *p
= ucontrol
->value
.bytes
.data
;
1070 mutex_lock(&ctl
->dsp
->pwr_lock
);
1072 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)
1075 memcpy(ctl
->cache
, p
, ctl
->len
);
1078 if (ctl
->enabled
&& ctl
->dsp
->running
)
1079 ret
= wm_coeff_write_control(ctl
, p
, ctl
->len
);
1081 mutex_unlock(&ctl
->dsp
->pwr_lock
);
1086 static int wm_coeff_tlv_put(struct snd_kcontrol
*kctl
,
1087 const unsigned int __user
*bytes
, unsigned int size
)
1089 struct soc_bytes_ext
*bytes_ext
=
1090 (struct soc_bytes_ext
*)kctl
->private_value
;
1091 struct wm_coeff_ctl
*ctl
= bytes_ext_to_ctl(bytes_ext
);
1094 mutex_lock(&ctl
->dsp
->pwr_lock
);
1096 if (copy_from_user(ctl
->cache
, bytes
, size
)) {
1100 if (ctl
->enabled
&& ctl
->dsp
->running
)
1101 ret
= wm_coeff_write_control(ctl
, ctl
->cache
, size
);
1102 else if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)
1106 mutex_unlock(&ctl
->dsp
->pwr_lock
);
1111 static int wm_coeff_put_acked(struct snd_kcontrol
*kctl
,
1112 struct snd_ctl_elem_value
*ucontrol
)
1114 struct soc_bytes_ext
*bytes_ext
=
1115 (struct soc_bytes_ext
*)kctl
->private_value
;
1116 struct wm_coeff_ctl
*ctl
= bytes_ext_to_ctl(bytes_ext
);
1117 unsigned int val
= ucontrol
->value
.integer
.value
[0];
1121 return 0; /* 0 means no event */
1123 mutex_lock(&ctl
->dsp
->pwr_lock
);
1125 if (ctl
->enabled
&& ctl
->dsp
->running
)
1126 ret
= wm_coeff_write_acked_control(ctl
, val
);
1130 mutex_unlock(&ctl
->dsp
->pwr_lock
);
1135 static int wm_coeff_read_control(struct wm_coeff_ctl
*ctl
,
1136 void *buf
, size_t len
)
1138 struct wm_adsp
*dsp
= ctl
->dsp
;
1143 ret
= wm_coeff_base_reg(ctl
, ®
);
1147 scratch
= kmalloc(len
, GFP_KERNEL
| GFP_DMA
);
1151 ret
= regmap_raw_read(dsp
->regmap
, reg
, scratch
, len
);
1153 adsp_err(dsp
, "Failed to read %zu bytes from %x: %d\n",
1158 adsp_dbg(dsp
, "Read %zu bytes from %x\n", len
, reg
);
1160 memcpy(buf
, scratch
, len
);
1166 static int wm_coeff_get(struct snd_kcontrol
*kctl
,
1167 struct snd_ctl_elem_value
*ucontrol
)
1169 struct soc_bytes_ext
*bytes_ext
=
1170 (struct soc_bytes_ext
*)kctl
->private_value
;
1171 struct wm_coeff_ctl
*ctl
= bytes_ext_to_ctl(bytes_ext
);
1172 char *p
= ucontrol
->value
.bytes
.data
;
1175 mutex_lock(&ctl
->dsp
->pwr_lock
);
1177 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
) {
1178 if (ctl
->enabled
&& ctl
->dsp
->running
)
1179 ret
= wm_coeff_read_control(ctl
, p
, ctl
->len
);
1183 if (!ctl
->flags
&& ctl
->enabled
&& ctl
->dsp
->running
)
1184 ret
= wm_coeff_read_control(ctl
, ctl
->cache
, ctl
->len
);
1186 memcpy(p
, ctl
->cache
, ctl
->len
);
1189 mutex_unlock(&ctl
->dsp
->pwr_lock
);
1194 static int wm_coeff_tlv_get(struct snd_kcontrol
*kctl
,
1195 unsigned int __user
*bytes
, unsigned int size
)
1197 struct soc_bytes_ext
*bytes_ext
=
1198 (struct soc_bytes_ext
*)kctl
->private_value
;
1199 struct wm_coeff_ctl
*ctl
= bytes_ext_to_ctl(bytes_ext
);
1202 mutex_lock(&ctl
->dsp
->pwr_lock
);
1204 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
) {
1205 if (ctl
->enabled
&& ctl
->dsp
->running
)
1206 ret
= wm_coeff_read_control(ctl
, ctl
->cache
, size
);
1210 if (!ctl
->flags
&& ctl
->enabled
&& ctl
->dsp
->running
)
1211 ret
= wm_coeff_read_control(ctl
, ctl
->cache
, size
);
1214 if (!ret
&& copy_to_user(bytes
, ctl
->cache
, size
))
1217 mutex_unlock(&ctl
->dsp
->pwr_lock
);
1222 static int wm_coeff_get_acked(struct snd_kcontrol
*kcontrol
,
1223 struct snd_ctl_elem_value
*ucontrol
)
1226 * Although it's not useful to read an acked control, we must satisfy
1227 * user-side assumptions that all controls are readable and that a
1228 * write of the same value should be filtered out (it's valid to send
1229 * the same event number again to the firmware). We therefore return 0,
1230 * meaning "no event" so valid event numbers will always be a change
1232 ucontrol
->value
.integer
.value
[0] = 0;
1237 struct wmfw_ctl_work
{
1238 struct wm_adsp
*dsp
;
1239 struct wm_coeff_ctl
*ctl
;
1240 struct work_struct work
;
1243 static unsigned int wmfw_convert_flags(unsigned int in
, unsigned int len
)
1245 unsigned int out
, rd
, wr
, vol
;
1247 if (len
> ADSP_MAX_STD_CTRL_SIZE
) {
1248 rd
= SNDRV_CTL_ELEM_ACCESS_TLV_READ
;
1249 wr
= SNDRV_CTL_ELEM_ACCESS_TLV_WRITE
;
1250 vol
= SNDRV_CTL_ELEM_ACCESS_VOLATILE
;
1252 out
= SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK
;
1254 rd
= SNDRV_CTL_ELEM_ACCESS_READ
;
1255 wr
= SNDRV_CTL_ELEM_ACCESS_WRITE
;
1256 vol
= SNDRV_CTL_ELEM_ACCESS_VOLATILE
;
1263 if (in
& WMFW_CTL_FLAG_WRITEABLE
)
1265 if (in
& WMFW_CTL_FLAG_VOLATILE
)
1268 out
|= rd
| wr
| vol
;
1274 static int wmfw_add_ctl(struct wm_adsp
*dsp
, struct wm_coeff_ctl
*ctl
)
1276 struct snd_kcontrol_new
*kcontrol
;
1279 if (!ctl
|| !ctl
->name
)
1282 kcontrol
= kzalloc(sizeof(*kcontrol
), GFP_KERNEL
);
1286 kcontrol
->name
= ctl
->name
;
1287 kcontrol
->info
= wm_coeff_info
;
1288 kcontrol
->iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
1289 kcontrol
->tlv
.c
= snd_soc_bytes_tlv_callback
;
1290 kcontrol
->private_value
= (unsigned long)&ctl
->bytes_ext
;
1291 kcontrol
->access
= wmfw_convert_flags(ctl
->flags
, ctl
->len
);
1293 switch (ctl
->type
) {
1294 case WMFW_CTL_TYPE_ACKED
:
1295 kcontrol
->get
= wm_coeff_get_acked
;
1296 kcontrol
->put
= wm_coeff_put_acked
;
1299 if (kcontrol
->access
& SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK
) {
1300 ctl
->bytes_ext
.max
= ctl
->len
;
1301 ctl
->bytes_ext
.get
= wm_coeff_tlv_get
;
1302 ctl
->bytes_ext
.put
= wm_coeff_tlv_put
;
1304 kcontrol
->get
= wm_coeff_get
;
1305 kcontrol
->put
= wm_coeff_put
;
1310 ret
= snd_soc_add_component_controls(dsp
->component
, kcontrol
, 1);
1323 static int wm_coeff_init_control_caches(struct wm_adsp
*dsp
)
1325 struct wm_coeff_ctl
*ctl
;
1328 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
1329 if (!ctl
->enabled
|| ctl
->set
)
1331 if (ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)
1335 * For readable controls populate the cache from the DSP memory.
1336 * For non-readable controls the cache was zero-filled when
1337 * created so we don't need to do anything.
1339 if (!ctl
->flags
|| (ctl
->flags
& WMFW_CTL_FLAG_READABLE
)) {
1340 ret
= wm_coeff_read_control(ctl
, ctl
->cache
, ctl
->len
);
1349 static int wm_coeff_sync_controls(struct wm_adsp
*dsp
)
1351 struct wm_coeff_ctl
*ctl
;
1354 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
1357 if (ctl
->set
&& !(ctl
->flags
& WMFW_CTL_FLAG_VOLATILE
)) {
1358 ret
= wm_coeff_write_control(ctl
, ctl
->cache
, ctl
->len
);
1367 static void wm_adsp_signal_event_controls(struct wm_adsp
*dsp
,
1370 struct wm_coeff_ctl
*ctl
;
1373 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
1374 if (ctl
->type
!= WMFW_CTL_TYPE_HOSTEVENT
)
1380 ret
= wm_coeff_write_acked_control(ctl
, event
);
1383 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1384 event
, ctl
->alg_region
.alg
, ret
);
1388 static void wm_adsp_ctl_work(struct work_struct
*work
)
1390 struct wmfw_ctl_work
*ctl_work
= container_of(work
,
1391 struct wmfw_ctl_work
,
1394 wmfw_add_ctl(ctl_work
->dsp
, ctl_work
->ctl
);
1398 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl
*ctl
)
1405 static int wm_adsp_create_control(struct wm_adsp
*dsp
,
1406 const struct wm_adsp_alg_region
*alg_region
,
1407 unsigned int offset
, unsigned int len
,
1408 const char *subname
, unsigned int subname_len
,
1409 unsigned int flags
, unsigned int type
)
1411 struct wm_coeff_ctl
*ctl
;
1412 struct wmfw_ctl_work
*ctl_work
;
1413 char name
[SNDRV_CTL_ELEM_ID_NAME_MAXLEN
];
1414 const char *region_name
;
1417 region_name
= wm_adsp_mem_region_name(alg_region
->type
);
1419 adsp_err(dsp
, "Unknown region type: %d\n", alg_region
->type
);
1423 switch (dsp
->fw_ver
) {
1426 snprintf(name
, SNDRV_CTL_ELEM_ID_NAME_MAXLEN
, "%s %s %x",
1427 dsp
->name
, region_name
, alg_region
->alg
);
1428 subname
= NULL
; /* don't append subname */
1431 ret
= snprintf(name
, SNDRV_CTL_ELEM_ID_NAME_MAXLEN
,
1432 "%s%c %.12s %x", dsp
->name
, *region_name
,
1433 wm_adsp_fw_text
[dsp
->fw
], alg_region
->alg
);
1436 ret
= snprintf(name
, SNDRV_CTL_ELEM_ID_NAME_MAXLEN
,
1437 "%s %.12s %x", dsp
->name
,
1438 wm_adsp_fw_text
[dsp
->fw
], alg_region
->alg
);
1443 int avail
= SNDRV_CTL_ELEM_ID_NAME_MAXLEN
- ret
- 2;
1446 if (dsp
->component
->name_prefix
)
1447 avail
-= strlen(dsp
->component
->name_prefix
) + 1;
1449 /* Truncate the subname from the start if it is too long */
1450 if (subname_len
> avail
)
1451 skip
= subname_len
- avail
;
1453 snprintf(name
+ ret
, SNDRV_CTL_ELEM_ID_NAME_MAXLEN
- ret
,
1454 " %.*s", subname_len
- skip
, subname
+ skip
);
1457 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
1458 if (!strcmp(ctl
->name
, name
)) {
1465 ctl
= kzalloc(sizeof(*ctl
), GFP_KERNEL
);
1468 ctl
->fw_name
= wm_adsp_fw_text
[dsp
->fw
];
1469 ctl
->alg_region
= *alg_region
;
1470 ctl
->name
= kmemdup(name
, strlen(name
) + 1, GFP_KERNEL
);
1477 ctl
->ops
.xget
= wm_coeff_get
;
1478 ctl
->ops
.xput
= wm_coeff_put
;
1483 ctl
->offset
= offset
;
1485 ctl
->cache
= kzalloc(ctl
->len
, GFP_KERNEL
);
1491 list_add(&ctl
->list
, &dsp
->ctl_list
);
1493 if (flags
& WMFW_CTL_FLAG_SYS
)
1496 ctl_work
= kzalloc(sizeof(*ctl_work
), GFP_KERNEL
);
1502 ctl_work
->dsp
= dsp
;
1503 ctl_work
->ctl
= ctl
;
1504 INIT_WORK(&ctl_work
->work
, wm_adsp_ctl_work
);
1505 schedule_work(&ctl_work
->work
);
1519 struct wm_coeff_parsed_alg
{
1526 struct wm_coeff_parsed_coeff
{
1536 static int wm_coeff_parse_string(int bytes
, const u8
**pos
, const u8
**str
)
1545 length
= le16_to_cpu(*((__le16
*)*pos
));
1552 *str
= *pos
+ bytes
;
1554 *pos
+= ((length
+ bytes
) + 3) & ~0x03;
1559 static int wm_coeff_parse_int(int bytes
, const u8
**pos
)
1565 val
= le16_to_cpu(*((__le16
*)*pos
));
1568 val
= le32_to_cpu(*((__le32
*)*pos
));
1579 static inline void wm_coeff_parse_alg(struct wm_adsp
*dsp
, const u8
**data
,
1580 struct wm_coeff_parsed_alg
*blk
)
1582 const struct wmfw_adsp_alg_data
*raw
;
1584 switch (dsp
->fw_ver
) {
1587 raw
= (const struct wmfw_adsp_alg_data
*)*data
;
1590 blk
->id
= le32_to_cpu(raw
->id
);
1591 blk
->name
= raw
->name
;
1592 blk
->name_len
= strlen(raw
->name
);
1593 blk
->ncoeff
= le32_to_cpu(raw
->ncoeff
);
1596 blk
->id
= wm_coeff_parse_int(sizeof(raw
->id
), data
);
1597 blk
->name_len
= wm_coeff_parse_string(sizeof(u8
), data
,
1599 wm_coeff_parse_string(sizeof(u16
), data
, NULL
);
1600 blk
->ncoeff
= wm_coeff_parse_int(sizeof(raw
->ncoeff
), data
);
1604 adsp_dbg(dsp
, "Algorithm ID: %#x\n", blk
->id
);
1605 adsp_dbg(dsp
, "Algorithm name: %.*s\n", blk
->name_len
, blk
->name
);
1606 adsp_dbg(dsp
, "# of coefficient descriptors: %#x\n", blk
->ncoeff
);
1609 static inline void wm_coeff_parse_coeff(struct wm_adsp
*dsp
, const u8
**data
,
1610 struct wm_coeff_parsed_coeff
*blk
)
1612 const struct wmfw_adsp_coeff_data
*raw
;
1616 switch (dsp
->fw_ver
) {
1619 raw
= (const struct wmfw_adsp_coeff_data
*)*data
;
1620 *data
= *data
+ sizeof(raw
->hdr
) + le32_to_cpu(raw
->hdr
.size
);
1622 blk
->offset
= le16_to_cpu(raw
->hdr
.offset
);
1623 blk
->mem_type
= le16_to_cpu(raw
->hdr
.type
);
1624 blk
->name
= raw
->name
;
1625 blk
->name_len
= strlen(raw
->name
);
1626 blk
->ctl_type
= le16_to_cpu(raw
->ctl_type
);
1627 blk
->flags
= le16_to_cpu(raw
->flags
);
1628 blk
->len
= le32_to_cpu(raw
->len
);
1632 blk
->offset
= wm_coeff_parse_int(sizeof(raw
->hdr
.offset
), &tmp
);
1633 blk
->mem_type
= wm_coeff_parse_int(sizeof(raw
->hdr
.type
), &tmp
);
1634 length
= wm_coeff_parse_int(sizeof(raw
->hdr
.size
), &tmp
);
1635 blk
->name_len
= wm_coeff_parse_string(sizeof(u8
), &tmp
,
1637 wm_coeff_parse_string(sizeof(u8
), &tmp
, NULL
);
1638 wm_coeff_parse_string(sizeof(u16
), &tmp
, NULL
);
1639 blk
->ctl_type
= wm_coeff_parse_int(sizeof(raw
->ctl_type
), &tmp
);
1640 blk
->flags
= wm_coeff_parse_int(sizeof(raw
->flags
), &tmp
);
1641 blk
->len
= wm_coeff_parse_int(sizeof(raw
->len
), &tmp
);
1643 *data
= *data
+ sizeof(raw
->hdr
) + length
;
1647 adsp_dbg(dsp
, "\tCoefficient type: %#x\n", blk
->mem_type
);
1648 adsp_dbg(dsp
, "\tCoefficient offset: %#x\n", blk
->offset
);
1649 adsp_dbg(dsp
, "\tCoefficient name: %.*s\n", blk
->name_len
, blk
->name
);
1650 adsp_dbg(dsp
, "\tCoefficient flags: %#x\n", blk
->flags
);
1651 adsp_dbg(dsp
, "\tALSA control type: %#x\n", blk
->ctl_type
);
1652 adsp_dbg(dsp
, "\tALSA control len: %#x\n", blk
->len
);
1655 static int wm_adsp_check_coeff_flags(struct wm_adsp
*dsp
,
1656 const struct wm_coeff_parsed_coeff
*coeff_blk
,
1657 unsigned int f_required
,
1658 unsigned int f_illegal
)
1660 if ((coeff_blk
->flags
& f_illegal
) ||
1661 ((coeff_blk
->flags
& f_required
) != f_required
)) {
1662 adsp_err(dsp
, "Illegal flags 0x%x for control type 0x%x\n",
1663 coeff_blk
->flags
, coeff_blk
->ctl_type
);
1670 static int wm_adsp_parse_coeff(struct wm_adsp
*dsp
,
1671 const struct wmfw_region
*region
)
1673 struct wm_adsp_alg_region alg_region
= {};
1674 struct wm_coeff_parsed_alg alg_blk
;
1675 struct wm_coeff_parsed_coeff coeff_blk
;
1676 const u8
*data
= region
->data
;
1679 wm_coeff_parse_alg(dsp
, &data
, &alg_blk
);
1680 for (i
= 0; i
< alg_blk
.ncoeff
; i
++) {
1681 wm_coeff_parse_coeff(dsp
, &data
, &coeff_blk
);
1683 switch (coeff_blk
.ctl_type
) {
1684 case SNDRV_CTL_ELEM_TYPE_BYTES
:
1686 case WMFW_CTL_TYPE_ACKED
:
1687 if (coeff_blk
.flags
& WMFW_CTL_FLAG_SYS
)
1688 continue; /* ignore */
1690 ret
= wm_adsp_check_coeff_flags(dsp
, &coeff_blk
,
1691 WMFW_CTL_FLAG_VOLATILE
|
1692 WMFW_CTL_FLAG_WRITEABLE
|
1693 WMFW_CTL_FLAG_READABLE
,
1698 case WMFW_CTL_TYPE_HOSTEVENT
:
1699 ret
= wm_adsp_check_coeff_flags(dsp
, &coeff_blk
,
1701 WMFW_CTL_FLAG_VOLATILE
|
1702 WMFW_CTL_FLAG_WRITEABLE
|
1703 WMFW_CTL_FLAG_READABLE
,
1708 case WMFW_CTL_TYPE_HOST_BUFFER
:
1709 ret
= wm_adsp_check_coeff_flags(dsp
, &coeff_blk
,
1711 WMFW_CTL_FLAG_VOLATILE
|
1712 WMFW_CTL_FLAG_READABLE
,
1718 adsp_err(dsp
, "Unknown control type: %d\n",
1719 coeff_blk
.ctl_type
);
1723 alg_region
.type
= coeff_blk
.mem_type
;
1724 alg_region
.alg
= alg_blk
.id
;
1726 ret
= wm_adsp_create_control(dsp
, &alg_region
,
1732 coeff_blk
.ctl_type
);
1734 adsp_err(dsp
, "Failed to create control: %.*s, %d\n",
1735 coeff_blk
.name_len
, coeff_blk
.name
, ret
);
1741 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp
*dsp
,
1742 const char * const file
,
1744 const struct firmware
*firmware
)
1746 const struct wmfw_adsp1_sizes
*adsp1_sizes
;
1748 adsp1_sizes
= (void *)&firmware
->data
[pos
];
1750 adsp_dbg(dsp
, "%s: %d DM, %d PM, %d ZM\n", file
,
1751 le32_to_cpu(adsp1_sizes
->dm
), le32_to_cpu(adsp1_sizes
->pm
),
1752 le32_to_cpu(adsp1_sizes
->zm
));
1754 return pos
+ sizeof(*adsp1_sizes
);
1757 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp
*dsp
,
1758 const char * const file
,
1760 const struct firmware
*firmware
)
1762 const struct wmfw_adsp2_sizes
*adsp2_sizes
;
1764 adsp2_sizes
= (void *)&firmware
->data
[pos
];
1766 adsp_dbg(dsp
, "%s: %d XM, %d YM %d PM, %d ZM\n", file
,
1767 le32_to_cpu(adsp2_sizes
->xm
), le32_to_cpu(adsp2_sizes
->ym
),
1768 le32_to_cpu(adsp2_sizes
->pm
), le32_to_cpu(adsp2_sizes
->zm
));
1770 return pos
+ sizeof(*adsp2_sizes
);
1773 static bool wm_adsp_validate_version(struct wm_adsp
*dsp
, unsigned int version
)
1777 adsp_warn(dsp
, "Deprecated file format %d\n", version
);
1787 static bool wm_halo_validate_version(struct wm_adsp
*dsp
, unsigned int version
)
1797 static int wm_adsp_load(struct wm_adsp
*dsp
)
1799 LIST_HEAD(buf_list
);
1800 const struct firmware
*firmware
;
1801 struct regmap
*regmap
= dsp
->regmap
;
1802 unsigned int pos
= 0;
1803 const struct wmfw_header
*header
;
1804 const struct wmfw_adsp1_sizes
*adsp1_sizes
;
1805 const struct wmfw_footer
*footer
;
1806 const struct wmfw_region
*region
;
1807 const struct wm_adsp_region
*mem
;
1808 const char *region_name
;
1809 char *file
, *text
= NULL
;
1810 struct wm_adsp_buf
*buf
;
1813 int ret
, offset
, type
;
1815 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
1819 snprintf(file
, PAGE_SIZE
, "%s-%s-%s.wmfw", dsp
->part
, dsp
->fwf_name
,
1820 wm_adsp_fw
[dsp
->fw
].file
);
1821 file
[PAGE_SIZE
- 1] = '\0';
1823 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
1825 adsp_err(dsp
, "Failed to request '%s'\n", file
);
1830 pos
= sizeof(*header
) + sizeof(*adsp1_sizes
) + sizeof(*footer
);
1831 if (pos
>= firmware
->size
) {
1832 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
1833 file
, firmware
->size
);
1837 header
= (void *)&firmware
->data
[0];
1839 if (memcmp(&header
->magic
[0], "WMFW", 4) != 0) {
1840 adsp_err(dsp
, "%s: invalid magic\n", file
);
1844 if (!dsp
->ops
->validate_version(dsp
, header
->ver
)) {
1845 adsp_err(dsp
, "%s: unknown file format %d\n",
1850 adsp_info(dsp
, "Firmware version: %d\n", header
->ver
);
1851 dsp
->fw_ver
= header
->ver
;
1853 if (header
->core
!= dsp
->type
) {
1854 adsp_err(dsp
, "%s: invalid core %d != %d\n",
1855 file
, header
->core
, dsp
->type
);
1859 pos
= sizeof(*header
);
1860 pos
= dsp
->ops
->parse_sizes(dsp
, file
, pos
, firmware
);
1862 footer
= (void *)&firmware
->data
[pos
];
1863 pos
+= sizeof(*footer
);
1865 if (le32_to_cpu(header
->len
) != pos
) {
1866 adsp_err(dsp
, "%s: unexpected header length %d\n",
1867 file
, le32_to_cpu(header
->len
));
1871 adsp_dbg(dsp
, "%s: timestamp %llu\n", file
,
1872 le64_to_cpu(footer
->timestamp
));
1874 while (pos
< firmware
->size
&&
1875 sizeof(*region
) < firmware
->size
- pos
) {
1876 region
= (void *)&(firmware
->data
[pos
]);
1877 region_name
= "Unknown";
1880 offset
= le32_to_cpu(region
->offset
) & 0xffffff;
1881 type
= be32_to_cpu(region
->type
) & 0xff;
1884 case WMFW_NAME_TEXT
:
1885 region_name
= "Firmware name";
1886 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
1889 case WMFW_ALGORITHM_DATA
:
1890 region_name
= "Algorithm";
1891 ret
= wm_adsp_parse_coeff(dsp
, region
);
1895 case WMFW_INFO_TEXT
:
1896 region_name
= "Information";
1897 text
= kzalloc(le32_to_cpu(region
->len
) + 1,
1901 region_name
= "Absolute";
1909 case WMFW_HALO_PM_PACKED
:
1910 case WMFW_HALO_XM_PACKED
:
1911 case WMFW_HALO_YM_PACKED
:
1912 mem
= wm_adsp_find_region(dsp
, type
);
1914 adsp_err(dsp
, "No region of type: %x\n", type
);
1919 region_name
= wm_adsp_mem_region_name(type
);
1920 reg
= dsp
->ops
->region_to_reg(mem
, offset
);
1924 "%s.%d: Unknown region type %x at %d(%x)\n",
1925 file
, regions
, type
, pos
, pos
);
1929 adsp_dbg(dsp
, "%s.%d: %d bytes at %d in %s\n", file
,
1930 regions
, le32_to_cpu(region
->len
), offset
,
1933 if (le32_to_cpu(region
->len
) >
1934 firmware
->size
- pos
- sizeof(*region
)) {
1936 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1937 file
, regions
, region_name
,
1938 le32_to_cpu(region
->len
), firmware
->size
);
1944 memcpy(text
, region
->data
, le32_to_cpu(region
->len
));
1945 adsp_info(dsp
, "%s: %s\n", file
, text
);
1951 buf
= wm_adsp_buf_alloc(region
->data
,
1952 le32_to_cpu(region
->len
),
1955 adsp_err(dsp
, "Out of memory\n");
1960 ret
= regmap_raw_write_async(regmap
, reg
, buf
->buf
,
1961 le32_to_cpu(region
->len
));
1964 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1966 le32_to_cpu(region
->len
), offset
,
1972 pos
+= le32_to_cpu(region
->len
) + sizeof(*region
);
1976 ret
= regmap_async_complete(regmap
);
1978 adsp_err(dsp
, "Failed to complete async write: %d\n", ret
);
1982 if (pos
> firmware
->size
)
1983 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
1984 file
, regions
, pos
- firmware
->size
);
1986 wm_adsp_debugfs_save_wmfwname(dsp
, file
);
1989 regmap_async_complete(regmap
);
1990 wm_adsp_buf_free(&buf_list
);
1991 release_firmware(firmware
);
1999 static void wm_adsp_ctl_fixup_base(struct wm_adsp
*dsp
,
2000 const struct wm_adsp_alg_region
*alg_region
)
2002 struct wm_coeff_ctl
*ctl
;
2004 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
2005 if (ctl
->fw_name
== wm_adsp_fw_text
[dsp
->fw
] &&
2006 alg_region
->alg
== ctl
->alg_region
.alg
&&
2007 alg_region
->type
== ctl
->alg_region
.type
) {
2008 ctl
->alg_region
.base
= alg_region
->base
;
2013 static void *wm_adsp_read_algs(struct wm_adsp
*dsp
, size_t n_algs
,
2014 const struct wm_adsp_region
*mem
,
2015 unsigned int pos
, unsigned int len
)
2023 adsp_err(dsp
, "No algorithms\n");
2024 return ERR_PTR(-EINVAL
);
2027 if (n_algs
> 1024) {
2028 adsp_err(dsp
, "Algorithm count %zx excessive\n", n_algs
);
2029 return ERR_PTR(-EINVAL
);
2032 /* Read the terminator first to validate the length */
2033 reg
= dsp
->ops
->region_to_reg(mem
, pos
+ len
);
2035 ret
= regmap_raw_read(dsp
->regmap
, reg
, &val
, sizeof(val
));
2037 adsp_err(dsp
, "Failed to read algorithm list end: %d\n",
2039 return ERR_PTR(ret
);
2042 if (be32_to_cpu(val
) != 0xbedead)
2043 adsp_warn(dsp
, "Algorithm list end %x 0x%x != 0xbedead\n",
2044 reg
, be32_to_cpu(val
));
2046 /* Convert length from DSP words to bytes */
2049 alg
= kzalloc(len
, GFP_KERNEL
| GFP_DMA
);
2051 return ERR_PTR(-ENOMEM
);
2053 reg
= dsp
->ops
->region_to_reg(mem
, pos
);
2055 ret
= regmap_raw_read(dsp
->regmap
, reg
, alg
, len
);
2057 adsp_err(dsp
, "Failed to read algorithm list: %d\n", ret
);
2059 return ERR_PTR(ret
);
2065 static struct wm_adsp_alg_region
*
2066 wm_adsp_find_alg_region(struct wm_adsp
*dsp
, int type
, unsigned int id
)
2068 struct wm_adsp_alg_region
*alg_region
;
2070 list_for_each_entry(alg_region
, &dsp
->alg_regions
, list
) {
2071 if (id
== alg_region
->alg
&& type
== alg_region
->type
)
2078 static struct wm_adsp_alg_region
*wm_adsp_create_region(struct wm_adsp
*dsp
,
2079 int type
, __be32 id
,
2082 struct wm_adsp_alg_region
*alg_region
;
2084 alg_region
= kzalloc(sizeof(*alg_region
), GFP_KERNEL
);
2086 return ERR_PTR(-ENOMEM
);
2088 alg_region
->type
= type
;
2089 alg_region
->alg
= be32_to_cpu(id
);
2090 alg_region
->base
= be32_to_cpu(base
);
2092 list_add_tail(&alg_region
->list
, &dsp
->alg_regions
);
2094 if (dsp
->fw_ver
> 0)
2095 wm_adsp_ctl_fixup_base(dsp
, alg_region
);
2100 static void wm_adsp_free_alg_regions(struct wm_adsp
*dsp
)
2102 struct wm_adsp_alg_region
*alg_region
;
2104 while (!list_empty(&dsp
->alg_regions
)) {
2105 alg_region
= list_first_entry(&dsp
->alg_regions
,
2106 struct wm_adsp_alg_region
,
2108 list_del(&alg_region
->list
);
2113 static void wmfw_parse_id_header(struct wm_adsp
*dsp
,
2114 struct wmfw_id_hdr
*fw
, int nalgs
)
2116 dsp
->fw_id
= be32_to_cpu(fw
->id
);
2117 dsp
->fw_id_version
= be32_to_cpu(fw
->ver
);
2119 adsp_info(dsp
, "Firmware: %x v%d.%d.%d, %d algorithms\n",
2120 dsp
->fw_id
, (dsp
->fw_id_version
& 0xff0000) >> 16,
2121 (dsp
->fw_id_version
& 0xff00) >> 8, dsp
->fw_id_version
& 0xff,
2125 static void wmfw_v3_parse_id_header(struct wm_adsp
*dsp
,
2126 struct wmfw_v3_id_hdr
*fw
, int nalgs
)
2128 dsp
->fw_id
= be32_to_cpu(fw
->id
);
2129 dsp
->fw_id_version
= be32_to_cpu(fw
->ver
);
2130 dsp
->fw_vendor_id
= be32_to_cpu(fw
->vendor_id
);
2132 adsp_info(dsp
, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
2133 dsp
->fw_id
, dsp
->fw_vendor_id
,
2134 (dsp
->fw_id_version
& 0xff0000) >> 16,
2135 (dsp
->fw_id_version
& 0xff00) >> 8, dsp
->fw_id_version
& 0xff,
2139 static int wm_adsp_create_regions(struct wm_adsp
*dsp
, __be32 id
, int nregions
,
2140 int *type
, __be32
*base
)
2142 struct wm_adsp_alg_region
*alg_region
;
2145 for (i
= 0; i
< nregions
; i
++) {
2146 alg_region
= wm_adsp_create_region(dsp
, type
[i
], id
, base
[i
]);
2147 if (IS_ERR(alg_region
))
2148 return PTR_ERR(alg_region
);
2154 static int wm_adsp1_setup_algs(struct wm_adsp
*dsp
)
2156 struct wmfw_adsp1_id_hdr adsp1_id
;
2157 struct wmfw_adsp1_alg_hdr
*adsp1_alg
;
2158 struct wm_adsp_alg_region
*alg_region
;
2159 const struct wm_adsp_region
*mem
;
2160 unsigned int pos
, len
;
2164 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP1_DM
);
2168 ret
= regmap_raw_read(dsp
->regmap
, mem
->base
, &adsp1_id
,
2171 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
2176 n_algs
= be32_to_cpu(adsp1_id
.n_algs
);
2178 wmfw_parse_id_header(dsp
, &adsp1_id
.fw
, n_algs
);
2180 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_ZM
,
2181 adsp1_id
.fw
.id
, adsp1_id
.zm
);
2182 if (IS_ERR(alg_region
))
2183 return PTR_ERR(alg_region
);
2185 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_DM
,
2186 adsp1_id
.fw
.id
, adsp1_id
.dm
);
2187 if (IS_ERR(alg_region
))
2188 return PTR_ERR(alg_region
);
2190 /* Calculate offset and length in DSP words */
2191 pos
= sizeof(adsp1_id
) / sizeof(u32
);
2192 len
= (sizeof(*adsp1_alg
) * n_algs
) / sizeof(u32
);
2194 adsp1_alg
= wm_adsp_read_algs(dsp
, n_algs
, mem
, pos
, len
);
2195 if (IS_ERR(adsp1_alg
))
2196 return PTR_ERR(adsp1_alg
);
2198 for (i
= 0; i
< n_algs
; i
++) {
2199 adsp_info(dsp
, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2200 i
, be32_to_cpu(adsp1_alg
[i
].alg
.id
),
2201 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
2202 (be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff00) >> 8,
2203 be32_to_cpu(adsp1_alg
[i
].alg
.ver
) & 0xff,
2204 be32_to_cpu(adsp1_alg
[i
].dm
),
2205 be32_to_cpu(adsp1_alg
[i
].zm
));
2207 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_DM
,
2208 adsp1_alg
[i
].alg
.id
,
2210 if (IS_ERR(alg_region
)) {
2211 ret
= PTR_ERR(alg_region
);
2214 if (dsp
->fw_ver
== 0) {
2215 if (i
+ 1 < n_algs
) {
2216 len
= be32_to_cpu(adsp1_alg
[i
+ 1].dm
);
2217 len
-= be32_to_cpu(adsp1_alg
[i
].dm
);
2219 wm_adsp_create_control(dsp
, alg_region
, 0,
2221 SNDRV_CTL_ELEM_TYPE_BYTES
);
2223 adsp_warn(dsp
, "Missing length info for region DM with ID %x\n",
2224 be32_to_cpu(adsp1_alg
[i
].alg
.id
));
2228 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP1_ZM
,
2229 adsp1_alg
[i
].alg
.id
,
2231 if (IS_ERR(alg_region
)) {
2232 ret
= PTR_ERR(alg_region
);
2235 if (dsp
->fw_ver
== 0) {
2236 if (i
+ 1 < n_algs
) {
2237 len
= be32_to_cpu(adsp1_alg
[i
+ 1].zm
);
2238 len
-= be32_to_cpu(adsp1_alg
[i
].zm
);
2240 wm_adsp_create_control(dsp
, alg_region
, 0,
2242 SNDRV_CTL_ELEM_TYPE_BYTES
);
2244 adsp_warn(dsp
, "Missing length info for region ZM with ID %x\n",
2245 be32_to_cpu(adsp1_alg
[i
].alg
.id
));
2255 static int wm_adsp2_setup_algs(struct wm_adsp
*dsp
)
2257 struct wmfw_adsp2_id_hdr adsp2_id
;
2258 struct wmfw_adsp2_alg_hdr
*adsp2_alg
;
2259 struct wm_adsp_alg_region
*alg_region
;
2260 const struct wm_adsp_region
*mem
;
2261 unsigned int pos
, len
;
2265 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP2_XM
);
2269 ret
= regmap_raw_read(dsp
->regmap
, mem
->base
, &adsp2_id
,
2272 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
2277 n_algs
= be32_to_cpu(adsp2_id
.n_algs
);
2279 wmfw_parse_id_header(dsp
, &adsp2_id
.fw
, n_algs
);
2281 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_XM
,
2282 adsp2_id
.fw
.id
, adsp2_id
.xm
);
2283 if (IS_ERR(alg_region
))
2284 return PTR_ERR(alg_region
);
2286 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_YM
,
2287 adsp2_id
.fw
.id
, adsp2_id
.ym
);
2288 if (IS_ERR(alg_region
))
2289 return PTR_ERR(alg_region
);
2291 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_ZM
,
2292 adsp2_id
.fw
.id
, adsp2_id
.zm
);
2293 if (IS_ERR(alg_region
))
2294 return PTR_ERR(alg_region
);
2296 /* Calculate offset and length in DSP words */
2297 pos
= sizeof(adsp2_id
) / sizeof(u32
);
2298 len
= (sizeof(*adsp2_alg
) * n_algs
) / sizeof(u32
);
2300 adsp2_alg
= wm_adsp_read_algs(dsp
, n_algs
, mem
, pos
, len
);
2301 if (IS_ERR(adsp2_alg
))
2302 return PTR_ERR(adsp2_alg
);
2304 for (i
= 0; i
< n_algs
; i
++) {
2306 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2307 i
, be32_to_cpu(adsp2_alg
[i
].alg
.id
),
2308 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
2309 (be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff00) >> 8,
2310 be32_to_cpu(adsp2_alg
[i
].alg
.ver
) & 0xff,
2311 be32_to_cpu(adsp2_alg
[i
].xm
),
2312 be32_to_cpu(adsp2_alg
[i
].ym
),
2313 be32_to_cpu(adsp2_alg
[i
].zm
));
2315 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_XM
,
2316 adsp2_alg
[i
].alg
.id
,
2318 if (IS_ERR(alg_region
)) {
2319 ret
= PTR_ERR(alg_region
);
2322 if (dsp
->fw_ver
== 0) {
2323 if (i
+ 1 < n_algs
) {
2324 len
= be32_to_cpu(adsp2_alg
[i
+ 1].xm
);
2325 len
-= be32_to_cpu(adsp2_alg
[i
].xm
);
2327 wm_adsp_create_control(dsp
, alg_region
, 0,
2329 SNDRV_CTL_ELEM_TYPE_BYTES
);
2331 adsp_warn(dsp
, "Missing length info for region XM with ID %x\n",
2332 be32_to_cpu(adsp2_alg
[i
].alg
.id
));
2336 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_YM
,
2337 adsp2_alg
[i
].alg
.id
,
2339 if (IS_ERR(alg_region
)) {
2340 ret
= PTR_ERR(alg_region
);
2343 if (dsp
->fw_ver
== 0) {
2344 if (i
+ 1 < n_algs
) {
2345 len
= be32_to_cpu(adsp2_alg
[i
+ 1].ym
);
2346 len
-= be32_to_cpu(adsp2_alg
[i
].ym
);
2348 wm_adsp_create_control(dsp
, alg_region
, 0,
2350 SNDRV_CTL_ELEM_TYPE_BYTES
);
2352 adsp_warn(dsp
, "Missing length info for region YM with ID %x\n",
2353 be32_to_cpu(adsp2_alg
[i
].alg
.id
));
2357 alg_region
= wm_adsp_create_region(dsp
, WMFW_ADSP2_ZM
,
2358 adsp2_alg
[i
].alg
.id
,
2360 if (IS_ERR(alg_region
)) {
2361 ret
= PTR_ERR(alg_region
);
2364 if (dsp
->fw_ver
== 0) {
2365 if (i
+ 1 < n_algs
) {
2366 len
= be32_to_cpu(adsp2_alg
[i
+ 1].zm
);
2367 len
-= be32_to_cpu(adsp2_alg
[i
].zm
);
2369 wm_adsp_create_control(dsp
, alg_region
, 0,
2371 SNDRV_CTL_ELEM_TYPE_BYTES
);
2373 adsp_warn(dsp
, "Missing length info for region ZM with ID %x\n",
2374 be32_to_cpu(adsp2_alg
[i
].alg
.id
));
2384 static int wm_halo_create_regions(struct wm_adsp
*dsp
, __be32 id
,
2385 __be32 xm_base
, __be32 ym_base
)
2388 WMFW_ADSP2_XM
, WMFW_HALO_XM_PACKED
,
2389 WMFW_ADSP2_YM
, WMFW_HALO_YM_PACKED
2391 __be32 bases
[] = { xm_base
, xm_base
, ym_base
, ym_base
};
2393 return wm_adsp_create_regions(dsp
, id
, ARRAY_SIZE(types
), types
, bases
);
2396 static int wm_halo_setup_algs(struct wm_adsp
*dsp
)
2398 struct wmfw_halo_id_hdr halo_id
;
2399 struct wmfw_halo_alg_hdr
*halo_alg
;
2400 const struct wm_adsp_region
*mem
;
2401 unsigned int pos
, len
;
2405 mem
= wm_adsp_find_region(dsp
, WMFW_ADSP2_XM
);
2409 ret
= regmap_raw_read(dsp
->regmap
, mem
->base
, &halo_id
,
2412 adsp_err(dsp
, "Failed to read algorithm info: %d\n",
2417 n_algs
= be32_to_cpu(halo_id
.n_algs
);
2419 wmfw_v3_parse_id_header(dsp
, &halo_id
.fw
, n_algs
);
2421 ret
= wm_halo_create_regions(dsp
, halo_id
.fw
.id
,
2422 halo_id
.xm_base
, halo_id
.ym_base
);
2426 /* Calculate offset and length in DSP words */
2427 pos
= sizeof(halo_id
) / sizeof(u32
);
2428 len
= (sizeof(*halo_alg
) * n_algs
) / sizeof(u32
);
2430 halo_alg
= wm_adsp_read_algs(dsp
, n_algs
, mem
, pos
, len
);
2431 if (IS_ERR(halo_alg
))
2432 return PTR_ERR(halo_alg
);
2434 for (i
= 0; i
< n_algs
; i
++) {
2436 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
2437 i
, be32_to_cpu(halo_alg
[i
].alg
.id
),
2438 (be32_to_cpu(halo_alg
[i
].alg
.ver
) & 0xff0000) >> 16,
2439 (be32_to_cpu(halo_alg
[i
].alg
.ver
) & 0xff00) >> 8,
2440 be32_to_cpu(halo_alg
[i
].alg
.ver
) & 0xff,
2441 be32_to_cpu(halo_alg
[i
].xm_base
),
2442 be32_to_cpu(halo_alg
[i
].ym_base
));
2444 ret
= wm_halo_create_regions(dsp
, halo_alg
[i
].alg
.id
,
2445 halo_alg
[i
].xm_base
,
2446 halo_alg
[i
].ym_base
);
2456 static int wm_adsp_load_coeff(struct wm_adsp
*dsp
)
2458 LIST_HEAD(buf_list
);
2459 struct regmap
*regmap
= dsp
->regmap
;
2460 struct wmfw_coeff_hdr
*hdr
;
2461 struct wmfw_coeff_item
*blk
;
2462 const struct firmware
*firmware
;
2463 const struct wm_adsp_region
*mem
;
2464 struct wm_adsp_alg_region
*alg_region
;
2465 const char *region_name
;
2466 int ret
, pos
, blocks
, type
, offset
, reg
;
2468 struct wm_adsp_buf
*buf
;
2470 file
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
2474 snprintf(file
, PAGE_SIZE
, "%s-%s-%s.bin", dsp
->part
, dsp
->fwf_name
,
2475 wm_adsp_fw
[dsp
->fw
].file
);
2476 file
[PAGE_SIZE
- 1] = '\0';
2478 ret
= request_firmware(&firmware
, file
, dsp
->dev
);
2480 adsp_warn(dsp
, "Failed to request '%s'\n", file
);
2486 if (sizeof(*hdr
) >= firmware
->size
) {
2487 adsp_err(dsp
, "%s: file too short, %zu bytes\n",
2488 file
, firmware
->size
);
2492 hdr
= (void *)&firmware
->data
[0];
2493 if (memcmp(hdr
->magic
, "WMDR", 4) != 0) {
2494 adsp_err(dsp
, "%s: invalid magic\n", file
);
2498 switch (be32_to_cpu(hdr
->rev
) & 0xff) {
2502 adsp_err(dsp
, "%s: Unsupported coefficient file format %d\n",
2503 file
, be32_to_cpu(hdr
->rev
) & 0xff);
2508 adsp_dbg(dsp
, "%s: v%d.%d.%d\n", file
,
2509 (le32_to_cpu(hdr
->ver
) >> 16) & 0xff,
2510 (le32_to_cpu(hdr
->ver
) >> 8) & 0xff,
2511 le32_to_cpu(hdr
->ver
) & 0xff);
2513 pos
= le32_to_cpu(hdr
->len
);
2516 while (pos
< firmware
->size
&&
2517 sizeof(*blk
) < firmware
->size
- pos
) {
2518 blk
= (void *)(&firmware
->data
[pos
]);
2520 type
= le16_to_cpu(blk
->type
);
2521 offset
= le16_to_cpu(blk
->offset
);
2523 adsp_dbg(dsp
, "%s.%d: %x v%d.%d.%d\n",
2524 file
, blocks
, le32_to_cpu(blk
->id
),
2525 (le32_to_cpu(blk
->ver
) >> 16) & 0xff,
2526 (le32_to_cpu(blk
->ver
) >> 8) & 0xff,
2527 le32_to_cpu(blk
->ver
) & 0xff);
2528 adsp_dbg(dsp
, "%s.%d: %d bytes at 0x%x in %x\n",
2529 file
, blocks
, le32_to_cpu(blk
->len
), offset
, type
);
2532 region_name
= "Unknown";
2534 case (WMFW_NAME_TEXT
<< 8):
2535 case (WMFW_INFO_TEXT
<< 8):
2537 case (WMFW_ABSOLUTE
<< 8):
2539 * Old files may use this for global
2542 if (le32_to_cpu(blk
->id
) == dsp
->fw_id
&&
2544 region_name
= "global coefficients";
2545 mem
= wm_adsp_find_region(dsp
, type
);
2547 adsp_err(dsp
, "No ZM\n");
2550 reg
= dsp
->ops
->region_to_reg(mem
, 0);
2553 region_name
= "register";
2562 case WMFW_HALO_XM_PACKED
:
2563 case WMFW_HALO_YM_PACKED
:
2564 case WMFW_HALO_PM_PACKED
:
2565 adsp_dbg(dsp
, "%s.%d: %d bytes in %x for %x\n",
2566 file
, blocks
, le32_to_cpu(blk
->len
),
2567 type
, le32_to_cpu(blk
->id
));
2569 mem
= wm_adsp_find_region(dsp
, type
);
2571 adsp_err(dsp
, "No base for region %x\n", type
);
2575 alg_region
= wm_adsp_find_alg_region(dsp
, type
,
2576 le32_to_cpu(blk
->id
));
2578 reg
= alg_region
->base
;
2579 reg
= dsp
->ops
->region_to_reg(mem
, reg
);
2582 adsp_err(dsp
, "No %x for algorithm %x\n",
2583 type
, le32_to_cpu(blk
->id
));
2588 adsp_err(dsp
, "%s.%d: Unknown region type %x at %d\n",
2589 file
, blocks
, type
, pos
);
2594 if (le32_to_cpu(blk
->len
) >
2595 firmware
->size
- pos
- sizeof(*blk
)) {
2597 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2598 file
, blocks
, region_name
,
2599 le32_to_cpu(blk
->len
),
2605 buf
= wm_adsp_buf_alloc(blk
->data
,
2606 le32_to_cpu(blk
->len
),
2609 adsp_err(dsp
, "Out of memory\n");
2614 adsp_dbg(dsp
, "%s.%d: Writing %d bytes at %x\n",
2615 file
, blocks
, le32_to_cpu(blk
->len
),
2617 ret
= regmap_raw_write_async(regmap
, reg
, buf
->buf
,
2618 le32_to_cpu(blk
->len
));
2621 "%s.%d: Failed to write to %x in %s: %d\n",
2622 file
, blocks
, reg
, region_name
, ret
);
2626 pos
+= (le32_to_cpu(blk
->len
) + sizeof(*blk
) + 3) & ~0x03;
2630 ret
= regmap_async_complete(regmap
);
2632 adsp_err(dsp
, "Failed to complete async write: %d\n", ret
);
2634 if (pos
> firmware
->size
)
2635 adsp_warn(dsp
, "%s.%d: %zu bytes at end of file\n",
2636 file
, blocks
, pos
- firmware
->size
);
2638 wm_adsp_debugfs_save_binname(dsp
, file
);
2641 regmap_async_complete(regmap
);
2642 release_firmware(firmware
);
2643 wm_adsp_buf_free(&buf_list
);
2649 static int wm_adsp_create_name(struct wm_adsp
*dsp
)
2654 dsp
->name
= devm_kasprintf(dsp
->dev
, GFP_KERNEL
, "DSP%d",
2660 if (!dsp
->fwf_name
) {
2661 p
= devm_kstrdup(dsp
->dev
, dsp
->name
, GFP_KERNEL
);
2666 for (; *p
!= 0; ++p
)
2673 static int wm_adsp_common_init(struct wm_adsp
*dsp
)
2677 ret
= wm_adsp_create_name(dsp
);
2681 INIT_LIST_HEAD(&dsp
->alg_regions
);
2682 INIT_LIST_HEAD(&dsp
->ctl_list
);
2683 INIT_LIST_HEAD(&dsp
->compr_list
);
2684 INIT_LIST_HEAD(&dsp
->buffer_list
);
2686 mutex_init(&dsp
->pwr_lock
);
2691 int wm_adsp1_init(struct wm_adsp
*dsp
)
2693 dsp
->ops
= &wm_adsp1_ops
;
2695 return wm_adsp_common_init(dsp
);
2697 EXPORT_SYMBOL_GPL(wm_adsp1_init
);
2699 int wm_adsp1_event(struct snd_soc_dapm_widget
*w
,
2700 struct snd_kcontrol
*kcontrol
,
2703 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
2704 struct wm_adsp
*dsps
= snd_soc_component_get_drvdata(component
);
2705 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
2706 struct wm_coeff_ctl
*ctl
;
2710 dsp
->component
= component
;
2712 mutex_lock(&dsp
->pwr_lock
);
2715 case SND_SOC_DAPM_POST_PMU
:
2716 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
2717 ADSP1_SYS_ENA
, ADSP1_SYS_ENA
);
2720 * For simplicity set the DSP clock rate to be the
2721 * SYSCLK rate rather than making it configurable.
2723 if (dsp
->sysclk_reg
) {
2724 ret
= regmap_read(dsp
->regmap
, dsp
->sysclk_reg
, &val
);
2726 adsp_err(dsp
, "Failed to read SYSCLK state: %d\n",
2731 val
= (val
& dsp
->sysclk_mask
) >> dsp
->sysclk_shift
;
2733 ret
= regmap_update_bits(dsp
->regmap
,
2734 dsp
->base
+ ADSP1_CONTROL_31
,
2735 ADSP1_CLK_SEL_MASK
, val
);
2737 adsp_err(dsp
, "Failed to set clock rate: %d\n",
2743 ret
= wm_adsp_load(dsp
);
2747 ret
= wm_adsp1_setup_algs(dsp
);
2751 ret
= wm_adsp_load_coeff(dsp
);
2755 /* Initialize caches for enabled and unset controls */
2756 ret
= wm_coeff_init_control_caches(dsp
);
2760 /* Sync set controls */
2761 ret
= wm_coeff_sync_controls(dsp
);
2767 /* Start the core running */
2768 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
2769 ADSP1_CORE_ENA
| ADSP1_START
,
2770 ADSP1_CORE_ENA
| ADSP1_START
);
2772 dsp
->running
= true;
2775 case SND_SOC_DAPM_PRE_PMD
:
2776 dsp
->running
= false;
2777 dsp
->booted
= false;
2780 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
2781 ADSP1_CORE_ENA
| ADSP1_START
, 0);
2783 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_19
,
2784 ADSP1_WDMA_BUFFER_LENGTH_MASK
, 0);
2786 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
2789 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
)
2793 wm_adsp_free_alg_regions(dsp
);
2800 mutex_unlock(&dsp
->pwr_lock
);
2805 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP1_CONTROL_30
,
2808 mutex_unlock(&dsp
->pwr_lock
);
2812 EXPORT_SYMBOL_GPL(wm_adsp1_event
);
2814 static int wm_adsp2v2_enable_core(struct wm_adsp
*dsp
)
2819 /* Wait for the RAM to start, should be near instantaneous */
2820 for (count
= 0; count
< 10; ++count
) {
2821 ret
= regmap_read(dsp
->regmap
, dsp
->base
+ ADSP2_STATUS1
, &val
);
2825 if (val
& ADSP2_RAM_RDY
)
2828 usleep_range(250, 500);
2831 if (!(val
& ADSP2_RAM_RDY
)) {
2832 adsp_err(dsp
, "Failed to start DSP RAM\n");
2836 adsp_dbg(dsp
, "RAM ready after %d polls\n", count
);
2841 static int wm_adsp2_enable_core(struct wm_adsp
*dsp
)
2845 ret
= regmap_update_bits_async(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
2846 ADSP2_SYS_ENA
, ADSP2_SYS_ENA
);
2850 return wm_adsp2v2_enable_core(dsp
);
2853 static int wm_adsp2_lock(struct wm_adsp
*dsp
, unsigned int lock_regions
)
2855 struct regmap
*regmap
= dsp
->regmap
;
2856 unsigned int code0
, code1
, lock_reg
;
2858 if (!(lock_regions
& WM_ADSP2_REGION_ALL
))
2861 lock_regions
&= WM_ADSP2_REGION_ALL
;
2862 lock_reg
= dsp
->base
+ ADSP2_LOCK_REGION_1_LOCK_REGION_0
;
2864 while (lock_regions
) {
2866 if (lock_regions
& BIT(0)) {
2867 code0
= ADSP2_LOCK_CODE_0
;
2868 code1
= ADSP2_LOCK_CODE_1
;
2870 if (lock_regions
& BIT(1)) {
2871 code0
|= ADSP2_LOCK_CODE_0
<< ADSP2_LOCK_REGION_SHIFT
;
2872 code1
|= ADSP2_LOCK_CODE_1
<< ADSP2_LOCK_REGION_SHIFT
;
2874 regmap_write(regmap
, lock_reg
, code0
);
2875 regmap_write(regmap
, lock_reg
, code1
);
2883 static int wm_adsp2_enable_memory(struct wm_adsp
*dsp
)
2885 return regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
2886 ADSP2_MEM_ENA
, ADSP2_MEM_ENA
);
2889 static void wm_adsp2_disable_memory(struct wm_adsp
*dsp
)
2891 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
2895 static void wm_adsp2_disable_core(struct wm_adsp
*dsp
)
2897 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_RDMA_CONFIG_1
, 0);
2898 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_WDMA_CONFIG_1
, 0);
2899 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_WDMA_CONFIG_2
, 0);
2901 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
2905 static void wm_adsp2v2_disable_core(struct wm_adsp
*dsp
)
2907 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_RDMA_CONFIG_1
, 0);
2908 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2_WDMA_CONFIG_1
, 0);
2909 regmap_write(dsp
->regmap
, dsp
->base
+ ADSP2V2_WDMA_CONFIG_2
, 0);
2912 static void wm_adsp_boot_work(struct work_struct
*work
)
2914 struct wm_adsp
*dsp
= container_of(work
,
2919 mutex_lock(&dsp
->pwr_lock
);
2921 if (dsp
->ops
->enable_memory
) {
2922 ret
= dsp
->ops
->enable_memory(dsp
);
2927 if (dsp
->ops
->enable_core
) {
2928 ret
= dsp
->ops
->enable_core(dsp
);
2933 ret
= wm_adsp_load(dsp
);
2937 ret
= dsp
->ops
->setup_algs(dsp
);
2941 ret
= wm_adsp_load_coeff(dsp
);
2945 /* Initialize caches for enabled and unset controls */
2946 ret
= wm_coeff_init_control_caches(dsp
);
2950 if (dsp
->ops
->disable_core
)
2951 dsp
->ops
->disable_core(dsp
);
2955 mutex_unlock(&dsp
->pwr_lock
);
2960 if (dsp
->ops
->disable_core
)
2961 dsp
->ops
->disable_core(dsp
);
2963 if (dsp
->ops
->disable_memory
)
2964 dsp
->ops
->disable_memory(dsp
);
2966 mutex_unlock(&dsp
->pwr_lock
);
2969 static int wm_halo_configure_mpu(struct wm_adsp
*dsp
, unsigned int lock_regions
)
2971 struct reg_sequence config
[] = {
2972 { dsp
->base
+ HALO_MPU_LOCK_CONFIG
, 0x5555 },
2973 { dsp
->base
+ HALO_MPU_LOCK_CONFIG
, 0xAAAA },
2974 { dsp
->base
+ HALO_MPU_XMEM_ACCESS_0
, 0xFFFFFFFF },
2975 { dsp
->base
+ HALO_MPU_YMEM_ACCESS_0
, 0xFFFFFFFF },
2976 { dsp
->base
+ HALO_MPU_WINDOW_ACCESS_0
, lock_regions
},
2977 { dsp
->base
+ HALO_MPU_XREG_ACCESS_0
, lock_regions
},
2978 { dsp
->base
+ HALO_MPU_YREG_ACCESS_0
, lock_regions
},
2979 { dsp
->base
+ HALO_MPU_XMEM_ACCESS_1
, 0xFFFFFFFF },
2980 { dsp
->base
+ HALO_MPU_YMEM_ACCESS_1
, 0xFFFFFFFF },
2981 { dsp
->base
+ HALO_MPU_WINDOW_ACCESS_1
, lock_regions
},
2982 { dsp
->base
+ HALO_MPU_XREG_ACCESS_1
, lock_regions
},
2983 { dsp
->base
+ HALO_MPU_YREG_ACCESS_1
, lock_regions
},
2984 { dsp
->base
+ HALO_MPU_XMEM_ACCESS_2
, 0xFFFFFFFF },
2985 { dsp
->base
+ HALO_MPU_YMEM_ACCESS_2
, 0xFFFFFFFF },
2986 { dsp
->base
+ HALO_MPU_WINDOW_ACCESS_2
, lock_regions
},
2987 { dsp
->base
+ HALO_MPU_XREG_ACCESS_2
, lock_regions
},
2988 { dsp
->base
+ HALO_MPU_YREG_ACCESS_2
, lock_regions
},
2989 { dsp
->base
+ HALO_MPU_XMEM_ACCESS_3
, 0xFFFFFFFF },
2990 { dsp
->base
+ HALO_MPU_YMEM_ACCESS_3
, 0xFFFFFFFF },
2991 { dsp
->base
+ HALO_MPU_WINDOW_ACCESS_3
, lock_regions
},
2992 { dsp
->base
+ HALO_MPU_XREG_ACCESS_3
, lock_regions
},
2993 { dsp
->base
+ HALO_MPU_YREG_ACCESS_3
, lock_regions
},
2994 { dsp
->base
+ HALO_MPU_LOCK_CONFIG
, 0 },
2997 return regmap_multi_reg_write(dsp
->regmap
, config
, ARRAY_SIZE(config
));
3000 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget
*w
, unsigned int freq
)
3002 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
3003 struct wm_adsp
*dsps
= snd_soc_component_get_drvdata(component
);
3004 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
3007 ret
= regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CLOCKING
,
3009 freq
<< ADSP2_CLK_SEL_SHIFT
);
3011 adsp_err(dsp
, "Failed to set clock rate: %d\n", ret
);
3015 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk
);
3017 int wm_adsp2_preloader_get(struct snd_kcontrol
*kcontrol
,
3018 struct snd_ctl_elem_value
*ucontrol
)
3020 struct snd_soc_component
*component
= snd_soc_kcontrol_component(kcontrol
);
3021 struct wm_adsp
*dsps
= snd_soc_component_get_drvdata(component
);
3022 struct soc_mixer_control
*mc
=
3023 (struct soc_mixer_control
*)kcontrol
->private_value
;
3024 struct wm_adsp
*dsp
= &dsps
[mc
->shift
- 1];
3026 ucontrol
->value
.integer
.value
[0] = dsp
->preloaded
;
3030 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get
);
3032 int wm_adsp2_preloader_put(struct snd_kcontrol
*kcontrol
,
3033 struct snd_ctl_elem_value
*ucontrol
)
3035 struct snd_soc_component
*component
= snd_soc_kcontrol_component(kcontrol
);
3036 struct wm_adsp
*dsps
= snd_soc_component_get_drvdata(component
);
3037 struct snd_soc_dapm_context
*dapm
= snd_soc_component_get_dapm(component
);
3038 struct soc_mixer_control
*mc
=
3039 (struct soc_mixer_control
*)kcontrol
->private_value
;
3040 struct wm_adsp
*dsp
= &dsps
[mc
->shift
- 1];
3043 snprintf(preload
, ARRAY_SIZE(preload
), "%s Preload", dsp
->name
);
3045 dsp
->preloaded
= ucontrol
->value
.integer
.value
[0];
3047 if (ucontrol
->value
.integer
.value
[0])
3048 snd_soc_component_force_enable_pin(component
, preload
);
3050 snd_soc_component_disable_pin(component
, preload
);
3052 snd_soc_dapm_sync(dapm
);
3054 flush_work(&dsp
->boot_work
);
3058 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put
);
3060 static void wm_adsp_stop_watchdog(struct wm_adsp
*dsp
)
3062 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_WATCHDOG
,
3063 ADSP2_WDT_ENA_MASK
, 0);
3066 static void wm_halo_stop_watchdog(struct wm_adsp
*dsp
)
3068 regmap_update_bits(dsp
->regmap
, dsp
->base
+ HALO_WDT_CONTROL
,
3069 HALO_WDT_EN_MASK
, 0);
3072 int wm_adsp_early_event(struct snd_soc_dapm_widget
*w
,
3073 struct snd_kcontrol
*kcontrol
, int event
)
3075 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
3076 struct wm_adsp
*dsps
= snd_soc_component_get_drvdata(component
);
3077 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
3078 struct wm_coeff_ctl
*ctl
;
3081 case SND_SOC_DAPM_PRE_PMU
:
3082 queue_work(system_unbound_wq
, &dsp
->boot_work
);
3084 case SND_SOC_DAPM_PRE_PMD
:
3085 mutex_lock(&dsp
->pwr_lock
);
3087 wm_adsp_debugfs_clear(dsp
);
3090 dsp
->fw_id_version
= 0;
3092 dsp
->booted
= false;
3094 if (dsp
->ops
->disable_memory
)
3095 dsp
->ops
->disable_memory(dsp
);
3097 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
)
3100 wm_adsp_free_alg_regions(dsp
);
3102 mutex_unlock(&dsp
->pwr_lock
);
3104 adsp_dbg(dsp
, "Shutdown complete\n");
3112 EXPORT_SYMBOL_GPL(wm_adsp_early_event
);
3114 static int wm_adsp2_start_core(struct wm_adsp
*dsp
)
3116 return regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
3117 ADSP2_CORE_ENA
| ADSP2_START
,
3118 ADSP2_CORE_ENA
| ADSP2_START
);
3121 static void wm_adsp2_stop_core(struct wm_adsp
*dsp
)
3123 regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
3124 ADSP2_CORE_ENA
| ADSP2_START
, 0);
3127 int wm_adsp_event(struct snd_soc_dapm_widget
*w
,
3128 struct snd_kcontrol
*kcontrol
, int event
)
3130 struct snd_soc_component
*component
= snd_soc_dapm_to_component(w
->dapm
);
3131 struct wm_adsp
*dsps
= snd_soc_component_get_drvdata(component
);
3132 struct wm_adsp
*dsp
= &dsps
[w
->shift
];
3136 case SND_SOC_DAPM_POST_PMU
:
3137 flush_work(&dsp
->boot_work
);
3139 mutex_lock(&dsp
->pwr_lock
);
3146 if (dsp
->ops
->enable_core
) {
3147 ret
= dsp
->ops
->enable_core(dsp
);
3152 /* Sync set controls */
3153 ret
= wm_coeff_sync_controls(dsp
);
3157 if (dsp
->ops
->lock_memory
) {
3158 ret
= dsp
->ops
->lock_memory(dsp
, dsp
->lock_regions
);
3160 adsp_err(dsp
, "Error configuring MPU: %d\n",
3166 if (dsp
->ops
->start_core
) {
3167 ret
= dsp
->ops
->start_core(dsp
);
3172 if (wm_adsp_fw
[dsp
->fw
].num_caps
!= 0) {
3173 ret
= wm_adsp_buffer_init(dsp
);
3178 dsp
->running
= true;
3180 mutex_unlock(&dsp
->pwr_lock
);
3183 case SND_SOC_DAPM_PRE_PMD
:
3184 /* Tell the firmware to cleanup */
3185 wm_adsp_signal_event_controls(dsp
, WM_ADSP_FW_EVENT_SHUTDOWN
);
3187 if (dsp
->ops
->stop_watchdog
)
3188 dsp
->ops
->stop_watchdog(dsp
);
3190 /* Log firmware state, it can be useful for analysis */
3191 if (dsp
->ops
->show_fw_status
)
3192 dsp
->ops
->show_fw_status(dsp
);
3194 mutex_lock(&dsp
->pwr_lock
);
3196 dsp
->running
= false;
3198 if (dsp
->ops
->stop_core
)
3199 dsp
->ops
->stop_core(dsp
);
3200 if (dsp
->ops
->disable_core
)
3201 dsp
->ops
->disable_core(dsp
);
3203 if (wm_adsp_fw
[dsp
->fw
].num_caps
!= 0)
3204 wm_adsp_buffer_free(dsp
);
3206 dsp
->fatal_error
= false;
3208 mutex_unlock(&dsp
->pwr_lock
);
3210 adsp_dbg(dsp
, "Execution stopped\n");
3219 if (dsp
->ops
->stop_core
)
3220 dsp
->ops
->stop_core(dsp
);
3221 if (dsp
->ops
->disable_core
)
3222 dsp
->ops
->disable_core(dsp
);
3223 mutex_unlock(&dsp
->pwr_lock
);
3226 EXPORT_SYMBOL_GPL(wm_adsp_event
);
3228 static int wm_halo_start_core(struct wm_adsp
*dsp
)
3230 return regmap_update_bits(dsp
->regmap
,
3231 dsp
->base
+ HALO_CCM_CORE_CONTROL
,
3232 HALO_CORE_EN
, HALO_CORE_EN
);
3235 static void wm_halo_stop_core(struct wm_adsp
*dsp
)
3237 regmap_update_bits(dsp
->regmap
, dsp
->base
+ HALO_CCM_CORE_CONTROL
,
3240 /* reset halo core with CORE_SOFT_RESET */
3241 regmap_update_bits(dsp
->regmap
, dsp
->base
+ HALO_CORE_SOFT_RESET
,
3242 HALO_CORE_SOFT_RESET_MASK
, 1);
3245 int wm_adsp2_component_probe(struct wm_adsp
*dsp
, struct snd_soc_component
*component
)
3249 snprintf(preload
, ARRAY_SIZE(preload
), "%s Preload", dsp
->name
);
3250 snd_soc_component_disable_pin(component
, preload
);
3252 wm_adsp2_init_debugfs(dsp
, component
);
3254 dsp
->component
= component
;
3258 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe
);
3260 int wm_adsp2_component_remove(struct wm_adsp
*dsp
, struct snd_soc_component
*component
)
3262 wm_adsp2_cleanup_debugfs(dsp
);
3266 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove
);
3268 int wm_adsp2_init(struct wm_adsp
*dsp
)
3272 ret
= wm_adsp_common_init(dsp
);
3279 * Disable the DSP memory by default when in reset for a small
3282 ret
= regmap_update_bits(dsp
->regmap
, dsp
->base
+ ADSP2_CONTROL
,
3286 "Failed to clear memory retention: %d\n", ret
);
3290 dsp
->ops
= &wm_adsp2_ops
[0];
3293 dsp
->ops
= &wm_adsp2_ops
[1];
3296 dsp
->ops
= &wm_adsp2_ops
[2];
3300 INIT_WORK(&dsp
->boot_work
, wm_adsp_boot_work
);
3304 EXPORT_SYMBOL_GPL(wm_adsp2_init
);
3306 int wm_halo_init(struct wm_adsp
*dsp
)
3310 ret
= wm_adsp_common_init(dsp
);
3314 dsp
->ops
= &wm_halo_ops
;
3316 INIT_WORK(&dsp
->boot_work
, wm_adsp_boot_work
);
3320 EXPORT_SYMBOL_GPL(wm_halo_init
);
3322 void wm_adsp2_remove(struct wm_adsp
*dsp
)
3324 struct wm_coeff_ctl
*ctl
;
3326 while (!list_empty(&dsp
->ctl_list
)) {
3327 ctl
= list_first_entry(&dsp
->ctl_list
, struct wm_coeff_ctl
,
3329 list_del(&ctl
->list
);
3330 wm_adsp_free_ctl_blk(ctl
);
3333 EXPORT_SYMBOL_GPL(wm_adsp2_remove
);
3335 static inline int wm_adsp_compr_attached(struct wm_adsp_compr
*compr
)
3337 return compr
->buf
!= NULL
;
3340 static int wm_adsp_compr_attach(struct wm_adsp_compr
*compr
)
3342 struct wm_adsp_compr_buf
*buf
= NULL
, *tmp
;
3344 if (compr
->dsp
->fatal_error
)
3347 list_for_each_entry(tmp
, &compr
->dsp
->buffer_list
, list
) {
3348 if (!tmp
->name
|| !strcmp(compr
->name
, tmp
->name
)) {
3363 static void wm_adsp_compr_detach(struct wm_adsp_compr
*compr
)
3368 /* Wake the poll so it can see buffer is no longer attached */
3370 snd_compr_fragment_elapsed(compr
->stream
);
3372 if (wm_adsp_compr_attached(compr
)) {
3373 compr
->buf
->compr
= NULL
;
3378 int wm_adsp_compr_open(struct wm_adsp
*dsp
, struct snd_compr_stream
*stream
)
3380 struct wm_adsp_compr
*compr
, *tmp
;
3381 struct snd_soc_pcm_runtime
*rtd
= stream
->private_data
;
3384 mutex_lock(&dsp
->pwr_lock
);
3386 if (wm_adsp_fw
[dsp
->fw
].num_caps
== 0) {
3387 adsp_err(dsp
, "%s: Firmware does not support compressed API\n",
3388 rtd
->codec_dai
->name
);
3393 if (wm_adsp_fw
[dsp
->fw
].compr_direction
!= stream
->direction
) {
3394 adsp_err(dsp
, "%s: Firmware does not support stream direction\n",
3395 rtd
->codec_dai
->name
);
3400 list_for_each_entry(tmp
, &dsp
->compr_list
, list
) {
3401 if (!strcmp(tmp
->name
, rtd
->codec_dai
->name
)) {
3402 adsp_err(dsp
, "%s: Only a single stream supported per dai\n",
3403 rtd
->codec_dai
->name
);
3409 compr
= kzalloc(sizeof(*compr
), GFP_KERNEL
);
3416 compr
->stream
= stream
;
3417 compr
->name
= rtd
->codec_dai
->name
;
3419 list_add_tail(&compr
->list
, &dsp
->compr_list
);
3421 stream
->runtime
->private_data
= compr
;
3424 mutex_unlock(&dsp
->pwr_lock
);
3428 EXPORT_SYMBOL_GPL(wm_adsp_compr_open
);
3430 int wm_adsp_compr_free(struct snd_compr_stream
*stream
)
3432 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
3433 struct wm_adsp
*dsp
= compr
->dsp
;
3435 mutex_lock(&dsp
->pwr_lock
);
3437 wm_adsp_compr_detach(compr
);
3438 list_del(&compr
->list
);
3440 kfree(compr
->raw_buf
);
3443 mutex_unlock(&dsp
->pwr_lock
);
3447 EXPORT_SYMBOL_GPL(wm_adsp_compr_free
);
3449 static int wm_adsp_compr_check_params(struct snd_compr_stream
*stream
,
3450 struct snd_compr_params
*params
)
3452 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
3453 struct wm_adsp
*dsp
= compr
->dsp
;
3454 const struct wm_adsp_fw_caps
*caps
;
3455 const struct snd_codec_desc
*desc
;
3458 if (params
->buffer
.fragment_size
< WM_ADSP_MIN_FRAGMENT_SIZE
||
3459 params
->buffer
.fragment_size
> WM_ADSP_MAX_FRAGMENT_SIZE
||
3460 params
->buffer
.fragments
< WM_ADSP_MIN_FRAGMENTS
||
3461 params
->buffer
.fragments
> WM_ADSP_MAX_FRAGMENTS
||
3462 params
->buffer
.fragment_size
% WM_ADSP_DATA_WORD_SIZE
) {
3463 compr_err(compr
, "Invalid buffer fragsize=%d fragments=%d\n",
3464 params
->buffer
.fragment_size
,
3465 params
->buffer
.fragments
);
3470 for (i
= 0; i
< wm_adsp_fw
[dsp
->fw
].num_caps
; i
++) {
3471 caps
= &wm_adsp_fw
[dsp
->fw
].caps
[i
];
3474 if (caps
->id
!= params
->codec
.id
)
3477 if (stream
->direction
== SND_COMPRESS_PLAYBACK
) {
3478 if (desc
->max_ch
< params
->codec
.ch_out
)
3481 if (desc
->max_ch
< params
->codec
.ch_in
)
3485 if (!(desc
->formats
& (1 << params
->codec
.format
)))
3488 for (j
= 0; j
< desc
->num_sample_rates
; ++j
)
3489 if (desc
->sample_rates
[j
] == params
->codec
.sample_rate
)
3493 compr_err(compr
, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3494 params
->codec
.id
, params
->codec
.ch_in
, params
->codec
.ch_out
,
3495 params
->codec
.sample_rate
, params
->codec
.format
);
3499 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr
*compr
)
3501 return compr
->size
.fragment_size
/ WM_ADSP_DATA_WORD_SIZE
;
3504 int wm_adsp_compr_set_params(struct snd_compr_stream
*stream
,
3505 struct snd_compr_params
*params
)
3507 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
3511 ret
= wm_adsp_compr_check_params(stream
, params
);
3515 compr
->size
= params
->buffer
;
3517 compr_dbg(compr
, "fragment_size=%d fragments=%d\n",
3518 compr
->size
.fragment_size
, compr
->size
.fragments
);
3520 size
= wm_adsp_compr_frag_words(compr
) * sizeof(*compr
->raw_buf
);
3521 compr
->raw_buf
= kmalloc(size
, GFP_DMA
| GFP_KERNEL
);
3522 if (!compr
->raw_buf
)
3525 compr
->sample_rate
= params
->codec
.sample_rate
;
3529 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params
);
3531 int wm_adsp_compr_get_caps(struct snd_compr_stream
*stream
,
3532 struct snd_compr_caps
*caps
)
3534 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
3535 int fw
= compr
->dsp
->fw
;
3538 if (wm_adsp_fw
[fw
].caps
) {
3539 for (i
= 0; i
< wm_adsp_fw
[fw
].num_caps
; i
++)
3540 caps
->codecs
[i
] = wm_adsp_fw
[fw
].caps
[i
].id
;
3542 caps
->num_codecs
= i
;
3543 caps
->direction
= wm_adsp_fw
[fw
].compr_direction
;
3545 caps
->min_fragment_size
= WM_ADSP_MIN_FRAGMENT_SIZE
;
3546 caps
->max_fragment_size
= WM_ADSP_MAX_FRAGMENT_SIZE
;
3547 caps
->min_fragments
= WM_ADSP_MIN_FRAGMENTS
;
3548 caps
->max_fragments
= WM_ADSP_MAX_FRAGMENTS
;
3553 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps
);
3555 static int wm_adsp_read_data_block(struct wm_adsp
*dsp
, int mem_type
,
3556 unsigned int mem_addr
,
3557 unsigned int num_words
, u32
*data
)
3559 struct wm_adsp_region
const *mem
= wm_adsp_find_region(dsp
, mem_type
);
3560 unsigned int i
, reg
;
3566 reg
= dsp
->ops
->region_to_reg(mem
, mem_addr
);
3568 ret
= regmap_raw_read(dsp
->regmap
, reg
, data
,
3569 sizeof(*data
) * num_words
);
3573 for (i
= 0; i
< num_words
; ++i
)
3574 data
[i
] = be32_to_cpu(data
[i
]) & 0x00ffffffu
;
3579 static inline int wm_adsp_read_data_word(struct wm_adsp
*dsp
, int mem_type
,
3580 unsigned int mem_addr
, u32
*data
)
3582 return wm_adsp_read_data_block(dsp
, mem_type
, mem_addr
, 1, data
);
3585 static int wm_adsp_write_data_word(struct wm_adsp
*dsp
, int mem_type
,
3586 unsigned int mem_addr
, u32 data
)
3588 struct wm_adsp_region
const *mem
= wm_adsp_find_region(dsp
, mem_type
);
3594 reg
= dsp
->ops
->region_to_reg(mem
, mem_addr
);
3596 data
= cpu_to_be32(data
& 0x00ffffffu
);
3598 return regmap_raw_write(dsp
->regmap
, reg
, &data
, sizeof(data
));
3601 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf
*buf
,
3602 unsigned int field_offset
, u32
*data
)
3604 return wm_adsp_read_data_word(buf
->dsp
, buf
->host_buf_mem_type
,
3605 buf
->host_buf_ptr
+ field_offset
, data
);
3608 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf
*buf
,
3609 unsigned int field_offset
, u32 data
)
3611 return wm_adsp_write_data_word(buf
->dsp
, buf
->host_buf_mem_type
,
3612 buf
->host_buf_ptr
+ field_offset
, data
);
3615 static void wm_adsp_remove_padding(u32
*buf
, int nwords
, int data_word_size
)
3617 u8
*pack_in
= (u8
*)buf
;
3618 u8
*pack_out
= (u8
*)buf
;
3621 /* Remove the padding bytes from the data read from the DSP */
3622 for (i
= 0; i
< nwords
; i
++) {
3623 for (j
= 0; j
< data_word_size
; j
++)
3624 *pack_out
++ = *pack_in
++;
3626 pack_in
+= sizeof(*buf
) - data_word_size
;
3630 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf
*buf
)
3632 const struct wm_adsp_fw_caps
*caps
= wm_adsp_fw
[buf
->dsp
->fw
].caps
;
3633 struct wm_adsp_buffer_region
*region
;
3637 buf
->regions
= kcalloc(caps
->num_regions
, sizeof(*buf
->regions
),
3642 for (i
= 0; i
< caps
->num_regions
; ++i
) {
3643 region
= &buf
->regions
[i
];
3645 region
->offset
= offset
;
3646 region
->mem_type
= caps
->region_defs
[i
].mem_type
;
3648 ret
= wm_adsp_buffer_read(buf
, caps
->region_defs
[i
].base_offset
,
3649 ®ion
->base_addr
);
3653 ret
= wm_adsp_buffer_read(buf
, caps
->region_defs
[i
].size_offset
,
3658 region
->cumulative_size
= offset
;
3661 "region=%d type=%d base=%08x off=%08x size=%08x\n",
3662 i
, region
->mem_type
, region
->base_addr
,
3663 region
->offset
, region
->cumulative_size
);
3669 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf
*buf
)
3671 buf
->irq_count
= 0xFFFFFFFF;
3672 buf
->read_index
= -1;
3676 static struct wm_adsp_compr_buf
*wm_adsp_buffer_alloc(struct wm_adsp
*dsp
)
3678 struct wm_adsp_compr_buf
*buf
;
3680 buf
= kzalloc(sizeof(*buf
), GFP_KERNEL
);
3686 wm_adsp_buffer_clear(buf
);
3688 list_add_tail(&buf
->list
, &dsp
->buffer_list
);
3693 static int wm_adsp_buffer_parse_legacy(struct wm_adsp
*dsp
)
3695 struct wm_adsp_alg_region
*alg_region
;
3696 struct wm_adsp_compr_buf
*buf
;
3697 u32 xmalg
, addr
, magic
;
3700 alg_region
= wm_adsp_find_alg_region(dsp
, WMFW_ADSP2_XM
, dsp
->fw_id
);
3702 adsp_err(dsp
, "No algorithm region found\n");
3706 buf
= wm_adsp_buffer_alloc(dsp
);
3710 xmalg
= dsp
->ops
->sys_config_size
/ sizeof(__be32
);
3712 addr
= alg_region
->base
+ xmalg
+ ALG_XM_FIELD(magic
);
3713 ret
= wm_adsp_read_data_word(dsp
, WMFW_ADSP2_XM
, addr
, &magic
);
3717 if (magic
!= WM_ADSP_ALG_XM_STRUCT_MAGIC
)
3720 addr
= alg_region
->base
+ xmalg
+ ALG_XM_FIELD(host_buf_ptr
);
3721 for (i
= 0; i
< 5; ++i
) {
3722 ret
= wm_adsp_read_data_word(dsp
, WMFW_ADSP2_XM
, addr
,
3723 &buf
->host_buf_ptr
);
3727 if (buf
->host_buf_ptr
)
3730 usleep_range(1000, 2000);
3733 if (!buf
->host_buf_ptr
)
3736 buf
->host_buf_mem_type
= WMFW_ADSP2_XM
;
3738 ret
= wm_adsp_buffer_populate(buf
);
3742 compr_dbg(buf
, "legacy host_buf_ptr=%x\n", buf
->host_buf_ptr
);
3747 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl
*ctl
)
3749 struct wm_adsp_host_buf_coeff_v1 coeff_v1
;
3750 struct wm_adsp_compr_buf
*buf
;
3751 unsigned int val
, reg
;
3754 ret
= wm_coeff_base_reg(ctl
, ®
);
3758 for (i
= 0; i
< 5; ++i
) {
3759 ret
= regmap_raw_read(ctl
->dsp
->regmap
, reg
, &val
, sizeof(val
));
3766 usleep_range(1000, 2000);
3770 adsp_err(ctl
->dsp
, "Failed to acquire host buffer\n");
3774 buf
= wm_adsp_buffer_alloc(ctl
->dsp
);
3778 buf
->host_buf_mem_type
= ctl
->alg_region
.type
;
3779 buf
->host_buf_ptr
= be32_to_cpu(val
);
3781 ret
= wm_adsp_buffer_populate(buf
);
3786 * v0 host_buffer coefficients didn't have versioning, so if the
3787 * control is one word, assume version 0.
3789 if (ctl
->len
== 4) {
3790 compr_dbg(buf
, "host_buf_ptr=%x\n", buf
->host_buf_ptr
);
3794 ret
= regmap_raw_read(ctl
->dsp
->regmap
, reg
, &coeff_v1
,
3799 coeff_v1
.versions
= be32_to_cpu(coeff_v1
.versions
);
3800 val
= coeff_v1
.versions
& HOST_BUF_COEFF_COMPAT_VER_MASK
;
3801 val
>>= HOST_BUF_COEFF_COMPAT_VER_SHIFT
;
3803 if (val
> HOST_BUF_COEFF_SUPPORTED_COMPAT_VER
) {
3805 "Host buffer coeff ver %u > supported version %u\n",
3806 val
, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER
);
3810 for (i
= 0; i
< ARRAY_SIZE(coeff_v1
.name
); i
++)
3811 coeff_v1
.name
[i
] = be32_to_cpu(coeff_v1
.name
[i
]);
3813 wm_adsp_remove_padding((u32
*)&coeff_v1
.name
,
3814 ARRAY_SIZE(coeff_v1
.name
),
3815 WM_ADSP_DATA_WORD_SIZE
);
3817 buf
->name
= kasprintf(GFP_KERNEL
, "%s-dsp-%s", ctl
->dsp
->part
,
3818 (char *)&coeff_v1
.name
);
3820 compr_dbg(buf
, "host_buf_ptr=%x coeff version %u\n",
3821 buf
->host_buf_ptr
, val
);
3826 static int wm_adsp_buffer_init(struct wm_adsp
*dsp
)
3828 struct wm_coeff_ctl
*ctl
;
3831 list_for_each_entry(ctl
, &dsp
->ctl_list
, list
) {
3832 if (ctl
->type
!= WMFW_CTL_TYPE_HOST_BUFFER
)
3838 ret
= wm_adsp_buffer_parse_coeff(ctl
);
3840 adsp_err(dsp
, "Failed to parse coeff: %d\n", ret
);
3842 } else if (ret
== 0) {
3843 /* Only one buffer supported for version 0 */
3848 if (list_empty(&dsp
->buffer_list
)) {
3849 /* Fall back to legacy support */
3850 ret
= wm_adsp_buffer_parse_legacy(dsp
);
3852 adsp_err(dsp
, "Failed to parse legacy: %d\n", ret
);
3860 wm_adsp_buffer_free(dsp
);
3864 static int wm_adsp_buffer_free(struct wm_adsp
*dsp
)
3866 struct wm_adsp_compr_buf
*buf
, *tmp
;
3868 list_for_each_entry_safe(buf
, tmp
, &dsp
->buffer_list
, list
) {
3869 wm_adsp_compr_detach(buf
->compr
);
3872 kfree(buf
->regions
);
3873 list_del(&buf
->list
);
3880 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf
*buf
)
3884 ret
= wm_adsp_buffer_read(buf
, HOST_BUFFER_FIELD(error
), &buf
->error
);
3886 compr_err(buf
, "Failed to check buffer error: %d\n", ret
);
3889 if (buf
->error
!= 0) {
3890 compr_err(buf
, "Buffer error occurred: %d\n", buf
->error
);
3897 int wm_adsp_compr_trigger(struct snd_compr_stream
*stream
, int cmd
)
3899 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
3900 struct wm_adsp
*dsp
= compr
->dsp
;
3903 compr_dbg(compr
, "Trigger: %d\n", cmd
);
3905 mutex_lock(&dsp
->pwr_lock
);
3908 case SNDRV_PCM_TRIGGER_START
:
3909 if (!wm_adsp_compr_attached(compr
)) {
3910 ret
= wm_adsp_compr_attach(compr
);
3912 compr_err(compr
, "Failed to link buffer and stream: %d\n",
3918 ret
= wm_adsp_buffer_get_error(compr
->buf
);
3922 /* Trigger the IRQ at one fragment of data */
3923 ret
= wm_adsp_buffer_write(compr
->buf
,
3924 HOST_BUFFER_FIELD(high_water_mark
),
3925 wm_adsp_compr_frag_words(compr
));
3927 compr_err(compr
, "Failed to set high water mark: %d\n",
3932 case SNDRV_PCM_TRIGGER_STOP
:
3933 if (wm_adsp_compr_attached(compr
))
3934 wm_adsp_buffer_clear(compr
->buf
);
3941 mutex_unlock(&dsp
->pwr_lock
);
3945 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger
);
3947 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf
*buf
)
3949 int last_region
= wm_adsp_fw
[buf
->dsp
->fw
].caps
->num_regions
- 1;
3951 return buf
->regions
[last_region
].cumulative_size
;
3954 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf
*buf
)
3956 u32 next_read_index
, next_write_index
;
3957 int write_index
, read_index
, avail
;
3960 /* Only sync read index if we haven't already read a valid index */
3961 if (buf
->read_index
< 0) {
3962 ret
= wm_adsp_buffer_read(buf
,
3963 HOST_BUFFER_FIELD(next_read_index
),
3968 read_index
= sign_extend32(next_read_index
, 23);
3970 if (read_index
< 0) {
3971 compr_dbg(buf
, "Avail check on unstarted stream\n");
3975 buf
->read_index
= read_index
;
3978 ret
= wm_adsp_buffer_read(buf
, HOST_BUFFER_FIELD(next_write_index
),
3983 write_index
= sign_extend32(next_write_index
, 23);
3985 avail
= write_index
- buf
->read_index
;
3987 avail
+= wm_adsp_buffer_size(buf
);
3989 compr_dbg(buf
, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
3990 buf
->read_index
, write_index
, avail
* WM_ADSP_DATA_WORD_SIZE
);
3997 int wm_adsp_compr_handle_irq(struct wm_adsp
*dsp
)
3999 struct wm_adsp_compr_buf
*buf
;
4000 struct wm_adsp_compr
*compr
;
4003 mutex_lock(&dsp
->pwr_lock
);
4005 if (list_empty(&dsp
->buffer_list
)) {
4010 adsp_dbg(dsp
, "Handling buffer IRQ\n");
4012 list_for_each_entry(buf
, &dsp
->buffer_list
, list
) {
4015 ret
= wm_adsp_buffer_get_error(buf
);
4017 goto out_notify
; /* Wake poll to report error */
4019 ret
= wm_adsp_buffer_read(buf
, HOST_BUFFER_FIELD(irq_count
),
4022 compr_err(buf
, "Failed to get irq_count: %d\n", ret
);
4026 ret
= wm_adsp_buffer_update_avail(buf
);
4028 compr_err(buf
, "Error reading avail: %d\n", ret
);
4032 if (wm_adsp_fw
[dsp
->fw
].voice_trigger
&& buf
->irq_count
== 2)
4033 ret
= WM_ADSP_COMPR_VOICE_TRIGGER
;
4036 if (compr
&& compr
->stream
)
4037 snd_compr_fragment_elapsed(compr
->stream
);
4041 mutex_unlock(&dsp
->pwr_lock
);
4045 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq
);
4047 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf
*buf
)
4049 if (buf
->irq_count
& 0x01)
4052 compr_dbg(buf
, "Enable IRQ(0x%x) for next fragment\n", buf
->irq_count
);
4054 buf
->irq_count
|= 0x01;
4056 return wm_adsp_buffer_write(buf
, HOST_BUFFER_FIELD(irq_ack
),
4060 int wm_adsp_compr_pointer(struct snd_compr_stream
*stream
,
4061 struct snd_compr_tstamp
*tstamp
)
4063 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
4064 struct wm_adsp
*dsp
= compr
->dsp
;
4065 struct wm_adsp_compr_buf
*buf
;
4068 compr_dbg(compr
, "Pointer request\n");
4070 mutex_lock(&dsp
->pwr_lock
);
4074 if (dsp
->fatal_error
|| !buf
|| buf
->error
) {
4075 snd_compr_stop_error(stream
, SNDRV_PCM_STATE_XRUN
);
4080 if (buf
->avail
< wm_adsp_compr_frag_words(compr
)) {
4081 ret
= wm_adsp_buffer_update_avail(buf
);
4083 compr_err(compr
, "Error reading avail: %d\n", ret
);
4088 * If we really have less than 1 fragment available tell the
4089 * DSP to inform us once a whole fragment is available.
4091 if (buf
->avail
< wm_adsp_compr_frag_words(compr
)) {
4092 ret
= wm_adsp_buffer_get_error(buf
);
4095 snd_compr_stop_error(stream
,
4096 SNDRV_PCM_STATE_XRUN
);
4100 ret
= wm_adsp_buffer_reenable_irq(buf
);
4102 compr_err(compr
, "Failed to re-enable buffer IRQ: %d\n",
4109 tstamp
->copied_total
= compr
->copied_total
;
4110 tstamp
->copied_total
+= buf
->avail
* WM_ADSP_DATA_WORD_SIZE
;
4111 tstamp
->sampling_rate
= compr
->sample_rate
;
4114 mutex_unlock(&dsp
->pwr_lock
);
4118 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer
);
4120 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr
*compr
, int target
)
4122 struct wm_adsp_compr_buf
*buf
= compr
->buf
;
4123 unsigned int adsp_addr
;
4124 int mem_type
, nwords
, max_read
;
4127 /* Calculate read parameters */
4128 for (i
= 0; i
< wm_adsp_fw
[buf
->dsp
->fw
].caps
->num_regions
; ++i
)
4129 if (buf
->read_index
< buf
->regions
[i
].cumulative_size
)
4132 if (i
== wm_adsp_fw
[buf
->dsp
->fw
].caps
->num_regions
)
4135 mem_type
= buf
->regions
[i
].mem_type
;
4136 adsp_addr
= buf
->regions
[i
].base_addr
+
4137 (buf
->read_index
- buf
->regions
[i
].offset
);
4139 max_read
= wm_adsp_compr_frag_words(compr
);
4140 nwords
= buf
->regions
[i
].cumulative_size
- buf
->read_index
;
4142 if (nwords
> target
)
4144 if (nwords
> buf
->avail
)
4145 nwords
= buf
->avail
;
4146 if (nwords
> max_read
)
4151 /* Read data from DSP */
4152 ret
= wm_adsp_read_data_block(buf
->dsp
, mem_type
, adsp_addr
,
4153 nwords
, compr
->raw_buf
);
4157 wm_adsp_remove_padding(compr
->raw_buf
, nwords
, WM_ADSP_DATA_WORD_SIZE
);
4159 /* update read index to account for words read */
4160 buf
->read_index
+= nwords
;
4161 if (buf
->read_index
== wm_adsp_buffer_size(buf
))
4162 buf
->read_index
= 0;
4164 ret
= wm_adsp_buffer_write(buf
, HOST_BUFFER_FIELD(next_read_index
),
4169 /* update avail to account for words read */
4170 buf
->avail
-= nwords
;
4175 static int wm_adsp_compr_read(struct wm_adsp_compr
*compr
,
4176 char __user
*buf
, size_t count
)
4178 struct wm_adsp
*dsp
= compr
->dsp
;
4182 compr_dbg(compr
, "Requested read of %zu bytes\n", count
);
4184 if (dsp
->fatal_error
|| !compr
->buf
|| compr
->buf
->error
) {
4185 snd_compr_stop_error(compr
->stream
, SNDRV_PCM_STATE_XRUN
);
4189 count
/= WM_ADSP_DATA_WORD_SIZE
;
4192 nwords
= wm_adsp_buffer_capture_block(compr
, count
);
4194 compr_err(compr
, "Failed to capture block: %d\n",
4199 nbytes
= nwords
* WM_ADSP_DATA_WORD_SIZE
;
4201 compr_dbg(compr
, "Read %d bytes\n", nbytes
);
4203 if (copy_to_user(buf
+ ntotal
, compr
->raw_buf
, nbytes
)) {
4204 compr_err(compr
, "Failed to copy data to user: %d, %d\n",
4211 } while (nwords
> 0 && count
> 0);
4213 compr
->copied_total
+= ntotal
;
4218 int wm_adsp_compr_copy(struct snd_compr_stream
*stream
, char __user
*buf
,
4221 struct wm_adsp_compr
*compr
= stream
->runtime
->private_data
;
4222 struct wm_adsp
*dsp
= compr
->dsp
;
4225 mutex_lock(&dsp
->pwr_lock
);
4227 if (stream
->direction
== SND_COMPRESS_CAPTURE
)
4228 ret
= wm_adsp_compr_read(compr
, buf
, count
);
4232 mutex_unlock(&dsp
->pwr_lock
);
4236 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy
);
4238 static void wm_adsp_fatal_error(struct wm_adsp
*dsp
)
4240 struct wm_adsp_compr
*compr
;
4242 dsp
->fatal_error
= true;
4244 list_for_each_entry(compr
, &dsp
->compr_list
, list
) {
4246 snd_compr_fragment_elapsed(compr
->stream
);
4250 irqreturn_t
wm_adsp2_bus_error(int irq
, void *data
)
4252 struct wm_adsp
*dsp
= (struct wm_adsp
*)data
;
4254 struct regmap
*regmap
= dsp
->regmap
;
4257 mutex_lock(&dsp
->pwr_lock
);
4259 ret
= regmap_read(regmap
, dsp
->base
+ ADSP2_LOCK_REGION_CTRL
, &val
);
4262 "Failed to read Region Lock Ctrl register: %d\n", ret
);
4266 if (val
& ADSP2_WDT_TIMEOUT_STS_MASK
) {
4267 adsp_err(dsp
, "watchdog timeout error\n");
4268 dsp
->ops
->stop_watchdog(dsp
);
4269 wm_adsp_fatal_error(dsp
);
4272 if (val
& (ADSP2_SLAVE_ERR_MASK
| ADSP2_REGION_LOCK_ERR_MASK
)) {
4273 if (val
& ADSP2_SLAVE_ERR_MASK
)
4274 adsp_err(dsp
, "bus error: slave error\n");
4276 adsp_err(dsp
, "bus error: region lock error\n");
4278 ret
= regmap_read(regmap
, dsp
->base
+ ADSP2_BUS_ERR_ADDR
, &val
);
4281 "Failed to read Bus Err Addr register: %d\n",
4286 adsp_err(dsp
, "bus error address = 0x%x\n",
4287 val
& ADSP2_BUS_ERR_ADDR_MASK
);
4289 ret
= regmap_read(regmap
,
4290 dsp
->base
+ ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR
,
4294 "Failed to read Pmem Xmem Err Addr register: %d\n",
4299 adsp_err(dsp
, "xmem error address = 0x%x\n",
4300 val
& ADSP2_XMEM_ERR_ADDR_MASK
);
4301 adsp_err(dsp
, "pmem error address = 0x%x\n",
4302 (val
& ADSP2_PMEM_ERR_ADDR_MASK
) >>
4303 ADSP2_PMEM_ERR_ADDR_SHIFT
);
4306 regmap_update_bits(regmap
, dsp
->base
+ ADSP2_LOCK_REGION_CTRL
,
4307 ADSP2_CTRL_ERR_EINT
, ADSP2_CTRL_ERR_EINT
);
4310 mutex_unlock(&dsp
->pwr_lock
);
4314 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error
);
4316 irqreturn_t
wm_halo_bus_error(int irq
, void *data
)
4318 struct wm_adsp
*dsp
= (struct wm_adsp
*)data
;
4319 struct regmap
*regmap
= dsp
->regmap
;
4320 unsigned int fault
[6];
4321 struct reg_sequence clear
[] = {
4322 { dsp
->base
+ HALO_MPU_XM_VIO_STATUS
, 0x0 },
4323 { dsp
->base
+ HALO_MPU_YM_VIO_STATUS
, 0x0 },
4324 { dsp
->base
+ HALO_MPU_PM_VIO_STATUS
, 0x0 },
4328 mutex_lock(&dsp
->pwr_lock
);
4330 ret
= regmap_read(regmap
, dsp
->base_sysinfo
+ HALO_AHBM_WINDOW_DEBUG_1
,
4333 adsp_warn(dsp
, "Failed to read AHB DEBUG_1: %d\n", ret
);
4337 adsp_warn(dsp
, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
4338 *fault
& HALO_AHBM_FLAGS_ERR_MASK
,
4339 (*fault
& HALO_AHBM_CORE_ERR_ADDR_MASK
) >>
4340 HALO_AHBM_CORE_ERR_ADDR_SHIFT
);
4342 ret
= regmap_read(regmap
, dsp
->base_sysinfo
+ HALO_AHBM_WINDOW_DEBUG_0
,
4345 adsp_warn(dsp
, "Failed to read AHB DEBUG_0: %d\n", ret
);
4349 adsp_warn(dsp
, "AHB: SYS_ADDR: 0x%x\n", *fault
);
4351 ret
= regmap_bulk_read(regmap
, dsp
->base
+ HALO_MPU_XM_VIO_ADDR
,
4352 fault
, ARRAY_SIZE(fault
));
4354 adsp_warn(dsp
, "Failed to read MPU fault info: %d\n", ret
);
4358 adsp_warn(dsp
, "XM: STATUS:0x%x ADDR:0x%x\n", fault
[1], fault
[0]);
4359 adsp_warn(dsp
, "YM: STATUS:0x%x ADDR:0x%x\n", fault
[3], fault
[2]);
4360 adsp_warn(dsp
, "PM: STATUS:0x%x ADDR:0x%x\n", fault
[5], fault
[4]);
4362 ret
= regmap_multi_reg_write(dsp
->regmap
, clear
, ARRAY_SIZE(clear
));
4364 adsp_warn(dsp
, "Failed to clear MPU status: %d\n", ret
);
4367 mutex_unlock(&dsp
->pwr_lock
);
4371 EXPORT_SYMBOL_GPL(wm_halo_bus_error
);
4373 irqreturn_t
wm_halo_wdt_expire(int irq
, void *data
)
4375 struct wm_adsp
*dsp
= data
;
4377 mutex_lock(&dsp
->pwr_lock
);
4379 adsp_warn(dsp
, "WDT Expiry Fault\n");
4380 dsp
->ops
->stop_watchdog(dsp
);
4381 wm_adsp_fatal_error(dsp
);
4383 mutex_unlock(&dsp
->pwr_lock
);
4387 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire
);
4389 static struct wm_adsp_ops wm_adsp1_ops
= {
4390 .validate_version
= wm_adsp_validate_version
,
4391 .parse_sizes
= wm_adsp1_parse_sizes
,
4392 .region_to_reg
= wm_adsp_region_to_reg
,
4395 static struct wm_adsp_ops wm_adsp2_ops
[] = {
4397 .sys_config_size
= sizeof(struct wm_adsp_system_config_xm_hdr
),
4398 .parse_sizes
= wm_adsp2_parse_sizes
,
4399 .validate_version
= wm_adsp_validate_version
,
4400 .setup_algs
= wm_adsp2_setup_algs
,
4401 .region_to_reg
= wm_adsp_region_to_reg
,
4403 .show_fw_status
= wm_adsp2_show_fw_status
,
4405 .enable_memory
= wm_adsp2_enable_memory
,
4406 .disable_memory
= wm_adsp2_disable_memory
,
4408 .enable_core
= wm_adsp2_enable_core
,
4409 .disable_core
= wm_adsp2_disable_core
,
4411 .start_core
= wm_adsp2_start_core
,
4412 .stop_core
= wm_adsp2_stop_core
,
4416 .sys_config_size
= sizeof(struct wm_adsp_system_config_xm_hdr
),
4417 .parse_sizes
= wm_adsp2_parse_sizes
,
4418 .validate_version
= wm_adsp_validate_version
,
4419 .setup_algs
= wm_adsp2_setup_algs
,
4420 .region_to_reg
= wm_adsp_region_to_reg
,
4422 .show_fw_status
= wm_adsp2v2_show_fw_status
,
4424 .enable_memory
= wm_adsp2_enable_memory
,
4425 .disable_memory
= wm_adsp2_disable_memory
,
4426 .lock_memory
= wm_adsp2_lock
,
4428 .enable_core
= wm_adsp2v2_enable_core
,
4429 .disable_core
= wm_adsp2v2_disable_core
,
4431 .start_core
= wm_adsp2_start_core
,
4432 .stop_core
= wm_adsp2_stop_core
,
4435 .sys_config_size
= sizeof(struct wm_adsp_system_config_xm_hdr
),
4436 .parse_sizes
= wm_adsp2_parse_sizes
,
4437 .validate_version
= wm_adsp_validate_version
,
4438 .setup_algs
= wm_adsp2_setup_algs
,
4439 .region_to_reg
= wm_adsp_region_to_reg
,
4441 .show_fw_status
= wm_adsp2v2_show_fw_status
,
4442 .stop_watchdog
= wm_adsp_stop_watchdog
,
4444 .enable_memory
= wm_adsp2_enable_memory
,
4445 .disable_memory
= wm_adsp2_disable_memory
,
4446 .lock_memory
= wm_adsp2_lock
,
4448 .enable_core
= wm_adsp2v2_enable_core
,
4449 .disable_core
= wm_adsp2v2_disable_core
,
4451 .start_core
= wm_adsp2_start_core
,
4452 .stop_core
= wm_adsp2_stop_core
,
4456 static struct wm_adsp_ops wm_halo_ops
= {
4457 .sys_config_size
= sizeof(struct wm_halo_system_config_xm_hdr
),
4458 .parse_sizes
= wm_adsp2_parse_sizes
,
4459 .validate_version
= wm_halo_validate_version
,
4460 .setup_algs
= wm_halo_setup_algs
,
4461 .region_to_reg
= wm_halo_region_to_reg
,
4463 .show_fw_status
= wm_halo_show_fw_status
,
4464 .stop_watchdog
= wm_halo_stop_watchdog
,
4466 .lock_memory
= wm_halo_configure_mpu
,
4468 .start_core
= wm_halo_start_core
,
4469 .stop_core
= wm_halo_stop_core
,
4472 MODULE_LICENSE("GPL v2");