sound/soc/davinci/davinci-i2s.c

   1 /*
   2  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24
  25 #include "davinci-pcm.h"
  26
  27
  28 /*
  29  * NOTE:  terminology here is confusing.
  30  *
  31  *  - This driver supports the "Audio Serial Port" (ASP),
  32  *    found on dm6446, dm355, and other DaVinci chips.
  33  *
  34  *  - But it labels it a "Multi-channel Buffered Serial Port"
  35  *    (McBSP) as on older chips like the dm642 ... which was
  36  *    backward-compatible, possibly explaining that confusion.
  37  *
  38  *  - OMAP chips have a controller called McBSP, which is
  39  *    incompatible with the DaVinci flavor of McBSP.
  40  *
  41  *  - Newer DaVinci chips have a controller called McASP,
  42  *    incompatible with ASP and with either McBSP.
  43  *
  44  * In short:  this uses ASP to implement I2S, not McBSP.
  45  * And it won't be the only DaVinci implemention of I2S.
  46  */
  47 #define DAVINCI_MCBSP_DRR_REG   0x00
  48 #define DAVINCI_MCBSP_DXR_REG   0x04
  49 #define DAVINCI_MCBSP_SPCR_REG  0x08
  50 #define DAVINCI_MCBSP_RCR_REG   0x0c
  51 #define DAVINCI_MCBSP_XCR_REG   0x10
  52 #define DAVINCI_MCBSP_SRGR_REG  0x14
  53 #define DAVINCI_MCBSP_PCR_REG   0x24
  54
  55 #define DAVINCI_MCBSP_SPCR_RRST         (1 << 0)
  56 #define DAVINCI_MCBSP_SPCR_RINTM(v)     ((v) << 4)
  57 #define DAVINCI_MCBSP_SPCR_XRST         (1 << 16)
  58 #define DAVINCI_MCBSP_SPCR_XINTM(v)     ((v) << 20)
  59 #define DAVINCI_MCBSP_SPCR_GRST         (1 << 22)
  60 #define DAVINCI_MCBSP_SPCR_FRST         (1 << 23)
  61 #define DAVINCI_MCBSP_SPCR_FREE         (1 << 25)
  62
  63 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)    ((v) << 5)
  64 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)    ((v) << 8)
  65 #define DAVINCI_MCBSP_RCR_RDATDLY(v)    ((v) << 16)
  66 #define DAVINCI_MCBSP_RCR_RFIG          (1 << 18)
  67 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)    ((v) << 21)
  68
  69 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)    ((v) << 5)
  70 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)    ((v) << 8)
  71 #define DAVINCI_MCBSP_XCR_XDATDLY(v)    ((v) << 16)
  72 #define DAVINCI_MCBSP_XCR_XFIG          (1 << 18)
  73 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)    ((v) << 21)
  74
  75 #define DAVINCI_MCBSP_SRGR_FWID(v)      ((v) << 8)
  76 #define DAVINCI_MCBSP_SRGR_FPER(v)      ((v) << 16)
  77 #define DAVINCI_MCBSP_SRGR_FSGM         (1 << 28)
  78
  79 #define DAVINCI_MCBSP_PCR_CLKRP         (1 << 0)
  80 #define DAVINCI_MCBSP_PCR_CLKXP         (1 << 1)
  81 #define DAVINCI_MCBSP_PCR_FSRP          (1 << 2)
  82 #define DAVINCI_MCBSP_PCR_FSXP          (1 << 3)
  83 #define DAVINCI_MCBSP_PCR_SCLKME        (1 << 7)
  84 #define DAVINCI_MCBSP_PCR_CLKRM         (1 << 8)
  85 #define DAVINCI_MCBSP_PCR_CLKXM         (1 << 9)
  86 #define DAVINCI_MCBSP_PCR_FSRM          (1 << 10)
  87 #define DAVINCI_MCBSP_PCR_FSXM          (1 << 11)
  88
  89 enum {
  90         DAVINCI_MCBSP_WORD_8 = 0,
  91         DAVINCI_MCBSP_WORD_12,
  92         DAVINCI_MCBSP_WORD_16,
  93         DAVINCI_MCBSP_WORD_20,
  94         DAVINCI_MCBSP_WORD_24,
  95         DAVINCI_MCBSP_WORD_32,
  96 };
  97
  98 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
  99         .name = "I2S PCM Stereo out",
 100 };
 101
 102 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
 103         .name = "I2S PCM Stereo in",
 104 };
 105
 106 struct davinci_mcbsp_dev {
 107         void __iomem                    *base;
 108 #define MOD_DSP_A       0
 109 #define MOD_DSP_B       1
 110         int                             mode;
 111         u32                             pcr;
 112         struct clk                      *clk;
 113         struct davinci_pcm_dma_params   *dma_params[2];
 114 };
 115
 116 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
 117                                            int reg, u32 val)
 118 {
 119         __raw_writel(val, dev->base + reg);
 120 }
 121
 122 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
 123 {
 124         return __raw_readl(dev->base + reg);
 125 }
 126
 127 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
 128 {
 129         u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
 130         /* The clock needs to toggle to complete reset.
 131          * So, fake it by toggling the clk polarity.
 132          */
 133         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
 134         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
 135 }
 136
 137 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
 138                 struct snd_pcm_substream *substream)
 139 {
 140         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 141         struct snd_soc_device *socdev = rtd->socdev;
 142         struct snd_soc_platform *platform = socdev->card->platform;
 143         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 144         u32 spcr;
 145         u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
 146         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 147         if (spcr & mask) {
 148                 /* start off disabled */
 149                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
 150                                 spcr & ~mask);
 151                 toggle_clock(dev, playback);
 152         }
 153         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
 154                         DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
 155                 /* Start the sample generator */
 156                 spcr |= DAVINCI_MCBSP_SPCR_GRST;
 157                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 158         }
 159
 160         if (playback) {
 161                 /* Stop the DMA to avoid data loss */
 162                 /* while the transmitter is out of reset to handle XSYNCERR */
 163                 if (platform->pcm_ops->trigger) {
 164                         int ret = platform->pcm_ops->trigger(substream,
 165                                 SNDRV_PCM_TRIGGER_STOP);
 166                         if (ret < 0)
 167                                 printk(KERN_DEBUG "Playback DMA stop failed\n");
 168                 }
 169
 170                 /* Enable the transmitter */
 171                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 172                 spcr |= DAVINCI_MCBSP_SPCR_XRST;
 173                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 174
 175                 /* wait for any unexpected frame sync error to occur */
 176                 udelay(100);
 177
 178                 /* Disable the transmitter to clear any outstanding XSYNCERR */
 179                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 180                 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
 181                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 182                 toggle_clock(dev, playback);
 183
 184                 /* Restart the DMA */
 185                 if (platform->pcm_ops->trigger) {
 186                         int ret = platform->pcm_ops->trigger(substream,
 187                                 SNDRV_PCM_TRIGGER_START);
 188                         if (ret < 0)
 189                                 printk(KERN_DEBUG "Playback DMA start failed\n");
 190                 }
 191         }
 192
 193         /* Enable transmitter or receiver */
 194         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 195         spcr |= mask;
 196
 197         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
 198                 /* Start frame sync */
 199                 spcr |= DAVINCI_MCBSP_SPCR_FRST;
 200         }
 201         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 202 }
 203
 204 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
 205 {
 206         u32 spcr;
 207
 208         /* Reset transmitter/receiver and sample rate/frame sync generators */
 209         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 210         spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
 211         spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
 212         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 213         toggle_clock(dev, playback);
 214 }
 215
 216 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
 217                                struct snd_soc_dai *cpu_dai)
 218 {
 219         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 220         cpu_dai->dma_data = dev->dma_params[substream->stream];
 221         return 0;
 222 }
 223
 224 #define DEFAULT_BITPERSAMPLE    16
 225
 226 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 227                                    unsigned int fmt)
 228 {
 229         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 230         unsigned int pcr;
 231         unsigned int srgr;
 232         srgr = DAVINCI_MCBSP_SRGR_FSGM |
 233                 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
 234                 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 235
 236         /* set master/slave audio interface */
 237         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 238         case SND_SOC_DAIFMT_CBS_CFS:
 239                 /* cpu is master */
 240                 pcr = DAVINCI_MCBSP_PCR_FSXM |
 241                         DAVINCI_MCBSP_PCR_FSRM |
 242                         DAVINCI_MCBSP_PCR_CLKXM |
 243                         DAVINCI_MCBSP_PCR_CLKRM;
 244                 break;
 245         case SND_SOC_DAIFMT_CBM_CFS:
 246                 /* McBSP CLKR pin is the input for the Sample Rate Generator.
 247                  * McBSP FSR and FSX are driven by the Sample Rate Generator. */
 248                 pcr = DAVINCI_MCBSP_PCR_SCLKME |
 249                         DAVINCI_MCBSP_PCR_FSXM |
 250                         DAVINCI_MCBSP_PCR_FSRM;
 251                 break;
 252         case SND_SOC_DAIFMT_CBM_CFM:
 253                 /* codec is master */
 254                 pcr = 0;
 255                 break;
 256         default:
 257                 printk(KERN_ERR "%s:bad master\n", __func__);
 258                 return -EINVAL;
 259         }
 260
 261         /* interface format */
 262         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 263         case SND_SOC_DAIFMT_I2S:
 264                 /* Davinci doesn't support TRUE I2S, but some codecs will have
 265                  * the left and right channels contiguous. This allows
 266                  * dsp_a mode to be used with an inverted normal frame clk.
 267                  * If your codec is master and does not have contiguous
 268                  * channels, then you will have sound on only one channel.
 269                  * Try using a different mode, or codec as slave.
 270                  *
 271                  * The TLV320AIC33 is an example of a codec where this works.
 272                  * It has a variable bit clock frequency allowing it to have
 273                  * valid data on every bit clock.
 274                  *
 275                  * The TLV320AIC23 is an example of a codec where this does not
 276                  * work. It has a fixed bit clock frequency with progressively
 277                  * more empty bit clock slots between channels as the sample
 278                  * rate is lowered.
 279                  */
 280                 fmt ^= SND_SOC_DAIFMT_NB_IF;
 281         case SND_SOC_DAIFMT_DSP_A:
 282                 dev->mode = MOD_DSP_A;
 283                 break;
 284         case SND_SOC_DAIFMT_DSP_B:
 285                 dev->mode = MOD_DSP_B;
 286                 break;
 287         default:
 288                 printk(KERN_ERR "%s:bad format\n", __func__);
 289                 return -EINVAL;
 290         }
 291
 292         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 293         case SND_SOC_DAIFMT_NB_NF:
 294                 /* CLKRP Receive clock polarity,
 295                  *      1 - sampled on rising edge of CLKR
 296                  *      valid on rising edge
 297                  * CLKXP Transmit clock polarity,
 298                  *      1 - clocked on falling edge of CLKX
 299                  *      valid on rising edge
 300                  * FSRP  Receive frame sync pol, 0 - active high
 301                  * FSXP  Transmit frame sync pol, 0 - active high
 302                  */
 303                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
 304                 break;
 305         case SND_SOC_DAIFMT_IB_IF:
 306                 /* CLKRP Receive clock polarity,
 307                  *      0 - sampled on falling edge of CLKR
 308                  *      valid on falling edge
 309                  * CLKXP Transmit clock polarity,
 310                  *      0 - clocked on rising edge of CLKX
 311                  *      valid on falling edge
 312                  * FSRP  Receive frame sync pol, 1 - active low
 313                  * FSXP  Transmit frame sync pol, 1 - active low
 314                  */
 315                 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 316                 break;
 317         case SND_SOC_DAIFMT_NB_IF:
 318                 /* CLKRP Receive clock polarity,
 319                  *      1 - sampled on rising edge of CLKR
 320                  *      valid on rising edge
 321                  * CLKXP Transmit clock polarity,
 322                  *      1 - clocked on falling edge of CLKX
 323                  *      valid on rising edge
 324                  * FSRP  Receive frame sync pol, 1 - active low
 325                  * FSXP  Transmit frame sync pol, 1 - active low
 326                  */
 327                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
 328                         DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 329                 break;
 330         case SND_SOC_DAIFMT_IB_NF:
 331                 /* CLKRP Receive clock polarity,
 332                  *      0 - sampled on falling edge of CLKR
 333                  *      valid on falling edge
 334                  * CLKXP Transmit clock polarity,
 335                  *      0 - clocked on rising edge of CLKX
 336                  *      valid on falling edge
 337                  * FSRP  Receive frame sync pol, 0 - active high
 338                  * FSXP  Transmit frame sync pol, 0 - active high
 339                  */
 340                 break;
 341         default:
 342                 return -EINVAL;
 343         }
 344         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 345         dev->pcr = pcr;
 346         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
 347         return 0;
 348 }
 349
 350 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 351                                  struct snd_pcm_hw_params *params,
 352                                  struct snd_soc_dai *dai)
 353 {
 354         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 355         struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
 356         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 357         struct snd_interval *i = NULL;
 358         int mcbsp_word_length;
 359         unsigned int rcr, xcr, srgr;
 360         u32 spcr;
 361
 362         /* general line settings */
 363         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 364         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 365                 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 366                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 367         } else {
 368                 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 369                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 370         }
 371
 372         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
 373         srgr = DAVINCI_MCBSP_SRGR_FSGM;
 374         srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
 375
 376         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
 377         srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
 378         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 379
 380         rcr = DAVINCI_MCBSP_RCR_RFIG;
 381         xcr = DAVINCI_MCBSP_XCR_XFIG;
 382         if (dev->mode == MOD_DSP_B) {
 383                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
 384                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
 385         } else {
 386                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
 387                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
 388         }
 389         /* Determine xfer data type */
 390         switch (params_format(params)) {
 391         case SNDRV_PCM_FORMAT_S8:
 392                 dma_params->data_type = 1;
 393                 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
 394                 break;
 395         case SNDRV_PCM_FORMAT_S16_LE:
 396                 dma_params->data_type = 2;
 397                 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
 398                 break;
 399         case SNDRV_PCM_FORMAT_S32_LE:
 400                 dma_params->data_type = 4;
 401                 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
 402                 break;
 403         default:
 404                 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
 405                 return -EINVAL;
 406         }
 407
 408         rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1);
 409         xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1);
 410
 411         rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 412                 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
 413         xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
 414                 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
 415
 416         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 417                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 418         else
 419                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 420         return 0;
 421 }
 422
 423 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 424                                struct snd_soc_dai *dai)
 425 {
 426         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 427         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 428         int ret = 0;
 429         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 430
 431         switch (cmd) {
 432         case SNDRV_PCM_TRIGGER_START:
 433         case SNDRV_PCM_TRIGGER_RESUME:
 434         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 435                 davinci_mcbsp_start(dev, substream);
 436                 break;
 437         case SNDRV_PCM_TRIGGER_STOP:
 438         case SNDRV_PCM_TRIGGER_SUSPEND:
 439         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 440                 davinci_mcbsp_stop(dev, playback);
 441                 break;
 442         default:
 443                 ret = -EINVAL;
 444         }
 445
 446         return ret;
 447 }
 448
 449 static int davinci_i2s_probe(struct platform_device *pdev,
 450                              struct snd_soc_dai *dai)
 451 {
 452         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 453         struct snd_soc_card *card = socdev->card;
 454         struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
 455         struct davinci_mcbsp_dev *dev;
 456         struct resource *mem, *ioarea;
 457         struct evm_snd_platform_data *pdata;
 458         int ret;
 459
 460         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 461         if (!mem) {
 462                 dev_err(&pdev->dev, "no mem resource?\n");
 463                 return -ENODEV;
 464         }
 465
 466         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 467                                     pdev->name);
 468         if (!ioarea) {
 469                 dev_err(&pdev->dev, "McBSP region already claimed\n");
 470                 return -EBUSY;
 471         }
 472
 473         dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
 474         if (!dev) {
 475                 ret = -ENOMEM;
 476                 goto err_release_region;
 477         }
 478
 479         cpu_dai->private_data = dev;
 480
 481         dev->clk = clk_get(&pdev->dev, NULL);
 482         if (IS_ERR(dev->clk)) {
 483                 ret = -ENODEV;
 484                 goto err_free_mem;
 485         }
 486         clk_enable(dev->clk);
 487
 488         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 489         pdata = pdev->dev.platform_data;
 490
 491         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
 492         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
 493         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
 494             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
 495
 496         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
 497         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
 498         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
 499             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
 500
 501         return 0;
 502
 503 err_free_mem:
 504         kfree(dev);
 505 err_release_region:
 506         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 507
 508         return ret;
 509 }
 510
 511 static void davinci_i2s_remove(struct platform_device *pdev,
 512                                struct snd_soc_dai *dai)
 513 {
 514         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 515         struct snd_soc_card *card = socdev->card;
 516         struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
 517         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 518         struct resource *mem;
 519
 520         clk_disable(dev->clk);
 521         clk_put(dev->clk);
 522         dev->clk = NULL;
 523
 524         kfree(dev);
 525
 526         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 527         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 528 }
 529
 530 #define DAVINCI_I2S_RATES       SNDRV_PCM_RATE_8000_96000
 531
 532 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 533         .startup        = davinci_i2s_startup,
 534         .trigger        = davinci_i2s_trigger,
 535         .hw_params      = davinci_i2s_hw_params,
 536         .set_fmt        = davinci_i2s_set_dai_fmt,
 537 };
 538
 539 struct snd_soc_dai davinci_i2s_dai = {
 540         .name = "davinci-i2s",
 541         .id = 0,
 542         .probe = davinci_i2s_probe,
 543         .remove = davinci_i2s_remove,
 544         .playback = {
 545                 .channels_min = 2,
 546                 .channels_max = 2,
 547                 .rates = DAVINCI_I2S_RATES,
 548                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 549         .capture = {
 550                 .channels_min = 2,
 551                 .channels_max = 2,
 552                 .rates = DAVINCI_I2S_RATES,
 553                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 554         .ops = &davinci_i2s_dai_ops,
 555 };
 556 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
 557
 558 static int __init davinci_i2s_init(void)
 559 {
 560         return snd_soc_register_dai(&davinci_i2s_dai);
 561 }
 562 module_init(davinci_i2s_init);
 563
 564 static void __exit davinci_i2s_exit(void)
 565 {
 566         snd_soc_unregister_dai(&davinci_i2s_dai);
 567 }
 568 module_exit(davinci_i2s_exit);
 569
 570 MODULE_AUTHOR("Vladimir Barinov");
 571 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
 572 MODULE_LICENSE("GPL");