2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/initval.h>
34 #include <sound/soc.h>
35 #include <sound/dmaengine_pcm.h>
37 #include "davinci-pcm.h"
38 #include "davinci-mcasp.h"
40 struct davinci_mcasp_context
{
50 struct davinci_mcasp
{
51 struct davinci_pcm_dma_params dma_params
[2];
52 struct snd_dmaengine_dai_dma_data dma_data
[2];
57 /* McASP specific data */
69 /* McASP FIFO related */
75 #ifdef CONFIG_PM_SLEEP
76 struct davinci_mcasp_context context
;
80 static inline void mcasp_set_bits(struct davinci_mcasp
*mcasp
, u32 offset
,
83 void __iomem
*reg
= mcasp
->base
+ offset
;
84 __raw_writel(__raw_readl(reg
) | val
, reg
);
87 static inline void mcasp_clr_bits(struct davinci_mcasp
*mcasp
, u32 offset
,
90 void __iomem
*reg
= mcasp
->base
+ offset
;
91 __raw_writel((__raw_readl(reg
) & ~(val
)), reg
);
94 static inline void mcasp_mod_bits(struct davinci_mcasp
*mcasp
, u32 offset
,
97 void __iomem
*reg
= mcasp
->base
+ offset
;
98 __raw_writel((__raw_readl(reg
) & ~mask
) | val
, reg
);
101 static inline void mcasp_set_reg(struct davinci_mcasp
*mcasp
, u32 offset
,
104 __raw_writel(val
, mcasp
->base
+ offset
);
107 static inline u32
mcasp_get_reg(struct davinci_mcasp
*mcasp
, u32 offset
)
109 return (u32
)__raw_readl(mcasp
->base
+ offset
);
112 static void mcasp_set_ctl_reg(struct davinci_mcasp
*mcasp
, u32 ctl_reg
, u32 val
)
116 mcasp_set_bits(mcasp
, ctl_reg
, val
);
118 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
119 /* loop count is to avoid the lock-up */
120 for (i
= 0; i
< 1000; i
++) {
121 if ((mcasp_get_reg(mcasp
, ctl_reg
) & val
) == val
)
125 if (i
== 1000 && ((mcasp_get_reg(mcasp
, ctl_reg
) & val
) != val
))
126 printk(KERN_ERR
"GBLCTL write error\n");
129 static bool mcasp_is_synchronous(struct davinci_mcasp
*mcasp
)
131 u32 rxfmctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
);
132 u32 aclkxctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
);
134 return !(aclkxctl
& TX_ASYNC
) && rxfmctl
& AFSRE
;
137 static void mcasp_start_rx(struct davinci_mcasp
*mcasp
)
139 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXHCLKRST
);
140 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXCLKRST
);
143 * When ASYNC == 0 the transmit and receive sections operate
144 * synchronously from the transmit clock and frame sync. We need to make
145 * sure that the TX signlas are enabled when starting reception.
147 if (mcasp_is_synchronous(mcasp
)) {
148 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXHCLKRST
);
149 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXCLKRST
);
152 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXSERCLR
);
153 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXBUF_REG
, 0);
155 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXSMRST
);
156 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXFSRST
);
157 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXBUF_REG
, 0);
159 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXSMRST
);
160 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, RXFSRST
);
162 if (mcasp_is_synchronous(mcasp
))
163 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXFSRST
);
166 static void mcasp_start_tx(struct davinci_mcasp
*mcasp
)
171 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXHCLKRST
);
172 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXCLKRST
);
173 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXSERCLR
);
174 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXBUF_REG
, 0);
176 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXSMRST
);
177 mcasp_set_ctl_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, TXFSRST
);
178 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXBUF_REG
, 0);
179 for (i
= 0; i
< mcasp
->num_serializer
; i
++) {
180 if (mcasp
->serial_dir
[i
] == TX_MODE
) {
186 /* wait for TX ready */
188 while (!(mcasp_get_reg(mcasp
, DAVINCI_MCASP_XRSRCTL_REG(offset
)) &
189 TXSTATE
) && (cnt
< 100000))
192 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXBUF_REG
, 0);
195 static void davinci_mcasp_start(struct davinci_mcasp
*mcasp
, int stream
)
201 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
202 if (mcasp
->txnumevt
) { /* enable FIFO */
203 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
204 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
205 mcasp_set_bits(mcasp
, reg
, FIFO_ENABLE
);
207 mcasp_start_tx(mcasp
);
209 if (mcasp
->rxnumevt
) { /* enable FIFO */
210 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
211 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
212 mcasp_set_bits(mcasp
, reg
, FIFO_ENABLE
);
214 mcasp_start_rx(mcasp
);
218 static void mcasp_stop_rx(struct davinci_mcasp
*mcasp
)
221 * In synchronous mode stop the TX clocks if no other stream is
224 if (mcasp_is_synchronous(mcasp
) && !mcasp
->streams
)
225 mcasp_set_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, 0);
227 mcasp_set_reg(mcasp
, DAVINCI_MCASP_GBLCTLR_REG
, 0);
228 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXSTAT_REG
, 0xFFFFFFFF);
231 static void mcasp_stop_tx(struct davinci_mcasp
*mcasp
)
236 * In synchronous mode keep TX clocks running if the capture stream is
239 if (mcasp_is_synchronous(mcasp
) && mcasp
->streams
)
240 val
= TXHCLKRST
| TXCLKRST
| TXFSRST
;
242 mcasp_set_reg(mcasp
, DAVINCI_MCASP_GBLCTLX_REG
, val
);
243 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
, 0xFFFFFFFF);
246 static void davinci_mcasp_stop(struct davinci_mcasp
*mcasp
, int stream
)
252 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
253 if (mcasp
->txnumevt
) { /* disable FIFO */
254 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
255 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
257 mcasp_stop_tx(mcasp
);
259 if (mcasp
->rxnumevt
) { /* disable FIFO */
260 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
261 mcasp_clr_bits(mcasp
, reg
, FIFO_ENABLE
);
263 mcasp_stop_rx(mcasp
);
267 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
270 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
273 pm_runtime_get_sync(mcasp
->dev
);
274 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
275 case SND_SOC_DAIFMT_DSP_B
:
276 case SND_SOC_DAIFMT_AC97
:
277 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXDUR
);
278 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRDUR
);
281 /* configure a full-word SYNC pulse (LRCLK) */
282 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXDUR
);
283 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRDUR
);
285 /* make 1st data bit occur one ACLK cycle after the frame sync */
286 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, FSXDLY(1));
287 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, FSRDLY(1));
291 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
292 case SND_SOC_DAIFMT_CBS_CFS
:
293 /* codec is clock and frame slave */
294 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
295 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
297 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
298 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
300 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, ACLKX
| ACLKR
);
301 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AFSX
| AFSR
);
302 mcasp
->bclk_master
= 1;
304 case SND_SOC_DAIFMT_CBM_CFS
:
305 /* codec is clock master and frame slave */
306 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
307 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
309 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
310 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
312 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, ACLKX
| ACLKR
);
313 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AFSX
| AFSR
);
314 mcasp
->bclk_master
= 0;
316 case SND_SOC_DAIFMT_CBM_CFM
:
317 /* codec is clock and frame master */
318 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
);
319 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
);
321 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRE
);
322 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, AFSRE
);
324 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
,
325 ACLKX
| AHCLKX
| AFSX
| ACLKR
| AHCLKR
| AFSR
);
326 mcasp
->bclk_master
= 0;
334 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
335 case SND_SOC_DAIFMT_IB_NF
:
336 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
337 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXPOL
);
339 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
340 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRPOL
);
343 case SND_SOC_DAIFMT_NB_IF
:
344 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
345 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXPOL
);
347 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
348 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRPOL
);
351 case SND_SOC_DAIFMT_IB_IF
:
352 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
353 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXPOL
);
355 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
356 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRPOL
);
359 case SND_SOC_DAIFMT_NB_NF
:
360 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXPOL
);
361 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, FSXPOL
);
363 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, ACLKRPOL
);
364 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, FSRPOL
);
372 pm_runtime_put_sync(mcasp
->dev
);
376 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai
*dai
, int div_id
, int div
)
378 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
381 case 0: /* MCLK divider */
382 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
,
383 AHCLKXDIV(div
- 1), AHCLKXDIV_MASK
);
384 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_AHCLKRCTL_REG
,
385 AHCLKRDIV(div
- 1), AHCLKRDIV_MASK
);
388 case 1: /* BCLK divider */
389 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
,
390 ACLKXDIV(div
- 1), ACLKXDIV_MASK
);
391 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
,
392 ACLKRDIV(div
- 1), ACLKRDIV_MASK
);
395 case 2: /* BCLK/LRCLK ratio */
396 mcasp
->bclk_lrclk_ratio
= div
;
406 static int davinci_mcasp_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
407 unsigned int freq
, int dir
)
409 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
411 if (dir
== SND_SOC_CLOCK_OUT
) {
412 mcasp_set_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
, AHCLKXE
);
413 mcasp_set_bits(mcasp
, DAVINCI_MCASP_AHCLKRCTL_REG
, AHCLKRE
);
414 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AHCLKX
);
416 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
, AHCLKXE
);
417 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_AHCLKRCTL_REG
, AHCLKRE
);
418 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AHCLKX
);
421 mcasp
->sysclk_freq
= freq
;
426 static int davinci_config_channel_size(struct davinci_mcasp
*mcasp
,
430 u32 tx_rotate
= (word_length
/ 4) & 0x7;
431 u32 rx_rotate
= (32 - word_length
) / 4;
432 u32 mask
= (1ULL << word_length
) - 1;
435 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
436 * callback, take it into account here. That allows us to for example
437 * send 32 bits per channel to the codec, while only 16 of them carry
439 * The clock ratio is given for a full period of data (for I2S format
440 * both left and right channels), so it has to be divided by number of
441 * tdm-slots (for I2S - divided by 2).
443 if (mcasp
->bclk_lrclk_ratio
)
444 word_length
= mcasp
->bclk_lrclk_ratio
/ mcasp
->tdm_slots
;
446 /* mapping of the XSSZ bit-field as described in the datasheet */
447 fmt
= (word_length
>> 1) - 1;
449 if (mcasp
->op_mode
!= DAVINCI_MCASP_DIT_MODE
) {
450 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, RXSSZ(fmt
),
452 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, TXSSZ(fmt
),
454 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, TXROT(tx_rotate
),
456 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, RXROT(rx_rotate
),
458 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXMASK_REG
, mask
);
461 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXMASK_REG
, mask
);
466 static int mcasp_common_hw_param(struct davinci_mcasp
*mcasp
, int stream
,
473 u8 slots
= mcasp
->tdm_slots
;
474 u8 max_active_serializers
= (channels
+ slots
- 1) / slots
;
476 /* Default configuration */
477 if (mcasp
->version
!= MCASP_VERSION_4
)
478 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PWREMUMGT_REG
, MCASP_SOFT
);
480 /* All PINS as McASP */
481 mcasp_set_reg(mcasp
, DAVINCI_MCASP_PFUNC_REG
, 0x00000000);
483 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
484 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXSTAT_REG
, 0xFFFFFFFF);
485 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_XEVTCTL_REG
, TXDATADMADIS
);
487 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXSTAT_REG
, 0xFFFFFFFF);
488 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_REVTCTL_REG
, RXDATADMADIS
);
491 for (i
= 0; i
< mcasp
->num_serializer
; i
++) {
492 mcasp_set_bits(mcasp
, DAVINCI_MCASP_XRSRCTL_REG(i
),
493 mcasp
->serial_dir
[i
]);
494 if (mcasp
->serial_dir
[i
] == TX_MODE
&&
495 tx_ser
< max_active_serializers
) {
496 mcasp_set_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AXR(i
));
498 } else if (mcasp
->serial_dir
[i
] == RX_MODE
&&
499 rx_ser
< max_active_serializers
) {
500 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_PDIR_REG
, AXR(i
));
503 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_XRSRCTL_REG(i
),
504 SRMOD_INACTIVE
, SRMOD_MASK
);
508 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
513 if (ser
< max_active_serializers
) {
514 dev_warn(mcasp
->dev
, "stream has more channels (%d) than are "
515 "enabled in mcasp (%d)\n", channels
, ser
* slots
);
519 if (mcasp
->txnumevt
&& stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
520 if (mcasp
->txnumevt
* tx_ser
> 64)
523 reg
= mcasp
->fifo_base
+ MCASP_WFIFOCTL_OFFSET
;
524 mcasp_mod_bits(mcasp
, reg
, tx_ser
, NUMDMA_MASK
);
525 mcasp_mod_bits(mcasp
, reg
, ((mcasp
->txnumevt
* tx_ser
) << 8),
529 if (mcasp
->rxnumevt
&& stream
== SNDRV_PCM_STREAM_CAPTURE
) {
530 if (mcasp
->rxnumevt
* rx_ser
> 64)
533 reg
= mcasp
->fifo_base
+ MCASP_RFIFOCTL_OFFSET
;
534 mcasp_mod_bits(mcasp
, reg
, rx_ser
, NUMDMA_MASK
);
535 mcasp_mod_bits(mcasp
, reg
, ((mcasp
->rxnumevt
* rx_ser
) << 8),
542 static int mcasp_i2s_hw_param(struct davinci_mcasp
*mcasp
, int stream
)
548 if ((mcasp
->tdm_slots
< 2) || (mcasp
->tdm_slots
> 32)) {
549 dev_err(mcasp
->dev
, "tdm slot %d not supported\n",
554 active_slots
= (mcasp
->tdm_slots
> 31) ? 32 : mcasp
->tdm_slots
;
555 for (i
= 0; i
< active_slots
; i
++)
558 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, TX_ASYNC
);
560 if (!mcasp
->dat_port
)
563 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXTDM_REG
, mask
);
564 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, busel
| TXORD
);
565 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
,
566 FSXMOD(mcasp
->tdm_slots
), FSXMOD(0x1FF));
568 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXTDM_REG
, mask
);
569 mcasp_set_bits(mcasp
, DAVINCI_MCASP_RXFMT_REG
, busel
| RXORD
);
570 mcasp_mod_bits(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
,
571 FSRMOD(mcasp
->tdm_slots
), FSRMOD(0x1FF));
577 static int mcasp_dit_hw_param(struct davinci_mcasp
*mcasp
)
579 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
581 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXFMT_REG
, TXROT(6) | TXSSZ(15));
583 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
584 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, AFSXE
| FSXMOD(0x180));
586 /* Set the TX tdm : for all the slots */
587 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXTDM_REG
, 0xFFFFFFFF);
589 /* Set the TX clock controls : div = 1 and internal */
590 mcasp_set_bits(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, ACLKXE
| TX_ASYNC
);
592 mcasp_clr_bits(mcasp
, DAVINCI_MCASP_XEVTCTL_REG
, TXDATADMADIS
);
594 /* Only 44100 and 48000 are valid, both have the same setting */
595 mcasp_set_bits(mcasp
, DAVINCI_MCASP_AHCLKXCTL_REG
, AHCLKXDIV(3));
598 mcasp_set_bits(mcasp
, DAVINCI_MCASP_TXDITCTL_REG
, DITEN
);
603 static int davinci_mcasp_hw_params(struct snd_pcm_substream
*substream
,
604 struct snd_pcm_hw_params
*params
,
605 struct snd_soc_dai
*cpu_dai
)
607 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
608 struct davinci_pcm_dma_params
*dma_params
=
609 &mcasp
->dma_params
[substream
->stream
];
610 struct snd_dmaengine_dai_dma_data
*dma_data
=
611 &mcasp
->dma_data
[substream
->stream
];
614 u8 slots
= mcasp
->tdm_slots
;
615 u8 active_serializers
;
616 int channels
= params_channels(params
);
619 /* If mcasp is BCLK master we need to set BCLK divider */
620 if (mcasp
->bclk_master
) {
621 unsigned int bclk_freq
= snd_soc_params_to_bclk(params
);
622 if (mcasp
->sysclk_freq
% bclk_freq
!= 0) {
623 dev_err(mcasp
->dev
, "Can't produce requred BCLK\n");
626 davinci_mcasp_set_clkdiv(
627 cpu_dai
, 1, mcasp
->sysclk_freq
/ bclk_freq
);
630 ret
= mcasp_common_hw_param(mcasp
, substream
->stream
, channels
);
634 if (mcasp
->op_mode
== DAVINCI_MCASP_DIT_MODE
)
635 ret
= mcasp_dit_hw_param(mcasp
);
637 ret
= mcasp_i2s_hw_param(mcasp
, substream
->stream
);
642 switch (params_format(params
)) {
643 case SNDRV_PCM_FORMAT_U8
:
644 case SNDRV_PCM_FORMAT_S8
:
645 dma_params
->data_type
= 1;
649 case SNDRV_PCM_FORMAT_U16_LE
:
650 case SNDRV_PCM_FORMAT_S16_LE
:
651 dma_params
->data_type
= 2;
655 case SNDRV_PCM_FORMAT_U24_3LE
:
656 case SNDRV_PCM_FORMAT_S24_3LE
:
657 dma_params
->data_type
= 3;
661 case SNDRV_PCM_FORMAT_U24_LE
:
662 case SNDRV_PCM_FORMAT_S24_LE
:
663 case SNDRV_PCM_FORMAT_U32_LE
:
664 case SNDRV_PCM_FORMAT_S32_LE
:
665 dma_params
->data_type
= 4;
670 printk(KERN_WARNING
"davinci-mcasp: unsupported PCM format");
674 /* Calculate FIFO level */
675 active_serializers
= (channels
+ slots
- 1) / slots
;
676 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
677 fifo_level
= mcasp
->txnumevt
* active_serializers
;
679 fifo_level
= mcasp
->rxnumevt
* active_serializers
;
681 if (mcasp
->version
== MCASP_VERSION_2
&& !fifo_level
)
682 dma_params
->acnt
= 4;
684 dma_params
->acnt
= dma_params
->data_type
;
686 dma_params
->fifo_level
= fifo_level
;
687 dma_data
->maxburst
= fifo_level
;
689 davinci_config_channel_size(mcasp
, word_length
);
694 static int davinci_mcasp_trigger(struct snd_pcm_substream
*substream
,
695 int cmd
, struct snd_soc_dai
*cpu_dai
)
697 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(cpu_dai
);
701 case SNDRV_PCM_TRIGGER_RESUME
:
702 case SNDRV_PCM_TRIGGER_START
:
703 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
704 davinci_mcasp_start(mcasp
, substream
->stream
);
706 case SNDRV_PCM_TRIGGER_SUSPEND
:
707 case SNDRV_PCM_TRIGGER_STOP
:
708 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
709 davinci_mcasp_stop(mcasp
, substream
->stream
);
719 static int davinci_mcasp_startup(struct snd_pcm_substream
*substream
,
720 struct snd_soc_dai
*dai
)
722 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
724 if (mcasp
->version
== MCASP_VERSION_4
)
725 snd_soc_dai_set_dma_data(dai
, substream
,
726 &mcasp
->dma_data
[substream
->stream
]);
728 snd_soc_dai_set_dma_data(dai
, substream
, mcasp
->dma_params
);
733 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops
= {
734 .startup
= davinci_mcasp_startup
,
735 .trigger
= davinci_mcasp_trigger
,
736 .hw_params
= davinci_mcasp_hw_params
,
737 .set_fmt
= davinci_mcasp_set_dai_fmt
,
738 .set_clkdiv
= davinci_mcasp_set_clkdiv
,
739 .set_sysclk
= davinci_mcasp_set_sysclk
,
742 #ifdef CONFIG_PM_SLEEP
743 static int davinci_mcasp_suspend(struct snd_soc_dai
*dai
)
745 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
746 struct davinci_mcasp_context
*context
= &mcasp
->context
;
748 context
->txfmtctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
);
749 context
->rxfmtctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
);
750 context
->txfmt
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_TXFMT_REG
);
751 context
->rxfmt
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_RXFMT_REG
);
752 context
->aclkxctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
);
753 context
->aclkrctl
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
);
754 context
->pdir
= mcasp_get_reg(mcasp
, DAVINCI_MCASP_PDIR_REG
);
759 static int davinci_mcasp_resume(struct snd_soc_dai
*dai
)
761 struct davinci_mcasp
*mcasp
= snd_soc_dai_get_drvdata(dai
);
762 struct davinci_mcasp_context
*context
= &mcasp
->context
;
764 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXFMCTL_REG
, context
->txfmtctl
);
765 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXFMCTL_REG
, context
->rxfmtctl
);
766 mcasp_set_reg(mcasp
, DAVINCI_MCASP_TXFMT_REG
, context
->txfmt
);
767 mcasp_set_reg(mcasp
, DAVINCI_MCASP_RXFMT_REG
, context
->rxfmt
);
768 mcasp_set_reg(mcasp
, DAVINCI_MCASP_ACLKXCTL_REG
, context
->aclkxctl
);
769 mcasp_set_reg(mcasp
, DAVINCI_MCASP_ACLKRCTL_REG
, context
->aclkrctl
);
770 mcasp_set_reg(mcasp
, DAVINCI_MCASP_PDIR_REG
, context
->pdir
);
775 #define davinci_mcasp_suspend NULL
776 #define davinci_mcasp_resume NULL
779 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
781 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
782 SNDRV_PCM_FMTBIT_U8 | \
783 SNDRV_PCM_FMTBIT_S16_LE | \
784 SNDRV_PCM_FMTBIT_U16_LE | \
785 SNDRV_PCM_FMTBIT_S24_LE | \
786 SNDRV_PCM_FMTBIT_U24_LE | \
787 SNDRV_PCM_FMTBIT_S24_3LE | \
788 SNDRV_PCM_FMTBIT_U24_3LE | \
789 SNDRV_PCM_FMTBIT_S32_LE | \
790 SNDRV_PCM_FMTBIT_U32_LE)
792 static struct snd_soc_dai_driver davinci_mcasp_dai
[] = {
794 .name
= "davinci-mcasp.0",
795 .suspend
= davinci_mcasp_suspend
,
796 .resume
= davinci_mcasp_resume
,
799 .channels_max
= 32 * 16,
800 .rates
= DAVINCI_MCASP_RATES
,
801 .formats
= DAVINCI_MCASP_PCM_FMTS
,
805 .channels_max
= 32 * 16,
806 .rates
= DAVINCI_MCASP_RATES
,
807 .formats
= DAVINCI_MCASP_PCM_FMTS
,
809 .ops
= &davinci_mcasp_dai_ops
,
813 .name
= "davinci-mcasp.1",
817 .rates
= DAVINCI_MCASP_RATES
,
818 .formats
= DAVINCI_MCASP_PCM_FMTS
,
820 .ops
= &davinci_mcasp_dai_ops
,
825 static const struct snd_soc_component_driver davinci_mcasp_component
= {
826 .name
= "davinci-mcasp",
829 /* Some HW specific values and defaults. The rest is filled in from DT. */
830 static struct davinci_mcasp_pdata dm646x_mcasp_pdata
= {
831 .tx_dma_offset
= 0x400,
832 .rx_dma_offset
= 0x400,
833 .asp_chan_q
= EVENTQ_0
,
834 .version
= MCASP_VERSION_1
,
837 static struct davinci_mcasp_pdata da830_mcasp_pdata
= {
838 .tx_dma_offset
= 0x2000,
839 .rx_dma_offset
= 0x2000,
840 .asp_chan_q
= EVENTQ_0
,
841 .version
= MCASP_VERSION_2
,
844 static struct davinci_mcasp_pdata am33xx_mcasp_pdata
= {
847 .asp_chan_q
= EVENTQ_0
,
848 .version
= MCASP_VERSION_3
,
851 static struct davinci_mcasp_pdata dra7_mcasp_pdata
= {
852 .tx_dma_offset
= 0x200,
853 .rx_dma_offset
= 0x284,
854 .asp_chan_q
= EVENTQ_0
,
855 .version
= MCASP_VERSION_4
,
858 static const struct of_device_id mcasp_dt_ids
[] = {
860 .compatible
= "ti,dm646x-mcasp-audio",
861 .data
= &dm646x_mcasp_pdata
,
864 .compatible
= "ti,da830-mcasp-audio",
865 .data
= &da830_mcasp_pdata
,
868 .compatible
= "ti,am33xx-mcasp-audio",
869 .data
= &am33xx_mcasp_pdata
,
872 .compatible
= "ti,dra7-mcasp-audio",
873 .data
= &dra7_mcasp_pdata
,
877 MODULE_DEVICE_TABLE(of
, mcasp_dt_ids
);
879 static int mcasp_reparent_fck(struct platform_device
*pdev
)
881 struct device_node
*node
= pdev
->dev
.of_node
;
882 struct clk
*gfclk
, *parent_clk
;
883 const char *parent_name
;
889 parent_name
= of_get_property(node
, "fck_parent", NULL
);
893 gfclk
= clk_get(&pdev
->dev
, "fck");
895 dev_err(&pdev
->dev
, "failed to get fck\n");
896 return PTR_ERR(gfclk
);
899 parent_clk
= clk_get(NULL
, parent_name
);
900 if (IS_ERR(parent_clk
)) {
901 dev_err(&pdev
->dev
, "failed to get parent clock\n");
902 ret
= PTR_ERR(parent_clk
);
906 ret
= clk_set_parent(gfclk
, parent_clk
);
908 dev_err(&pdev
->dev
, "failed to reparent fck\n");
919 static struct davinci_mcasp_pdata
*davinci_mcasp_set_pdata_from_of(
920 struct platform_device
*pdev
)
922 struct device_node
*np
= pdev
->dev
.of_node
;
923 struct davinci_mcasp_pdata
*pdata
= NULL
;
924 const struct of_device_id
*match
=
925 of_match_device(mcasp_dt_ids
, &pdev
->dev
);
926 struct of_phandle_args dma_spec
;
928 const u32
*of_serial_dir32
;
932 if (pdev
->dev
.platform_data
) {
933 pdata
= pdev
->dev
.platform_data
;
936 pdata
= (struct davinci_mcasp_pdata
*) match
->data
;
938 /* control shouldn't reach here. something is wrong */
943 ret
= of_property_read_u32(np
, "op-mode", &val
);
945 pdata
->op_mode
= val
;
947 ret
= of_property_read_u32(np
, "tdm-slots", &val
);
949 if (val
< 2 || val
> 32) {
951 "tdm-slots must be in rage [2-32]\n");
956 pdata
->tdm_slots
= val
;
959 of_serial_dir32
= of_get_property(np
, "serial-dir", &val
);
961 if (of_serial_dir32
) {
962 u8
*of_serial_dir
= devm_kzalloc(&pdev
->dev
,
963 (sizeof(*of_serial_dir
) * val
),
965 if (!of_serial_dir
) {
970 for (i
= 0; i
< val
; i
++)
971 of_serial_dir
[i
] = be32_to_cpup(&of_serial_dir32
[i
]);
973 pdata
->num_serializer
= val
;
974 pdata
->serial_dir
= of_serial_dir
;
977 ret
= of_property_match_string(np
, "dma-names", "tx");
981 ret
= of_parse_phandle_with_args(np
, "dmas", "#dma-cells", ret
,
986 pdata
->tx_dma_channel
= dma_spec
.args
[0];
988 ret
= of_property_match_string(np
, "dma-names", "rx");
992 ret
= of_parse_phandle_with_args(np
, "dmas", "#dma-cells", ret
,
997 pdata
->rx_dma_channel
= dma_spec
.args
[0];
999 ret
= of_property_read_u32(np
, "tx-num-evt", &val
);
1001 pdata
->txnumevt
= val
;
1003 ret
= of_property_read_u32(np
, "rx-num-evt", &val
);
1005 pdata
->rxnumevt
= val
;
1007 ret
= of_property_read_u32(np
, "sram-size-playback", &val
);
1009 pdata
->sram_size_playback
= val
;
1011 ret
= of_property_read_u32(np
, "sram-size-capture", &val
);
1013 pdata
->sram_size_capture
= val
;
1019 dev_err(&pdev
->dev
, "Error populating platform data, err %d\n",
1026 static int davinci_mcasp_probe(struct platform_device
*pdev
)
1028 struct davinci_pcm_dma_params
*dma_params
;
1029 struct snd_dmaengine_dai_dma_data
*dma_data
;
1030 struct resource
*mem
, *ioarea
, *res
, *dat
;
1031 struct davinci_mcasp_pdata
*pdata
;
1032 struct davinci_mcasp
*mcasp
;
1035 if (!pdev
->dev
.platform_data
&& !pdev
->dev
.of_node
) {
1036 dev_err(&pdev
->dev
, "No platform data supplied\n");
1040 mcasp
= devm_kzalloc(&pdev
->dev
, sizeof(struct davinci_mcasp
),
1045 pdata
= davinci_mcasp_set_pdata_from_of(pdev
);
1047 dev_err(&pdev
->dev
, "no platform data\n");
1051 mem
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mpu");
1053 dev_warn(mcasp
->dev
,
1054 "\"mpu\" mem resource not found, using index 0\n");
1055 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1057 dev_err(&pdev
->dev
, "no mem resource?\n");
1062 ioarea
= devm_request_mem_region(&pdev
->dev
, mem
->start
,
1063 resource_size(mem
), pdev
->name
);
1065 dev_err(&pdev
->dev
, "Audio region already claimed\n");
1069 pm_runtime_enable(&pdev
->dev
);
1071 ret
= pm_runtime_get_sync(&pdev
->dev
);
1072 if (IS_ERR_VALUE(ret
)) {
1073 dev_err(&pdev
->dev
, "pm_runtime_get_sync() failed\n");
1077 mcasp
->base
= devm_ioremap(&pdev
->dev
, mem
->start
, resource_size(mem
));
1079 dev_err(&pdev
->dev
, "ioremap failed\n");
1081 goto err_release_clk
;
1084 mcasp
->op_mode
= pdata
->op_mode
;
1085 mcasp
->tdm_slots
= pdata
->tdm_slots
;
1086 mcasp
->num_serializer
= pdata
->num_serializer
;
1087 mcasp
->serial_dir
= pdata
->serial_dir
;
1088 mcasp
->version
= pdata
->version
;
1089 mcasp
->txnumevt
= pdata
->txnumevt
;
1090 mcasp
->rxnumevt
= pdata
->rxnumevt
;
1092 mcasp
->dev
= &pdev
->dev
;
1094 dat
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dat");
1096 mcasp
->dat_port
= true;
1098 dma_params
= &mcasp
->dma_params
[SNDRV_PCM_STREAM_PLAYBACK
];
1099 dma_data
= &mcasp
->dma_data
[SNDRV_PCM_STREAM_PLAYBACK
];
1100 dma_params
->asp_chan_q
= pdata
->asp_chan_q
;
1101 dma_params
->ram_chan_q
= pdata
->ram_chan_q
;
1102 dma_params
->sram_pool
= pdata
->sram_pool
;
1103 dma_params
->sram_size
= pdata
->sram_size_playback
;
1105 dma_params
->dma_addr
= dat
->start
;
1107 dma_params
->dma_addr
= mem
->start
+ pdata
->tx_dma_offset
;
1109 /* Unconditional dmaengine stuff */
1110 dma_data
->addr
= dma_params
->dma_addr
;
1112 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1114 dma_params
->channel
= res
->start
;
1116 dma_params
->channel
= pdata
->tx_dma_channel
;
1118 /* dmaengine filter data for DT and non-DT boot */
1119 if (pdev
->dev
.of_node
)
1120 dma_data
->filter_data
= "tx";
1122 dma_data
->filter_data
= &dma_params
->channel
;
1124 dma_params
= &mcasp
->dma_params
[SNDRV_PCM_STREAM_CAPTURE
];
1125 dma_data
= &mcasp
->dma_data
[SNDRV_PCM_STREAM_CAPTURE
];
1126 dma_params
->asp_chan_q
= pdata
->asp_chan_q
;
1127 dma_params
->ram_chan_q
= pdata
->ram_chan_q
;
1128 dma_params
->sram_pool
= pdata
->sram_pool
;
1129 dma_params
->sram_size
= pdata
->sram_size_capture
;
1131 dma_params
->dma_addr
= dat
->start
;
1133 dma_params
->dma_addr
= mem
->start
+ pdata
->rx_dma_offset
;
1135 /* Unconditional dmaengine stuff */
1136 dma_data
->addr
= dma_params
->dma_addr
;
1138 if (mcasp
->version
< MCASP_VERSION_3
) {
1139 mcasp
->fifo_base
= DAVINCI_MCASP_V2_AFIFO_BASE
;
1140 /* dma_params->dma_addr is pointing to the data port address */
1141 mcasp
->dat_port
= true;
1143 mcasp
->fifo_base
= DAVINCI_MCASP_V3_AFIFO_BASE
;
1146 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
1148 dma_params
->channel
= res
->start
;
1150 dma_params
->channel
= pdata
->rx_dma_channel
;
1152 /* dmaengine filter data for DT and non-DT boot */
1153 if (pdev
->dev
.of_node
)
1154 dma_data
->filter_data
= "rx";
1156 dma_data
->filter_data
= &dma_params
->channel
;
1158 dev_set_drvdata(&pdev
->dev
, mcasp
);
1160 mcasp_reparent_fck(pdev
);
1162 ret
= snd_soc_register_component(&pdev
->dev
, &davinci_mcasp_component
,
1163 &davinci_mcasp_dai
[pdata
->op_mode
], 1);
1166 goto err_release_clk
;
1168 if (mcasp
->version
!= MCASP_VERSION_4
) {
1169 ret
= davinci_soc_platform_register(&pdev
->dev
);
1171 dev_err(&pdev
->dev
, "register PCM failed: %d\n", ret
);
1172 goto err_unregister_component
;
1178 err_unregister_component
:
1179 snd_soc_unregister_component(&pdev
->dev
);
1181 pm_runtime_put_sync(&pdev
->dev
);
1182 pm_runtime_disable(&pdev
->dev
);
1186 static int davinci_mcasp_remove(struct platform_device
*pdev
)
1188 struct davinci_mcasp
*mcasp
= dev_get_drvdata(&pdev
->dev
);
1190 snd_soc_unregister_component(&pdev
->dev
);
1191 if (mcasp
->version
!= MCASP_VERSION_4
)
1192 davinci_soc_platform_unregister(&pdev
->dev
);
1194 pm_runtime_put_sync(&pdev
->dev
);
1195 pm_runtime_disable(&pdev
->dev
);
1200 static struct platform_driver davinci_mcasp_driver
= {
1201 .probe
= davinci_mcasp_probe
,
1202 .remove
= davinci_mcasp_remove
,
1204 .name
= "davinci-mcasp",
1205 .owner
= THIS_MODULE
,
1206 .of_match_table
= mcasp_dt_ids
,
1210 module_platform_driver(davinci_mcasp_driver
);
1212 MODULE_AUTHOR("Steve Chen");
1213 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1214 MODULE_LICENSE("GPL");