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ASoC: davinci-mcasp: Fix XDATA check in mcasp_start_tx
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / davinci / davinci-mcasp.c
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
40
41 #include "edma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
60 };
61
62 struct davinci_mcasp_context {
63 u32 config_regs[ARRAY_SIZE(context_regs)];
64 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
66 bool pm_state;
67 };
68
69 struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72 };
73
74 struct davinci_mcasp {
75 struct snd_dmaengine_dai_dma_data dma_data[2];
76 void __iomem *base;
77 u32 fifo_base;
78 struct device *dev;
79 struct snd_pcm_substream *substreams[2];
80
81 /* McASP specific data */
82 int tdm_slots;
83 u32 tdm_mask[2];
84 int slot_width;
85 u8 op_mode;
86 u8 num_serializer;
87 u8 *serial_dir;
88 u8 version;
89 u8 bclk_div;
90 int streams;
91 u32 irq_request[2];
92 int dma_request[2];
93
94 int sysclk_freq;
95 bool bclk_master;
96
97 /* McASP FIFO related */
98 u8 txnumevt;
99 u8 rxnumevt;
100
101 bool dat_port;
102
103 /* Used for comstraint setting on the second stream */
104 u32 channels;
105
106 #ifdef CONFIG_PM_SLEEP
107 struct davinci_mcasp_context context;
108 #endif
109
110 struct davinci_mcasp_ruledata ruledata[2];
111 struct snd_pcm_hw_constraint_list chconstr[2];
112 };
113
114 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
115 u32 val)
116 {
117 void __iomem *reg = mcasp->base + offset;
118 __raw_writel(__raw_readl(reg) | val, reg);
119 }
120
121 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
122 u32 val)
123 {
124 void __iomem *reg = mcasp->base + offset;
125 __raw_writel((__raw_readl(reg) & ~(val)), reg);
126 }
127
128 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
129 u32 val, u32 mask)
130 {
131 void __iomem *reg = mcasp->base + offset;
132 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
133 }
134
135 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
136 u32 val)
137 {
138 __raw_writel(val, mcasp->base + offset);
139 }
140
141 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
142 {
143 return (u32)__raw_readl(mcasp->base + offset);
144 }
145
146 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
147 {
148 int i = 0;
149
150 mcasp_set_bits(mcasp, ctl_reg, val);
151
152 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
153 /* loop count is to avoid the lock-up */
154 for (i = 0; i < 1000; i++) {
155 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
156 break;
157 }
158
159 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
160 printk(KERN_ERR "GBLCTL write error\n");
161 }
162
163 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
164 {
165 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
166 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
167
168 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
169 }
170
171 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
172 {
173 if (mcasp->rxnumevt) { /* enable FIFO */
174 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
175
176 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
177 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
178 }
179
180 /* Start clocks */
181 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
182 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
183 /*
184 * When ASYNC == 0 the transmit and receive sections operate
185 * synchronously from the transmit clock and frame sync. We need to make
186 * sure that the TX signlas are enabled when starting reception.
187 */
188 if (mcasp_is_synchronous(mcasp)) {
189 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
191 }
192
193 /* Activate serializer(s) */
194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
195 /* Release RX state machine */
196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
197 /* Release Frame Sync generator */
198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
199 if (mcasp_is_synchronous(mcasp))
200 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
201
202 /* enable receive IRQs */
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
204 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
205 }
206
207 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
208 {
209 u32 cnt;
210
211 if (mcasp->txnumevt) { /* enable FIFO */
212 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
213
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
216 }
217
218 /* Start clocks */
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
221 /* Activate serializer(s) */
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
223
224 /* wait for XDATA to be cleared */
225 cnt = 0;
226 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
227 (cnt < 100000))
228 cnt++;
229
230 /* Release TX state machine */
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
232 /* Release Frame Sync generator */
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
234
235 /* enable transmit IRQs */
236 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
237 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
238 }
239
240 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
241 {
242 mcasp->streams++;
243
244 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
245 mcasp_start_tx(mcasp);
246 else
247 mcasp_start_rx(mcasp);
248 }
249
250 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
251 {
252 /* disable IRQ sources */
253 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
254 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
255
256 /*
257 * In synchronous mode stop the TX clocks if no other stream is
258 * running
259 */
260 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
261 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
262
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
265
266 if (mcasp->rxnumevt) { /* disable FIFO */
267 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
268
269 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
270 }
271 }
272
273 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
274 {
275 u32 val = 0;
276
277 /* disable IRQ sources */
278 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
279 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
280
281 /*
282 * In synchronous mode keep TX clocks running if the capture stream is
283 * still running.
284 */
285 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
286 val = TXHCLKRST | TXCLKRST | TXFSRST;
287
288 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
289 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
290
291 if (mcasp->txnumevt) { /* disable FIFO */
292 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
293
294 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
295 }
296 }
297
298 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
299 {
300 mcasp->streams--;
301
302 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
303 mcasp_stop_tx(mcasp);
304 else
305 mcasp_stop_rx(mcasp);
306 }
307
308 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
309 {
310 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
311 struct snd_pcm_substream *substream;
312 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
313 u32 handled_mask = 0;
314 u32 stat;
315
316 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
317 if (stat & XUNDRN & irq_mask) {
318 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
319 handled_mask |= XUNDRN;
320
321 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
322 if (substream) {
323 snd_pcm_stream_lock_irq(substream);
324 if (snd_pcm_running(substream))
325 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
326 snd_pcm_stream_unlock_irq(substream);
327 }
328 }
329
330 if (!handled_mask)
331 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
332 stat);
333
334 if (stat & XRERR)
335 handled_mask |= XRERR;
336
337 /* Ack the handled event only */
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
339
340 return IRQ_RETVAL(handled_mask);
341 }
342
343 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
344 {
345 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
346 struct snd_pcm_substream *substream;
347 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
348 u32 handled_mask = 0;
349 u32 stat;
350
351 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
352 if (stat & ROVRN & irq_mask) {
353 dev_warn(mcasp->dev, "Receive buffer overflow\n");
354 handled_mask |= ROVRN;
355
356 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
357 if (substream) {
358 snd_pcm_stream_lock_irq(substream);
359 if (snd_pcm_running(substream))
360 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
361 snd_pcm_stream_unlock_irq(substream);
362 }
363 }
364
365 if (!handled_mask)
366 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
367 stat);
368
369 if (stat & XRERR)
370 handled_mask |= XRERR;
371
372 /* Ack the handled event only */
373 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
374
375 return IRQ_RETVAL(handled_mask);
376 }
377
378 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
379 {
380 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
381 irqreturn_t ret = IRQ_NONE;
382
383 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
384 ret = davinci_mcasp_tx_irq_handler(irq, data);
385
386 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
387 ret |= davinci_mcasp_rx_irq_handler(irq, data);
388
389 return ret;
390 }
391
392 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
393 unsigned int fmt)
394 {
395 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
396 int ret = 0;
397 u32 data_delay;
398 bool fs_pol_rising;
399 bool inv_fs = false;
400
401 pm_runtime_get_sync(mcasp->dev);
402 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
403 case SND_SOC_DAIFMT_DSP_A:
404 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
405 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
406 /* 1st data bit occur one ACLK cycle after the frame sync */
407 data_delay = 1;
408 break;
409 case SND_SOC_DAIFMT_DSP_B:
410 case SND_SOC_DAIFMT_AC97:
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
412 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
413 /* No delay after FS */
414 data_delay = 0;
415 break;
416 case SND_SOC_DAIFMT_I2S:
417 /* configure a full-word SYNC pulse (LRCLK) */
418 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
419 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
420 /* 1st data bit occur one ACLK cycle after the frame sync */
421 data_delay = 1;
422 /* FS need to be inverted */
423 inv_fs = true;
424 break;
425 case SND_SOC_DAIFMT_LEFT_J:
426 /* configure a full-word SYNC pulse (LRCLK) */
427 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
428 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
429 /* No delay after FS */
430 data_delay = 0;
431 break;
432 default:
433 ret = -EINVAL;
434 goto out;
435 }
436
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
438 FSXDLY(3));
439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
440 FSRDLY(3));
441
442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
443 case SND_SOC_DAIFMT_CBS_CFS:
444 /* codec is clock and frame slave */
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
446 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
447
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
450
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
453 mcasp->bclk_master = 1;
454 break;
455 case SND_SOC_DAIFMT_CBS_CFM:
456 /* codec is clock slave and frame master */
457 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
459
460 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
462
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
465 mcasp->bclk_master = 1;
466 break;
467 case SND_SOC_DAIFMT_CBM_CFS:
468 /* codec is clock master and frame slave */
469 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
471
472 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
473 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
474
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
477 mcasp->bclk_master = 0;
478 break;
479 case SND_SOC_DAIFMT_CBM_CFM:
480 /* codec is clock and frame master */
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
483
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
486
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
488 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
489 mcasp->bclk_master = 0;
490 break;
491 default:
492 ret = -EINVAL;
493 goto out;
494 }
495
496 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
497 case SND_SOC_DAIFMT_IB_NF:
498 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
499 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
500 fs_pol_rising = true;
501 break;
502 case SND_SOC_DAIFMT_NB_IF:
503 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
504 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
505 fs_pol_rising = false;
506 break;
507 case SND_SOC_DAIFMT_IB_IF:
508 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
509 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
510 fs_pol_rising = false;
511 break;
512 case SND_SOC_DAIFMT_NB_NF:
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
514 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
515 fs_pol_rising = true;
516 break;
517 default:
518 ret = -EINVAL;
519 goto out;
520 }
521
522 if (inv_fs)
523 fs_pol_rising = !fs_pol_rising;
524
525 if (fs_pol_rising) {
526 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
528 } else {
529 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
530 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
531 }
532 out:
533 pm_runtime_put(mcasp->dev);
534 return ret;
535 }
536
537 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
538 int div, bool explicit)
539 {
540 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
541
542 pm_runtime_get_sync(mcasp->dev);
543 switch (div_id) {
544 case 0: /* MCLK divider */
545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
546 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
547 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
548 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
549 break;
550
551 case 1: /* BCLK divider */
552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
553 ACLKXDIV(div - 1), ACLKXDIV_MASK);
554 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
555 ACLKRDIV(div - 1), ACLKRDIV_MASK);
556 if (explicit)
557 mcasp->bclk_div = div;
558 break;
559
560 case 2: /*
561 * BCLK/LRCLK ratio descries how many bit-clock cycles
562 * fit into one frame. The clock ratio is given for a
563 * full period of data (for I2S format both left and
564 * right channels), so it has to be divided by number
565 * of tdm-slots (for I2S - divided by 2).
566 * Instead of storing this ratio, we calculate a new
567 * tdm_slot width by dividing the the ratio by the
568 * number of configured tdm slots.
569 */
570 mcasp->slot_width = div / mcasp->tdm_slots;
571 if (div % mcasp->tdm_slots)
572 dev_warn(mcasp->dev,
573 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
574 __func__, div, mcasp->tdm_slots);
575 break;
576
577 default:
578 return -EINVAL;
579 }
580
581 pm_runtime_put(mcasp->dev);
582 return 0;
583 }
584
585 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
586 int div)
587 {
588 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
589 }
590
591 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
592 unsigned int freq, int dir)
593 {
594 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
595
596 pm_runtime_get_sync(mcasp->dev);
597 if (dir == SND_SOC_CLOCK_OUT) {
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
601 } else {
602 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
605 }
606
607 mcasp->sysclk_freq = freq;
608
609 pm_runtime_put(mcasp->dev);
610 return 0;
611 }
612
613 /* All serializers must have equal number of channels */
614 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
615 int serializers)
616 {
617 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
618 unsigned int *list = (unsigned int *) cl->list;
619 int slots = mcasp->tdm_slots;
620 int i, count = 0;
621
622 if (mcasp->tdm_mask[stream])
623 slots = hweight32(mcasp->tdm_mask[stream]);
624
625 for (i = 2; i <= slots; i++)
626 list[count++] = i;
627
628 for (i = 2; i <= serializers; i++)
629 list[count++] = i*slots;
630
631 cl->count = count;
632
633 return 0;
634 }
635
636 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
637 {
638 int rx_serializers = 0, tx_serializers = 0, ret, i;
639
640 for (i = 0; i < mcasp->num_serializer; i++)
641 if (mcasp->serial_dir[i] == TX_MODE)
642 tx_serializers++;
643 else if (mcasp->serial_dir[i] == RX_MODE)
644 rx_serializers++;
645
646 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
647 tx_serializers);
648 if (ret)
649 return ret;
650
651 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
652 rx_serializers);
653
654 return ret;
655 }
656
657
658 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
659 unsigned int tx_mask,
660 unsigned int rx_mask,
661 int slots, int slot_width)
662 {
663 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
664
665 dev_dbg(mcasp->dev,
666 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
667 __func__, tx_mask, rx_mask, slots, slot_width);
668
669 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
670 dev_err(mcasp->dev,
671 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
672 tx_mask, rx_mask, slots);
673 return -EINVAL;
674 }
675
676 if (slot_width &&
677 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
678 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
679 __func__, slot_width);
680 return -EINVAL;
681 }
682
683 mcasp->tdm_slots = slots;
684 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = rx_mask;
685 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = tx_mask;
686 mcasp->slot_width = slot_width;
687
688 return davinci_mcasp_set_ch_constraints(mcasp);
689 }
690
691 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
692 int sample_width)
693 {
694 u32 fmt;
695 u32 tx_rotate = (sample_width / 4) & 0x7;
696 u32 mask = (1ULL << sample_width) - 1;
697 u32 slot_width = sample_width;
698
699 /*
700 * For captured data we should not rotate, inversion and masking is
701 * enoguh to get the data to the right position:
702 * Format data from bus after reverse (XRBUF)
703 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
704 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
705 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
706 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
707 */
708 u32 rx_rotate = 0;
709
710 /*
711 * Setting the tdm slot width either with set_clkdiv() or
712 * set_tdm_slot() allows us to for example send 32 bits per
713 * channel to the codec, while only 16 of them carry audio
714 * payload.
715 */
716 if (mcasp->slot_width) {
717 /*
718 * When we have more bclk then it is needed for the
719 * data, we need to use the rotation to move the
720 * received samples to have correct alignment.
721 */
722 slot_width = mcasp->slot_width;
723 rx_rotate = (slot_width - sample_width) / 4;
724 }
725
726 /* mapping of the XSSZ bit-field as described in the datasheet */
727 fmt = (slot_width >> 1) - 1;
728
729 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
730 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
731 RXSSZ(0x0F));
732 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
733 TXSSZ(0x0F));
734 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
735 TXROT(7));
736 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
737 RXROT(7));
738 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
739 }
740
741 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
742
743 return 0;
744 }
745
746 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
747 int period_words, int channels)
748 {
749 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
750 int i;
751 u8 tx_ser = 0;
752 u8 rx_ser = 0;
753 u8 slots = mcasp->tdm_slots;
754 u8 max_active_serializers = (channels + slots - 1) / slots;
755 int active_serializers, numevt;
756 u32 reg;
757 /* Default configuration */
758 if (mcasp->version < MCASP_VERSION_3)
759 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
760
761 /* All PINS as McASP */
762 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
763
764 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
765 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
766 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
767 } else {
768 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
769 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
770 }
771
772 for (i = 0; i < mcasp->num_serializer; i++) {
773 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
774 mcasp->serial_dir[i]);
775 if (mcasp->serial_dir[i] == TX_MODE &&
776 tx_ser < max_active_serializers) {
777 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
778 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
779 DISMOD_LOW, DISMOD_MASK);
780 tx_ser++;
781 } else if (mcasp->serial_dir[i] == RX_MODE &&
782 rx_ser < max_active_serializers) {
783 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
784 rx_ser++;
785 } else {
786 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
787 SRMOD_INACTIVE, SRMOD_MASK);
788 }
789 }
790
791 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
792 active_serializers = tx_ser;
793 numevt = mcasp->txnumevt;
794 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
795 } else {
796 active_serializers = rx_ser;
797 numevt = mcasp->rxnumevt;
798 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
799 }
800
801 if (active_serializers < max_active_serializers) {
802 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
803 "enabled in mcasp (%d)\n", channels,
804 active_serializers * slots);
805 return -EINVAL;
806 }
807
808 /* AFIFO is not in use */
809 if (!numevt) {
810 /* Configure the burst size for platform drivers */
811 if (active_serializers > 1) {
812 /*
813 * If more than one serializers are in use we have one
814 * DMA request to provide data for all serializers.
815 * For example if three serializers are enabled the DMA
816 * need to transfer three words per DMA request.
817 */
818 dma_data->maxburst = active_serializers;
819 } else {
820 dma_data->maxburst = 0;
821 }
822 return 0;
823 }
824
825 if (period_words % active_serializers) {
826 dev_err(mcasp->dev, "Invalid combination of period words and "
827 "active serializers: %d, %d\n", period_words,
828 active_serializers);
829 return -EINVAL;
830 }
831
832 /*
833 * Calculate the optimal AFIFO depth for platform side:
834 * The number of words for numevt need to be in steps of active
835 * serializers.
836 */
837 numevt = (numevt / active_serializers) * active_serializers;
838
839 while (period_words % numevt && numevt > 0)
840 numevt -= active_serializers;
841 if (numevt <= 0)
842 numevt = active_serializers;
843
844 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
845 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
846
847 /* Configure the burst size for platform drivers */
848 if (numevt == 1)
849 numevt = 0;
850 dma_data->maxburst = numevt;
851
852 return 0;
853 }
854
855 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
856 int channels)
857 {
858 int i, active_slots;
859 int total_slots;
860 int active_serializers;
861 u32 mask = 0;
862 u32 busel = 0;
863
864 total_slots = mcasp->tdm_slots;
865
866 /*
867 * If more than one serializer is needed, then use them with
868 * all the specified tdm_slots. Otherwise, one serializer can
869 * cope with the transaction using just as many slots as there
870 * are channels in the stream.
871 */
872 if (mcasp->tdm_mask[stream]) {
873 active_slots = hweight32(mcasp->tdm_mask[stream]);
874 active_serializers = (channels + active_slots - 1) /
875 active_slots;
876 if (active_serializers == 1) {
877 active_slots = channels;
878 for (i = 0; i < total_slots; i++) {
879 if ((1 << i) & mcasp->tdm_mask[stream]) {
880 mask |= (1 << i);
881 if (--active_slots <= 0)
882 break;
883 }
884 }
885 }
886 } else {
887 active_serializers = (channels + total_slots - 1) / total_slots;
888 if (active_serializers == 1)
889 active_slots = channels;
890 else
891 active_slots = total_slots;
892
893 for (i = 0; i < active_slots; i++)
894 mask |= (1 << i);
895 }
896 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
897
898 if (!mcasp->dat_port)
899 busel = TXSEL;
900
901 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
902 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
903 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
904 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
905 FSXMOD(total_slots), FSXMOD(0x1FF));
906 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
907 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
908 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
909 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
910 FSRMOD(total_slots), FSRMOD(0x1FF));
911 }
912
913 return 0;
914 }
915
916 /* S/PDIF */
917 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
918 unsigned int rate)
919 {
920 u32 cs_value = 0;
921 u8 *cs_bytes = (u8*) &cs_value;
922
923 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
924 and LSB first */
925 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
926
927 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
928 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
929
930 /* Set the TX tdm : for all the slots */
931 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
932
933 /* Set the TX clock controls : div = 1 and internal */
934 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
935
936 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
937
938 /* Only 44100 and 48000 are valid, both have the same setting */
939 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
940
941 /* Enable the DIT */
942 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
943
944 /* Set S/PDIF channel status bits */
945 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
946 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
947
948 switch (rate) {
949 case 22050:
950 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
951 break;
952 case 24000:
953 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
954 break;
955 case 32000:
956 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
957 break;
958 case 44100:
959 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
960 break;
961 case 48000:
962 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
963 break;
964 case 88200:
965 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
966 break;
967 case 96000:
968 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
969 break;
970 case 176400:
971 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
972 break;
973 case 192000:
974 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
975 break;
976 default:
977 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
978 return -EINVAL;
979 }
980
981 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
982 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
983
984 return 0;
985 }
986
987 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
988 unsigned int bclk_freq,
989 int *error_ppm)
990 {
991 int div = mcasp->sysclk_freq / bclk_freq;
992 int rem = mcasp->sysclk_freq % bclk_freq;
993
994 if (rem != 0) {
995 if (div == 0 ||
996 ((mcasp->sysclk_freq / div) - bclk_freq) >
997 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
998 div++;
999 rem = rem - bclk_freq;
1000 }
1001 }
1002 if (error_ppm)
1003 *error_ppm =
1004 (div*1000000 + (int)div64_long(1000000LL*rem,
1005 (int)bclk_freq))
1006 /div - 1000000;
1007
1008 return div;
1009 }
1010
1011 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1012 struct snd_pcm_hw_params *params,
1013 struct snd_soc_dai *cpu_dai)
1014 {
1015 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1016 int word_length;
1017 int channels = params_channels(params);
1018 int period_size = params_period_size(params);
1019 int ret;
1020
1021 /*
1022 * If mcasp is BCLK master, and a BCLK divider was not provided by
1023 * the machine driver, we need to calculate the ratio.
1024 */
1025 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1026 int slots = mcasp->tdm_slots;
1027 int rate = params_rate(params);
1028 int sbits = params_width(params);
1029 int ppm, div;
1030
1031 if (mcasp->slot_width)
1032 sbits = mcasp->slot_width;
1033
1034 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
1035 &ppm);
1036 if (ppm)
1037 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1038 ppm);
1039
1040 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
1041 }
1042
1043 ret = mcasp_common_hw_param(mcasp, substream->stream,
1044 period_size * channels, channels);
1045 if (ret)
1046 return ret;
1047
1048 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1049 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1050 else
1051 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1052 channels);
1053
1054 if (ret)
1055 return ret;
1056
1057 switch (params_format(params)) {
1058 case SNDRV_PCM_FORMAT_U8:
1059 case SNDRV_PCM_FORMAT_S8:
1060 word_length = 8;
1061 break;
1062
1063 case SNDRV_PCM_FORMAT_U16_LE:
1064 case SNDRV_PCM_FORMAT_S16_LE:
1065 word_length = 16;
1066 break;
1067
1068 case SNDRV_PCM_FORMAT_U24_3LE:
1069 case SNDRV_PCM_FORMAT_S24_3LE:
1070 word_length = 24;
1071 break;
1072
1073 case SNDRV_PCM_FORMAT_U24_LE:
1074 case SNDRV_PCM_FORMAT_S24_LE:
1075 word_length = 24;
1076 break;
1077
1078 case SNDRV_PCM_FORMAT_U32_LE:
1079 case SNDRV_PCM_FORMAT_S32_LE:
1080 word_length = 32;
1081 break;
1082
1083 default:
1084 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1085 return -EINVAL;
1086 }
1087
1088 davinci_config_channel_size(mcasp, word_length);
1089
1090 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1091 mcasp->channels = channels;
1092
1093 return 0;
1094 }
1095
1096 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1097 int cmd, struct snd_soc_dai *cpu_dai)
1098 {
1099 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1100 int ret = 0;
1101
1102 switch (cmd) {
1103 case SNDRV_PCM_TRIGGER_RESUME:
1104 case SNDRV_PCM_TRIGGER_START:
1105 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1106 davinci_mcasp_start(mcasp, substream->stream);
1107 break;
1108 case SNDRV_PCM_TRIGGER_SUSPEND:
1109 case SNDRV_PCM_TRIGGER_STOP:
1110 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1111 davinci_mcasp_stop(mcasp, substream->stream);
1112 break;
1113
1114 default:
1115 ret = -EINVAL;
1116 }
1117
1118 return ret;
1119 }
1120
1121 static const unsigned int davinci_mcasp_dai_rates[] = {
1122 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1123 88200, 96000, 176400, 192000,
1124 };
1125
1126 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1127
1128 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1129 struct snd_pcm_hw_rule *rule)
1130 {
1131 struct davinci_mcasp_ruledata *rd = rule->private;
1132 struct snd_interval *ri =
1133 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1134 int sbits = params_width(params);
1135 int slots = rd->mcasp->tdm_slots;
1136 struct snd_interval range;
1137 int i;
1138
1139 if (rd->mcasp->slot_width)
1140 sbits = rd->mcasp->slot_width;
1141
1142 snd_interval_any(&range);
1143 range.empty = 1;
1144
1145 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1146 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1147 uint bclk_freq = sbits*slots*
1148 davinci_mcasp_dai_rates[i];
1149 int ppm;
1150
1151 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1152 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1153 if (range.empty) {
1154 range.min = davinci_mcasp_dai_rates[i];
1155 range.empty = 0;
1156 }
1157 range.max = davinci_mcasp_dai_rates[i];
1158 }
1159 }
1160 }
1161
1162 dev_dbg(rd->mcasp->dev,
1163 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1164 ri->min, ri->max, range.min, range.max, sbits, slots);
1165
1166 return snd_interval_refine(hw_param_interval(params, rule->var),
1167 &range);
1168 }
1169
1170 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1171 struct snd_pcm_hw_rule *rule)
1172 {
1173 struct davinci_mcasp_ruledata *rd = rule->private;
1174 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1175 struct snd_mask nfmt;
1176 int rate = params_rate(params);
1177 int slots = rd->mcasp->tdm_slots;
1178 int i, count = 0;
1179
1180 snd_mask_none(&nfmt);
1181
1182 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1183 if (snd_mask_test(fmt, i)) {
1184 uint sbits = snd_pcm_format_width(i);
1185 int ppm;
1186
1187 if (rd->mcasp->slot_width)
1188 sbits = rd->mcasp->slot_width;
1189
1190 davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
1191 &ppm);
1192 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1193 snd_mask_set(&nfmt, i);
1194 count++;
1195 }
1196 }
1197 }
1198 dev_dbg(rd->mcasp->dev,
1199 "%d possible sample format for %d Hz and %d tdm slots\n",
1200 count, rate, slots);
1201
1202 return snd_mask_refine(fmt, &nfmt);
1203 }
1204
1205 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1206 struct snd_soc_dai *cpu_dai)
1207 {
1208 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1209 struct davinci_mcasp_ruledata *ruledata =
1210 &mcasp->ruledata[substream->stream];
1211 u32 max_channels = 0;
1212 int i, dir;
1213 int tdm_slots = mcasp->tdm_slots;
1214
1215 if (mcasp->tdm_mask[substream->stream])
1216 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1217
1218 mcasp->substreams[substream->stream] = substream;
1219
1220 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1221 return 0;
1222
1223 /*
1224 * Limit the maximum allowed channels for the first stream:
1225 * number of serializers for the direction * tdm slots per serializer
1226 */
1227 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1228 dir = TX_MODE;
1229 else
1230 dir = RX_MODE;
1231
1232 for (i = 0; i < mcasp->num_serializer; i++) {
1233 if (mcasp->serial_dir[i] == dir)
1234 max_channels++;
1235 }
1236 ruledata->serializers = max_channels;
1237 max_channels *= tdm_slots;
1238 /*
1239 * If the already active stream has less channels than the calculated
1240 * limnit based on the seirializers * tdm_slots, we need to use that as
1241 * a constraint for the second stream.
1242 * Otherwise (first stream or less allowed channels) we use the
1243 * calculated constraint.
1244 */
1245 if (mcasp->channels && mcasp->channels < max_channels)
1246 max_channels = mcasp->channels;
1247 /*
1248 * But we can always allow channels upto the amount of
1249 * the available tdm_slots.
1250 */
1251 if (max_channels < tdm_slots)
1252 max_channels = tdm_slots;
1253
1254 snd_pcm_hw_constraint_minmax(substream->runtime,
1255 SNDRV_PCM_HW_PARAM_CHANNELS,
1256 2, max_channels);
1257
1258 snd_pcm_hw_constraint_list(substream->runtime,
1259 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1260 &mcasp->chconstr[substream->stream]);
1261
1262 if (mcasp->slot_width)
1263 snd_pcm_hw_constraint_minmax(substream->runtime,
1264 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1265 8, mcasp->slot_width);
1266
1267 /*
1268 * If we rely on implicit BCLK divider setting we should
1269 * set constraints based on what we can provide.
1270 */
1271 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1272 int ret;
1273
1274 ruledata->mcasp = mcasp;
1275
1276 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1277 SNDRV_PCM_HW_PARAM_RATE,
1278 davinci_mcasp_hw_rule_rate,
1279 ruledata,
1280 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1281 if (ret)
1282 return ret;
1283 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1284 SNDRV_PCM_HW_PARAM_FORMAT,
1285 davinci_mcasp_hw_rule_format,
1286 ruledata,
1287 SNDRV_PCM_HW_PARAM_RATE, -1);
1288 if (ret)
1289 return ret;
1290 }
1291
1292 return 0;
1293 }
1294
1295 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1296 struct snd_soc_dai *cpu_dai)
1297 {
1298 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1299
1300 mcasp->substreams[substream->stream] = NULL;
1301
1302 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1303 return;
1304
1305 if (!cpu_dai->active)
1306 mcasp->channels = 0;
1307 }
1308
1309 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1310 .startup = davinci_mcasp_startup,
1311 .shutdown = davinci_mcasp_shutdown,
1312 .trigger = davinci_mcasp_trigger,
1313 .hw_params = davinci_mcasp_hw_params,
1314 .set_fmt = davinci_mcasp_set_dai_fmt,
1315 .set_clkdiv = davinci_mcasp_set_clkdiv,
1316 .set_sysclk = davinci_mcasp_set_sysclk,
1317 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1318 };
1319
1320 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1321 {
1322 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1323
1324 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1325 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1326
1327 return 0;
1328 }
1329
1330 #ifdef CONFIG_PM_SLEEP
1331 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1332 {
1333 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1334 struct davinci_mcasp_context *context = &mcasp->context;
1335 u32 reg;
1336 int i;
1337
1338 context->pm_state = pm_runtime_active(mcasp->dev);
1339 if (!context->pm_state)
1340 pm_runtime_get_sync(mcasp->dev);
1341
1342 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1343 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1344
1345 if (mcasp->txnumevt) {
1346 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1347 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1348 }
1349 if (mcasp->rxnumevt) {
1350 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1351 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1352 }
1353
1354 for (i = 0; i < mcasp->num_serializer; i++)
1355 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1356 DAVINCI_MCASP_XRSRCTL_REG(i));
1357
1358 pm_runtime_put_sync(mcasp->dev);
1359
1360 return 0;
1361 }
1362
1363 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1364 {
1365 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1366 struct davinci_mcasp_context *context = &mcasp->context;
1367 u32 reg;
1368 int i;
1369
1370 pm_runtime_get_sync(mcasp->dev);
1371
1372 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1373 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1374
1375 if (mcasp->txnumevt) {
1376 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1377 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1378 }
1379 if (mcasp->rxnumevt) {
1380 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1381 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1382 }
1383
1384 for (i = 0; i < mcasp->num_serializer; i++)
1385 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1386 context->xrsr_regs[i]);
1387
1388 if (!context->pm_state)
1389 pm_runtime_put_sync(mcasp->dev);
1390
1391 return 0;
1392 }
1393 #else
1394 #define davinci_mcasp_suspend NULL
1395 #define davinci_mcasp_resume NULL
1396 #endif
1397
1398 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1399
1400 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1401 SNDRV_PCM_FMTBIT_U8 | \
1402 SNDRV_PCM_FMTBIT_S16_LE | \
1403 SNDRV_PCM_FMTBIT_U16_LE | \
1404 SNDRV_PCM_FMTBIT_S24_LE | \
1405 SNDRV_PCM_FMTBIT_U24_LE | \
1406 SNDRV_PCM_FMTBIT_S24_3LE | \
1407 SNDRV_PCM_FMTBIT_U24_3LE | \
1408 SNDRV_PCM_FMTBIT_S32_LE | \
1409 SNDRV_PCM_FMTBIT_U32_LE)
1410
1411 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1412 {
1413 .name = "davinci-mcasp.0",
1414 .probe = davinci_mcasp_dai_probe,
1415 .suspend = davinci_mcasp_suspend,
1416 .resume = davinci_mcasp_resume,
1417 .playback = {
1418 .channels_min = 2,
1419 .channels_max = 32 * 16,
1420 .rates = DAVINCI_MCASP_RATES,
1421 .formats = DAVINCI_MCASP_PCM_FMTS,
1422 },
1423 .capture = {
1424 .channels_min = 2,
1425 .channels_max = 32 * 16,
1426 .rates = DAVINCI_MCASP_RATES,
1427 .formats = DAVINCI_MCASP_PCM_FMTS,
1428 },
1429 .ops = &davinci_mcasp_dai_ops,
1430
1431 .symmetric_samplebits = 1,
1432 .symmetric_rates = 1,
1433 },
1434 {
1435 .name = "davinci-mcasp.1",
1436 .probe = davinci_mcasp_dai_probe,
1437 .playback = {
1438 .channels_min = 1,
1439 .channels_max = 384,
1440 .rates = DAVINCI_MCASP_RATES,
1441 .formats = DAVINCI_MCASP_PCM_FMTS,
1442 },
1443 .ops = &davinci_mcasp_dai_ops,
1444 },
1445
1446 };
1447
1448 static const struct snd_soc_component_driver davinci_mcasp_component = {
1449 .name = "davinci-mcasp",
1450 };
1451
1452 /* Some HW specific values and defaults. The rest is filled in from DT. */
1453 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1454 .tx_dma_offset = 0x400,
1455 .rx_dma_offset = 0x400,
1456 .version = MCASP_VERSION_1,
1457 };
1458
1459 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1460 .tx_dma_offset = 0x2000,
1461 .rx_dma_offset = 0x2000,
1462 .version = MCASP_VERSION_2,
1463 };
1464
1465 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1466 .tx_dma_offset = 0,
1467 .rx_dma_offset = 0,
1468 .version = MCASP_VERSION_3,
1469 };
1470
1471 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1472 .tx_dma_offset = 0x200,
1473 .rx_dma_offset = 0x284,
1474 .version = MCASP_VERSION_4,
1475 };
1476
1477 static const struct of_device_id mcasp_dt_ids[] = {
1478 {
1479 .compatible = "ti,dm646x-mcasp-audio",
1480 .data = &dm646x_mcasp_pdata,
1481 },
1482 {
1483 .compatible = "ti,da830-mcasp-audio",
1484 .data = &da830_mcasp_pdata,
1485 },
1486 {
1487 .compatible = "ti,am33xx-mcasp-audio",
1488 .data = &am33xx_mcasp_pdata,
1489 },
1490 {
1491 .compatible = "ti,dra7-mcasp-audio",
1492 .data = &dra7_mcasp_pdata,
1493 },
1494 { /* sentinel */ }
1495 };
1496 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1497
1498 static int mcasp_reparent_fck(struct platform_device *pdev)
1499 {
1500 struct device_node *node = pdev->dev.of_node;
1501 struct clk *gfclk, *parent_clk;
1502 const char *parent_name;
1503 int ret;
1504
1505 if (!node)
1506 return 0;
1507
1508 parent_name = of_get_property(node, "fck_parent", NULL);
1509 if (!parent_name)
1510 return 0;
1511
1512 gfclk = clk_get(&pdev->dev, "fck");
1513 if (IS_ERR(gfclk)) {
1514 dev_err(&pdev->dev, "failed to get fck\n");
1515 return PTR_ERR(gfclk);
1516 }
1517
1518 parent_clk = clk_get(NULL, parent_name);
1519 if (IS_ERR(parent_clk)) {
1520 dev_err(&pdev->dev, "failed to get parent clock\n");
1521 ret = PTR_ERR(parent_clk);
1522 goto err1;
1523 }
1524
1525 ret = clk_set_parent(gfclk, parent_clk);
1526 if (ret) {
1527 dev_err(&pdev->dev, "failed to reparent fck\n");
1528 goto err2;
1529 }
1530
1531 err2:
1532 clk_put(parent_clk);
1533 err1:
1534 clk_put(gfclk);
1535 return ret;
1536 }
1537
1538 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1539 struct platform_device *pdev)
1540 {
1541 struct device_node *np = pdev->dev.of_node;
1542 struct davinci_mcasp_pdata *pdata = NULL;
1543 const struct of_device_id *match =
1544 of_match_device(mcasp_dt_ids, &pdev->dev);
1545 struct of_phandle_args dma_spec;
1546
1547 const u32 *of_serial_dir32;
1548 u32 val;
1549 int i, ret = 0;
1550
1551 if (pdev->dev.platform_data) {
1552 pdata = pdev->dev.platform_data;
1553 return pdata;
1554 } else if (match) {
1555 pdata = (struct davinci_mcasp_pdata*) match->data;
1556 } else {
1557 /* control shouldn't reach here. something is wrong */
1558 ret = -EINVAL;
1559 goto nodata;
1560 }
1561
1562 ret = of_property_read_u32(np, "op-mode", &val);
1563 if (ret >= 0)
1564 pdata->op_mode = val;
1565
1566 ret = of_property_read_u32(np, "tdm-slots", &val);
1567 if (ret >= 0) {
1568 if (val < 2 || val > 32) {
1569 dev_err(&pdev->dev,
1570 "tdm-slots must be in rage [2-32]\n");
1571 ret = -EINVAL;
1572 goto nodata;
1573 }
1574
1575 pdata->tdm_slots = val;
1576 }
1577
1578 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1579 val /= sizeof(u32);
1580 if (of_serial_dir32) {
1581 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1582 (sizeof(*of_serial_dir) * val),
1583 GFP_KERNEL);
1584 if (!of_serial_dir) {
1585 ret = -ENOMEM;
1586 goto nodata;
1587 }
1588
1589 for (i = 0; i < val; i++)
1590 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1591
1592 pdata->num_serializer = val;
1593 pdata->serial_dir = of_serial_dir;
1594 }
1595
1596 ret = of_property_match_string(np, "dma-names", "tx");
1597 if (ret < 0)
1598 goto nodata;
1599
1600 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1601 &dma_spec);
1602 if (ret < 0)
1603 goto nodata;
1604
1605 pdata->tx_dma_channel = dma_spec.args[0];
1606
1607 /* RX is not valid in DIT mode */
1608 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1609 ret = of_property_match_string(np, "dma-names", "rx");
1610 if (ret < 0)
1611 goto nodata;
1612
1613 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1614 &dma_spec);
1615 if (ret < 0)
1616 goto nodata;
1617
1618 pdata->rx_dma_channel = dma_spec.args[0];
1619 }
1620
1621 ret = of_property_read_u32(np, "tx-num-evt", &val);
1622 if (ret >= 0)
1623 pdata->txnumevt = val;
1624
1625 ret = of_property_read_u32(np, "rx-num-evt", &val);
1626 if (ret >= 0)
1627 pdata->rxnumevt = val;
1628
1629 ret = of_property_read_u32(np, "sram-size-playback", &val);
1630 if (ret >= 0)
1631 pdata->sram_size_playback = val;
1632
1633 ret = of_property_read_u32(np, "sram-size-capture", &val);
1634 if (ret >= 0)
1635 pdata->sram_size_capture = val;
1636
1637 return pdata;
1638
1639 nodata:
1640 if (ret < 0) {
1641 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1642 ret);
1643 pdata = NULL;
1644 }
1645 return pdata;
1646 }
1647
1648 enum {
1649 PCM_EDMA,
1650 PCM_SDMA,
1651 };
1652 static const char *sdma_prefix = "ti,omap";
1653
1654 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1655 {
1656 struct dma_chan *chan;
1657 const char *tmp;
1658 int ret = PCM_EDMA;
1659
1660 if (!mcasp->dev->of_node)
1661 return PCM_EDMA;
1662
1663 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1664 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1665 if (IS_ERR(chan)) {
1666 if (PTR_ERR(chan) != -EPROBE_DEFER)
1667 dev_err(mcasp->dev,
1668 "Can't verify DMA configuration (%ld)\n",
1669 PTR_ERR(chan));
1670 return PTR_ERR(chan);
1671 }
1672 BUG_ON(!chan->device || !chan->device->dev);
1673
1674 if (chan->device->dev->of_node)
1675 ret = of_property_read_string(chan->device->dev->of_node,
1676 "compatible", &tmp);
1677 else
1678 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1679
1680 dma_release_channel(chan);
1681 if (ret)
1682 return ret;
1683
1684 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1685 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1686 return PCM_SDMA;
1687
1688 return PCM_EDMA;
1689 }
1690
1691 static int davinci_mcasp_probe(struct platform_device *pdev)
1692 {
1693 struct snd_dmaengine_dai_dma_data *dma_data;
1694 struct resource *mem, *res, *dat;
1695 struct davinci_mcasp_pdata *pdata;
1696 struct davinci_mcasp *mcasp;
1697 char *irq_name;
1698 int *dma;
1699 int irq;
1700 int ret;
1701
1702 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1703 dev_err(&pdev->dev, "No platform data supplied\n");
1704 return -EINVAL;
1705 }
1706
1707 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1708 GFP_KERNEL);
1709 if (!mcasp)
1710 return -ENOMEM;
1711
1712 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1713 if (!pdata) {
1714 dev_err(&pdev->dev, "no platform data\n");
1715 return -EINVAL;
1716 }
1717
1718 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1719 if (!mem) {
1720 dev_warn(mcasp->dev,
1721 "\"mpu\" mem resource not found, using index 0\n");
1722 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1723 if (!mem) {
1724 dev_err(&pdev->dev, "no mem resource?\n");
1725 return -ENODEV;
1726 }
1727 }
1728
1729 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1730 if (IS_ERR(mcasp->base))
1731 return PTR_ERR(mcasp->base);
1732
1733 pm_runtime_enable(&pdev->dev);
1734
1735 mcasp->op_mode = pdata->op_mode;
1736 /* sanity check for tdm slots parameter */
1737 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1738 if (pdata->tdm_slots < 2) {
1739 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1740 pdata->tdm_slots);
1741 mcasp->tdm_slots = 2;
1742 } else if (pdata->tdm_slots > 32) {
1743 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1744 pdata->tdm_slots);
1745 mcasp->tdm_slots = 32;
1746 } else {
1747 mcasp->tdm_slots = pdata->tdm_slots;
1748 }
1749 }
1750
1751 mcasp->num_serializer = pdata->num_serializer;
1752 #ifdef CONFIG_PM_SLEEP
1753 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1754 sizeof(u32) * mcasp->num_serializer,
1755 GFP_KERNEL);
1756 #endif
1757 mcasp->serial_dir = pdata->serial_dir;
1758 mcasp->version = pdata->version;
1759 mcasp->txnumevt = pdata->txnumevt;
1760 mcasp->rxnumevt = pdata->rxnumevt;
1761
1762 mcasp->dev = &pdev->dev;
1763
1764 irq = platform_get_irq_byname(pdev, "common");
1765 if (irq >= 0) {
1766 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1767 dev_name(&pdev->dev));
1768 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1769 davinci_mcasp_common_irq_handler,
1770 IRQF_ONESHOT | IRQF_SHARED,
1771 irq_name, mcasp);
1772 if (ret) {
1773 dev_err(&pdev->dev, "common IRQ request failed\n");
1774 goto err;
1775 }
1776
1777 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1778 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1779 }
1780
1781 irq = platform_get_irq_byname(pdev, "rx");
1782 if (irq >= 0) {
1783 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1784 dev_name(&pdev->dev));
1785 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1786 davinci_mcasp_rx_irq_handler,
1787 IRQF_ONESHOT, irq_name, mcasp);
1788 if (ret) {
1789 dev_err(&pdev->dev, "RX IRQ request failed\n");
1790 goto err;
1791 }
1792
1793 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1794 }
1795
1796 irq = platform_get_irq_byname(pdev, "tx");
1797 if (irq >= 0) {
1798 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1799 dev_name(&pdev->dev));
1800 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1801 davinci_mcasp_tx_irq_handler,
1802 IRQF_ONESHOT, irq_name, mcasp);
1803 if (ret) {
1804 dev_err(&pdev->dev, "TX IRQ request failed\n");
1805 goto err;
1806 }
1807
1808 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1809 }
1810
1811 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1812 if (dat)
1813 mcasp->dat_port = true;
1814
1815 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1816 if (dat)
1817 dma_data->addr = dat->start;
1818 else
1819 dma_data->addr = mem->start + pdata->tx_dma_offset;
1820
1821 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1822 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1823 if (res)
1824 *dma = res->start;
1825 else
1826 *dma = pdata->tx_dma_channel;
1827
1828 /* dmaengine filter data for DT and non-DT boot */
1829 if (pdev->dev.of_node)
1830 dma_data->filter_data = "tx";
1831 else
1832 dma_data->filter_data = dma;
1833
1834 /* RX is not valid in DIT mode */
1835 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1836 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1837 if (dat)
1838 dma_data->addr = dat->start;
1839 else
1840 dma_data->addr = mem->start + pdata->rx_dma_offset;
1841
1842 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1843 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1844 if (res)
1845 *dma = res->start;
1846 else
1847 *dma = pdata->rx_dma_channel;
1848
1849 /* dmaengine filter data for DT and non-DT boot */
1850 if (pdev->dev.of_node)
1851 dma_data->filter_data = "rx";
1852 else
1853 dma_data->filter_data = dma;
1854 }
1855
1856 if (mcasp->version < MCASP_VERSION_3) {
1857 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1858 /* dma_params->dma_addr is pointing to the data port address */
1859 mcasp->dat_port = true;
1860 } else {
1861 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1862 }
1863
1864 /* Allocate memory for long enough list for all possible
1865 * scenarios. Maximum number tdm slots is 32 and there cannot
1866 * be more serializers than given in the configuration. The
1867 * serializer directions could be taken into account, but it
1868 * would make code much more complex and save only couple of
1869 * bytes.
1870 */
1871 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1872 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1873 (32 + mcasp->num_serializer - 2),
1874 GFP_KERNEL);
1875
1876 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
1877 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1878 (32 + mcasp->num_serializer - 2),
1879 GFP_KERNEL);
1880
1881 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1882 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
1883 return -ENOMEM;
1884
1885 ret = davinci_mcasp_set_ch_constraints(mcasp);
1886 if (ret)
1887 goto err;
1888
1889 dev_set_drvdata(&pdev->dev, mcasp);
1890
1891 mcasp_reparent_fck(pdev);
1892
1893 ret = devm_snd_soc_register_component(&pdev->dev,
1894 &davinci_mcasp_component,
1895 &davinci_mcasp_dai[pdata->op_mode], 1);
1896
1897 if (ret != 0)
1898 goto err;
1899
1900 ret = davinci_mcasp_get_dma_type(mcasp);
1901 switch (ret) {
1902 case PCM_EDMA:
1903 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1904 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1905 IS_MODULE(CONFIG_SND_EDMA_SOC))
1906 ret = edma_pcm_platform_register(&pdev->dev);
1907 #else
1908 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
1909 ret = -EINVAL;
1910 goto err;
1911 #endif
1912 break;
1913 case PCM_SDMA:
1914 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1915 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1916 IS_MODULE(CONFIG_SND_OMAP_SOC))
1917 ret = omap_pcm_platform_register(&pdev->dev);
1918 #else
1919 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
1920 ret = -EINVAL;
1921 goto err;
1922 #endif
1923 break;
1924 default:
1925 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
1926 case -EPROBE_DEFER:
1927 goto err;
1928 break;
1929 }
1930
1931 if (ret) {
1932 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1933 goto err;
1934 }
1935
1936 return 0;
1937
1938 err:
1939 pm_runtime_disable(&pdev->dev);
1940 return ret;
1941 }
1942
1943 static int davinci_mcasp_remove(struct platform_device *pdev)
1944 {
1945 pm_runtime_disable(&pdev->dev);
1946
1947 return 0;
1948 }
1949
1950 static struct platform_driver davinci_mcasp_driver = {
1951 .probe = davinci_mcasp_probe,
1952 .remove = davinci_mcasp_remove,
1953 .driver = {
1954 .name = "davinci-mcasp",
1955 .of_match_table = mcasp_dt_ids,
1956 },
1957 };
1958
1959 module_platform_driver(davinci_mcasp_driver);
1960
1961 MODULE_AUTHOR("Steve Chen");
1962 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1963 MODULE_LICENSE("GPL");
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