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ASoC: fsl_esai: fix channel swap issue when stream starts
[mirror_ubuntu-bionic-kernel.git] / sound / soc / fsl / fsl_esai.c
1 /*
2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18
19 #include "fsl_esai.h"
20 #include "imx-pcm.h"
21
22 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
23 SNDRV_PCM_FMTBIT_S16_LE | \
24 SNDRV_PCM_FMTBIT_S20_3LE | \
25 SNDRV_PCM_FMTBIT_S24_LE)
26
27 /**
28 * fsl_esai: ESAI private data
29 *
30 * @dma_params_rx: DMA parameters for receive channel
31 * @dma_params_tx: DMA parameters for transmit channel
32 * @pdev: platform device pointer
33 * @regmap: regmap handler
34 * @coreclk: clock source to access register
35 * @extalclk: esai clock source to derive HCK, SCK and FS
36 * @fsysclk: system clock source to derive HCK, SCK and FS
37 * @spbaclk: SPBA clock (optional, depending on SoC design)
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @slots: number of slots
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
47 * @name: driver name
48 */
49 struct fsl_esai {
50 struct snd_dmaengine_dai_dma_data dma_params_rx;
51 struct snd_dmaengine_dai_dma_data dma_params_tx;
52 struct platform_device *pdev;
53 struct regmap *regmap;
54 struct clk *coreclk;
55 struct clk *extalclk;
56 struct clk *fsysclk;
57 struct clk *spbaclk;
58 u32 fifo_depth;
59 u32 slot_width;
60 u32 slots;
61 u32 tx_mask;
62 u32 rx_mask;
63 u32 hck_rate[2];
64 u32 sck_rate[2];
65 bool hck_dir[2];
66 bool sck_div[2];
67 bool slave_mode;
68 bool synchronous;
69 char name[32];
70 };
71
72 static irqreturn_t esai_isr(int irq, void *devid)
73 {
74 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
75 struct platform_device *pdev = esai_priv->pdev;
76 u32 esr;
77
78 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
79
80 if (esr & ESAI_ESR_TINIT_MASK)
81 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
82
83 if (esr & ESAI_ESR_RFF_MASK)
84 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
85
86 if (esr & ESAI_ESR_TFE_MASK)
87 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
88
89 if (esr & ESAI_ESR_TLS_MASK)
90 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
91
92 if (esr & ESAI_ESR_TDE_MASK)
93 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
94
95 if (esr & ESAI_ESR_TED_MASK)
96 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
97
98 if (esr & ESAI_ESR_TD_MASK)
99 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
100
101 if (esr & ESAI_ESR_RLS_MASK)
102 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
103
104 if (esr & ESAI_ESR_RDE_MASK)
105 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
106
107 if (esr & ESAI_ESR_RED_MASK)
108 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
109
110 if (esr & ESAI_ESR_RD_MASK)
111 dev_dbg(&pdev->dev, "isr: Receiving data\n");
112
113 return IRQ_HANDLED;
114 }
115
116 /**
117 * This function is used to calculate the divisors of psr, pm, fp and it is
118 * supposed to be called in set_dai_sysclk() and set_bclk().
119 *
120 * @ratio: desired overall ratio for the paticipating dividers
121 * @usefp: for HCK setting, there is no need to set fp divider
122 * @fp: bypass other dividers by setting fp directly if fp != 0
123 * @tx: current setting is for playback or capture
124 */
125 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
126 bool usefp, u32 fp)
127 {
128 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
129 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
130
131 maxfp = usefp ? 16 : 1;
132
133 if (usefp && fp)
134 goto out_fp;
135
136 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
137 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
138 2 * 8 * 256 * maxfp);
139 return -EINVAL;
140 } else if (ratio % 2) {
141 dev_err(dai->dev, "the raio must be even if using upper divider\n");
142 return -EINVAL;
143 }
144
145 ratio /= 2;
146
147 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
148
149 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
150 if (ratio <= 256) {
151 pm = ratio;
152 fp = 1;
153 goto out;
154 }
155
156 /* Set the max fluctuation -- 0.1% of the max devisor */
157 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
158
159 /* Find the best value for PM */
160 for (i = 1; i <= 256; i++) {
161 for (j = 1; j <= maxfp; j++) {
162 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
163 prod = (psr ? 1 : 8) * i * j;
164
165 if (prod == ratio)
166 sub = 0;
167 else if (prod / ratio == 1)
168 sub = prod - ratio;
169 else if (ratio / prod == 1)
170 sub = ratio - prod;
171 else
172 continue;
173
174 /* Calculate the fraction */
175 sub = sub * 1000 / ratio;
176 if (sub < savesub) {
177 savesub = sub;
178 pm = i;
179 fp = j;
180 }
181
182 /* We are lucky */
183 if (savesub == 0)
184 goto out;
185 }
186 }
187
188 if (pm == 999) {
189 dev_err(dai->dev, "failed to calculate proper divisors\n");
190 return -EINVAL;
191 }
192
193 out:
194 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
195 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
196 psr | ESAI_xCCR_xPM(pm));
197
198 out_fp:
199 /* Bypass fp if not being required */
200 if (maxfp <= 1)
201 return 0;
202
203 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
204 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
205
206 return 0;
207 }
208
209 /**
210 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
211 *
212 * @Parameters:
213 * clk_id: The clock source of HCKT/HCKR
214 * (Input from outside; output from inside, FSYS or EXTAL)
215 * freq: The required clock rate of HCKT/HCKR
216 * dir: The clock direction of HCKT/HCKR
217 *
218 * Note: If the direction is input, we do not care about clk_id.
219 */
220 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
221 unsigned int freq, int dir)
222 {
223 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
224 struct clk *clksrc = esai_priv->extalclk;
225 bool tx = clk_id <= ESAI_HCKT_EXTAL;
226 bool in = dir == SND_SOC_CLOCK_IN;
227 u32 ratio, ecr = 0;
228 unsigned long clk_rate;
229 int ret;
230
231 /* Bypass divider settings if the requirement doesn't change */
232 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
233 return 0;
234
235 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
236 esai_priv->sck_div[tx] = true;
237
238 /* Set the direction of HCKT/HCKR pins */
239 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
240 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
241
242 if (in)
243 goto out;
244
245 switch (clk_id) {
246 case ESAI_HCKT_FSYS:
247 case ESAI_HCKR_FSYS:
248 clksrc = esai_priv->fsysclk;
249 break;
250 case ESAI_HCKT_EXTAL:
251 ecr |= ESAI_ECR_ETI;
252 case ESAI_HCKR_EXTAL:
253 ecr |= ESAI_ECR_ERI;
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 if (IS_ERR(clksrc)) {
260 dev_err(dai->dev, "no assigned %s clock\n",
261 clk_id % 2 ? "extal" : "fsys");
262 return PTR_ERR(clksrc);
263 }
264 clk_rate = clk_get_rate(clksrc);
265
266 ratio = clk_rate / freq;
267 if (ratio * freq > clk_rate)
268 ret = ratio * freq - clk_rate;
269 else if (ratio * freq < clk_rate)
270 ret = clk_rate - ratio * freq;
271 else
272 ret = 0;
273
274 /* Block if clock source can not be divided into the required rate */
275 if (ret != 0 && clk_rate / ret < 1000) {
276 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
277 tx ? 'T' : 'R');
278 return -EINVAL;
279 }
280
281 /* Only EXTAL source can be output directly without using PSR and PM */
282 if (ratio == 1 && clksrc == esai_priv->extalclk) {
283 /* Bypass all the dividers if not being needed */
284 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
285 goto out;
286 } else if (ratio < 2) {
287 /* The ratio should be no less than 2 if using other sources */
288 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
289 tx ? 'T' : 'R');
290 return -EINVAL;
291 }
292
293 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
294 if (ret)
295 return ret;
296
297 esai_priv->sck_div[tx] = false;
298
299 out:
300 esai_priv->hck_dir[tx] = dir;
301 esai_priv->hck_rate[tx] = freq;
302
303 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
304 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
305 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
306
307 return 0;
308 }
309
310 /**
311 * This function configures the related dividers according to the bclk rate
312 */
313 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
314 {
315 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
316 u32 hck_rate = esai_priv->hck_rate[tx];
317 u32 sub, ratio = hck_rate / freq;
318 int ret;
319
320 /* Don't apply for fully slave mode or unchanged bclk */
321 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
322 return 0;
323
324 if (ratio * freq > hck_rate)
325 sub = ratio * freq - hck_rate;
326 else if (ratio * freq < hck_rate)
327 sub = hck_rate - ratio * freq;
328 else
329 sub = 0;
330
331 /* Block if clock source can not be divided into the required rate */
332 if (sub != 0 && hck_rate / sub < 1000) {
333 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
334 tx ? 'T' : 'R');
335 return -EINVAL;
336 }
337
338 /* The ratio should be contented by FP alone if bypassing PM and PSR */
339 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
340 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
341 return -EINVAL;
342 }
343
344 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
345 esai_priv->sck_div[tx] ? 0 : ratio);
346 if (ret)
347 return ret;
348
349 /* Save current bclk rate */
350 esai_priv->sck_rate[tx] = freq;
351
352 return 0;
353 }
354
355 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
356 u32 rx_mask, int slots, int slot_width)
357 {
358 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
359
360 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
361 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
362
363 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
364 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
365
366 esai_priv->slot_width = slot_width;
367 esai_priv->slots = slots;
368 esai_priv->tx_mask = tx_mask;
369 esai_priv->rx_mask = rx_mask;
370
371 return 0;
372 }
373
374 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
375 {
376 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
377 u32 xcr = 0, xccr = 0, mask;
378
379 /* DAI mode */
380 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
381 case SND_SOC_DAIFMT_I2S:
382 /* Data on rising edge of bclk, frame low, 1clk before data */
383 xcr |= ESAI_xCR_xFSR;
384 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
385 break;
386 case SND_SOC_DAIFMT_LEFT_J:
387 /* Data on rising edge of bclk, frame high */
388 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
389 break;
390 case SND_SOC_DAIFMT_RIGHT_J:
391 /* Data on rising edge of bclk, frame high, right aligned */
392 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
393 xcr |= ESAI_xCR_xWA;
394 break;
395 case SND_SOC_DAIFMT_DSP_A:
396 /* Data on rising edge of bclk, frame high, 1clk before data */
397 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
398 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
399 break;
400 case SND_SOC_DAIFMT_DSP_B:
401 /* Data on rising edge of bclk, frame high */
402 xcr |= ESAI_xCR_xFSL;
403 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
404 break;
405 default:
406 return -EINVAL;
407 }
408
409 /* DAI clock inversion */
410 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
411 case SND_SOC_DAIFMT_NB_NF:
412 /* Nothing to do for both normal cases */
413 break;
414 case SND_SOC_DAIFMT_IB_NF:
415 /* Invert bit clock */
416 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
417 break;
418 case SND_SOC_DAIFMT_NB_IF:
419 /* Invert frame clock */
420 xccr ^= ESAI_xCCR_xFSP;
421 break;
422 case SND_SOC_DAIFMT_IB_IF:
423 /* Invert both clocks */
424 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
425 break;
426 default:
427 return -EINVAL;
428 }
429
430 esai_priv->slave_mode = false;
431
432 /* DAI clock master masks */
433 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
434 case SND_SOC_DAIFMT_CBM_CFM:
435 esai_priv->slave_mode = true;
436 break;
437 case SND_SOC_DAIFMT_CBS_CFM:
438 xccr |= ESAI_xCCR_xCKD;
439 break;
440 case SND_SOC_DAIFMT_CBM_CFS:
441 xccr |= ESAI_xCCR_xFSD;
442 break;
443 case SND_SOC_DAIFMT_CBS_CFS:
444 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
445 break;
446 default:
447 return -EINVAL;
448 }
449
450 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
451 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
452 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
453
454 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
455 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
456 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
457 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
458
459 return 0;
460 }
461
462 static int fsl_esai_startup(struct snd_pcm_substream *substream,
463 struct snd_soc_dai *dai)
464 {
465 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
466 int ret;
467
468 /*
469 * Some platforms might use the same bit to gate all three or two of
470 * clocks, so keep all clocks open/close at the same time for safety
471 */
472 ret = clk_prepare_enable(esai_priv->coreclk);
473 if (ret)
474 return ret;
475 if (!IS_ERR(esai_priv->spbaclk)) {
476 ret = clk_prepare_enable(esai_priv->spbaclk);
477 if (ret)
478 goto err_spbaclk;
479 }
480 if (!IS_ERR(esai_priv->extalclk)) {
481 ret = clk_prepare_enable(esai_priv->extalclk);
482 if (ret)
483 goto err_extalck;
484 }
485 if (!IS_ERR(esai_priv->fsysclk)) {
486 ret = clk_prepare_enable(esai_priv->fsysclk);
487 if (ret)
488 goto err_fsysclk;
489 }
490
491 if (!dai->active) {
492 /* Set synchronous mode */
493 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
494 ESAI_SAICR_SYNC, esai_priv->synchronous ?
495 ESAI_SAICR_SYNC : 0);
496
497 /* Set a default slot number -- 2 */
498 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
499 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
500 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
501 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
502 }
503
504 return 0;
505
506 err_fsysclk:
507 if (!IS_ERR(esai_priv->extalclk))
508 clk_disable_unprepare(esai_priv->extalclk);
509 err_extalck:
510 if (!IS_ERR(esai_priv->spbaclk))
511 clk_disable_unprepare(esai_priv->spbaclk);
512 err_spbaclk:
513 clk_disable_unprepare(esai_priv->coreclk);
514
515 return ret;
516 }
517
518 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
519 struct snd_pcm_hw_params *params,
520 struct snd_soc_dai *dai)
521 {
522 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
523 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
524 u32 width = params_width(params);
525 u32 channels = params_channels(params);
526 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
527 u32 slot_width = width;
528 u32 bclk, mask, val;
529 int ret;
530
531 /* Override slot_width if being specifically set */
532 if (esai_priv->slot_width)
533 slot_width = esai_priv->slot_width;
534
535 bclk = params_rate(params) * slot_width * esai_priv->slots;
536
537 ret = fsl_esai_set_bclk(dai, tx, bclk);
538 if (ret)
539 return ret;
540
541 /* Use Normal mode to support monaural audio */
542 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
543 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
544 ESAI_xCR_xMOD_NETWORK : 0);
545
546 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
547 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
548
549 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
550 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
551 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
552 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
553
554 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
555
556 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
557 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
558
559 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
560
561 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
562 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
563 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
564 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
565 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
566 return 0;
567 }
568
569 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
570 struct snd_soc_dai *dai)
571 {
572 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
573
574 if (!IS_ERR(esai_priv->fsysclk))
575 clk_disable_unprepare(esai_priv->fsysclk);
576 if (!IS_ERR(esai_priv->extalclk))
577 clk_disable_unprepare(esai_priv->extalclk);
578 if (!IS_ERR(esai_priv->spbaclk))
579 clk_disable_unprepare(esai_priv->spbaclk);
580 clk_disable_unprepare(esai_priv->coreclk);
581 }
582
583 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
584 struct snd_soc_dai *dai)
585 {
586 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
587 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
588 u8 i, channels = substream->runtime->channels;
589 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
590 u32 mask;
591
592 switch (cmd) {
593 case SNDRV_PCM_TRIGGER_START:
594 case SNDRV_PCM_TRIGGER_RESUME:
595 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
596 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
597 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
598
599 /* Write initial words reqiured by ESAI as normal procedure */
600 for (i = 0; tx && i < channels; i++)
601 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
602
603 /*
604 * When set the TE/RE in the end of enablement flow, there
605 * will be channel swap issue for multi data line case.
606 * In order to workaround this issue, we switch the bit
607 * enablement sequence to below sequence
608 * 1) clear the xSMB & xSMA: which is done in probe and
609 * stop state.
610 * 2) set TE/RE
611 * 3) set xSMB
612 * 4) set xSMA: xSMA is the last one in this flow, which
613 * will trigger esai to start.
614 */
615 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
616 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
617 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
618 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
619
620 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
621 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
622 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
623 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
624
625 break;
626 case SNDRV_PCM_TRIGGER_SUSPEND:
627 case SNDRV_PCM_TRIGGER_STOP:
628 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
629 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
630 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
631 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
632 ESAI_xSMA_xS_MASK, 0);
633 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
634 ESAI_xSMB_xS_MASK, 0);
635
636 /* Disable and reset FIFO */
637 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
638 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
639 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
640 ESAI_xFCR_xFR, 0);
641 break;
642 default:
643 return -EINVAL;
644 }
645
646 return 0;
647 }
648
649 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
650 .startup = fsl_esai_startup,
651 .shutdown = fsl_esai_shutdown,
652 .trigger = fsl_esai_trigger,
653 .hw_params = fsl_esai_hw_params,
654 .set_sysclk = fsl_esai_set_dai_sysclk,
655 .set_fmt = fsl_esai_set_dai_fmt,
656 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
657 };
658
659 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
660 {
661 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
662
663 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
664 &esai_priv->dma_params_rx);
665
666 return 0;
667 }
668
669 static struct snd_soc_dai_driver fsl_esai_dai = {
670 .probe = fsl_esai_dai_probe,
671 .playback = {
672 .stream_name = "CPU-Playback",
673 .channels_min = 1,
674 .channels_max = 12,
675 .rates = SNDRV_PCM_RATE_8000_192000,
676 .formats = FSL_ESAI_FORMATS,
677 },
678 .capture = {
679 .stream_name = "CPU-Capture",
680 .channels_min = 1,
681 .channels_max = 8,
682 .rates = SNDRV_PCM_RATE_8000_192000,
683 .formats = FSL_ESAI_FORMATS,
684 },
685 .ops = &fsl_esai_dai_ops,
686 };
687
688 static const struct snd_soc_component_driver fsl_esai_component = {
689 .name = "fsl-esai",
690 };
691
692 static const struct reg_default fsl_esai_reg_defaults[] = {
693 {REG_ESAI_ETDR, 0x00000000},
694 {REG_ESAI_ECR, 0x00000000},
695 {REG_ESAI_TFCR, 0x00000000},
696 {REG_ESAI_RFCR, 0x00000000},
697 {REG_ESAI_TX0, 0x00000000},
698 {REG_ESAI_TX1, 0x00000000},
699 {REG_ESAI_TX2, 0x00000000},
700 {REG_ESAI_TX3, 0x00000000},
701 {REG_ESAI_TX4, 0x00000000},
702 {REG_ESAI_TX5, 0x00000000},
703 {REG_ESAI_TSR, 0x00000000},
704 {REG_ESAI_SAICR, 0x00000000},
705 {REG_ESAI_TCR, 0x00000000},
706 {REG_ESAI_TCCR, 0x00000000},
707 {REG_ESAI_RCR, 0x00000000},
708 {REG_ESAI_RCCR, 0x00000000},
709 {REG_ESAI_TSMA, 0x0000ffff},
710 {REG_ESAI_TSMB, 0x0000ffff},
711 {REG_ESAI_RSMA, 0x0000ffff},
712 {REG_ESAI_RSMB, 0x0000ffff},
713 {REG_ESAI_PRRC, 0x00000000},
714 {REG_ESAI_PCRC, 0x00000000},
715 };
716
717 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
718 {
719 switch (reg) {
720 case REG_ESAI_ERDR:
721 case REG_ESAI_ECR:
722 case REG_ESAI_ESR:
723 case REG_ESAI_TFCR:
724 case REG_ESAI_TFSR:
725 case REG_ESAI_RFCR:
726 case REG_ESAI_RFSR:
727 case REG_ESAI_RX0:
728 case REG_ESAI_RX1:
729 case REG_ESAI_RX2:
730 case REG_ESAI_RX3:
731 case REG_ESAI_SAISR:
732 case REG_ESAI_SAICR:
733 case REG_ESAI_TCR:
734 case REG_ESAI_TCCR:
735 case REG_ESAI_RCR:
736 case REG_ESAI_RCCR:
737 case REG_ESAI_TSMA:
738 case REG_ESAI_TSMB:
739 case REG_ESAI_RSMA:
740 case REG_ESAI_RSMB:
741 case REG_ESAI_PRRC:
742 case REG_ESAI_PCRC:
743 return true;
744 default:
745 return false;
746 }
747 }
748
749 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
750 {
751 switch (reg) {
752 case REG_ESAI_ERDR:
753 case REG_ESAI_ESR:
754 case REG_ESAI_TFSR:
755 case REG_ESAI_RFSR:
756 case REG_ESAI_RX0:
757 case REG_ESAI_RX1:
758 case REG_ESAI_RX2:
759 case REG_ESAI_RX3:
760 case REG_ESAI_SAISR:
761 return true;
762 default:
763 return false;
764 }
765 }
766
767 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
768 {
769 switch (reg) {
770 case REG_ESAI_ETDR:
771 case REG_ESAI_ECR:
772 case REG_ESAI_TFCR:
773 case REG_ESAI_RFCR:
774 case REG_ESAI_TX0:
775 case REG_ESAI_TX1:
776 case REG_ESAI_TX2:
777 case REG_ESAI_TX3:
778 case REG_ESAI_TX4:
779 case REG_ESAI_TX5:
780 case REG_ESAI_TSR:
781 case REG_ESAI_SAICR:
782 case REG_ESAI_TCR:
783 case REG_ESAI_TCCR:
784 case REG_ESAI_RCR:
785 case REG_ESAI_RCCR:
786 case REG_ESAI_TSMA:
787 case REG_ESAI_TSMB:
788 case REG_ESAI_RSMA:
789 case REG_ESAI_RSMB:
790 case REG_ESAI_PRRC:
791 case REG_ESAI_PCRC:
792 return true;
793 default:
794 return false;
795 }
796 }
797
798 static const struct regmap_config fsl_esai_regmap_config = {
799 .reg_bits = 32,
800 .reg_stride = 4,
801 .val_bits = 32,
802
803 .max_register = REG_ESAI_PCRC,
804 .reg_defaults = fsl_esai_reg_defaults,
805 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
806 .readable_reg = fsl_esai_readable_reg,
807 .volatile_reg = fsl_esai_volatile_reg,
808 .writeable_reg = fsl_esai_writeable_reg,
809 .cache_type = REGCACHE_FLAT,
810 };
811
812 static int fsl_esai_probe(struct platform_device *pdev)
813 {
814 struct device_node *np = pdev->dev.of_node;
815 struct fsl_esai *esai_priv;
816 struct resource *res;
817 const uint32_t *iprop;
818 void __iomem *regs;
819 int irq, ret;
820
821 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
822 if (!esai_priv)
823 return -ENOMEM;
824
825 esai_priv->pdev = pdev;
826 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
827
828 /* Get the addresses and IRQ */
829 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
830 regs = devm_ioremap_resource(&pdev->dev, res);
831 if (IS_ERR(regs))
832 return PTR_ERR(regs);
833
834 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
835 "core", regs, &fsl_esai_regmap_config);
836 if (IS_ERR(esai_priv->regmap)) {
837 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
838 PTR_ERR(esai_priv->regmap));
839 return PTR_ERR(esai_priv->regmap);
840 }
841
842 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
843 if (IS_ERR(esai_priv->coreclk)) {
844 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
845 PTR_ERR(esai_priv->coreclk));
846 return PTR_ERR(esai_priv->coreclk);
847 }
848
849 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
850 if (IS_ERR(esai_priv->extalclk))
851 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
852 PTR_ERR(esai_priv->extalclk));
853
854 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
855 if (IS_ERR(esai_priv->fsysclk))
856 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
857 PTR_ERR(esai_priv->fsysclk));
858
859 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
860 if (IS_ERR(esai_priv->spbaclk))
861 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
862 PTR_ERR(esai_priv->spbaclk));
863
864 irq = platform_get_irq(pdev, 0);
865 if (irq < 0) {
866 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
867 return irq;
868 }
869
870 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
871 esai_priv->name, esai_priv);
872 if (ret) {
873 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
874 return ret;
875 }
876
877 /* Set a default slot number */
878 esai_priv->slots = 2;
879
880 /* Set a default master/slave state */
881 esai_priv->slave_mode = true;
882
883 /* Determine the FIFO depth */
884 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
885 if (iprop)
886 esai_priv->fifo_depth = be32_to_cpup(iprop);
887 else
888 esai_priv->fifo_depth = 64;
889
890 esai_priv->dma_params_tx.maxburst = 16;
891 esai_priv->dma_params_rx.maxburst = 16;
892 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
893 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
894
895 esai_priv->synchronous =
896 of_property_read_bool(np, "fsl,esai-synchronous");
897
898 /* Implement full symmetry for synchronous mode */
899 if (esai_priv->synchronous) {
900 fsl_esai_dai.symmetric_rates = 1;
901 fsl_esai_dai.symmetric_channels = 1;
902 fsl_esai_dai.symmetric_samplebits = 1;
903 }
904
905 dev_set_drvdata(&pdev->dev, esai_priv);
906
907 /* Reset ESAI unit */
908 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
909 if (ret) {
910 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
911 return ret;
912 }
913
914 /*
915 * We need to enable ESAI so as to access some of its registers.
916 * Otherwise, we would fail to dump regmap from user space.
917 */
918 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
919 if (ret) {
920 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
921 return ret;
922 }
923
924 esai_priv->tx_mask = 0xFFFFFFFF;
925 esai_priv->rx_mask = 0xFFFFFFFF;
926
927 /* Clear the TSMA, TSMB, RSMA, RSMB */
928 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
929 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
930 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
931 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
932
933 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
934 &fsl_esai_dai, 1);
935 if (ret) {
936 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
937 return ret;
938 }
939
940 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
941 if (ret)
942 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
943
944 return ret;
945 }
946
947 static const struct of_device_id fsl_esai_dt_ids[] = {
948 { .compatible = "fsl,imx35-esai", },
949 { .compatible = "fsl,vf610-esai", },
950 {}
951 };
952 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
953
954 #ifdef CONFIG_PM_SLEEP
955 static int fsl_esai_suspend(struct device *dev)
956 {
957 struct fsl_esai *esai = dev_get_drvdata(dev);
958
959 regcache_cache_only(esai->regmap, true);
960 regcache_mark_dirty(esai->regmap);
961
962 return 0;
963 }
964
965 static int fsl_esai_resume(struct device *dev)
966 {
967 struct fsl_esai *esai = dev_get_drvdata(dev);
968 int ret;
969
970 regcache_cache_only(esai->regmap, false);
971
972 /* FIFO reset for safety */
973 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
974 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
975 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
976 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
977
978 ret = regcache_sync(esai->regmap);
979 if (ret)
980 return ret;
981
982 /* FIFO reset done */
983 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
984 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
985
986 return 0;
987 }
988 #endif /* CONFIG_PM_SLEEP */
989
990 static const struct dev_pm_ops fsl_esai_pm_ops = {
991 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
992 };
993
994 static struct platform_driver fsl_esai_driver = {
995 .probe = fsl_esai_probe,
996 .driver = {
997 .name = "fsl-esai-dai",
998 .pm = &fsl_esai_pm_ops,
999 .of_match_table = fsl_esai_dt_ids,
1000 },
1001 };
1002
1003 module_platform_driver(fsl_esai_driver);
1004
1005 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1006 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1007 MODULE_LICENSE("GPL v2");
1008 MODULE_ALIAS("platform:fsl-esai-dai");
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