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[mirror_ubuntu-bionic-kernel.git] / sound / soc / fsl / fsl_esai.c
1 /*
2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
18
19 #include "fsl_esai.h"
20 #include "imx-pcm.h"
21
22 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
23 SNDRV_PCM_FMTBIT_S16_LE | \
24 SNDRV_PCM_FMTBIT_S20_3LE | \
25 SNDRV_PCM_FMTBIT_S24_LE)
26
27 /**
28 * fsl_esai: ESAI private data
29 *
30 * @dma_params_rx: DMA parameters for receive channel
31 * @dma_params_tx: DMA parameters for transmit channel
32 * @pdev: platform device pointer
33 * @regmap: regmap handler
34 * @coreclk: clock source to access register
35 * @extalclk: esai clock source to derive HCK, SCK and FS
36 * @fsysclk: system clock source to derive HCK, SCK and FS
37 * @spbaclk: SPBA clock (optional, depending on SoC design)
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @slots: number of slots
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
47 * @name: driver name
48 */
49 struct fsl_esai {
50 struct snd_dmaengine_dai_dma_data dma_params_rx;
51 struct snd_dmaengine_dai_dma_data dma_params_tx;
52 struct platform_device *pdev;
53 struct regmap *regmap;
54 struct clk *coreclk;
55 struct clk *extalclk;
56 struct clk *fsysclk;
57 struct clk *spbaclk;
58 u32 fifo_depth;
59 u32 slot_width;
60 u32 slots;
61 u32 hck_rate[2];
62 u32 sck_rate[2];
63 bool hck_dir[2];
64 bool sck_div[2];
65 bool slave_mode;
66 bool synchronous;
67 char name[32];
68 };
69
70 static irqreturn_t esai_isr(int irq, void *devid)
71 {
72 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
73 struct platform_device *pdev = esai_priv->pdev;
74 u32 esr;
75
76 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
77
78 if (esr & ESAI_ESR_TINIT_MASK)
79 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
80
81 if (esr & ESAI_ESR_RFF_MASK)
82 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
83
84 if (esr & ESAI_ESR_TFE_MASK)
85 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
86
87 if (esr & ESAI_ESR_TLS_MASK)
88 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
89
90 if (esr & ESAI_ESR_TDE_MASK)
91 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
92
93 if (esr & ESAI_ESR_TED_MASK)
94 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
95
96 if (esr & ESAI_ESR_TD_MASK)
97 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
98
99 if (esr & ESAI_ESR_RLS_MASK)
100 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
101
102 if (esr & ESAI_ESR_RDE_MASK)
103 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
104
105 if (esr & ESAI_ESR_RED_MASK)
106 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
107
108 if (esr & ESAI_ESR_RD_MASK)
109 dev_dbg(&pdev->dev, "isr: Receiving data\n");
110
111 return IRQ_HANDLED;
112 }
113
114 /**
115 * This function is used to calculate the divisors of psr, pm, fp and it is
116 * supposed to be called in set_dai_sysclk() and set_bclk().
117 *
118 * @ratio: desired overall ratio for the paticipating dividers
119 * @usefp: for HCK setting, there is no need to set fp divider
120 * @fp: bypass other dividers by setting fp directly if fp != 0
121 * @tx: current setting is for playback or capture
122 */
123 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
124 bool usefp, u32 fp)
125 {
126 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
127 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
128
129 maxfp = usefp ? 16 : 1;
130
131 if (usefp && fp)
132 goto out_fp;
133
134 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
135 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
136 2 * 8 * 256 * maxfp);
137 return -EINVAL;
138 } else if (ratio % 2) {
139 dev_err(dai->dev, "the raio must be even if using upper divider\n");
140 return -EINVAL;
141 }
142
143 ratio /= 2;
144
145 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
146
147 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
148 if (ratio <= 256) {
149 pm = ratio;
150 fp = 1;
151 goto out;
152 }
153
154 /* Set the max fluctuation -- 0.1% of the max devisor */
155 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
156
157 /* Find the best value for PM */
158 for (i = 1; i <= 256; i++) {
159 for (j = 1; j <= maxfp; j++) {
160 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
161 prod = (psr ? 1 : 8) * i * j;
162
163 if (prod == ratio)
164 sub = 0;
165 else if (prod / ratio == 1)
166 sub = prod - ratio;
167 else if (ratio / prod == 1)
168 sub = ratio - prod;
169 else
170 continue;
171
172 /* Calculate the fraction */
173 sub = sub * 1000 / ratio;
174 if (sub < savesub) {
175 savesub = sub;
176 pm = i;
177 fp = j;
178 }
179
180 /* We are lucky */
181 if (savesub == 0)
182 goto out;
183 }
184 }
185
186 if (pm == 999) {
187 dev_err(dai->dev, "failed to calculate proper divisors\n");
188 return -EINVAL;
189 }
190
191 out:
192 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
193 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
194 psr | ESAI_xCCR_xPM(pm));
195
196 out_fp:
197 /* Bypass fp if not being required */
198 if (maxfp <= 1)
199 return 0;
200
201 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
202 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
203
204 return 0;
205 }
206
207 /**
208 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
209 *
210 * @Parameters:
211 * clk_id: The clock source of HCKT/HCKR
212 * (Input from outside; output from inside, FSYS or EXTAL)
213 * freq: The required clock rate of HCKT/HCKR
214 * dir: The clock direction of HCKT/HCKR
215 *
216 * Note: If the direction is input, we do not care about clk_id.
217 */
218 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
219 unsigned int freq, int dir)
220 {
221 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
222 struct clk *clksrc = esai_priv->extalclk;
223 bool tx = clk_id <= ESAI_HCKT_EXTAL;
224 bool in = dir == SND_SOC_CLOCK_IN;
225 u32 ratio, ecr = 0;
226 unsigned long clk_rate;
227 int ret;
228
229 /* Bypass divider settings if the requirement doesn't change */
230 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
231 return 0;
232
233 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
234 esai_priv->sck_div[tx] = true;
235
236 /* Set the direction of HCKT/HCKR pins */
237 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
238 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
239
240 if (in)
241 goto out;
242
243 switch (clk_id) {
244 case ESAI_HCKT_FSYS:
245 case ESAI_HCKR_FSYS:
246 clksrc = esai_priv->fsysclk;
247 break;
248 case ESAI_HCKT_EXTAL:
249 ecr |= ESAI_ECR_ETI;
250 case ESAI_HCKR_EXTAL:
251 ecr |= ESAI_ECR_ERI;
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 if (IS_ERR(clksrc)) {
258 dev_err(dai->dev, "no assigned %s clock\n",
259 clk_id % 2 ? "extal" : "fsys");
260 return PTR_ERR(clksrc);
261 }
262 clk_rate = clk_get_rate(clksrc);
263
264 ratio = clk_rate / freq;
265 if (ratio * freq > clk_rate)
266 ret = ratio * freq - clk_rate;
267 else if (ratio * freq < clk_rate)
268 ret = clk_rate - ratio * freq;
269 else
270 ret = 0;
271
272 /* Block if clock source can not be divided into the required rate */
273 if (ret != 0 && clk_rate / ret < 1000) {
274 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
275 tx ? 'T' : 'R');
276 return -EINVAL;
277 }
278
279 /* Only EXTAL source can be output directly without using PSR and PM */
280 if (ratio == 1 && clksrc == esai_priv->extalclk) {
281 /* Bypass all the dividers if not being needed */
282 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
283 goto out;
284 } else if (ratio < 2) {
285 /* The ratio should be no less than 2 if using other sources */
286 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
287 tx ? 'T' : 'R');
288 return -EINVAL;
289 }
290
291 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
292 if (ret)
293 return ret;
294
295 esai_priv->sck_div[tx] = false;
296
297 out:
298 esai_priv->hck_dir[tx] = dir;
299 esai_priv->hck_rate[tx] = freq;
300
301 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
302 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
303 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
304
305 return 0;
306 }
307
308 /**
309 * This function configures the related dividers according to the bclk rate
310 */
311 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
312 {
313 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
314 u32 hck_rate = esai_priv->hck_rate[tx];
315 u32 sub, ratio = hck_rate / freq;
316 int ret;
317
318 /* Don't apply for fully slave mode or unchanged bclk */
319 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
320 return 0;
321
322 if (ratio * freq > hck_rate)
323 sub = ratio * freq - hck_rate;
324 else if (ratio * freq < hck_rate)
325 sub = hck_rate - ratio * freq;
326 else
327 sub = 0;
328
329 /* Block if clock source can not be divided into the required rate */
330 if (sub != 0 && hck_rate / sub < 1000) {
331 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
332 tx ? 'T' : 'R');
333 return -EINVAL;
334 }
335
336 /* The ratio should be contented by FP alone if bypassing PM and PSR */
337 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
338 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
339 return -EINVAL;
340 }
341
342 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
343 esai_priv->sck_div[tx] ? 0 : ratio);
344 if (ret)
345 return ret;
346
347 /* Save current bclk rate */
348 esai_priv->sck_rate[tx] = freq;
349
350 return 0;
351 }
352
353 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
354 u32 rx_mask, int slots, int slot_width)
355 {
356 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
357
358 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
359 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
360
361 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
362 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
363 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
364 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
365
366 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
367 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
368
369 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
370 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
371 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
372 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
373
374 esai_priv->slot_width = slot_width;
375 esai_priv->slots = slots;
376
377 return 0;
378 }
379
380 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
381 {
382 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
383 u32 xcr = 0, xccr = 0, mask;
384
385 /* DAI mode */
386 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
387 case SND_SOC_DAIFMT_I2S:
388 /* Data on rising edge of bclk, frame low, 1clk before data */
389 xcr |= ESAI_xCR_xFSR;
390 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
391 break;
392 case SND_SOC_DAIFMT_LEFT_J:
393 /* Data on rising edge of bclk, frame high */
394 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
395 break;
396 case SND_SOC_DAIFMT_RIGHT_J:
397 /* Data on rising edge of bclk, frame high, right aligned */
398 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
399 xcr |= ESAI_xCR_xWA;
400 break;
401 case SND_SOC_DAIFMT_DSP_A:
402 /* Data on rising edge of bclk, frame high, 1clk before data */
403 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
404 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
405 break;
406 case SND_SOC_DAIFMT_DSP_B:
407 /* Data on rising edge of bclk, frame high */
408 xcr |= ESAI_xCR_xFSL;
409 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
410 break;
411 default:
412 return -EINVAL;
413 }
414
415 /* DAI clock inversion */
416 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
417 case SND_SOC_DAIFMT_NB_NF:
418 /* Nothing to do for both normal cases */
419 break;
420 case SND_SOC_DAIFMT_IB_NF:
421 /* Invert bit clock */
422 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
423 break;
424 case SND_SOC_DAIFMT_NB_IF:
425 /* Invert frame clock */
426 xccr ^= ESAI_xCCR_xFSP;
427 break;
428 case SND_SOC_DAIFMT_IB_IF:
429 /* Invert both clocks */
430 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 esai_priv->slave_mode = false;
437
438 /* DAI clock master masks */
439 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
440 case SND_SOC_DAIFMT_CBM_CFM:
441 esai_priv->slave_mode = true;
442 break;
443 case SND_SOC_DAIFMT_CBS_CFM:
444 xccr |= ESAI_xCCR_xCKD;
445 break;
446 case SND_SOC_DAIFMT_CBM_CFS:
447 xccr |= ESAI_xCCR_xFSD;
448 break;
449 case SND_SOC_DAIFMT_CBS_CFS:
450 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
451 break;
452 default:
453 return -EINVAL;
454 }
455
456 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
457 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
458 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
459
460 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
461 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
462 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
463 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
464
465 return 0;
466 }
467
468 static int fsl_esai_startup(struct snd_pcm_substream *substream,
469 struct snd_soc_dai *dai)
470 {
471 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
472 int ret;
473
474 /*
475 * Some platforms might use the same bit to gate all three or two of
476 * clocks, so keep all clocks open/close at the same time for safety
477 */
478 ret = clk_prepare_enable(esai_priv->coreclk);
479 if (ret)
480 return ret;
481 if (!IS_ERR(esai_priv->spbaclk)) {
482 ret = clk_prepare_enable(esai_priv->spbaclk);
483 if (ret)
484 goto err_spbaclk;
485 }
486 if (!IS_ERR(esai_priv->extalclk)) {
487 ret = clk_prepare_enable(esai_priv->extalclk);
488 if (ret)
489 goto err_extalck;
490 }
491 if (!IS_ERR(esai_priv->fsysclk)) {
492 ret = clk_prepare_enable(esai_priv->fsysclk);
493 if (ret)
494 goto err_fsysclk;
495 }
496
497 if (!dai->active) {
498 /* Set synchronous mode */
499 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
500 ESAI_SAICR_SYNC, esai_priv->synchronous ?
501 ESAI_SAICR_SYNC : 0);
502
503 /* Set a default slot number -- 2 */
504 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
505 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
506 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
507 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
508 }
509
510 return 0;
511
512 err_fsysclk:
513 if (!IS_ERR(esai_priv->extalclk))
514 clk_disable_unprepare(esai_priv->extalclk);
515 err_extalck:
516 if (!IS_ERR(esai_priv->spbaclk))
517 clk_disable_unprepare(esai_priv->spbaclk);
518 err_spbaclk:
519 clk_disable_unprepare(esai_priv->coreclk);
520
521 return ret;
522 }
523
524 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
525 struct snd_pcm_hw_params *params,
526 struct snd_soc_dai *dai)
527 {
528 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
529 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
530 u32 width = params_width(params);
531 u32 channels = params_channels(params);
532 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
533 u32 slot_width = width;
534 u32 bclk, mask, val;
535 int ret;
536
537 /* Override slot_width if being specifically set */
538 if (esai_priv->slot_width)
539 slot_width = esai_priv->slot_width;
540
541 bclk = params_rate(params) * slot_width * esai_priv->slots;
542
543 ret = fsl_esai_set_bclk(dai, tx, bclk);
544 if (ret)
545 return ret;
546
547 /* Use Normal mode to support monaural audio */
548 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
549 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
550 ESAI_xCR_xMOD_NETWORK : 0);
551
552 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
553 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
554
555 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
556 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
557 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
558 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
559
560 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
561
562 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
563 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
564
565 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
566
567 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
568 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
569 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
570 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
571 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
572 return 0;
573 }
574
575 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
576 struct snd_soc_dai *dai)
577 {
578 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
579
580 if (!IS_ERR(esai_priv->fsysclk))
581 clk_disable_unprepare(esai_priv->fsysclk);
582 if (!IS_ERR(esai_priv->extalclk))
583 clk_disable_unprepare(esai_priv->extalclk);
584 if (!IS_ERR(esai_priv->spbaclk))
585 clk_disable_unprepare(esai_priv->spbaclk);
586 clk_disable_unprepare(esai_priv->coreclk);
587 }
588
589 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
590 struct snd_soc_dai *dai)
591 {
592 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
593 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
594 u8 i, channels = substream->runtime->channels;
595 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
596
597 switch (cmd) {
598 case SNDRV_PCM_TRIGGER_START:
599 case SNDRV_PCM_TRIGGER_RESUME:
600 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
601 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
602 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
603
604 /* Write initial words reqiured by ESAI as normal procedure */
605 for (i = 0; tx && i < channels; i++)
606 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
607
608 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
609 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
610 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
611 break;
612 case SNDRV_PCM_TRIGGER_SUSPEND:
613 case SNDRV_PCM_TRIGGER_STOP:
614 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
615 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
616 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
617
618 /* Disable and reset FIFO */
619 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
620 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
621 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
622 ESAI_xFCR_xFR, 0);
623 break;
624 default:
625 return -EINVAL;
626 }
627
628 return 0;
629 }
630
631 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
632 .startup = fsl_esai_startup,
633 .shutdown = fsl_esai_shutdown,
634 .trigger = fsl_esai_trigger,
635 .hw_params = fsl_esai_hw_params,
636 .set_sysclk = fsl_esai_set_dai_sysclk,
637 .set_fmt = fsl_esai_set_dai_fmt,
638 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
639 };
640
641 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
642 {
643 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
644
645 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
646 &esai_priv->dma_params_rx);
647
648 return 0;
649 }
650
651 static struct snd_soc_dai_driver fsl_esai_dai = {
652 .probe = fsl_esai_dai_probe,
653 .playback = {
654 .stream_name = "CPU-Playback",
655 .channels_min = 1,
656 .channels_max = 12,
657 .rates = SNDRV_PCM_RATE_8000_192000,
658 .formats = FSL_ESAI_FORMATS,
659 },
660 .capture = {
661 .stream_name = "CPU-Capture",
662 .channels_min = 1,
663 .channels_max = 8,
664 .rates = SNDRV_PCM_RATE_8000_192000,
665 .formats = FSL_ESAI_FORMATS,
666 },
667 .ops = &fsl_esai_dai_ops,
668 };
669
670 static const struct snd_soc_component_driver fsl_esai_component = {
671 .name = "fsl-esai",
672 };
673
674 static const struct reg_default fsl_esai_reg_defaults[] = {
675 {REG_ESAI_ETDR, 0x00000000},
676 {REG_ESAI_ECR, 0x00000000},
677 {REG_ESAI_TFCR, 0x00000000},
678 {REG_ESAI_RFCR, 0x00000000},
679 {REG_ESAI_TX0, 0x00000000},
680 {REG_ESAI_TX1, 0x00000000},
681 {REG_ESAI_TX2, 0x00000000},
682 {REG_ESAI_TX3, 0x00000000},
683 {REG_ESAI_TX4, 0x00000000},
684 {REG_ESAI_TX5, 0x00000000},
685 {REG_ESAI_TSR, 0x00000000},
686 {REG_ESAI_SAICR, 0x00000000},
687 {REG_ESAI_TCR, 0x00000000},
688 {REG_ESAI_TCCR, 0x00000000},
689 {REG_ESAI_RCR, 0x00000000},
690 {REG_ESAI_RCCR, 0x00000000},
691 {REG_ESAI_TSMA, 0x0000ffff},
692 {REG_ESAI_TSMB, 0x0000ffff},
693 {REG_ESAI_RSMA, 0x0000ffff},
694 {REG_ESAI_RSMB, 0x0000ffff},
695 {REG_ESAI_PRRC, 0x00000000},
696 {REG_ESAI_PCRC, 0x00000000},
697 };
698
699 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
700 {
701 switch (reg) {
702 case REG_ESAI_ERDR:
703 case REG_ESAI_ECR:
704 case REG_ESAI_ESR:
705 case REG_ESAI_TFCR:
706 case REG_ESAI_TFSR:
707 case REG_ESAI_RFCR:
708 case REG_ESAI_RFSR:
709 case REG_ESAI_RX0:
710 case REG_ESAI_RX1:
711 case REG_ESAI_RX2:
712 case REG_ESAI_RX3:
713 case REG_ESAI_SAISR:
714 case REG_ESAI_SAICR:
715 case REG_ESAI_TCR:
716 case REG_ESAI_TCCR:
717 case REG_ESAI_RCR:
718 case REG_ESAI_RCCR:
719 case REG_ESAI_TSMA:
720 case REG_ESAI_TSMB:
721 case REG_ESAI_RSMA:
722 case REG_ESAI_RSMB:
723 case REG_ESAI_PRRC:
724 case REG_ESAI_PCRC:
725 return true;
726 default:
727 return false;
728 }
729 }
730
731 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
732 {
733 switch (reg) {
734 case REG_ESAI_ERDR:
735 case REG_ESAI_ESR:
736 case REG_ESAI_TFSR:
737 case REG_ESAI_RFSR:
738 case REG_ESAI_RX0:
739 case REG_ESAI_RX1:
740 case REG_ESAI_RX2:
741 case REG_ESAI_RX3:
742 case REG_ESAI_SAISR:
743 return true;
744 default:
745 return false;
746 }
747 }
748
749 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
750 {
751 switch (reg) {
752 case REG_ESAI_ETDR:
753 case REG_ESAI_ECR:
754 case REG_ESAI_TFCR:
755 case REG_ESAI_RFCR:
756 case REG_ESAI_TX0:
757 case REG_ESAI_TX1:
758 case REG_ESAI_TX2:
759 case REG_ESAI_TX3:
760 case REG_ESAI_TX4:
761 case REG_ESAI_TX5:
762 case REG_ESAI_TSR:
763 case REG_ESAI_SAICR:
764 case REG_ESAI_TCR:
765 case REG_ESAI_TCCR:
766 case REG_ESAI_RCR:
767 case REG_ESAI_RCCR:
768 case REG_ESAI_TSMA:
769 case REG_ESAI_TSMB:
770 case REG_ESAI_RSMA:
771 case REG_ESAI_RSMB:
772 case REG_ESAI_PRRC:
773 case REG_ESAI_PCRC:
774 return true;
775 default:
776 return false;
777 }
778 }
779
780 static const struct regmap_config fsl_esai_regmap_config = {
781 .reg_bits = 32,
782 .reg_stride = 4,
783 .val_bits = 32,
784
785 .max_register = REG_ESAI_PCRC,
786 .reg_defaults = fsl_esai_reg_defaults,
787 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
788 .readable_reg = fsl_esai_readable_reg,
789 .volatile_reg = fsl_esai_volatile_reg,
790 .writeable_reg = fsl_esai_writeable_reg,
791 .cache_type = REGCACHE_FLAT,
792 };
793
794 static int fsl_esai_probe(struct platform_device *pdev)
795 {
796 struct device_node *np = pdev->dev.of_node;
797 struct fsl_esai *esai_priv;
798 struct resource *res;
799 const uint32_t *iprop;
800 void __iomem *regs;
801 int irq, ret;
802
803 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
804 if (!esai_priv)
805 return -ENOMEM;
806
807 esai_priv->pdev = pdev;
808 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
809
810 /* Get the addresses and IRQ */
811 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
812 regs = devm_ioremap_resource(&pdev->dev, res);
813 if (IS_ERR(regs))
814 return PTR_ERR(regs);
815
816 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
817 "core", regs, &fsl_esai_regmap_config);
818 if (IS_ERR(esai_priv->regmap)) {
819 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
820 PTR_ERR(esai_priv->regmap));
821 return PTR_ERR(esai_priv->regmap);
822 }
823
824 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
825 if (IS_ERR(esai_priv->coreclk)) {
826 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
827 PTR_ERR(esai_priv->coreclk));
828 return PTR_ERR(esai_priv->coreclk);
829 }
830
831 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
832 if (IS_ERR(esai_priv->extalclk))
833 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
834 PTR_ERR(esai_priv->extalclk));
835
836 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
837 if (IS_ERR(esai_priv->fsysclk))
838 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
839 PTR_ERR(esai_priv->fsysclk));
840
841 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
842 if (IS_ERR(esai_priv->spbaclk))
843 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
844 PTR_ERR(esai_priv->spbaclk));
845
846 irq = platform_get_irq(pdev, 0);
847 if (irq < 0) {
848 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
849 return irq;
850 }
851
852 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
853 esai_priv->name, esai_priv);
854 if (ret) {
855 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
856 return ret;
857 }
858
859 /* Set a default slot number */
860 esai_priv->slots = 2;
861
862 /* Set a default master/slave state */
863 esai_priv->slave_mode = true;
864
865 /* Determine the FIFO depth */
866 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
867 if (iprop)
868 esai_priv->fifo_depth = be32_to_cpup(iprop);
869 else
870 esai_priv->fifo_depth = 64;
871
872 esai_priv->dma_params_tx.maxburst = 16;
873 esai_priv->dma_params_rx.maxburst = 16;
874 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
875 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
876
877 esai_priv->synchronous =
878 of_property_read_bool(np, "fsl,esai-synchronous");
879
880 /* Implement full symmetry for synchronous mode */
881 if (esai_priv->synchronous) {
882 fsl_esai_dai.symmetric_rates = 1;
883 fsl_esai_dai.symmetric_channels = 1;
884 fsl_esai_dai.symmetric_samplebits = 1;
885 }
886
887 dev_set_drvdata(&pdev->dev, esai_priv);
888
889 /* Reset ESAI unit */
890 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
891 if (ret) {
892 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
893 return ret;
894 }
895
896 /*
897 * We need to enable ESAI so as to access some of its registers.
898 * Otherwise, we would fail to dump regmap from user space.
899 */
900 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
901 if (ret) {
902 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
903 return ret;
904 }
905
906 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
907 &fsl_esai_dai, 1);
908 if (ret) {
909 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
910 return ret;
911 }
912
913 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
914 if (ret)
915 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
916
917 return ret;
918 }
919
920 static const struct of_device_id fsl_esai_dt_ids[] = {
921 { .compatible = "fsl,imx35-esai", },
922 { .compatible = "fsl,vf610-esai", },
923 {}
924 };
925 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
926
927 #ifdef CONFIG_PM_SLEEP
928 static int fsl_esai_suspend(struct device *dev)
929 {
930 struct fsl_esai *esai = dev_get_drvdata(dev);
931
932 regcache_cache_only(esai->regmap, true);
933 regcache_mark_dirty(esai->regmap);
934
935 return 0;
936 }
937
938 static int fsl_esai_resume(struct device *dev)
939 {
940 struct fsl_esai *esai = dev_get_drvdata(dev);
941 int ret;
942
943 regcache_cache_only(esai->regmap, false);
944
945 /* FIFO reset for safety */
946 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
947 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
948 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
949 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
950
951 ret = regcache_sync(esai->regmap);
952 if (ret)
953 return ret;
954
955 /* FIFO reset done */
956 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
957 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
958
959 return 0;
960 }
961 #endif /* CONFIG_PM_SLEEP */
962
963 static const struct dev_pm_ops fsl_esai_pm_ops = {
964 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
965 };
966
967 static struct platform_driver fsl_esai_driver = {
968 .probe = fsl_esai_probe,
969 .driver = {
970 .name = "fsl-esai-dai",
971 .pm = &fsl_esai_pm_ops,
972 .of_match_table = fsl_esai_dt_ids,
973 },
974 };
975
976 module_platform_driver(fsl_esai_driver);
977
978 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
979 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
980 MODULE_LICENSE("GPL v2");
981 MODULE_ALIAS("platform:fsl-esai-dai");
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