2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * The SSI has a limitation in that the samples must be in the same byte
71 * order as the host CPU. This is because when multiple bytes are written
72 * to the STX register, the bytes and bits must be written in the same
73 * order. The STX is a shift register, so all the bits need to be aligned
74 * (bit-endianness must match byte-endianness). Processors typically write
75 * the bits within a byte in the same order that the bytes of a word are
76 * written in. So if the host CPU is big-endian, then only big-endian
77 * samples will be written to STX properly.
80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
103 struct fsl_ssi_reg_val
{
110 struct fsl_ssi_rxtx_reg_val
{
111 struct fsl_ssi_reg_val rx
;
112 struct fsl_ssi_reg_val tx
;
115 static const struct reg_default fsl_ssi_reg_defaults
[] = {
129 static bool fsl_ssi_readable_reg(struct device
*dev
, unsigned int reg
)
132 case CCSR_SSI_SACCEN
:
133 case CCSR_SSI_SACCDIS
:
140 static bool fsl_ssi_volatile_reg(struct device
*dev
, unsigned int reg
)
149 case CCSR_SSI_SACADD
:
150 case CCSR_SSI_SACDAT
:
152 case CCSR_SSI_SACCST
:
159 static bool fsl_ssi_writeable_reg(struct device
*dev
, unsigned int reg
)
164 case CCSR_SSI_SACCST
:
171 static const struct regmap_config fsl_ssi_regconfig
= {
172 .max_register
= CCSR_SSI_SACCDIS
,
176 .val_format_endian
= REGMAP_ENDIAN_NATIVE
,
177 .reg_defaults
= fsl_ssi_reg_defaults
,
178 .num_reg_defaults
= ARRAY_SIZE(fsl_ssi_reg_defaults
),
179 .readable_reg
= fsl_ssi_readable_reg
,
180 .volatile_reg
= fsl_ssi_volatile_reg
,
181 .writeable_reg
= fsl_ssi_writeable_reg
,
182 .cache_type
= REGCACHE_RBTREE
,
185 struct fsl_ssi_soc_data
{
192 * fsl_ssi_private: per-SSI private data
194 * @reg: Pointer to the regmap registers
195 * @irq: IRQ of this SSI
196 * @cpu_dai_drv: CPU DAI driver for this device
198 * @dai_fmt: DAI configuration this device is currently used with
199 * @i2s_mode: i2s and network mode configuration of the device. Is used to
200 * switch between normal and i2s/network mode
201 * mode depending on the number of channels
202 * @use_dma: DMA is used or FIQ with stream filter
203 * @use_dual_fifo: DMA with support for both FIFOs used
204 * @fifo_deph: Depth of the SSI FIFOs
205 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
208 * @baudclk: SSI baud clock for master mode
209 * @baudclk_streams: Active streams that are using baudclk
210 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
212 * @dma_params_tx: DMA transmit parameters
213 * @dma_params_rx: DMA receive parameters
214 * @ssi_phys: physical address of the SSI registers
216 * @fiq_params: FIQ stream filtering parameters
218 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
220 * @dbg_stats: Debugging statistics
222 * @soc: SoC specific data
224 struct fsl_ssi_private
{
227 struct snd_soc_dai_driver cpu_dai_drv
;
229 unsigned int dai_fmt
;
233 bool has_ipg_clk_name
;
234 unsigned int fifo_depth
;
235 struct fsl_ssi_rxtx_reg_val rxtx_reg_val
;
239 unsigned int baudclk_streams
;
240 unsigned int bitclk_freq
;
242 /*regcache for SFCSR*/
246 struct snd_dmaengine_dai_dma_data dma_params_tx
;
247 struct snd_dmaengine_dai_dma_data dma_params_rx
;
250 /* params for non-dma FIQ stream filtered mode */
251 struct imx_pcm_fiq_params fiq_params
;
253 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
254 * should be replaced with simple-sound-card. */
255 struct platform_device
*pdev
;
257 struct fsl_ssi_dbg dbg_stats
;
259 const struct fsl_ssi_soc_data
*soc
;
263 * imx51 and later SoCs have a slightly different IP that allows the
264 * SSI configuration while the SSI unit is running.
266 * More important, it is necessary on those SoCs to configure the
267 * sperate TX/RX DMA bits just before starting the stream
268 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
269 * sends any DMA requests to the SDMA unit, otherwise it is not defined
270 * how the SDMA unit handles the DMA request.
272 * SDMA units are present on devices starting at imx35 but the imx35
273 * reference manual states that the DMA bits should not be changed
274 * while the SSI unit is running (SSIEN). So we support the necessary
275 * online configuration of fsl-ssi starting at imx51.
278 static struct fsl_ssi_soc_data fsl_ssi_mpc8610
= {
280 .offline_config
= true,
281 .sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
282 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
283 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
286 static struct fsl_ssi_soc_data fsl_ssi_imx21
= {
288 .offline_config
= true,
289 .sisr_write_mask
= 0,
292 static struct fsl_ssi_soc_data fsl_ssi_imx35
= {
294 .offline_config
= true,
295 .sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
296 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
297 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
300 static struct fsl_ssi_soc_data fsl_ssi_imx51
= {
302 .offline_config
= false,
303 .sisr_write_mask
= CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
304 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
307 static const struct of_device_id fsl_ssi_ids
[] = {
308 { .compatible
= "fsl,mpc8610-ssi", .data
= &fsl_ssi_mpc8610
},
309 { .compatible
= "fsl,imx51-ssi", .data
= &fsl_ssi_imx51
},
310 { .compatible
= "fsl,imx35-ssi", .data
= &fsl_ssi_imx35
},
311 { .compatible
= "fsl,imx21-ssi", .data
= &fsl_ssi_imx21
},
314 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
316 static bool fsl_ssi_is_ac97(struct fsl_ssi_private
*ssi_private
)
318 return !!(ssi_private
->dai_fmt
& SND_SOC_DAIFMT_AC97
);
321 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private
*ssi_private
)
323 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_MASTER_MASK
) ==
324 SND_SOC_DAIFMT_CBS_CFS
;
327 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private
*ssi_private
)
329 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_MASTER_MASK
) ==
330 SND_SOC_DAIFMT_CBM_CFS
;
333 * fsl_ssi_isr: SSI interrupt handler
335 * Although it's possible to use the interrupt handler to send and receive
336 * data to/from the SSI, we use the DMA instead. Programming is more
337 * complicated, but the performance is much better.
339 * This interrupt handler is used only to gather statistics.
341 * @irq: IRQ of the SSI device
342 * @dev_id: pointer to the ssi_private structure for this SSI device
344 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
346 struct fsl_ssi_private
*ssi_private
= dev_id
;
347 struct regmap
*regs
= ssi_private
->regs
;
351 /* We got an interrupt, so read the status register to see what we
352 were interrupted for. We mask it with the Interrupt Enable register
353 so that we only check for events that we're interested in.
355 regmap_read(regs
, CCSR_SSI_SISR
, &sisr
);
357 sisr2
= sisr
& ssi_private
->soc
->sisr_write_mask
;
358 /* Clear the bits that we set */
360 regmap_write(regs
, CCSR_SSI_SISR
, sisr2
);
362 fsl_ssi_dbg_isr(&ssi_private
->dbg_stats
, sisr
);
368 * Enable/Disable all rx/tx config flags at once.
370 static void fsl_ssi_rxtx_config(struct fsl_ssi_private
*ssi_private
,
373 struct regmap
*regs
= ssi_private
->regs
;
374 struct fsl_ssi_rxtx_reg_val
*vals
= &ssi_private
->rxtx_reg_val
;
377 regmap_update_bits(regs
, CCSR_SSI_SIER
,
378 vals
->rx
.sier
| vals
->tx
.sier
,
379 vals
->rx
.sier
| vals
->tx
.sier
);
380 regmap_update_bits(regs
, CCSR_SSI_SRCR
,
381 vals
->rx
.srcr
| vals
->tx
.srcr
,
382 vals
->rx
.srcr
| vals
->tx
.srcr
);
383 regmap_update_bits(regs
, CCSR_SSI_STCR
,
384 vals
->rx
.stcr
| vals
->tx
.stcr
,
385 vals
->rx
.stcr
| vals
->tx
.stcr
);
387 regmap_update_bits(regs
, CCSR_SSI_SRCR
,
388 vals
->rx
.srcr
| vals
->tx
.srcr
, 0);
389 regmap_update_bits(regs
, CCSR_SSI_STCR
,
390 vals
->rx
.stcr
| vals
->tx
.stcr
, 0);
391 regmap_update_bits(regs
, CCSR_SSI_SIER
,
392 vals
->rx
.sier
| vals
->tx
.sier
, 0);
397 * Calculate the bits that have to be disabled for the current stream that is
398 * getting disabled. This keeps the bits enabled that are necessary for the
399 * second stream to work if 'stream_active' is true.
401 * Detailed calculation:
402 * These are the values that need to be active after disabling. For non-active
403 * second stream, this is 0:
404 * vals_stream * !!stream_active
406 * The following computes the overall differences between the setup for the
407 * to-disable stream and the active stream, a simple XOR:
408 * vals_disable ^ (vals_stream * !!(stream_active))
410 * The full expression adds a mask on all values we care about
412 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
414 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
417 * Enable/Disable a ssi configuration. You have to pass either
418 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
420 static void fsl_ssi_config(struct fsl_ssi_private
*ssi_private
, bool enable
,
421 struct fsl_ssi_reg_val
*vals
)
423 struct regmap
*regs
= ssi_private
->regs
;
424 struct fsl_ssi_reg_val
*avals
;
425 int nr_active_streams
;
429 regmap_read(regs
, CCSR_SSI_SCR
, &scr_val
);
431 nr_active_streams
= !!(scr_val
& CCSR_SSI_SCR_TE
) +
432 !!(scr_val
& CCSR_SSI_SCR_RE
);
434 if (nr_active_streams
- 1 > 0)
439 /* Find the other direction values rx or tx which we do not want to
441 if (&ssi_private
->rxtx_reg_val
.rx
== vals
)
442 avals
= &ssi_private
->rxtx_reg_val
.tx
;
444 avals
= &ssi_private
->rxtx_reg_val
.rx
;
446 /* If vals should be disabled, start with disabling the unit */
448 u32 scr
= fsl_ssi_disable_val(vals
->scr
, avals
->scr
,
450 regmap_update_bits(regs
, CCSR_SSI_SCR
, scr
, 0);
454 * We are running on a SoC which does not support online SSI
455 * reconfiguration, so we have to enable all necessary flags at once
456 * even if we do not use them later (capture and playback configuration)
458 if (ssi_private
->soc
->offline_config
) {
459 if ((enable
&& !nr_active_streams
) ||
460 (!enable
&& !keep_active
))
461 fsl_ssi_rxtx_config(ssi_private
, enable
);
467 * Configure single direction units while the SSI unit is running
468 * (online configuration)
471 regmap_update_bits(regs
, CCSR_SSI_SIER
, vals
->sier
, vals
->sier
);
472 regmap_update_bits(regs
, CCSR_SSI_SRCR
, vals
->srcr
, vals
->srcr
);
473 regmap_update_bits(regs
, CCSR_SSI_STCR
, vals
->stcr
, vals
->stcr
);
480 * Disabling the necessary flags for one of rx/tx while the
481 * other stream is active is a little bit more difficult. We
482 * have to disable only those flags that differ between both
483 * streams (rx XOR tx) and that are set in the stream that is
484 * disabled now. Otherwise we could alter flags of the other
488 /* These assignments are simply vals without bits set in avals*/
489 sier
= fsl_ssi_disable_val(vals
->sier
, avals
->sier
,
491 srcr
= fsl_ssi_disable_val(vals
->srcr
, avals
->srcr
,
493 stcr
= fsl_ssi_disable_val(vals
->stcr
, avals
->stcr
,
496 regmap_update_bits(regs
, CCSR_SSI_SRCR
, srcr
, 0);
497 regmap_update_bits(regs
, CCSR_SSI_STCR
, stcr
, 0);
498 regmap_update_bits(regs
, CCSR_SSI_SIER
, sier
, 0);
502 /* Enabling of subunits is done after configuration */
504 regmap_update_bits(regs
, CCSR_SSI_SCR
, vals
->scr
, vals
->scr
);
508 static void fsl_ssi_rx_config(struct fsl_ssi_private
*ssi_private
, bool enable
)
510 fsl_ssi_config(ssi_private
, enable
, &ssi_private
->rxtx_reg_val
.rx
);
513 static void fsl_ssi_tx_config(struct fsl_ssi_private
*ssi_private
, bool enable
)
515 fsl_ssi_config(ssi_private
, enable
, &ssi_private
->rxtx_reg_val
.tx
);
519 * Setup rx/tx register values used to enable/disable the streams. These will
520 * be used later in fsl_ssi_config to setup the streams without the need to
521 * check for all different SSI modes.
523 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private
*ssi_private
)
525 struct fsl_ssi_rxtx_reg_val
*reg
= &ssi_private
->rxtx_reg_val
;
527 reg
->rx
.sier
= CCSR_SSI_SIER_RFF0_EN
;
528 reg
->rx
.srcr
= CCSR_SSI_SRCR_RFEN0
;
530 reg
->tx
.sier
= CCSR_SSI_SIER_TFE0_EN
;
531 reg
->tx
.stcr
= CCSR_SSI_STCR_TFEN0
;
534 if (!fsl_ssi_is_ac97(ssi_private
)) {
535 reg
->rx
.scr
= CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
;
536 reg
->rx
.sier
|= CCSR_SSI_SIER_RFF0_EN
;
537 reg
->tx
.scr
= CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
;
538 reg
->tx
.sier
|= CCSR_SSI_SIER_TFE0_EN
;
541 if (ssi_private
->use_dma
) {
542 reg
->rx
.sier
|= CCSR_SSI_SIER_RDMAE
;
543 reg
->tx
.sier
|= CCSR_SSI_SIER_TDMAE
;
545 reg
->rx
.sier
|= CCSR_SSI_SIER_RIE
;
546 reg
->tx
.sier
|= CCSR_SSI_SIER_TIE
;
549 reg
->rx
.sier
|= FSLSSI_SIER_DBG_RX_FLAGS
;
550 reg
->tx
.sier
|= FSLSSI_SIER_DBG_TX_FLAGS
;
553 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
555 struct regmap
*regs
= ssi_private
->regs
;
558 * Setup the clock control register
560 regmap_write(regs
, CCSR_SSI_STCCR
,
561 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
562 regmap_write(regs
, CCSR_SSI_SRCCR
,
563 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
566 * Enable AC97 mode and startup the SSI
568 regmap_write(regs
, CCSR_SSI_SACNT
,
569 CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
);
570 regmap_write(regs
, CCSR_SSI_SACCDIS
, 0xff);
571 regmap_write(regs
, CCSR_SSI_SACCEN
, 0x300);
574 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
575 * codec before a stream is started.
577 regmap_update_bits(regs
, CCSR_SSI_SCR
,
578 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
,
579 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
581 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_WAIT(3));
585 * fsl_ssi_startup: create a new substream
587 * This is the first function called when a stream is opened.
589 * If this is the first stream open, then grab the IRQ and program most of
592 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
593 struct snd_soc_dai
*dai
)
595 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
596 struct fsl_ssi_private
*ssi_private
=
597 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
600 ret
= clk_prepare_enable(ssi_private
->clk
);
604 /* When using dual fifo mode, it is safer to ensure an even period
605 * size. If appearing to an odd number while DMA always starts its
606 * task from fifo0, fifo1 would be neglected at the end of each
607 * period. But SSI would still access fifo1 with an invalid data.
609 if (ssi_private
->use_dual_fifo
)
610 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
611 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
, 2);
617 * fsl_ssi_shutdown: shutdown the SSI
620 static void fsl_ssi_shutdown(struct snd_pcm_substream
*substream
,
621 struct snd_soc_dai
*dai
)
623 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
624 struct fsl_ssi_private
*ssi_private
=
625 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
627 clk_disable_unprepare(ssi_private
->clk
);
632 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
634 * Note: This function can be only called when using SSI as DAI master
636 * Quick instruction for parameters:
637 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
638 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
640 static int fsl_ssi_set_bclk(struct snd_pcm_substream
*substream
,
641 struct snd_soc_dai
*cpu_dai
,
642 struct snd_pcm_hw_params
*hw_params
)
644 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
645 struct regmap
*regs
= ssi_private
->regs
;
646 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
647 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
648 unsigned long clkrate
, baudrate
, tmprate
;
649 u64 sub
, savesub
= 100000;
651 bool baudclk_is_used
;
653 /* Prefer the explicitly set bitclock frequency */
654 if (ssi_private
->bitclk_freq
)
655 freq
= ssi_private
->bitclk_freq
;
657 freq
= params_channels(hw_params
) * 32 * params_rate(hw_params
);
659 /* Don't apply it to any non-baudclk circumstance */
660 if (IS_ERR(ssi_private
->baudclk
))
663 baudclk_is_used
= ssi_private
->baudclk_streams
& ~(BIT(substream
->stream
));
665 /* It should be already enough to divide clock by setting pm alone */
669 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
671 for (i
= 0; i
< 255; i
++) {
672 tmprate
= freq
* factor
* (i
+ 1);
675 clkrate
= clk_get_rate(ssi_private
->baudclk
);
677 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
680 * Hardware limitation: The bclk rate must be
681 * never greater than 1/5 IPG clock rate
683 if (clkrate
* 5 > clk_get_rate(ssi_private
->clk
))
687 afreq
= clkrate
/ (i
+ 1);
691 else if (freq
/ afreq
== 1)
693 else if (afreq
/ freq
== 1)
698 /* Calculate the fraction */
702 if (sub
< savesub
&& !(i
== 0 && psr
== 0 && div2
== 0)) {
713 /* No proper pm found if it is still remaining the initial value */
715 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
719 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
720 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
721 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
|
724 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
|| synchronous
)
725 regmap_update_bits(regs
, CCSR_SSI_STCCR
, mask
, stccr
);
727 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, mask
, stccr
);
729 if (!baudclk_is_used
) {
730 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
732 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
740 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
741 int clk_id
, unsigned int freq
, int dir
)
743 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
745 ssi_private
->bitclk_freq
= freq
;
751 * fsl_ssi_hw_params - program the sample size
753 * Most of the SSI registers have been programmed in the startup function,
754 * but the word length must be programmed here. Unfortunately, programming
755 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
756 * cause a problem with supporting simultaneous playback and capture. If
757 * the SSI is already playing a stream, then that stream may be temporarily
758 * stopped when you start capture.
760 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
763 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
764 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
766 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
767 struct regmap
*regs
= ssi_private
->regs
;
768 unsigned int channels
= params_channels(hw_params
);
769 unsigned int sample_size
=
770 snd_pcm_format_width(params_format(hw_params
));
771 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
776 regmap_read(regs
, CCSR_SSI_SCR
, &scr_val
);
777 enabled
= scr_val
& CCSR_SSI_SCR_SSIEN
;
780 * If we're in synchronous mode, and the SSI is already enabled,
781 * then STCCR is already set properly.
783 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
786 if (fsl_ssi_is_i2s_master(ssi_private
)) {
787 ret
= fsl_ssi_set_bclk(substream
, cpu_dai
, hw_params
);
791 /* Do not enable the clock if it is already enabled */
792 if (!(ssi_private
->baudclk_streams
& BIT(substream
->stream
))) {
793 ret
= clk_prepare_enable(ssi_private
->baudclk
);
797 ssi_private
->baudclk_streams
|= BIT(substream
->stream
);
801 if (!fsl_ssi_is_ac97(ssi_private
)) {
804 * Switch to normal net mode in order to have a frame sync
805 * signal every 32 bits instead of 16 bits
807 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private
) && sample_size
== 16)
808 i2smode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
|
811 i2smode
= ssi_private
->i2s_mode
;
813 regmap_update_bits(regs
, CCSR_SSI_SCR
,
814 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
815 channels
== 1 ? 0 : i2smode
);
819 * FIXME: The documentation says that SxCCR[WL] should not be
820 * modified while the SSI is enabled. The only time this can
821 * happen is if we're trying to do simultaneous playback and
822 * capture in asynchronous mode. Unfortunately, I have been enable
823 * to get that to work at all on the P1022DS. Therefore, we don't
824 * bother to disable/enable the SSI when setting SxCCR[WL], because
825 * the SSI will stop anyway. Maybe one day, this will get fixed.
828 /* In synchronous mode, the SSI uses STCCR for capture */
829 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
830 ssi_private
->cpu_dai_drv
.symmetric_rates
)
831 regmap_update_bits(regs
, CCSR_SSI_STCCR
, CCSR_SSI_SxCCR_WL_MASK
,
834 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, CCSR_SSI_SxCCR_WL_MASK
,
840 static int fsl_ssi_hw_free(struct snd_pcm_substream
*substream
,
841 struct snd_soc_dai
*cpu_dai
)
843 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
844 struct fsl_ssi_private
*ssi_private
=
845 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
847 if (fsl_ssi_is_i2s_master(ssi_private
) &&
848 ssi_private
->baudclk_streams
& BIT(substream
->stream
)) {
849 clk_disable_unprepare(ssi_private
->baudclk
);
850 ssi_private
->baudclk_streams
&= ~BIT(substream
->stream
);
856 static int _fsl_ssi_set_dai_fmt(struct device
*dev
,
857 struct fsl_ssi_private
*ssi_private
,
860 struct regmap
*regs
= ssi_private
->regs
;
861 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
864 ssi_private
->dai_fmt
= fmt
;
866 if (fsl_ssi_is_i2s_master(ssi_private
) && IS_ERR(ssi_private
->baudclk
)) {
867 dev_err(dev
, "baudclk is missing which is necessary for master mode\n");
871 fsl_ssi_setup_reg_vals(ssi_private
);
873 regmap_read(regs
, CCSR_SSI_SCR
, &scr
);
874 scr
&= ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
875 scr
|= CCSR_SSI_SCR_SYNC_TX_FS
;
877 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
878 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
880 regmap_read(regs
, CCSR_SSI_STCR
, &stcr
);
881 regmap_read(regs
, CCSR_SSI_SRCR
, &srcr
);
885 ssi_private
->i2s_mode
= CCSR_SSI_SCR_NET
;
886 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
887 case SND_SOC_DAIFMT_I2S
:
888 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
889 case SND_SOC_DAIFMT_CBM_CFS
:
890 case SND_SOC_DAIFMT_CBS_CFS
:
891 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_MASTER
;
892 regmap_update_bits(regs
, CCSR_SSI_STCCR
,
893 CCSR_SSI_SxCCR_DC_MASK
,
894 CCSR_SSI_SxCCR_DC(2));
895 regmap_update_bits(regs
, CCSR_SSI_SRCCR
,
896 CCSR_SSI_SxCCR_DC_MASK
,
897 CCSR_SSI_SxCCR_DC(2));
899 case SND_SOC_DAIFMT_CBM_CFM
:
900 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
906 /* Data on rising edge of bclk, frame low, 1clk before data */
907 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
908 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
910 case SND_SOC_DAIFMT_LEFT_J
:
911 /* Data on rising edge of bclk, frame high */
912 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
914 case SND_SOC_DAIFMT_DSP_A
:
915 /* Data on rising edge of bclk, frame high, 1clk before data */
916 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
917 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
919 case SND_SOC_DAIFMT_DSP_B
:
920 /* Data on rising edge of bclk, frame high */
921 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
922 CCSR_SSI_STCR_TXBIT0
;
924 case SND_SOC_DAIFMT_AC97
:
925 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_NORMAL
;
930 scr
|= ssi_private
->i2s_mode
;
932 /* DAI clock inversion */
933 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
934 case SND_SOC_DAIFMT_NB_NF
:
935 /* Nothing to do for both normal cases */
937 case SND_SOC_DAIFMT_IB_NF
:
938 /* Invert bit clock */
939 strcr
^= CCSR_SSI_STCR_TSCKP
;
941 case SND_SOC_DAIFMT_NB_IF
:
942 /* Invert frame clock */
943 strcr
^= CCSR_SSI_STCR_TFSI
;
945 case SND_SOC_DAIFMT_IB_IF
:
946 /* Invert both clocks */
947 strcr
^= CCSR_SSI_STCR_TSCKP
;
948 strcr
^= CCSR_SSI_STCR_TFSI
;
954 /* DAI clock master masks */
955 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
956 case SND_SOC_DAIFMT_CBS_CFS
:
957 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
958 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
960 case SND_SOC_DAIFMT_CBM_CFM
:
961 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
963 case SND_SOC_DAIFMT_CBM_CFS
:
964 strcr
&= ~CCSR_SSI_STCR_TXDIR
;
965 strcr
|= CCSR_SSI_STCR_TFDIR
;
966 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
969 if (!fsl_ssi_is_ac97(ssi_private
))
976 if (ssi_private
->cpu_dai_drv
.symmetric_rates
977 || fsl_ssi_is_ac97(ssi_private
)) {
978 /* Need to clear RXDIR when using SYNC or AC97 mode */
979 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
980 scr
|= CCSR_SSI_SCR_SYN
;
983 regmap_write(regs
, CCSR_SSI_STCR
, stcr
);
984 regmap_write(regs
, CCSR_SSI_SRCR
, srcr
);
985 regmap_write(regs
, CCSR_SSI_SCR
, scr
);
988 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
989 * use FIFO 1. We program the transmit water to signal a DMA transfer
990 * if there are only two (or fewer) elements left in the FIFO. Two
991 * elements equals one frame (left channel, right channel). This value,
992 * however, depends on the depth of the transmit buffer.
994 * We set the watermark on the same level as the DMA burstsize. For
995 * fiq it is probably better to use the biggest possible watermark
998 if (ssi_private
->use_dma
)
999 wm
= ssi_private
->fifo_depth
- 2;
1001 wm
= ssi_private
->fifo_depth
;
1003 regmap_write(regs
, CCSR_SSI_SFCSR
,
1004 CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
1005 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
));
1007 if (ssi_private
->use_dual_fifo
) {
1008 regmap_update_bits(regs
, CCSR_SSI_SRCR
, CCSR_SSI_SRCR_RFEN1
,
1009 CCSR_SSI_SRCR_RFEN1
);
1010 regmap_update_bits(regs
, CCSR_SSI_STCR
, CCSR_SSI_STCR_TFEN1
,
1011 CCSR_SSI_STCR_TFEN1
);
1012 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_TCH_EN
,
1013 CCSR_SSI_SCR_TCH_EN
);
1016 if (fmt
& SND_SOC_DAIFMT_AC97
)
1017 fsl_ssi_setup_ac97(ssi_private
);
1024 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1026 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
1028 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
1030 return _fsl_ssi_set_dai_fmt(cpu_dai
->dev
, ssi_private
, fmt
);
1034 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1036 * Note: This function can be only called when using SSI as DAI master
1038 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
1039 u32 rx_mask
, int slots
, int slot_width
)
1041 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
1042 struct regmap
*regs
= ssi_private
->regs
;
1045 /* The slot number should be >= 2 if using Network mode or I2S mode */
1046 regmap_read(regs
, CCSR_SSI_SCR
, &val
);
1047 val
&= CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
;
1048 if (val
&& slots
< 2) {
1049 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
1053 regmap_update_bits(regs
, CCSR_SSI_STCCR
, CCSR_SSI_SxCCR_DC_MASK
,
1054 CCSR_SSI_SxCCR_DC(slots
));
1055 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, CCSR_SSI_SxCCR_DC_MASK
,
1056 CCSR_SSI_SxCCR_DC(slots
));
1058 /* The register SxMSKs needs SSI to provide essential clock due to
1059 * hardware design. So we here temporarily enable SSI to set them.
1061 regmap_read(regs
, CCSR_SSI_SCR
, &val
);
1062 val
&= CCSR_SSI_SCR_SSIEN
;
1063 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_SSIEN
,
1064 CCSR_SSI_SCR_SSIEN
);
1066 regmap_write(regs
, CCSR_SSI_STMSK
, ~tx_mask
);
1067 regmap_write(regs
, CCSR_SSI_SRMSK
, ~rx_mask
);
1069 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_SSIEN
, val
);
1075 * fsl_ssi_trigger: start and stop the DMA transfer.
1077 * This function is called by ALSA to start, stop, pause, and resume the DMA
1080 * The DMA channel is in external master start and pause mode, which
1081 * means the SSI completely controls the flow of data.
1083 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1084 struct snd_soc_dai
*dai
)
1086 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1087 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
1088 struct regmap
*regs
= ssi_private
->regs
;
1091 case SNDRV_PCM_TRIGGER_START
:
1092 case SNDRV_PCM_TRIGGER_RESUME
:
1093 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1094 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1095 fsl_ssi_tx_config(ssi_private
, true);
1097 fsl_ssi_rx_config(ssi_private
, true);
1100 case SNDRV_PCM_TRIGGER_STOP
:
1101 case SNDRV_PCM_TRIGGER_SUSPEND
:
1102 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1103 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1104 fsl_ssi_tx_config(ssi_private
, false);
1106 fsl_ssi_rx_config(ssi_private
, false);
1113 if (fsl_ssi_is_ac97(ssi_private
)) {
1114 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1115 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_TX_CLR
);
1117 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_RX_CLR
);
1123 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
1125 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
1127 if (ssi_private
->soc
->imx
&& ssi_private
->use_dma
) {
1128 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
1129 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
1135 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
1136 .startup
= fsl_ssi_startup
,
1137 .shutdown
= fsl_ssi_shutdown
,
1138 .hw_params
= fsl_ssi_hw_params
,
1139 .hw_free
= fsl_ssi_hw_free
,
1140 .set_fmt
= fsl_ssi_set_dai_fmt
,
1141 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
1142 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
1143 .trigger
= fsl_ssi_trigger
,
1146 /* Template for the CPU dai driver structure */
1147 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
1148 .probe
= fsl_ssi_dai_probe
,
1150 .stream_name
= "CPU-Playback",
1153 .rates
= FSLSSI_I2S_RATES
,
1154 .formats
= FSLSSI_I2S_FORMATS
,
1157 .stream_name
= "CPU-Capture",
1160 .rates
= FSLSSI_I2S_RATES
,
1161 .formats
= FSLSSI_I2S_FORMATS
,
1163 .ops
= &fsl_ssi_dai_ops
,
1166 static const struct snd_soc_component_driver fsl_ssi_component
= {
1170 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
1171 .bus_control
= true,
1172 .probe
= fsl_ssi_dai_probe
,
1174 .stream_name
= "AC97 Playback",
1177 .rates
= SNDRV_PCM_RATE_8000_48000
,
1178 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1181 .stream_name
= "AC97 Capture",
1184 .rates
= SNDRV_PCM_RATE_48000
,
1185 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1187 .ops
= &fsl_ssi_dai_ops
,
1191 static struct fsl_ssi_private
*fsl_ac97_data
;
1193 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
1196 struct regmap
*regs
= fsl_ac97_data
->regs
;
1204 ret
= clk_prepare_enable(fsl_ac97_data
->clk
);
1206 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1212 regmap_write(regs
, CCSR_SSI_SACADD
, lreg
);
1215 regmap_write(regs
, CCSR_SSI_SACDAT
, lval
);
1217 regmap_update_bits(regs
, CCSR_SSI_SACNT
, CCSR_SSI_SACNT_RDWR_MASK
,
1221 clk_disable_unprepare(fsl_ac97_data
->clk
);
1224 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
1227 struct regmap
*regs
= fsl_ac97_data
->regs
;
1229 unsigned short val
= -1;
1234 ret
= clk_prepare_enable(fsl_ac97_data
->clk
);
1236 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1241 lreg
= (reg
& 0x7f) << 12;
1242 regmap_write(regs
, CCSR_SSI_SACADD
, lreg
);
1243 regmap_update_bits(regs
, CCSR_SSI_SACNT
, CCSR_SSI_SACNT_RDWR_MASK
,
1248 regmap_read(regs
, CCSR_SSI_SACDAT
, ®_val
);
1249 val
= (reg_val
>> 4) & 0xffff;
1251 clk_disable_unprepare(fsl_ac97_data
->clk
);
1256 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
1257 .read
= fsl_ssi_ac97_read
,
1258 .write
= fsl_ssi_ac97_write
,
1262 * Make every character in a string lower-case
1264 static void make_lowercase(char *s
)
1270 if ((c
>= 'A') && (c
<= 'Z'))
1271 *p
= c
+ ('a' - 'A');
1276 static int fsl_ssi_imx_probe(struct platform_device
*pdev
,
1277 struct fsl_ssi_private
*ssi_private
, void __iomem
*iomem
)
1279 struct device_node
*np
= pdev
->dev
.of_node
;
1283 if (ssi_private
->has_ipg_clk_name
)
1284 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
1286 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1287 if (IS_ERR(ssi_private
->clk
)) {
1288 ret
= PTR_ERR(ssi_private
->clk
);
1289 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1293 if (!ssi_private
->has_ipg_clk_name
) {
1294 ret
= clk_prepare_enable(ssi_private
->clk
);
1296 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n", ret
);
1301 /* For those SLAVE implementations, we ignore non-baudclk cases
1302 * and, instead, abandon MASTER mode that needs baud clock.
1304 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1305 if (IS_ERR(ssi_private
->baudclk
))
1306 dev_dbg(&pdev
->dev
, "could not get baud clock: %ld\n",
1307 PTR_ERR(ssi_private
->baudclk
));
1310 * We have burstsize be "fifo_depth - 2" to match the SSI
1311 * watermark setting in fsl_ssi_startup().
1313 ssi_private
->dma_params_tx
.maxburst
= ssi_private
->fifo_depth
- 2;
1314 ssi_private
->dma_params_rx
.maxburst
= ssi_private
->fifo_depth
- 2;
1315 ssi_private
->dma_params_tx
.addr
= ssi_private
->ssi_phys
+ CCSR_SSI_STX0
;
1316 ssi_private
->dma_params_rx
.addr
= ssi_private
->ssi_phys
+ CCSR_SSI_SRX0
;
1318 ret
= of_property_read_u32_array(np
, "dmas", dmas
, 4);
1319 if (ssi_private
->use_dma
&& !ret
&& dmas
[2] == IMX_DMATYPE_SSI_DUAL
) {
1320 ssi_private
->use_dual_fifo
= true;
1321 /* When using dual fifo mode, we need to keep watermark
1322 * as even numbers due to dma script limitation.
1324 ssi_private
->dma_params_tx
.maxburst
&= ~0x1;
1325 ssi_private
->dma_params_rx
.maxburst
&= ~0x1;
1328 if (!ssi_private
->use_dma
) {
1331 * Some boards use an incompatible codec. To get it
1332 * working, we are using imx-fiq-pcm-audio, that
1333 * can handle those codecs. DMA is not possible in this
1337 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1338 ssi_private
->fiq_params
.base
= iomem
;
1339 ssi_private
->fiq_params
.dma_params_rx
=
1340 &ssi_private
->dma_params_rx
;
1341 ssi_private
->fiq_params
.dma_params_tx
=
1342 &ssi_private
->dma_params_tx
;
1344 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1348 ret
= imx_pcm_dma_init(pdev
, IMX_SSI_DMABUF_SIZE
);
1357 if (!ssi_private
->has_ipg_clk_name
)
1358 clk_disable_unprepare(ssi_private
->clk
);
1362 static void fsl_ssi_imx_clean(struct platform_device
*pdev
,
1363 struct fsl_ssi_private
*ssi_private
)
1365 if (!ssi_private
->use_dma
)
1366 imx_pcm_fiq_exit(pdev
);
1367 if (!ssi_private
->has_ipg_clk_name
)
1368 clk_disable_unprepare(ssi_private
->clk
);
1371 static int fsl_ssi_probe(struct platform_device
*pdev
)
1373 struct fsl_ssi_private
*ssi_private
;
1375 struct device_node
*np
= pdev
->dev
.of_node
;
1376 const struct of_device_id
*of_id
;
1377 const char *p
, *sprop
;
1378 const uint32_t *iprop
;
1379 struct resource
*res
;
1380 void __iomem
*iomem
;
1383 of_id
= of_match_device(fsl_ssi_ids
, &pdev
->dev
);
1384 if (!of_id
|| !of_id
->data
)
1387 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
),
1390 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1394 ssi_private
->soc
= of_id
->data
;
1396 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1398 if (!strcmp(sprop
, "ac97-slave"))
1399 ssi_private
->dai_fmt
= SND_SOC_DAIFMT_AC97
;
1402 ssi_private
->use_dma
= !of_property_read_bool(np
,
1403 "fsl,fiq-stream-filter");
1405 if (fsl_ssi_is_ac97(ssi_private
)) {
1406 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1407 sizeof(fsl_ssi_ac97_dai
));
1409 fsl_ac97_data
= ssi_private
;
1411 ret
= snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1413 dev_err(&pdev
->dev
, "could not set AC'97 ops\n");
1417 /* Initialize this copy of the CPU DAI driver structure */
1418 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1419 sizeof(fsl_ssi_dai_template
));
1421 ssi_private
->cpu_dai_drv
.name
= dev_name(&pdev
->dev
);
1423 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1424 iomem
= devm_ioremap_resource(&pdev
->dev
, res
);
1426 return PTR_ERR(iomem
);
1427 ssi_private
->ssi_phys
= res
->start
;
1429 ret
= of_property_match_string(np
, "clock-names", "ipg");
1431 ssi_private
->has_ipg_clk_name
= false;
1432 ssi_private
->regs
= devm_regmap_init_mmio(&pdev
->dev
, iomem
,
1433 &fsl_ssi_regconfig
);
1435 ssi_private
->has_ipg_clk_name
= true;
1436 ssi_private
->regs
= devm_regmap_init_mmio_clk(&pdev
->dev
,
1437 "ipg", iomem
, &fsl_ssi_regconfig
);
1439 if (IS_ERR(ssi_private
->regs
)) {
1440 dev_err(&pdev
->dev
, "Failed to init register map\n");
1441 return PTR_ERR(ssi_private
->regs
);
1444 ssi_private
->irq
= platform_get_irq(pdev
, 0);
1445 if (ssi_private
->irq
< 0) {
1446 dev_err(&pdev
->dev
, "no irq for node %s\n", pdev
->name
);
1447 return ssi_private
->irq
;
1450 /* Are the RX and the TX clocks locked? */
1451 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1452 if (!fsl_ssi_is_ac97(ssi_private
))
1453 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1455 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1456 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1459 /* Determine the FIFO depth. */
1460 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1462 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1464 /* Older 8610 DTs didn't have the fifo-depth property */
1465 ssi_private
->fifo_depth
= 8;
1467 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1469 if (ssi_private
->soc
->imx
) {
1470 ret
= fsl_ssi_imx_probe(pdev
, ssi_private
, iomem
);
1475 ret
= devm_snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1476 &ssi_private
->cpu_dai_drv
, 1);
1478 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1479 goto error_asoc_register
;
1482 if (ssi_private
->use_dma
) {
1483 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1484 fsl_ssi_isr
, 0, dev_name(&pdev
->dev
),
1487 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1489 goto error_asoc_register
;
1493 ret
= fsl_ssi_debugfs_create(&ssi_private
->dbg_stats
, &pdev
->dev
);
1495 goto error_asoc_register
;
1498 * If codec-handle property is missing from SSI node, we assume
1499 * that the machine driver uses new binding which does not require
1500 * SSI driver to trigger machine driver's probe.
1502 if (!of_get_property(np
, "codec-handle", NULL
))
1505 /* Trigger the machine driver's probe function. The platform driver
1506 * name of the machine driver is taken from /compatible property of the
1507 * device tree. We also pass the address of the CPU DAI driver
1510 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1511 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1512 p
= strrchr(sprop
, ',');
1515 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1516 make_lowercase(name
);
1519 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1520 if (IS_ERR(ssi_private
->pdev
)) {
1521 ret
= PTR_ERR(ssi_private
->pdev
);
1522 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1523 goto error_sound_card
;
1527 if (ssi_private
->dai_fmt
)
1528 _fsl_ssi_set_dai_fmt(&pdev
->dev
, ssi_private
,
1529 ssi_private
->dai_fmt
);
1531 if (fsl_ssi_is_ac97(ssi_private
)) {
1534 ret
= of_property_read_u32(np
, "cell-index", &ssi_idx
);
1536 dev_err(&pdev
->dev
, "cannot get SSI index property\n");
1537 goto error_sound_card
;
1541 platform_device_register_data(NULL
,
1542 "ac97-codec", ssi_idx
, NULL
, 0);
1543 if (IS_ERR(ssi_private
->pdev
)) {
1544 ret
= PTR_ERR(ssi_private
->pdev
);
1546 "failed to register AC97 codec platform: %d\n",
1548 goto error_sound_card
;
1555 fsl_ssi_debugfs_remove(&ssi_private
->dbg_stats
);
1557 error_asoc_register
:
1558 if (ssi_private
->soc
->imx
)
1559 fsl_ssi_imx_clean(pdev
, ssi_private
);
1564 static int fsl_ssi_remove(struct platform_device
*pdev
)
1566 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1568 fsl_ssi_debugfs_remove(&ssi_private
->dbg_stats
);
1570 if (ssi_private
->pdev
)
1571 platform_device_unregister(ssi_private
->pdev
);
1573 if (ssi_private
->soc
->imx
)
1574 fsl_ssi_imx_clean(pdev
, ssi_private
);
1576 if (fsl_ssi_is_ac97(ssi_private
))
1577 snd_soc_set_ac97_ops(NULL
);
1582 #ifdef CONFIG_PM_SLEEP
1583 static int fsl_ssi_suspend(struct device
*dev
)
1585 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(dev
);
1586 struct regmap
*regs
= ssi_private
->regs
;
1588 regmap_read(regs
, CCSR_SSI_SFCSR
,
1589 &ssi_private
->regcache_sfcsr
);
1591 regcache_cache_only(regs
, true);
1592 regcache_mark_dirty(regs
);
1597 static int fsl_ssi_resume(struct device
*dev
)
1599 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(dev
);
1600 struct regmap
*regs
= ssi_private
->regs
;
1602 regcache_cache_only(regs
, false);
1604 regmap_update_bits(regs
, CCSR_SSI_SFCSR
,
1605 CCSR_SSI_SFCSR_RFWM1_MASK
| CCSR_SSI_SFCSR_TFWM1_MASK
|
1606 CCSR_SSI_SFCSR_RFWM0_MASK
| CCSR_SSI_SFCSR_TFWM0_MASK
,
1607 ssi_private
->regcache_sfcsr
);
1609 return regcache_sync(regs
);
1611 #endif /* CONFIG_PM_SLEEP */
1613 static const struct dev_pm_ops fsl_ssi_pm
= {
1614 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend
, fsl_ssi_resume
)
1617 static struct platform_driver fsl_ssi_driver
= {
1619 .name
= "fsl-ssi-dai",
1620 .of_match_table
= fsl_ssi_ids
,
1623 .probe
= fsl_ssi_probe
,
1624 .remove
= fsl_ssi_remove
,
1627 module_platform_driver(fsl_ssi_driver
);
1629 MODULE_ALIAS("platform:fsl-ssi-dai");
1630 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1631 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1632 MODULE_LICENSE("GPL v2");